mirror of
https://github.com/asmjit/asmjit.git
synced 2025-12-18 04:54:36 +03:00
[ABI] Completely reworked instruction DB and generators
* Instruction database is now part of asmjit to keep it in sync * X86/X64 ISA data has been reworked, now in a proper JSON format * ARM32 ISA data has been added (currently only DB, support later) * ARM64 ISA data has been added * ARM features detection has been updated
This commit is contained in:
kobalicek
@@ -3,23 +3,15 @@
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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// ============================================================================
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// tablegen-x86.js
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//
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// The purpose of this script is to fetch all instructions' names into a single
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// string and to optimize common patterns that appear in instruction data. It
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// prevents relocation of small strings (instruction names) that has to be done
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// by a linker to make all pointers the binary application/library uses valid.
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// This approach decreases the final size of AsmJit binary and relocation data.
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//
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// NOTE: This script relies on 'asmdb' package. Either install it by using
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// node.js package manager (npm) or by copying/symlinking the whole asmdb
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// directory as [asmjit]/tools/asmdb.
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// ============================================================================
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"use strict";
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const fs = require("fs");
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const path = require("path");
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const cxx = require("./gencxx.js");
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const commons = require("./gencommons.js");
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const core = require("./tablegen.js");
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const asmdb = core.asmdb;
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const kIndent = core.kIndent;
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@@ -33,56 +25,28 @@ const IndexedArray = core.IndexedArray;
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const hasOwn = Object.prototype.hasOwnProperty;
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const disclaimer = StringUtils.disclaimer;
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const FAIL = core.FAIL;
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const DEBUG = core.DEBUG;
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const DEBUG = commons.DEBUG;
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const FATAL = commons.FATAL;
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const decToHex = StringUtils.decToHex;
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function readJSON(fileName) {
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const content = fs.readFileSync(fileName);
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return JSON.parse(content);
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}
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const x86data = readJSON(path.join(__dirname, "..", "db", asmdb.x86.dbName));
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// TODO: Fix these regressions:
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// cvtsi2ss
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// enqcmd
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// ============================================================================
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// [tablegen.x86.x86isa]
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// ============================================================================
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// Create the X86 database and add some special cases recognized by AsmJit.
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const x86isa = new asmdb.x86.ISA({
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instructions: [
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// Imul in [reg, imm] form is encoded as [reg, reg, imm].
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["imul", "r16, ib" , "RMI" , "66 6B /r ib" , "ANY OF=W SF=W ZF=U AF=U PF=U CF=W"],
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["imul", "r32, ib" , "RMI" , "6B /r ib" , "ANY OF=W SF=W ZF=U AF=U PF=U CF=W"],
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["imul", "r64, ib" , "RMI" , "REX.W 6B /r ib", "X64 OF=W SF=W ZF=U AF=U PF=U CF=W"],
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["imul", "r16, iw/uw" , "RMI" , "66 69 /r iw" , "ANY OF=W SF=W ZF=U AF=U PF=U CF=W"],
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["imul", "r32, id/ud" , "RMI" , "69 /r id" , "ANY OF=W SF=W ZF=U AF=U PF=U CF=W"],
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["imul", "r64, id" , "RMI" , "REX.W 69 /r id", "X64 OF=W SF=W ZF=U AF=U PF=U CF=W"],
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// Movabs (X64 only).
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["movabs", "W:r64, iq/uq" , "I" , "REX.W B8+r iq", "X64"],
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["movabs", "w:al, moff8" , "NONE", "A0" , "X64"],
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["movabs", "w:ax, moff16" , "NONE", "66 A1" , "X64"],
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["movabs", "W:eax, moff32", "NONE", "A1" , "X64"],
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["movabs", "W:rax, moff64", "NONE", "REX.W A1" , "X64"],
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["movabs", "W:moff8, al" , "NONE", "A2" , "X64"],
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["movabs", "W:moff16, ax" , "NONE", "66 A3" , "X64"],
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["movabs", "W:moff32, eax", "NONE", "A3" , "X64"],
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["movabs", "W:moff64, rax", "NONE", "REX.W A3" , "X64"]
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]
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});
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// Remapped instructions contain mapping between instructions that AsmJit expects
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// and instructions provided by asmdb. In general, AsmJit uses string instructions
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// (like cmps, movs, etc...) without the suffix, so we just remap these and keep
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// all others.
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const RemappedInsts = {
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__proto__: null,
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"cmpsd": { names: ["cmpsd"] , rep: false },
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"movsd": { names: ["movsd"] , rep: false },
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"cmps" : { names: ["cmpsb", "cmpsw", "cmpsd", "cmpsq"], rep: true },
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"movs" : { names: ["movsb", "movsw", "movsd", "movsq"], rep: true },
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"lods" : { names: ["lodsb", "lodsw", "lodsd", "lodsq"], rep: null },
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"scas" : { names: ["scasb", "scasw", "scasd", "scasq"], rep: null },
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"stos" : { names: ["stosb", "stosw", "stosd", "stosq"], rep: null },
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"ins" : { names: ["insb" , "insw" , "insd" ] , rep: null },
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"outs" : { names: ["outsb", "outsw", "outsd"] , rep: null }
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};
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const x86isa = new asmdb.x86.ISA(x86data);
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// ============================================================================
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// [tablegen.x86.Filter]
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@@ -95,7 +59,7 @@ class Filter {
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for (var i = 0; i < instArray.length; i++) {
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const inst = instArray[i];
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if (inst.attributes.AltForm)
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if (inst.altForm)
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continue;
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const s = inst.operands.map((op) => { return op.isImm() ? "imm" : op.toString(); }).join(", ");
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@@ -113,7 +77,7 @@ class Filter {
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const result = [];
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for (var i = 0; i < instArray.length; i++) {
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const inst = instArray[i];
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if (inst.attributes.AltForm)
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if (inst.altForm)
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continue;
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result.push(inst);
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}
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@@ -167,7 +131,28 @@ class GenUtils {
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}
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static cpuFeaturesOf(dbInsts) {
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return ArrayUtils.sorted(dbInsts.unionCpuFeatures());
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function cmp(a, b) {
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if (a.startsWith("AVX512") && !b.startsWith("AVX512"))
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return 1;
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if (b.startsWith("AVX512") && !a.startsWith("AVX512"))
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return -1;
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if (a.startsWith("AVX") && !b.startsWith("AVX"))
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return 1;
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if (b.startsWith("AVX") && !a.startsWith("AVX"))
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return -1;
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if (a === "FPU" && b !== "FPU")
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return 1;
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if (b === "FPU" && a !== "FPU")
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return -1;
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return a < b ? -1 : a === b ? 0 : 1;
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}
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const features = Object.getOwnPropertyNames(dbInsts.unionCpuFeatures());
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features.sort(cmp);
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return features;
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}
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static assignVexEvexCompatibilityFlags(f, dbInsts) {
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@@ -261,16 +246,16 @@ class GenUtils {
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const dbInst = dbInsts[i];
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const operands = dbInst.operands;
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if (dbInst.attributes.Lock ) f.Lock = true;
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if (dbInst.attributes.XAcquire ) f.XAcquire = true;
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if (dbInst.attributes.XRelease ) f.XRelease = true;
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if (dbInst.attributes.BND ) f.Rep = true;
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if (dbInst.attributes.REP ) f.Rep = true;
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if (dbInst.attributes.REPNE ) f.Rep = true;
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if (dbInst.attributes.RepIgnored ) f.RepIgnored = true;
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if (dbInst.attributes.ImplicitZeroing) f.Avx512ImplicitZ = true;
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if (dbInst.prefixes.lock ) f.Lock = true;
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if (dbInst.prefixes.xacquire ) f.XAcquire = true;
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if (dbInst.prefixes.xrelease ) f.XRelease = true;
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if (dbInst.prefixes.bnd ) f.Rep = true;
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if (dbInst.prefixes.rep ) f.Rep = true;
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if (dbInst.prefixes.repne ) f.Rep = true;
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if (dbInst.prefixes.repIgnore ) f.RepIgnored = true;
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if (dbInst.k === "zeroing" ) f.Avx512ImplicitZ = true;
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if (dbInst.fpu) {
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if (dbInst.category.FPU) {
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for (var j = 0; j < operands.length; j++) {
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const op = operands[j];
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if (op.memSize === 16) f.FpuM16 = true;
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@@ -280,7 +265,7 @@ class GenUtils {
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}
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}
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if (dbInst.attributes.Tsib)
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if (dbInst.tsib)
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f.Tsib = true;
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if (dbInst.vsibReg)
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@@ -289,12 +274,11 @@ class GenUtils {
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if (dbInst.prefix === "VEX" || dbInst.prefix === "XOP")
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f.Vex = true;
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if (dbInst.encodingPreference === "EVEX")
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f.PreferEvex = true;
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if (dbInst.prefix === "EVEX") {
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f.Evex = true;
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if (dbInst.extensions["AVX512_VNNI"])
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f.PreferEvex = true;
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if (dbInst.kmask) f.Avx512K = true;
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if (dbInst.zmask) f.Avx512Z = true;
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@@ -418,7 +402,7 @@ class GenUtils {
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}
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}
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static fixedRegOf(reg) {
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static fixedRegOfRegName(reg) {
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switch (reg) {
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case "es" : return 1;
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case "cs" : return 2;
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@@ -447,11 +431,23 @@ class GenUtils {
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}
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}
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static fixedRegOf(op) {
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if (op.isReg()) {
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return GenUtils.fixedRegOfRegName(op.reg);
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}
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else if (op.isMem() && op.memRegOnly) {
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return GenUtils.fixedRegOfRegName(op.memRegOnly);
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}
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else {
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return -1;
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}
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}
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static controlFlow(dbInsts) {
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if (dbInsts.checkAttribute("Control", "Jump")) return "Jump";
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if (dbInsts.checkAttribute("Control", "Call")) return "Call";
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if (dbInsts.checkAttribute("Control", "Branch")) return "Branch";
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if (dbInsts.checkAttribute("Control", "Return")) return "Return";
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if (dbInsts.checkAttribute("control", "jump")) return "Jump";
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if (dbInsts.checkAttribute("control", "call")) return "Call";
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if (dbInsts.checkAttribute("control", "branch")) return "Branch";
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if (dbInsts.checkAttribute("control", "return")) return "Return";
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return "Regular";
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}
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}
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@@ -473,16 +469,7 @@ class X86TableGen extends core.TableGen {
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// Get instructions (dbInsts) having the same name as understood by AsmJit.
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query(name) {
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const remapped = RemappedInsts[name];
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if (!remapped) return x86isa.query(name);
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const dbInsts = x86isa.query(remapped.names);
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const rep = remapped.rep;
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if (rep === null) return dbInsts;
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return dbInsts.filter((inst) => {
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return rep === !!(inst.attributes.REP || inst.attributes.REPNE);
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});
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return x86isa.query(name);
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}
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// --------------------------------------------------------------------------
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@@ -514,7 +501,7 @@ class X86TableGen extends core.TableGen {
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const dbInsts = this.query(name);
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if (name && !dbInsts.length)
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FAIL(`Instruction '${name}' not found in asmdb`);
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FATAL(`Instruction '${name}' not found in asmdb`);
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const flags = GenUtils.flagsOf(dbInsts);
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const controlFlow = GenUtils.controlFlow(dbInsts);
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@@ -547,7 +534,7 @@ class X86TableGen extends core.TableGen {
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}
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if (this.insts.length === 0)
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FAIL("X86TableGen.parse(): Invalid parsing regexp (no data parsed)");
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FATAL("X86TableGen.parse(): Invalid parsing regexp (no data parsed)");
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console.log("Number of Instructions: " + this.insts.length);
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}
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@@ -830,7 +817,7 @@ class IdEnum extends core.IdEnum {
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var text = "";
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var features = GenUtils.cpuFeaturesOf(dbInsts);
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const priorityFeatures = ["AVX_VNNI"];
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const priorityFeatures = ["AVX_VNNI", "AVX_VNNI_INT8", "AVX_IFMA", "AVX_NE_CONVERT"];
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if (features.length) {
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text += "{";
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@@ -968,7 +955,7 @@ class AltOpcodeTable extends core.Task {
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components[2] = "00";
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}
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else {
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FAIL(`Failed to process opcode '${opcode}'`);
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FATAL(`Failed to process opcode '${opcode}'`);
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}
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const newOpcode = joinOpcodeComponents(components);
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@@ -1035,7 +1022,7 @@ function StringifyOpArray(a, map) {
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else if (hasOwn.call(map, op))
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mapped = map[op];
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else
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FAIL(`UNHANDLED OPERAND '${op}'`);
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FATAL(`UNHANDLED OPERAND '${op}'`);
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s += (s ? " | " : "") + mapped;
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}
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return s ? s : "0";
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@@ -1252,14 +1239,14 @@ class ISignature extends Array {
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mergeWith(other) {
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// If both architectures are the same, it's fine to merge.
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var ok = this.x86 === other.x86 && this.x64 === other.x64;
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const sameArch = this.x86 === other.x86 && this.x64 === other.x64;
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// If the first arch is [X86|X64] and the second [X64] it's also fine.
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if (!ok && this.x86 && this.x64 && !other.x86 && other.x64)
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ok = true;
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// if (!ok && this.x86 && this.x64 && !other.x86 && other.x64)
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// ok = true;
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// It's not ok if both signatures have different number of implicit operands.
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if (!ok || this.implicit !== other.implicit)
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if (!sameArch || this.implicit !== other.implicit)
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return false;
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// It's not ok if both signatures have different number of operands.
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@@ -1267,8 +1254,8 @@ class ISignature extends Array {
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if (len !== other.length)
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return false;
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var xorIndex = -1;
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for (var i = 0; i < len; i++) {
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let xorIndex = -1;
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for (let i = 0; i < len; i++) {
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const xor = this[i].xor(other[i]);
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if (xor === null) continue;
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@@ -1279,12 +1266,9 @@ class ISignature extends Array {
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}
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// Bail if mergeWidth at operand-level failed.
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if (xorIndex !== -1 && !this[xorIndex].mergeWith(other[xorIndex]))
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if (xorIndex === -1 || !this[xorIndex].mergeWith(other[xorIndex]))
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return false;
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this.x86 = this.x86 || other.x86;
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this.x64 = this.x64 || other.x64;
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return true;
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}
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@@ -1295,7 +1279,7 @@ class ISignature extends Array {
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class SignatureArray extends Array {
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// Iterate over all signatures and check which operands don't need explicit memory size.
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calcImplicitMemSize() {
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calcImplicitMemSize(instName) {
|
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// Calculates a hash-value (aka key) of all register operands specified by `regOps` in `inst`.
|
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function keyOf(inst, regOps) {
|
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var s = "";
|
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@@ -1410,6 +1394,8 @@ class SignatureArray extends Array {
|
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// then keep this implicit as it won't do any harm. These instructions
|
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// cannot be mixed and it will make implicit the 32-bit one in cases
|
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// where X64 introduced 64-bit ones like `cvtsi2ss`.
|
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if (!/^(bndcl|bndcn|bndcu|ptwrite|(v)?cvtsi2ss|(v)?cvtsi2sd|vcvtusi2ss|vcvtusi2sd)$/.test(instName))
|
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implicit = false;
|
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}
|
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else {
|
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implicit = false;
|
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@@ -1422,8 +1408,9 @@ class SignatureArray extends Array {
|
||||
// Patch all instructions to accept implicit-size memory operand.
|
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for (bIndex = 0; bIndex < sameSizeSet.length; bIndex++) {
|
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const bInst = sameSizeSet[bIndex];
|
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if (implicit)
|
||||
if (implicit) {
|
||||
bInst[memPos].flags.mem = true;
|
||||
}
|
||||
|
||||
if (!implicit)
|
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DEBUG(`${this.name}: Explicit: ${bInst}`);
|
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@@ -1592,7 +1579,9 @@ class InstSignatureTable extends core.Task {
|
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}
|
||||
|
||||
makeSignatures(dbInsts) {
|
||||
const instName = dbInsts.length ? dbInsts[0].name : "";
|
||||
const signatures = new SignatureArray();
|
||||
|
||||
for (var i = 0; i < dbInsts.length; i++) {
|
||||
const inst = dbInsts[i];
|
||||
const ops = inst.operands;
|
||||
@@ -1676,29 +1665,9 @@ class InstSignatureTable extends core.Task {
|
||||
op.flags.implicit = true;
|
||||
}
|
||||
|
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const seg = iop.memSeg;
|
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const seg = iop.memSegment;
|
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if (seg) {
|
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switch (inst.name) {
|
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case "cmpsb": op.flags.m8 = true; break;
|
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case "cmpsw": op.flags.m16 = true; break;
|
||||
case "cmpsd": op.flags.m32 = true; break;
|
||||
case "cmpsq": op.flags.m64 = true; break;
|
||||
case "lodsb": op.flags.m8 = true; break;
|
||||
case "lodsw": op.flags.m16 = true; break;
|
||||
case "lodsd": op.flags.m32 = true; break;
|
||||
case "lodsq": op.flags.m64 = true; break;
|
||||
case "movsb": op.flags.m8 = true; break;
|
||||
case "movsw": op.flags.m16 = true; break;
|
||||
case "movsd": op.flags.m32 = true; break;
|
||||
case "movsq": op.flags.m64 = true; break;
|
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case "scasb": op.flags.m8 = true; break;
|
||||
case "scasw": op.flags.m16 = true; break;
|
||||
case "scasd": op.flags.m32 = true; break;
|
||||
case "scasq": op.flags.m64 = true; break;
|
||||
case "stosb": op.flags.m8 = true; break;
|
||||
case "stosw": op.flags.m16 = true; break;
|
||||
case "stosd": op.flags.m32 = true; break;
|
||||
case "stosq": op.flags.m64 = true; break;
|
||||
case "insb": op.flags.m8 = true; break;
|
||||
case "insw": op.flags.m16 = true; break;
|
||||
case "insd": op.flags.m32 = true; break;
|
||||
@@ -1718,6 +1687,9 @@ class InstSignatureTable extends core.Task {
|
||||
default: console.log(`UNKNOWN MEM IN INSTRUCTION '${inst.name}'`); break;
|
||||
}
|
||||
|
||||
if (iop.memRegOnly)
|
||||
reg = iop.memRegOnly;
|
||||
|
||||
if (seg === "ds") op.flags.memDS = true;
|
||||
if (seg === "es") op.flags.memES = true;
|
||||
if (reg === "reg") { op.flags.memBase = true; }
|
||||
@@ -1730,30 +1702,37 @@ class InstSignatureTable extends core.Task {
|
||||
else if (reg) {
|
||||
if (reg == "r8") {
|
||||
op.flags["r8lo"] = true;
|
||||
op.flags["r8hi"] = true;
|
||||
|
||||
if (!inst.w || inst.w === "W0")
|
||||
op.flags["r8hi"] = true;
|
||||
}
|
||||
else {
|
||||
op.flags[reg] = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (mem) {
|
||||
op.flags[mem] = true;
|
||||
// HACK: Allow LEA|CL*|PREFETCH* to use any memory size.
|
||||
if (/^(cldemote|clwb|clflush\w*|lea|prefetch\w*)$/.test(inst.name)) {
|
||||
// HACK: Allow LEA to use any memory size.
|
||||
if (/^(lea)$/.test(inst.name)) {
|
||||
op.flags.mem = true;
|
||||
Object.assign(op.flags, MemOp);
|
||||
}
|
||||
|
||||
// HACK: These instructions specify explicit memory size, but it's just informational.
|
||||
if (inst.name === "enqcmd" || inst.name === "enqcmds" || inst.name === "movdir64b")
|
||||
if (/^(call|enqcmd|enqcmds|lcall|ljmp|movdir64b)$/.test(inst.name)) {
|
||||
op.flags.mem = true;
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
if (imm) {
|
||||
if (iop.immSign === "any" || iop.immSign === "signed" ) op.flags["i" + imm] = true;
|
||||
if (iop.immSign === "any" || iop.immSign === "unsigned") op.flags["u" + imm] = true;
|
||||
}
|
||||
if (rel) op.flags["rel" + rel] = true;
|
||||
|
||||
if (rel) {
|
||||
op.flags["rel" + rel] = true;
|
||||
}
|
||||
|
||||
row.push(op);
|
||||
}
|
||||
@@ -1764,8 +1743,8 @@ class InstSignatureTable extends core.Task {
|
||||
}
|
||||
}
|
||||
|
||||
if (signatures.length && GenUtils.canUseImplicitMemSize(dbInsts[0].name))
|
||||
signatures.calcImplicitMemSize();
|
||||
if (signatures.length && GenUtils.canUseImplicitMemSize(instName))
|
||||
signatures.calcImplicitMemSize(instName);
|
||||
|
||||
signatures.compact();
|
||||
return signatures;
|
||||
@@ -1868,7 +1847,7 @@ class AdditionalInfoTable extends core.Task {
|
||||
if (dbInst.name === "mov")
|
||||
continue;
|
||||
|
||||
const specialRegs = dbInst.specialRegs;
|
||||
const regs = dbInst.io;
|
||||
|
||||
// Mov is a special case, moving to/from control regs makes flags undefined,
|
||||
// which we don't want to have in `X86InstDB::operationData`. This is, thus,
|
||||
@@ -1876,28 +1855,28 @@ class AdditionalInfoTable extends core.Task {
|
||||
if (dbInst.name === "mov")
|
||||
continue;
|
||||
|
||||
for (var specialReg in specialRegs) {
|
||||
for (var reg in regs) {
|
||||
var flag = "";
|
||||
switch (specialReg) {
|
||||
case "FLAGS.CF": flag = "CF"; break;
|
||||
case "FLAGS.OF": flag = "OF"; break;
|
||||
case "FLAGS.SF": flag = "SF"; break;
|
||||
case "FLAGS.ZF": flag = "ZF"; break;
|
||||
case "FLAGS.AF": flag = "AF"; break;
|
||||
case "FLAGS.PF": flag = "PF"; break;
|
||||
case "FLAGS.DF": flag = "DF"; break;
|
||||
case "FLAGS.IF": flag = "IF"; break;
|
||||
//case "FLAGS.TF": flag = "TF"; break;
|
||||
case "FLAGS.AC": flag = "AC"; break;
|
||||
case "X86SW.C0": flag = "C0"; break;
|
||||
case "X86SW.C1": flag = "C1"; break;
|
||||
case "X86SW.C2": flag = "C2"; break;
|
||||
case "X86SW.C3": flag = "C3"; break;
|
||||
switch (reg) {
|
||||
case "CF": flag = "CF"; break;
|
||||
case "OF": flag = "OF"; break;
|
||||
case "SF": flag = "SF"; break;
|
||||
case "ZF": flag = "ZF"; break;
|
||||
case "AF": flag = "AF"; break;
|
||||
case "PF": flag = "PF"; break;
|
||||
case "DF": flag = "DF"; break;
|
||||
case "IF": flag = "IF"; break;
|
||||
//case "TF": flag = "TF"; break;
|
||||
case "AC": flag = "AC"; break;
|
||||
case "C0": flag = "C0"; break;
|
||||
case "C1": flag = "C1"; break;
|
||||
case "C2": flag = "C2"; break;
|
||||
case "C3": flag = "C3"; break;
|
||||
default:
|
||||
continue;
|
||||
}
|
||||
|
||||
switch (specialRegs[specialReg]) {
|
||||
switch (regs[reg]) {
|
||||
case "R":
|
||||
r[flag] = true;
|
||||
break;
|
||||
@@ -2132,7 +2111,7 @@ class InstRWInfoTable extends core.Task {
|
||||
for (var j = start; j <= end; j++) {
|
||||
const bytePos = j >> 3;
|
||||
if (bytePos < 0 || bytePos >= arr.length)
|
||||
FAIL(`Range ${start}:${end} cannot be used to create a byte-mask`);
|
||||
FATAL(`Range ${start}:${end} cannot be used to create a byte-mask`);
|
||||
arr[bytePos] = 1;
|
||||
}
|
||||
}
|
||||
@@ -2163,7 +2142,7 @@ class InstRWInfoTable extends core.Task {
|
||||
access: op.read && op.write ? "X" : op.read ? "R" : op.write ? "W" : "?",
|
||||
clc: 0,
|
||||
flags: {},
|
||||
fixed: GenUtils.fixedRegOf(op.reg),
|
||||
fixed: GenUtils.fixedRegOf(op),
|
||||
index: op.rwxIndex,
|
||||
width: op.rwxWidth
|
||||
};
|
||||
@@ -2197,10 +2176,7 @@ class InstRWInfoTable extends core.Task {
|
||||
// NOTE: Avoid push/pop here as PUSH/POP has many variations for segment registers,
|
||||
// which would set 'd.fixed' field even for GP variation of the instuction.
|
||||
if (instName !== "push" && instName !== "pop") {
|
||||
if (op.isReg())
|
||||
d.fixed = GenUtils.fixedRegOf(op.reg);
|
||||
else
|
||||
d.fixed = GenUtils.fixedRegOf(op.mem);
|
||||
d.fixed = GenUtils.fixedRegOf(op);
|
||||
}
|
||||
|
||||
switch (instName) {
|
||||
@@ -2232,7 +2208,7 @@ class InstRWInfoTable extends core.Task {
|
||||
}
|
||||
|
||||
if (d.fixed !== -1) {
|
||||
if (op.memSeg)
|
||||
if (op.memSegment)
|
||||
d.flags.MemPhysId = true;
|
||||
else
|
||||
d.flags.RegPhysId = true;
|
||||
@@ -2320,7 +2296,7 @@ class InstRWInfoTable extends core.Task {
|
||||
if (queryRwByData(dbInsts, this.rwCategoryByData[k]))
|
||||
return { category: k, rwOps: nullOps() };
|
||||
|
||||
// FAILURE: Missing data to categorize this instruction.
|
||||
// FATALURE: Missing data to categorize this instruction.
|
||||
if (name) {
|
||||
const items = dumpRwToData(dbInsts)
|
||||
console.log(`RW: ${dbInsts.length ? dbInsts[0].name : ""}:`);
|
||||
@@ -2410,7 +2386,7 @@ class InstRWInfoTable extends core.Task {
|
||||
if (/^(punpcklbw|punpckldq|punpcklwd)$/.test(dbInst.name))
|
||||
return "None";
|
||||
|
||||
return StringUtils.capitalize(dbInst.name);
|
||||
return cxx.Utils.capitalize(dbInst.name);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user