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[abi] Reorganized instruction DB, removed deprecated instructions

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* Removed AVX512_ER, AVX512_PF, AVX512_4FMAPS, and AVX512_4VNNIW
    extensions and corresponding instructions (these were never
    advertised by any x86 CPU and were only used by Xeon Phi acc.,
    which AsmJit never supported)
  * Removed CPU extensions HLE, MPX, and TSX
  * Kept extension RTM, which is only for backward compatibility to
    recognize instructions, but it's no longer checked by CpuInfo as
    it's been deprecated together with HLE and MPX
  * The xtest instruction now reports it requires RTM
  * Reorganized x86 extensions a bit - they are now reordered to group
    them by category, preparing for the future where extension IDs will
    be always added after existing records for ABI compatibility
  * Instruction vcvtneps2bf16 no longer accepts form without an explicit
    memory operand size
  * Removed aliased instructions in CMOVcc, Jcc, And SETcc categories,
    now there is only a single instruction id for all aliased instructions.
  * Added a new feature to always show instruction aliases in Logger, which
    includes formatting instructio nodes (Builder, Compiler)

Instruction DB-only updates (not applied to C++ yet):

  * AsmJit DB from now uses the same license as AsmJit (Zlib) and
    no longer applies dual licensing (Zlib and Public Domain)
  * Added support for aggregated instruction definitions in
    x86 instruction database, which should simplify the maintenance
    and reduce bugs (also the syntax is comparable to descriptions
    used by Intel APX instruction manuals)
  * Added support for APX instructions and new features
  * Added support for AVX10.1 and AVX10.2 instructions (both new
    instructions and new encodings of existing instructions)
  * Added support for MOVRS instructions
  * Added support for KL instructions (loadiwkey)
  * Added support for AESKLE instructions
  * Added support for AESKLEWIDE_KL instructions
  * Added support for AMX_[AVX512|MOVRS|FP8|TF32|TRANSPOSE]
  * NOTE: None of the instruction additions is currently used by
    Asmjit, it's a pure database update that needs more work to
    make all the instructions available in future AsmJit
This commit is contained in:
kobalicek
2025-05-10 15:03:54 +02:00
parent 9eb6edbf71
commit 6c9a6b2454
52 changed files with 10539 additions and 10602 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
.github/workflows/build-config.json vendored
View File

@@ -17,7 +17,7 @@
{ "optional": true, "cmd": ["asmjit_test_assembler", "--validate"] },
{ "optional": true, "cmd": ["asmjit_test_emitters"] },
{ "optional": true, "cmd": ["asmjit_test_execute"] },
{ "optional": true, "cmd": ["asmjit_test_compiler", "--verbose", "--dump-asm"] },
{ "optional": true, "cmd": ["asmjit_test_compiler"] },
{ "optional": true, "cmd": ["asmjit_test_instinfo"] },
{ "optional": true, "cmd": ["asmjit_test_x86_sections"] },
{ "optional": true, "cmd": ["asmjit_test_perf", "--quick"] }

40
.github/workflows/build.yml vendored
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@@ -35,28 +35,28 @@ jobs:
fail-fast: false
matrix:
include:
- { title: "diag-analyze" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Debug" , diagnostics: "analyze-build" }
- { title: "diag-asan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", diagnostics: "asan", defs: "ASMJIT_TEST=1" }
- { title: "diag-msan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", diagnostics: "msan", defs: "ASMJIT_TEST=1" }
- { title: "diag-ubsan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", diagnostics: "ubsan", defs: "ASMJIT_TEST=1" }
- { title: "diag-hardened" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", diagnostics: "hardened", defs: "ASMJIT_TEST=1" }
- { title: "diag-valgrind" , host: "ubuntu-24.04" , arch: "x64" , cc: "clang-18", conf: "Release", diagnostics: "valgrind", defs: "ASMJIT_TEST=1" }
- { title: "diag-analyze" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Debug" , diagnostics: "analyze-build" }
- { title: "diag-asan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", diagnostics: "asan", defs: "ASMJIT_TEST=1" }
- { title: "diag-msan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", diagnostics: "msan", defs: "ASMJIT_TEST=1" }
- { title: "diag-ubsan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", diagnostics: "ubsan", defs: "ASMJIT_TEST=1" }
- { title: "diag-hardened" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", diagnostics: "hardened", defs: "ASMJIT_TEST=1" }
- { title: "diag-valgrind" , host: "ubuntu-24.04" , arch: "x64" , cc: "clang-19", conf: "Release", diagnostics: "valgrind", defs: "ASMJIT_TEST=1" }
- { title: "no-deprecated" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_DEPRECATED=1" }
- { title: "no-intrinsics" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_INTRINSICS=1" }
- { title: "no-logging" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1" }
- { title: "no-logging-text" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1,ASMJIT_NO_TEXT=1" }
- { title: "no-builder" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_BUILDER=1" }
- { title: "no-compiler" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_COMPILER=1" }
- { title: "no-introspection", host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_COMPILER=1,ASMJIT_NO_INTROSPECTION=1" }
- { title: "no-jit" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_JIT=1" }
- { title: "no-validation" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_VALIDATION=1" }
- { title: "no-x86" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_X86=1" }
- { title: "no-aarch64" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_AARCH64=1" }
- { title: "no-deprecated" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_DEPRECATED=1" }
- { title: "no-intrinsics" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_INTRINSICS=1" }
- { title: "no-logging" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1" }
- { title: "no-logging-text" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1,ASMJIT_NO_TEXT=1" }
- { title: "no-builder" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_BUILDER=1" }
- { title: "no-compiler" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_COMPILER=1" }
- { title: "no-introspection", host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_COMPILER=1,ASMJIT_NO_INTROSPECTION=1" }
- { title: "no-jit" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_JIT=1" }
- { title: "no-validation" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_VALIDATION=1" }
- { title: "no-x86" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_X86=1" }
- { title: "no-aarch64" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_AARCH64=1" }
- { title: "lang-c++17" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++17" }
- { title: "lang-c++20" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++20" }
- { title: "lang-c++23" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++23" }
- { title: "lang-c++17" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++17" }
- { title: "lang-c++20" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++20" }
- { title: "lang-c++23" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++23" }
- { title: "linux" , host: "ubuntu-22.04" , arch: "x86" , cc: "gcc-9" , conf: "Debug" , defs: "ASMJIT_TEST=1" }
- { title: "linux" , host: "ubuntu-22.04" , arch: "x86" , cc: "gcc-9" , conf: "Release", defs: "ASMJIT_TEST=1" }

2
LICENSE.md
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@@ -1,4 +1,4 @@
Copyright (c) 2008-2024 The AsmJit Authors
Copyright (c) 2008-2025 The AsmJit Authors
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages

37
db/LICENSE.md
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@@ -1,26 +1,17 @@
AsmJit database is dual licensed under Zlib and Unlicense (public domain)
Copyright (c) 2008-2025 The AsmJit Authors
This is free and unencumbered software released into the public domain.
This software is provided 'as-is', without any express or implied
warranty. In no event will the authors be held liable for any damages
arising from the use of this software.
Anyone is free to copy, modify, publish, use, compile, sell, or
distribute this software, either in source code form or as a compiled
binary, for any purpose, commercial or non-commercial, and by any
means.
Permission is granted to anyone to use this software for any purpose,
including commercial applications, and to alter it and redistribute it
freely, subject to the following restrictions:
In jurisdictions that recognize copyright laws, the author or authors
of this software dedicate any and all copyright interest in the
software to the public domain. We make this dedication for the benefit
of the public at large and to the detriment of our heirs and
successors. We intend this dedication to be an overt act of
relinquishment in perpetuity of all present and future rights to this
software under copyright law.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
OTHER DEALINGS IN THE SOFTWARE.
For more information, please refer to <http://unlicense.org>
1. The origin of this software must not be misrepresented; you must not
claim that you wrote the original software. If you use this software
in a product, an acknowledgment in the product documentation would be
appreciated but is not required.
2. Altered source versions must be plainly marked as such, and must not be
misrepresented as being the original software.
3. This notice may not be removed or altered from any source distribution.

2
db/README.md
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@@ -18,4 +18,4 @@ This project will be refactored and documented in the future.
License
-------
AsmJit database is dual licensed under Zlib (AsmJit license) or public domain. The database can be used for any purpose, not just by AsmJit.
AsmJit database is licensed under [Zlib License](./LICENSE.md)

19
db/aarch32.js
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@@ -1,7 +1,7 @@
// This file is part of AsmJit project <https://asmjit.com>
//
// See asmjit.h or LICENSE.md for license and copyright information
// SPDX-License-Identifier: (Zlib or Unlicense)
// SPDX-License-Identifier: Zlib
(function($scope, $as) {
"use strict";
@@ -14,11 +14,11 @@ function FAIL(msg) { throw new Error("[AArch32] " + msg); }
const base = $scope.base ? $scope.base : require("./base.js");
const exp = $scope.exp ? $scope.exp : require("./exp.js")
const hasOwn = Object.prototype.hasOwnProperty;
const dict = base.dict;
const NONE = base.NONE;
const Parsing = base.Parsing;
const MapUtils = base.MapUtils;
const hasOwn = base.hasOwn;
// Export
// ======
@@ -256,7 +256,8 @@ function splitOpcodeFields(s) {
// ARM operand.
class Operand extends base.Operand {
constructor(def) {
super(def);
super();
this.data = def;
}
hasMemModes() {
@@ -323,9 +324,9 @@ class Instruction extends base.Instruction {
super(db, data);
// name, operands, encoding, opcode, metadata
const encoding = hasOwn.call(data, "a32") ? "a32" :
hasOwn.call(data, "t32") ? "t32" :
hasOwn.call(data, "t16") ? "t16" : "";
const encoding = hasOwn(data, "a32") ? "a32" :
hasOwn(data, "t32") ? "t32" :
hasOwn(data, "t16") ? "t16" : "";
this.name = data.name;
this.it = dict(); // THUMB's 'it' flags.
@@ -962,9 +963,9 @@ class ISA extends base.ISA {
const names = (sep !== -1 ? sgn.substring(0, sep) : sgn).trim().split("/");
const operands = sep !== -1 ? sgn.substring(sep + 1) : "";
const encoding = hasOwn.call(obj, "a32") ? "a32" :
hasOwn.call(obj, "t32") ? "t32" :
hasOwn.call(obj, "t16") ? "t16" : "";
const encoding = hasOwn(obj, "a32") ? "a32" :
hasOwn(obj, "t32") ? "t32" :
hasOwn(obj, "t16") ? "t16" : "";
if (!encoding)
FAIL(`Instruction ${names.join("/")} doesn't encoding, it must provide either a32, t32, or t16 field`);

11
db/aarch64.js
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@@ -1,7 +1,7 @@
// This file is part of AsmJit project <https://asmjit.com>
//
// See asmjit.h or LICENSE.md for license and copyright information
// SPDX-License-Identifier: (Zlib or Unlicense)
// SPDX-License-Identifier: Zlib
(function($scope, $as) {
"use strict";
@@ -296,7 +296,8 @@ function splitOpcodeFields(s) {
// ARM operand.
class Operand extends base.Operand {
constructor(def) {
super(def);
super();
this.data = def;
// Register.
this.sp = ""; // GP register stack access: ["", "WSP" or "SP"].
@@ -895,9 +896,9 @@ class ISA extends base.ISA {
_addInstructions(groups) {
for (let group of groups) {
for (let inst of group.data) {
const sgn = Utils.splitInstructionSignature(inst.inst);
const data = MapUtils.cloneExcept(inst, { "inst": true });
for (let instructions of group.data) {
const sgn = Utils.splitInstructionSignature(instructions.inst);
const data = MapUtils.cloneExcept(instructions, { "inst": true });
mergeGroupData(data, group)

124
db/base.js
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@@ -1,24 +1,28 @@
// This file is part of AsmJit project <https://asmjit.com>
//
// See asmjit.h or LICENSE.md for license and copyright information
// SPDX-License-Identifier: (Zlib or Unlicense)
// SPDX-License-Identifier: Zlib
(function($scope, $as) {
"use strict";
function FAIL(msg) { throw new Error("[BASE] " + msg); }
// Import.
const hasOwn = Object.prototype.hasOwnProperty;
const exp = $scope.exp ? $scope.exp : require("./exp.js");
// Export.
const base = $scope[$as] = Object.create(null);
base.exp = exp;
// Import.
const hasOwnProperty = Object.prototype.hasOwnProperty;
function hasOwn(object, key) {
return hasOwnProperty.call(object, key);
}
base.hasOwn = hasOwn;
function dict(src) {
const dst = Object.create(null);
if (src)
@@ -131,8 +135,14 @@ base.Parsing = Parsing;
// asmdb.base.MapUtils
// ===================
const MapUtils = {
cloneExcept(map, except) {
class MapUtils {
static cloneExcept(map, except) {
if (typeof except === "string") {
const key = except;
except = Object.create(null);
except[key] = true;
}
const out = Object.create(null);
for (let k in map) {
if (k in except)
@@ -141,6 +151,14 @@ const MapUtils = {
}
return out;
}
static mapFromArray(array) {
const out = Object.create(null);
for (let k of array) {
out[k] = true;
}
return out;
}
};
base.MapUtils = MapUtils;
@@ -158,9 +176,9 @@ const OperandFlags = Object.freeze({
base.OperandFlags = OperandFlags;
class Operand {
constructor(data) {
constructor() {
this.type = ""; // Type of the operand ("reg", "reg-list", "mem", "reg/mem", "imm", "rel").
this.data = data; // The operand's data (possibly processed).
this.data = ""; // The operand's data (possibly processed).
this.flags = 0;
this.reg = ""; // Register operand's definition.
@@ -246,7 +264,7 @@ class Instruction {
this.specialRegs = dict(); // Information about read/write to special registers.
this.altForm = false; // This is an alternative form, not needed to create a signature.
this.alt = false; // This is an alternative form, not needed to create a signature.
this.volatile = false; // Instruction is volatile and should not be reordered.
this.control = "none"; // Control flow type (none by default).
this.privilege = ""; // Privilege-level required to execute the instruction.
@@ -373,8 +391,8 @@ class InstructionGroup extends Array {
unionCpuFeatures(name) {
const result = dict();
for (let i = 0; i < this.length; i++) {
const inst = this[i];
const features = inst.ext;
const instruction = this[i];
const features = instruction.ext;
for (let k in features)
result[k] = features[k];
}
@@ -401,13 +419,14 @@ class ISA {
this._instructionNames = null; // Instruction names (sorted), regenerated when needed.
this._instructionMap = dict(); // Instruction name to `Instruction[]` mapping.
this._aliases = dict(); // Instruction aliases.
this._aliasMap = dict(); // Instruction aliases.
this._cpuLevels = dict(); // Architecture versions.
this._extensions = dict(); // Architecture extensions.
this._attributes = dict(); // Instruction attributes.
this._specialRegs = dict(); // Special registers.
this._shortcuts = dict(); // Shortcuts used by instructions metadata.
this.stats = {
insts : 0, // Number of all instructions.
instructions : 0, // Number of all instructions.
groups: 0 // Number of grouped instructions (having unique name).
};
}
@@ -436,7 +455,7 @@ class ISA {
}
get instructionMap() { return this._instructionMap; }
get aliases() { return this._aliases; }
get aliases() { return this._aliasMap; }
get cpuLevels() { return this._cpuLevels; }
get extensions() { return this._extensions; }
get attributes() { return this._attributes; }
@@ -458,27 +477,31 @@ class ISA {
return result;
}
aliasData(name) {
return this._aliases[name] || null;
}
_queryByName(name, copy) {
let result = EmptyInstructionGroup;
const map = this._instructionMap;
if (typeof name === "string") {
const insts = map[name];
if (insts) result = insts;
const instructions = map[name];
if (instructions) result = instructions;
return copy ? result.slice() : result;
}
if (Array.isArray(name)) {
const names = name;
for (let i = 0; i < names.length; i++) {
const insts = map[names[i]];
if (!insts) continue;
const instructions = map[names[i]];
if (!instructions) continue;
if (result === EmptyInstructionGroup)
result = new InstructionGroup();
for (let j = 0; j < insts.length; j++)
result.push(insts[j]);
for (let j = 0; j < instructions.length; j++)
result.push(instructions[j]);
}
return result;
}
@@ -507,23 +530,24 @@ class ISA {
if (data.specialRegs) this._addSpecialRegs(data.specialRegs);
if (data.shortcuts) this._addShortcuts(data.shortcuts);
if (data.instructions) this._addInstructions(data.instructions);
if (data.aliases) this._addAliases(data.aliases);
if (data.postproc) this._postProc(data.postproc);
}
_postProc(groups) {
for (let group of groups) {
for (let iRule of group.instructions) {
const names = iRule.inst.split(" ");
const names = iRule.name.split(" ");
for (let name of names) {
const insts = this._instructionMap[name];
if (!insts)
const instructions = this._instructionMap[name];
if (!instructions)
FAIL(`Instruction ${name} referenced by '${group.group}' group doesn't exist`);
for (let k in iRule) {
if (k === "inst" || k === "data")
if (k === "name" || k === "data")
continue;
for (let inst of insts) {
inst._assignAttribute(k, iRule[k]);
for (let instruction of instructions) {
instruction._assignAttribute(k, iRule[k]);
}
}
}
@@ -630,28 +654,60 @@ class ISA {
FAIL("ISA._addInstructions() must be reimplemented");
}
_addInstruction(inst) {
_addInstruction(instruction) {
let group;
if (hasOwn.call(this._instructionMap, inst.name)) {
group = this._instructionMap[inst.name];
if (hasOwn(this._instructionMap, instruction.name)) {
group = this._instructionMap[instruction.name];
}
else {
group = new InstructionGroup();
this._instructionNames = null;
this._instructionMap[inst.name] = group;
this._instructionMap[instruction.name] = group;
this.stats.groups++;
}
if (inst.aliasOf)
this._aliases[inst.name] = inst.aliasOf;
if (instruction.aliasOf) {
this._addAlias(instruction.name, instruction.aliasOf);
}
group.push(inst);
this.stats.insts++;
group.push(instruction);
this.stats.instructions++;
this._instructions = null;
return this;
}
// Add aliases from instruction database - aliases must be an object where each key is a non-aliased instruction.
_addAliases(aliases) {
for (let instructionName in aliases) {
const data = aliases[instructionName];
for (let aliasName of data.aliases) {
this._addAlias(instructionName, aliasName, data.format || "");
}
}
}
_addAlias(instructionName, aliasName, aliasFormat) {
const group = this._instructionMap[instructionName];
if (!group) {
FAIL(`Instruction ${instructionName} doesn't exist when processing alias (${aliasName})`);
}
let alias = this._aliases[instructionName];
if (!alias) {
alias = dict({
primaryName: instructionName,
aliasNames: [],
format: ""
});
this._aliases[instructionName] = alias;
}
this._aliasMap[aliasName] = instructionName;
alias.aliasNames.push(aliasName);
alias.format = aliasFormat || "";
}
}
base.ISA = ISA;

2
db/exp.js
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@@ -1,7 +1,7 @@
// This file is part of AsmJit project <https://asmjit.com>
//
// See asmjit.h or LICENSE.md for license and copyright information
// SPDX-License-Identifier: (Zlib or Unlicense)
// SPDX-License-Identifier: Zlib
(function($scope, $as) {
"use strict";

2
db/index.js
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@@ -1,7 +1,7 @@
// This file is part of AsmJit project <https://asmjit.com>
//
// See asmjit.h or LICENSE.md for license and copyright information
// SPDX-License-Identifier: (Zlib or Unlicense)
// SPDX-License-Identifier: Zlib
"use strict";

8942
db/isa_x86.json
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145
db/isa_x86.md Normal file
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@@ -0,0 +1,145 @@
X86 ISA - JSON Database Documentation
-------------------------------------
This file provides a documentation of isa_x86.json file, which contains a compact X86 and X86_64 instruction database. The database has been created from several manuals from Intel and AMD, which describes the encoding of instructions and other properties. The database tries to keep the instruction and opcode formats compatible with the database, however, in cases where applicable it tries to simplify it (for example merging instructions that all use either XMM, YMM, or ZMM registers, etc...).
## Instruction Category
Each set of instructions start with category group, which looks like the following:
```json
{"category": "<LIST_OF_CATEGORIES>", "ext": "<LIST_OF_EXTENSIONS>", /* flags, */ "instructions": [
/* (instruction records) */
]}
```
Fields:
- `category` - describes a single or multiple categories this instruction belongs to. In general the database is written in a way to provide "baseline" and "extended" categories, so have the following categories used to distinguish between different set of instructions:
- `GP` - General purpose instructions.
- `GP_EXT` - Extensions to general purpose instructions (such as BMI, POPCNT, etc...).
- `MMX` - MMX and 3DNOW instructions (in general instructions using MM registers).
- `SSE` - SSE to SSE4.2 instructions, including other extensions that don't use VEX/EVEX prefixes.
- `AVX` - AVX, AVX2, and other instructions that use SIMD registers (XMM, YMM) and VEX prefix.
- `AVX512` - AVX512 instructions.
- `ext` (optional) - describes extensions required to execute the instruction. When multiple extensions are in the list it means ALL of them must be available. For example `AESNI` means that `AESNI` extension is required, `AVX AESNI` means that both `AVX` and `AESNI` extensions are required.
- `deprecated` (optional) - deprecation flag (either `true` or `false`), by default instructions are not deprecated.
- `volatile` (optional) - volatility flag (either `true` or `false`), by default instructions are not volatile (note that volatile flag is used for code generators and in general it says that the instruction should not be reordered and nothing above it should move below and vice versa).
- `instructions` - array of instruction records, one line per instruction.
## Instruction Record
A single instruction record looks like the following:
```json
{"<ARCH>": "<INSTRUCTION_SIGNATURE>", "op": "[<ENCODING_OPS>] <ENCODING_DATA>" /*, <ADDITIONAL_DATA>*/ }
```
### Architecture Field
`<ARCH>` field describes the architecture and optionally `APX_F` promoted instruction:
- `any` - The instruction can run in both 32-bit and 64-bit mode and shares the encoding.
- `x86` - The instruction can only run in 32-bit mode. This in general may be an indication that the instruction was deprecated in 64-bit mode or that the instruction has a different signature in 64-bit mode (some instructions require 32-bit registers in 32-bit mode and 64-bit registers in 64-bit mode, for example)
- `x64` - The instruction can only run in 64-bit mode.
- `apx` - The instruction can only run in 64-bit mode with `APX_F` extension present. This notation is only used for `APX_F` instructions that provide alternative `EVEX` encoding to existing instructions, but not new `APX_F` only instructions. For example `jmpabs` instruction is a new `APX_F` instruction, thus the arch notation it uses is `x64`.
Explanation: The database uses this "variable" field name to save space and to avoid defining the architecture elsewhere.
### Instruction Signature
Instruction signature is composed of the following components:
```
[<PREFIX>|<OPTIONS>] <INSTRUCTION_NAME>|<ALIASES> <OPERANDS>
```
- `[<PREFIX>|<OPTIONS>]` (optional) - prefixes and other options:
- `[bnd]` - instruction supports `bnd` prefix (deprecated).
- `[lock]` - instruction supports `lock` prefix.
- `[xacquire]` - instruction supports `xacquire` prefix.
- `[xacqrel]` - instruction supports both `xacquire` and `xrelease` prefixes.
- `[xrelease]` - instruction supports `xrelease` prefix.
- `[rep]` - instruction supports `rep` prefix (or `repe`).
- `[repne]` - instruction supports `repne` prefix.
- `[repIgnore]` - instruction supports `rep` prefix, which is ignored during execution (to support for example `rep ret`).
- `<INSTRUCTION_NAME>|<ALIASES>` (required) - the name of the instruction possibly followed by aliases if the instruction has them
- if the instruction has aliases, they will be recognized in AsmJit API (the API will provide aliases), but will not have a separate instruction identifier
- for example `cmovz|cmove` is a `cmovz` instruction that has a `cmove` alias.
- `<OPERANDS>` (optional):
- When an instruction has multiple operands, they are separated by comma.
- Registers:
- `r8` - 8-bit general purpose register.
- `r16` - 16-bit general purpose register.
- `r32` - 32-bit general purpose register.
- `r64` - 64-bit general purpose register (x64 only).
- `mm` - 64-bit MM register.
- `xmm` - 128-bit XMM register (SSE).
- `ymm` - 256-bit YMM register (AVX)
- `zmm` - 512-bit ZMM register (AVX512/AVX10).
- `k` - 64-bit K register (AVX512/AVX10).
- `tmm` - TMM register (AMX).
- `creg` - Control register.
- `dreg` - Debug register.
- `st(x)` - FPU register.
- `rip` - Instruction pointer register (used during addressing).
- `bnd` - Bounds register (deprecated).
- Memory:
- `mem` - Memory operand without size specified.
- `m8-m512` - Memory operand of a specified size.
- Immediate values
- `imm4` - Signed or unsigned 4-bit immediate value (only used by instructions where the other 4 bits are used to encode additional register operand).
- `imm8` - Signed or unsigned 8-bit immediate value.
- `imm16` - Signed or unsigned 16-bit immediate value.
- `imm32` - Signed or unsigned 32-bit immediate value.
- `imm64` - Signed or unsigned 64-bit immediate value.
- `imms8` - Signed 8-bit immediate value (instructions that sign-extend the immediate value to 32 or 64 bits).
- `immu8` - Unsigned 8-bit immediate value (instructions that zero-extend the immediate value to 32 or 64 bits).
- `immu16` - Unsigned 16-bit immediate value (instructions that zero-extend the immediate value to 32 or 64 bits).
- `imms32` - Signed 32-bit immediate value (instructions that sign-extend the immediate value to 64 bits).
- `immu32` - Unsigned 32-bit immediate value (instructions that zero-extend the immediate value to 64 bits).
- Relative operands (addressing labels and relative locations in code):
- `rel8` - 8-bit signed relative displacement.
- `rel16` - 16-bit signed relative displacement.
- `rel32` - 32-bit signed relative displacement.
- Combining:
- Register and memory operands can be combined, for example `r8/m8` means either 8-bit register or 8-bit memory operand
- Read/Write access:
- The first operand must be decorated by access in a form `[r|w|x]: <OPERAND>`:
- `R:` - read access.
- `W:` - write access (overwrites the whole register).
- `w:` - write access (only overwrites an addressed part of the register - 8-bit and 16-bit GP registers use this access).
- `X:` - read/write access (the final write operation overwrites the whole register).
- `x:` - read/write access (the final write operation only overwrites the addressed part of the register - 16-bit GP access).
- The access of the second operand and following operands is implied to be read-only, when not specified explicitly.
- Grouping:
- If the encoding used for multiple register combinations is the same, multiple instructions can be grouped into a single record.
- `GP` Instructions:
- `ry` - either `r32` or `r64`.
- `my` - either `m32` or `m64`.
- `rv` - either `r16`, `r32`, or `r64`.
- `mv` - either `m16`, `m32`, or `m64`.
- `immv` - either `imm16`, `imm32`, or `simm32`.
- All registers must match, example: `add x:rv, rv/mv` - either all `r16/m16`, `r32/m32`, or `r64/m64`.
- When `rv/mv/immv` is used, the instruction must use `66h` prefix (or 66h part of `VEX/EVEX`) when a 16-bit `r16/m16` is used, and `REX.W` (or `W` part of `VEX/EVEX`) when a 64-bit `r64/m64` is used. The immediate expands to `imm16` for instructions working with 16-bit registers, to `imm32` for instructions working with 32-bit registers, and to `simm32` for instructions working with 64-bit registers (32-bit immediate sign extended to 64 bits).
- When `rv/mv` is used with `w` and `x` access option, it only applies to a 16-bit operation, wider operations would use `W` or `X` (this is an architectural constraint that the tool processing the database must be aware of)
- Why `y` and `v`? `ry/my` and `rv/mv` appeared in initial manuals describing `APX_F` extension, so this database is using exactly this notation to group multiple instructions into a single entry.
- `AVX` Instructions:
- `xy/mxy` - either `xmm/m128` or `ymm/m256` register operand.
- All registers must match, example: `vfmadd132pd X:xy, xy, xy/mxy` - either all `xmm/m128` or all `ymm/m256`.
- Why `xy/mxy`? This notation is not used by instruction manuals, but we have found it easy to use and understand.
- `AVX512` and `AVX10` Instructions:
- `xxx/mxxx` - either `xmm[31:0]/m32`, `xmm[63:0]/m64`, or `xmm/m128` register operand.
- `xxy/mxxy` - either `xmm[63:0]/m64`, `xmm/m128`, or `ymm/m256` register operand.
- `xyz/mxyz` - either `xmm/m128`, `ymm/m256`, or `zmm/m512` register operand.
- All registers must match, example: `vvfmadd132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}` - either all `xmm/m128`, `ymm/m256`, or `zmm/m512`.
- Embedded rounding `{er}` and `{sae}` are grouped - in AVX512 case only 512-bit operations can use `{er}/{sae}`; in AVX10.2 case both 256-bit and 512-bit operations can use `{er}/{sae}`, but not 128-bit operations - the assembler or the tool processing this data must be aware of this architectural constraint.
- Why `xyz/mxyz`? This notation is not used by instruction manuals, but we have found it easy to use and understand.

2
db/package.json
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@@ -1,7 +1,7 @@
{
"name": "asmdb",
"version": "0.1.0",
"license": "Unlicense",
"license": "Zlib",
"engines": { "node": ">=8" },
"description": "Instructions database and utilities for X86/X64 and ARM (THUMB/A32/A64) architectures.",

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db/x86.js
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19
src/asmjit/arm/a64formatter.cpp
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@@ -24,17 +24,23 @@ ASMJIT_BEGIN_SUB_NAMESPACE(a64)
ASMJIT_FAVOR_SIZE Error FormatterInternal::formatInstruction(
String& sb,
FormatFlags flags,
FormatFlags formatFlags,
const BaseEmitter* emitter,
Arch arch,
const BaseInst& inst, const Operand_* operands, size_t opCount) noexcept {
// Format instruction options and instruction mnemonic.
InstId instId = inst.realId();
if (instId != Inst::kIdNone && instId < Inst::_kIdCount)
ASMJIT_PROPAGATE(InstInternal::instIdToString(instId, sb));
else
if (instId != Inst::kIdNone && instId < Inst::_kIdCount) {
InstStringifyOptions stringifyOptions =
Support::test(formatFlags, FormatFlags::kShowAliases)
? InstStringifyOptions::kAliases
: InstStringifyOptions::kNone;
ASMJIT_PROPAGATE(InstInternal::instIdToString(instId, stringifyOptions, sb));
}
else {
ASMJIT_PROPAGATE(sb.appendFormat("[InstId=#%u]", unsigned(instId)));
}
CondCode cc = inst.armCondCode();
if (cc != CondCode::kAL) {
@@ -44,11 +50,12 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatInstruction(
for (uint32_t i = 0; i < opCount; i++) {
const Operand_& op = operands[i];
if (op.isNone())
if (op.isNone()) {
break;
}
ASMJIT_PROPAGATE(sb.append(i == 0 ? " " : ", "));
ASMJIT_PROPAGATE(formatOperand(sb, flags, emitter, arch, op));
ASMJIT_PROPAGATE(formatOperand(sb, formatFlags, emitter, arch, op));
}
return kErrorOk;

18
src/asmjit/arm/a64instapi.cpp
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@@ -21,16 +21,28 @@ namespace InstInternal {
// ========================
#ifndef ASMJIT_NO_TEXT
Error instIdToString(InstId instId, String& output) noexcept {
Error instIdToString(InstId instId, InstStringifyOptions options, String& output) noexcept {
uint32_t realId = instId & uint32_t(InstIdParts::kRealId);
if (ASMJIT_UNLIKELY(!Inst::isDefinedId(realId)))
return DebugUtils::errored(kErrorInvalidInstruction);
return InstNameUtils::decode(output, InstDB::_instNameIndexTable[realId], InstDB::_instNameStringTable);
return InstNameUtils::decode(InstDB::_instNameIndexTable[realId], options, InstDB::_instNameStringTable, output);
}
InstId stringToInstId(const char* s, size_t len) noexcept {
return InstNameUtils::find(s, len, InstDB::instNameIndex, InstDB::_instNameIndexTable, InstDB::_instNameStringTable);
if (ASMJIT_UNLIKELY(!s)) {
return BaseInst::kIdNone;
}
if (len == SIZE_MAX) {
len = strlen(s);
}
if (len == 0u || len > InstDB::instNameIndex.maxNameLength) {
return BaseInst::kIdNone;
}
return InstNameUtils::findInstruction(s, len, InstDB::_instNameIndexTable, InstDB::_instNameStringTable, InstDB::instNameIndex);
}
#endif // !ASMJIT_NO_TEXT

2
src/asmjit/arm/a64instapi_p.h
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@@ -18,7 +18,7 @@ ASMJIT_BEGIN_SUB_NAMESPACE(a64)
namespace InstInternal {
#ifndef ASMJIT_NO_TEXT
Error ASMJIT_CDECL instIdToString(InstId instId, String& output) noexcept;
Error ASMJIT_CDECL instIdToString(InstId instId, InstStringifyOptions options, String& output) noexcept;
InstId ASMJIT_CDECL stringToInstId(const char* s, size_t len) noexcept;
#endif // !ASMJIT_NO_TEXT

13
src/asmjit/core.h
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@@ -275,6 +275,19 @@ namespace asmjit {
//!
//! \section api_changes API Changes
//!
//! ### Changes committed at XXXX-XX-XX
//!
//! Core changes:
//!
//! - Removed AVX512 functionality that was never used on x86 hardware as Xeon Phi was never supported by AsmJit:
//!
//! - AVX512_ER
//! - AVX512_PF
//! - AVX512_4FMAPS
//! - AVX512_4VNNIW
//!
//! - Instruction 'vcvtneps2bf16' no longer accepts memory operand without explicit size (to minimize ambiguity)
//!
//! ### Changes committed at 2024-01-01
//!
//! Core changes:

4
src/asmjit/core/api-config.h
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@@ -16,7 +16,7 @@
#define ASMJIT_LIBRARY_MAKE_VERSION(major, minor, patch) ((major << 16) | (minor << 8) | (patch))
//! AsmJit library version, see \ref ASMJIT_LIBRARY_MAKE_VERSION for a version format reference.
#define ASMJIT_LIBRARY_VERSION ASMJIT_LIBRARY_MAKE_VERSION(1, 14, 0)
#define ASMJIT_LIBRARY_VERSION ASMJIT_LIBRARY_MAKE_VERSION(1, 15, 0)
//! \def ASMJIT_ABI_NAMESPACE
//!
@@ -27,7 +27,7 @@
//! AsmJit default, which makes it possible to use multiple AsmJit libraries within a single project, totally
//! controlled by users. This is useful especially in cases in which some of such library comes from third party.
#if !defined(ASMJIT_ABI_NAMESPACE)
#define ASMJIT_ABI_NAMESPACE v1_14
#define ASMJIT_ABI_NAMESPACE v1_15
#endif // !ASMJIT_ABI_NAMESPACE
//! \}

24
src/asmjit/core/compiler.h
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@@ -118,18 +118,6 @@ public:
//! Emits a sentinel that marks the end of the current function.
ASMJIT_API Error endFunc();
#if !defined(ASMJIT_NO_DEPRECATED)
inline Error _setArg(size_t argIndex, size_t valueIndex, const BaseReg& reg);
//! Sets a function argument at `argIndex` to `reg`.
ASMJIT_DEPRECATED("Setting arguments through Compiler is deprecated, use FuncNode->setArg() instead")
inline Error setArg(size_t argIndex, const BaseReg& reg) { return _setArg(argIndex, 0, reg); }
//! Sets a function argument at `argIndex` at `valueIndex` to `reg`.
ASMJIT_DEPRECATED("Setting arguments through Compiler is deprecated, use FuncNode->setArg() instead")
inline Error setArg(size_t argIndex, size_t valueIndex, const BaseReg& reg) { return _setArg(argIndex, valueIndex, reg); }
#endif
inline Error addRet(const Operand_& o0, const Operand_& o1) {
FuncRetNode* node;
return addFuncRetNode(&node, o0, o1);
@@ -721,18 +709,6 @@ public:
//! \}
};
#if !defined(ASMJIT_NO_DEPRECATED)
inline Error BaseCompiler::_setArg(size_t argIndex, size_t valueIndex, const BaseReg& reg) {
FuncNode* func = _func;
if (ASMJIT_UNLIKELY(!func))
return reportError(DebugUtils::errored(kErrorInvalidState));
func->setArg(argIndex, valueIndex, reg);
return kErrorOk;
}
#endif
//! \}
ASMJIT_END_NAMESPACE

116
src/asmjit/core/cpuinfo.cpp
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@@ -235,8 +235,8 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept {
// We are gonna execute CPUID, which was introduced by I486, so it's the requirement.
features.add(Ext::kI486);
// CPUID EAX=0
// -----------
// CPUID EAX=0x00 (Basic CPUID Information)
// ----------------------------------------
// Get vendor string/id.
cpuidQuery(&regs, 0x0);
@@ -246,10 +246,10 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept {
simplifyCpuVendor(cpu, regs.ebx, regs.edx, regs.ecx);
// CPUID EAX=1
// -----------
// CPUID EAX=0x01 (Basic CPUID Information)
// ----------------------------------------
if (maxId >= 0x1) {
if (maxId >= 0x01u) {
// Get feature flags in ECX/EDX and family/model in EAX.
cpuidQuery(&regs, 0x1);
@@ -317,39 +317,35 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept {
}
constexpr uint32_t kXCR0_AMX_Bits = 0x3u << 17;
bool amxEnabledByOS = (xcr0.eax & kXCR0_AMX_Bits) == kXCR0_AMX_Bits;
bool amxEnabled = (xcr0.eax & kXCR0_AMX_Bits) == kXCR0_AMX_Bits;
#if defined(__APPLE__)
// Apple platform provides on-demand AVX512 support. When an AVX512 instruction is used the first time it results
// in #UD, which would cause the thread being promoted to use AVX512 support by the OS in addition to enabling the
// necessary bits in XCR0 register.
bool avx512EnabledByOS = true;
bool avx512Enabled = true;
#else
// - XCR0[2:1] == 11b - XMM/YMM states need to be enabled by OS.
// - XCR0[7:5] == 111b - Upper 256-bit of ZMM0-XMM15 and ZMM16-ZMM31 need to be enabled by OS.
constexpr uint32_t kXCR0_AVX512_Bits = (0x3u << 1) | (0x7u << 5);
bool avx512EnabledByOS = (xcr0.eax & kXCR0_AVX512_Bits) == kXCR0_AVX512_Bits;
bool avx512Enabled = (xcr0.eax & kXCR0_AVX512_Bits) == kXCR0_AVX512_Bits;
#endif
// CPUID EAX=7 ECX=0
// -----------------
bool avx10Enabled = false;
// Detect new features if the processor supports CPUID-07.
bool maybeMPX = false;
// CPUID EAX=0x07 ECX=0 (Structured Extended Feature Flags Enumeration Leaf)
// -------------------------------------------------------------------------
if (maxId >= 0x7) {
if (maxId >= 0x07u) {
cpuidQuery(&regs, 0x7);
maybeMPX = bitTest(regs.ebx, 14);
maxSubLeafId_0x7 = regs.eax;
features.addIf(bitTest(regs.ebx, 0), Ext::kFSGSBASE);
features.addIf(bitTest(regs.ebx, 3), Ext::kBMI);
features.addIf(bitTest(regs.ebx, 4), Ext::kHLE);
features.addIf(bitTest(regs.ebx, 7), Ext::kSMEP);
features.addIf(bitTest(regs.ebx, 8), Ext::kBMI2);
features.addIf(bitTest(regs.ebx, 9), Ext::kERMS);
features.addIf(bitTest(regs.ebx, 11), Ext::kRTM);
features.addIf(bitTest(regs.ebx, 18), Ext::kRDSEED);
features.addIf(bitTest(regs.ebx, 19), Ext::kADX);
features.addIf(bitTest(regs.ebx, 20), Ext::kSMAP);
@@ -364,6 +360,7 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept {
features.addIf(bitTest(regs.ecx, 9), Ext::kVAES);
features.addIf(bitTest(regs.ecx, 10), Ext::kVPCLMULQDQ);
features.addIf(bitTest(regs.ecx, 22), Ext::kRDPID);
features.addIf(bitTest(regs.ecx, 23), Ext::kKL);
features.addIf(bitTest(regs.ecx, 25), Ext::kCLDEMOTE);
features.addIf(bitTest(regs.ecx, 27), Ext::kMOVDIRI);
features.addIf(bitTest(regs.ecx, 28), Ext::kMOVDIR64B);
@@ -375,22 +372,15 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept {
features.addIf(bitTest(regs.edx, 18), Ext::kPCONFIG);
features.addIf(bitTest(regs.edx, 20), Ext::kCET_IBT);
// Detect 'TSX' - Requires at least one of `HLE` and `RTM` features.
if (features.hasHLE() || features.hasRTM()) {
features.add(Ext::kTSX);
}
if (bitTest(regs.ebx, 5) && features.hasAVX()) {
features.add(Ext::kAVX2);
}
if (avx512EnabledByOS && bitTest(regs.ebx, 16)) {
if (avx512Enabled && bitTest(regs.ebx, 16)) {
features.add(Ext::kAVX512_F);
features.addIf(bitTest(regs.ebx, 17), Ext::kAVX512_DQ);
features.addIf(bitTest(regs.ebx, 21), Ext::kAVX512_IFMA);
features.addIf(bitTest(regs.ebx, 26), Ext::kAVX512_PF);
features.addIf(bitTest(regs.ebx, 27), Ext::kAVX512_ER);
features.addIf(bitTest(regs.ebx, 28), Ext::kAVX512_CD);
features.addIf(bitTest(regs.ebx, 30), Ext::kAVX512_BW);
features.addIf(bitTest(regs.ebx, 31), Ext::kAVX512_VL);
@@ -399,21 +389,19 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept {
features.addIf(bitTest(regs.ecx, 11), Ext::kAVX512_VNNI);
features.addIf(bitTest(regs.ecx, 12), Ext::kAVX512_BITALG);
features.addIf(bitTest(regs.ecx, 14), Ext::kAVX512_VPOPCNTDQ);
features.addIf(bitTest(regs.edx, 2), Ext::kAVX512_4VNNIW);
features.addIf(bitTest(regs.edx, 3), Ext::kAVX512_4FMAPS);
features.addIf(bitTest(regs.edx, 8), Ext::kAVX512_VP2INTERSECT);
features.addIf(bitTest(regs.edx, 23), Ext::kAVX512_FP16);
}
if (amxEnabledByOS) {
if (amxEnabled) {
features.addIf(bitTest(regs.edx, 22), Ext::kAMX_BF16);
features.addIf(bitTest(regs.edx, 24), Ext::kAMX_TILE);
features.addIf(bitTest(regs.edx, 25), Ext::kAMX_INT8);
}
}
// CPUID EAX=7 ECX=1
// -----------------
// CPUID EAX=0x07 ECX=1 (Structured Extended Feature Enumeration Sub-leaf)
// -----------------------------------------------------------------------
if (maxSubLeafId_0x7 >= 1) {
cpuidQuery(&regs, 0x7, 1);
@@ -430,6 +418,8 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept {
features.addIf(bitTest(regs.eax, 22), Ext::kHRESET);
features.addIf(bitTest(regs.eax, 26), Ext::kLAM);
features.addIf(bitTest(regs.eax, 27), Ext::kMSRLIST);
features.addIf(bitTest(regs.eax, 31), Ext::kMOVRS);
features.addIf(bitTest(regs.ecx, 5), Ext::kMSR_IMM);
features.addIf(bitTest(regs.ebx, 1), Ext::kTSE);
features.addIf(bitTest(regs.edx, 14), Ext::kPREFETCHI);
features.addIf(bitTest(regs.edx, 18), Ext::kCET_SSS);
@@ -447,22 +437,20 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept {
features.addIf(bitTest(regs.eax, 5), Ext::kAVX512_BF16);
}
if (amxEnabledByOS) {
if (features.hasAVX512_F()) {
avx10Enabled = Support::bitTest(regs.edx, 19);
}
if (amxEnabled) {
features.addIf(bitTest(regs.eax, 21), Ext::kAMX_FP16);
features.addIf(bitTest(regs.edx, 8), Ext::kAMX_COMPLEX);
}
}
// CPUID EAX=13 ECX=0
// ------------------
if (maxId >= 0xD) {
cpuidQuery(&regs, 0xD, 0);
// Both CPUID result and XCR0 has to be enabled to have support for MPX.
if (((regs.eax & xcr0.eax) & 0x00000018u) == 0x00000018u && maybeMPX)
features.add(Ext::kMPX);
// CPUID EAX=0x0D ECX=1 (Processor Extended State Enumeration Sub-leaf)
// --------------------------------------------------------------------
if (maxId >= 0x0Du) {
cpuidQuery(&regs, 0xD, 1);
features.addIf(bitTest(regs.eax, 0), Ext::kXSAVEOPT);
@@ -470,15 +458,57 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept {
features.addIf(bitTest(regs.eax, 3), Ext::kXSAVES);
}
// CPUID EAX=14 ECX=0
// ------------------
// CPUID EAX=0x0E ECX=0 (Processor Trace Enumeration Main Leaf)
// ------------------------------------------------------------
if (maxId >= 0xE) {
cpuidQuery(&regs, 0xE, 0);
if (maxId >= 0x0Eu) {
cpuidQuery(&regs, 0x0E, 0);
features.addIf(bitTest(regs.ebx, 4), Ext::kPTWRITE);
}
// CPUID EAX=0x19 ECX=0 (Key Locker Leaf)
// --------------------------------------
if (maxId >= 0x19u && features.hasKL()) {
cpuidQuery(&regs, 0x19, 0);
features.addIf(bitTest(regs.ebx, 0), Ext::kAESKLE);
features.addIf(bitTest(regs.ebx, 0) && bitTest(regs.ebx, 2), Ext::kAESKLEWIDE_KL);
}
// CPUID EAX=0x1E ECX=1 (TMUL Information Sub-leaf)
// ------------------------------------------------
if (maxId >= 0x1Eu && features.hasAMX_TILE()) {
cpuidQuery(&regs, 0x1E, 1);
// NOTE: Some AMX flags are mirrored here from CPUID[0x07, 0x00].
features.addIf(bitTest(regs.eax, 0), Ext::kAMX_INT8);
features.addIf(bitTest(regs.eax, 1), Ext::kAMX_BF16);
features.addIf(bitTest(regs.eax, 2), Ext::kAMX_COMPLEX);
features.addIf(bitTest(regs.eax, 3), Ext::kAMX_FP16);
features.addIf(bitTest(regs.eax, 4), Ext::kAMX_FP8);
features.addIf(bitTest(regs.eax, 5), Ext::kAMX_TRANSPOSE);
features.addIf(bitTest(regs.eax, 6), Ext::kAMX_TF32);
features.addIf(bitTest(regs.eax, 7), Ext::kAMX_AVX512);
features.addIf(bitTest(regs.eax, 8), Ext::kAMX_MOVRS);
}
// CPUID EAX=0x24 ECX=0 (AVX10 Information)
// ----------------------------------------
if (maxId >= 0x24u && avx10Enabled) {
// EAX output is the maximum supported sub-leaf.
cpuidQuery(&regs, 0x24, 0);
// AVX10 Converged Vector ISA version.
uint32_t ver = regs.ebx & 0xFFu;
features.addIf(ver >= 1u, Ext::kAVX10_1);
features.addIf(ver >= 2u, Ext::kAVX10_2);
}
// CPUID EAX=0x80000000...maxId
// ----------------------------

282
src/asmjit/core/cpuinfo.h
View File

@@ -174,11 +174,6 @@ public:
//! Tests whether this CPU features data matches `other`.
ASMJIT_INLINE_NODEBUG bool equals(const Data& other) const noexcept { return _bits == other._bits; }
#if !defined(ASMJIT_NO_DEPRECATED)
ASMJIT_DEPRECATED("Use CpuFeatures::Data::equals() instead")
ASMJIT_INLINE_NODEBUG bool eq(const Data& other) const noexcept { return equals(other); }
#endif // !ASMJIT_NO_DEPRECATED
//! \}
};
@@ -191,42 +186,9 @@ public:
kMT, //!< CPU has multi-threading capabilities.
kNX, //!< CPU has Not-Execute-Bit aka DEP (data-execution prevention).
k3DNOW, //!< CPU has 3DNOW (3DNOW base instructions) {AMD} (deprecated).
k3DNOW2, //!< CPU has 3DNOW2 (enhanced 3DNOW) {AMD} (deprecated).
kADX, //!< CPU has ADX (multi-precision add-carry instruction extensions).
kAESNI, //!< CPU has AESNI (AES encode/decode instructions).
kALTMOVCR8, //!< CPU has LOCK MOV R<->CR0 (supports `MOV R<->CR8` via `LOCK MOV R<->CR0` in 32-bit mode) {AMD}.
kAMX_BF16, //!< CPU has AMX_BF16 (AMX-BF16 instructions).
kAMX_COMPLEX, //!< CPU has AMX_COMPLEX (AMX-COMPLEX instructions).
kAMX_FP16, //!< CPU has AMX_FP16 (AMX-FP16 instructions).
kAMX_INT8, //!< CPU has AMX_INT8 (AMX-INT8 instructions).
kAMX_TILE, //!< CPU has AMX_TILE (advanced matrix extensions).
kAPX_F, //!< CPU has APX_F (advanced performance extensions - 32 GP registers, REX2 prefix, ...) {X86_64}.
kAVX, //!< CPU has AVX (advanced vector extensions).
kAVX2, //!< CPU has AVX2 (advanced vector extensions 2).
kAVX512_4FMAPS, //!< CPU has AVX512_FMAPS (FMA packed single).
kAVX512_4VNNIW, //!< CPU has AVX512_VNNIW (vector NN instructions word variable precision).
kAVX512_BF16, //!< CPU has AVX512_BF16 (AVX512 BFLOAT16 support instructions).
kAVX512_BITALG, //!< CPU has AVX512_BITALG (AVX512 VPOPCNT[B|W] and VPSHUFBITQMB instructions).
kAVX512_BW, //!< CPU has AVX512_BW (AVX512 integer BYTE|WORD instructions).
kAVX512_CD, //!< CPU has AVX512_CD (AVX512 conflict detection DWORD|QWORD instructions).
kAVX512_DQ, //!< CPU has AVX512_DQ (AVX512 integer DWORD|QWORD instructions).
kAVX512_ER, //!< CPU has AVX512_ER (AVX512 exponential and reciprocal instructions).
kAVX512_F, //!< CPU has AVX512_F (AVX512 foundation).
kAVX512_FP16, //!< CPU has AVX512_FP16 (AVX512 FP16 instructions).
kAVX512_IFMA, //!< CPU has AVX512_IFMA (AVX512 integer fused-multiply-add using 52-bit precision).
kAVX512_PF, //!< CPU has AVX512_PF (AVX512 prefetch instructions).
kAVX512_VBMI, //!< CPU has AVX512_VBMI (AVX152 vector byte manipulation instructions).
kAVX512_VBMI2, //!< CPU has AVX512_VBMI2 (AVX512 vector byte manipulation instructions v2).
kAVX512_VL, //!< CPU has AVX512_VL (AVX512 vector length extensions).
kAVX512_VNNI, //!< CPU has AVX512_VNNI (AVX512 vector neural network instructions).
kAVX512_VP2INTERSECT, //!< CPU has AVX512_VP2INTERSECT
kAVX512_VPOPCNTDQ, //!< CPU has AVX512_VPOPCNTDQ (AVX512 VPOPCNT[D|Q] instructions).
kAVX_IFMA, //!< CPU has AVX_IFMA (AVX/VEX encoding of vpmadd52huq/vpmadd52luq).
kAVX_NE_CONVERT, //!< CPU has AVX_NE_CONVERT.
kAVX_VNNI, //!< CPU has AVX_VNNI (AVX/VEX encoding of vpdpbusd/vpdpbusds/vpdpwssd/vpdpwssds).
kAVX_VNNI_INT16, //!< CPU has AVX_VNNI_INT16.
kAVX_VNNI_INT8, //!< CPU has AVX_VNNI_INT8.
kBMI, //!< CPU has BMI (bit manipulation instructions #1).
kBMI2, //!< CPU has BMI2 (bit manipulation instructions #2).
kCET_IBT, //!< CPU has CET-IBT (indirect branch tracking).
@@ -244,10 +206,6 @@ public:
kENCLV, //!< CPU has ENCLV.
kENQCMD, //!< CPU has ENQCMD (enqueue stores).
kERMS, //!< CPU has ERMS (enhanced REP MOVSB/STOSB).
kF16C, //!< CPU has F16C (AVX FP16 conversion instructions).
kFMA, //!< CPU has FMA (AVX fused-multiply-add - 3 operand form).
kFMA4, //!< CPU has FMA4 (AVX fused-multiply-add - 4 operand form) (deprecated).
kFPU, //!< CPU has FPU (FPU support).
kFSGSBASE, //!< CPU has FSGSBASE.
kFSRM, //!< CPU has FSRM (fast short REP MOVSB).
kFSRC, //!< CPU has FSRC (fast short REP CMPSB|SCASB).
@@ -255,9 +213,6 @@ public:
kFXSR, //!< CPU has FXSR (FXSAVE/FXRSTOR instructions).
kFXSROPT, //!< CPU has FXSROTP (FXSAVE/FXRSTOR is optimized).
kFZRM, //!< CPU has FZRM (fast zero-length REP MOVSB).
kGEODE, //!< CPU has GEODE extensions (GEODE 3DNOW additions) (deprecated).
kGFNI, //!< CPU has GFNI (galois field instructions).
kHLE, //!< CPU has HLE.
kHRESET, //!< CPU has HRESET.
kI486, //!< CPU has I486 features (I486+ support).
kINVLPGB, //!< CPU has INVLPGB.
@@ -266,20 +221,19 @@ public:
kLWP, //!< CPU has LWP (lightweight profiling) {AMD}.
kLZCNT, //!< CPU has LZCNT (LZCNT instruction).
kMCOMMIT, //!< CPU has MCOMMIT (MCOMMIT instruction).
kMMX, //!< CPU has MMX (MMX base instructions) (deprecated).
kMMX2, //!< CPU has MMX2 (MMX2 extensions or initial SSE extensions) (deprecated).
kMONITOR, //!< CPU has MONITOR (MONITOR/MWAIT instructions).
kMONITORX, //!< CPU has MONITORX (MONITORX/MWAITX instructions).
kMOVBE, //!< CPU has MOVBE (move with byte-order swap).
kMOVDIR64B, //!< CPU has MOVDIR64B (move 64 bytes as direct store).
kMOVDIRI, //!< CPU has MOVDIRI (move dword/qword as direct store).
kMOVRS, //!< CPU has MOVRS (move from shared memory).
kMPX, //!< CPU has MPX (memory protection extensions).
kMSR, //!< CPU has MSR (RDMSR/WRMSR instructions).
kMSRLIST, //!< CPU has MSRLIST.
kMSR_IMM, //!< CPU has MSR_IMM (RDMSR/WRMSR immediate encoding).
kMSSE, //!< CPU has MSSE (misaligned SSE support).
kOSXSAVE, //!< CPU has OSXSAVE (XSAVE enabled by OS).
kOSPKE, //!< CPU has OSPKE (PKE enabled by OS).
kPCLMULQDQ, //!< CPU has PCLMULQDQ (packed carry-less multiplication).
kPCONFIG, //!< CPU has PCONFIG (PCONFIG instruction).
kPOPCNT, //!< CPU has POPCNT (POPCNT instruction).
kPREFETCHI, //!< CPU has PREFETCHI.
@@ -294,54 +248,103 @@ public:
kRDSEED, //!< CPU has RDSEED (RDSEED instruction).
kRDTSC, //!< CPU has RDTSC.
kRDTSCP, //!< CPU has RDTSCP.
kRTM, //!< CPU has RTM.
kRTM, //!< CPU has RTM (RTM instructions - deprecated).
kSEAM, //!< CPU has SEAM.
kSERIALIZE, //!< CPU has SERIALIZE.
kSEV, //!< CPU has SEV (secure encrypted virtualization).
kSEV_ES, //!< CPU has SEV_ES (SEV encrypted state).
kSEV_SNP, //!< CPU has SEV_SNP (SEV secure nested paging).
kSHA, //!< CPU has SHA (SHA-1 and SHA-256 instructions).
kSHA512, //!< CPU has SHA512 (SHA-512 instructions).
kSKINIT, //!< CPU has SKINIT (SKINIT/STGI instructions) {AMD}.
kSM3, //!< CPU has SM3 (SM3 hash extensions).
kSM4, //!< CPU has SM4 (SM4 cipher extensions).
kSMAP, //!< CPU has SMAP (supervisor-mode access prevention).
kSME, //!< CPU has SME (secure memory encryption).
kSMEP, //!< CPU has SMEP (supervisor-mode execution prevention).
kSMX, //!< CPU has SMX (safer mode extensions).
kSSE, //!< CPU has SSE (SSE instructions).
kSSE2, //!< CPU has SSE2 (SSE2 instructions).
kSSE3, //!< CPU has SSE3 (SSE3 instructions).
kSSE4_1, //!< CPU has SSE4.1 (SSE4.1 instructions).
kSSE4_2, //!< CPU has SSE4.2 (SSE4.2 instructions).
kSSE4A, //!< CPU has SSE4A (SSE4.A instructions) {AMD} (deprecated).
kSSSE3, //!< CPU has SSSE3 (SSSE3 instructions).
kSVM, //!< CPU has SVM (virtualization) {AMD}.
kTBM, //!< CPU has TBM (trailing bit manipulation) {AMD}.
kTSE, //!< CPU has TSE.
kTSX, //!< CPU has TSX.
kTSXLDTRK, //!< CPU has TSXLDTRK.
kUINTR, //!< CPU has UINTR (user interrupts).
kVAES, //!< CPU has VAES (vector AES 256|512 bit support).
kVMX, //!< CPU has VMX (virtualization) {INTEL}.
kVPCLMULQDQ, //!< CPU has VPCLMULQDQ (vector PCLMULQDQ 256|512-bit support).
kWAITPKG, //!< CPU has WAITPKG (UMONITOR, UMWAIT, TPAUSE).
kWBNOINVD, //!< CPU has WBNOINVD.
kWRMSRNS, //!< CPU has WRMSRNS.
kXOP, //!< CPU has XOP (XOP instructions) {AMD} (deprecated).
kXSAVE, //!< CPU has XSAVE.
kXSAVEC, //!< CPU has XSAVEC.
kXSAVEOPT, //!< CPU has XSAVEOPT.
kXSAVES, //!< CPU has XSAVES.
kFPU, //!< CPU has FPU (FPU support).
kMMX, //!< CPU has MMX (MMX base instructions) (deprecated).
kMMX2, //!< CPU has MMX2 (MMX2 extensions or initial SSE extensions) (deprecated).
k3DNOW, //!< CPU has 3DNOW (3DNOW base instructions) {AMD} (deprecated).
k3DNOW2, //!< CPU has 3DNOW2 (enhanced 3DNOW) {AMD} (deprecated).
kGEODE, //!< CPU has GEODE extensions (GEODE 3DNOW additions) (deprecated).
kSSE, //!< CPU has SSE (SSE instructions).
kSSE2, //!< CPU has SSE2 (SSE2 instructions).
kSSE3, //!< CPU has SSE3 (SSE3 instructions).
kSSSE3, //!< CPU has SSSE3 (SSSE3 instructions).
kSSE4_1, //!< CPU has SSE4.1 (SSE4.1 instructions).
kSSE4_2, //!< CPU has SSE4.2 (SSE4.2 instructions).
kSSE4A, //!< CPU has SSE4A (SSE4.A instructions) {AMD} (deprecated).
kPCLMULQDQ, //!< CPU has PCLMULQDQ (packed carry-less multiplication).
kAVX, //!< CPU has AVX (advanced vector extensions).
kAVX2, //!< CPU has AVX2 (advanced vector extensions 2).
kAVX_IFMA, //!< CPU has AVX_IFMA (AVX/VEX encoding of vpmadd52huq/vpmadd52luq).
kAVX_NE_CONVERT, //!< CPU has AVX_NE_CONVERT.
kAVX_VNNI, //!< CPU has AVX_VNNI (AVX/VEX encoding of vpdpbusd/vpdpbusds/vpdpwssd/vpdpwssds).
kAVX_VNNI_INT16, //!< CPU has AVX_VNNI_INT16.
kAVX_VNNI_INT8, //!< CPU has AVX_VNNI_INT8.
kF16C, //!< CPU has F16C (AVX FP16 conversion instructions).
kFMA, //!< CPU has FMA (AVX fused-multiply-add - 3 operand form).
kFMA4, //!< CPU has FMA4 (AVX fused-multiply-add - 4 operand form) (deprecated).
kXOP, //!< CPU has XOP (XOP instructions) {AMD} (deprecated).
kAVX512_BF16, //!< CPU has AVX512_BF16 (AVX512 BFLOAT16 support instructions).
kAVX512_BITALG, //!< CPU has AVX512_BITALG (AVX512 VPOPCNT[B|W] and VPSHUFBITQMB instructions).
kAVX512_BW, //!< CPU has AVX512_BW (AVX512 integer BYTE|WORD instructions).
kAVX512_CD, //!< CPU has AVX512_CD (AVX512 conflict detection DWORD|QWORD instructions).
kAVX512_DQ, //!< CPU has AVX512_DQ (AVX512 integer DWORD|QWORD instructions).
kAVX512_F, //!< CPU has AVX512_F (AVX512 foundation).
kAVX512_FP16, //!< CPU has AVX512_FP16 (AVX512 FP16 instructions).
kAVX512_IFMA, //!< CPU has AVX512_IFMA (AVX512 integer fused-multiply-add using 52-bit precision).
kAVX512_VBMI, //!< CPU has AVX512_VBMI (AVX512 vector byte manipulation instructions).
kAVX512_VBMI2, //!< CPU has AVX512_VBMI2 (AVX512 vector byte manipulation instructions v2).
kAVX512_VL, //!< CPU has AVX512_VL (AVX512 vector length extensions).
kAVX512_VNNI, //!< CPU has AVX512_VNNI (AVX512 vector neural network instructions).
kAVX512_VP2INTERSECT, //!< CPU has AVX512_VP2INTERSECT
kAVX512_VPOPCNTDQ, //!< CPU has AVX512_VPOPCNTDQ (AVX512 VPOPCNT[D|Q] instructions).
kAESNI, //!< CPU has AESNI (AES encode/decode instructions).
kGFNI, //!< CPU has GFNI (galois field instructions).
kSHA, //!< CPU has SHA (SHA-1 and SHA-256 instructions).
kSHA512, //!< CPU has SHA512 (SHA-512 instructions).
kSM3, //!< CPU has SM3 (SM3 hash extensions).
kSM4, //!< CPU has SM4 (SM4 cipher extensions).
kVAES, //!< CPU has VAES (vector AES 256|512 bit support).
kVPCLMULQDQ, //!< CPU has VPCLMULQDQ (vector PCLMULQDQ 256|512-bit support).
kKL, //!< CPU has KL (Key Locker).
kAESKLE, //!< CPU has AESKLE (AESKLE).
kAESKLEWIDE_KL, //!< CPU has AESKLE+WIDEKL+KL (AESKLE & WIDEKL instructions and KL enabled)
kAVX10_1, //!< CPU has AVX10.1/512 (AVX10.1 with 512-bit vectors).
kAVX10_2, //!< CPU has AVX10.2/512 (AVX10.2 with 512-bit vectors).
kAMX_AVX512, //!< CPU has AMX_AVX512 (AMX-AVX512 instructions).
kAMX_BF16, //!< CPU has AMX_BF16 (AMX-BF16 instructions).
kAMX_COMPLEX, //!< CPU has AMX_COMPLEX (AMX-COMPLEX instructions).
kAMX_FP16, //!< CPU has AMX_FP16 (AMX-FP16 instructions).
kAMX_FP8, //!< CPU has AMX_FP8 (AMX-FP8 instructions).
kAMX_INT8, //!< CPU has AMX_INT8 (AMX-INT8 instructions).
kAMX_MOVRS, //!< CPU has AMX_MOVRS (AMX-MOVRS instructions).
kAMX_TF32, //!< CPU has AMX_TF32 (AMX-TF32 instructions).
kAMX_TILE, //!< CPU has AMX_TILE (advanced matrix extensions).
kAMX_TRANSPOSE, //!< CPU has AMX_TRANSPOSE (AMX-TRANSPOSE instructions).
// @EnumValuesEnd@
#ifndef ASMJIT_NO_DEPRECATED
kAVX512_CDI = kAVX512_CD,
kAVX512_ERI = kAVX512_ER,
kAVX512_PFI = kAVX512_PF,
#endif
kMaxValue = kXSAVES
kMaxValue = kAMX_TILE
};
#define ASMJIT_X86_FEATURE(FEATURE) \
@@ -350,42 +353,9 @@ public:
ASMJIT_X86_FEATURE(MT)
ASMJIT_X86_FEATURE(NX)
ASMJIT_X86_FEATURE(3DNOW)
ASMJIT_X86_FEATURE(3DNOW2)
ASMJIT_X86_FEATURE(ADX)
ASMJIT_X86_FEATURE(AESNI)
ASMJIT_X86_FEATURE(ALTMOVCR8)
ASMJIT_X86_FEATURE(AMX_BF16)
ASMJIT_X86_FEATURE(AMX_COMPLEX)
ASMJIT_X86_FEATURE(AMX_FP16)
ASMJIT_X86_FEATURE(AMX_INT8)
ASMJIT_X86_FEATURE(AMX_TILE)
ASMJIT_X86_FEATURE(APX_F)
ASMJIT_X86_FEATURE(AVX)
ASMJIT_X86_FEATURE(AVX2)
ASMJIT_X86_FEATURE(AVX512_4FMAPS)
ASMJIT_X86_FEATURE(AVX512_4VNNIW)
ASMJIT_X86_FEATURE(AVX512_BF16)
ASMJIT_X86_FEATURE(AVX512_BITALG)
ASMJIT_X86_FEATURE(AVX512_BW)
ASMJIT_X86_FEATURE(AVX512_CD)
ASMJIT_X86_FEATURE(AVX512_DQ)
ASMJIT_X86_FEATURE(AVX512_ER)
ASMJIT_X86_FEATURE(AVX512_F)
ASMJIT_X86_FEATURE(AVX512_FP16)
ASMJIT_X86_FEATURE(AVX512_IFMA)
ASMJIT_X86_FEATURE(AVX512_PF)
ASMJIT_X86_FEATURE(AVX512_VBMI)
ASMJIT_X86_FEATURE(AVX512_VBMI2)
ASMJIT_X86_FEATURE(AVX512_VL)
ASMJIT_X86_FEATURE(AVX512_VNNI)
ASMJIT_X86_FEATURE(AVX512_VP2INTERSECT)
ASMJIT_X86_FEATURE(AVX512_VPOPCNTDQ)
ASMJIT_X86_FEATURE(AVX_IFMA)
ASMJIT_X86_FEATURE(AVX_NE_CONVERT)
ASMJIT_X86_FEATURE(AVX_VNNI)
ASMJIT_X86_FEATURE(AVX_VNNI_INT16)
ASMJIT_X86_FEATURE(AVX_VNNI_INT8)
ASMJIT_X86_FEATURE(BMI)
ASMJIT_X86_FEATURE(BMI2)
ASMJIT_X86_FEATURE(CET_IBT)
@@ -402,10 +372,6 @@ public:
ASMJIT_X86_FEATURE(ENCLV)
ASMJIT_X86_FEATURE(ENQCMD)
ASMJIT_X86_FEATURE(ERMS)
ASMJIT_X86_FEATURE(F16C)
ASMJIT_X86_FEATURE(FMA)
ASMJIT_X86_FEATURE(FMA4)
ASMJIT_X86_FEATURE(FPU)
ASMJIT_X86_FEATURE(FSGSBASE)
ASMJIT_X86_FEATURE(FSRM)
ASMJIT_X86_FEATURE(FSRC)
@@ -413,9 +379,6 @@ public:
ASMJIT_X86_FEATURE(FXSR)
ASMJIT_X86_FEATURE(FXSROPT)
ASMJIT_X86_FEATURE(FZRM)
ASMJIT_X86_FEATURE(GEODE)
ASMJIT_X86_FEATURE(GFNI)
ASMJIT_X86_FEATURE(HLE)
ASMJIT_X86_FEATURE(HRESET)
ASMJIT_X86_FEATURE(I486)
ASMJIT_X86_FEATURE(INVLPGB)
@@ -424,20 +387,19 @@ public:
ASMJIT_X86_FEATURE(LWP)
ASMJIT_X86_FEATURE(LZCNT)
ASMJIT_X86_FEATURE(MCOMMIT)
ASMJIT_X86_FEATURE(MMX)
ASMJIT_X86_FEATURE(MMX2)
ASMJIT_X86_FEATURE(MONITOR)
ASMJIT_X86_FEATURE(MONITORX)
ASMJIT_X86_FEATURE(MOVBE)
ASMJIT_X86_FEATURE(MOVDIR64B)
ASMJIT_X86_FEATURE(MOVDIRI)
ASMJIT_X86_FEATURE(MOVRS)
ASMJIT_X86_FEATURE(MPX)
ASMJIT_X86_FEATURE(MSR)
ASMJIT_X86_FEATURE(MSRLIST)
ASMJIT_X86_FEATURE(MSR_IMM)
ASMJIT_X86_FEATURE(MSSE)
ASMJIT_X86_FEATURE(OSXSAVE)
ASMJIT_X86_FEATURE(OSPKE)
ASMJIT_X86_FEATURE(PCLMULQDQ)
ASMJIT_X86_FEATURE(PCONFIG)
ASMJIT_X86_FEATURE(POPCNT)
ASMJIT_X86_FEATURE(PREFETCHI)
@@ -458,46 +420,93 @@ public:
ASMJIT_X86_FEATURE(SEV)
ASMJIT_X86_FEATURE(SEV_ES)
ASMJIT_X86_FEATURE(SEV_SNP)
ASMJIT_X86_FEATURE(SHA)
ASMJIT_X86_FEATURE(SKINIT)
ASMJIT_X86_FEATURE(SMAP)
ASMJIT_X86_FEATURE(SMEP)
ASMJIT_X86_FEATURE(SMX)
ASMJIT_X86_FEATURE(SSE)
ASMJIT_X86_FEATURE(SSE2)
ASMJIT_X86_FEATURE(SSE3)
ASMJIT_X86_FEATURE(SSE4_1)
ASMJIT_X86_FEATURE(SSE4_2)
ASMJIT_X86_FEATURE(SSE4A)
ASMJIT_X86_FEATURE(SSSE3)
ASMJIT_X86_FEATURE(SVM)
ASMJIT_X86_FEATURE(TBM)
ASMJIT_X86_FEATURE(TSE)
ASMJIT_X86_FEATURE(TSX)
ASMJIT_X86_FEATURE(TSXLDTRK)
ASMJIT_X86_FEATURE(UINTR)
ASMJIT_X86_FEATURE(VAES)
ASMJIT_X86_FEATURE(VMX)
ASMJIT_X86_FEATURE(VPCLMULQDQ)
ASMJIT_X86_FEATURE(WAITPKG)
ASMJIT_X86_FEATURE(WBNOINVD)
ASMJIT_X86_FEATURE(WRMSRNS)
ASMJIT_X86_FEATURE(XOP)
ASMJIT_X86_FEATURE(XSAVE)
ASMJIT_X86_FEATURE(XSAVEC)
ASMJIT_X86_FEATURE(XSAVEOPT)
ASMJIT_X86_FEATURE(XSAVES)
#ifndef ASMJIT_NO_DEPRECATED
ASMJIT_DEPRECATED("Use hasAVX512_CD() instead")
ASMJIT_X86_FEATURE(AVX512_CDI)
ASMJIT_X86_FEATURE(FPU)
ASMJIT_X86_FEATURE(MMX)
ASMJIT_X86_FEATURE(MMX2)
ASMJIT_X86_FEATURE(3DNOW)
ASMJIT_X86_FEATURE(3DNOW2)
ASMJIT_X86_FEATURE(GEODE)
ASMJIT_DEPRECATED("Use hasAVX512_ER() instead")
ASMJIT_X86_FEATURE(AVX512_ERI)
ASMJIT_X86_FEATURE(SSE)
ASMJIT_X86_FEATURE(SSE2)
ASMJIT_X86_FEATURE(SSE3)
ASMJIT_X86_FEATURE(SSSE3)
ASMJIT_X86_FEATURE(SSE4_1)
ASMJIT_X86_FEATURE(SSE4_2)
ASMJIT_X86_FEATURE(SSE4A)
ASMJIT_X86_FEATURE(PCLMULQDQ)
ASMJIT_DEPRECATED("Use hasAVX512_PF() instead")
ASMJIT_X86_FEATURE(AVX512_PFI)
#endif
ASMJIT_X86_FEATURE(AVX)
ASMJIT_X86_FEATURE(AVX2)
ASMJIT_X86_FEATURE(AVX_IFMA)
ASMJIT_X86_FEATURE(AVX_NE_CONVERT)
ASMJIT_X86_FEATURE(AVX_VNNI)
ASMJIT_X86_FEATURE(AVX_VNNI_INT16)
ASMJIT_X86_FEATURE(AVX_VNNI_INT8)
ASMJIT_X86_FEATURE(F16C)
ASMJIT_X86_FEATURE(FMA)
ASMJIT_X86_FEATURE(FMA4)
ASMJIT_X86_FEATURE(XOP)
ASMJIT_X86_FEATURE(AVX512_BF16)
ASMJIT_X86_FEATURE(AVX512_BITALG)
ASMJIT_X86_FEATURE(AVX512_BW)
ASMJIT_X86_FEATURE(AVX512_CD)
ASMJIT_X86_FEATURE(AVX512_DQ)
ASMJIT_X86_FEATURE(AVX512_F)
ASMJIT_X86_FEATURE(AVX512_FP16)
ASMJIT_X86_FEATURE(AVX512_IFMA)
ASMJIT_X86_FEATURE(AVX512_VBMI)
ASMJIT_X86_FEATURE(AVX512_VBMI2)
ASMJIT_X86_FEATURE(AVX512_VL)
ASMJIT_X86_FEATURE(AVX512_VNNI)
ASMJIT_X86_FEATURE(AVX512_VP2INTERSECT)
ASMJIT_X86_FEATURE(AVX512_VPOPCNTDQ)
ASMJIT_X86_FEATURE(AESNI)
ASMJIT_X86_FEATURE(GFNI)
ASMJIT_X86_FEATURE(SHA)
ASMJIT_X86_FEATURE(SHA512)
ASMJIT_X86_FEATURE(SM3)
ASMJIT_X86_FEATURE(SM4)
ASMJIT_X86_FEATURE(VAES)
ASMJIT_X86_FEATURE(VPCLMULQDQ)
ASMJIT_X86_FEATURE(KL)
ASMJIT_X86_FEATURE(AESKLE)
ASMJIT_X86_FEATURE(AESKLEWIDE_KL)
ASMJIT_X86_FEATURE(AVX10_1)
ASMJIT_X86_FEATURE(AVX10_2)
ASMJIT_X86_FEATURE(AMX_AVX512)
ASMJIT_X86_FEATURE(AMX_BF16)
ASMJIT_X86_FEATURE(AMX_COMPLEX)
ASMJIT_X86_FEATURE(AMX_FP16)
ASMJIT_X86_FEATURE(AMX_FP8)
ASMJIT_X86_FEATURE(AMX_INT8)
ASMJIT_X86_FEATURE(AMX_MOVRS)
ASMJIT_X86_FEATURE(AMX_TF32)
ASMJIT_X86_FEATURE(AMX_TILE)
ASMJIT_X86_FEATURE(AMX_TRANSPOSE)
#undef ASMJIT_X86_FEATURE
};
@@ -1032,11 +1041,6 @@ public:
//! Tests whether this CPU features matches `other`.
ASMJIT_INLINE_NODEBUG bool equals(const CpuFeatures& other) const noexcept { return _data.equals(other._data); }
#if !defined(ASMJIT_NO_DEPRECATED)
ASMJIT_DEPRECATED("Use CpuFeatures::equals() instead")
ASMJIT_INLINE_NODEBUG bool eq(const CpuFeatures& other) const noexcept { return equals(other); }
#endif // !ASMJIT_NO_DEPRECATED
//! \}
};

25
src/asmjit/core/formatter.h
View File

@@ -26,20 +26,25 @@ enum class FormatFlags : uint32_t {
//! No formatting flags.
kNone = 0u,
//! Show also binary form of each logged instruction (Assembler).
//! Show also a binary representation of each logged instruction (Assembler).
kMachineCode = 0x00000001u,
//! Show aliases of some instructions that have them.
//!
//! This option is now mostly for x86/x64 to show aliases of instructions such as `cmov<cc>`, `j<cc>`, `set<cc>`,
//! etc...
kShowAliases = 0x00000008u,
//! Show a text explanation of some immediate values.
kExplainImms = 0x00000002u,
kExplainImms = 0x00000010u,
//! Use hexadecimal notation of immediate values.
kHexImms = 0x00000004u,
kHexImms = 0x00000020u,
//! Use hexadecimal notation of addresses and offsets in addresses.
kHexOffsets = 0x00000008u,
//! Show casts between virtual register types (Compiler output).
kRegCasts = 0x00000010u,
//! Show positions associated with nodes (Compiler output).
kPositions = 0x00000020u,
//! Always format a register type (Compiler output).
kRegType = 0x00000040u
kHexOffsets = 0x00000040u,
//! Show casts between virtual register types (Compiler).
kRegCasts = 0x00000100u,
//! Show positions associated with nodes (Compiler).
kPositions = 0x00000200u,
//! Always format a register type (Compiler).
kRegType = 0x00000400u
};
ASMJIT_DEFINE_ENUM_FLAGS(FormatFlags)

22
src/asmjit/core/func.h
View File

@@ -95,15 +95,6 @@ enum class CallConvId : uint8_t {
//! Maximum value of `CallConvId`.
kMaxValue = kX64Windows
// Deprecated Aliases
// ------------------
#if !defined(ASMJIT_NO_DEPRECATED)
,
kNone = kCDecl,
kHost = kCDecl
#endif // !ASMJIT_NO_DEPRECATED
};
//! Strategy used by calling conventions to assign registers to function arguments.
@@ -536,19 +527,6 @@ struct FuncSignature {
//! \}
};
#if !defined(ASMJIT_NO_DEPRECATED)
template<typename... RetValueAndArgs>
class FuncSignatureT : public FuncSignature {
public:
ASMJIT_DEPRECATED("Use FuncSignature::build<RetValueAndArgs>() instead")
ASMJIT_INLINE_NODEBUG constexpr FuncSignatureT(CallConvId ccId = CallConvId::kCDecl, uint32_t vaIndex = kNoVarArgs) noexcept
: FuncSignature(ccId, vaIndex, (TypeId(TypeUtils::TypeIdOfT<RetValueAndArgs>::kTypeId))... ) {}
};
ASMJIT_DEPRECATED("Use FuncSignature instead of FuncSignatureBuilder")
typedef FuncSignature FuncSignatureBuilder;
#endif // !ASMJIT_NO_DEPRECATED
//! Argument or return value (or its part) as defined by `FuncSignature`, but with register or stack address
//! (and other metadata) assigned.
struct FuncValue {

42
src/asmjit/core/inst.cpp
View File

@@ -21,15 +21,17 @@ ASMJIT_BEGIN_NAMESPACE
// ===========================
#ifndef ASMJIT_NO_TEXT
Error InstAPI::instIdToString(Arch arch, InstId instId, String& output) noexcept {
Error InstAPI::instIdToString(Arch arch, InstId instId, InstStringifyOptions options, String& output) noexcept {
#if !defined(ASMJIT_NO_X86)
if (Environment::isFamilyX86(arch))
return x86::InstInternal::instIdToString(instId, output);
if (Environment::isFamilyX86(arch)) {
return x86::InstInternal::instIdToString(instId, options, output);
}
#endif
#if !defined(ASMJIT_NO_AARCH64)
if (Environment::isFamilyAArch64(arch))
return a64::InstInternal::instIdToString(instId, output);
if (Environment::isFamilyAArch64(arch)) {
return a64::InstInternal::instIdToString(instId, options, output);
}
#endif
return DebugUtils::errored(kErrorInvalidArch);
@@ -37,13 +39,15 @@ Error InstAPI::instIdToString(Arch arch, InstId instId, String& output) noexcept
InstId InstAPI::stringToInstId(Arch arch, const char* s, size_t len) noexcept {
#if !defined(ASMJIT_NO_X86)
if (Environment::isFamilyX86(arch))
if (Environment::isFamilyX86(arch)) {
return x86::InstInternal::stringToInstId(s, len);
}
#endif
#if !defined(ASMJIT_NO_AARCH64)
if (Environment::isFamilyAArch64(arch))
if (Environment::isFamilyAArch64(arch)) {
return a64::InstInternal::stringToInstId(s, len);
}
#endif
return 0;
@@ -57,16 +61,19 @@ InstId InstAPI::stringToInstId(Arch arch, const char* s, size_t len) noexcept {
Error InstAPI::validate(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, ValidationFlags validationFlags) noexcept {
#if !defined(ASMJIT_NO_X86)
if (Environment::isFamilyX86(arch)) {
if (arch == Arch::kX86)
if (arch == Arch::kX86) {
return x86::InstInternal::validateX86(inst, operands, opCount, validationFlags);
else
}
else {
return x86::InstInternal::validateX64(inst, operands, opCount, validationFlags);
}
}
#endif
#if !defined(ASMJIT_NO_AARCH64)
if (Environment::isFamilyAArch64(arch))
if (Environment::isFamilyAArch64(arch)) {
return a64::InstInternal::validate(inst, operands, opCount, validationFlags);
}
#endif
return DebugUtils::errored(kErrorInvalidArch);
@@ -78,17 +85,20 @@ Error InstAPI::validate(Arch arch, const BaseInst& inst, const Operand_* operand
#ifndef ASMJIT_NO_INTROSPECTION
Error InstAPI::queryRWInfo(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, InstRWInfo* out) noexcept {
if (ASMJIT_UNLIKELY(opCount > Globals::kMaxOpCount))
if (ASMJIT_UNLIKELY(opCount > Globals::kMaxOpCount)) {
return DebugUtils::errored(kErrorInvalidArgument);
}
#if !defined(ASMJIT_NO_X86)
if (Environment::isFamilyX86(arch))
if (Environment::isFamilyX86(arch)) {
return x86::InstInternal::queryRWInfo(arch, inst, operands, opCount, out);
}
#endif
#if !defined(ASMJIT_NO_AARCH64)
if (Environment::isFamilyAArch64(arch))
if (Environment::isFamilyAArch64(arch)) {
return a64::InstInternal::queryRWInfo(inst, operands, opCount, out);
}
#endif
return DebugUtils::errored(kErrorInvalidArch);
@@ -101,13 +111,15 @@ Error InstAPI::queryRWInfo(Arch arch, const BaseInst& inst, const Operand_* oper
#ifndef ASMJIT_NO_INTROSPECTION
Error InstAPI::queryFeatures(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, CpuFeatures* out) noexcept {
#if !defined(ASMJIT_NO_X86)
if (Environment::isFamilyX86(arch))
if (Environment::isFamilyX86(arch)) {
return x86::InstInternal::queryFeatures(arch, inst, operands, opCount, out);
}
#endif
#if !defined(ASMJIT_NO_AARCH64)
if (Environment::isFamilyAArch64(arch))
if (Environment::isFamilyAArch64(arch)) {
return a64::InstInternal::queryFeatures(inst, operands, opCount, out);
}
#endif
return DebugUtils::errored(kErrorInvalidArch);

24
src/asmjit/core/inst.h
View File

@@ -201,6 +201,21 @@ enum class InstSameRegHint : uint8_t {
kWO = 2
};
//! Options that can be used when converting instruction IDs to strings.
enum class InstStringifyOptions : uint32_t {
//! No options.
kNone = 0x00000000u,
//! Stringify a full instruction name with known aliases.
//!
//! This option is designed for architectures where instruction aliases are common, for example X86, and where
//! multiple aliases can be used in assembly code to distinguish between intention - for example instructions
//! such as JZ and JE are the same, but the first is used in a context of equality to zero, and the second is
//! used when two values equal (for example JE next to CMP).
kAliases = 0x00000001u
};
ASMJIT_DEFINE_ENUM_FLAGS(InstStringifyOptions)
//! Instruction id, options, and extraReg in a single structure. This structure exists mainly to simplify analysis
//! and validation API that requires `BaseInst` and `Operand[]` array.
class BaseInst {
@@ -769,11 +784,16 @@ ASMJIT_DEFINE_ENUM_FLAGS(ValidationFlags)
namespace InstAPI {
#ifndef ASMJIT_NO_TEXT
//! Appends the name of the instruction specified by `instId` and `instOptions` into the `output` string.
//! Appends the name of the instruction specified by `instId` and `options` into the `output` string.
//!
//! \note Instruction options would only affect instruction prefix & suffix, other options would be ignored.
//! If `instOptions` is zero then only raw instruction name (without any additional text) will be appended.
ASMJIT_API Error instIdToString(Arch arch, InstId instId, String& output) noexcept;
ASMJIT_API Error instIdToString(Arch arch, InstId instId, InstStringifyOptions options, String& output) noexcept;
ASMJIT_DEPRECATED("Use `instIdToString()` with `InstStringifyOptions` parameter")
static inline Error instIdToString(Arch arch, InstId instId, String& output) noexcept {
return instIdToString(arch, instId, InstStringifyOptions::kNone, output);
}
//! Parses an instruction name in the given string `s`. Length is specified by `len` argument, which can be
//! `SIZE_MAX` if `s` is known to be null terminated.

79
src/asmjit/core/instdb.cpp
View File

@@ -17,11 +17,14 @@ static ASMJIT_FORCE_INLINE char decode5BitChar(uint32_t c) noexcept {
return char(base + c);
}
static ASMJIT_FORCE_INLINE size_t decodeToBuffer(char nameOut[kBufferSize], uint32_t nameValue, const char* stringTable) noexcept {
static ASMJIT_FORCE_INLINE size_t decodeToBuffer(char nameOut[kBufferSize], uint32_t nameValue, InstStringifyOptions options, const char* stringTable) noexcept {
size_t i;
if (nameValue & 0x80000000u) {
// Small string of 5-bit characters.
//
// NOTE: Small string optimization never provides additional
// aliases formatting, so we don't have to consider `options`.
for (i = 0; i < 6; i++, nameValue >>= 5) {
uint32_t c = nameValue & 0x1F;
if (c == 0)
@@ -37,52 +40,61 @@ static ASMJIT_FORCE_INLINE size_t decodeToBuffer(char nameOut[kBufferSize], uint
size_t suffixBase = (nameValue >> 16) & 0xFFFu;
size_t suffixSize = (nameValue >> 28) & 0x7u;
for (i = 0; i < prefixSize; i++)
if (Support::test(options, InstStringifyOptions::kAliases) && suffixBase == 0xFFFu) {
// Alias formatting immediately follows the instruction name in string table.
// The first character specifies the length and then string data follows.
prefixBase += prefixSize;
prefixSize = uint8_t(stringTable[prefixBase]);
ASMJIT_ASSERT(prefixSize <= kBufferSize);
prefixBase += 1; // Skip the byte that specifies the length of a formatted alias.
}
for (i = 0; i < prefixSize; i++) {
nameOut[i] = stringTable[prefixBase + i];
}
char* suffixOut = nameOut + prefixSize;
for (i = 0; i < suffixSize; i++)
for (i = 0; i < suffixSize; i++) {
suffixOut[i] = stringTable[suffixBase + i];
}
return prefixSize + suffixSize;
}
}
Error decode(String& output, uint32_t nameValue, const char* stringTable) noexcept {
Error decode(uint32_t nameValue, InstStringifyOptions options, const char* stringTable, String& output) noexcept {
char nameData[kBufferSize];
size_t nameSize = decodeToBuffer(nameData, nameValue, stringTable);
size_t nameSize = decodeToBuffer(nameData, nameValue, options, stringTable);
return output.append(nameData, nameSize);
}
InstId find(const char* s, size_t len, const InstNameIndex& nameIndex, const uint32_t* nameTable, const char* stringTable) noexcept {
if (ASMJIT_UNLIKELY(!s))
return BaseInst::kIdNone;
InstId findInstruction(const char* s, size_t len, const uint32_t* nameTable, const char* stringTable, const InstNameIndex& nameIndex) noexcept {
ASMJIT_ASSERT(s != nullptr);
ASMJIT_ASSERT(len > 0u);
if (len == SIZE_MAX)
len = strlen(s);
if (ASMJIT_UNLIKELY(len == 0 || len > nameIndex.maxNameLength))
return BaseInst::kIdNone;
uint32_t prefix = uint32_t(s[0]) - 'a';
if (ASMJIT_UNLIKELY(prefix > 'z' - 'a'))
uint32_t prefix = uint32_t(s[0]) - uint32_t('a');
if (ASMJIT_UNLIKELY(prefix > uint32_t('z') - uint32_t('a'))) {
return BaseInst::kIdNone;
}
size_t base = nameIndex.data[prefix].start;
size_t end = nameIndex.data[prefix].end;
if (ASMJIT_UNLIKELY(!base))
if (ASMJIT_UNLIKELY(!base)) {
return BaseInst::kIdNone;
}
char nameData[kBufferSize];
for (size_t lim = end - base; lim != 0; lim >>= 1) {
size_t instId = base + (lim >> 1);
size_t nameSize = decodeToBuffer(nameData, nameTable[instId], stringTable);
size_t nameSize = decodeToBuffer(nameData, nameTable[instId], InstStringifyOptions::kNone, stringTable);
int result = Support::compareStringViews(s, len, nameData, nameSize);
if (result < 0)
if (result < 0) {
continue;
}
if (result > 0) {
base = instId + 1;
@@ -96,6 +108,35 @@ InstId find(const char* s, size_t len, const InstNameIndex& nameIndex, const uin
return BaseInst::kIdNone;
}
uint32_t findAlias(const char* s, size_t len, const uint32_t* nameTable, const char* stringTable, uint32_t aliasNameCount) noexcept {
ASMJIT_ASSERT(s != nullptr);
ASMJIT_ASSERT(len > 0u);
size_t base = 0;
char nameData[kBufferSize];
for (size_t lim = size_t(aliasNameCount) - base; lim != 0; lim >>= 1) {
size_t index = base + (lim >> 1);
size_t nameSize = decodeToBuffer(nameData, nameTable[index], InstStringifyOptions::kNone, stringTable);
int result = Support::compareStringViews(s, len, nameData, nameSize);
if (result < 0) {
continue;
}
if (result > 0) {
base = index + 1;
lim--;
continue;
}
return uint32_t(index);
}
return Globals::kInvalidId;
}
} // {InstNameUtils}
ASMJIT_END_NAMESPACE

5
src/asmjit/core/instdb_p.h
View File

@@ -27,8 +27,9 @@ struct InstNameIndex {
namespace InstNameUtils {
Error decode(String& output, uint32_t nameValue, const char* stringTable) noexcept;
InstId find(const char* s, size_t len, const InstNameIndex& nameIndex, const uint32_t* nameTable, const char* stringTable) noexcept;
Error decode(uint32_t nameValue, InstStringifyOptions options, const char* stringTable, String& output) noexcept;
InstId findInstruction(const char* s, size_t len, const uint32_t* nameTable, const char* stringTable, const InstNameIndex& nameIndex) noexcept;
uint32_t findAlias(const char* s, size_t len, const uint32_t* nameTable, const char* stringTable, uint32_t aliasNameCount) noexcept;
} // {InstNameUtils}

29
src/asmjit/core/jitallocator.h
View File

@@ -323,35 +323,6 @@ public:
//! If the pointer is matched, the function returns `kErrorOk` and fills `out` with the corresponding span.
ASMJIT_API Error query(Span& out, void* rx) const noexcept;
#if !defined(ASMJIT_NO_DEPRECATED)
//! Allocates a new memory block of the requested `size`.
ASMJIT_DEPRECATED("Use alloc(Span& out, size_t size) instead")
ASMJIT_FORCE_INLINE Error alloc(void** rxPtrOut, void** rwPtrOut, size_t size) noexcept {
Span span;
Error err = alloc(span, size);
*rwPtrOut = span.rw();
*rxPtrOut = span.rx();
return err;
}
ASMJIT_DEPRECATED("Use shrink(Span& span, size_t newSize) instead")
ASMJIT_FORCE_INLINE Error shrink(void* rxPtr, size_t newSize) noexcept {
Span span;
ASMJIT_PROPAGATE(query(span, rxPtr));
return (span.size() > newSize) ? shrink(span, newSize) : Error(kErrorOk);
}
ASMJIT_DEPRECATED("Use query(Span& out, void* rx) instead")
ASMJIT_FORCE_INLINE Error query(void* rxPtr, void** rxPtrOut, void** rwPtrOut, size_t* sizeOut) const noexcept {
Span span;
Error err = query(span, rxPtr);
*rxPtrOut = span.rx();
*rwPtrOut = span.rw();
*sizeOut = span.size();
return err;
}
#endif
//! \}
//! \name Write Operations

16
src/asmjit/core/operand.h
View File

@@ -745,17 +745,6 @@ struct Operand_ {
ASMJIT_INLINE_NODEBUG constexpr uint32_t x86RmSize() const noexcept { return _signature.size(); }
//! \}
#if !defined(ASMJIT_NO_DEPRECATED)
ASMJIT_DEPRECATED("hasSize() is no longer portable - use x86RmSize() or x86::Mem::hasSize() instead, if your target is X86/X86_64")
ASMJIT_INLINE_NODEBUG constexpr bool hasSize() const noexcept { return x86RmSize() != 0u; }
ASMJIT_DEPRECATED("hasSize() is no longer portable - use x86RmSize() or x86::Mem::hasSize() instead, if your target is X86/X86_64")
ASMJIT_INLINE_NODEBUG constexpr bool hasSize(uint32_t s) const noexcept { return x86RmSize() == s; }
ASMJIT_DEPRECATED("size() is no longer portable - use x86RmSize() or x86::Mem::size() instead, if your target is X86/X86_64")
ASMJIT_INLINE_NODEBUG constexpr uint32_t size() const noexcept { return _signature.getField<Signature::kSizeMask>(); }
#endif
};
//! Base class representing an operand in AsmJit (default constructed version).
@@ -1665,11 +1654,6 @@ public:
ASMJIT_INLINE_NODEBUG void resetOffsetLo32() noexcept { setOffsetLo32(0); }
//! \}
#if !defined(ASMJIT_NO_DEPRECATED)
ASMJIT_DEPRECATED("setSize() is no longer portable - use setX86RmSize() or x86::Mem::setSize() instead, if your target is X86/X86_64")
ASMJIT_INLINE_NODEBUG void setSize(uint32_t size) noexcept { _signature.setField<Signature::kSizeMask>(size); }
#endif
};
//! Type of the an immediate value.

13
src/asmjit/core/string.h
View File

@@ -55,11 +55,6 @@ union FixedString {
inline bool equals(const char* other) const noexcept { return strcmp(str, other) == 0; }
#if !defined(ASMJIT_NO_DEPRECATED)
ASMJIT_DEPRECATED("Use FixedString::equals() instead")
inline bool eq(const char* other) const noexcept { return equals(other); }
#endif // !ASMJIT_NO_DEPRECATED
//! \}
};
@@ -318,14 +313,6 @@ public:
ASMJIT_API bool equals(const char* other, size_t size = SIZE_MAX) const noexcept;
ASMJIT_INLINE_NODEBUG bool equals(const String& other) const noexcept { return equals(other.data(), other.size()); }
#if !defined(ASMJIT_NO_DEPRECATED)
ASMJIT_DEPRECATED("Use String::equals() instead")
ASMJIT_INLINE_NODEBUG bool eq(const char* other, size_t size = SIZE_MAX) const noexcept { return equals(other, size); }
ASMJIT_DEPRECATED("Use String::equals() instead")
ASMJIT_INLINE_NODEBUG bool eq(const String& other) const noexcept { return equals(other.data(), other.size()); }
#endif // !ASMJIT_NO_DEPRECATED
//! \}
//! \name Internal Functions

5
src/asmjit/core/zonevector.h
View File

@@ -690,11 +690,6 @@ public:
return true;
}
#if !defined(ASMJIT_NO_DEPRECATED)
ASMJIT_DEPRECATED("Use ZoneVector::equals() instead")
ASMJIT_FORCE_INLINE bool eq(const ZoneBitVector& other) const noexcept { return equals(other); }
#endif // !ASMJIT_NO_DEPRECATED
//! \}
//! \name Memory Management

30
src/asmjit/x86/x86assembler.cpp
View File

@@ -2976,13 +2976,6 @@ CaseExtRm:
}
break;
case InstDB::kEncodingVexM_VM:
if (isign3 == ENC_OPS1(Mem)) {
rmRel = &o0;
goto EmitVexEvexM;
}
break;
case InstDB::kEncodingVexMr_Lx:
opcode |= x86OpcodeLBySize(o0.x86RmSize() | o1.x86RmSize());
@@ -3110,28 +3103,6 @@ CaseVexRm:
}
break;
case InstDB::kEncodingVexRm_T1_4X: {
const Operand_& o3 = opExt[EmitterUtils::kOp3];
const Operand_& o4 = opExt[EmitterUtils::kOp4];
const Operand_& o5 = opExt[EmitterUtils::kOp5];
if (Reg::isVec(o0) && Reg::isVec(o1) && Reg::isVec(o2) && Reg::isVec(o3) && Reg::isVec(o4) && o5.isMem()) {
// Registers [o1, o2, o3, o4] must start aligned and must be consecutive.
uint32_t i1 = o1.id();
uint32_t i2 = o2.id();
uint32_t i3 = o3.id();
uint32_t i4 = o4.id();
if (ASMJIT_UNLIKELY((i1 & 0x3) != 0 || i2 != i1 + 1 || i3 != i1 + 2 || i4 != i1 + 3))
goto NotConsecutiveRegs;
opReg = x86PackRegAndVvvvv(o0.id(), i1);
rmRel = &o5;
goto EmitVexEvexM;
}
break;
}
case InstDB::kEncodingVexRmi_Wx:
opcode.addWIf(unsigned(Reg::isGpq(o0)) | unsigned(Reg::isGpq(o1)));
goto CaseVexRmi;
@@ -5000,7 +4971,6 @@ EmitDone:
ERROR_HANDLER(InvalidBroadcast)
ERROR_HANDLER(OperandSizeMismatch)
ERROR_HANDLER(AmbiguousOperandSize)
ERROR_HANDLER(NotConsecutiveRegs)
#undef ERROR_HANDLER
Failed:

50
src/asmjit/x86/x86emitter.h
View File

@@ -580,10 +580,10 @@ public:
ASMJIT_INST_2x(sbb, Sbb, Gp, Imm) // ANY
ASMJIT_INST_2x(sbb, Sbb, Mem, Gp) // ANY
ASMJIT_INST_2x(sbb, Sbb, Mem, Imm) // ANY
ASMJIT_INST_2x(sal, Sal, Gp, Gp_CL) // ANY
ASMJIT_INST_2x(sal, Sal, Mem, Gp_CL) // ANY
ASMJIT_INST_2x(sal, Sal, Gp, Imm) // ANY
ASMJIT_INST_2x(sal, Sal, Mem, Imm) // ANY
ASMJIT_INST_2x(sal, Shl, Gp, Gp_CL) // ANY
ASMJIT_INST_2x(sal, Shl, Mem, Gp_CL) // ANY
ASMJIT_INST_2x(sal, Shl, Gp, Imm) // ANY
ASMJIT_INST_2x(sal, Shl, Mem, Imm) // ANY
ASMJIT_INST_2x(sar, Sar, Gp, Gp_CL) // ANY
ASMJIT_INST_2x(sar, Sar, Mem, Gp_CL) // ANY
ASMJIT_INST_2x(sar, Sar, Gp, Imm) // ANY
@@ -2242,10 +2242,6 @@ public:
ASMJIT_INST_3x(kxord, Kxord, KReg, KReg, KReg) // AVX512_BW
ASMJIT_INST_3x(kxorq, Kxorq, KReg, KReg, KReg) // AVX512_BW
ASMJIT_INST_3x(kxorw, Kxorw, KReg, KReg, KReg) // AVX512_F
ASMJIT_INST_6x(v4fmaddps, V4fmaddps, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz}
ASMJIT_INST_6x(v4fmaddss, V4fmaddss, Xmm, Xmm, Xmm, Xmm, Xmm, Mem) // AVX512_4FMAPS{kz}
ASMJIT_INST_6x(v4fnmaddps, V4fnmaddps, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz}
ASMJIT_INST_6x(v4fnmaddss, V4fnmaddss, Xmm, Xmm, Xmm, Xmm, Xmm, Mem) // AVX512_4FMAPS{kz}
ASMJIT_INST_3x(vaddpd, Vaddpd, Vec, Vec, Vec) // AVX AVX512_F{kz|b64}
ASMJIT_INST_3x(vaddpd, Vaddpd, Vec, Vec, Mem) // AVX AVX512_F{kz|b64}
ASMJIT_INST_3x(vaddps, Vaddps, Vec, Vec, Vec) // AVX AVX512_F{kz|b32}
@@ -2442,10 +2438,6 @@ public:
ASMJIT_INST_4x(vdppd, Vdppd, Vec, Vec, Mem, Imm) // AVX
ASMJIT_INST_4x(vdpps, Vdpps, Vec, Vec, Vec, Imm) // AVX
ASMJIT_INST_4x(vdpps, Vdpps, Vec, Vec, Mem, Imm) // AVX
ASMJIT_INST_2x(vexp2pd, Vexp2pd, Vec, Vec) // AVX512_ER{kz|sae|b64}
ASMJIT_INST_2x(vexp2pd, Vexp2pd, Vec, Mem) // AVX512_ER{kz|sae|b64}
ASMJIT_INST_2x(vexp2ps, Vexp2ps, Vec, Vec) // AVX512_ER{kz|sae|b32}
ASMJIT_INST_2x(vexp2ps, Vexp2ps, Vec, Mem) // AVX512_ER{kz|sae|b32}
ASMJIT_INST_2x(vexpandpd, Vexpandpd, Vec, Vec) // AVX512_F{kz}
ASMJIT_INST_2x(vexpandpd, Vexpandpd, Vec, Mem) // AVX512_F{kz}
ASMJIT_INST_2x(vexpandps, Vexpandps, Vec, Vec) // AVX512_F{kz}
@@ -2612,14 +2604,6 @@ public:
ASMJIT_INST_3x(vgatherdpd, Vgatherdpd, Vec, Mem, Vec) // AVX2
ASMJIT_INST_2x(vgatherdps, Vgatherdps, Vec, Mem) // AVX512_F{k}
ASMJIT_INST_3x(vgatherdps, Vgatherdps, Vec, Mem, Vec) // AVX2
ASMJIT_INST_1x(vgatherpf0dpd, Vgatherpf0dpd, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vgatherpf0dps, Vgatherpf0dps, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vgatherpf0qpd, Vgatherpf0qpd, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vgatherpf0qps, Vgatherpf0qps, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vgatherpf1dpd, Vgatherpf1dpd, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vgatherpf1dps, Vgatherpf1dps, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vgatherpf1qpd, Vgatherpf1qpd, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vgatherpf1qps, Vgatherpf1qps, Mem) // AVX512_PF{k}
ASMJIT_INST_2x(vgatherqpd, Vgatherqpd, Vec, Mem) // AVX512_F{k}
ASMJIT_INST_3x(vgatherqpd, Vgatherqpd, Vec, Mem, Vec) // AVX2
ASMJIT_INST_2x(vgatherqps, Vgatherqps, Vec, Mem) // AVX512_F{k}
@@ -2790,8 +2774,6 @@ public:
ASMJIT_INST_4x(vp2intersectd, Vp2intersectd, KReg, KReg, Vec, Mem) // AVX512_VP2INTERSECT{kz}
ASMJIT_INST_4x(vp2intersectq, Vp2intersectq, KReg, KReg, Vec, Vec) // AVX512_VP2INTERSECT{kz}
ASMJIT_INST_4x(vp2intersectq, Vp2intersectq, KReg, KReg, Vec, Mem) // AVX512_VP2INTERSECT{kz}
ASMJIT_INST_6x(vp4dpwssd, Vp4dpwssd, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz}
ASMJIT_INST_6x(vp4dpwssds, Vp4dpwssds, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz}
ASMJIT_INST_2x(vpabsb, Vpabsb, Vec, Vec) // AVX+ AVX512_BW{kz}
ASMJIT_INST_2x(vpabsb, Vpabsb, Vec, Mem) // AVX+ AVX512_BW{kz}
ASMJIT_INST_2x(vpabsd, Vpabsd, Vec, Vec) // AVX+ AVX512_F{kz}
@@ -3391,14 +3373,6 @@ public:
ASMJIT_INST_3x(vrcp14sd, Vrcp14sd, Xmm, Xmm, Mem) // AVX512_F{kz}
ASMJIT_INST_3x(vrcp14ss, Vrcp14ss, Xmm, Xmm, Xmm) // AVX512_F{kz}
ASMJIT_INST_3x(vrcp14ss, Vrcp14ss, Xmm, Xmm, Mem) // AVX512_F{kz}
ASMJIT_INST_2x(vrcp28pd, Vrcp28pd, Vec, Vec) // AVX512_ER{kz|sae|b64}
ASMJIT_INST_2x(vrcp28pd, Vrcp28pd, Vec, Mem) // AVX512_ER{kz|sae|b64}
ASMJIT_INST_2x(vrcp28ps, Vrcp28ps, Vec, Vec) // AVX512_ER{kz|sae|b32}
ASMJIT_INST_2x(vrcp28ps, Vrcp28ps, Vec, Mem) // AVX512_ER{kz|sae|b32}
ASMJIT_INST_3x(vrcp28sd, Vrcp28sd, Xmm, Xmm, Xmm) // AVX512_ER{kz|sae}
ASMJIT_INST_3x(vrcp28sd, Vrcp28sd, Xmm, Xmm, Mem) // AVX512_ER{kz|sae}
ASMJIT_INST_3x(vrcp28ss, Vrcp28ss, Xmm, Xmm, Xmm) // AVX512_ER{kz|sae}
ASMJIT_INST_3x(vrcp28ss, Vrcp28ss, Xmm, Xmm, Mem) // AVX512_ER{kz|sae}
ASMJIT_INST_2x(vrcpps, Vrcpps, Vec, Vec) // AVX
ASMJIT_INST_2x(vrcpps, Vrcpps, Vec, Mem) // AVX
ASMJIT_INST_3x(vrcpss, Vrcpss, Xmm, Xmm, Xmm) // AVX
@@ -3435,14 +3409,6 @@ public:
ASMJIT_INST_3x(vrsqrt14sd, Vrsqrt14sd, Xmm, Xmm, Mem) // AVX512_F{kz}
ASMJIT_INST_3x(vrsqrt14ss, Vrsqrt14ss, Xmm, Xmm, Xmm) // AVX512_F{kz}
ASMJIT_INST_3x(vrsqrt14ss, Vrsqrt14ss, Xmm, Xmm, Mem) // AVX512_F{kz}
ASMJIT_INST_2x(vrsqrt28pd, Vrsqrt28pd, Vec, Vec) // AVX512_ER{kz|sae|b64}
ASMJIT_INST_2x(vrsqrt28pd, Vrsqrt28pd, Vec, Mem) // AVX512_ER{kz|sae|b64}
ASMJIT_INST_2x(vrsqrt28ps, Vrsqrt28ps, Vec, Vec) // AVX512_ER{kz|sae|b32}
ASMJIT_INST_2x(vrsqrt28ps, Vrsqrt28ps, Vec, Mem) // AVX512_ER{kz|sae|b32}
ASMJIT_INST_3x(vrsqrt28sd, Vrsqrt28sd, Xmm, Xmm, Xmm) // AVX512_ER{kz|sae}
ASMJIT_INST_3x(vrsqrt28sd, Vrsqrt28sd, Xmm, Xmm, Mem) // AVX512_ER{kz|sae}
ASMJIT_INST_3x(vrsqrt28ss, Vrsqrt28ss, Xmm, Xmm, Xmm) // AVX512_ER{kz|sae}
ASMJIT_INST_3x(vrsqrt28ss, Vrsqrt28ss, Xmm, Xmm, Mem) // AVX512_ER{kz|sae}
ASMJIT_INST_2x(vrsqrtps, Vrsqrtps, Vec, Vec) // AVX
ASMJIT_INST_2x(vrsqrtps, Vrsqrtps, Vec, Mem) // AVX
ASMJIT_INST_3x(vrsqrtss, Vrsqrtss, Xmm, Xmm, Xmm) // AVX
@@ -3457,14 +3423,6 @@ public:
ASMJIT_INST_3x(vscalefss, Vscalefss, Xmm, Xmm, Mem) // AVX512_F{kz|er}
ASMJIT_INST_2x(vscatterdpd, Vscatterdpd, Mem, Vec) // AVX512_F{k}
ASMJIT_INST_2x(vscatterdps, Vscatterdps, Mem, Vec) // AVX512_F{k}
ASMJIT_INST_1x(vscatterpf0dpd, Vscatterpf0dpd, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vscatterpf0dps, Vscatterpf0dps, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vscatterpf0qpd, Vscatterpf0qpd, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vscatterpf0qps, Vscatterpf0qps, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vscatterpf1dpd, Vscatterpf1dpd, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vscatterpf1dps, Vscatterpf1dps, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vscatterpf1qpd, Vscatterpf1qpd, Mem) // AVX512_PF{k}
ASMJIT_INST_1x(vscatterpf1qps, Vscatterpf1qps, Mem) // AVX512_PF{k}
ASMJIT_INST_2x(vscatterqpd, Vscatterqpd, Mem, Vec) // AVX512_F{k}
ASMJIT_INST_2x(vscatterqps, Vscatterqps, Mem, Vec) // AVX512_F{k}
ASMJIT_INST_4x(vshuff32x4, Vshuff32x4, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32}

149
src/asmjit/x86/x86formatter.cpp
View File

@@ -210,42 +210,9 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
"None\0"
"MT\0"
"NX\0"
"3DNOW\0"
"3DNOW2\0"
"ADX\0"
"AESNI\0"
"ALTMOVCR8\0"
"AMX_BF16\0"
"AMX_COMPLEX\0"
"AMX_FP16\0"
"AMX_INT8\0"
"AMX_TILE\0"
"APX_F\0"
"AVX\0"
"AVX2\0"
"AVX512_4FMAPS\0"
"AVX512_4VNNIW\0"
"AVX512_BF16\0"
"AVX512_BITALG\0"
"AVX512_BW\0"
"AVX512_CD\0"
"AVX512_DQ\0"
"AVX512_ER\0"
"AVX512_F\0"
"AVX512_FP16\0"
"AVX512_IFMA\0"
"AVX512_PF\0"
"AVX512_VBMI\0"
"AVX512_VBMI2\0"
"AVX512_VL\0"
"AVX512_VNNI\0"
"AVX512_VP2INTERSECT\0"
"AVX512_VPOPCNTDQ\0"
"AVX_IFMA\0"
"AVX_NE_CONVERT\0"
"AVX_VNNI\0"
"AVX_VNNI_INT16\0"
"AVX_VNNI_INT8\0"
"BMI\0"
"BMI2\0"
"CET_IBT\0"
@@ -263,10 +230,6 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
"ENCLV\0"
"ENQCMD\0"
"ERMS\0"
"F16C\0"
"FMA\0"
"FMA4\0"
"FPU\0"
"FSGSBASE\0"
"FSRM\0"
"FSRC\0"
@@ -274,9 +237,6 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
"FXSR\0"
"FXSROPT\0"
"FZRM\0"
"GEODE\0"
"GFNI\0"
"HLE\0"
"HRESET\0"
"I486\0"
"INVLPGB\0"
@@ -285,20 +245,19 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
"LWP\0"
"LZCNT\0"
"MCOMMIT\0"
"MMX\0"
"MMX2\0"
"MONITOR\0"
"MONITORX\0"
"MOVBE\0"
"MOVDIR64B\0"
"MOVDIRI\0"
"MOVRS\0"
"MPX\0"
"MSR\0"
"MSRLIST\0"
"MSR_IMM\0"
"MSSE\0"
"OSXSAVE\0"
"OSPKE\0"
"PCLMULQDQ\0"
"PCONFIG\0"
"POPCNT\0"
"PREFETCHI\0"
@@ -319,52 +278,99 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept
"SEV\0"
"SEV_ES\0"
"SEV_SNP\0"
"SHA\0"
"SHA512\0"
"SKINIT\0"
"SM3\0"
"SM4\0"
"SMAP\0"
"SME\0"
"SMEP\0"
"SMX\0"
"SSE\0"
"SSE2\0"
"SSE3\0"
"SSE4_1\0"
"SSE4_2\0"
"SSE4A\0"
"SSSE3\0"
"SVM\0"
"TBM\0"
"TSE\0"
"TSX\0"
"TSXLDTRK\0"
"UINTR\0"
"VAES\0"
"VMX\0"
"VPCLMULQDQ\0"
"WAITPKG\0"
"WBNOINVD\0"
"WRMSRNS\0"
"XOP\0"
"XSAVE\0"
"XSAVEC\0"
"XSAVEOPT\0"
"XSAVES\0"
"FPU\0"
"MMX\0"
"MMX2\0"
"3DNOW\0"
"3DNOW2\0"
"GEODE\0"
"SSE\0"
"SSE2\0"
"SSE3\0"
"SSSE3\0"
"SSE4_1\0"
"SSE4_2\0"
"SSE4A\0"
"PCLMULQDQ\0"
"AVX\0"
"AVX2\0"
"AVX_IFMA\0"
"AVX_NE_CONVERT\0"
"AVX_VNNI\0"
"AVX_VNNI_INT16\0"
"AVX_VNNI_INT8\0"
"F16C\0"
"FMA\0"
"FMA4\0"
"XOP\0"
"AVX512_BF16\0"
"AVX512_BITALG\0"
"AVX512_BW\0"
"AVX512_CD\0"
"AVX512_DQ\0"
"AVX512_F\0"
"AVX512_FP16\0"
"AVX512_IFMA\0"
"AVX512_VBMI\0"
"AVX512_VBMI2\0"
"AVX512_VL\0"
"AVX512_VNNI\0"
"AVX512_VP2INTERSECT\0"
"AVX512_VPOPCNTDQ\0"
"AESNI\0"
"GFNI\0"
"SHA\0"
"SHA512\0"
"SM3\0"
"SM4\0"
"VAES\0"
"VPCLMULQDQ\0"
"KL\0"
"AESKLE\0"
"AESKLEWIDE_KL\0"
"AVX10_1\0"
"AVX10_2\0"
"AMX_AVX512\0"
"AMX_BF16\0"
"AMX_COMPLEX\0"
"AMX_FP16\0"
"AMX_FP8\0"
"AMX_INT8\0"
"AMX_MOVRS\0"
"AMX_TF32\0"
"AMX_TILE\0"
"AMX_TRANSPOSE\0"
"<Unknown>\0";
static const uint16_t sFeatureIndex[] = {
0, 5, 8, 11, 17, 24, 28, 34, 44, 53, 65, 74, 83, 92, 98, 102, 107, 121, 135,
147, 161, 171, 181, 191, 201, 210, 222, 234, 244, 256, 269, 279, 291, 311,
328, 337, 352, 361, 376, 390, 394, 399, 407, 414, 422, 431, 439, 450, 455,
462, 467, 477, 488, 498, 504, 511, 516, 521, 525, 530, 534, 543, 548, 553,
558, 563, 571, 576, 582, 587, 591, 598, 603, 611, 620, 624, 628, 634, 642,
646, 651, 659, 668, 674, 684, 692, 696, 700, 708, 713, 721, 727, 737, 745,
752, 762, 772, 784, 792, 800, 809, 815, 821, 828, 835, 841, 848, 852, 857,
867, 871, 878, 886, 890, 897, 904, 908, 912, 917, 921, 926, 930, 934, 939,
944, 951, 958, 964, 970, 974, 978, 982, 986, 995, 1001, 1006, 1010, 1021,
1029, 1038, 1046, 1050, 1056, 1063, 1072, 1079
0, 5, 8, 11, 15, 25, 31, 35, 40, 48, 55, 63, 72, 80, 91, 96, 103, 108, 118,
129, 139, 145, 152, 157, 166, 171, 176, 181, 186, 194, 199, 206, 211, 219,
228, 232, 236, 242, 250, 258, 267, 273, 283, 291, 297, 301, 305, 313, 321,
326, 334, 340, 348, 355, 365, 375, 387, 395, 403, 412, 418, 424, 431, 438,
444, 451, 455, 460, 470, 474, 481, 489, 496, 501, 505, 510, 514, 518, 522,
526, 535, 541, 545, 553, 562, 570, 576, 583, 592, 599, 603, 607, 612, 618,
625, 631, 635, 640, 645, 651, 658, 665, 671, 681, 685, 690, 699, 714, 723,
738, 752, 757, 761, 766, 770, 782, 796, 806, 816, 826, 835, 847, 859, 871,
884, 894, 906, 926, 943, 949, 954, 958, 965, 969, 973, 978, 989, 992, 999,
1013, 1021, 1029, 1040, 1049, 1061, 1070, 1078, 1087, 1097, 1106, 1115, 1129
};
// @EnumStringEnd@
@@ -929,7 +935,12 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatInstruction(
}
}
ASMJIT_PROPAGATE(InstInternal::instIdToString(instId, sb));
InstStringifyOptions stringifyOptions =
Support::test(formatFlags, FormatFlags::kShowAliases)
? InstStringifyOptions::kAliases
: InstStringifyOptions::kNone;
ASMJIT_PROPAGATE(InstInternal::instIdToString(instId, stringifyOptions, sb));
}
else {
ASMJIT_PROPAGATE(sb.appendFormat("[InstId=#%u]", unsigned(instId)));

449
src/asmjit/x86/x86globals.h
View File

@@ -203,24 +203,12 @@ namespace Inst {
kIdClwb, //!< Instruction 'clwb' {CLWB}.
kIdClzero, //!< Instruction 'clzero' {CLZERO}.
kIdCmc, //!< Instruction 'cmc'.
kIdCmova, //!< Instruction 'cmova' {CMOV}.
kIdCmovae, //!< Instruction 'cmovae' {CMOV}.
kIdCmovb, //!< Instruction 'cmovb' {CMOV}.
kIdCmovbe, //!< Instruction 'cmovbe' {CMOV}.
kIdCmovc, //!< Instruction 'cmovc' {CMOV}.
kIdCmove, //!< Instruction 'cmove' {CMOV}.
kIdCmovg, //!< Instruction 'cmovg' {CMOV}.
kIdCmovge, //!< Instruction 'cmovge' {CMOV}.
kIdCmovl, //!< Instruction 'cmovl' {CMOV}.
kIdCmovle, //!< Instruction 'cmovle' {CMOV}.
kIdCmovna, //!< Instruction 'cmovna' {CMOV}.
kIdCmovnae, //!< Instruction 'cmovnae' {CMOV}.
kIdCmovnb, //!< Instruction 'cmovnb' {CMOV}.
kIdCmovnbe, //!< Instruction 'cmovnbe' {CMOV}.
kIdCmovnc, //!< Instruction 'cmovnc' {CMOV}.
kIdCmovne, //!< Instruction 'cmovne' {CMOV}.
kIdCmovng, //!< Instruction 'cmovng' {CMOV}.
kIdCmovnge, //!< Instruction 'cmovnge' {CMOV}.
kIdCmovnl, //!< Instruction 'cmovnl' {CMOV}.
kIdCmovnle, //!< Instruction 'cmovnle' {CMOV}.
kIdCmovno, //!< Instruction 'cmovno' {CMOV}.
@@ -229,8 +217,6 @@ namespace Inst {
kIdCmovnz, //!< Instruction 'cmovnz' {CMOV}.
kIdCmovo, //!< Instruction 'cmovo' {CMOV}.
kIdCmovp, //!< Instruction 'cmovp' {CMOV}.
kIdCmovpe, //!< Instruction 'cmovpe' {CMOV}.
kIdCmovpo, //!< Instruction 'cmovpo' {CMOV}.
kIdCmovs, //!< Instruction 'cmovs' {CMOV}.
kIdCmovz, //!< Instruction 'cmovz' {CMOV}.
kIdCmp, //!< Instruction 'cmp'.
@@ -435,26 +421,14 @@ namespace Inst {
kIdIret, //!< Instruction 'iret'.
kIdIretd, //!< Instruction 'iretd'.
kIdIretq, //!< Instruction 'iretq' (X64).
kIdJa, //!< Instruction 'ja'.
kIdJae, //!< Instruction 'jae'.
kIdJb, //!< Instruction 'jb'.
kIdJbe, //!< Instruction 'jbe'.
kIdJc, //!< Instruction 'jc'.
kIdJe, //!< Instruction 'je'.
kIdJecxz, //!< Instruction 'jecxz'.
kIdJg, //!< Instruction 'jg'.
kIdJge, //!< Instruction 'jge'.
kIdJl, //!< Instruction 'jl'.
kIdJle, //!< Instruction 'jle'.
kIdJmp, //!< Instruction 'jmp'.
kIdJna, //!< Instruction 'jna'.
kIdJnae, //!< Instruction 'jnae'.
kIdJnb, //!< Instruction 'jnb'.
kIdJnbe, //!< Instruction 'jnbe'.
kIdJnc, //!< Instruction 'jnc'.
kIdJne, //!< Instruction 'jne'.
kIdJng, //!< Instruction 'jng'.
kIdJnge, //!< Instruction 'jnge'.
kIdJnl, //!< Instruction 'jnl'.
kIdJnle, //!< Instruction 'jnle'.
kIdJno, //!< Instruction 'jno'.
@@ -463,8 +437,6 @@ namespace Inst {
kIdJnz, //!< Instruction 'jnz'.
kIdJo, //!< Instruction 'jo'.
kIdJp, //!< Instruction 'jp'.
kIdJpe, //!< Instruction 'jpe'.
kIdJpo, //!< Instruction 'jpo'.
kIdJs, //!< Instruction 'js'.
kIdJz, //!< Instruction 'jz'.
kIdKaddb, //!< Instruction 'kaddb' {AVX512_DQ}.
@@ -802,7 +774,7 @@ namespace Inst {
kIdRcr, //!< Instruction 'rcr'.
kIdRdfsbase, //!< Instruction 'rdfsbase' {FSGSBASE} (X64).
kIdRdgsbase, //!< Instruction 'rdgsbase' {FSGSBASE} (X64).
kIdRdmsr, //!< Instruction 'rdmsr' {MSR}.
kIdRdmsr, //!< Instruction 'rdmsr' {MSR|MSR_IMM}.
kIdRdpid, //!< Instruction 'rdpid' {RDPID}.
kIdRdpkru, //!< Instruction 'rdpkru' {OSPKE}.
kIdRdpmc, //!< Instruction 'rdpmc'.
@@ -829,7 +801,6 @@ namespace Inst {
kIdRsqrtss, //!< Instruction 'rsqrtss' {SSE}.
kIdRstorssp, //!< Instruction 'rstorssp' {CET_SS}.
kIdSahf, //!< Instruction 'sahf' {LAHFSAHF}.
kIdSal, //!< Instruction 'sal'.
kIdSar, //!< Instruction 'sar'.
kIdSarx, //!< Instruction 'sarx' {BMI2}.
kIdSaveprevssp, //!< Instruction 'saveprevssp' {CET_SS}.
@@ -840,24 +811,12 @@ namespace Inst {
kIdSeamret, //!< Instruction 'seamret' {SEAM}.
kIdSenduipi, //!< Instruction 'senduipi' {UINTR} (X64).
kIdSerialize, //!< Instruction 'serialize' {SERIALIZE}.
kIdSeta, //!< Instruction 'seta'.
kIdSetae, //!< Instruction 'setae'.
kIdSetb, //!< Instruction 'setb'.
kIdSetbe, //!< Instruction 'setbe'.
kIdSetc, //!< Instruction 'setc'.
kIdSete, //!< Instruction 'sete'.
kIdSetg, //!< Instruction 'setg'.
kIdSetge, //!< Instruction 'setge'.
kIdSetl, //!< Instruction 'setl'.
kIdSetle, //!< Instruction 'setle'.
kIdSetna, //!< Instruction 'setna'.
kIdSetnae, //!< Instruction 'setnae'.
kIdSetnb, //!< Instruction 'setnb'.
kIdSetnbe, //!< Instruction 'setnbe'.
kIdSetnc, //!< Instruction 'setnc'.
kIdSetne, //!< Instruction 'setne'.
kIdSetng, //!< Instruction 'setng'.
kIdSetnge, //!< Instruction 'setnge'.
kIdSetnl, //!< Instruction 'setnl'.
kIdSetnle, //!< Instruction 'setnle'.
kIdSetno, //!< Instruction 'setno'.
@@ -866,8 +825,6 @@ namespace Inst {
kIdSetnz, //!< Instruction 'setnz'.
kIdSeto, //!< Instruction 'seto'.
kIdSetp, //!< Instruction 'setp'.
kIdSetpe, //!< Instruction 'setpe'.
kIdSetpo, //!< Instruction 'setpo'.
kIdSets, //!< Instruction 'sets'.
kIdSetssbsy, //!< Instruction 'setssbsy' {CET_SS}.
kIdSetz, //!< Instruction 'setz'.
@@ -952,16 +909,12 @@ namespace Inst {
kIdUnpckhps, //!< Instruction 'unpckhps' {SSE}.
kIdUnpcklpd, //!< Instruction 'unpcklpd' {SSE2}.
kIdUnpcklps, //!< Instruction 'unpcklps' {SSE}.
kIdV4fmaddps, //!< Instruction 'v4fmaddps' {AVX512_4FMAPS}.
kIdV4fmaddss, //!< Instruction 'v4fmaddss' {AVX512_4FMAPS}.
kIdV4fnmaddps, //!< Instruction 'v4fnmaddps' {AVX512_4FMAPS}.
kIdV4fnmaddss, //!< Instruction 'v4fnmaddss' {AVX512_4FMAPS}.
kIdVaddpd, //!< Instruction 'vaddpd' {AVX|AVX512_F+VL}.
kIdVaddph, //!< Instruction 'vaddph' {AVX512_FP16+VL}.
kIdVaddps, //!< Instruction 'vaddps' {AVX|AVX512_F+VL}.
kIdVaddsd, //!< Instruction 'vaddsd' {AVX|AVX512_F}.
kIdVaddsh, //!< Instruction 'vaddsh' {AVX512_FP16}.
kIdVaddss, //!< Instruction 'vaddss' {AVX|AVX512_F}.
kIdVaddsd, //!< Instruction 'vaddsd' {AVX|AVX512_F+VL}.
kIdVaddsh, //!< Instruction 'vaddsh' {AVX512_FP16+VL}.
kIdVaddss, //!< Instruction 'vaddss' {AVX|AVX512_F+VL}.
kIdVaddsubpd, //!< Instruction 'vaddsubpd' {AVX}.
kIdVaddsubps, //!< Instruction 'vaddsubps' {AVX}.
kIdVaesdec, //!< Instruction 'vaesdec' {AVX|AVX512_F+VL & AESNI|VAES}.
@@ -986,27 +939,27 @@ namespace Inst {
kIdVblendvps, //!< Instruction 'vblendvps' {AVX}.
kIdVbroadcastf128, //!< Instruction 'vbroadcastf128' {AVX}.
kIdVbroadcastf32x2, //!< Instruction 'vbroadcastf32x2' {AVX512_DQ+VL}.
kIdVbroadcastf32x4, //!< Instruction 'vbroadcastf32x4' {AVX512_F}.
kIdVbroadcastf32x8, //!< Instruction 'vbroadcastf32x8' {AVX512_DQ}.
kIdVbroadcastf32x4, //!< Instruction 'vbroadcastf32x4' {AVX512_F+VL}.
kIdVbroadcastf32x8, //!< Instruction 'vbroadcastf32x8' {AVX512_DQ+VL}.
kIdVbroadcastf64x2, //!< Instruction 'vbroadcastf64x2' {AVX512_DQ+VL}.
kIdVbroadcastf64x4, //!< Instruction 'vbroadcastf64x4' {AVX512_F}.
kIdVbroadcastf64x4, //!< Instruction 'vbroadcastf64x4' {AVX512_F+VL}.
kIdVbroadcasti128, //!< Instruction 'vbroadcasti128' {AVX2}.
kIdVbroadcasti32x2, //!< Instruction 'vbroadcasti32x2' {AVX512_DQ+VL}.
kIdVbroadcasti32x4, //!< Instruction 'vbroadcasti32x4' {AVX512_F+VL}.
kIdVbroadcasti32x8, //!< Instruction 'vbroadcasti32x8' {AVX512_DQ}.
kIdVbroadcasti32x8, //!< Instruction 'vbroadcasti32x8' {AVX512_DQ+VL}.
kIdVbroadcasti64x2, //!< Instruction 'vbroadcasti64x2' {AVX512_DQ+VL}.
kIdVbroadcasti64x4, //!< Instruction 'vbroadcasti64x4' {AVX512_F}.
kIdVbroadcasti64x4, //!< Instruction 'vbroadcasti64x4' {AVX512_F+VL}.
kIdVbroadcastsd, //!< Instruction 'vbroadcastsd' {AVX|AVX2|AVX512_F+VL}.
kIdVbroadcastss, //!< Instruction 'vbroadcastss' {AVX|AVX2|AVX512_F+VL}.
kIdVcmppd, //!< Instruction 'vcmppd' {AVX|AVX512_F+VL}.
kIdVcmpph, //!< Instruction 'vcmpph' {AVX512_FP16+VL}.
kIdVcmpps, //!< Instruction 'vcmpps' {AVX|AVX512_F+VL}.
kIdVcmpsd, //!< Instruction 'vcmpsd' {AVX|AVX512_F}.
kIdVcmpsh, //!< Instruction 'vcmpsh' {AVX512_FP16}.
kIdVcmpss, //!< Instruction 'vcmpss' {AVX|AVX512_F}.
kIdVcomisd, //!< Instruction 'vcomisd' {AVX|AVX512_F}.
kIdVcomish, //!< Instruction 'vcomish' {AVX512_FP16}.
kIdVcomiss, //!< Instruction 'vcomiss' {AVX|AVX512_F}.
kIdVcmpsd, //!< Instruction 'vcmpsd' {AVX|AVX512_F+VL}.
kIdVcmpsh, //!< Instruction 'vcmpsh' {AVX512_FP16+VL}.
kIdVcmpss, //!< Instruction 'vcmpss' {AVX|AVX512_F+VL}.
kIdVcomisd, //!< Instruction 'vcomisd' {AVX|AVX512_F+VL}.
kIdVcomish, //!< Instruction 'vcomish' {AVX512_FP16+VL}.
kIdVcomiss, //!< Instruction 'vcomiss' {AVX|AVX512_F+VL}.
kIdVcompresspd, //!< Instruction 'vcompresspd' {AVX512_F+VL}.
kIdVcompressps, //!< Instruction 'vcompressps' {AVX512_F+VL}.
kIdVcvtdq2pd, //!< Instruction 'vcvtdq2pd' {AVX|AVX512_F+VL}.
@@ -1043,21 +996,21 @@ namespace Inst {
kIdVcvtqq2pd, //!< Instruction 'vcvtqq2pd' {AVX512_DQ+VL}.
kIdVcvtqq2ph, //!< Instruction 'vcvtqq2ph' {AVX512_FP16+VL}.
kIdVcvtqq2ps, //!< Instruction 'vcvtqq2ps' {AVX512_DQ+VL}.
kIdVcvtsd2sh, //!< Instruction 'vcvtsd2sh' {AVX512_FP16}.
kIdVcvtsd2si, //!< Instruction 'vcvtsd2si' {AVX|AVX512_F}.
kIdVcvtsd2ss, //!< Instruction 'vcvtsd2ss' {AVX|AVX512_F}.
kIdVcvtsd2usi, //!< Instruction 'vcvtsd2usi' {AVX512_F}.
kIdVcvtsh2sd, //!< Instruction 'vcvtsh2sd' {AVX512_FP16}.
kIdVcvtsh2si, //!< Instruction 'vcvtsh2si' {AVX512_FP16}.
kIdVcvtsh2ss, //!< Instruction 'vcvtsh2ss' {AVX512_FP16}.
kIdVcvtsh2usi, //!< Instruction 'vcvtsh2usi' {AVX512_FP16}.
kIdVcvtsi2sd, //!< Instruction 'vcvtsi2sd' {AVX|AVX512_F}.
kIdVcvtsi2sh, //!< Instruction 'vcvtsi2sh' {AVX512_FP16}.
kIdVcvtsi2ss, //!< Instruction 'vcvtsi2ss' {AVX|AVX512_F}.
kIdVcvtss2sd, //!< Instruction 'vcvtss2sd' {AVX|AVX512_F}.
kIdVcvtss2sh, //!< Instruction 'vcvtss2sh' {AVX512_FP16}.
kIdVcvtss2si, //!< Instruction 'vcvtss2si' {AVX|AVX512_F}.
kIdVcvtss2usi, //!< Instruction 'vcvtss2usi' {AVX512_F}.
kIdVcvtsd2sh, //!< Instruction 'vcvtsd2sh' {AVX512_FP16+VL}.
kIdVcvtsd2si, //!< Instruction 'vcvtsd2si' {AVX|AVX512_F+VL}.
kIdVcvtsd2ss, //!< Instruction 'vcvtsd2ss' {AVX|AVX512_F+VL}.
kIdVcvtsd2usi, //!< Instruction 'vcvtsd2usi' {AVX512_F+VL}.
kIdVcvtsh2sd, //!< Instruction 'vcvtsh2sd' {AVX512_FP16+VL}.
kIdVcvtsh2si, //!< Instruction 'vcvtsh2si' {AVX512_FP16+VL}.
kIdVcvtsh2ss, //!< Instruction 'vcvtsh2ss' {AVX512_FP16+VL}.
kIdVcvtsh2usi, //!< Instruction 'vcvtsh2usi' {AVX512_FP16+VL}.
kIdVcvtsi2sd, //!< Instruction 'vcvtsi2sd' {AVX|AVX512_F+VL}.
kIdVcvtsi2sh, //!< Instruction 'vcvtsi2sh' {AVX512_FP16+VL}.
kIdVcvtsi2ss, //!< Instruction 'vcvtsi2ss' {AVX|AVX512_F+VL}.
kIdVcvtss2sd, //!< Instruction 'vcvtss2sd' {AVX|AVX512_F+VL}.
kIdVcvtss2sh, //!< Instruction 'vcvtss2sh' {AVX512_FP16+VL}.
kIdVcvtss2si, //!< Instruction 'vcvtss2si' {AVX|AVX512_F+VL}.
kIdVcvtss2usi, //!< Instruction 'vcvtss2usi' {AVX512_F+VL}.
kIdVcvttpd2dq, //!< Instruction 'vcvttpd2dq' {AVX|AVX512_F+VL}.
kIdVcvttpd2qq, //!< Instruction 'vcvttpd2qq' {AVX512_F+VL}.
kIdVcvttpd2udq, //!< Instruction 'vcvttpd2udq' {AVX512_F+VL}.
@@ -1072,78 +1025,76 @@ namespace Inst {
kIdVcvttps2qq, //!< Instruction 'vcvttps2qq' {AVX512_DQ+VL}.
kIdVcvttps2udq, //!< Instruction 'vcvttps2udq' {AVX512_F+VL}.
kIdVcvttps2uqq, //!< Instruction 'vcvttps2uqq' {AVX512_DQ+VL}.
kIdVcvttsd2si, //!< Instruction 'vcvttsd2si' {AVX|AVX512_F}.
kIdVcvttsd2usi, //!< Instruction 'vcvttsd2usi' {AVX512_F}.
kIdVcvttsh2si, //!< Instruction 'vcvttsh2si' {AVX512_FP16}.
kIdVcvttsh2usi, //!< Instruction 'vcvttsh2usi' {AVX512_FP16}.
kIdVcvttss2si, //!< Instruction 'vcvttss2si' {AVX|AVX512_F}.
kIdVcvttss2usi, //!< Instruction 'vcvttss2usi' {AVX512_F}.
kIdVcvttsd2si, //!< Instruction 'vcvttsd2si' {AVX|AVX512_F+VL}.
kIdVcvttsd2usi, //!< Instruction 'vcvttsd2usi' {AVX512_F+VL}.
kIdVcvttsh2si, //!< Instruction 'vcvttsh2si' {AVX512_FP16+VL}.
kIdVcvttsh2usi, //!< Instruction 'vcvttsh2usi' {AVX512_FP16+VL}.
kIdVcvttss2si, //!< Instruction 'vcvttss2si' {AVX|AVX512_F+VL}.
kIdVcvttss2usi, //!< Instruction 'vcvttss2usi' {AVX512_F+VL}.
kIdVcvtudq2pd, //!< Instruction 'vcvtudq2pd' {AVX512_F+VL}.
kIdVcvtudq2ph, //!< Instruction 'vcvtudq2ph' {AVX512_FP16+VL}.
kIdVcvtudq2ps, //!< Instruction 'vcvtudq2ps' {AVX512_F+VL}.
kIdVcvtuqq2pd, //!< Instruction 'vcvtuqq2pd' {AVX512_DQ+VL}.
kIdVcvtuqq2ph, //!< Instruction 'vcvtuqq2ph' {AVX512_FP16+VL}.
kIdVcvtuqq2ps, //!< Instruction 'vcvtuqq2ps' {AVX512_DQ+VL}.
kIdVcvtusi2sd, //!< Instruction 'vcvtusi2sd' {AVX512_F}.
kIdVcvtusi2sh, //!< Instruction 'vcvtusi2sh' {AVX512_FP16}.
kIdVcvtusi2ss, //!< Instruction 'vcvtusi2ss' {AVX512_F}.
kIdVcvtusi2sd, //!< Instruction 'vcvtusi2sd' {AVX512_F+VL}.
kIdVcvtusi2sh, //!< Instruction 'vcvtusi2sh' {AVX512_FP16+VL}.
kIdVcvtusi2ss, //!< Instruction 'vcvtusi2ss' {AVX512_F+VL}.
kIdVcvtuw2ph, //!< Instruction 'vcvtuw2ph' {AVX512_FP16+VL}.
kIdVcvtw2ph, //!< Instruction 'vcvtw2ph' {AVX512_FP16+VL}.
kIdVdbpsadbw, //!< Instruction 'vdbpsadbw' {AVX512_BW+VL}.
kIdVdivpd, //!< Instruction 'vdivpd' {AVX|AVX512_F+VL}.
kIdVdivph, //!< Instruction 'vdivph' {AVX512_FP16+VL}.
kIdVdivps, //!< Instruction 'vdivps' {AVX|AVX512_F+VL}.
kIdVdivsd, //!< Instruction 'vdivsd' {AVX|AVX512_F}.
kIdVdivsh, //!< Instruction 'vdivsh' {AVX512_FP16}.
kIdVdivss, //!< Instruction 'vdivss' {AVX|AVX512_F}.
kIdVdivsd, //!< Instruction 'vdivsd' {AVX|AVX512_F+VL}.
kIdVdivsh, //!< Instruction 'vdivsh' {AVX512_FP16+VL}.
kIdVdivss, //!< Instruction 'vdivss' {AVX|AVX512_F+VL}.
kIdVdpbf16ps, //!< Instruction 'vdpbf16ps' {AVX512_BF16+VL}.
kIdVdppd, //!< Instruction 'vdppd' {AVX}.
kIdVdpps, //!< Instruction 'vdpps' {AVX}.
kIdVerr, //!< Instruction 'verr'.
kIdVerw, //!< Instruction 'verw'.
kIdVexp2pd, //!< Instruction 'vexp2pd' {AVX512_ER}.
kIdVexp2ps, //!< Instruction 'vexp2ps' {AVX512_ER}.
kIdVexpandpd, //!< Instruction 'vexpandpd' {AVX512_F+VL}.
kIdVexpandps, //!< Instruction 'vexpandps' {AVX512_F+VL}.
kIdVextractf128, //!< Instruction 'vextractf128' {AVX}.
kIdVextractf32x4, //!< Instruction 'vextractf32x4' {AVX512_F+VL}.
kIdVextractf32x8, //!< Instruction 'vextractf32x8' {AVX512_DQ}.
kIdVextractf32x8, //!< Instruction 'vextractf32x8' {AVX512_DQ+VL}.
kIdVextractf64x2, //!< Instruction 'vextractf64x2' {AVX512_DQ+VL}.
kIdVextractf64x4, //!< Instruction 'vextractf64x4' {AVX512_F}.
kIdVextractf64x4, //!< Instruction 'vextractf64x4' {AVX512_F+VL}.
kIdVextracti128, //!< Instruction 'vextracti128' {AVX2}.
kIdVextracti32x4, //!< Instruction 'vextracti32x4' {AVX512_F+VL}.
kIdVextracti32x8, //!< Instruction 'vextracti32x8' {AVX512_DQ}.
kIdVextracti32x8, //!< Instruction 'vextracti32x8' {AVX512_DQ+VL}.
kIdVextracti64x2, //!< Instruction 'vextracti64x2' {AVX512_DQ+VL}.
kIdVextracti64x4, //!< Instruction 'vextracti64x4' {AVX512_F}.
kIdVextractps, //!< Instruction 'vextractps' {AVX|AVX512_F}.
kIdVextracti64x4, //!< Instruction 'vextracti64x4' {AVX512_F+VL}.
kIdVextractps, //!< Instruction 'vextractps' {AVX|AVX512_F+VL}.
kIdVfcmaddcph, //!< Instruction 'vfcmaddcph' {AVX512_FP16+VL}.
kIdVfcmaddcsh, //!< Instruction 'vfcmaddcsh' {AVX512_FP16}.
kIdVfcmaddcsh, //!< Instruction 'vfcmaddcsh' {AVX512_FP16+VL}.
kIdVfcmulcph, //!< Instruction 'vfcmulcph' {AVX512_FP16+VL}.
kIdVfcmulcsh, //!< Instruction 'vfcmulcsh' {AVX512_FP16}.
kIdVfcmulcsh, //!< Instruction 'vfcmulcsh' {AVX512_FP16+VL}.
kIdVfixupimmpd, //!< Instruction 'vfixupimmpd' {AVX512_F+VL}.
kIdVfixupimmps, //!< Instruction 'vfixupimmps' {AVX512_F+VL}.
kIdVfixupimmsd, //!< Instruction 'vfixupimmsd' {AVX512_F}.
kIdVfixupimmss, //!< Instruction 'vfixupimmss' {AVX512_F}.
kIdVfixupimmsd, //!< Instruction 'vfixupimmsd' {AVX512_F+VL}.
kIdVfixupimmss, //!< Instruction 'vfixupimmss' {AVX512_F+VL}.
kIdVfmadd132pd, //!< Instruction 'vfmadd132pd' {FMA|AVX512_F+VL}.
kIdVfmadd132ph, //!< Instruction 'vfmadd132ph' {AVX512_FP16+VL}.
kIdVfmadd132ps, //!< Instruction 'vfmadd132ps' {FMA|AVX512_F+VL}.
kIdVfmadd132sd, //!< Instruction 'vfmadd132sd' {FMA|AVX512_F}.
kIdVfmadd132sh, //!< Instruction 'vfmadd132sh' {AVX512_FP16}.
kIdVfmadd132ss, //!< Instruction 'vfmadd132ss' {FMA|AVX512_F}.
kIdVfmadd132sd, //!< Instruction 'vfmadd132sd' {FMA|AVX512_F+VL}.
kIdVfmadd132sh, //!< Instruction 'vfmadd132sh' {AVX512_FP16+VL}.
kIdVfmadd132ss, //!< Instruction 'vfmadd132ss' {FMA|AVX512_F+VL}.
kIdVfmadd213pd, //!< Instruction 'vfmadd213pd' {FMA|AVX512_F+VL}.
kIdVfmadd213ph, //!< Instruction 'vfmadd213ph' {AVX512_FP16+VL}.
kIdVfmadd213ps, //!< Instruction 'vfmadd213ps' {FMA|AVX512_F+VL}.
kIdVfmadd213sd, //!< Instruction 'vfmadd213sd' {FMA|AVX512_F}.
kIdVfmadd213sh, //!< Instruction 'vfmadd213sh' {AVX512_FP16}.
kIdVfmadd213ss, //!< Instruction 'vfmadd213ss' {FMA|AVX512_F}.
kIdVfmadd213sd, //!< Instruction 'vfmadd213sd' {FMA|AVX512_F+VL}.
kIdVfmadd213sh, //!< Instruction 'vfmadd213sh' {AVX512_FP16+VL}.
kIdVfmadd213ss, //!< Instruction 'vfmadd213ss' {FMA|AVX512_F+VL}.
kIdVfmadd231pd, //!< Instruction 'vfmadd231pd' {FMA|AVX512_F+VL}.
kIdVfmadd231ph, //!< Instruction 'vfmadd231ph' {AVX512_FP16+VL}.
kIdVfmadd231ps, //!< Instruction 'vfmadd231ps' {FMA|AVX512_F+VL}.
kIdVfmadd231sd, //!< Instruction 'vfmadd231sd' {FMA|AVX512_F}.
kIdVfmadd231sh, //!< Instruction 'vfmadd231sh' {AVX512_FP16}.
kIdVfmadd231ss, //!< Instruction 'vfmadd231ss' {FMA|AVX512_F}.
kIdVfmadd231sd, //!< Instruction 'vfmadd231sd' {FMA|AVX512_F+VL}.
kIdVfmadd231sh, //!< Instruction 'vfmadd231sh' {AVX512_FP16+VL}.
kIdVfmadd231ss, //!< Instruction 'vfmadd231ss' {FMA|AVX512_F+VL}.
kIdVfmaddcph, //!< Instruction 'vfmaddcph' {AVX512_FP16+VL}.
kIdVfmaddcsh, //!< Instruction 'vfmaddcsh' {AVX512_FP16}.
kIdVfmaddcsh, //!< Instruction 'vfmaddcsh' {AVX512_FP16+VL}.
kIdVfmaddpd, //!< Instruction 'vfmaddpd' {FMA4}.
kIdVfmaddps, //!< Instruction 'vfmaddps' {FMA4}.
kIdVfmaddsd, //!< Instruction 'vfmaddsd' {FMA4}.
@@ -1162,21 +1113,21 @@ namespace Inst {
kIdVfmsub132pd, //!< Instruction 'vfmsub132pd' {FMA|AVX512_F+VL}.
kIdVfmsub132ph, //!< Instruction 'vfmsub132ph' {AVX512_FP16+VL}.
kIdVfmsub132ps, //!< Instruction 'vfmsub132ps' {FMA|AVX512_F+VL}.
kIdVfmsub132sd, //!< Instruction 'vfmsub132sd' {FMA|AVX512_F}.
kIdVfmsub132sh, //!< Instruction 'vfmsub132sh' {AVX512_FP16}.
kIdVfmsub132ss, //!< Instruction 'vfmsub132ss' {FMA|AVX512_F}.
kIdVfmsub132sd, //!< Instruction 'vfmsub132sd' {FMA|AVX512_F+VL}.
kIdVfmsub132sh, //!< Instruction 'vfmsub132sh' {AVX512_FP16+VL}.
kIdVfmsub132ss, //!< Instruction 'vfmsub132ss' {FMA|AVX512_F+VL}.
kIdVfmsub213pd, //!< Instruction 'vfmsub213pd' {FMA|AVX512_F+VL}.
kIdVfmsub213ph, //!< Instruction 'vfmsub213ph' {AVX512_FP16+VL}.
kIdVfmsub213ps, //!< Instruction 'vfmsub213ps' {FMA|AVX512_F+VL}.
kIdVfmsub213sd, //!< Instruction 'vfmsub213sd' {FMA|AVX512_F}.
kIdVfmsub213sh, //!< Instruction 'vfmsub213sh' {AVX512_FP16}.
kIdVfmsub213ss, //!< Instruction 'vfmsub213ss' {FMA|AVX512_F}.
kIdVfmsub213sd, //!< Instruction 'vfmsub213sd' {FMA|AVX512_F+VL}.
kIdVfmsub213sh, //!< Instruction 'vfmsub213sh' {AVX512_FP16+VL}.
kIdVfmsub213ss, //!< Instruction 'vfmsub213ss' {FMA|AVX512_F+VL}.
kIdVfmsub231pd, //!< Instruction 'vfmsub231pd' {FMA|AVX512_F+VL}.
kIdVfmsub231ph, //!< Instruction 'vfmsub231ph' {AVX512_FP16+VL}.
kIdVfmsub231ps, //!< Instruction 'vfmsub231ps' {FMA|AVX512_F+VL}.
kIdVfmsub231sd, //!< Instruction 'vfmsub231sd' {FMA|AVX512_F}.
kIdVfmsub231sh, //!< Instruction 'vfmsub231sh' {AVX512_FP16}.
kIdVfmsub231ss, //!< Instruction 'vfmsub231ss' {FMA|AVX512_F}.
kIdVfmsub231sd, //!< Instruction 'vfmsub231sd' {FMA|AVX512_F+VL}.
kIdVfmsub231sh, //!< Instruction 'vfmsub231sh' {AVX512_FP16+VL}.
kIdVfmsub231ss, //!< Instruction 'vfmsub231ss' {FMA|AVX512_F+VL}.
kIdVfmsubadd132pd, //!< Instruction 'vfmsubadd132pd' {FMA|AVX512_F+VL}.
kIdVfmsubadd132ph, //!< Instruction 'vfmsubadd132ph' {AVX512_FP16+VL}.
kIdVfmsubadd132ps, //!< Instruction 'vfmsubadd132ps' {FMA|AVX512_F+VL}.
@@ -1197,21 +1148,21 @@ namespace Inst {
kIdVfnmadd132pd, //!< Instruction 'vfnmadd132pd' {FMA|AVX512_F+VL}.
kIdVfnmadd132ph, //!< Instruction 'vfnmadd132ph' {AVX512_FP16+VL}.
kIdVfnmadd132ps, //!< Instruction 'vfnmadd132ps' {FMA|AVX512_F+VL}.
kIdVfnmadd132sd, //!< Instruction 'vfnmadd132sd' {FMA|AVX512_F}.
kIdVfnmadd132sh, //!< Instruction 'vfnmadd132sh' {AVX512_FP16}.
kIdVfnmadd132ss, //!< Instruction 'vfnmadd132ss' {FMA|AVX512_F}.
kIdVfnmadd132sd, //!< Instruction 'vfnmadd132sd' {FMA|AVX512_F+VL}.
kIdVfnmadd132sh, //!< Instruction 'vfnmadd132sh' {AVX512_FP16+VL}.
kIdVfnmadd132ss, //!< Instruction 'vfnmadd132ss' {FMA|AVX512_F+VL}.
kIdVfnmadd213pd, //!< Instruction 'vfnmadd213pd' {FMA|AVX512_F+VL}.
kIdVfnmadd213ph, //!< Instruction 'vfnmadd213ph' {AVX512_FP16+VL}.
kIdVfnmadd213ps, //!< Instruction 'vfnmadd213ps' {FMA|AVX512_F+VL}.
kIdVfnmadd213sd, //!< Instruction 'vfnmadd213sd' {FMA|AVX512_F}.
kIdVfnmadd213sh, //!< Instruction 'vfnmadd213sh' {AVX512_FP16}.
kIdVfnmadd213ss, //!< Instruction 'vfnmadd213ss' {FMA|AVX512_F}.
kIdVfnmadd213sd, //!< Instruction 'vfnmadd213sd' {FMA|AVX512_F+VL}.
kIdVfnmadd213sh, //!< Instruction 'vfnmadd213sh' {AVX512_FP16+VL}.
kIdVfnmadd213ss, //!< Instruction 'vfnmadd213ss' {FMA|AVX512_F+VL}.
kIdVfnmadd231pd, //!< Instruction 'vfnmadd231pd' {FMA|AVX512_F+VL}.
kIdVfnmadd231ph, //!< Instruction 'vfnmadd231ph' {AVX512_FP16+VL}.
kIdVfnmadd231ps, //!< Instruction 'vfnmadd231ps' {FMA|AVX512_F+VL}.
kIdVfnmadd231sd, //!< Instruction 'vfnmadd231sd' {FMA|AVX512_F}.
kIdVfnmadd231sh, //!< Instruction 'vfnmadd231sh' {AVX512_FP16}.
kIdVfnmadd231ss, //!< Instruction 'vfnmadd231ss' {FMA|AVX512_F}.
kIdVfnmadd231sd, //!< Instruction 'vfnmadd231sd' {FMA|AVX512_F+VL}.
kIdVfnmadd231sh, //!< Instruction 'vfnmadd231sh' {AVX512_FP16+VL}.
kIdVfnmadd231ss, //!< Instruction 'vfnmadd231ss' {FMA|AVX512_F+VL}.
kIdVfnmaddpd, //!< Instruction 'vfnmaddpd' {FMA4}.
kIdVfnmaddps, //!< Instruction 'vfnmaddps' {FMA4}.
kIdVfnmaddsd, //!< Instruction 'vfnmaddsd' {FMA4}.
@@ -1219,21 +1170,21 @@ namespace Inst {
kIdVfnmsub132pd, //!< Instruction 'vfnmsub132pd' {FMA|AVX512_F+VL}.
kIdVfnmsub132ph, //!< Instruction 'vfnmsub132ph' {AVX512_FP16+VL}.
kIdVfnmsub132ps, //!< Instruction 'vfnmsub132ps' {FMA|AVX512_F+VL}.
kIdVfnmsub132sd, //!< Instruction 'vfnmsub132sd' {FMA|AVX512_F}.
kIdVfnmsub132sh, //!< Instruction 'vfnmsub132sh' {AVX512_FP16}.
kIdVfnmsub132ss, //!< Instruction 'vfnmsub132ss' {FMA|AVX512_F}.
kIdVfnmsub132sd, //!< Instruction 'vfnmsub132sd' {FMA|AVX512_F+VL}.
kIdVfnmsub132sh, //!< Instruction 'vfnmsub132sh' {AVX512_FP16+VL}.
kIdVfnmsub132ss, //!< Instruction 'vfnmsub132ss' {FMA|AVX512_F+VL}.
kIdVfnmsub213pd, //!< Instruction 'vfnmsub213pd' {FMA|AVX512_F+VL}.
kIdVfnmsub213ph, //!< Instruction 'vfnmsub213ph' {AVX512_FP16+VL}.
kIdVfnmsub213ps, //!< Instruction 'vfnmsub213ps' {FMA|AVX512_F+VL}.
kIdVfnmsub213sd, //!< Instruction 'vfnmsub213sd' {FMA|AVX512_F}.
kIdVfnmsub213sh, //!< Instruction 'vfnmsub213sh' {AVX512_FP16}.
kIdVfnmsub213ss, //!< Instruction 'vfnmsub213ss' {FMA|AVX512_F}.
kIdVfnmsub213sd, //!< Instruction 'vfnmsub213sd' {FMA|AVX512_F+VL}.
kIdVfnmsub213sh, //!< Instruction 'vfnmsub213sh' {AVX512_FP16+VL}.
kIdVfnmsub213ss, //!< Instruction 'vfnmsub213ss' {FMA|AVX512_F+VL}.
kIdVfnmsub231pd, //!< Instruction 'vfnmsub231pd' {FMA|AVX512_F+VL}.
kIdVfnmsub231ph, //!< Instruction 'vfnmsub231ph' {AVX512_FP16+VL}.
kIdVfnmsub231ps, //!< Instruction 'vfnmsub231ps' {FMA|AVX512_F+VL}.
kIdVfnmsub231sd, //!< Instruction 'vfnmsub231sd' {FMA|AVX512_F}.
kIdVfnmsub231sh, //!< Instruction 'vfnmsub231sh' {AVX512_FP16}.
kIdVfnmsub231ss, //!< Instruction 'vfnmsub231ss' {FMA|AVX512_F}.
kIdVfnmsub231sd, //!< Instruction 'vfnmsub231sd' {FMA|AVX512_F+VL}.
kIdVfnmsub231sh, //!< Instruction 'vfnmsub231sh' {AVX512_FP16+VL}.
kIdVfnmsub231ss, //!< Instruction 'vfnmsub231ss' {FMA|AVX512_F+VL}.
kIdVfnmsubpd, //!< Instruction 'vfnmsubpd' {FMA4}.
kIdVfnmsubps, //!< Instruction 'vfnmsubps' {FMA4}.
kIdVfnmsubsd, //!< Instruction 'vfnmsubsd' {FMA4}.
@@ -1241,37 +1192,29 @@ namespace Inst {
kIdVfpclasspd, //!< Instruction 'vfpclasspd' {AVX512_DQ+VL}.
kIdVfpclassph, //!< Instruction 'vfpclassph' {AVX512_FP16+VL}.
kIdVfpclassps, //!< Instruction 'vfpclassps' {AVX512_DQ+VL}.
kIdVfpclasssd, //!< Instruction 'vfpclasssd' {AVX512_DQ}.
kIdVfpclasssh, //!< Instruction 'vfpclasssh' {AVX512_FP16}.
kIdVfpclassss, //!< Instruction 'vfpclassss' {AVX512_DQ}.
kIdVfpclasssd, //!< Instruction 'vfpclasssd' {AVX512_DQ+VL}.
kIdVfpclasssh, //!< Instruction 'vfpclasssh' {AVX512_FP16+VL}.
kIdVfpclassss, //!< Instruction 'vfpclassss' {AVX512_DQ+VL}.
kIdVfrczpd, //!< Instruction 'vfrczpd' {XOP}.
kIdVfrczps, //!< Instruction 'vfrczps' {XOP}.
kIdVfrczsd, //!< Instruction 'vfrczsd' {XOP}.
kIdVfrczss, //!< Instruction 'vfrczss' {XOP}.
kIdVgatherdpd, //!< Instruction 'vgatherdpd' {AVX2|AVX512_F+VL}.
kIdVgatherdps, //!< Instruction 'vgatherdps' {AVX2|AVX512_F+VL}.
kIdVgatherpf0dpd, //!< Instruction 'vgatherpf0dpd' {AVX512_PF}.
kIdVgatherpf0dps, //!< Instruction 'vgatherpf0dps' {AVX512_PF}.
kIdVgatherpf0qpd, //!< Instruction 'vgatherpf0qpd' {AVX512_PF}.
kIdVgatherpf0qps, //!< Instruction 'vgatherpf0qps' {AVX512_PF}.
kIdVgatherpf1dpd, //!< Instruction 'vgatherpf1dpd' {AVX512_PF}.
kIdVgatherpf1dps, //!< Instruction 'vgatherpf1dps' {AVX512_PF}.
kIdVgatherpf1qpd, //!< Instruction 'vgatherpf1qpd' {AVX512_PF}.
kIdVgatherpf1qps, //!< Instruction 'vgatherpf1qps' {AVX512_PF}.
kIdVgatherqpd, //!< Instruction 'vgatherqpd' {AVX2|AVX512_F+VL}.
kIdVgatherqps, //!< Instruction 'vgatherqps' {AVX2|AVX512_F+VL}.
kIdVgetexppd, //!< Instruction 'vgetexppd' {AVX512_F+VL}.
kIdVgetexpph, //!< Instruction 'vgetexpph' {AVX512_FP16+VL}.
kIdVgetexpps, //!< Instruction 'vgetexpps' {AVX512_F+VL}.
kIdVgetexpsd, //!< Instruction 'vgetexpsd' {AVX512_F}.
kIdVgetexpsh, //!< Instruction 'vgetexpsh' {AVX512_FP16}.
kIdVgetexpss, //!< Instruction 'vgetexpss' {AVX512_F}.
kIdVgetexpsd, //!< Instruction 'vgetexpsd' {AVX512_F+VL}.
kIdVgetexpsh, //!< Instruction 'vgetexpsh' {AVX512_FP16+VL}.
kIdVgetexpss, //!< Instruction 'vgetexpss' {AVX512_F+VL}.
kIdVgetmantpd, //!< Instruction 'vgetmantpd' {AVX512_F+VL}.
kIdVgetmantph, //!< Instruction 'vgetmantph' {AVX512_FP16+VL}.
kIdVgetmantps, //!< Instruction 'vgetmantps' {AVX512_F+VL}.
kIdVgetmantsd, //!< Instruction 'vgetmantsd' {AVX512_F}.
kIdVgetmantsh, //!< Instruction 'vgetmantsh' {AVX512_FP16}.
kIdVgetmantss, //!< Instruction 'vgetmantss' {AVX512_F}.
kIdVgetmantsd, //!< Instruction 'vgetmantsd' {AVX512_F+VL}.
kIdVgetmantsh, //!< Instruction 'vgetmantsh' {AVX512_FP16+VL}.
kIdVgetmantss, //!< Instruction 'vgetmantss' {AVX512_F+VL}.
kIdVgf2p8affineinvqb, //!< Instruction 'vgf2p8affineinvqb' {AVX|AVX512_F+VL & GFNI}.
kIdVgf2p8affineqb, //!< Instruction 'vgf2p8affineqb' {AVX|AVX512_F+VL & GFNI}.
kIdVgf2p8mulb, //!< Instruction 'vgf2p8mulb' {AVX|AVX512_F+VL & GFNI}.
@@ -1281,15 +1224,15 @@ namespace Inst {
kIdVhsubps, //!< Instruction 'vhsubps' {AVX}.
kIdVinsertf128, //!< Instruction 'vinsertf128' {AVX}.
kIdVinsertf32x4, //!< Instruction 'vinsertf32x4' {AVX512_F+VL}.
kIdVinsertf32x8, //!< Instruction 'vinsertf32x8' {AVX512_DQ}.
kIdVinsertf32x8, //!< Instruction 'vinsertf32x8' {AVX512_DQ+VL}.
kIdVinsertf64x2, //!< Instruction 'vinsertf64x2' {AVX512_DQ+VL}.
kIdVinsertf64x4, //!< Instruction 'vinsertf64x4' {AVX512_F}.
kIdVinsertf64x4, //!< Instruction 'vinsertf64x4' {AVX512_F+VL}.
kIdVinserti128, //!< Instruction 'vinserti128' {AVX2}.
kIdVinserti32x4, //!< Instruction 'vinserti32x4' {AVX512_F+VL}.
kIdVinserti32x8, //!< Instruction 'vinserti32x8' {AVX512_DQ}.
kIdVinserti32x8, //!< Instruction 'vinserti32x8' {AVX512_DQ+VL}.
kIdVinserti64x2, //!< Instruction 'vinserti64x2' {AVX512_DQ+VL}.
kIdVinserti64x4, //!< Instruction 'vinserti64x4' {AVX512_F}.
kIdVinsertps, //!< Instruction 'vinsertps' {AVX|AVX512_F}.
kIdVinserti64x4, //!< Instruction 'vinserti64x4' {AVX512_F+VL}.
kIdVinsertps, //!< Instruction 'vinsertps' {AVX|AVX512_F+VL}.
kIdVlddqu, //!< Instruction 'vlddqu' {AVX}.
kIdVldmxcsr, //!< Instruction 'vldmxcsr' {AVX}.
kIdVmaskmovdqu, //!< Instruction 'vmaskmovdqu' {AVX}.
@@ -1298,9 +1241,9 @@ namespace Inst {
kIdVmaxpd, //!< Instruction 'vmaxpd' {AVX|AVX512_F+VL}.
kIdVmaxph, //!< Instruction 'vmaxph' {AVX512_FP16+VL}.
kIdVmaxps, //!< Instruction 'vmaxps' {AVX|AVX512_F+VL}.
kIdVmaxsd, //!< Instruction 'vmaxsd' {AVX|AVX512_F}.
kIdVmaxsh, //!< Instruction 'vmaxsh' {AVX512_FP16}.
kIdVmaxss, //!< Instruction 'vmaxss' {AVX|AVX512_F}.
kIdVmaxsd, //!< Instruction 'vmaxsd' {AVX|AVX512_F+VL}.
kIdVmaxsh, //!< Instruction 'vmaxsh' {AVX512_FP16+VL}.
kIdVmaxss, //!< Instruction 'vmaxss' {AVX|AVX512_F+VL}.
kIdVmcall, //!< Instruction 'vmcall' {VMX}.
kIdVmclear, //!< Instruction 'vmclear' {VMX}.
kIdVmfunc, //!< Instruction 'vmfunc' {VMX}.
@@ -1308,15 +1251,15 @@ namespace Inst {
kIdVminpd, //!< Instruction 'vminpd' {AVX|AVX512_F+VL}.
kIdVminph, //!< Instruction 'vminph' {AVX512_FP16+VL}.
kIdVminps, //!< Instruction 'vminps' {AVX|AVX512_F+VL}.
kIdVminsd, //!< Instruction 'vminsd' {AVX|AVX512_F}.
kIdVminsh, //!< Instruction 'vminsh' {AVX512_FP16}.
kIdVminss, //!< Instruction 'vminss' {AVX|AVX512_F}.
kIdVminsd, //!< Instruction 'vminsd' {AVX|AVX512_F+VL}.
kIdVminsh, //!< Instruction 'vminsh' {AVX512_FP16+VL}.
kIdVminss, //!< Instruction 'vminss' {AVX|AVX512_F+VL}.
kIdVmlaunch, //!< Instruction 'vmlaunch' {VMX}.
kIdVmload, //!< Instruction 'vmload' {SVM}.
kIdVmmcall, //!< Instruction 'vmmcall' {SVM}.
kIdVmovapd, //!< Instruction 'vmovapd' {AVX|AVX512_F+VL}.
kIdVmovaps, //!< Instruction 'vmovaps' {AVX|AVX512_F+VL}.
kIdVmovd, //!< Instruction 'vmovd' {AVX|AVX512_F}.
kIdVmovd, //!< Instruction 'vmovd' {AVX|AVX512_F+VL}.
kIdVmovddup, //!< Instruction 'vmovddup' {AVX|AVX512_F+VL}.
kIdVmovdqa, //!< Instruction 'vmovdqa' {AVX}.
kIdVmovdqa32, //!< Instruction 'vmovdqa32' {AVX512_F+VL}.
@@ -1326,27 +1269,27 @@ namespace Inst {
kIdVmovdqu32, //!< Instruction 'vmovdqu32' {AVX512_F+VL}.
kIdVmovdqu64, //!< Instruction 'vmovdqu64' {AVX512_F+VL}.
kIdVmovdqu8, //!< Instruction 'vmovdqu8' {AVX512_BW+VL}.
kIdVmovhlps, //!< Instruction 'vmovhlps' {AVX|AVX512_F}.
kIdVmovhpd, //!< Instruction 'vmovhpd' {AVX|AVX512_F}.
kIdVmovhps, //!< Instruction 'vmovhps' {AVX|AVX512_F}.
kIdVmovlhps, //!< Instruction 'vmovlhps' {AVX|AVX512_F}.
kIdVmovlpd, //!< Instruction 'vmovlpd' {AVX|AVX512_F}.
kIdVmovlps, //!< Instruction 'vmovlps' {AVX|AVX512_F}.
kIdVmovhlps, //!< Instruction 'vmovhlps' {AVX|AVX512_F+VL}.
kIdVmovhpd, //!< Instruction 'vmovhpd' {AVX|AVX512_F+VL}.
kIdVmovhps, //!< Instruction 'vmovhps' {AVX|AVX512_F+VL}.
kIdVmovlhps, //!< Instruction 'vmovlhps' {AVX|AVX512_F+VL}.
kIdVmovlpd, //!< Instruction 'vmovlpd' {AVX|AVX512_F+VL}.
kIdVmovlps, //!< Instruction 'vmovlps' {AVX|AVX512_F+VL}.
kIdVmovmskpd, //!< Instruction 'vmovmskpd' {AVX}.
kIdVmovmskps, //!< Instruction 'vmovmskps' {AVX}.
kIdVmovntdq, //!< Instruction 'vmovntdq' {AVX|AVX512_F+VL}.
kIdVmovntdqa, //!< Instruction 'vmovntdqa' {AVX|AVX2|AVX512_F+VL}.
kIdVmovntpd, //!< Instruction 'vmovntpd' {AVX|AVX512_F+VL}.
kIdVmovntps, //!< Instruction 'vmovntps' {AVX|AVX512_F+VL}.
kIdVmovq, //!< Instruction 'vmovq' {AVX|AVX512_F}.
kIdVmovsd, //!< Instruction 'vmovsd' {AVX|AVX512_F}.
kIdVmovsh, //!< Instruction 'vmovsh' {AVX512_FP16}.
kIdVmovq, //!< Instruction 'vmovq' {AVX|AVX512_F+VL}.
kIdVmovsd, //!< Instruction 'vmovsd' {AVX|AVX512_F+VL}.
kIdVmovsh, //!< Instruction 'vmovsh' {AVX512_FP16+VL}.
kIdVmovshdup, //!< Instruction 'vmovshdup' {AVX|AVX512_F+VL}.
kIdVmovsldup, //!< Instruction 'vmovsldup' {AVX|AVX512_F+VL}.
kIdVmovss, //!< Instruction 'vmovss' {AVX|AVX512_F}.
kIdVmovss, //!< Instruction 'vmovss' {AVX|AVX512_F+VL}.
kIdVmovupd, //!< Instruction 'vmovupd' {AVX|AVX512_F+VL}.
kIdVmovups, //!< Instruction 'vmovups' {AVX|AVX512_F+VL}.
kIdVmovw, //!< Instruction 'vmovw' {AVX512_FP16}.
kIdVmovw, //!< Instruction 'vmovw' {AVX512_FP16+VL}.
kIdVmpsadbw, //!< Instruction 'vmpsadbw' {AVX|AVX2}.
kIdVmptrld, //!< Instruction 'vmptrld' {VMX}.
kIdVmptrst, //!< Instruction 'vmptrst' {VMX}.
@@ -1357,9 +1300,9 @@ namespace Inst {
kIdVmulpd, //!< Instruction 'vmulpd' {AVX|AVX512_F+VL}.
kIdVmulph, //!< Instruction 'vmulph' {AVX512_FP16+VL}.
kIdVmulps, //!< Instruction 'vmulps' {AVX|AVX512_F+VL}.
kIdVmulsd, //!< Instruction 'vmulsd' {AVX|AVX512_F}.
kIdVmulsh, //!< Instruction 'vmulsh' {AVX512_FP16}.
kIdVmulss, //!< Instruction 'vmulss' {AVX|AVX512_F}.
kIdVmulsd, //!< Instruction 'vmulsd' {AVX|AVX512_F+VL}.
kIdVmulsh, //!< Instruction 'vmulsh' {AVX512_FP16+VL}.
kIdVmulss, //!< Instruction 'vmulss' {AVX|AVX512_F+VL}.
kIdVmwrite, //!< Instruction 'vmwrite' {VMX}.
kIdVmxoff, //!< Instruction 'vmxoff' {VMX}.
kIdVmxon, //!< Instruction 'vmxon' {VMX}.
@@ -1367,8 +1310,6 @@ namespace Inst {
kIdVorps, //!< Instruction 'vorps' {AVX|AVX512_DQ+VL}.
kIdVp2intersectd, //!< Instruction 'vp2intersectd' {AVX512_VP2INTERSECT+VL}.
kIdVp2intersectq, //!< Instruction 'vp2intersectq' {AVX512_VP2INTERSECT+VL}.
kIdVp4dpwssd, //!< Instruction 'vp4dpwssd' {AVX512_4VNNIW}.
kIdVp4dpwssds, //!< Instruction 'vp4dpwssds' {AVX512_4VNNIW}.
kIdVpabsb, //!< Instruction 'vpabsb' {AVX|AVX2|AVX512_BW+VL}.
kIdVpabsd, //!< Instruction 'vpabsd' {AVX|AVX2|AVX512_F+VL}.
kIdVpabsq, //!< Instruction 'vpabsq' {AVX512_F+VL}.
@@ -1487,10 +1428,10 @@ namespace Inst {
kIdVpexpandd, //!< Instruction 'vpexpandd' {AVX512_F+VL}.
kIdVpexpandq, //!< Instruction 'vpexpandq' {AVX512_F+VL}.
kIdVpexpandw, //!< Instruction 'vpexpandw' {AVX512_VBMI2+VL}.
kIdVpextrb, //!< Instruction 'vpextrb' {AVX|AVX512_BW}.
kIdVpextrd, //!< Instruction 'vpextrd' {AVX|AVX512_DQ}.
kIdVpextrq, //!< Instruction 'vpextrq' {AVX|AVX512_DQ} (X64).
kIdVpextrw, //!< Instruction 'vpextrw' {AVX|AVX512_BW}.
kIdVpextrb, //!< Instruction 'vpextrb' {AVX|AVX512_BW+VL}.
kIdVpextrd, //!< Instruction 'vpextrd' {AVX|AVX512_DQ+VL}.
kIdVpextrq, //!< Instruction 'vpextrq' {AVX|AVX512_DQ+VL} (X64).
kIdVpextrw, //!< Instruction 'vpextrw' {AVX|AVX512_BW+VL}.
kIdVpgatherdd, //!< Instruction 'vpgatherdd' {AVX2|AVX512_F+VL}.
kIdVpgatherdq, //!< Instruction 'vpgatherdq' {AVX2|AVX512_F+VL}.
kIdVpgatherqd, //!< Instruction 'vpgatherqd' {AVX2|AVX512_F+VL}.
@@ -1517,10 +1458,10 @@ namespace Inst {
kIdVphsubsw, //!< Instruction 'vphsubsw' {AVX|AVX2}.
kIdVphsubw, //!< Instruction 'vphsubw' {AVX|AVX2}.
kIdVphsubwd, //!< Instruction 'vphsubwd' {XOP}.
kIdVpinsrb, //!< Instruction 'vpinsrb' {AVX|AVX512_BW}.
kIdVpinsrd, //!< Instruction 'vpinsrd' {AVX|AVX512_DQ}.
kIdVpinsrq, //!< Instruction 'vpinsrq' {AVX|AVX512_DQ} (X64).
kIdVpinsrw, //!< Instruction 'vpinsrw' {AVX|AVX512_BW}.
kIdVpinsrb, //!< Instruction 'vpinsrb' {AVX|AVX512_BW+VL}.
kIdVpinsrd, //!< Instruction 'vpinsrd' {AVX|AVX512_DQ+VL}.
kIdVpinsrq, //!< Instruction 'vpinsrq' {AVX|AVX512_DQ+VL} (X64).
kIdVpinsrw, //!< Instruction 'vpinsrw' {AVX|AVX512_BW+VL}.
kIdVplzcntd, //!< Instruction 'vplzcntd' {AVX512_CD+VL}.
kIdVplzcntq, //!< Instruction 'vplzcntq' {AVX512_CD+VL}.
kIdVpmacsdd, //!< Instruction 'vpmacsdd' {XOP}.
@@ -1710,64 +1651,48 @@ namespace Inst {
kIdVpxorq, //!< Instruction 'vpxorq' {AVX512_F+VL}.
kIdVrangepd, //!< Instruction 'vrangepd' {AVX512_DQ+VL}.
kIdVrangeps, //!< Instruction 'vrangeps' {AVX512_DQ+VL}.
kIdVrangesd, //!< Instruction 'vrangesd' {AVX512_DQ}.
kIdVrangess, //!< Instruction 'vrangess' {AVX512_DQ}.
kIdVrangesd, //!< Instruction 'vrangesd' {AVX512_DQ+VL}.
kIdVrangess, //!< Instruction 'vrangess' {AVX512_DQ+VL}.
kIdVrcp14pd, //!< Instruction 'vrcp14pd' {AVX512_F+VL}.
kIdVrcp14ps, //!< Instruction 'vrcp14ps' {AVX512_F+VL}.
kIdVrcp14sd, //!< Instruction 'vrcp14sd' {AVX512_F}.
kIdVrcp14ss, //!< Instruction 'vrcp14ss' {AVX512_F}.
kIdVrcp28pd, //!< Instruction 'vrcp28pd' {AVX512_ER}.
kIdVrcp28ps, //!< Instruction 'vrcp28ps' {AVX512_ER}.
kIdVrcp28sd, //!< Instruction 'vrcp28sd' {AVX512_ER}.
kIdVrcp28ss, //!< Instruction 'vrcp28ss' {AVX512_ER}.
kIdVrcpph, //!< Instruction 'vrcpph' {AVX512_FP16}.
kIdVrcp14sd, //!< Instruction 'vrcp14sd' {AVX512_F+VL}.
kIdVrcp14ss, //!< Instruction 'vrcp14ss' {AVX512_F+VL}.
kIdVrcpph, //!< Instruction 'vrcpph' {AVX512_FP16+VL}.
kIdVrcpps, //!< Instruction 'vrcpps' {AVX}.
kIdVrcpsh, //!< Instruction 'vrcpsh' {AVX512_FP16}.
kIdVrcpsh, //!< Instruction 'vrcpsh' {AVX512_FP16+VL}.
kIdVrcpss, //!< Instruction 'vrcpss' {AVX}.
kIdVreducepd, //!< Instruction 'vreducepd' {AVX512_DQ+VL}.
kIdVreduceph, //!< Instruction 'vreduceph' {AVX512_FP16+VL}.
kIdVreduceps, //!< Instruction 'vreduceps' {AVX512_DQ+VL}.
kIdVreducesd, //!< Instruction 'vreducesd' {AVX512_DQ}.
kIdVreducesh, //!< Instruction 'vreducesh' {AVX512_FP16}.
kIdVreducess, //!< Instruction 'vreducess' {AVX512_DQ}.
kIdVreducesd, //!< Instruction 'vreducesd' {AVX512_DQ+VL}.
kIdVreducesh, //!< Instruction 'vreducesh' {AVX512_FP16+VL}.
kIdVreducess, //!< Instruction 'vreducess' {AVX512_DQ+VL}.
kIdVrndscalepd, //!< Instruction 'vrndscalepd' {AVX512_F+VL}.
kIdVrndscaleph, //!< Instruction 'vrndscaleph' {AVX512_FP16+VL}.
kIdVrndscaleps, //!< Instruction 'vrndscaleps' {AVX512_F+VL}.
kIdVrndscalesd, //!< Instruction 'vrndscalesd' {AVX512_F}.
kIdVrndscalesh, //!< Instruction 'vrndscalesh' {AVX512_FP16}.
kIdVrndscaless, //!< Instruction 'vrndscaless' {AVX512_F}.
kIdVrndscalesd, //!< Instruction 'vrndscalesd' {AVX512_F+VL}.
kIdVrndscalesh, //!< Instruction 'vrndscalesh' {AVX512_FP16+VL}.
kIdVrndscaless, //!< Instruction 'vrndscaless' {AVX512_F+VL}.
kIdVroundpd, //!< Instruction 'vroundpd' {AVX}.
kIdVroundps, //!< Instruction 'vroundps' {AVX}.
kIdVroundsd, //!< Instruction 'vroundsd' {AVX}.
kIdVroundss, //!< Instruction 'vroundss' {AVX}.
kIdVrsqrt14pd, //!< Instruction 'vrsqrt14pd' {AVX512_F+VL}.
kIdVrsqrt14ps, //!< Instruction 'vrsqrt14ps' {AVX512_F+VL}.
kIdVrsqrt14sd, //!< Instruction 'vrsqrt14sd' {AVX512_F}.
kIdVrsqrt14ss, //!< Instruction 'vrsqrt14ss' {AVX512_F}.
kIdVrsqrt28pd, //!< Instruction 'vrsqrt28pd' {AVX512_ER}.
kIdVrsqrt28ps, //!< Instruction 'vrsqrt28ps' {AVX512_ER}.
kIdVrsqrt28sd, //!< Instruction 'vrsqrt28sd' {AVX512_ER}.
kIdVrsqrt28ss, //!< Instruction 'vrsqrt28ss' {AVX512_ER}.
kIdVrsqrt14sd, //!< Instruction 'vrsqrt14sd' {AVX512_F+VL}.
kIdVrsqrt14ss, //!< Instruction 'vrsqrt14ss' {AVX512_F+VL}.
kIdVrsqrtph, //!< Instruction 'vrsqrtph' {AVX512_FP16+VL}.
kIdVrsqrtps, //!< Instruction 'vrsqrtps' {AVX}.
kIdVrsqrtsh, //!< Instruction 'vrsqrtsh' {AVX512_FP16}.
kIdVrsqrtsh, //!< Instruction 'vrsqrtsh' {AVX512_FP16+VL}.
kIdVrsqrtss, //!< Instruction 'vrsqrtss' {AVX}.
kIdVscalefpd, //!< Instruction 'vscalefpd' {AVX512_F+VL}.
kIdVscalefph, //!< Instruction 'vscalefph' {AVX512_FP16+VL}.
kIdVscalefps, //!< Instruction 'vscalefps' {AVX512_F+VL}.
kIdVscalefsd, //!< Instruction 'vscalefsd' {AVX512_F}.
kIdVscalefsh, //!< Instruction 'vscalefsh' {AVX512_FP16}.
kIdVscalefss, //!< Instruction 'vscalefss' {AVX512_F}.
kIdVscalefsd, //!< Instruction 'vscalefsd' {AVX512_F+VL}.
kIdVscalefsh, //!< Instruction 'vscalefsh' {AVX512_FP16+VL}.
kIdVscalefss, //!< Instruction 'vscalefss' {AVX512_F+VL}.
kIdVscatterdpd, //!< Instruction 'vscatterdpd' {AVX512_F+VL}.
kIdVscatterdps, //!< Instruction 'vscatterdps' {AVX512_F+VL}.
kIdVscatterpf0dpd, //!< Instruction 'vscatterpf0dpd' {AVX512_PF}.
kIdVscatterpf0dps, //!< Instruction 'vscatterpf0dps' {AVX512_PF}.
kIdVscatterpf0qpd, //!< Instruction 'vscatterpf0qpd' {AVX512_PF}.
kIdVscatterpf0qps, //!< Instruction 'vscatterpf0qps' {AVX512_PF}.
kIdVscatterpf1dpd, //!< Instruction 'vscatterpf1dpd' {AVX512_PF}.
kIdVscatterpf1dps, //!< Instruction 'vscatterpf1dps' {AVX512_PF}.
kIdVscatterpf1qpd, //!< Instruction 'vscatterpf1qpd' {AVX512_PF}.
kIdVscatterpf1qps, //!< Instruction 'vscatterpf1qps' {AVX512_PF}.
kIdVscatterqpd, //!< Instruction 'vscatterqpd' {AVX512_F+VL}.
kIdVscatterqps, //!< Instruction 'vscatterqps' {AVX512_F+VL}.
kIdVsha512msg1, //!< Instruction 'vsha512msg1' {AVX & SHA512}.
@@ -1787,21 +1712,21 @@ namespace Inst {
kIdVsqrtpd, //!< Instruction 'vsqrtpd' {AVX|AVX512_F+VL}.
kIdVsqrtph, //!< Instruction 'vsqrtph' {AVX512_FP16+VL}.
kIdVsqrtps, //!< Instruction 'vsqrtps' {AVX|AVX512_F+VL}.
kIdVsqrtsd, //!< Instruction 'vsqrtsd' {AVX|AVX512_F}.
kIdVsqrtsh, //!< Instruction 'vsqrtsh' {AVX512_FP16}.
kIdVsqrtss, //!< Instruction 'vsqrtss' {AVX|AVX512_F}.
kIdVsqrtsd, //!< Instruction 'vsqrtsd' {AVX|AVX512_F+VL}.
kIdVsqrtsh, //!< Instruction 'vsqrtsh' {AVX512_FP16+VL}.
kIdVsqrtss, //!< Instruction 'vsqrtss' {AVX|AVX512_F+VL}.
kIdVstmxcsr, //!< Instruction 'vstmxcsr' {AVX}.
kIdVsubpd, //!< Instruction 'vsubpd' {AVX|AVX512_F+VL}.
kIdVsubph, //!< Instruction 'vsubph' {AVX512_FP16+VL}.
kIdVsubps, //!< Instruction 'vsubps' {AVX|AVX512_F+VL}.
kIdVsubsd, //!< Instruction 'vsubsd' {AVX|AVX512_F}.
kIdVsubsh, //!< Instruction 'vsubsh' {AVX512_FP16}.
kIdVsubss, //!< Instruction 'vsubss' {AVX|AVX512_F}.
kIdVsubsd, //!< Instruction 'vsubsd' {AVX|AVX512_F+VL}.
kIdVsubsh, //!< Instruction 'vsubsh' {AVX512_FP16+VL}.
kIdVsubss, //!< Instruction 'vsubss' {AVX|AVX512_F+VL}.
kIdVtestpd, //!< Instruction 'vtestpd' {AVX}.
kIdVtestps, //!< Instruction 'vtestps' {AVX}.
kIdVucomisd, //!< Instruction 'vucomisd' {AVX|AVX512_F}.
kIdVucomish, //!< Instruction 'vucomish' {AVX512_FP16}.
kIdVucomiss, //!< Instruction 'vucomiss' {AVX|AVX512_F}.
kIdVucomisd, //!< Instruction 'vucomisd' {AVX|AVX512_F+VL}.
kIdVucomish, //!< Instruction 'vucomish' {AVX512_FP16+VL}.
kIdVucomiss, //!< Instruction 'vucomiss' {AVX|AVX512_F+VL}.
kIdVunpckhpd, //!< Instruction 'vunpckhpd' {AVX|AVX512_F+VL}.
kIdVunpckhps, //!< Instruction 'vunpckhps' {AVX|AVX512_F+VL}.
kIdVunpcklpd, //!< Instruction 'vunpcklpd' {AVX|AVX512_F+VL}.
@@ -1844,8 +1769,54 @@ namespace Inst {
kIdXsaves64, //!< Instruction 'xsaves64' {XSAVES} (X64).
kIdXsetbv, //!< Instruction 'xsetbv' {XSAVE}.
kIdXsusldtrk, //!< Instruction 'xsusldtrk' {TSXLDTRK}.
kIdXtest, //!< Instruction 'xtest' {TSX}.
_kIdCount
kIdXtest, //!< Instruction 'xtest' {RTM}.
_kIdCount,
// Aliases.
kIdCmovnae = kIdCmovb,
kIdCmovc = kIdCmovb,
kIdCmovna = kIdCmovbe,
kIdCmovnge = kIdCmovl,
kIdCmovng = kIdCmovle,
kIdCmovae = kIdCmovnb,
kIdCmovnc = kIdCmovnb,
kIdCmova = kIdCmovnbe,
kIdCmovge = kIdCmovnl,
kIdCmovg = kIdCmovnle,
kIdCmovpo = kIdCmovnp,
kIdCmovne = kIdCmovnz,
kIdCmovpe = kIdCmovp,
kIdCmove = kIdCmovz,
kIdWait = kIdFwait,
kIdJnae = kIdJb,
kIdJc = kIdJb,
kIdJna = kIdJbe,
kIdJnge = kIdJl,
kIdJng = kIdJle,
kIdJae = kIdJnb,
kIdJnc = kIdJnb,
kIdJa = kIdJnbe,
kIdJge = kIdJnl,
kIdJg = kIdJnle,
kIdJpo = kIdJnp,
kIdJne = kIdJnz,
kIdJpe = kIdJp,
kIdJe = kIdJz,
kIdSetnae = kIdSetb,
kIdSetc = kIdSetb,
kIdSetna = kIdSetbe,
kIdSetnge = kIdSetl,
kIdSetng = kIdSetle,
kIdSetae = kIdSetnb,
kIdSetnc = kIdSetnb,
kIdSeta = kIdSetnbe,
kIdSetge = kIdSetnl,
kIdSetg = kIdSetnle,
kIdSetpo = kIdSetnp,
kIdSetne = kIdSetnz,
kIdSetpe = kIdSetp,
kIdSete = kIdSetz,
kIdSal = kIdShl
// ${InstId:End}
};
@@ -1854,10 +1825,10 @@ namespace Inst {
//! \cond
#define ASMJIT_INST_FROM_COND(ID) \
ID##o, ID##no, ID##b , ID##ae, \
ID##e, ID##ne, ID##be, ID##a , \
ID##s, ID##ns, ID##pe, ID##po, \
ID##l, ID##ge, ID##le, ID##g
ID##o, ID##no, ID##b , ID##nb , \
ID##z, ID##nz, ID##be, ID##nbe, \
ID##s, ID##ns, ID##p , ID##np , \
ID##l, ID##nl, ID##le, ID##nle
static constexpr uint16_t _jccTable[] = { ASMJIT_INST_FROM_COND(Inst::kIdJ) };
static constexpr uint16_t _setccTable[] = { ASMJIT_INST_FROM_COND(Inst::kIdSet) };

32
src/asmjit/x86/x86instapi.cpp
View File

@@ -22,15 +22,37 @@ namespace InstInternal {
// ========================
#ifndef ASMJIT_NO_TEXT
Error instIdToString(InstId instId, String& output) noexcept {
Error instIdToString(InstId instId, InstStringifyOptions options, String& output) noexcept {
if (ASMJIT_UNLIKELY(!Inst::isDefinedId(instId)))
return DebugUtils::errored(kErrorInvalidInstruction);
return InstNameUtils::decode(output, InstDB::_instNameIndexTable[instId], InstDB::_instNameStringTable);
return InstNameUtils::decode(InstDB::_instNameIndexTable[instId], options, InstDB::_instNameStringTable, output);
}
InstId stringToInstId(const char* s, size_t len) noexcept {
return InstNameUtils::find(s, len, InstDB::instNameIndex, InstDB::_instNameIndexTable, InstDB::_instNameStringTable);
if (ASMJIT_UNLIKELY(!s)) {
return BaseInst::kIdNone;
}
if (len == SIZE_MAX) {
len = strlen(s);
}
if (len == 0u || len > InstDB::instNameIndex.maxNameLength) {
return BaseInst::kIdNone;
}
InstId instId = InstNameUtils::findInstruction(s, len, InstDB::_instNameIndexTable, InstDB::_instNameStringTable, InstDB::instNameIndex);
if (instId != BaseInst::kIdNone) {
return instId;
}
uint32_t aliasIndex = InstNameUtils::findAlias(s, len, InstDB::_aliasNameIndexTable, InstDB::_aliasNameStringTable, InstDB::kAliasTableSize);
if (aliasIndex != Globals::kInvalidId) {
return InstDB::_aliasIndexToInstId[aliasIndex];
}
return BaseInst::kIdNone;
}
#endif // !ASMJIT_NO_TEXT
@@ -1668,12 +1690,12 @@ UNIT(x86_inst_api_text) {
INFO("Matching all X86 instructions");
for (uint32_t a = 1; a < Inst::_kIdCount; a++) {
StringTmp<128> aName;
EXPECT_EQ(InstInternal::instIdToString(a, aName), kErrorOk)
EXPECT_EQ(InstInternal::instIdToString(a, InstStringifyOptions::kNone, aName), kErrorOk)
.message("Failed to get the name of instruction #%u", a);
uint32_t b = InstInternal::stringToInstId(aName.data(), aName.size());
StringTmp<128> bName;
InstInternal::instIdToString(b, bName);
InstInternal::instIdToString(b, InstStringifyOptions::kNone, bName);
EXPECT_EQ(a, b)
.message("Instructions do not match \"%s\" (#%u) != \"%s\" (#%u)", aName.data(), a, bName.data(), b);
}

2
src/asmjit/x86/x86instapi_p.h
View File

@@ -18,7 +18,7 @@ ASMJIT_BEGIN_SUB_NAMESPACE(x86)
namespace InstInternal {
#ifndef ASMJIT_NO_TEXT
Error ASMJIT_CDECL instIdToString(InstId instId, String& output) noexcept;
Error ASMJIT_CDECL instIdToString(InstId instId, InstStringifyOptions options, String& output) noexcept;
InstId ASMJIT_CDECL stringToInstId(const char* s, size_t len) noexcept;
#endif // !ASMJIT_NO_TEXT

8931
src/asmjit/x86/x86instdb.cpp
View File

File diff suppressed because it is too large Load Diff

2
src/asmjit/x86/x86instdb.h
View File

@@ -319,8 +319,6 @@ enum class Avx512Flags : uint32_t {
kB32 = 0x00000020u,
//! Supports 64-bit broadcast 'b64'.
kB64 = 0x00000040u,
//! Operates on a vector of consecutive registers (AVX512_4FMAPS and AVX512_4VNNIW).
kT4X = 0x00000080u,
//! Implicit zeroing if {k} masking is used. Using {z} is not valid in this case as it's implicit.
kImplicitZ = 0x00000100,

14
src/asmjit/x86/x86instdb_p.h
View File

@@ -122,7 +122,6 @@ enum EncodingId : uint32_t {
kEncodingVexKmov, //!< VEX [RM|MR] (used by kmov[b|w|d|q]).
kEncodingVexR_Wx, //!< VEX|EVEX [R] (propagatex VEX.W if GPQ used).
kEncodingVexM, //!< VEX|EVEX [M].
kEncodingVexM_VM, //!< VEX|EVEX [M] (propagates VEX|EVEX.L, VSIB support).
kEncodingVexMr_Lx, //!< VEX|EVEX [MR] (propagates VEX|EVEX.L if YMM used).
kEncodingVexMr_VM, //!< VEX|EVEX [MR] (VSIB support).
kEncodingVexMri, //!< VEX|EVEX [MRI].
@@ -136,7 +135,6 @@ enum EncodingId : uint32_t {
kEncodingVexRm_Lx_Narrow, //!< VEX|EVEX [RM] (the destination vector size is narrowed).
kEncodingVexRm_Lx_Bcst, //!< VEX|EVEX [RM] (can handle broadcast r32/r64).
kEncodingVexRm_VM, //!< VEX|EVEX [RM] (propagates VEX|EVEX.L, VSIB support).
kEncodingVexRm_T1_4X, //!< EVEX [RM] (used by NN instructions that use RM-T1_4X encoding).
kEncodingVexRmi, //!< VEX|EVEX [RMI].
kEncodingVexRmi_Wx, //!< VEX|EVEX [RMI] (propagates VEX|EVEX.W if GPQ used).
kEncodingVexRmi_Lx, //!< VEX|EVEX [RMI] (propagates VEX|EVEX.L if YMM used).
@@ -288,9 +286,21 @@ extern const uint32_t _mainOpcodeTable[];
extern const uint32_t _altOpcodeTable[];
#ifndef ASMJIT_NO_TEXT
extern const InstNameIndex instNameIndex;
extern const char _instNameStringTable[];
extern const uint32_t _instNameIndexTable[];
extern const char _aliasNameStringTable[];
extern const uint32_t _aliasNameIndexTable[];
extern const uint32_t _aliasIndexToInstId[];
// ${NameDataInfo:Begin}
// ------------------- Automatically generated, do not edit -------------------
static constexpr uint32_t kAliasTableSize = 44;
// ----------------------------------------------------------------------------
// ${NameDataInfo:End}
#endif // !ASMJIT_NO_TEXT
extern const AdditionalInfo _additionalInfoTable[];

2
src/asmjit/x86/x86opcode_p.h
View File

@@ -173,8 +173,6 @@ struct Opcode {
kCDTT_FVM = kCDTT_ByLL,
kCDTT_T1S = kCDTT_None,
kCDTT_T1F = kCDTT_None,
kCDTT_T1_4X = kCDTT_None,
kCDTT_T4X = kCDTT_None, // Alias to have only 3 letters.
kCDTT_T2 = kCDTT_None,
kCDTT_T4 = kCDTT_None,
kCDTT_T8 = kCDTT_None,

59
test/asmjit_test_assembler_x64.cpp
View File

@@ -5545,14 +5545,6 @@ static void ASMJIT_NOINLINE testX64AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("C4E1ED47CB" , kxord(k1, k2, k3));
TEST_INSTRUCTION("C4E1EC47CB" , kxorq(k1, k2, k3));
TEST_INSTRUCTION("C5EC47CB" , kxorw(k1, k2, k3));
TEST_INSTRUCTION("62F25F489A4C1A08" , v4fmaddps(zmm1, zmm4, zmm5, zmm6, zmm7, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F25F489A4C1A08" , v4fmaddps(zmm1, zmm4, zmm5, zmm6, zmm7, xmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F25F089B4C1A08" , v4fmaddss(xmm1, xmm4, xmm5, xmm6, xmm7, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F25F089B4C1A08" , v4fmaddss(xmm1, xmm4, xmm5, xmm6, xmm7, xmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F25F48AA4C1A08" , v4fnmaddps(zmm1, zmm4, zmm5, zmm6, zmm7, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F25F48AA4C1A08" , v4fnmaddps(zmm1, zmm4, zmm5, zmm6, zmm7, xmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F25F08AB4C1A08" , v4fnmaddss(xmm1, xmm4, xmm5, xmm6, xmm7, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F25F08AB4C1A08" , v4fnmaddss(xmm1, xmm4, xmm5, xmm6, xmm7, xmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F1ED4858CB" , vaddpd(zmm1, zmm2, zmm3));
TEST_INSTRUCTION("62F1ED48584C2B02" , vaddpd(zmm1, zmm2, ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F1ED48584C2B02" , vaddpd(zmm1, zmm2, zmmword_ptr(rbx, rbp, 0, 128)));
@@ -5726,7 +5718,6 @@ static void ASMJIT_NOINLINE testX64AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F27E08724C1A08" , vcvtneps2bf16(xmm1, xmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F27E28724C1A04" , vcvtneps2bf16(xmm1, ymmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F27E4872CA" , vcvtneps2bf16(ymm1, zmm2));
TEST_INSTRUCTION("62F27E48724C1A02" , vcvtneps2bf16(ymm1, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F27E48724C1A02" , vcvtneps2bf16(ymm1, zmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F1FF48E6CA" , vcvtpd2dq(ymm1, zmm2));
TEST_INSTRUCTION("62F1FF48E64C1A02" , vcvtpd2dq(ymm1, ptr(rdx, rbx, 0, 128)));
@@ -5964,12 +5955,6 @@ static void ASMJIT_NOINLINE testX64AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F1ED485ECB" , vdivpd(zmm1, zmm2, zmm3));
TEST_INSTRUCTION("62F1ED485E4C2B02" , vdivpd(zmm1, zmm2, ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F1ED485E4C2B02" , vdivpd(zmm1, zmm2, zmmword_ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F2FD48C8CA" , vexp2pd(zmm1, zmm2));
TEST_INSTRUCTION("62F2FD48C84C1A02" , vexp2pd(zmm1, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F2FD48C84C1A02" , vexp2pd(zmm1, zmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F27D48C8CA" , vexp2ps(zmm1, zmm2));
TEST_INSTRUCTION("62F27D48C84C1A02" , vexp2ps(zmm1, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F27D48C84C1A02" , vexp2ps(zmm1, zmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F2FD0888CA" , vexpandpd(xmm1, xmm2));
TEST_INSTRUCTION("62F2FD08884C1A10" , vexpandpd(xmm1, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F2FD08884C1A10" , vexpandpd(xmm1, xmmword_ptr(rdx, rbx, 0, 128)));
@@ -6180,14 +6165,6 @@ static void ASMJIT_NOINLINE testX64AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F27D09924C1A20" , k(k1).vgatherdps(xmm1, ptr(rdx, xmm3, 0, 128)));
TEST_INSTRUCTION("62F27D29924C1A20" , k(k1).vgatherdps(ymm1, ptr(rdx, ymm3, 0, 128)));
TEST_INSTRUCTION("62F27D49924C1A20" , k(k1).vgatherdps(zmm1, ptr(rdx, zmm3, 0, 128)));
TEST_INSTRUCTION("62F2FD49C64C1110" , k(k1).vgatherpf0dpd(ptr(rcx, ymm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C64C1120" , k(k1).vgatherpf0dps(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C74C1110" , k(k1).vgatherpf0qpd(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C74C1120" , k(k1).vgatherpf0qps(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C6541110" , k(k1).vgatherpf1dpd(ptr(rcx, ymm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C6541120" , k(k1).vgatherpf1dps(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C7541110" , k(k1).vgatherpf1qpd(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C7541120" , k(k1).vgatherpf1qps(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD09934C1A10" , k(k1).vgatherqpd(xmm1, ptr(rdx, xmm3, 0, 128)));
TEST_INSTRUCTION("62F2FD29934C1A10" , k(k1).vgatherqpd(ymm1, ptr(rdx, ymm3, 0, 128)));
TEST_INSTRUCTION("62F2FD49934C1A10" , k(k1).vgatherqpd(zmm1, ptr(rdx, zmm3, 0, 128)));
@@ -6460,10 +6437,6 @@ static void ASMJIT_NOINLINE testX64AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F2DF4868D1" , vp2intersectq(k2, k3, zmm4, zmm1));
TEST_INSTRUCTION("62F2DF4868541102" , vp2intersectq(k2, k3, zmm4, ptr(rcx, rdx, 0, 128)));
TEST_INSTRUCTION("62F2DF4868541102" , vp2intersectq(k2, k3, zmm4, zmmword_ptr(rcx, rdx, 0, 128)));
TEST_INSTRUCTION("62F25F48524C1A08" , vp4dpwssd(zmm1, zmm4, zmm5, zmm6, zmm7, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F25F48524C1A08" , vp4dpwssd(zmm1, zmm4, zmm5, zmm6, zmm7, xmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F25F48534C1A08" , vp4dpwssds(zmm1, zmm4, zmm5, zmm6, zmm7, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F25F48534C1A08" , vp4dpwssds(zmm1, zmm4, zmm5, zmm6, zmm7, xmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F27D481CCA" , vpabsb(zmm1, zmm2));
TEST_INSTRUCTION("62F27D481C4C1A02" , vpabsb(zmm1, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F27D481C4C1A02" , vpabsb(zmm1, zmmword_ptr(rdx, rbx, 0, 128)));
@@ -8088,18 +8061,6 @@ static void ASMJIT_NOINLINE testX64AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F26D084DCB" , vrcp14ss(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F26D084D4C2B20" , vrcp14ss(xmm1, xmm2, ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F26D084D4C2B20" , vrcp14ss(xmm1, xmm2, dword_ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F2FD48CACA" , vrcp28pd(zmm1, zmm2));
TEST_INSTRUCTION("62F2FD48CA4C1A02" , vrcp28pd(zmm1, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F2FD48CA4C1A02" , vrcp28pd(zmm1, zmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F27D48CACA" , vrcp28ps(zmm1, zmm2));
TEST_INSTRUCTION("62F27D48CA4C1A02" , vrcp28ps(zmm1, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F27D48CA4C1A02" , vrcp28ps(zmm1, zmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F2ED08CBCB" , vrcp28sd(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F2ED08CB4C2B10" , vrcp28sd(xmm1, xmm2, ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F2ED08CB4C2B10" , vrcp28sd(xmm1, xmm2, qword_ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F26D08CBCB" , vrcp28ss(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F26D08CB4C2B20" , vrcp28ss(xmm1, xmm2, ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F26D08CB4C2B20" , vrcp28ss(xmm1, xmm2, dword_ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F3FD0856CA01" , vreducepd(xmm1, xmm2, 1));
TEST_INSTRUCTION("62F3FD08564C1A0801" , vreducepd(xmm1, ptr(rdx, rbx, 0, 128), 1));
TEST_INSTRUCTION("62F3FD08564C1A0801" , vreducepd(xmm1, xmmword_ptr(rdx, rbx, 0, 128), 1));
@@ -8172,18 +8133,6 @@ static void ASMJIT_NOINLINE testX64AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F26D084FCB" , vrsqrt14ss(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F26D084F4C2B20" , vrsqrt14ss(xmm1, xmm2, ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F26D084F4C2B20" , vrsqrt14ss(xmm1, xmm2, dword_ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F2FD48CCCA" , vrsqrt28pd(zmm1, zmm2));
TEST_INSTRUCTION("62F2FD48CC4C1A02" , vrsqrt28pd(zmm1, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F2FD48CC4C1A02" , vrsqrt28pd(zmm1, zmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F27D48CCCA" , vrsqrt28ps(zmm1, zmm2));
TEST_INSTRUCTION("62F27D48CC4C1A02" , vrsqrt28ps(zmm1, ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F27D48CC4C1A02" , vrsqrt28ps(zmm1, zmmword_ptr(rdx, rbx, 0, 128)));
TEST_INSTRUCTION("62F2ED08CDCB" , vrsqrt28sd(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F2ED08CD4C2B10" , vrsqrt28sd(xmm1, xmm2, ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F2ED08CD4C2B10" , vrsqrt28sd(xmm1, xmm2, qword_ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F26D08CDCB" , vrsqrt28ss(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F26D08CD4C2B20" , vrsqrt28ss(xmm1, xmm2, ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F26D08CD4C2B20" , vrsqrt28ss(xmm1, xmm2, dword_ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F2ED082CCB" , vscalefpd(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F2ED082C4C2B08" , vscalefpd(xmm1, xmm2, ptr(rbx, rbp, 0, 128)));
TEST_INSTRUCTION("62F2ED082C4C2B08" , vscalefpd(xmm1, xmm2, xmmword_ptr(rbx, rbp, 0, 128)));
@@ -8214,14 +8163,6 @@ static void ASMJIT_NOINLINE testX64AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F27D09A25C1120" , k(k1).vscatterdps(ptr(rcx, xmm2, 0, 128), xmm3));
TEST_INSTRUCTION("62F27D29A25C1120" , k(k1).vscatterdps(ptr(rcx, ymm2, 0, 128), ymm3));
TEST_INSTRUCTION("62F27D49A25C1120" , k(k1).vscatterdps(ptr(rcx, zmm2, 0, 128), zmm3));
TEST_INSTRUCTION("62F2FD49C66C1110" , k(k1).vscatterpf0dpd(ptr(rcx, ymm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C66C1120" , k(k1).vscatterpf0dps(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C76C1110" , k(k1).vscatterpf0qpd(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C76C1120" , k(k1).vscatterpf0qps(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C6741110" , k(k1).vscatterpf1dpd(ptr(rcx, ymm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C6741120" , k(k1).vscatterpf1dps(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C7741110" , k(k1).vscatterpf1qpd(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C7741120" , k(k1).vscatterpf1qps(ptr(rcx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD09A35C1110" , k(k1).vscatterqpd(ptr(rcx, xmm2, 0, 128), xmm3));
TEST_INSTRUCTION("62F2FD29A35C1110" , k(k1).vscatterqpd(ptr(rcx, ymm2, 0, 128), ymm3));
TEST_INSTRUCTION("62F2FD49A35C1110" , k(k1).vscatterqpd(ptr(rcx, zmm2, 0, 128), zmm3));

59
test/asmjit_test_assembler_x86.cpp
View File

@@ -5025,14 +5025,6 @@ static void ASMJIT_NOINLINE testX86AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("C4E1ED47CB" , kxord(k1, k2, k3));
TEST_INSTRUCTION("C4E1EC47CB" , kxorq(k1, k2, k3));
TEST_INSTRUCTION("C5EC47CB" , kxorw(k1, k2, k3));
TEST_INSTRUCTION("62F25F489A4C1A08" , v4fmaddps(zmm1, zmm4, zmm5, zmm6, zmm7, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F25F489A4C1A08" , v4fmaddps(zmm1, zmm4, zmm5, zmm6, zmm7, xmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F25F089B4C1A08" , v4fmaddss(xmm1, xmm4, xmm5, xmm6, xmm7, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F25F089B4C1A08" , v4fmaddss(xmm1, xmm4, xmm5, xmm6, xmm7, xmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F25F48AA4C1A08" , v4fnmaddps(zmm1, zmm4, zmm5, zmm6, zmm7, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F25F48AA4C1A08" , v4fnmaddps(zmm1, zmm4, zmm5, zmm6, zmm7, xmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F25F08AB4C1A08" , v4fnmaddss(xmm1, xmm4, xmm5, xmm6, xmm7, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F25F08AB4C1A08" , v4fnmaddss(xmm1, xmm4, xmm5, xmm6, xmm7, xmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F1ED4858CB" , vaddpd(zmm1, zmm2, zmm3));
TEST_INSTRUCTION("62F1ED48584C2B02" , vaddpd(zmm1, zmm2, ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F1ED48584C2B02" , vaddpd(zmm1, zmm2, zmmword_ptr(ebx, ebp, 0, 128)));
@@ -5206,7 +5198,6 @@ static void ASMJIT_NOINLINE testX86AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F27E08724C1A08" , vcvtneps2bf16(xmm1, xmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F27E28724C1A04" , vcvtneps2bf16(xmm1, ymmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F27E4872CA" , vcvtneps2bf16(ymm1, zmm2));
TEST_INSTRUCTION("62F27E48724C1A02" , vcvtneps2bf16(ymm1, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F27E48724C1A02" , vcvtneps2bf16(ymm1, zmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F1FF48E6CA" , vcvtpd2dq(ymm1, zmm2));
TEST_INSTRUCTION("62F1FF48E64C1A02" , vcvtpd2dq(ymm1, ptr(edx, ebx, 0, 128)));
@@ -5428,12 +5419,6 @@ static void ASMJIT_NOINLINE testX86AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F26E4852CB" , vdpbf16ps(zmm1, zmm2, zmm3));
TEST_INSTRUCTION("62F26E48524C2B02" , vdpbf16ps(zmm1, zmm2, ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F26E48524C2B02" , vdpbf16ps(zmm1, zmm2, zmmword_ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F2FD48C8CA" , vexp2pd(zmm1, zmm2));
TEST_INSTRUCTION("62F2FD48C84C1A02" , vexp2pd(zmm1, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F2FD48C84C1A02" , vexp2pd(zmm1, zmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F27D48C8CA" , vexp2ps(zmm1, zmm2));
TEST_INSTRUCTION("62F27D48C84C1A02" , vexp2ps(zmm1, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F27D48C84C1A02" , vexp2ps(zmm1, zmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F2FD0888CA" , vexpandpd(xmm1, xmm2));
TEST_INSTRUCTION("62F2FD08884C1A10" , vexpandpd(xmm1, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F2FD08884C1A10" , vexpandpd(xmm1, xmmword_ptr(edx, ebx, 0, 128)));
@@ -5644,14 +5629,6 @@ static void ASMJIT_NOINLINE testX86AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F27D09924C1A20" , k(k1).vgatherdps(xmm1, ptr(edx, xmm3, 0, 128)));
TEST_INSTRUCTION("62F27D29924C1A20" , k(k1).vgatherdps(ymm1, ptr(edx, ymm3, 0, 128)));
TEST_INSTRUCTION("62F27D49924C1A20" , k(k1).vgatherdps(zmm1, ptr(edx, zmm3, 0, 128)));
TEST_INSTRUCTION("62F2FD49C64C1110" , k(k1).vgatherpf0dpd(ptr(ecx, ymm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C64C1120" , k(k1).vgatherpf0dps(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C74C1110" , k(k1).vgatherpf0qpd(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C74C1120" , k(k1).vgatherpf0qps(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C6541110" , k(k1).vgatherpf1dpd(ptr(ecx, ymm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C6541120" , k(k1).vgatherpf1dps(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C7541110" , k(k1).vgatherpf1qpd(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C7541120" , k(k1).vgatherpf1qps(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD09934C1A10" , k(k1).vgatherqpd(xmm1, ptr(edx, xmm3, 0, 128)));
TEST_INSTRUCTION("62F2FD29934C1A10" , k(k1).vgatherqpd(ymm1, ptr(edx, ymm3, 0, 128)));
TEST_INSTRUCTION("62F2FD49934C1A10" , k(k1).vgatherqpd(zmm1, ptr(edx, zmm3, 0, 128)));
@@ -5920,10 +5897,6 @@ static void ASMJIT_NOINLINE testX86AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F2DF4868D1" , vp2intersectq(k2, k3, zmm4, zmm1));
TEST_INSTRUCTION("62F2DF4868541102" , vp2intersectq(k2, k3, zmm4, ptr(ecx, edx, 0, 128)));
TEST_INSTRUCTION("62F2DF4868541102" , vp2intersectq(k2, k3, zmm4, zmmword_ptr(ecx, edx, 0, 128)));
TEST_INSTRUCTION("62F25F48524C1A08" , vp4dpwssd(zmm1, zmm4, zmm5, zmm6, zmm7, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F25F48524C1A08" , vp4dpwssd(zmm1, zmm4, zmm5, zmm6, zmm7, xmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F25F48534C1A08" , vp4dpwssds(zmm1, zmm4, zmm5, zmm6, zmm7, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F25F48534C1A08" , vp4dpwssds(zmm1, zmm4, zmm5, zmm6, zmm7, xmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F27D481CCA" , vpabsb(zmm1, zmm2));
TEST_INSTRUCTION("62F27D481C4C1A02" , vpabsb(zmm1, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F27D481C4C1A02" , vpabsb(zmm1, zmmword_ptr(edx, ebx, 0, 128)));
@@ -7545,18 +7518,6 @@ static void ASMJIT_NOINLINE testX86AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F26D084DCB" , vrcp14ss(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F26D084D4C2B20" , vrcp14ss(xmm1, xmm2, ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F26D084D4C2B20" , vrcp14ss(xmm1, xmm2, dword_ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F2FD48CACA" , vrcp28pd(zmm1, zmm2));
TEST_INSTRUCTION("62F2FD48CA4C1A02" , vrcp28pd(zmm1, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F2FD48CA4C1A02" , vrcp28pd(zmm1, zmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F27D48CACA" , vrcp28ps(zmm1, zmm2));
TEST_INSTRUCTION("62F27D48CA4C1A02" , vrcp28ps(zmm1, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F27D48CA4C1A02" , vrcp28ps(zmm1, zmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F2ED08CBCB" , vrcp28sd(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F2ED08CB4C2B10" , vrcp28sd(xmm1, xmm2, ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F2ED08CB4C2B10" , vrcp28sd(xmm1, xmm2, qword_ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F26D08CBCB" , vrcp28ss(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F26D08CB4C2B20" , vrcp28ss(xmm1, xmm2, ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F26D08CB4C2B20" , vrcp28ss(xmm1, xmm2, dword_ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F3FD0856CA01" , vreducepd(xmm1, xmm2, 1));
TEST_INSTRUCTION("62F3FD08564C1A0801" , vreducepd(xmm1, ptr(edx, ebx, 0, 128), 1));
TEST_INSTRUCTION("62F3FD08564C1A0801" , vreducepd(xmm1, xmmword_ptr(edx, ebx, 0, 128), 1));
@@ -7629,18 +7590,6 @@ static void ASMJIT_NOINLINE testX86AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F26D084FCB" , vrsqrt14ss(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F26D084F4C2B20" , vrsqrt14ss(xmm1, xmm2, ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F26D084F4C2B20" , vrsqrt14ss(xmm1, xmm2, dword_ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F2FD48CCCA" , vrsqrt28pd(zmm1, zmm2));
TEST_INSTRUCTION("62F2FD48CC4C1A02" , vrsqrt28pd(zmm1, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F2FD48CC4C1A02" , vrsqrt28pd(zmm1, zmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F27D48CCCA" , vrsqrt28ps(zmm1, zmm2));
TEST_INSTRUCTION("62F27D48CC4C1A02" , vrsqrt28ps(zmm1, ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F27D48CC4C1A02" , vrsqrt28ps(zmm1, zmmword_ptr(edx, ebx, 0, 128)));
TEST_INSTRUCTION("62F2ED08CDCB" , vrsqrt28sd(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F2ED08CD4C2B10" , vrsqrt28sd(xmm1, xmm2, ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F2ED08CD4C2B10" , vrsqrt28sd(xmm1, xmm2, qword_ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F26D08CDCB" , vrsqrt28ss(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F26D08CD4C2B20" , vrsqrt28ss(xmm1, xmm2, ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F26D08CD4C2B20" , vrsqrt28ss(xmm1, xmm2, dword_ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F2ED082CCB" , vscalefpd(xmm1, xmm2, xmm3));
TEST_INSTRUCTION("62F2ED082C4C2B08" , vscalefpd(xmm1, xmm2, ptr(ebx, ebp, 0, 128)));
TEST_INSTRUCTION("62F2ED082C4C2B08" , vscalefpd(xmm1, xmm2, xmmword_ptr(ebx, ebp, 0, 128)));
@@ -7671,14 +7620,6 @@ static void ASMJIT_NOINLINE testX86AssemblerAVX512(AssemblerTester<x86::Assemble
TEST_INSTRUCTION("62F27D09A25C1120" , k(k1).vscatterdps(ptr(ecx, xmm2, 0, 128), xmm3));
TEST_INSTRUCTION("62F27D29A25C1120" , k(k1).vscatterdps(ptr(ecx, ymm2, 0, 128), ymm3));
TEST_INSTRUCTION("62F27D49A25C1120" , k(k1).vscatterdps(ptr(ecx, zmm2, 0, 128), zmm3));
TEST_INSTRUCTION("62F2FD49C66C1110" , k(k1).vscatterpf0dpd(ptr(ecx, ymm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C66C1120" , k(k1).vscatterpf0dps(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C76C1110" , k(k1).vscatterpf0qpd(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C76C1120" , k(k1).vscatterpf0qps(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C6741110" , k(k1).vscatterpf1dpd(ptr(ecx, ymm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C6741120" , k(k1).vscatterpf1dps(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD49C7741110" , k(k1).vscatterpf1qpd(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F27D49C7741120" , k(k1).vscatterpf1qps(ptr(ecx, zmm2, 0, 128)));
TEST_INSTRUCTION("62F2FD09A35C1110" , k(k1).vscatterqpd(ptr(ecx, xmm2, 0, 128), xmm3));
TEST_INSTRUCTION("62F2FD29A35C1110" , k(k1).vscatterqpd(ptr(ecx, ymm2, 0, 128), ymm3));
TEST_INSTRUCTION("62F2FD49A35C1110" , k(k1).vscatterqpd(ptr(ecx, zmm2, 0, 128), zmm3));

1
test/asmjit_test_compiler.cpp
View File

@@ -96,6 +96,7 @@ int TestApp::run() {
FormatOptions formatOptions;
formatOptions.addFlags(
FormatFlags::kMachineCode |
FormatFlags::kShowAliases |
FormatFlags::kExplainImms |
FormatFlags::kRegCasts );
formatOptions.setIndentation(FormatIndentationGroup::kCode, 2);

8
test/asmjit_test_instinfo.cpp
View File

@@ -173,6 +173,14 @@ static void testX86Arch() {
printInfoExtra(arch, Inst::kIdVaddpd, InstOptions::kNone, k1, zmm0, zmm1, zmm2);
printInfoExtra(arch, Inst::kIdVaddpd, InstOptions::kX86_ZMask, k1, zmm0, zmm1, zmm2);
printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, xmm0, xmm1);
printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, ymm0, xmm1);
printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, zmm0, ymm1);
printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, xmm0, ptr(rsi));
printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, ymm0, ptr(rsi));
printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, zmm0, ptr(rsi));
#endif // !ASMJIT_NO_X86
}

36
test/asmjit_test_perf_x86.cpp
View File

@@ -2456,8 +2456,6 @@ static void generateAvx512SequenceInternalRegOnly(
cc.evex().vdivps(zmmA, zmmB, zmmC);
cc.evex().vdivsd(xmmA, xmmB, xmmC);
cc.evex().vdivss(xmmA, xmmB, xmmC);
cc.evex().vexp2pd(zmmA, zmmB);
cc.evex().vexp2ps(zmmA, zmmB);
cc.evex().vexpandpd(xmmA, xmmB);
cc.evex().vexpandpd(ymmA, ymmB);
cc.evex().vexpandpd(zmmA, zmmB);
@@ -3447,10 +3445,6 @@ static void generateAvx512SequenceInternalRegOnly(
cc.evex().vrcp14ps(zmmA, zmmB);
cc.evex().vrcp14sd(xmmA, xmmB, xmmC);
cc.evex().vrcp14ss(xmmA, xmmB, xmmC);
cc.evex().vrcp28pd(zmmA, zmmB);
cc.evex().vrcp28ps(zmmA, zmmB);
cc.evex().vrcp28sd(xmmA, xmmB, xmmC);
cc.evex().vrcp28ss(xmmA, xmmB, xmmC);
cc.evex().vreducepd(xmmA, xmmB, 0);
cc.evex().vreducepd(ymmA, ymmB, 0);
cc.evex().vreducepd(zmmA, zmmB, 0);
@@ -3475,10 +3469,6 @@ static void generateAvx512SequenceInternalRegOnly(
cc.evex().vrsqrt14ps(zmmA, zmmB);
cc.evex().vrsqrt14sd(xmmA, xmmB, xmmC);
cc.evex().vrsqrt14ss(xmmA, xmmB, xmmC);
cc.evex().vrsqrt28pd(zmmA, zmmB);
cc.evex().vrsqrt28ps(zmmA, zmmB);
cc.evex().vrsqrt28sd(xmmA, xmmB, xmmC);
cc.evex().vrsqrt28ss(xmmA, xmmB, xmmC);
cc.evex().vscalefpd(xmmA, xmmB, xmmC);
cc.evex().vscalefpd(ymmA, ymmB, ymmC);
cc.evex().vscalefpd(zmmA, zmmB, zmmC);
@@ -3778,8 +3768,6 @@ static void generateAvx512SequenceInternalRegMem(
cc.evex().vdivps(zmmA, zmmB, m);
cc.evex().vdivsd(xmmA, xmmB, m);
cc.evex().vdivss(xmmA, xmmB, m);
cc.evex().vexp2pd(zmmA, m);
cc.evex().vexp2ps(zmmA, m);
cc.evex().vexpandpd(xmmA, m);
cc.evex().vexpandpd(ymmA, m);
cc.evex().vexpandpd(zmmA, m);
@@ -3953,14 +3941,6 @@ static void generateAvx512SequenceInternalRegMem(
cc.evex().k(kA).vgatherdps(xmmA, vx_ptr);
cc.evex().k(kA).vgatherdps(ymmA, vy_ptr);
cc.evex().k(kA).vgatherdps(zmmA, vz_ptr);
cc.evex().k(kA).vgatherpf0dpd(vy_ptr);
cc.evex().k(kA).vgatherpf0dps(vz_ptr);
cc.evex().k(kA).vgatherpf0qpd(vz_ptr);
cc.evex().k(kA).vgatherpf0qps(vz_ptr);
cc.evex().k(kA).vgatherpf1dpd(vy_ptr);
cc.evex().k(kA).vgatherpf1dps(vz_ptr);
cc.evex().k(kA).vgatherpf1qpd(vz_ptr);
cc.evex().k(kA).vgatherpf1qps(vz_ptr);
cc.evex().k(kA).vgatherqpd(xmmA, vx_ptr);
cc.evex().k(kA).vgatherqpd(ymmA, vy_ptr);
cc.evex().k(kA).vgatherqpd(zmmA, vz_ptr);
@@ -4793,10 +4773,6 @@ static void generateAvx512SequenceInternalRegMem(
cc.evex().vrcp14ps(zmmA, m);
cc.evex().vrcp14sd(xmmA, xmmB, m);
cc.evex().vrcp14ss(xmmA, xmmB, m);
cc.evex().vrcp28pd(zmmA, m);
cc.evex().vrcp28ps(zmmA, m);
cc.evex().vrcp28sd(xmmA, xmmB, m);
cc.evex().vrcp28ss(xmmA, xmmB, m);
cc.evex().vreducepd(xmmA, m, 0);
cc.evex().vreducepd(ymmA, m, 0);
cc.evex().vreducepd(zmmA, m, 0);
@@ -4821,10 +4797,6 @@ static void generateAvx512SequenceInternalRegMem(
cc.evex().vrsqrt14ps(zmmA, m);
cc.evex().vrsqrt14sd(xmmA, xmmB, m);
cc.evex().vrsqrt14ss(xmmA, xmmB, m);
cc.evex().vrsqrt28pd(zmmA, m);
cc.evex().vrsqrt28ps(zmmA, m);
cc.evex().vrsqrt28sd(xmmA, xmmB, m);
cc.evex().vrsqrt28ss(xmmA, xmmB, m);
cc.evex().vscalefpd(xmmA, xmmB, m);
cc.evex().vscalefpd(ymmA, ymmB, m);
cc.evex().vscalefpd(zmmA, zmmB, m);
@@ -4839,14 +4811,6 @@ static void generateAvx512SequenceInternalRegMem(
cc.evex().k(kA).vscatterdps(vx_ptr, xmmB);
cc.evex().k(kA).vscatterdps(vy_ptr, ymmB);
cc.evex().k(kA).vscatterdps(vz_ptr, zmmB);
cc.evex().k(kA).vscatterpf0dpd(vy_ptr);
cc.evex().k(kA).vscatterpf0dps(vz_ptr);
cc.evex().k(kA).vscatterpf0qpd(vz_ptr);
cc.evex().k(kA).vscatterpf0qps(vz_ptr);
cc.evex().k(kA).vscatterpf1dpd(vy_ptr);
cc.evex().k(kA).vscatterpf1dps(vz_ptr);
cc.evex().k(kA).vscatterpf1qpd(vz_ptr);
cc.evex().k(kA).vscatterpf1qps(vz_ptr);
cc.evex().k(kA).vscatterqpd(vx_ptr, xmmB);
cc.evex().k(kA).vscatterqpd(vy_ptr, ymmB);
cc.evex().k(kA).vscatterqpd(vz_ptr, zmmB);

3
tools/generator-commons.js
View File

@@ -215,6 +215,9 @@ exports.ArrayUtils = ArrayUtils;
class StringUtils {
static asString(x) { return String(x); }
static makeEnumName(name) {
return name ? name.charAt(0).toUpperCase() + name.substring(1) : "";
}
static countOf(s, pattern) {
if (!pattern)
FATAL(`Pattern cannot be empty`);

8
tools/generator-cxx.js
View File

@@ -9,7 +9,7 @@ const FATAL = commons.FATAL;
// Utilities to convert primitives to C++ code.
class Utils {
static toHex(val, pad) {
static toHexRaw(val, pad) {
if (val < 0)
val = 0xFFFFFFFF + val + 1;
@@ -17,7 +17,11 @@ class Utils {
if (pad != null && s.length < pad)
s = "0".repeat(pad - s.length) + s;
return "0x" + s.toUpperCase();
return s.toUpperCase();
}
static toHex(val, pad) {
return "0x" + Utils.toHexRaw(val, pad);
}
static capitalize(s) {

8
tools/tablegen-a64.js
View File

@@ -132,8 +132,8 @@ class ArmTableGen extends core.TableGen {
var m;
while ((m = re.exec(stringData)) !== null) {
var enum_ = m[1];
var name = enum_ === "None" ? "" : enum_.toLowerCase();
var enumName = m[1];
var name = enumName === "None" ? "" : enumName.toLowerCase();
var encoding = m[2].trim();
var opcodeData = m[3].trim();
var rwInfo = m[4].trim();
@@ -149,11 +149,11 @@ class ArmTableGen extends core.TableGen {
encodingDataIndex === "encodingDataIndex")
continue;
this.addInst({
this.addInstruction({
id : 0, // Instruction id (numeric value).
name : name, // Instruction name.
displayName : displayName, // Instruction name to display.
enum : enum_, // Instruction enum without `kId` prefix.
enum : enumName, // Instruction enum without `kId` prefix.
encoding : encoding, // Opcode encoding.
opcodeData : opcodeData, // Opcode data.
opcodeDataIndex : -1, // Opcode data index.

385
tools/tablegen-x86.js
View File

@@ -50,7 +50,7 @@ class Filter {
const result = [];
const known = {};
for (var i = 0; i < instArray.length; i++) {
for (let i = 0; i < instArray.length; i++) {
const inst = instArray[i];
if (inst.altForm)
continue;
@@ -68,9 +68,9 @@ class Filter {
static noAltForm(instArray) {
const result = [];
for (var i = 0; i < instArray.length; i++) {
for (let i = 0; i < instArray.length; i++) {
const inst = instArray[i];
if (inst.altForm)
if (inst.alt)
continue;
result.push(inst);
}
@@ -109,11 +109,11 @@ const VexToEvexMap = {
class GenUtils {
static cpuArchOf(dbInsts) {
var anyArch = false;
var x86Arch = false;
var x64Arch = false;
let anyArch = false;
let x86Arch = false;
let x64Arch = false;
for (var i = 0; i < dbInsts.length; i++) {
for (let i = 0; i < dbInsts.length; i++) {
const dbInst = dbInsts[i];
if (dbInst.arch === "ANY") anyArch = true;
if (dbInst.arch === "X86") x86Arch = true;
@@ -203,16 +203,15 @@ class GenUtils {
static flagsOf(dbInsts) {
const f = Object.create(null);
var i, j;
var mib = dbInsts.length > 0 && /^(?:bndldx|bndstx)$/.test(dbInsts[0].name);
let mib = dbInsts.length > 0 && /^(?:bndldx|bndstx)$/.test(dbInsts[0].name);
if (mib)
f.Mib = true;
var mmx = false;
var vec = false;
let mmx = false;
let vec = false;
for (i = 0; i < dbInsts.length; i++) {
for (let i = 0; i < dbInsts.length; i++) {
const dbInst = dbInsts[i];
const operands = dbInst.operands;
@@ -222,7 +221,7 @@ class GenUtils {
if (dbInst.name === "vzeroall" || dbInst.name === "vzeroupper")
vec = true;
for (j = 0; j < operands.length; j++) {
for (let j = 0; j < operands.length; j++) {
const op = operands[j];
if (op.reg === "mm")
mmx = true;
@@ -235,7 +234,7 @@ class GenUtils {
if (mmx) f.Mmx = true;
if (vec) f.Vec = true;
for (i = 0; i < dbInsts.length; i++) {
for (let i = 0; i < dbInsts.length; i++) {
const dbInst = dbInsts[i];
const operands = dbInst.operands;
@@ -249,7 +248,7 @@ class GenUtils {
if (dbInst.k === "zeroing" ) f.Avx512ImplicitZ = true;
if (dbInst.category.FPU) {
for (var j = 0; j < operands.length; j++) {
for (let j = 0; j < operands.length; j++) {
const op = operands[j];
if (op.memSize === 16) f.FpuM16 = true;
if (op.memSize === 32) f.FpuM32 = true;
@@ -296,7 +295,7 @@ class GenUtils {
}
static eqOps(aOps, aFrom, bOps, bFrom) {
var x = 0;
let x = 0;
for (;;) {
const aIndex = x + aFrom;
const bIndex = x + bFrom;
@@ -462,7 +461,9 @@ class X86TableGen extends core.TableGen {
// Get instructions (dbInsts) having the same name as understood by AsmJit.
query(name) {
return x86isa.query(name);
return x86isa.query({ name: name, filter: function(inst) {
return !inst.ext.APX_F && !inst.ext.AVX10_1 && !inst.ext.AVX10_2;
}});
}
// --------------------------------------------------------------------------
@@ -484,13 +485,13 @@ class X86TableGen extends core.TableGen {
"([^\\)]+)" + "\\)", // [08] OperationDataIndex.
"g");
var m;
let m;
while ((m = re.exec(data)) !== null) {
var enum_ = m[1];
var name = enum_ === "None" ? "" : enum_.toLowerCase();
var encoding = m[2].trim();
var opcode0 = m[3].trim();
var opcode1 = m[4].trim();
let enum_ = m[1];
let name = enum_ === "None" ? "" : enum_.toLowerCase();
let encoding = m[2].trim();
let opcode0 = m[3].trim();
let opcode1 = m[4].trim();
const dbInsts = this.query(name);
if (name && !dbInsts.length)
@@ -500,7 +501,9 @@ class X86TableGen extends core.TableGen {
const controlFlow = GenUtils.controlFlow(dbInsts);
const singleRegCase = GenUtils.singleRegCase(name);
this.addInst({
const aliasData = x86isa.aliasData(name);
this.addInstruction({
id : 0, // Instruction id (numeric value).
name : name, // Instruction name.
displayName : name, // Instruction name to display.
@@ -514,6 +517,8 @@ class X86TableGen extends core.TableGen {
controlFlow : controlFlow,
singleRegCase : singleRegCase,
aliases : aliasData,
mainOpcodeValue : -1, // Main opcode value (0.255 hex).
mainOpcodeIndex : -1, // Index to InstDB::_mainOpcodeTable.
altOpcodeIndex : -1, // Index to InstDB::_altOpcodeTable.
@@ -533,7 +538,7 @@ class X86TableGen extends core.TableGen {
}
merge() {
var s = StringUtils.format(this.insts, "", true, function(inst) {
let s = StringUtils.format(this.insts, "", true, function(inst) {
return "INST(" +
String(inst.enum ).padEnd(17) + ", " +
String(inst.encoding ).padEnd(19) + ", " +
@@ -563,12 +568,12 @@ class X86TableGen extends core.TableGen {
"wait" // Maps to `fwait`, which AsmJit uses instead.
]);
var out = "";
let out = "";
x86isa.instructionNames.forEach(function(name) {
var dbInsts = x86isa.query(name);
let dbInsts = x86isa.query(name);
if (!this.instMap[name] && ignored[name] !== true) {
console.log(`MISSING INSTRUCTION '${name}'`);
var inst = this.newInstFromGroup(dbInsts);
let inst = this.newInstFromGroup(dbInsts);
if (inst) {
out += " INST(" +
String(inst.enum ).padEnd(17) + ", " +
@@ -593,10 +598,10 @@ class X86TableGen extends core.TableGen {
}
function GetAccess(dbInst) {
var operands = dbInst.operands;
let operands = dbInst.operands;
if (!operands.length) return "";
var op = operands[0];
let op = operands[0];
if (op.read && op.write)
return "RW";
else if (op.read)
@@ -618,8 +623,8 @@ class X86TableGen extends core.TableGen {
for (let j = 0; j < dbi.operands.length; j++) {
s += ", ";
const op = dbi.operands[j];
var reg = op.reg;
var mem = op.mem;
let reg = op.reg;
let mem = op.mem;
if (op.isReg() && op.isMem()) {
if (choice == 0) mem = null;
@@ -653,27 +658,27 @@ class X86TableGen extends core.TableGen {
return results;
}
var dbi = dbInsts[0];
let dbi = dbInsts[0];
var id = this.insts.length;
var name = dbi.name;
var enum_ = name[0].toUpperCase() + name.substr(1);
let id = this.insts.length;
let name = dbi.name;
let enum_ = name[0].toUpperCase() + name.substr(1);
var opcode = dbi.opcodeHex;
var modR = dbi.modR;
var mm = dbi.mm;
var pp = dbi.pp;
var encoding = dbi.encoding;
var isVec = isVecPrefix(dbi.prefix);
var evexCount = 0;
let opcode = dbi.opcode.byte;
let modR = dbi.opcode.modr;
let mm = dbi.opcode.mm;
let pp = dbi.opcode.pp;
let encoding = dbi.encoding;
let isVec = isVecPrefix(dbi.prefix);
let evexCount = 0;
var access = GetAccess(dbi);
let access = GetAccess(dbi);
var vexL = undefined;
var vexW = undefined;
var evexW = undefined;
var cdshl = "_";
var tupleType = "_";
let vexL = undefined;
let vexW = undefined;
let evexW = undefined;
let cdshl = "_";
let tupleType = "_";
const tupleTypeToCDSHL = {
"FVM": "4",
@@ -687,12 +692,12 @@ class X86TableGen extends core.TableGen {
const emitMap = {};
for (var i = 0; i < dbInsts.length; i++) {
for (let i = 0; i < dbInsts.length; i++) {
dbi = dbInsts[i];
if (dbi.prefix === "VEX" || dbi.prefix === "XOP") {
var newVexL = String(dbi.l === "128" ? 0 : dbi.l === "256" ? 1 : dbi.l === "512" ? 2 : "_");
var newVexW = String(dbi.w === "W0" ? 0 : dbi.w === "W1" ? 1 : "_");
let newVexL = String(dbi.opcode.l === "128" ? 0 : dbi.opcode.l === "256" ? 1 : dbi.opcode.l === "512" ? 2 : "_");
let newVexW = String(dbi.opcode.w === "W0" ? 0 : dbi.opcode.w === "W1" ? 1 : "_");
if (vexL !== undefined && vexL !== newVexL)
vexL = "x";
@@ -706,7 +711,7 @@ class X86TableGen extends core.TableGen {
if (dbi.prefix === "EVEX") {
evexCount++;
var newEvexW = String(dbi.w === "W0" ? 0 : dbi.w === "W1" ? 1 : "_");
let newEvexW = String(dbi.opcode.w === "W0" ? 0 : dbi.opcode.w === "W1" ? 1 : "_");
if (evexW !== undefined && evexW !== newEvexW)
evexW = "x";
else
@@ -721,10 +726,10 @@ class X86TableGen extends core.TableGen {
}
}
if (opcode !== dbi.opcodeHex ) { console.log(`${dbi.name}: ISSUE: Opcode ${opcode} != ${dbi.opcodeHex}`); return null; }
if (modR !== dbi.modR ) { console.log(`${dbi.name}: ISSUE: ModR ${modR} != ${dbi.modR}`); return null; }
if (mm !== dbi.mm ) { console.log(`${dbi.name}: ISSUE: MM ${mm} != ${dbi.mm}`); return null; }
if (pp !== dbi.pp ) { console.log(`${dbi.name}: ISSUE: PP ${pp} != ${dbi.pp}`); return null; }
if (opcode !== dbi.opcode.byte) { console.log(`${dbi.name}: ISSUE: Opcode ${opcode} != ${dbi.opcode.byte}`); return null; }
if (modR !== dbi.opcode.modr) { console.log(`${dbi.name}: ISSUE: ModR ${modR} != ${dbi.opcode.modr}`); return null; }
if (mm !== dbi.opcode.mm ) { console.log(`${dbi.name}: ISSUE: MM ${mm} != ${dbi.opcode.mm}`); return null; }
if (pp !== dbi.opcode.pp ) { console.log(`${dbi.name}: ISSUE: PP ${pp} != ${dbi.opcode.pp}`); return null; }
if (encoding !== dbi.encoding ) { console.log(`${dbi.name}: ISSUE: Enc ${encoding} != ${dbi.encoding}`); return null; }
if (access !== GetAccess(dbi) ) { console.log(`${dbi.name}: ISSUE: Access ${access} != ${GetAccess(dbi)}`); return null; }
if (isVec != isVecPrefix(dbi.prefix)) { console.log(`${dbi.name}: ISSUE: Vex/Non-Vex mismatch`); return null; }
@@ -740,10 +745,10 @@ class X86TableGen extends core.TableGen {
if (tupleType !== "_")
cdshl = tupleTypeToCDSHL[tupleType] || "?";
var ppmm = pp.padEnd(2).replace(/ /g, "0") +
let ppmm = pp.padEnd(2).replace(/ /g, "0") +
mm.padEnd(4).replace(/ /g, "0") ;
var composed = composeOpCode({
let composed = composeOpCode({
type : evexCount == dbInsts.length ? "E" : isVec ? "V" : "O",
prefix: ppmm,
opcode: opcode,
@@ -804,11 +809,11 @@ class IdEnum extends core.IdEnum {
return features.filter(function(item) { return /^(AVX|FMA)/.test(item) === avx; });
}
var dbInsts = inst.dbInsts;
let dbInsts = inst.dbInsts;
if (!dbInsts.length) return "Invalid instruction id.";
var text = "";
var features = GenUtils.cpuFeaturesOf(dbInsts);
let text = "";
let features = GenUtils.cpuFeaturesOf(dbInsts);
const priorityFeatures = ["AVX_VNNI", "AVX_VNNI_INT8", "AVX_IFMA", "AVX_NE_CONVERT"];
@@ -840,7 +845,7 @@ class IdEnum extends core.IdEnum {
text += "}";
}
var arch = GenUtils.cpuArchOf(dbInsts);
let arch = GenUtils.cpuArchOf(dbInsts);
if (arch)
text += (text ? " " : "") + arch;
@@ -854,7 +859,7 @@ class IdEnum extends core.IdEnum {
class NameTable extends core.NameTable {
constructor() {
super("NameTable");
super("NameTable", null, true);
}
}
@@ -934,7 +939,7 @@ class AltOpcodeTable extends core.Task {
if (opcode === "0")
return ["00", 0];
var opcodeByte = "";
let opcodeByte = "";
const components = normalizeOpcodeComponents(splitOpcodeToComponents(opcode));
if (components[0] === "O_FPU") {
@@ -1006,10 +1011,10 @@ const cmpOp = StringUtils.makePriorityCompare([
]);
function StringifyOpArray(a, map) {
var s = "";
for (var i = 0; i < a.length; i++) {
let s = "";
for (let i = 0; i < a.length; i++) {
const op = a[i];
var mapped = null;
let mapped = null;
if (typeof map === "function")
mapped = map(op);
else if (hasOwn.call(map, op))
@@ -1039,11 +1044,10 @@ class OSignature {
const af = this.flags;
const bf = other.flags;
var k;
var indexKind = "";
var hasReg = false;
let hasReg = false;
let indexKind = "";
for (k in af) {
for (let k in af) {
const index = asmdb.x86.Utils.regIndexOf(k);
const kind = asmdb.x86.Utils.regKindOf(k);
@@ -1055,7 +1059,7 @@ class OSignature {
}
if (hasReg) {
for (k in bf) {
for (let k in bf) {
const index = asmdb.x86.Utils.regIndexOf(k);
if (index !== null && index !== -1) {
const kind = asmdb.x86.Utils.regKindOf(k);
@@ -1066,20 +1070,20 @@ class OSignature {
}
// Can merge...
for (k in bf)
for (let k in bf)
af[k] = true;
return true;
}
toString() {
var s = "";
var flags = this.flags;
let s = "";
let flags = this.flags;
for (var k in flags) {
for (let k in flags) {
if (k === "read" || k === "write" || k === "implicit" || k === "memDS" || k === "memES")
continue;
var x = k;
let x = k;
if (x === "memZAX") x = "zax";
if (x === "memZDI") x = "zdi";
if (x === "memZSI") x = "zsi";
@@ -1096,10 +1100,10 @@ class OSignature {
}
toAsmJitOpData() {
var opFlags = Object.create(null);
var regMask = 0;
let opFlags = Object.create(null);
let regMask = 0;
for (var k in this.flags) {
for (let k in this.flags) {
switch (k) {
case "r8lo" : opFlags.RegGpbLo = true; break;
case "r8hi" : opFlags.RegGpbHi = true; break;
@@ -1223,7 +1227,7 @@ class ISignature extends Array {
const len = this.length;
if (len !== other.length) return false;
for (var i = 0; i < len; i++)
for (let i = 0; i < len; i++)
if (!this[i].equals(other[i]))
return false;
@@ -1239,8 +1243,9 @@ class ISignature extends Array {
// ok = true;
// It's not ok if both signatures have different number of implicit operands.
if (!sameArch || this.implicit !== other.implicit)
if (!sameArch || this.implicit !== other.implicit) {
return false;
}
// It's not ok if both signatures have different number of operands.
const len = this.length;
@@ -1250,7 +1255,8 @@ class ISignature extends Array {
let xorIndex = -1;
for (let i = 0; i < len; i++) {
const xor = this[i].xor(other[i]);
if (xor === null) continue;
if (xor === null)
continue;
if (xorIndex === -1)
xorIndex = i;
@@ -1258,7 +1264,7 @@ class ISignature extends Array {
return false;
}
// Bail if mergeWidth at operand-level failed.
// Bail if mergeWith at operand-level failed.
if (xorIndex === -1 || !this[xorIndex].mergeWith(other[xorIndex]))
return false;
@@ -1271,12 +1277,16 @@ class ISignature extends Array {
}
class SignatureArray extends Array {
constructor(instructionName) {
super();
this.instructionName = instructionName;
}
// Iterate over all signatures and check which operands don't need explicit memory size.
calcImplicitMemSize(instName) {
// Calculates a hash-value (aka key) of all register operands specified by `regOps` in `inst`.
function keyOf(inst, regOps) {
var s = "";
for (var i = 0; i < inst.length; i++) {
let s = "";
for (let i = 0; i < inst.length; i++) {
const op = inst[i];
if (regOps & (1 << i))
s += "{" + ArrayUtils.sorted(ObjectUtils.and(op.flags, RegOp)).join("|") + "}";
@@ -1284,19 +1294,16 @@ class SignatureArray extends Array {
return s || "?";
}
var i;
var aIndex, bIndex;
for (aIndex = 0; aIndex < this.length; aIndex++) {
for (let aIndex = 0; aIndex < this.length; aIndex++) {
const aInst = this[aIndex];
const len = aInst.length;
var memOp = "";
var memPos = -1;
var regOps = 0;
let memOp = "";
let memPos = -1;
let regOps = 0;
// Check if this instruction signature has a memory operand of explicit size.
for (i = 0; i < len; i++) {
for (let i = 0; i < len; i++) {
const aOp = aInst[i];
const mem = ObjectUtils.findKey(aOp.flags, MemOp);
@@ -1328,12 +1335,12 @@ class SignatureArray extends Array {
const diffSizeSet = [];
const diffSizeHash = Object.create(null);
for (bIndex = 0; bIndex < this.length; bIndex++) {
for (let bIndex = 0; bIndex < this.length; bIndex++) {
const bInst = this[bIndex];
if (aIndex === bIndex || len !== bInst.length) continue;
var hasMatch = 1;
for (i = 0; i < len; i++) {
let hasMatch = 1;
for (let i = 0; i < len; i++) {
if (i === memPos) continue;
const reg = ObjectUtils.hasAny(bInst[i].flags, RegOp);
@@ -1368,14 +1375,14 @@ class SignatureArray extends Array {
//
// B) The memory operand has implicit-size if `diffSizeSet` contains different
// register signatures than `sameSizeSet`.
var implicit = true;
let implicit = true;
if (!diffSizeSet.length) {
// Case A:
}
else {
// Case B: Find collisions in `sameSizeSet` and `diffSizeSet`.
for (bIndex = 0; bIndex < sameSizeSet.length; bIndex++) {
for (let bIndex = 0; bIndex < sameSizeSet.length; bIndex++) {
const bInst = sameSizeSet[bIndex];
const key = keyOf(bInst, regOps);
@@ -1399,25 +1406,26 @@ class SignatureArray extends Array {
}
// Patch all instructions to accept implicit-size memory operand.
for (bIndex = 0; bIndex < sameSizeSet.length; bIndex++) {
for (let bIndex = 0; bIndex < sameSizeSet.length; bIndex++) {
const bInst = sameSizeSet[bIndex];
if (implicit) {
bInst[memPos].flags.mem = true;
}
if (!implicit)
if (!implicit) {
DEBUG(`${this.name}: Explicit: ${bInst}`);
}
}
}
}
compact() {
var didSomething = true;
let didSomething = true;
while (didSomething) {
didSomething = false;
for (var i = 0; i < this.length; i++) {
var row = this[i];
var j = i + 1;
for (let i = 0; i < this.length; i++) {
let row = this[i];
let j = i + 1;
while (j < this.length) {
if (row.mergeWith(this[j])) {
this.splice(j, 1);
@@ -1431,7 +1439,7 @@ class SignatureArray extends Array {
}
toString() {
return `[${this.join(", ")}]`;
return `[${this.join(",\n")}]`;
}
}
@@ -1467,12 +1475,12 @@ class InstSignatureTable extends core.Task {
const indexes = iSignatureMap[rows[0].data];
if (indexes === undefined) return -1;
for (var i = 0; i < indexes.length; i++) {
for (let i = 0; i < indexes.length; i++) {
const index = indexes[i];
if (index + len > iSignatureArr.length) continue;
var ok = true;
for (var j = 0; j < len; j++) {
let ok = true;
for (let j = 0; j < len; j++) {
if (iSignatureArr[index + j].data !== rows[j].data) {
ok = false;
break;
@@ -1489,7 +1497,7 @@ class InstSignatureTable extends core.Task {
function indexSignatures(signatures) {
const result = iSignatureArr.length;
for (var i = 0; i < signatures.length; i++) {
for (let i = 0; i < signatures.length; i++) {
const signature = signatures[i];
const idx = iSignatureArr.length;
@@ -1503,21 +1511,21 @@ class InstSignatureTable extends core.Task {
return result;
}
for (var len = this.maxOpRows; len >= 0; len--) {
for (let len = this.maxOpRows; len >= 0; len--) {
insts.forEach((inst) => {
const signatures = inst.signatures;
if (signatures.length === len) {
const signatureEntries = [];
for (var j = 0; j < len; j++) {
for (let j = 0; j < len; j++) {
const signature = signatures[j];
var signatureEntry = `ROW(${signature.length}, ${signature.x86 ? 1 : 0}, ${signature.x64 ? 1 : 0}, ${signature.implicit}`;
var signatureComment = signature.toString();
let signatureEntry = `ROW(${signature.length}, ${signature.x86 ? 1 : 0}, ${signature.x64 ? 1 : 0}, ${signature.implicit}`;
let signatureComment = signature.toString();
var x = 0;
let x = 0;
while (x < signature.length) {
const h = signature[x].toAsmJitOpData();
var index = -1;
let index = -1;
if (!hasOwn.call(oSignatureMap, h)) {
index = oSignatureArr.length;
oSignatureMap[h] = index;
@@ -1540,8 +1548,8 @@ class InstSignatureTable extends core.Task {
signatureEntries.push({ data: signatureEntry, comment: signatureComment, refs: 0 });
}
var count = signatureEntries.length;
var index = findSignaturesIndex(signatureEntries);
let count = signatureEntries.length;
let index = findSignaturesIndex(signatureEntries);
if (index === -1)
index = indexSignatures(signatureEntries);
@@ -1553,7 +1561,7 @@ class InstSignatureTable extends core.Task {
});
}
var s = `#define ROW(count, x86, x64, implicit, o0, o1, o2, o3, o4, o5) \\\n` +
let s = `#define ROW(count, x86, x64, implicit, o0, o1, o2, o3, o4, o5) \\\n` +
` { count, uint8_t(x86 ? uint8_t(InstDB::Mode::kX86) : uint8_t(0)) | \\\n` +
` (x64 ? uint8_t(InstDB::Mode::kX64) : uint8_t(0)) , \\\n` +
` implicit, \\\n` +
@@ -1573,9 +1581,9 @@ class InstSignatureTable extends core.Task {
makeSignatures(dbInsts) {
const instName = dbInsts.length ? dbInsts[0].name : "";
const signatures = new SignatureArray();
const signatures = new SignatureArray(instName);
for (var i = 0; i < dbInsts.length; i++) {
for (let i = 0; i < dbInsts.length; i++) {
const inst = dbInsts[i];
const ops = inst.operands;
@@ -1598,19 +1606,21 @@ class InstSignatureTable extends core.Task {
// 1a. mov reg, reg
// 1b. mov reg, mem
// 2b. mov mem, reg
var modrmCount = 1;
for (var modrm = 0; modrm < modrmCount; modrm++) {
var row = new ISignature(inst.name);
let modrmCount = 1;
for (let modrm = 0; modrm < modrmCount; modrm++) {
let row = new ISignature(inst.name);
row.x86 = (inst.arch === "ANY" || inst.arch === "X86");
row.x64 = (inst.arch === "ANY" || inst.arch === "X64");
for (var j = 0; j < ops.length; j++) {
var iop = ops[j];
let j;
for (j = 0; j < ops.length; j++) {
let iop = ops[j];
var reg = iop.reg;
var mem = iop.mem;
var imm = iop.imm;
var rel = iop.rel;
let reg = iop.reg;
let mem = iop.mem;
let imm = iop.imm;
let rel = iop.rel;
// Skip all instructions having implicit `imm` operand of `1`.
if (iop.immValue !== null)
@@ -1731,10 +1741,11 @@ class InstSignatureTable extends core.Task {
}
// Not equal if we terminated the loop.
if (j === ops.length)
if (j === ops.length) {
signatures.push(row);
}
}
}
if (signatures.length && GenUtils.canUseImplicitMemSize(instName))
signatures.calcImplicitMemSize(instName);
@@ -1765,10 +1776,10 @@ class AdditionalInfoTable extends core.Task {
insts.forEach((inst) => {
const dbInsts = inst.dbInsts;
var features = GenUtils.cpuFeaturesOf(dbInsts).map(function(f) { return `EXT(${f})`; }).join(", ");
let features = GenUtils.cpuFeaturesOf(dbInsts).map(function(f) { return `EXT(${f})`; }).join(", ");
if (!features) features = "0";
var [r, w] = this.rwFlagsOf(dbInsts);
let [r, w] = this.rwFlagsOf(dbInsts);
const rData = r.map(function(flag) { return `FLAG(${flag})`; }).join(" | ") || "0";
const wData = w.map(function(flag) { return `FLAG(${flag})`; }).join(" | ") || "0";
const instFlags = Object.create(null);
@@ -1815,7 +1826,7 @@ class AdditionalInfoTable extends core.Task {
inst.additionalInfoIndex = additionaInfoTable.addIndexed(`{ ${instFlagsIndex}, ${rwInfoIndex}, { ${features} } }`);
});
var s = `#define EXT(VAL) uint32_t(CpuFeatures::X86::k##VAL)\n` +
let s = `#define EXT(VAL) uint32_t(CpuFeatures::X86::k##VAL)\n` +
`const InstDB::AdditionalInfo InstDB::_additionalInfoTable[] = {\n${StringUtils.format(additionaInfoTable, kIndent, true)}\n};\n` +
`#undef EXT\n` +
`\n` +
@@ -1833,7 +1844,7 @@ class AdditionalInfoTable extends core.Task {
const r = Object.create(null);
const w = Object.create(null);
for (var i = 0; i < dbInsts.length; i++) {
for (let i = 0; i < dbInsts.length; i++) {
const dbInst = dbInsts[i];
// Omit special cases, this is handled well in C++ code.
@@ -1848,8 +1859,8 @@ class AdditionalInfoTable extends core.Task {
if (dbInst.name === "mov")
continue;
for (var reg in regs) {
var flag = "";
for (let reg in regs) {
let flag = "";
switch (reg) {
case "CF": flag = "CF"; break;
case "OF": flag = "OF"; break;
@@ -2000,13 +2011,13 @@ class InstRWInfoTable extends core.Task {
const rwInfoArray = [this.rwInfo(inst, o2Insts), this.rwInfo(inst, oxInsts)];
const rmInfoArray = [this.rmInfo(inst, o2Insts), this.rmInfo(inst, oxInsts)];
for (var i = 0; i < 2; i++) {
for (let i = 0; i < 2; i++) {
const rwInfo = rwInfoArray[i];
const rmInfo = rmInfoArray[i];
const rwOps = rwInfo.rwOps;
const rwOpsIndex = [];
for (var j = 0; j < rwOps.length; j++) {
for (let j = 0; j < rwOps.length; j++) {
const op = rwOps[j];
if (!op) {
rwOpsIndex.push(this.opInfoTable.addIndexed(noOpInfo));
@@ -2066,7 +2077,7 @@ class InstRWInfoTable extends core.Task {
}
});
var s = "";
let s = "";
s += "const uint8_t InstDB::rwInfoIndexA[Inst::_kIdCount] = {\n" + StringUtils.format(this.rwInfoIndexA, kIndent, -1) + "\n};\n";
s += "\n";
s += "const uint8_t InstDB::rwInfoIndexB[Inst::_kIdCount] = {\n" + StringUtils.format(this.rwInfoIndexB, kIndent, -1) + "\n};\n";
@@ -2091,17 +2102,17 @@ class InstRWInfoTable extends core.Task {
byteMaskFromBitRanges(ranges) {
const arr = [];
for (var i = 0; i < 64; i++)
for (let i = 0; i < 64; i++)
arr.push(0);
for (var i = 0; i < ranges.length; i++) {
for (let i = 0; i < ranges.length; i++) {
const start = ranges[i].start;
const end = ranges[i].end;
if (start < 0)
continue;
for (var j = start; j <= end; j++) {
for (let j = start; j <= end; j++) {
const bytePos = j >> 3;
if (bytePos < 0 || bytePos >= arr.length)
FATAL(`Range ${start}:${end} cannot be used to create a byte-mask`);
@@ -2109,8 +2120,8 @@ class InstRWInfoTable extends core.Task {
}
}
var s = "0x";
for (var i = arr.length - 4; i >= 0; i -= 4) {
let s = "0x";
for (let i = arr.length - 4; i >= 0; i -= 4) {
const value = (arr[i + 3] << 3) | (arr[i + 2] << 2) | (arr[i + 1] << 1) | arr[i];
s += value.toString(16).toUpperCase();
}
@@ -2142,18 +2153,18 @@ class InstRWInfoTable extends core.Task {
}
function queryRwGeneric(dbInsts, step) {
var rwOps = nullOps();
for (var i = 0; i < dbInsts.length; i++) {
let rwOps = nullOps();
for (let i = 0; i < dbInsts.length; i++) {
const dbInst = dbInsts[i];
const operands = dbInst.operands;
for (var j = 0; j < operands.length; j++) {
for (let j = 0; j < operands.length; j++) {
const op = operands[j];
if (!op.isRegOrMem())
continue;
const opSize = op.isReg() ? op.regSize : op.memSize;
var d = {
let d = {
access: op.read && op.write ? "X" : op.read ? "R" : op.write ? "W" : "?",
clc: 0,
flags: {},
@@ -2192,7 +2203,7 @@ class InstRWInfoTable extends core.Task {
if (op.regIndexRel)
d.flags.Consecutive = true;
for (var k in self.rwOpFlagsForInstruction(asmInst.name, j))
for (let k in self.rwOpFlagsForInstruction(asmInst.name, j))
d.flags[k] = true;
if ((step === -1 || step === j) || op.rwxIndex !== 0 || op.rwxWidth !== opSize) {
@@ -2234,17 +2245,17 @@ class InstRWInfoTable extends core.Task {
}
function queryRwByData(dbInsts, rwOpsArray) {
for (var i = 0; i < dbInsts.length; i++) {
for (let i = 0; i < dbInsts.length; i++) {
const dbInst = dbInsts[i];
const operands = dbInst.operands;
const rwOps = nullOps();
for (var j = 0; j < operands.length; j++) {
for (let j = 0; j < operands.length; j++) {
rwOps[j] = makeRwFromOp(operands[j])
}
var match = 0;
for (var j = 0; j < rwOpsArray.length; j++)
let match = 0;
for (let j = 0; j < rwOpsArray.length; j++)
match |= ObjectUtils.equals(rwOps, rwOpsArray[j]);
if (!match)
@@ -2256,12 +2267,12 @@ class InstRWInfoTable extends core.Task {
function dumpRwToData(dbInsts) {
const out = [];
for (var i = 0; i < dbInsts.length; i++) {
for (let i = 0; i < dbInsts.length; i++) {
const dbInst = dbInsts[i];
const operands = dbInst.operands;
const rwOps = nullOps();
for (var j = 0; j < operands.length; j++)
for (let j = 0; j < operands.length; j++)
rwOps[j] = makeRwFromOp(operands[j])
if (ArrayUtils.deepIndexOf(out, rwOps) !== -1)
@@ -2278,18 +2289,18 @@ class InstRWInfoTable extends core.Task {
return { category: this.rwCategoryByName[name], rwOps: nullOps() };
// Generic rules.
for (var i = -1; i <= 6; i++) {
for (let i = -1; i <= 6; i++) {
const rwInfo = queryRwGeneric(dbInsts, i);
if (rwInfo)
return rwInfo;
}
// Specific rules.
for (var k in this.rwCategoryByData)
for (let k in this.rwCategoryByData)
if (queryRwByData(dbInsts, this.rwCategoryByData[k]))
return { category: k, rwOps: nullOps() };
// FATALURE: Missing data to categorize this instruction.
// FATAL: Missing data to categorize this instruction.
if (name) {
const items = dumpRwToData(dbInsts)
console.log(`RW: ${dbInsts.length ? dbInsts[0].name : ""}:`);
@@ -2345,16 +2356,16 @@ class InstRWInfoTable extends core.Task {
}
rmReplaceableCategory(dbInsts) {
var category = null;
let category = null;
for (var i = 0; i < dbInsts.length; i++) {
for (let i = 0; i < dbInsts.length; i++) {
const dbInst = dbInsts[i];
const operands = dbInst.operands;
var rs = -1;
var ms = -1;
let rs = -1;
let ms = -1;
for (var j = 0; j < operands.length; j++) {
for (let j = 0; j < operands.length; j++) {
const op = operands[j];
if (op.isMem())
ms = op.memSize;
@@ -2362,7 +2373,7 @@ class InstRWInfoTable extends core.Task {
rs = Math.max(rs, op.regSize);
}
var c = (rs === -1 ) ? "None" :
let c = (rs === -1 ) ? "None" :
(ms === -1 ) ? "None" :
(ms === rs ) ? "Fixed" :
(ms === rs / 2) ? "Half" :
@@ -2391,9 +2402,9 @@ class InstRWInfoTable extends core.Task {
rmReplaceableIndexes(dbInsts) {
function maskOf(inst, fn) {
var m = 0;
var operands = inst.operands;
for (var i = 0; i < operands.length; i++)
let m = 0;
let operands = inst.operands;
for (let i = 0; i < operands.length; i++)
if (fn(operands[i]))
m |= (1 << i);
return m;
@@ -2402,19 +2413,19 @@ class InstRWInfoTable extends core.Task {
function getRegIndexes(inst) { return maskOf(inst, function(op) { return op.isReg(); }); };
function getMemIndexes(inst) { return maskOf(inst, function(op) { return op.isMem(); }); };
var mask = 0;
let mask = 0;
for (var i = 0; i < dbInsts.length; i++) {
for (let i = 0; i < dbInsts.length; i++) {
const dbInst = dbInsts[i];
var mi = getMemIndexes(dbInst);
var ri = getRegIndexes(dbInst) & ~mi;
let mi = getMemIndexes(dbInst);
let ri = getRegIndexes(dbInst) & ~mi;
if (!mi)
continue;
const match = dbInsts.some((inst) => {
var ti = getRegIndexes(inst);
let ti = getRegIndexes(inst);
return ((ri & ti) === ri && (mi & ti) === mi);
});
@@ -2427,13 +2438,13 @@ class InstRWInfoTable extends core.Task {
}
rmFixedSize(insts) {
var savedOp = null;
let savedOp = null;
for (var i = 0; i < insts.length; i++) {
for (let i = 0; i < insts.length; i++) {
const inst = insts[i];
const operands = inst.operands;
for (var j = 0; j < operands.length; j++) {
for (let j = 0; j < operands.length; j++) {
const op = operands[j];
if (op.mem) {
if (savedOp && savedOp.mem !== op.mem)
@@ -2447,11 +2458,11 @@ class InstRWInfoTable extends core.Task {
}
rmIsConsistent(insts) {
var hasMem = 0;
for (var i = 0; i < insts.length; i++) {
let hasMem = 0;
for (let i = 0; i < insts.length; i++) {
const inst = insts[i];
const operands = inst.operands;
for (var j = 0; j < operands.length; j++) {
for (let j = 0; j < operands.length; j++) {
const op = operands[j];
if (op.mem) {
hasMem = 1;
@@ -2470,16 +2481,16 @@ class InstRWInfoTable extends core.Task {
const memMap = {};
const immMap = {};
for (var i = 0; i < dbInsts.length; i++) {
for (let i = 0; i < dbInsts.length; i++) {
const dbInst = dbInsts[i];
const operands = dbInst.operands;
var memStr = "";
var immStr = "";
var hasMem = false;
var hasImm = false;
let memStr = "";
let immStr = "";
let hasMem = false;
let hasImm = false;
for (var j = 0; j < operands.length; j++) {
for (let j = 0; j < operands.length; j++) {
const op = operands[j];
if (j) {
memStr += ", ";
@@ -2607,7 +2618,7 @@ class InstCommonTable extends core.Task {
inst.commonInfoIndex = table.addIndexed(row);
});
var s = `#define F(VAL) uint32_t(InstDB::InstFlags::k##VAL)\n` +
let s = `#define F(VAL) uint32_t(InstDB::InstFlags::k##VAL)\n` +
`#define X(VAL) uint32_t(InstDB::Avx512Flags::k##VAL)\n` +
`#define CONTROL_FLOW(VAL) uint8_t(InstControlFlow::k##VAL)\n` +
`#define SAME_REG_HINT(VAL) uint8_t(InstSameRegHint::k##VAL)\n` +

149
tools/tablegen.js
View File

@@ -56,35 +56,50 @@ class InstructionNameData {
this.maxNameLength = 0;
}
add(s) {
// First try to encode the string with 5-bit characters that fit into a 32-bit int.
if (/^[a-z0-4]{0,6}$/.test(s)) {
let index = 0;
for (let i = 0; i < s.length; i++)
index |= charTo5Bit(s[i]) << (i * 5);
add(name, alt) {
if (name === alt) {
alt = "";
}
this.names.push(s);
if (this.maxNameLength < name.length) {
this.maxNameLength = name.length;
}
this.names.push(name);
// First try to encode the string with 5-bit characters that fit into a 32-bit int.
if (/^[a-z0-4]{0,6}$/.test(name) && !alt) {
let index = 0;
for (let i = 0; i < name.length; i++) {
index |= charTo5Bit(name[i]) << (i * 5);
}
this.indexComment.push(`Small '${name}'.`);
this.primaryTable.push(index | (1 << 31));
this.indexComment.push(`Small '${s}'.`);
}
else if (alt) {
const prefixIndex = this.addOrReferenceString(name + String.fromCharCode(alt.length) + alt);
if (name === "jz") {
console.log(`jz prefix: ${prefixIndex}`);
}
this.indexComment.push(`Large '${name}' + '${alt}'`);
this.primaryTable.push(prefixIndex | (name.length << 12) | (0xFFF << 16) | 0);
}
else {
// Put the string into a string table.
this.names.push(s);
this.primaryTable.push(-1);
this.indexComment.push(``);
this.primaryTable.push(0);
}
if (this.maxNameLength < s.length)
this.maxNameLength = s.length;
}
index() {
const kMaxPrefixSize = 15;
const kMaxSuffixSize = 7;
const kMaxSuffixSize = 6;
const names = [];
for (let idx = 0; idx < this.primaryTable.length; idx++) {
if (this.primaryTable[idx] === -1) {
if (this.primaryTable[idx] === 0) {
names.push({ name: this.names[idx], index: idx });
}
}
@@ -205,11 +220,20 @@ class InstructionNameData {
FATAL(`IndexedString.formatStringTable(): Not indexed yet, call index()`);
let s = "";
for (let i = 0; i < this.stringTable.length; i += 80) {
let line = "";
for (let i = 0; i < this.stringTable.length; i++) {
const c = this.stringTable.charCodeAt(i);
line += "\\x" + cxx.Utils.toHexRaw(c, 2);
if (line.length >= 115 || i === this.stringTable.length - 1) {
if (s)
s += "\n"
s += '"' + this.stringTable.substring(i, i + 80) + '"';
s += `"${line}"`;
line = "";
}
}
s += ";\n";
return `const char ${tableName}[] =\n${StringUtils.indent(s, " ")}\n`;
@@ -288,7 +312,9 @@ class Injector {
const path = kAsmJitRoot + "/" + file;
console.log(`MODIFIED '${file}'`);
if (!fs.existsSync(path + ".backup")) {
fs.writeFileSync(path + ".backup", obj.prev, "utf8");
}
fs.writeFileSync(path, obj.data, "utf8");
}
}
@@ -418,7 +444,7 @@ class TableGen extends Injector{
// [Instruction Management]
// --------------------------------------------------------------------------
addInst(inst) {
addInstruction(inst) {
if (this.instMap[inst.name])
FATAL(`TableGen.addInst(): Instruction '${inst.name}' already added`);
@@ -471,19 +497,35 @@ class IdEnum extends Task {
run() {
const insts = this.ctx.insts;
var s = "";
for (var i = 0; i < insts.length; i++) {
let s = "";
let aliases = "";
for (let i = 0; i < insts.length; i++) {
const inst = insts[i];
var line = "kId" + inst.enum + (i ? "" : " = 0") + ",";
var text = this.comment(inst);
let line = "kId" + inst.enum + (i ? "" : " = 0") + ",";
let text = this.comment(inst);
if (text)
line = line.padEnd(37) + "//!< " + text;
s += line + "\n";
if (inst.aliases) {
for (let aliasName of inst.aliases.aliasNames) {
if (aliases) aliases += ",\n";
aliases += `kId${StringUtils.makeEnumName(aliasName)} = kId${inst.enum}`;
}
}
}
s += "_kIdCount";
if (aliases) {
s += ",\n\n" + "// Aliases.\n" + aliases + "\n";
}
else {
s += "\n";
}
s += "_kIdCount\n";
return this.ctx.inject("InstId", s);
}
@@ -507,16 +549,43 @@ class Output {
};
exports.Output = Output;
function generateNameData(out, instructions) {
function cmp(a, b) { return (a < b) ? -1 : a > b ? 1 : 0; }
function generateNameData(out, instructions, generateAliases) {
const none = "Inst::kIdNone";
const aliases = [];
const aliasNameData = new InstructionNameData();
const aliasLinkData = [];
const instFirst = new Array(26);
const instLast = new Array(26);
const instNameData = new InstructionNameData();
for (let i = 0; i < instructions.length; i++)
instNameData.add(instructions[i].displayName);
for (let i = 0; i < instructions.length; i++) {
const instruction = instructions[i];
if (instruction.aliases) {
instNameData.add(instruction.displayName, instruction.aliases.format);
for (let aliasName of instruction.aliases.aliasNames) {
aliases.push({ name: instruction.name, alt: aliasName });
}
}
else {
instNameData.add(instruction.displayName);
}
}
aliases.sort(function(a, b) { return cmp(a.alt, b.alt); });
for (let i = 0; i < aliases.length; i++) {
const alias = aliases[i];
aliasNameData.add(alias.alt);
aliasLinkData.push(`Inst::kId${StringUtils.makeEnumName(alias.name)}`);
}
instNameData.index();
aliasNameData.index();
for (let i = 0; i < instructions.length; i++) {
const inst = instructions[i];
@@ -548,21 +617,41 @@ function generateNameData(out, instructions) {
s += `\n`;
s += instNameData.formatIndexTable("InstDB::_instNameIndexTable");
const dataSize = instNameData.getSize() + 26 * 4;
let dataSize = instNameData.getSize() + 26 * 4;
if (generateAliases) {
s += `\n`;
s += aliasNameData.formatStringTable("InstDB::_aliasNameStringTable");
s += `\n`;
s += aliasNameData.formatIndexTable("InstDB::_aliasNameIndexTable");
s += "\n";
s += "const uint32_t InstDB::_aliasIndexToInstId[] = {\n" + StringUtils.format(aliasLinkData, " ", true, null) + "\n};\n";
dataSize += aliasNameData.getSize();
let info = `static constexpr uint32_t kAliasTableSize = ${aliasLinkData.length};\n`;
out.add("NameDataInfo", StringUtils.disclaimer(info), 0);
}
out.add("NameData", StringUtils.disclaimer(s), dataSize);
return out;
}
exports.generateNameData = generateNameData;
class NameTable extends Task {
constructor(name, deps) {
constructor(name, deps, generateAliases) {
super(name || "NameTable", deps);
this.generateAliases = generateAliases;
}
run() {
const output = new Output();
generateNameData(output, this.ctx.insts);
generateNameData(output, this.ctx.insts, this.generateAliases);
this.ctx.inject("NameData", output.content["NameData"], output.tableSize["NameData"]);
if (this.generateAliases) {
this.ctx.inject("NameDataInfo", output.content["NameDataInfo"], output.tableSize["NameDataInfo"]);
}
}
}
exports.NameTable = NameTable;