diff --git a/.github/workflows/build-config.json b/.github/workflows/build-config.json index ff65ac7..e72d8e3 100644 --- a/.github/workflows/build-config.json +++ b/.github/workflows/build-config.json @@ -17,7 +17,7 @@ { "optional": true, "cmd": ["asmjit_test_assembler", "--validate"] }, { "optional": true, "cmd": ["asmjit_test_emitters"] }, { "optional": true, "cmd": ["asmjit_test_execute"] }, - { "optional": true, "cmd": ["asmjit_test_compiler", "--verbose", "--dump-asm"] }, + { "optional": true, "cmd": ["asmjit_test_compiler"] }, { "optional": true, "cmd": ["asmjit_test_instinfo"] }, { "optional": true, "cmd": ["asmjit_test_x86_sections"] }, { "optional": true, "cmd": ["asmjit_test_perf", "--quick"] } diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 77a927c..04eeebe 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -35,28 +35,28 @@ jobs: fail-fast: false matrix: include: - - { title: "diag-analyze" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Debug" , diagnostics: "analyze-build" } - - { title: "diag-asan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", diagnostics: "asan", defs: "ASMJIT_TEST=1" } - - { title: "diag-msan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", diagnostics: "msan", defs: "ASMJIT_TEST=1" } - - { title: "diag-ubsan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", diagnostics: "ubsan", defs: "ASMJIT_TEST=1" } - - { title: "diag-hardened" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", diagnostics: "hardened", defs: "ASMJIT_TEST=1" } - - { title: "diag-valgrind" , host: "ubuntu-24.04" , arch: "x64" , cc: "clang-18", conf: "Release", diagnostics: "valgrind", defs: "ASMJIT_TEST=1" } + - { title: "diag-analyze" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Debug" , diagnostics: "analyze-build" } + - { title: "diag-asan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", diagnostics: "asan", defs: "ASMJIT_TEST=1" } + - { title: "diag-msan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", diagnostics: "msan", defs: "ASMJIT_TEST=1" } + - { title: "diag-ubsan" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", diagnostics: "ubsan", defs: "ASMJIT_TEST=1" } + - { title: "diag-hardened" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", diagnostics: "hardened", defs: "ASMJIT_TEST=1" } + - { title: "diag-valgrind" , host: "ubuntu-24.04" , arch: "x64" , cc: "clang-19", conf: "Release", diagnostics: "valgrind", defs: "ASMJIT_TEST=1" } - - { title: "no-deprecated" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_DEPRECATED=1" } - - { title: "no-intrinsics" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_INTRINSICS=1" } - - { title: "no-logging" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1" } - - { title: "no-logging-text" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1,ASMJIT_NO_TEXT=1" } - - { title: "no-builder" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_BUILDER=1" } - - { title: "no-compiler" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_COMPILER=1" } - - { title: "no-introspection", host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_COMPILER=1,ASMJIT_NO_INTROSPECTION=1" } - - { title: "no-jit" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_JIT=1" } - - { title: "no-validation" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_VALIDATION=1" } - - { title: "no-x86" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_X86=1" } - - { title: "no-aarch64" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_AARCH64=1" } + - { title: "no-deprecated" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_DEPRECATED=1" } + - { title: "no-intrinsics" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_INTRINSICS=1" } + - { title: "no-logging" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1" } + - { title: "no-logging-text" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_LOGGING=1,ASMJIT_NO_TEXT=1" } + - { title: "no-builder" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_BUILDER=1" } + - { title: "no-compiler" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_COMPILER=1" } + - { title: "no-introspection", host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_COMPILER=1,ASMJIT_NO_INTROSPECTION=1" } + - { title: "no-jit" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_JIT=1" } + - { title: "no-validation" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_VALIDATION=1" } + - { title: "no-x86" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_X86=1" } + - { title: "no-aarch64" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Release", defs: "ASMJIT_TEST=1,ASMJIT_NO_AARCH64=1" } - - { title: "lang-c++17" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++17" } - - { title: "lang-c++20" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++20" } - - { title: "lang-c++23" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-18", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++23" } + - { title: "lang-c++17" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++17" } + - { title: "lang-c++20" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++20" } + - { title: "lang-c++23" , host: "ubuntu-latest" , arch: "x64" , cc: "clang-19", conf: "Debug" , defs: "ASMJIT_TEST=1,CMAKE_CXX_FLAGS=-std=c++23" } - { title: "linux" , host: "ubuntu-22.04" , arch: "x86" , cc: "gcc-9" , conf: "Debug" , defs: "ASMJIT_TEST=1" } - { title: "linux" , host: "ubuntu-22.04" , arch: "x86" , cc: "gcc-9" , conf: "Release", defs: "ASMJIT_TEST=1" } diff --git a/LICENSE.md b/LICENSE.md index d87dbf9..e01395c 100644 --- a/LICENSE.md +++ b/LICENSE.md @@ -1,4 +1,4 @@ -Copyright (c) 2008-2024 The AsmJit Authors +Copyright (c) 2008-2025 The AsmJit Authors This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages diff --git a/db/LICENSE.md b/db/LICENSE.md index 9fc2f1a..e01395c 100644 --- a/db/LICENSE.md +++ b/db/LICENSE.md @@ -1,26 +1,17 @@ -AsmJit database is dual licensed under Zlib and Unlicense (public domain) +Copyright (c) 2008-2025 The AsmJit Authors -This is free and unencumbered software released into the public domain. +This software is provided 'as-is', without any express or implied +warranty. In no event will the authors be held liable for any damages +arising from the use of this software. -Anyone is free to copy, modify, publish, use, compile, sell, or -distribute this software, either in source code form or as a compiled -binary, for any purpose, commercial or non-commercial, and by any -means. +Permission is granted to anyone to use this software for any purpose, +including commercial applications, and to alter it and redistribute it +freely, subject to the following restrictions: -In jurisdictions that recognize copyright laws, the author or authors -of this software dedicate any and all copyright interest in the -software to the public domain. We make this dedication for the benefit -of the public at large and to the detriment of our heirs and -successors. We intend this dedication to be an overt act of -relinquishment in perpetuity of all present and future rights to this -software under copyright law. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR -OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -OTHER DEALINGS IN THE SOFTWARE. - -For more information, please refer to \ No newline at end of file +1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software + in a product, an acknowledgment in the product documentation would be + appreciated but is not required. +2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. +3. This notice may not be removed or altered from any source distribution. diff --git a/db/README.md b/db/README.md index 12eaf9b..faddd94 100644 --- a/db/README.md +++ b/db/README.md @@ -18,4 +18,4 @@ This project will be refactored and documented in the future. License ------- -AsmJit database is dual licensed under Zlib (AsmJit license) or public domain. The database can be used for any purpose, not just by AsmJit. \ No newline at end of file +AsmJit database is licensed under [Zlib License](./LICENSE.md) diff --git a/db/aarch32.js b/db/aarch32.js index dac8ac9..7d80d41 100644 --- a/db/aarch32.js +++ b/db/aarch32.js @@ -1,7 +1,7 @@ // This file is part of AsmJit project // // See asmjit.h or LICENSE.md for license and copyright information -// SPDX-License-Identifier: (Zlib or Unlicense) +// SPDX-License-Identifier: Zlib (function($scope, $as) { "use strict"; @@ -14,11 +14,11 @@ function FAIL(msg) { throw new Error("[AArch32] " + msg); } const base = $scope.base ? $scope.base : require("./base.js"); const exp = $scope.exp ? $scope.exp : require("./exp.js") -const hasOwn = Object.prototype.hasOwnProperty; const dict = base.dict; const NONE = base.NONE; const Parsing = base.Parsing; const MapUtils = base.MapUtils; +const hasOwn = base.hasOwn; // Export // ====== @@ -256,7 +256,8 @@ function splitOpcodeFields(s) { // ARM operand. class Operand extends base.Operand { constructor(def) { - super(def); + super(); + this.data = def; } hasMemModes() { @@ -323,9 +324,9 @@ class Instruction extends base.Instruction { super(db, data); // name, operands, encoding, opcode, metadata - const encoding = hasOwn.call(data, "a32") ? "a32" : - hasOwn.call(data, "t32") ? "t32" : - hasOwn.call(data, "t16") ? "t16" : ""; + const encoding = hasOwn(data, "a32") ? "a32" : + hasOwn(data, "t32") ? "t32" : + hasOwn(data, "t16") ? "t16" : ""; this.name = data.name; this.it = dict(); // THUMB's 'it' flags. @@ -962,9 +963,9 @@ class ISA extends base.ISA { const names = (sep !== -1 ? sgn.substring(0, sep) : sgn).trim().split("/"); const operands = sep !== -1 ? sgn.substring(sep + 1) : ""; - const encoding = hasOwn.call(obj, "a32") ? "a32" : - hasOwn.call(obj, "t32") ? "t32" : - hasOwn.call(obj, "t16") ? "t16" : ""; + const encoding = hasOwn(obj, "a32") ? "a32" : + hasOwn(obj, "t32") ? "t32" : + hasOwn(obj, "t16") ? "t16" : ""; if (!encoding) FAIL(`Instruction ${names.join("/")} doesn't encoding, it must provide either a32, t32, or t16 field`); diff --git a/db/aarch64.js b/db/aarch64.js index 70932f7..070d9fa 100644 --- a/db/aarch64.js +++ b/db/aarch64.js @@ -1,7 +1,7 @@ // This file is part of AsmJit project // // See asmjit.h or LICENSE.md for license and copyright information -// SPDX-License-Identifier: (Zlib or Unlicense) +// SPDX-License-Identifier: Zlib (function($scope, $as) { "use strict"; @@ -296,7 +296,8 @@ function splitOpcodeFields(s) { // ARM operand. class Operand extends base.Operand { constructor(def) { - super(def); + super(); + this.data = def; // Register. this.sp = ""; // GP register stack access: ["", "WSP" or "SP"]. @@ -895,9 +896,9 @@ class ISA extends base.ISA { _addInstructions(groups) { for (let group of groups) { - for (let inst of group.data) { - const sgn = Utils.splitInstructionSignature(inst.inst); - const data = MapUtils.cloneExcept(inst, { "inst": true }); + for (let instructions of group.data) { + const sgn = Utils.splitInstructionSignature(instructions.inst); + const data = MapUtils.cloneExcept(instructions, { "inst": true }); mergeGroupData(data, group) diff --git a/db/base.js b/db/base.js index 11ef2b1..bedb13f 100644 --- a/db/base.js +++ b/db/base.js @@ -1,24 +1,28 @@ // This file is part of AsmJit project // // See asmjit.h or LICENSE.md for license and copyright information -// SPDX-License-Identifier: (Zlib or Unlicense) +// SPDX-License-Identifier: Zlib (function($scope, $as) { "use strict"; function FAIL(msg) { throw new Error("[BASE] " + msg); } -// Import. -const hasOwn = Object.prototype.hasOwnProperty; - const exp = $scope.exp ? $scope.exp : require("./exp.js"); - // Export. const base = $scope[$as] = Object.create(null); base.exp = exp; +// Import. +const hasOwnProperty = Object.prototype.hasOwnProperty; + +function hasOwn(object, key) { + return hasOwnProperty.call(object, key); +} +base.hasOwn = hasOwn; + function dict(src) { const dst = Object.create(null); if (src) @@ -131,8 +135,14 @@ base.Parsing = Parsing; // asmdb.base.MapUtils // =================== -const MapUtils = { - cloneExcept(map, except) { +class MapUtils { + static cloneExcept(map, except) { + if (typeof except === "string") { + const key = except; + except = Object.create(null); + except[key] = true; + } + const out = Object.create(null); for (let k in map) { if (k in except) @@ -141,6 +151,14 @@ const MapUtils = { } return out; } + + static mapFromArray(array) { + const out = Object.create(null); + for (let k of array) { + out[k] = true; + } + return out; + } }; base.MapUtils = MapUtils; @@ -158,9 +176,9 @@ const OperandFlags = Object.freeze({ base.OperandFlags = OperandFlags; class Operand { - constructor(data) { + constructor() { this.type = ""; // Type of the operand ("reg", "reg-list", "mem", "reg/mem", "imm", "rel"). - this.data = data; // The operand's data (possibly processed). + this.data = ""; // The operand's data (possibly processed). this.flags = 0; this.reg = ""; // Register operand's definition. @@ -246,7 +264,7 @@ class Instruction { this.specialRegs = dict(); // Information about read/write to special registers. - this.altForm = false; // This is an alternative form, not needed to create a signature. + this.alt = false; // This is an alternative form, not needed to create a signature. this.volatile = false; // Instruction is volatile and should not be reordered. this.control = "none"; // Control flow type (none by default). this.privilege = ""; // Privilege-level required to execute the instruction. @@ -373,8 +391,8 @@ class InstructionGroup extends Array { unionCpuFeatures(name) { const result = dict(); for (let i = 0; i < this.length; i++) { - const inst = this[i]; - const features = inst.ext; + const instruction = this[i]; + const features = instruction.ext; for (let k in features) result[k] = features[k]; } @@ -401,13 +419,14 @@ class ISA { this._instructionNames = null; // Instruction names (sorted), regenerated when needed. this._instructionMap = dict(); // Instruction name to `Instruction[]` mapping. this._aliases = dict(); // Instruction aliases. + this._aliasMap = dict(); // Instruction aliases. this._cpuLevels = dict(); // Architecture versions. this._extensions = dict(); // Architecture extensions. this._attributes = dict(); // Instruction attributes. this._specialRegs = dict(); // Special registers. this._shortcuts = dict(); // Shortcuts used by instructions metadata. this.stats = { - insts : 0, // Number of all instructions. + instructions : 0, // Number of all instructions. groups: 0 // Number of grouped instructions (having unique name). }; } @@ -436,7 +455,7 @@ class ISA { } get instructionMap() { return this._instructionMap; } - get aliases() { return this._aliases; } + get aliases() { return this._aliasMap; } get cpuLevels() { return this._cpuLevels; } get extensions() { return this._extensions; } get attributes() { return this._attributes; } @@ -458,27 +477,31 @@ class ISA { return result; } + aliasData(name) { + return this._aliases[name] || null; + } + _queryByName(name, copy) { let result = EmptyInstructionGroup; const map = this._instructionMap; if (typeof name === "string") { - const insts = map[name]; - if (insts) result = insts; + const instructions = map[name]; + if (instructions) result = instructions; return copy ? result.slice() : result; } if (Array.isArray(name)) { const names = name; for (let i = 0; i < names.length; i++) { - const insts = map[names[i]]; - if (!insts) continue; + const instructions = map[names[i]]; + if (!instructions) continue; if (result === EmptyInstructionGroup) result = new InstructionGroup(); - for (let j = 0; j < insts.length; j++) - result.push(insts[j]); + for (let j = 0; j < instructions.length; j++) + result.push(instructions[j]); } return result; } @@ -507,23 +530,24 @@ class ISA { if (data.specialRegs) this._addSpecialRegs(data.specialRegs); if (data.shortcuts) this._addShortcuts(data.shortcuts); if (data.instructions) this._addInstructions(data.instructions); + if (data.aliases) this._addAliases(data.aliases); if (data.postproc) this._postProc(data.postproc); } _postProc(groups) { for (let group of groups) { for (let iRule of group.instructions) { - const names = iRule.inst.split(" "); + const names = iRule.name.split(" "); for (let name of names) { - const insts = this._instructionMap[name]; - if (!insts) + const instructions = this._instructionMap[name]; + if (!instructions) FAIL(`Instruction ${name} referenced by '${group.group}' group doesn't exist`); for (let k in iRule) { - if (k === "inst" || k === "data") + if (k === "name" || k === "data") continue; - for (let inst of insts) { - inst._assignAttribute(k, iRule[k]); + for (let instruction of instructions) { + instruction._assignAttribute(k, iRule[k]); } } } @@ -630,28 +654,60 @@ class ISA { FAIL("ISA._addInstructions() must be reimplemented"); } - _addInstruction(inst) { + _addInstruction(instruction) { let group; - if (hasOwn.call(this._instructionMap, inst.name)) { - group = this._instructionMap[inst.name]; + if (hasOwn(this._instructionMap, instruction.name)) { + group = this._instructionMap[instruction.name]; } else { group = new InstructionGroup(); this._instructionNames = null; - this._instructionMap[inst.name] = group; + this._instructionMap[instruction.name] = group; this.stats.groups++; } - if (inst.aliasOf) - this._aliases[inst.name] = inst.aliasOf; + if (instruction.aliasOf) { + this._addAlias(instruction.name, instruction.aliasOf); + } - group.push(inst); - this.stats.insts++; + group.push(instruction); + this.stats.instructions++; this._instructions = null; return this; } + + // Add aliases from instruction database - aliases must be an object where each key is a non-aliased instruction. + _addAliases(aliases) { + for (let instructionName in aliases) { + const data = aliases[instructionName]; + for (let aliasName of data.aliases) { + this._addAlias(instructionName, aliasName, data.format || ""); + } + } + } + + _addAlias(instructionName, aliasName, aliasFormat) { + const group = this._instructionMap[instructionName]; + if (!group) { + FAIL(`Instruction ${instructionName} doesn't exist when processing alias (${aliasName})`); + } + + let alias = this._aliases[instructionName]; + if (!alias) { + alias = dict({ + primaryName: instructionName, + aliasNames: [], + format: "" + }); + this._aliases[instructionName] = alias; + } + + this._aliasMap[aliasName] = instructionName; + alias.aliasNames.push(aliasName); + alias.format = aliasFormat || ""; + } } base.ISA = ISA; diff --git a/db/exp.js b/db/exp.js index ac5b325..956912a 100644 --- a/db/exp.js +++ b/db/exp.js @@ -1,7 +1,7 @@ // This file is part of AsmJit project // // See asmjit.h or LICENSE.md for license and copyright information -// SPDX-License-Identifier: (Zlib or Unlicense) +// SPDX-License-Identifier: Zlib (function($scope, $as) { "use strict"; diff --git a/db/index.js b/db/index.js index 9c32d30..61d8eb8 100644 --- a/db/index.js +++ b/db/index.js @@ -1,7 +1,7 @@ // This file is part of AsmJit project // // See asmjit.h or LICENSE.md for license and copyright information -// SPDX-License-Identifier: (Zlib or Unlicense) +// SPDX-License-Identifier: Zlib "use strict"; diff --git a/db/isa_x86.json b/db/isa_x86.json index b264298..027ac3f 100644 --- a/db/isa_x86.json +++ b/db/isa_x86.json @@ -1,4767 +1,4319 @@ { "instructions": [ - {"category": "GP", "data": [ - {"inst": "adc x:al, ib/ub" , "op": "14 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X", "altForm": true}, - {"inst": "adc x:ax, iw/uw" , "op": "66 15 iw" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X", "altForm": true}, - {"inst": "adc X:eax, id/ud" , "op": "15 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X", "altForm": true}, - {"inst": "adc X:rax, id" , "op": "REX.W 15 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X", "altForm": true}, - {"inst": "[lock|xacqrel] adc x:r8/m8, ib/ub" , "op": "M: 80 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] adc x:r16/m16, iw/uw" , "op": "M: 66 81 /2 iw" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] adc X:r32/m32, id/ud" , "op": "M: 81 /2 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] adc X:r64/m64, id" , "op": "M: REX.W 81 /2 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] adc x:r16/m16, ib" , "op": "M: 66 83 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] adc X:r32/m32, ib" , "op": "M: 83 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] adc X:r64/m64, ib" , "op": "M: REX.W 83 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] adc x:~r8/m8, ~r8" , "op": "MR: 10 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] adc x:~r16/m16, ~r16" , "op": "MR: 66 11 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] adc X:~r32/m32, ~r32" , "op": "MR: 11 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] adc X:~r64/m64, ~r64" , "op": "MR: REX.W 11 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "adc x:~r8, ~r8/m8" , "op": "RM: 12 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "adc x:~r16, ~r16/m16" , "op": "RM: 66 13 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "adc X:~r32, ~r32/m32" , "op": "RM: 13 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "adc X:~r64, ~r64/m64" , "op": "RM: REX.W 13 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "add x:al, ib/ub" , "op": "04 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "add x:ax, iw/uw" , "op": "66 05 iw" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "add X:eax, id/ud" , "op": "05 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "add X:rax, id" , "op": "REX.W 05 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "[lock|xacqrel] add x:r8/m8, ib/ub" , "op": "M: 80 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] add x:r16/m16, iw/uw" , "op": "M: 66 81 /0 iw" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] add X:r32/m32, id/ud" , "op": "M: 81 /0 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] add X:r64/m64, id" , "op": "M: REX.W 81 /0 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] add x:r16/m16, ib" , "op": "M: 66 83 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] add X:r32/m32, ib" , "op": "M: 83 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] add X:r64/m64, ib" , "op": "M: REX.W 83 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] add x:~r8/m8, ~r8" , "op": "MR: 00 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] add x:~r16/m16, ~r16" , "op": "MR: 66 01 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] add X:~r32/m32, ~r32" , "op": "MR: 01 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] add X:~r64/m64, ~r64" , "op": "MR: REX.W 01 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "add x:~r8, ~r8/m8" , "op": "RM: 02 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "add x:~r16, ~r16/m16" , "op": "RM: 66 03 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "add X:~r32, ~r32/m32" , "op": "RM: 03 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "add X:~r64, ~r64/m64" , "op": "RM: REX.W 03 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "and x:al, ib/ub" , "op": "24 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "and x:ax, iw/uw" , "op": "66 25 iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "and X:eax, id/ud" , "op": "25 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "and X:rax, ud" , "op": "25 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "and X:rax, id" , "op": "REX.W 25 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "[lock|xacqrel] and x:r8/m8, ib/ub" , "op": "M: 80 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] and x:r16/m16, iw/uw" , "op": "M: 66 81 /4 iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] and X:r32/m32, id/ud" , "op": "M: 81 /4 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] and X:r64, ud" , "op": "M: 81 /4 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] and X:r64/m64, id" , "op": "M: REX.W 81 /4 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] and x:r16/m16, ib/ub" , "op": "M: 66 83 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] and X:r32/m32, ib/ub" , "op": "M: 83 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] and X:r64/m64, ib/ub" , "op": "M: REX.W 83 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] and x:~r8/m8, ~r8" , "op": "MR: 20 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] and x:~r16/m16, ~r16" , "op": "MR: 66 21 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] and X:~r32/m32, ~r32" , "op": "MR: 21 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] and X:~r64/m64, ~r64" , "op": "MR: REX.W 21 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "and x:~r8, ~r8/m8" , "op": "RM: 22 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "and x:~r16, ~r16/m16" , "op": "RM: 66 23 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "and X:~r32, ~r32/m32" , "op": "RM: 23 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "and X:~r64, ~r64/m64" , "op": "RM: REX.W 23 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "bsf w:r16, r16/m16" , "op": "RM: 66 0F BC /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=U"}, - {"inst": "bsf W:r32, r32/m32" , "op": "RM: 0F BC /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=U"}, - {"inst": "bsf W:r64, r64/m64" , "op": "RM: REX.W 0F BC /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=U"}, - {"inst": "bsr w:r16, r16/m16" , "op": "RM: 66 0F BD /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=U"}, - {"inst": "bsr W:r32, r32/m32" , "op": "RM: 0F BD /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=U"}, - {"inst": "bsr W:r64, r64/m64" , "op": "RM: REX.W 0F BD /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=U"}, - {"inst": "bswap X:r16" , "op": "66 0F C8+r"}, - {"inst": "bswap X:r32" , "op": "0F C8+r"}, - {"inst": "bswap X:r64" , "op": "REX.W 0F C8+r"}, - {"inst": "bt R:r16/m16, ib/ub" , "op": "M: 66 0F BA /4 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "bt R:r32/m32, ib/ub" , "op": "M: 0F BA /4 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "bt R:r64/m64, ib/ub" , "op": "M: REX.W 0F BA /4 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "bt R:r16/m16, r16" , "op": "MR: 66 0F A3 /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "bt R:r32/m32, r32" , "op": "MR: 0F A3 /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "bt R:r64/m64, r64" , "op": "MR: REX.W 0F A3 /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btc x:r16/m16, ib/ub" , "op": "M: 66 0F BA /7 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btc X:r32/m32, ib/ub" , "op": "M: 0F BA /7 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btc X:r64/m64, ib/ub" , "op": "M: REX.W 0F BA /7 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btc x:r16/m16, r16" , "op": "MR: 66 0F BB /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btc X:r32/m32, r32" , "op": "MR: 0F BB /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btc X:r64/m64, r64" , "op": "MR: REX.W 0F BB /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btr x:r16/m16, ib/ub" , "op": "M: 66 0F BA /6 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btr X:r32/m32, ib/ub" , "op": "M: 0F BA /6 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btr X:r64/m64, ib/ub" , "op": "M: REX.W 0F BA /6 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btr x:r16/m16, r16" , "op": "MR: 66 0F B3 /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btr X:r32/m32, r32" , "op": "MR: 0F B3 /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] btr X:r64/m64, r64" , "op": "MR: REX.W 0F B3 /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] bts x:r16/m16, ib/ub" , "op": "M: 66 0F BA /5 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] bts X:r32/m32, ib/ub" , "op": "M: 0F BA /5 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] bts X:r64/m64, ib/ub" , "op": "M: REX.W 0F BA /5 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] bts x:r16/m16, r16" , "op": "MR: 66 0F AB /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] bts X:r32/m32, r32" , "op": "MR: 0F AB /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] bts X:r64/m64, r64" , "op": "MR: REX.W 0F AB /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, - {"inst": "[bnd|repIgnore] call rel16" , "op": "66 E8 cw" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "arch": "X86"}, - {"inst": "[bnd|repIgnore] call rel32" , "op": "E8 cd" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "[bnd|repIgnore] call R:r16/m16" , "op": "66 FF /2" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "arch": "X86"}, - {"inst": "[bnd|repIgnore] call R:r32/m32" , "op": "FF /2" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "arch": "X86"}, - {"inst": "[bnd|repIgnore] call R:r64/m64" , "op": "FF /2" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "arch": "X64"}, - {"inst": "cbw x:" , "op": "66 98"}, - {"inst": "cdq W:, " , "op": "99"}, - {"inst": "cdqe X:" , "op": "REX.W 98"}, - {"inst": "clc" , "op": "F8" , "io": "CF=0"}, - {"inst": "cld" , "op": "FC" , "io": "DF=0"}, - {"inst": "cmc" , "op": "F5" , "io": "CF=X"}, - {"inst": "cmp R:al, ib/ub" , "op": "3C ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "cmp R:ax, iw/uw" , "op": "66 3D iw" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "cmp R:eax, id/ud" , "op": "3D id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "cmp R:rax, id" , "op": "REX.W 3D id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "cmp R:r8/m8, ib/ub" , "op": "M: 80 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r16/m16, iw/uw" , "op": "M: 66 81 /7 iw" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r32/m32, id/ud" , "op": "M: 81 /7 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r64/m64, id" , "op": "M: REX.W 81 /7 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r16/m16, ib" , "op": "M: 66 83 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r32/m32, ib" , "op": "M: 83 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r64/m64, ib" , "op": "M: REX.W 83 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r8/m8, r8" , "op": "MR: 38 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r16/m16, r16" , "op": "MR: 66 39 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r32/m32, r32" , "op": "MR: 39 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r64/m64, r64" , "op": "MR: REX.W 39 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r8, r8/m8" , "op": "RM: 3A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r16, r16/m16" , "op": "RM: 66 3B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r32, r32/m32" , "op": "RM: 3B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cmp R:r64, r64/m64" , "op": "RM: REX.W 3B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[rep|repne] cmps R:m8(ds:zsi), R:m8(es:zdi)" , "op": "A6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, - {"inst": "[rep|repne] cmps R:m16(ds:zsi), R:m16(es:zdi)" , "op": "66 A7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, - {"inst": "[rep|repne] cmps R:m32(ds:zsi), R:m32(es:zdi)" , "op": "A7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, - {"inst": "[rep|repne] cmps R:m64(ds:zsi), R:m64(es:zdi)" , "op": "REX.W A7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, - {"inst": "cwde X:" , "op": "98"}, - {"inst": "cqo W:, " , "op": "REX.W 99"}, - {"inst": "cwd w:, " , "op": "66 99"}, - {"inst": "dec x:r16" , "op": "66 48+r" , "io": "OF=W SF=W ZF=W AF=W PF=W", "arch": "X86"}, - {"inst": "dec X:r32" , "op": "48+r" , "io": "OF=W SF=W ZF=W AF=W PF=W", "arch": "X86"}, - {"inst": "[lock|xacqrel] dec x:r8/m8" , "op": "FE /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "[lock|xacqrel] dec x:r16/m16" , "op": "66 FF /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "[lock|xacqrel] dec X:r32/m32" , "op": "FF /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "[lock|xacqrel] dec X:r64/m64" , "op": "REX.W FF /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "div x:, r8/m8" , "op": "F6 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "div x:, x:, r16/m16" , "op": "66 F7 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "div X:, X:, r32/m32" , "op": "F7 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "div X:, X:, r64/m64" , "op": "REX.W F7 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "enter iw/uw, ib/ub" , "op": "C8 iw ib" , "volatile": true}, - {"inst": "idiv x:, r8/m8" , "op": "F6 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "idiv x:, x:, r16/m16" , "op": "66 F7 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "idiv X:, X:, r32/m32" , "op": "F7 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "idiv X:, X:, r64/m64" , "op": "REX.W F7 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "imul x:, r8/m8" , "op": "F6 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul w:, x:, r16/m16" , "op": "66 F7 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul W:, X:, r32/m32" , "op": "F7 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul W:, X:, r64/m64" , "op": "REX.W F7 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul x:~r16, ~r16/m16" , "op": "RM: 66 0F AF /r" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul X:~r32, ~r32/m32" , "op": "RM: 0F AF /r" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul X:~r64, ~r64/m64" , "op": "RM: REX.W 0F AF /r" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul w:r16, r16/m16, ib" , "op": "RM: 66 6B /r ib" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul W:r32, r32/m32, ib" , "op": "RM: 6B /r ib" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul W:r64, r64/m64, ib" , "op": "RM: REX.W 6B /r ib" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul w:r16, r16/m16, iw/uw" , "op": "RM: 66 69 /r iw" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul W:r32, r32/m32, id/ud" , "op": "RM: 69 /r id" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "imul W:r64, r64/m64, id" , "op": "RM: REX.W 69 /r id" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, - {"inst": "inc x:r16" , "op": "66 40+r" , "io": "OF=W SF=W ZF=W AF=W PF=W", "arch": "X86"}, - {"inst": "inc X:r32" , "op": "40+r" , "io": "OF=W SF=W ZF=W AF=W PF=W", "arch": "X86"}, - {"inst": "[lock] inc x:r8/m8" , "op": "FE /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "[lock] inc x:r16/m16" , "op": "66 FF /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "[lock] inc X:r32/m32" , "op": "FF /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "[lock] inc X:r64/m64" , "op": "REX.W FF /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "iret" , "op": "66 CF" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "iretd" , "op": "CF" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "iretq" , "op": "REX.W CF" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "[bnd] jo rel8" , "op": "70 cb" , "io": "OF=R"}, - {"inst": "[bnd] jo rel16" , "op": "66 0F 80 cw" , "io": "OF=R"}, - {"inst": "[bnd] jo rel32" , "op": "0F 80 cd" , "io": "OF=R"}, - {"inst": "[bnd] jno rel8" , "op": "71 cb" , "io": "OF=R"}, - {"inst": "[bnd] jno rel16" , "op": "66 0F 81 cw" , "io": "OF=R"}, - {"inst": "[bnd] jno rel32" , "op": "0F 81 cd" , "io": "OF=R"}, - {"inst": "[bnd] jb|jnae|jc rel8" , "op": "72 cb" , "io": "CF=R"}, - {"inst": "[bnd] jb|jnae|jc rel16" , "op": "66 0F 82 cw" , "io": "CF=R"}, - {"inst": "[bnd] jb|jnae|jc rel32" , "op": "0F 82 cd" , "io": "CF=R"}, - {"inst": "[bnd] jae|jnb|jnc rel8" , "op": "73 cb" , "io": "CF=R"}, - {"inst": "[bnd] jae|jnb|jnc rel16" , "op": "66 0F 83 cw" , "io": "CF=R"}, - {"inst": "[bnd] jae|jnb|jnc rel32" , "op": "0F 83 cd" , "io": "CF=R"}, - {"inst": "[bnd] je|jz rel8" , "op": "74 cb" , "io": "ZF=R"}, - {"inst": "[bnd] je|jz rel16" , "op": "66 0F 84 cw" , "io": "ZF=R"}, - {"inst": "[bnd] je|jz rel32" , "op": "0F 84 cd" , "io": "ZF=R"}, - {"inst": "[bnd] jne|jnz rel8" , "op": "75 cb" , "io": "ZF=R"}, - {"inst": "[bnd] jne|jnz rel16" , "op": "66 0F 85 cw" , "io": "ZF=R"}, - {"inst": "[bnd] jne|jnz rel32" , "op": "0F 85 cd" , "io": "ZF=R"}, - {"inst": "[bnd] jbe|jna rel8" , "op": "76 cb" , "io": "CF=R ZF=R"}, - {"inst": "[bnd] jbe|jna rel16" , "op": "66 0F 86 cw" , "io": "CF=R ZF=R"}, - {"inst": "[bnd] jbe|jna rel32" , "op": "0F 86 cd" , "io": "CF=R ZF=R"}, - {"inst": "[bnd] ja|jnbe rel8" , "op": "77 cb" , "io": "CF=R ZF=R"}, - {"inst": "[bnd] ja|jnbe rel16" , "op": "66 0F 87 cw" , "io": "CF=R ZF=R"}, - {"inst": "[bnd] ja|jnbe rel32" , "op": "0F 87 cd" , "io": "CF=R ZF=R"}, - {"inst": "[bnd] js rel8" , "op": "78 cb" , "io": "SF=R"}, - {"inst": "[bnd] js rel16" , "op": "66 0F 88 cw" , "io": "SF=R"}, - {"inst": "[bnd] js rel32" , "op": "0F 88 cd" , "io": "SF=R"}, - {"inst": "[bnd] jns rel8" , "op": "79 cb" , "io": "SF=R"}, - {"inst": "[bnd] jns rel16" , "op": "66 0F 89 cw" , "io": "SF=R"}, - {"inst": "[bnd] jns rel32" , "op": "0F 89 cd" , "io": "SF=R"}, - {"inst": "[bnd] jp|jpe rel8" , "op": "7A cb" , "io": "PF=R"}, - {"inst": "[bnd] jp|jpe rel16" , "op": "66 0F 8A cw" , "io": "PF=R"}, - {"inst": "[bnd] jp|jpe rel32" , "op": "0F 8A cd" , "io": "PF=R"}, - {"inst": "[bnd] jnp|jpo rel8" , "op": "7B cb" , "io": "PF=R"}, - {"inst": "[bnd] jnp|jpo rel16" , "op": "66 0F 8B cw" , "io": "PF=R"}, - {"inst": "[bnd] jnp|jpo rel32" , "op": "0F 8B cd" , "io": "PF=R"}, - {"inst": "[bnd] jl|jnge rel8" , "op": "7C cb" , "io": "SF=R OF=R"}, - {"inst": "[bnd] jl|jnge rel16" , "op": "66 0F 8C cw" , "io": "SF=R OF=R"}, - {"inst": "[bnd] jl|jnge rel32" , "op": "0F 8C cd" , "io": "SF=R OF=R"}, - {"inst": "[bnd] jge|jnl rel8" , "op": "7D cb" , "io": "SF=R OF=R"}, - {"inst": "[bnd] jge|jnl rel16" , "op": "66 0F 8D cw" , "io": "SF=R OF=R"}, - {"inst": "[bnd] jge|jnl rel32" , "op": "0F 8D cd" , "io": "SF=R OF=R"}, - {"inst": "[bnd] jle|jng rel8" , "op": "7E cb" , "io": "ZF=R SF=R OF=R"}, - {"inst": "[bnd] jle|jng rel16" , "op": "66 0F 8E cw" , "io": "ZF=R SF=R OF=R"}, - {"inst": "[bnd] jle|jng rel32" , "op": "0F 8E cd" , "io": "ZF=R SF=R OF=R"}, - {"inst": "[bnd] jg|jnle rel8" , "op": "7F cb" , "io": "ZF=R SF=R OF=R"}, - {"inst": "[bnd] jg|jnle rel16" , "op": "66 0F 8F cw" , "io": "ZF=R SF=R OF=R"}, - {"inst": "[bnd] jg|jnle rel32" , "op": "0F 8F cd" , "io": "ZF=R SF=R OF=R"}, - {"inst": "[bnd] jecxz R:, rel8" , "op": "67 E3 cb" , "arch": "X86"}, - {"inst": "[bnd] jecxz R:, rel8" , "op": "E3 cb" , "arch": "X86"}, - {"inst": "[bnd] jecxz R:, rel8" , "op": "67 E3 cb" , "arch": "X64"}, - {"inst": "[bnd] jecxz R:, rel8" , "op": "E3 cb" , "arch": "X64"}, - {"inst": "[bnd] jmp rel8" , "op": "EB cb"}, - {"inst": "[bnd] jmp rel16" , "op": "66 E9 cw" , "arch": "X86"}, - {"inst": "[bnd] jmp rel32" , "op": "E9 cd"}, - {"inst": "[bnd] jmp R:r32/m32" , "op": "FF /4" , "arch": "X86"}, - {"inst": "[bnd] jmp R:r64/m64" , "op": "FF /4" , "arch": "X64"}, - {"inst": "lcall iw, iw" , "op": "66 9A iw iw" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "arch": "X86"}, - {"inst": "lcall iw, id" , "op": "9A id iw" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "arch": "X86"}, - {"inst": "lcall R:m16_16" , "op": "66 FF /3" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "lcall R:m16_32" , "op": "FF /3" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, - {"inst": "lcall R:m16_64" , "op": "REX.W FF /3" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "arch": "X64"}, - {"inst": "lea w:r16, mem" , "op": "RM: 67 8D /r"}, - {"inst": "lea W:r32, mem" , "op": "RM: 8D /r"}, - {"inst": "lea W:r64, mem" , "op": "RM: REX.W 8D /r"}, - {"inst": "leave" , "op": "C9" , "volatile": true}, - {"inst": "ljmp iw, iw" , "op": "66 EA iw iw" , "arch": "X86"}, - {"inst": "ljmp iw, id" , "op": "EA id iw" , "arch": "X86"}, - {"inst": "ljmp R:m16_16" , "op": "66 FF /5"}, - {"inst": "ljmp R:m16_32" , "op": "FF /5"}, - {"inst": "ljmp R:m16_64" , "op": "REX.W FF /5"}, - {"inst": "[rep] lods w:al, R:m8(ds:zsi)" , "op": "AC" , "io": "DF=R"}, - {"inst": "[rep] lods w:ax, R:m16(ds:zsi)" , "op": "66 AD" , "io": "DF=R"}, - {"inst": "[rep] lods W:eax, R:m32(ds:zsi)" , "op": "AD" , "io": "DF=R"}, - {"inst": "[rep] lods W:rax, R:m64(ds:zsi)" , "op": "REX.W AD" , "io": "DF=R"}, - {"inst": "loop x:, rel8" , "op": "67 E2 cb" , "arch": "X86"}, - {"inst": "loop X:, rel8" , "op": "E2 cb" , "arch": "X86"}, - {"inst": "loop X:, rel8" , "op": "67 E2 cb" , "arch": "X64"}, - {"inst": "loop X:, rel8" , "op": "E2 cb" , "arch": "X64"}, - {"inst": "loope x:, rel8" , "op": "67 E1 cb" , "io": "ZF=R", "arch": "X86"}, - {"inst": "loope X:, rel8" , "op": "E1 cb" , "io": "ZF=R", "arch": "X86"}, - {"inst": "loope X:, rel8" , "op": "67 E1 cb" , "io": "ZF=R", "arch": "X64"}, - {"inst": "loope X:, rel8" , "op": "E1 cb" , "io": "ZF=R", "arch": "X64"}, - {"inst": "loopne x:, rel8" , "op": "67 E0 cb" , "io": "ZF=R", "arch": "X86"}, - {"inst": "loopne X:, rel8" , "op": "E0 cb" , "io": "ZF=R", "arch": "X86"}, - {"inst": "loopne X:, rel8" , "op": "67 E0 cb" , "io": "ZF=R", "arch": "X64"}, - {"inst": "loopne X:, rel8" , "op": "E0 cb" , "io": "ZF=R", "arch": "X64"}, - {"inst": "[xrelease] mov w:r8/m8, r8" , "op": "MR: 88 /r"}, - {"inst": "[xrelease] mov w:r16/m16, r16" , "op": "MR: 66 89 /r"}, - {"inst": "[xrelease] mov W:r32/m32, r32" , "op": "MR: 89 /r"}, - {"inst": "[xrelease] mov W:r64/m64, r64" , "op": "MR: REX.W 89 /r"}, - {"inst": "[xrelease] mov w:r8/m8, ib/ub" , "op": "M: C6 /0 ib"}, - {"inst": "[xrelease] mov w:r16/m16, iw/uw" , "op": "M: 66 C7 /0 iw"}, - {"inst": "[xrelease] mov W:r32/m32, id/ud" , "op": "M: C7 /0 id"}, - {"inst": "[xrelease] mov W:r64/m64, id" , "op": "M: REX.W C7 /0 id"}, - {"inst": "mov w:r8, ib/ub" , "op": "B0+r ib"}, - {"inst": "mov w:r16, iw/uw" , "op": "66 B8+r iw"}, - {"inst": "mov W:r32, id/ud" , "op": "B8+r id"}, - {"inst": "mov W:r64, iq/uq" , "op": "REX.W B8+r iq"}, - {"inst": "mov w:r8, r8/m8" , "op": "RM: 8A /r"}, - {"inst": "mov w:r16, r16/m16" , "op": "RM: 66 8B /r"}, - {"inst": "mov W:r32, r32/m32" , "op": "RM: 8B /r"}, - {"inst": "mov W:r64, r64/m64" , "op": "RM: REX.W 8B /r"}, - {"inst": "mov w:r16/m16, sreg" , "op": "MR: 66 8C /r"}, - {"inst": "mov W:r32/m16, sreg" , "op": "MR: 8C /r"}, - {"inst": "mov W:r64/m16, sreg" , "op": "MR: REX.W 8C /r"}, - {"inst": "mov W:sreg, r16/m16" , "op": "RM: 66 8E /r"}, - {"inst": "mov W:sreg, r32/m16" , "op": "RM: 8E /r"}, - {"inst": "mov W:sreg, r64/m16" , "op": "RM: REX.W 8E /r"}, - {"inst": "mov w:al, moff8" , "op": "A0 moff"}, - {"inst": "mov w:ax, moff16" , "op": "66 A1 moff"}, - {"inst": "mov W:eax, moff32" , "op": "A1 moff"}, - {"inst": "mov W:rax, moff64" , "op": "REX.W A1 moff"}, - {"inst": "mov W:moff8, al" , "op": "A2 moff"}, - {"inst": "mov W:moff16, ax" , "op": "66 A3 moff"}, - {"inst": "mov W:moff32, eax" , "op": "A3 moff"}, - {"inst": "mov W:moff64, rax" , "op": "REX.W A3 moff"}, - {"inst": "mov W:r32, creg" , "op": "MR: 0F 20 /r" , "arch": "X86", "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, - {"inst": "mov W:r64, creg" , "op": "MR: 0F 20 /r" , "arch": "X64", "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, - {"inst": "mov W:creg, r32" , "op": "RM: 0F 22 /r" , "arch": "X86", "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, - {"inst": "mov W:creg, r64" , "op": "RM: 0F 22 /r" , "arch": "X64", "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, - {"inst": "mov W:r32, dreg" , "op": "MR: 0F 21 /r" , "arch": "X86", "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, - {"inst": "mov W:r64, dreg" , "op": "MR: 0F 21 /r" , "arch": "X64", "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, - {"inst": "mov W:dreg, r32" , "op": "RM: 0F 23 /r" , "arch": "X86", "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, - {"inst": "mov W:dreg, r64" , "op": "RM: 0F 23 /r" , "arch": "X64", "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, - {"inst": "movabs W:r64, iq/uq" , "op": "REX.W B8+r iq"}, - {"inst": "movabs w:al, moff8" , "op": "A0 moff"}, - {"inst": "movabs w:ax, moff16" , "op": "66 A1 moff"}, - {"inst": "movabs W:eax, moff32" , "op": "A1 moff"}, - {"inst": "movabs W:rax, moff64" , "op": "REX.W A1 moff"}, - {"inst": "movabs W:moff8, al" , "op": "A2 moff"}, - {"inst": "movabs W:moff16, ax" , "op": "66 A3 moff"}, - {"inst": "movabs W:moff32, eax" , "op": "A3 moff"}, - {"inst": "movabs W:moff64, rax" , "op": "REX.W A3 moff"}, - {"inst": "[rep] movs W:m8(es:zdi), R:m8(ds:zsi)" , "op": "A4" , "io": "DF=R"}, - {"inst": "[rep] movs W:m16(es:zdi), R:m16(ds:zsi)" , "op": "66 A5" , "io": "DF=R"}, - {"inst": "[rep] movs W:m32(es:zdi), R:m32(ds:zsi)" , "op": "A5" , "io": "DF=R"}, - {"inst": "[rep] movs W:m64(es:zdi), R:m64(ds:zsi)" , "op": "REX.W A5" , "io": "DF=R"}, - {"inst": "movsx w:r16, r8/m8" , "op": "RM: 66 0F BE /r"}, - {"inst": "movsx W:r32, r8/m8" , "op": "RM: 0F BE /r"}, - {"inst": "movsx W:r64, r8/m8" , "op": "RM: REX.W 0F BE /r"}, - {"inst": "movsx W:r32, r16/m16" , "op": "RM: 0F BF /r"}, - {"inst": "movsx W:r64, r16/m16" , "op": "RM: REX.W 0F BF /r"}, - {"inst": "movsxd W:r16, r16/m16" , "op": "RM: 66 63 /r" , "arch": "X64"}, - {"inst": "movsxd W:r32, r32/m32" , "op": "RM: 63 /r" , "arch": "X64"}, - {"inst": "movsxd W:r64, r32/m32" , "op": "RM: REX.W 63 /r" , "arch": "X64"}, - {"inst": "movzx w:r16, r8/m8" , "op": "RM: 66 0F B6 /r"}, - {"inst": "movzx W:r32, r8/m8" , "op": "RM: 0F B6 /r"}, - {"inst": "movzx W:r64, r8/m8" , "op": "RM: REX.W 0F B6 /r"}, - {"inst": "movzx W:r32, r16/m16" , "op": "RM: 0F B7 /r"}, - {"inst": "movzx W:r64, r16/m16" , "op": "RM: REX.W 0F B7 /r"}, - {"inst": "mul x:, r8/m8" , "op": "F6 /4" , "io": "OF=W SF=U ZF=U AF=U PF=U CF=W"}, - {"inst": "mul w:, x:, r16/m16" , "op": "66 F7 /4" , "io": "OF=W SF=U ZF=U AF=U PF=U CF=W"}, - {"inst": "mul W:, X:, r32/m32" , "op": "F7 /4" , "io": "OF=W SF=U ZF=U AF=U PF=U CF=W"}, - {"inst": "mul W:, X:, r64/m64" , "op": "REX.W F7 /4" , "io": "OF=W SF=U ZF=U AF=U PF=U CF=W"}, - {"inst": "[lock|xacqrel] neg x:r8/m8" , "op": "F6 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] neg x:r16/m16" , "op": "66 F7 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] neg X:r32/m32" , "op": "F7 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] neg X:r64/m64" , "op": "REX.W F7 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "nop" , "op": "90"}, - {"inst": "nop R:r16/m16" , "op": "66 0F 1F /0"}, - {"inst": "nop R:r32/m32" , "op": "0F 1F /0"}, - {"inst": "nop R:r64/m64" , "op": "REX.W 0F 1F /0"}, - {"inst": "nop R:r16/m16, r16" , "op": "MR: 66 0F 1F /r"}, - {"inst": "nop R:r32/m32, r32" , "op": "MR: 0F 1F /r"}, - {"inst": "nop R:r64/m64, r64" , "op": "MR: REX.W 0F 1F /r"}, - {"inst": "[lock|xacqrel] not x:r8/m8" , "op": "F6 /2"}, - {"inst": "[lock|xacqrel] not x:r16/m16" , "op": "66 F7 /2"}, - {"inst": "[lock|xacqrel] not X:r32/m32" , "op": "F7 /2"}, - {"inst": "[lock|xacqrel] not X:r64/m64" , "op": "REX.W F7 /2"}, - {"inst": "or x:al, ib/ub" , "op": "0C ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "or x:ax, iw/uw" , "op": "66 0D iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "or X:eax, id/ud" , "op": "0D id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "or X:rax, id" , "op": "REX.W 0D id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "[lock|xacqrel] or x:r8/m8, ib/ub" , "op": "M: 80 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] or x:r16/m16, iw/uw" , "op": "M: 66 81 /1 iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] or X:r32/m32, id/ud" , "op": "M: 81 /1 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] or X:r64/m64, id" , "op": "M: REX.W 81 /1 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] or x:r16/m16, ib" , "op": "M: 66 83 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] or X:r32/m32, ib" , "op": "M: 83 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] or X:r64/m64, ib" , "op": "M: REX.W 83 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] or x:~r8/m8, ~r8" , "op": "MR: 08 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] or x:~r16/m16, ~r16" , "op": "MR: 66 09 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] or X:~r32/m32, ~r32" , "op": "MR: 09 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] or X:~r64/m64, ~r64" , "op": "MR: REX.W 09 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "or x:~r8, ~r8/m8" , "op": "RM: 0A /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "or x:~r16, ~r16/m16" , "op": "RM: 66 0B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "or X:~r32, ~r32/m32" , "op": "RM: 0B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "or X:~r64, ~r64/m64" , "op": "RM: REX.W 0B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "pop w:r16/m16" , "op": "66 8F /0"}, - {"inst": "pop W:r32/m32" , "op": "8F /0" , "arch": "X86"}, - {"inst": "pop W:r64/m64" , "op": "8F /0" , "arch": "X64"}, - {"inst": "pop w:r16" , "op": "66 58+r"}, - {"inst": "pop W:r32" , "op": "58+r" , "arch": "X86"}, - {"inst": "pop W:r64" , "op": "58+r" , "arch": "X64"}, - {"inst": "pop W:ds" , "op": "1F" , "arch": "X86"}, - {"inst": "pop W:es" , "op": "07" , "arch": "X86"}, - {"inst": "pop W:ss" , "op": "17" , "arch": "X86"}, - {"inst": "pop W:fs" , "op": "0F A1"}, - {"inst": "pop W:gs" , "op": "0F A9"}, - {"inst": "popf" , "op": "66 9D" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=W IF=W TF=W"}, - {"inst": "popfd" , "op": "9D" , "arch": "X86", "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=W IF=W TF=W"}, - {"inst": "popfq" , "op": "9D" , "arch": "X64", "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=W IF=W TF=W"}, - {"inst": "push R:r16/m16" , "op": "66 FF /6"}, - {"inst": "push R:r32/m32" , "op": "FF /6" , "arch": "X86"}, - {"inst": "push R:r64/m64" , "op": "FF /6" , "arch": "X64"}, - {"inst": "push R:r16" , "op": "66 50+r"}, - {"inst": "push R:r32" , "op": "50+r" , "arch": "X86"}, - {"inst": "push R:r64" , "op": "50+r" , "arch": "X64"}, - {"inst": "push ib" , "op": "6A ib"}, - {"inst": "push id/ud" , "op": "68 id" , "arch": "X86"}, - {"inst": "push id" , "op": "68 id" , "arch": "X64"}, - {"inst": "push R:cs" , "op": "0E" , "arch": "X86"}, - {"inst": "push R:ss" , "op": "16" , "arch": "X86"}, - {"inst": "push R:ds" , "op": "1E" , "arch": "X86"}, - {"inst": "push R:es" , "op": "06" , "arch": "X86"}, - {"inst": "push R:fs" , "op": "0F A0"}, - {"inst": "push R:gs" , "op": "0F A8"}, - {"inst": "pushf" , "op": "66 9C" , "io": "OF=R SF=R ZF=R AF=R PF=R CF=R DF=R IF=R TF=R"}, - {"inst": "pushfd" , "op": "9C" , "arch": "X86", "io": "OF=R SF=R ZF=R AF=R PF=R CF=R DF=R IF=R TF=R"}, - {"inst": "pushfq" , "op": "9C" , "arch": "X64", "io": "OF=R SF=R ZF=R AF=R PF=R CF=R DF=R IF=R TF=R"}, - {"inst": "pushw iw" , "op": "66 68 iw"}, - {"inst": "rcl x:r8/m8, 1" , "op": "D0 /2" , "io": "CF=X OF=X", "altForm": true}, - {"inst": "rcl x:r8/m8, cl" , "op": "D2 /2" , "io": "CF=X OF=X"}, - {"inst": "rcl x:r8/m8, ib/ub" , "op": "M: C0 /2 ib" , "io": "CF=X OF=X"}, - {"inst": "rcl x:r16/m16, 1" , "op": "66 D1 /2" , "io": "CF=X OF=X", "altForm": true}, - {"inst": "rcl x:r16/m16, cl" , "op": "66 D3 /2" , "io": "CF=X OF=X"}, - {"inst": "rcl x:r16/m16, ib/ub" , "op": "M: 66 C1 /2 ib" , "io": "CF=X OF=X"}, - {"inst": "rcl X:r32/m32, 1" , "op": "D1 /2" , "io": "CF=X OF=X", "altForm": true}, - {"inst": "rcl X:r32/m32, cl" , "op": "D3 /2" , "io": "CF=X OF=X"}, - {"inst": "rcl X:r32/m32, ib/ub" , "op": "M: C1 /2 ib" , "io": "CF=X OF=X"}, - {"inst": "rcl X:r64/m64, 1" , "op": "REX.W D1 /2" , "io": "CF=X OF=X", "altForm": true}, - {"inst": "rcl X:r64/m64, cl" , "op": "REX.W D3 /2" , "io": "CF=X OF=X"}, - {"inst": "rcl X:r64/m64, ib/ub" , "op": "M: REX.W C1 /2 ib" , "io": "CF=X OF=X"}, - {"inst": "rcr x:r8/m8, 1" , "op": "D0 /3" , "io": "CF=X OF=X", "altForm": true}, - {"inst": "rcr x:r8/m8, cl" , "op": "D2 /3" , "io": "CF=X OF=X"}, - {"inst": "rcr x:r8/m8, ib/ub" , "op": "M: C0 /3 ib" , "io": "CF=X OF=X"}, - {"inst": "rcr x:r16/m16, 1" , "op": "66 D1 /3" , "io": "CF=X OF=X", "altForm": true}, - {"inst": "rcr x:r16/m16, cl" , "op": "66 D3 /3" , "io": "CF=X OF=X"}, - {"inst": "rcr x:r16/m16, ib/ub" , "op": "M: 66 C1 /3 ib" , "io": "CF=X OF=X"}, - {"inst": "rcr X:r32/m32, 1" , "op": "D1 /3" , "io": "CF=X OF=X", "altForm": true}, - {"inst": "rcr X:r32/m32, cl" , "op": "D3 /3" , "io": "CF=X OF=X"}, - {"inst": "rcr X:r32/m32, ib/ub" , "op": "M: C1 /3 ib" , "io": "CF=X OF=X"}, - {"inst": "rcr X:r64/m64, 1" , "op": "REX.W D1 /3" , "io": "CF=X OF=X", "altForm": true}, - {"inst": "rcr X:r64/m64, cl" , "op": "REX.W D3 /3" , "io": "CF=X OF=X"}, - {"inst": "rcr X:r64/m64, ib/ub" , "op": "M: REX.W C1 /3 ib" , "io": "CF=X OF=X"}, - {"inst": "[bnd|repIgnore] ret" , "op": "C3"}, - {"inst": "[bnd|repIgnore] ret uw" , "op": "C2 iw"}, - {"inst": "retf" , "op": "CB"}, - {"inst": "retf uw" , "op": "CA iw"}, - {"inst": "rol x:r8/m8, 1" , "op": "D0 /0" , "io": "CF=W OF=W", "altForm": true}, - {"inst": "rol x:r8/m8, cl" , "op": "D2 /0" , "io": "CF=W OF=W"}, - {"inst": "rol x:r8/m8, ib/ub" , "op": "M: C0 /0 ib" , "io": "CF=W OF=W"}, - {"inst": "rol x:r16/m16, 1" , "op": "66 D1 /0" , "io": "CF=W OF=W", "altForm": true}, - {"inst": "rol x:r16/m16, cl" , "op": "66 D3 /0" , "io": "CF=W OF=W"}, - {"inst": "rol x:r16/m16, ib/ub" , "op": "M: 66 C1 /0 ib" , "io": "CF=W OF=W"}, - {"inst": "rol X:r32/m32, 1" , "op": "D1 /0" , "io": "CF=W OF=W", "altForm": true}, - {"inst": "rol X:r32/m32, cl" , "op": "D3 /0" , "io": "CF=W OF=W"}, - {"inst": "rol X:r32/m32, ib/ub" , "op": "M: C1 /0 ib" , "io": "CF=W OF=W"}, - {"inst": "rol X:r64/m64, 1" , "op": "REX.W D1 /0" , "io": "CF=W OF=W", "altForm": true}, - {"inst": "rol X:r64/m64, cl" , "op": "REX.W D3 /0" , "io": "CF=W OF=W"}, - {"inst": "rol X:r64/m64, ib/ub" , "op": "M: REX.W C1 /0 ib" , "io": "CF=W OF=W"}, - {"inst": "ror x:r8/m8, 1" , "op": "D0 /1" , "io": "CF=W OF=W", "altForm": true}, - {"inst": "ror x:r8/m8, cl" , "op": "D2 /1" , "io": "CF=W OF=W"}, - {"inst": "ror x:r8/m8, ib/ub" , "op": "M: C0 /1 ib" , "io": "CF=W OF=W"}, - {"inst": "ror x:r16/m16, 1" , "op": "66 D1 /1" , "io": "CF=W OF=W", "altForm": true}, - {"inst": "ror x:r16/m16, cl" , "op": "66 D3 /1" , "io": "CF=W OF=W"}, - {"inst": "ror x:r16/m16, ib/ub" , "op": "M: 66 C1 /1 ib" , "io": "CF=W OF=W"}, - {"inst": "ror X:r32/m32, 1" , "op": "D1 /1" , "io": "CF=W OF=W", "altForm": true}, - {"inst": "ror X:r32/m32, cl" , "op": "D3 /1" , "io": "CF=W OF=W"}, - {"inst": "ror X:r32/m32, ib/ub" , "op": "M: C1 /1 ib" , "io": "CF=W OF=W"}, - {"inst": "ror X:r64/m64, 1" , "op": "REX.W D1 /1" , "io": "CF=W OF=W", "altForm": true}, - {"inst": "ror X:r64/m64, cl" , "op": "REX.W D3 /1" , "io": "CF=W OF=W"}, - {"inst": "ror X:r64/m64, ib/ub" , "op": "M: REX.W C1 /1 ib" , "io": "CF=W OF=W"}, - {"inst": "sar x:r8/m8, 1" , "op": "D0 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "sar x:r8/m8, cl" , "op": "D2 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sar x:r8/m8, ib/ub" , "op": "M: C0 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sar x:r16/m16, 1" , "op": "66 D1 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "sar x:r16/m16, cl" , "op": "66 D3 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sar x:r16/m16, ib/ub" , "op": "M: 66 C1 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sar X:r32/m32, 1" , "op": "D1 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "sar X:r32/m32, cl" , "op": "D3 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sar X:r32/m32, ib/ub" , "op": "M: C1 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sar X:r64/m64, 1" , "op": "REX.W D1 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "sar X:r64/m64, cl" , "op": "REX.W D3 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sar X:r64/m64, ib/ub" , "op": "M: REX.W C1 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sbb x:al, ib/ub" , "op": "1C ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X", "altForm": true}, - {"inst": "sbb x:ax, iw/uw" , "op": "66 1D iw" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X", "altForm": true}, - {"inst": "sbb X:eax, id/ud" , "op": "1D id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X", "altForm": true}, - {"inst": "sbb X:rax, id" , "op": "REX.W 1D id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X", "altForm": true}, - {"inst": "[lock|xacqrel] sbb x:r8/m8, ib/ub" , "op": "M: 80 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] sbb x:r16/m16, iw/uw" , "op": "M: 66 81 /3 iw" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] sbb X:r32/m32, id/ud" , "op": "M: 81 /3 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] sbb X:r64/m64, id" , "op": "M: REX.W 81 /3 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] sbb x:r16/m16, ib" , "op": "M: 66 83 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] sbb X:r32/m32, ib" , "op": "M: 83 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] sbb X:r64/m64, ib" , "op": "M: REX.W 83 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] sbb x:r8/m8, r8" , "op": "MR: 18 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] sbb x:r16/m16, r16" , "op": "MR: 66 19 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] sbb X:r32/m32, r32" , "op": "MR: 19 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[lock|xacqrel] sbb X:r64/m64, r64" , "op": "MR: REX.W 19 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "sbb x:r8, r8/m8" , "op": "RM: 1A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "sbb x:r16, r16/m16" , "op": "RM: 66 1B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "sbb X:r32, r32/m32" , "op": "RM: 1B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "sbb X:r64, r64/m64" , "op": "RM: REX.W 1B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, - {"inst": "[rep|repne] scas R:al, R:m8(es:zdi)" , "op": "AE" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, - {"inst": "[rep|repne] scas R:ax, R:m16(es:zdi)" , "op": "66 AF" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, - {"inst": "[rep|repne] scas R:eax, R:m32(es:zdi)" , "op": "AF" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, - {"inst": "[rep|repne] scas R:rax, R:m64(es:zdi)" , "op": "REX.W AF" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, - {"inst": "seto w:r8/m8" , "op": "0F 90 /r" , "io": "OF=R"}, - {"inst": "setno w:r8/m8" , "op": "0F 91 /r" , "io": "OF=R"}, - {"inst": "setb|setnae|setc w:r8/m8" , "op": "0F 92 /r" , "io": "CF=R"}, - {"inst": "setae|setnb|setnc w:r8/m8" , "op": "0F 93 /r" , "io": "CF=R"}, - {"inst": "sete|setz w:r8/m8" , "op": "0F 94 /r" , "io": "ZF=R"}, - {"inst": "setne|setnz w:r8/m8" , "op": "0F 95 /r" , "io": "ZF=R"}, - {"inst": "setbe|setna w:r8/m8" , "op": "0F 96 /r" , "io": "CF=R ZF=R"}, - {"inst": "seta|setnbe w:r8/m8" , "op": "0F 97 /r" , "io": "CF=R ZF=R"}, - {"inst": "sets w:r8/m8" , "op": "0F 98 /r" , "io": "SF=R"}, - {"inst": "setns w:r8/m8" , "op": "0F 99 /r" , "io": "SF=R"}, - {"inst": "setp|setpe w:r8/m8" , "op": "0F 9A /r" , "io": "PF=R"}, - {"inst": "setnp|setpo w:r8/m8" , "op": "0F 9B /r" , "io": "PF=R"}, - {"inst": "setl|setnge w:r8/m8" , "op": "0F 9C /r" , "io": "SF=R OF=R"}, - {"inst": "setge|setnl w:r8/m8" , "op": "0F 9D /r" , "io": "SF=R OF=R"}, - {"inst": "setle|setng w:r8/m8" , "op": "0F 9E /r" , "io": "ZF=R SF=R OF=R"}, - {"inst": "setg|setnle w:r8/m8" , "op": "0F 9F /r" , "io": "ZF=R SF=R OF=R"}, - {"inst": "shl|sal x:r8/m8, 1" , "op": "D0 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "shl|sal x:r8/m8, cl" , "op": "D2 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shl|sal x:r8/m8, ib/ub" , "op": "M: C0 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shl|sal x:r16/m16, 1" , "op": "66 D1 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "shl|sal x:r16/m16, cl" , "op": "66 D3 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shl|sal x:r16/m16, ib/ub" , "op": "M: 66 C1 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shl|sal X:r32/m32, 1" , "op": "D1 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "shl|sal X:r32/m32, cl" , "op": "D3 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shl|sal X:r32/m32, ib/ub" , "op": "M: C1 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shl|sal X:r64/m64, 1" , "op": "REX.W D1 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "shl|sal X:r64/m64, cl" , "op": "REX.W D3 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shl|sal X:r64/m64, ib/ub" , "op": "M: REX.W C1 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shr x:r8/m8, 1" , "op": "D0 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "shr x:r8/m8, cl" , "op": "D2 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shr x:r8/m8, ib/ub" , "op": "M: C0 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shr x:r16/m16, 1" , "op": "66 D1 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "shr x:r16/m16, cl" , "op": "66 D3 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shr x:r16/m16, ib/ub" , "op": "M: 66 C1 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shr X:r32/m32, 1" , "op": "D1 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "shr X:r32/m32, cl" , "op": "D3 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shr X:r32/m32, ib/ub" , "op": "M: C1 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shr X:r64/m64, 1" , "op": "REX.W D1 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "shr X:r64/m64, cl" , "op": "REX.W D3 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shr X:r64/m64, ib/ub" , "op": "M: REX.W C1 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "shld x:r16/m16, r16, cl" , "op": "MR: 66 0F A5 /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "shld x:r16/m16, r16, ib/ub" , "op": "MR: 66 0F A4 /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "shld X:r32/m32, r32, cl" , "op": "MR: 0F A5 /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "shld X:r32/m32, r32, ib/ub" , "op": "MR: 0F A4 /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "shld X:r64/m64, r64, cl" , "op": "MR: REX.W 0F A5 /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "shld X:r64/m64, r64, ib/ub" , "op": "MR: REX.W 0F A4 /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "shrd x:r16/m16, r16, cl" , "op": "MR: 66 0F AD /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "shrd x:r16/m16, r16, ib/ub" , "op": "MR: 66 0F AC /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "shrd X:r32/m32, r32, cl" , "op": "MR: 0F AD /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "shrd X:r32/m32, r32, ib/ub" , "op": "MR: 0F AC /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "shrd X:r64/m64, r64, cl" , "op": "MR: REX.W 0F AD /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "shrd X:r64/m64, r64, ib/ub" , "op": "MR: REX.W 0F AC /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, - {"inst": "stc" , "op": "F9" , "io": "CF=1"}, - {"inst": "std" , "op": "FD" , "io": "DF=1"}, - {"inst": "[rep] stos W:m8(es:zdi), R:al" , "op": "AA" , "io": "DF=R"}, - {"inst": "[rep] stos W:m16(es:zdi), R:ax" , "op": "66 AB" , "io": "DF=R"}, - {"inst": "[rep] stos W:m32(es:zdi), R:eax" , "op": "AB" , "io": "DF=R"}, - {"inst": "[rep] stos W:m64(es:zdi), R:rax" , "op": "REX.W AB" , "io": "DF=R"}, - {"inst": "sub x:al, ib/ub" , "op": "2C ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "sub x:ax, iw/uw" , "op": "66 2D iw" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "sub X:eax, id/ud" , "op": "2D id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "sub X:rax, id" , "op": "REX.W 2D id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W", "altForm": true}, - {"inst": "[lock|xacqrel] sub x:r8/m8, ib/ub" , "op": "M: 80 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] sub x:r16/m16, iw/uw" , "op": "M: 66 81 /5 iw" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] sub X:r32/m32, id/ud" , "op": "M: 81 /5 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] sub X:r64/m64, id" , "op": "M: REX.W 81 /5 id" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] sub x:r16/m16, ib" , "op": "M: 66 83 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] sub X:r32/m32, ib" , "op": "M: 83 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] sub X:r64/m64, ib" , "op": "M: REX.W 83 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] sub x:r8/m8, r8" , "op": "MR: 28 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] sub x:r16/m16, r16" , "op": "MR: 66 29 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] sub X:r32/m32, r32" , "op": "MR: 29 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] sub X:r64/m64, r64" , "op": "MR: REX.W 29 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sub x:r8, r8/m8" , "op": "RM: 2A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sub x:r16, r16/m16" , "op": "RM: 66 2B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sub X:r32, r32/m32" , "op": "RM: 2B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "sub X:r64, r64/m64" , "op": "RM: REX.W 2B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "test R:al, ib/ub" , "op": "A8 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "test R:ax, iw/uw" , "op": "66 A9 iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "test R:eax, id/ud" , "op": "A9 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "test R:rax, id" , "op": "REX.W A9 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "test R:r8/m8, ib/ub" , "op": "M: F6 /0 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "test R:r16/m16, iw/uw" , "op": "M: 66 F7 /0 iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "test R:r32/m32, id/ud" , "op": "M: F7 /0 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "test R:r64/m64, id" , "op": "M: REX.W F7 /0 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "test R:~r8/m8, ~r8" , "op": "MR: 84 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "test R:~r16/m16, ~r16" , "op": "MR: 66 85 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "test R:~r32/m32, ~r32" , "op": "MR: 85 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "test R:~r64/m64, ~r64" , "op": "MR: REX.W 85 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "ud0 r32, r32/m32" , "op": "RM: 0F FF /r"}, - {"inst": "ud1 r32, r32/m32" , "op": "RM: 0F B9 /r"}, - {"inst": "ud2" , "op": "0F 0B"}, - {"inst": "xchg x:~ax, x:~r16" , "op": "66 90+r" , "altForm": true}, - {"inst": "xchg X:~eax, X:~r32" , "op": "90+r" , "altForm": true}, - {"inst": "xchg X:~rax, X:~r64" , "op": "REX.W 90+r" , "altForm": true}, - {"inst": "xchg x:~r16, x:~ax" , "op": "66 90+r" , "altForm": true}, - {"inst": "xchg X:~r32, X:~eax" , "op": "90+r" , "altForm": true}, - {"inst": "xchg X:~r64, X:~rax" , "op": "REX.W 90+r" , "altForm": true}, - {"inst": "[ilock|xacquire] xchg x:~r8/m8, x:~r8" , "op": "MR: 86 /r"}, - {"inst": "[ilock|xacquire] xchg x:~r16/m16, x:~r16" , "op": "MR: 66 87 /r"}, - {"inst": "[ilock|xacquire] xchg X:~r32/m32, X:~r32" , "op": "MR: 87 /r"}, - {"inst": "[ilock|xacquire] xchg X:~r64/m64, X:~r64" , "op": "MR: REX.W 87 /r"}, - {"inst": "[ilock|xacquire] xchg x:~r8, x:~r8/m8" , "op": "RM: 86 /r"}, - {"inst": "[ilock|xacquire] xchg x:~r16, x:~r16/m16" , "op": "RM: 66 87 /r"}, - {"inst": "[ilock|xacquire] xchg X:~r32, X:~r32/m32" , "op": "RM: 87 /r"}, - {"inst": "[ilock|xacquire] xchg X:~r64, X:~r64/m64" , "op": "RM: REX.W 87 /r"}, - {"inst": "xor x:al, ib/ub" , "op": "34 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "xor x:ax, iw/uw" , "op": "66 35 iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "xor X:eax, id/ud" , "op": "35 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "xor X:rax, id" , "op": "REX.W 35 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0", "altForm": true}, - {"inst": "[lock|xacqrel] xor x:r8/m8, ib/ub" , "op": "M: 80 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] xor x:r16/m16, iw/uw" , "op": "M: 66 81 /6 iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] xor X:r32/m32, id/ud" , "op": "M: 81 /6 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] xor X:r64/m64, id" , "op": "M: REX.W 81 /6 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] xor x:r16/m16, ib" , "op": "M: 66 83 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] xor X:r32/m32, ib" , "op": "M: 83 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] xor X:r64/m64, ib" , "op": "M: REX.W 83 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] xor x:~r8/m8, ~r8" , "op": "MR: 30 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] xor x:~r16/m16, ~r16" , "op": "MR: 66 31 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] xor X:~r32/m32, ~r32" , "op": "MR: 31 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "[lock|xacqrel] xor X:~r64/m64, ~r64" , "op": "MR: REX.W 31 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "xor x:~r8, ~r8/m8" , "op": "RM: 32 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "xor x:~r16, ~r16/m16" , "op": "RM: 66 33 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "xor X:~r32, ~r32/m32" , "op": "RM: 33 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, - {"inst": "xor X:~r64, ~r64/m64" , "op": "RM: REX.W 33 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"} - ]}, - - {"category": "GP GP_IN_OUT", "volatile": true, "data": [ - {"inst": "in w:al, ib/ub" , "op": "E4 ib"}, - {"inst": "in w:ax, ib/ub" , "op": "66 E5 ib"}, - {"inst": "in W:eax, ib/ub" , "op": "E5 ib"}, - {"inst": "in w:al, dx" , "op": "EC"}, - {"inst": "in w:ax, dx" , "op": "66 ED"}, - {"inst": "in W:eax, dx" , "op": "ED"}, - {"inst": "[rep] ins W:m8(es:zdi), dx" , "op": "6C"}, - {"inst": "[rep] ins W:m16(es:zdi), dx" , "op": "66 6D"}, - {"inst": "[rep] ins W:m32(es:zdi), dx" , "op": "6D"}, - {"inst": "out ub, al" , "op": "E6 ib"}, - {"inst": "out ub, ax" , "op": "66 E7 ib"}, - {"inst": "out ub, eax" , "op": "E7 ib"}, - {"inst": "out R:dx, R:al" , "op": "EE"}, - {"inst": "out R:dx, R:ax" , "op": "66 EF"}, - {"inst": "out R:dx, R:eax" , "op": "EF"}, - {"inst": "[rep] outs R:dx, R:m8(ds:zsi)" , "op": "6E"}, - {"inst": "[rep] outs R:dx, R:m16(ds:zsi)" , "op": "66 6F"}, - {"inst": "[rep] outs R:dx, R:m32(ds:zsi)" , "op": "6F"} - ]}, - - {"category": "GP GP_EXT", "ext": "I486", "data": [ - {"inst": "[lock|xacqrel] cmpxchg x:r8/m8, r8, " , "op": "MR: 0F B0 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] cmpxchg x:r16/m16, r16, " , "op": "MR: 66 0F B1 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] cmpxchg X:r32/m32, r32, " , "op": "MR: 0F B1 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] cmpxchg X:r64/m64, r64, " , "op": "MR: REX.W 0F B1 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "cpuid X:, W:, X:, W:" , "op": "0F A2" , "volatile": true}, - {"inst": "[lock|xacqrel] xadd x:r8/m8, x:r8" , "op": "MR: 0F C0 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] xadd x:r16/m16, x:r16" , "op": "MR: 66 0F C1 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] xadd X:r32/m32, X:r32" , "op": "MR: 0F C1 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, - {"inst": "[lock|xacqrel] xadd X:r64/m64, X:r64" , "op": "MR: REX.W 0F C1 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"} - ]}, - - {"category": "GP GP_EXT", "ext": "3DNOW", "volatile": true, "data": [ - {"inst": "prefetch R:mem" , "op": "0F 0D /0"} - ]}, - - {"category": "GP GP_EXT", "ext": "ADX", "data": [ - {"inst": "adcx X:~r32, ~r32/m32" , "op": "RM: 66 0F 38 F6 /r" , "io": "CF=X"}, - {"inst": "adcx X:~r64, ~r64/m64" , "op": "RM: REX.W 66 0F 38 F6 /r" , "io": "CF=X"}, - {"inst": "adox X:~r32, ~r32/m32" , "op": "RM: F3 0F 38 F6 /r" , "io": "OF=X"}, - {"inst": "adox X:~r64, ~r64/m64" , "op": "RM: REX.W F3 0F 38 F6 /r" , "io": "OF=X"} - ]}, - - {"category": "GP GP_EXT", "ext": "BMI", "data": [ - {"inst": "andn W:r32, r32, r32/m32" , "op": "RVM: VEX.LZ.0F38.W0 F2 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=0"}, - {"inst": "andn W:r64, r64, r64/m64" , "op": "RVM: VEX.LZ.0F38.W1 F2 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=0"}, - {"inst": "bextr W:r32, r32/m32, r32" , "op": "RMV: VEX.LZ.0F38.W0 F7 /r" , "io": "OF=0 SF=U ZF=W AF=U PF=U CF=0"}, - {"inst": "bextr W:r64, r64/m64, r64" , "op": "RMV: VEX.LZ.0F38.W1 F7 /r" , "io": "OF=0 SF=U ZF=W AF=U PF=U CF=0"}, - {"inst": "blsi W:r32, r32/m32" , "op": "VM: VEX.LZ.0F38.W0 F3 /3" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, - {"inst": "blsi W:r64, r64/m64" , "op": "VM: VEX.LZ.0F38.W1 F3 /3" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, - {"inst": "blsmsk W:r32, r32/m32" , "op": "VM: VEX.LZ.0F38.W0 F3 /2" , "io": "OF=0 SF=W ZF=0 AF=U PF=U CF=W"}, - {"inst": "blsmsk W:r64, r64/m64" , "op": "VM: VEX.LZ.0F38.W1 F3 /2" , "io": "OF=0 SF=W ZF=0 AF=U PF=U CF=W"}, - {"inst": "blsr W:r32, r32/m32" , "op": "VM: VEX.LZ.0F38.W0 F3 /1" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, - {"inst": "blsr W:r64, r64/m64" , "op": "VM: VEX.LZ.0F38.W1 F3 /1" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, - {"inst": "tzcnt w:r16, r16/m16" , "op": "RM: 66 F3 0F BC /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"}, - {"inst": "tzcnt W:r32, r32/m32" , "op": "RM: F3 0F BC /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"}, - {"inst": "tzcnt W:r64, r64/m64" , "op": "RM: REX.W F3 0F BC /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"} - ]}, - - {"category": "GP GP_EXT", "ext": "BMI2", "data": [ - {"inst": "bzhi W:r32, r32/m32, r32" , "op": "RMV: VEX.LZ.0F38.W0 F5 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, - {"inst": "bzhi W:r64, r64/m64, r64" , "op": "RMV: VEX.LZ.0F38.W1 F5 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, - {"inst": "mulx W:r32, W:r32, ~r32/m32, ~" , "op": "RVM: VEX.LZ.F2.0F38.W0 F6 /r"}, - {"inst": "mulx W:r64, W:r64, ~r64/m64, ~" , "op": "RVM: VEX.LZ.F2.0F38.W1 F6 /r"}, - {"inst": "pdep W:r32, r32, r32/m32" , "op": "RVM: VEX.LZ.F2.0F38.W0 F5 /r"}, - {"inst": "pdep W:r64, r64, r64/m64" , "op": "RVM: VEX.LZ.F2.0F38.W1 F5 /r"}, - {"inst": "pext W:r32, r32, r32/m32" , "op": "RVM: VEX.LZ.F3.0F38.W0 F5 /r"}, - {"inst": "pext W:r64, r64, r64/m64" , "op": "RVM: VEX.LZ.F3.0F38.W1 F5 /r"}, - {"inst": "rorx W:r32, r32/m32, ib/ub" , "op": "RM: VEX.LZ.F2.0F3A.W0 F0 /r ib"}, - {"inst": "rorx W:r64, r64/m64, ib/ub" , "op": "RM: VEX.LZ.F2.0F3A.W1 F0 /r ib"}, - {"inst": "sarx W:r32, r32/m32, r32" , "op": "RMV: VEX.LZ.F3.0F38.W0 F7 /r"}, - {"inst": "sarx W:r64, r64/m64, r64" , "op": "RMV: VEX.LZ.F3.0F38.W1 F7 /r"}, - {"inst": "shlx W:r32, r32/m32, r32" , "op": "RMV: VEX.LZ.66.0F38.W0 F7 /r"}, - {"inst": "shlx W:r64, r64/m64, r64" , "op": "RMV: VEX.LZ.66.0F38.W1 F7 /r"}, - {"inst": "shrx W:r32, r32/m32, r32" , "op": "RMV: VEX.LZ.F2.0F38.W0 F7 /r"}, - {"inst": "shrx W:r64, r64/m64, r64" , "op": "RMV: VEX.LZ.F2.0F38.W1 F7 /r"} - ]}, - - {"category": "GP GP_EXT", "ext": "CET_SS", "volatile": true, "data": [ - {"inst": "incsspd r32" , "op": "F3 0F AE /5"}, - {"inst": "incsspq r64" , "op": "REX.W F3 0F AE /5"}, - {"inst": "rdsspd W:r32" , "op": "F3 0F 1E /1"}, - {"inst": "rdsspq W:r64" , "op": "REX.W F3 0F 1E /1"}, - {"inst": "rstorssp R:m64" , "op": "F3 0F 01 /5" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}, - {"inst": "saveprevssp" , "op": "F3 0F 01 EA" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"} - ]}, - - {"category": "GP GP_EXT", "ext": "CLDEMOTE", "data": [ - {"inst": "cldemote R:mem" , "op": "0F 1C /0"} - ]}, - - {"category": "GP GP_EXT", "ext": "CLFLUSH", "data": [ - {"inst": "clflush R:mem" , "op": "0F AE /7"} - ]}, - - {"category": "GP GP_EXT", "ext": "CLFLUSHOPT", "data": [ - {"inst": "clflushopt R:mem" , "op": "66 0F AE /7"} - ]}, - - {"category": "GP GP_EXT", "ext": "CLWB", "data": [ - {"inst": "clwb R:mem" , "op": "66 0F AE /6"} - ]}, - - {"category": "GP GP_EXT", "ext": "CLZERO", "data": [ - {"inst": "clzero R:" , "op": "0F 01 FC"} - ]}, - - {"category": "GP GP_EXT", "ext": "CMOV", "data": [ - {"inst": "cmovo x:r16, r16/m16" , "op": "RM: 66 0F 40 /r" , "io": "OF=R"}, - {"inst": "cmovo X:r32, r32/m32" , "op": "RM: 0F 40 /r" , "io": "OF=R"}, - {"inst": "cmovo X:r64, r64/m64" , "op": "RM: REX.W 0F 40 /r" , "io": "OF=R"}, - {"inst": "cmovno x:r16, r16/m16" , "op": "RM: 66 0F 41 /r" , "io": "OF=R"}, - {"inst": "cmovno X:r32, r32/m32" , "op": "RM: 0F 41 /r" , "io": "OF=R"}, - {"inst": "cmovno X:r64, r64/m64" , "op": "RM: REX.W 0F 41 /r" , "io": "OF=R"}, - {"inst": "cmovb|cmovnae|cmovc x:r16, r16/m16" , "op": "RM: 66 0F 42 /r" , "io": "CF=R"}, - {"inst": "cmovb|cmovnae|cmovc X:r32, r32/m32" , "op": "RM: 0F 42 /r" , "io": "CF=R"}, - {"inst": "cmovb|cmovnae|cmovc X:r64, r64/m64" , "op": "RM: REX.W 0F 42 /r" , "io": "CF=R"}, - {"inst": "cmovae|cmovnb|cmovnc x:r16, r16/m16" , "op": "RM: 66 0F 43 /r" , "io": "CF=R"}, - {"inst": "cmovae|cmovnb|cmovnc X:r32, r32/m32" , "op": "RM: 0F 43 /r" , "io": "CF=R"}, - {"inst": "cmovae|cmovnb|cmovnc X:r64, r64/m64" , "op": "RM: REX.W 0F 43 /r" , "io": "CF=R"}, - {"inst": "cmove|cmovz x:r16, r16/m16" , "op": "RM: 66 0F 44 /r" , "io": "ZF=R"}, - {"inst": "cmove|cmovz X:r32, r32/m32" , "op": "RM: 0F 44 /r" , "io": "ZF=R"}, - {"inst": "cmove|cmovz X:r64, r64/m64" , "op": "RM: REX.W 0F 44 /r" , "io": "ZF=R"}, - {"inst": "cmovne|cmovnz x:r16, r16/m16" , "op": "RM: 66 0F 45 /r" , "io": "ZF=R"}, - {"inst": "cmovne|cmovnz X:r32, r32/m32" , "op": "RM: 0F 45 /r" , "io": "ZF=R"}, - {"inst": "cmovne|cmovnz X:r64, r64/m64" , "op": "RM: REX.W 0F 45 /r" , "io": "ZF=R"}, - {"inst": "cmovbe|cmovna x:r16, r16/m16" , "op": "RM: 66 0F 46 /r" , "io": "CF=R ZF=R"}, - {"inst": "cmovbe|cmovna X:r32, r32/m32" , "op": "RM: 0F 46 /r" , "io": "CF=R ZF=R"}, - {"inst": "cmovbe|cmovna X:r64, r64/m64" , "op": "RM: REX.W 0F 46 /r" , "io": "CF=R ZF=R"}, - {"inst": "cmova|cmovnbe x:r16, r16/m16" , "op": "RM: 66 0F 47 /r" , "io": "CF=R ZF=R"}, - {"inst": "cmova|cmovnbe X:r32, r32/m32" , "op": "RM: 0F 47 /r" , "io": "CF=R ZF=R"}, - {"inst": "cmova|cmovnbe X:r64, r64/m64" , "op": "RM: REX.W 0F 47 /r" , "io": "CF=R ZF=R"}, - {"inst": "cmovs x:r16, r16/m16" , "op": "RM: 66 0F 48 /r" , "io": "SF=R"}, - {"inst": "cmovs X:r32, r32/m32" , "op": "RM: 0F 48 /r" , "io": "SF=R"}, - {"inst": "cmovs X:r64, r64/m64" , "op": "RM: REX.W 0F 48 /r" , "io": "SF=R"}, - {"inst": "cmovns x:r16, r16/m16" , "op": "RM: 66 0F 49 /r" , "io": "SF=R"}, - {"inst": "cmovns X:r32, r32/m32" , "op": "RM: 0F 49 /r" , "io": "SF=R"}, - {"inst": "cmovns X:r64, r64/m64" , "op": "RM: REX.W 0F 49 /r" , "io": "SF=R"}, - {"inst": "cmovp|cmovpe x:r16, r16/m16" , "op": "RM: 66 0F 4A /r" , "io": "PF=R"}, - {"inst": "cmovp|cmovpe X:r32, r32/m32" , "op": "RM: 0F 4A /r" , "io": "PF=R"}, - {"inst": "cmovp|cmovpe X:r64, r64/m64" , "op": "RM: REX.W 0F 4A /r" , "io": "PF=R"}, - {"inst": "cmovnp|cmovpo x:r16, r16/m16" , "op": "RM: 66 0F 4B /r" , "io": "PF=R"}, - {"inst": "cmovnp|cmovpo X:r32, r32/m32" , "op": "RM: 0F 4B /r" , "io": "PF=R"}, - {"inst": "cmovnp|cmovpo X:r64, r64/m64" , "op": "RM: REX.W 0F 4B /r" , "io": "PF=R"}, - {"inst": "cmovl|cmovnge x:r16, r16/m16" , "op": "RM: 66 0F 4C /r" , "io": "SF=R OF=R"}, - {"inst": "cmovl|cmovnge X:r32, r32/m32" , "op": "RM: 0F 4C /r" , "io": "SF=R OF=R"}, - {"inst": "cmovl|cmovnge X:r64, r64/m64" , "op": "RM: REX.W 0F 4C /r" , "io": "SF=R OF=R"}, - {"inst": "cmovge|cmovnl x:r16, r16/m16" , "op": "RM: 66 0F 4D /r" , "io": "SF=R OF=R"}, - {"inst": "cmovge|cmovnl X:r32, r32/m32" , "op": "RM: 0F 4D /r" , "io": "SF=R OF=R"}, - {"inst": "cmovge|cmovnl X:r64, r64/m64" , "op": "RM: REX.W 0F 4D /r" , "io": "SF=R OF=R"}, - {"inst": "cmovle|cmovng x:r16, r16/m16" , "op": "RM: 66 0F 4E /r" , "io": "ZF=R SF=R OF=R"}, - {"inst": "cmovle|cmovng X:r32, r32/m32" , "op": "RM: 0F 4E /r" , "io": "ZF=R SF=R OF=R"}, - {"inst": "cmovle|cmovng X:r64, r64/m64" , "op": "RM: REX.W 0F 4E /r" , "io": "ZF=R SF=R OF=R"}, - {"inst": "cmovg|cmovnle x:r16, r16/m16" , "op": "RM: 66 0F 4F /r" , "io": "ZF=R SF=R OF=R"}, - {"inst": "cmovg|cmovnle X:r32, r32/m32" , "op": "RM: 0F 4F /r" , "io": "ZF=R SF=R OF=R"}, - {"inst": "cmovg|cmovnle X:r64, r64/m64" , "op": "RM: REX.W 0F 4F /r" , "io": "ZF=R SF=R OF=R"} - ]}, - - {"category": "GP GP_EXT", "ext": "CMPCCXADD", "data": [ - {"inst": "cmpbexadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 E6 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpbexadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 E6 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpbxadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 E2 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpbxadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 E2 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmplexadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 EE /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmplexadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 EE /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmplxadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 EC /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmplxadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 EC /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnbexadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 E7 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnbexadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 E7 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnbxadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 E3 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnbxadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 E3 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnlexadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 EF /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnlexadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 EF /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnlxadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 ED /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnlxadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 ED /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnoxadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 E1 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnoxadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 E1 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnpxadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 EB /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnpxadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 EB /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnsxadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 E9 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnsxadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 E9 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnzxadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 E5 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpnzxadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 E5 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpoxadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 E0 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpoxadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 E0 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmppxadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 EA /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmppxadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 EA /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpsxadd X:m32, X:r32, R:r32" , "op": "MVR: VEX.128.66.0F38.W0 E8 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpsxadd X:m64, X:r64, R:r64" , "op": "MVR: VEX.128.66.0F38.W1 E8 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpzxadd X:m32, X:r32, R:r32" , "op": "VEX.128.66.0F38.W0 E4 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, - {"inst": "cmpzxadd X:m64, X:r64, R:r64" , "op": "VEX.128.66.0F38.W1 E4 /r" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"} - ]}, - - {"category": "GP GP_EXT", "ext": "CMPXCHG8B", "data": [ - {"inst": "[lock|xacqrel] cmpxchg8b X:m64,X:,X:,," , "op": "0F C7 /1" , "io": "ZF=W"} - ]}, - - {"category": "GP GP_EXT", "ext": "CMPXCHG16B", "data": [ - {"inst": "[lock|xacqrel] cmpxchg16b X:m128,X:,X:,,","op": "REX.W 0F C7 /1" , "io": "ZF=W"} - ]}, - - {"category": "GP GP_EXT", "ext": "FSGSBASE", "arch": "X64", "volatile": true, "data": [ - {"inst": "rdfsbase W:r32" , "op": "F3 0F AE /0"}, - {"inst": "rdfsbase W:r64" , "op": "REX.W F3 0F AE /0"}, - {"inst": "rdgsbase W:r32" , "op": "F3 0F AE /1"}, - {"inst": "rdgsbase W:r64" , "op": "REX.W F3 0F AE /1"}, - {"inst": "wrfsbase R:r32" , "op": "F3 0F AE /2"}, - {"inst": "wrfsbase R:r64" , "op": "REX.W F3 0F AE /2"}, - {"inst": "wrgsbase R:r32" , "op": "F3 0F AE /3"}, - {"inst": "wrgsbase R:r64" , "op": "REX.W F3 0F AE /3"} - ]}, - - {"category": "GP GP_EXT", "ext": "FXSR", "volatile": true, "data": [ - {"inst": "fxrstor R:mem" , "op": "0F AE /1" , "io": "C0=W C1=W C2=W C3=W"}, - {"inst": "fxrstor64 R:mem" , "op": "REX.W 0F AE /1" , "io": "C0=W C1=W C2=W C3=W"}, - {"inst": "fxsave W:mem" , "op": "0F AE /0" , "io": "C0=R C1=R C2=R C3=R"}, - {"inst": "fxsave64 W:mem" , "op": "REX.W 0F AE /0" , "io": "C0=R C1=R C2=R C3=R"} - ]}, - - {"category": "GP GP_EXT", "ext": "LAHFSAHF", "data": [ - {"inst": "lahf w:" , "op": "9F" , "io": "SF=R ZF=R AF=R PF=R CF=R"}, - {"inst": "sahf R:" , "op": "9E" , "io": "SF=W ZF=W AF=W PF=W CF=W"} - ]}, - - {"category": "GP GP_EXT", "ext": "LWP", "volatile": true, "data": [ - {"inst": "llwpcb R:r32" , "op": "XOP.L0.P0.M09.W0 12 /0"}, - {"inst": "llwpcb R:r64" , "op": "XOP.L0.P0.M09.W1 12 /0"}, - {"inst": "lwpins R:r32, R:r32/m32, id/ud" , "op": "VM: XOP.L0.P0.M0A.W0 12 /0 id"}, - {"inst": "lwpins R:r64, R:r32/m32, id/ud" , "op": "VM: XOP.L0.P0.M0A.W1 12 /0 id"}, - {"inst": "lwpval R:r32, R:r32/m32, id/ud" , "op": "VM: XOP.L0.P0.M0A.W0 12 /1 id"}, - {"inst": "lwpval R:r64, R:r32/m32, id/ud" , "op": "VM: XOP.L0.P0.M0A.W1 12 /1 id"}, - {"inst": "slwpcb W:r32" , "op": "XOP.L0.P0.M09.W0 12 /1"}, - {"inst": "slwpcb W:r64" , "op": "XOP.L0.P0.M09.W1 12 /1"} + {"category": "GP", "instructions": [ + {"any": "adc x:al, imm8" , "alt": true, "op": "[OP] 14 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "adc x:axv, immv" , "alt": true, "op": "[OP] 15 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "[lock|xacqrel] adc x:~r8/m8, ~r8" , "op": "[MR] 10 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "[lock|xacqrel] adc x:~rv/mv, ~rv" , "op": "[MR] 11 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "[lock|xacqrel] adc x:r8/m8, imm8" , "op": "[M ] 80 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "[lock|xacqrel] adc x:rv/mv, imms8" , "op": "[M ] 83 /2 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "[lock|xacqrel] adc x:rv/mv, immv" , "op": "[M ] 81 /2 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "adc x:~r8, ~r8/m8" , "op": "[RM] 12 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "adc x:~rv, ~rv/mv" , "op": "[RM] 13 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "add x:al, imm8" , "alt": true, "op": "[OP] 04 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "add x:axv, immv" , "alt": true, "op": "[OP] 05 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] add x:~r8/m8, ~r8" , "op": "[MR] 00 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] add x:~rv/mv, ~rv" , "op": "[MR] 01 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] add x:r8/m8, imm8" , "op": "[M ] 80 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] add x:rv/mv, imms8" , "op": "[M ] 83 /0 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] add x:rv/mv, immv" , "op": "[M ] 81 /0 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "add x:~r8, ~r8/m8" , "op": "[RM] 02 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "add x:~rv, ~rv/mv" , "op": "[RM] 03 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "and x:al, imm8" , "alt": true, "op": "[OP] 24 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "and x:ax, imm16" , "alt": true, "op": "[OP] 66 25 iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "and X:eax, imm32" , "alt": true, "op": "[OP] 25 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "and X:rax, immu32" , "alt": true, "op": "[OP] 25 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "and X:rax, imms32" , "alt": true, "op": "[OP] REX.W 25 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] and x:r8/m8, imm8" , "op": "[M ] 80 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] and x:r16/m16, imm16" , "op": "[M ] 66 81 /4 iw" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] and X:r32/m32, imm32" , "op": "[M ] 81 /4 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] and X:r64, immu32" , "op": "[M ] 81 /4 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] and X:r64/m64, imms32" , "op": "[M ] REX.W 81 /4 id" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] and x:rv/mv, imms8" , "op": "[M ] 83 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] and x:~r8/m8, ~r8" , "op": "[MR] 20 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] and x:~rv/mv, ~rv" , "op": "[MR] 21 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "and x:~r8, ~r8/m8" , "op": "[RM] 22 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "and x:~rv, ~rv/mv" , "op": "[RM] 23 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "bsf w:rv, rv/mv" , "op": "[RM] 0F BC /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=U"}, + {"any": "bsr w:rv, rv/mv" , "op": "[RM] 0F BD /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=U"}, + {"any": "bswap X:rv" , "op": "[OP] 0F C8+r"}, + {"any": "bt R:rv/mv, rv" , "op": "[MR] 0F A3 /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, + {"any": "bt R:rv/mv, imm8" , "op": "[M ] 0F BA /4 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, + {"any": "[lock|xacqrel] btc x:rv/mv, rv" , "op": "[MR] 0F BB /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, + {"any": "[lock|xacqrel] btc x:rv/mv, imm8" , "op": "[M ] 0F BA /7 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, + {"any": "[lock|xacqrel] btr x:rv/mv, rv" , "op": "[MR] 0F B3 /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, + {"any": "[lock|xacqrel] btr x:rv/mv, imm8" , "op": "[M ] 0F BA /6 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, + {"any": "[lock|xacqrel] bts x:rv/mv, rv" , "op": "[MR] 0F AB /r" , "io": "OF=U SF=U AF=U PF=U CF=W"}, + {"any": "[lock|xacqrel] bts x:rv/mv, imm8" , "op": "[M ] 0F BA /5 ib" , "io": "OF=U SF=U AF=U PF=U CF=W"}, + {"x86": "[bnd|repIgnore] call rel16" , "op": "[OP] 66 E8 cw" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "[bnd|repIgnore] call rel32" , "op": "[OP] E8 cd" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"x86": "[bnd|repIgnore] call R:r16/m16" , "op": "[OP] 66 FF /2" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"x86": "[bnd|repIgnore] call R:r32/m32" , "op": "[OP] FF /2" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"x64": "[bnd|repIgnore] call R:r64/m64" , "op": "[OP] FF /2" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "cbw x:" , "op": "[OP] 66 98"}, + {"any": "cdq W:, " , "op": "[OP] 99"}, + {"any": "cdqe X:" , "op": "[OP] REX.W 98"}, + {"any": "clc" , "op": "[OP] F8" , "io": "CF=0"}, + {"any": "cld" , "op": "[OP] FC" , "io": "DF=0"}, + {"any": "cmc" , "op": "[OP] F5" , "io": "CF=X"}, + {"any": "cmp R:r8/m8, r8" , "op": "[MR] 38 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "cmp R:rv/mv, rv" , "op": "[MR] 39 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "cmp R:r8, r8/m8" , "op": "[RM] 3A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "cmp R:rv, rv/mv" , "op": "[RM] 3B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "cmp R:al, imm8" , "alt": true, "op": "[OP] 3C ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "cmp R:axv, immv" , "alt": true, "op": "[OP] 3D iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "cmp R:r8/m8, imm8" , "op": "[M ] 80 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "cmp R:rv/mv, imms8" , "op": "[M ] 83 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "cmp R:rv/mv, immv" , "op": "[M ] 81 /7 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[rep|repne] cmps R:m8(ds:zsi), R:m8(es:zdi)" , "op": "[OP] A6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, + {"any": "[rep|repne] cmps R:m16(ds:zsi), R:m16(es:zdi)" , "op": "[OP] 66 A7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, + {"any": "[rep|repne] cmps R:m32(ds:zsi), R:m32(es:zdi)" , "op": "[OP] A7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, + {"any": "[rep|repne] cmps R:m64(ds:zsi), R:m64(es:zdi)" , "op": "[OP] REX.W A7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, + {"any": "cwde X:" , "op": "[OP] 98"}, + {"any": "cqo W:, " , "op": "[OP] REX.W 99"}, + {"any": "cwd w:, " , "op": "[OP] 66 99"}, + {"x86": "dec x:r16" , "op": "[OP] 66 48+r" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"x86": "dec X:r32" , "op": "[OP] 48+r" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "[lock|xacqrel] dec x:r8/m8" , "op": "[OP] FE /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "[lock|xacqrel] dec x:rv/mv" , "op": "[OP] FF /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "div x:, R:r8/m8" , "op": "[M ] F6 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "div x:, x:, rv/mv" , "op": "[M ] F7 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "enter imm16, imm8" , "op": "[OP] C8 iw ib" , "volatile": true}, + {"any": "idiv x:, R:r8/m8" , "op": "[M ] F6 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "idiv x:, x:, rv/mv" , "op": "[M ] F7 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "imul x:, R:r8/m8" , "op": "[M ] F6 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"any": "imul w:, x:, rv/mv" , "op": "[M ] F7 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"any": "imul x:~rv, ~rv/mv" , "op": "[RM] 0F AF /r" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"any": "imul w:rv, R:rv/mv, imms8" , "op": "[RM] 6B /r ib" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"any": "imul w:rv, R:rv/mv, immv" , "op": "[RM] 69 /r iv" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"x86": "inc x:r16" , "op": "[OP] 66 40+r" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"x86": "inc X:r32" , "op": "[OP] 40+r" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "[lock] inc x:r8/m8" , "op": "[M ] FE /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "[lock] inc x:rv/mv" , "op": "[M ] FF /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "iret" , "op": "[OP] 66 CF" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "iretd" , "op": "[OP] CF" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "iretq" , "op": "[OP] REX.W CF" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "[bnd] jb rel8" , "op": "[OP] 72 cb" , "io": "CF=R"}, + {"x86": "[bnd] jb rel16" , "op": "[OP] 66 0F 82 cw" , "io": "CF=R"}, + {"any": "[bnd] jb rel32" , "op": "[OP] 0F 82 cd" , "io": "CF=R"}, + {"any": "[bnd] jbe rel8" , "op": "[OP] 76 cb" , "io": "CF=R ZF=R"}, + {"x86": "[bnd] jbe rel16" , "op": "[OP] 66 0F 86 cw" , "io": "CF=R ZF=R"}, + {"any": "[bnd] jbe rel32" , "op": "[OP] 0F 86 cd" , "io": "CF=R ZF=R"}, + {"any": "[bnd] jl rel8" , "op": "[OP] 7C cb" , "io": "SF=R OF=R"}, + {"x86": "[bnd] jl rel16" , "op": "[OP] 66 0F 8C cw" , "io": "SF=R OF=R"}, + {"any": "[bnd] jl rel32" , "op": "[OP] 0F 8C cd" , "io": "SF=R OF=R"}, + {"any": "[bnd] jle rel8" , "op": "[OP] 7E cb" , "io": "ZF=R SF=R OF=R"}, + {"x86": "[bnd] jle rel16" , "op": "[OP] 66 0F 8E cw" , "io": "ZF=R SF=R OF=R"}, + {"any": "[bnd] jle rel32" , "op": "[OP] 0F 8E cd" , "io": "ZF=R SF=R OF=R"}, + {"any": "[bnd] jnb rel8" , "op": "[OP] 73 cb" , "io": "CF=R"}, + {"x86": "[bnd] jnb rel16" , "op": "[OP] 66 0F 83 cw" , "io": "CF=R"}, + {"any": "[bnd] jnb rel32" , "op": "[OP] 0F 83 cd" , "io": "CF=R"}, + {"any": "[bnd] jnbe rel8" , "op": "[OP] 77 cb" , "io": "CF=R ZF=R"}, + {"x86": "[bnd] jnbe rel16" , "op": "[OP] 66 0F 87 cw" , "io": "CF=R ZF=R"}, + {"any": "[bnd] jnbe rel32" , "op": "[OP] 0F 87 cd" , "io": "CF=R ZF=R"}, + {"any": "[bnd] jnl rel8" , "op": "[OP] 7D cb" , "io": "SF=R OF=R"}, + {"x86": "[bnd] jnl rel16" , "op": "[OP] 66 0F 8D cw" , "io": "SF=R OF=R"}, + {"any": "[bnd] jnl rel32" , "op": "[OP] 0F 8D cd" , "io": "SF=R OF=R"}, + {"any": "[bnd] jnle rel8" , "op": "[OP] 7F cb" , "io": "ZF=R SF=R OF=R"}, + {"x86": "[bnd] jnle rel16" , "op": "[OP] 66 0F 8F cw" , "io": "ZF=R SF=R OF=R"}, + {"any": "[bnd] jnle rel32" , "op": "[OP] 0F 8F cd" , "io": "ZF=R SF=R OF=R"}, + {"any": "[bnd] jno rel8" , "op": "[OP] 71 cb" , "io": "OF=R"}, + {"x86": "[bnd] jno rel16" , "op": "[OP] 66 0F 81 cw" , "io": "OF=R"}, + {"any": "[bnd] jno rel32" , "op": "[OP] 0F 81 cd" , "io": "OF=R"}, + {"any": "[bnd] jnp rel8" , "op": "[OP] 7B cb" , "io": "PF=R"}, + {"x86": "[bnd] jnp rel16" , "op": "[OP] 66 0F 8B cw" , "io": "PF=R"}, + {"any": "[bnd] jnp rel32" , "op": "[OP] 0F 8B cd" , "io": "PF=R"}, + {"any": "[bnd] jns rel8" , "op": "[OP] 79 cb" , "io": "SF=R"}, + {"x86": "[bnd] jns rel16" , "op": "[OP] 66 0F 89 cw" , "io": "SF=R"}, + {"any": "[bnd] jns rel32" , "op": "[OP] 0F 89 cd" , "io": "SF=R"}, + {"any": "[bnd] jnz rel8" , "op": "[OP] 75 cb" , "io": "ZF=R"}, + {"x86": "[bnd] jnz rel16" , "op": "[OP] 66 0F 85 cw" , "io": "ZF=R"}, + {"any": "[bnd] jnz rel32" , "op": "[OP] 0F 85 cd" , "io": "ZF=R"}, + {"any": "[bnd] jo rel8" , "op": "[OP] 70 cb" , "io": "OF=R"}, + {"x86": "[bnd] jo rel16" , "op": "[OP] 66 0F 80 cw" , "io": "OF=R"}, + {"any": "[bnd] jo rel32" , "op": "[OP] 0F 80 cd" , "io": "OF=R"}, + {"any": "[bnd] jp rel8" , "op": "[OP] 7A cb" , "io": "PF=R"}, + {"x86": "[bnd] jp rel16" , "op": "[OP] 66 0F 8A cw" , "io": "PF=R"}, + {"any": "[bnd] jp rel32" , "op": "[OP] 0F 8A cd" , "io": "PF=R"}, + {"any": "[bnd] js rel8" , "op": "[OP] 78 cb" , "io": "SF=R"}, + {"x86": "[bnd] js rel16" , "op": "[OP] 66 0F 88 cw" , "io": "SF=R"}, + {"any": "[bnd] js rel32" , "op": "[OP] 0F 88 cd" , "io": "SF=R"}, + {"any": "[bnd] jz rel8" , "op": "[OP] 74 cb" , "io": "ZF=R"}, + {"x86": "[bnd] jz rel16" , "op": "[OP] 66 0F 84 cw" , "io": "ZF=R"}, + {"any": "[bnd] jz rel32" , "op": "[OP] 0F 84 cd" , "io": "ZF=R"}, + {"x86": "[bnd] jecxz R:, rel8" , "op": "[OP] 67 E3 cb"}, + {"x86": "[bnd] jecxz R:, rel8" , "op": "[OP] E3 cb"}, + {"x64": "[bnd] jecxz R:, rel8" , "op": "[OP] 67 E3 cb"}, + {"x64": "[bnd] jecxz R:, rel8" , "op": "[OP] E3 cb"}, + {"any": "[bnd] jmp rel8" , "op": "[OP] EB cb"}, + {"x86": "[bnd] jmp rel16" , "op": "[OP] 66 E9 cw"}, + {"any": "[bnd] jmp rel32" , "op": "[OP] E9 cd"}, + {"x86": "[bnd] jmp R:r32/m32" , "op": "[M ] FF /4"}, + {"x64": "[bnd] jmp R:r64/m64" , "op": "[M ] FF /4"}, + {"x86": "lcall imm16, imm16" , "op": "[OP] 66 9A iw iw" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"x86": "lcall imm16, imm32" , "op": "[OP] 9A id iw" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "lcall R:m16_16" , "op": "[M ] 66 FF /3" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "lcall R:m16_32" , "op": "[M ] FF /3" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"x64": "lcall R:m16_64" , "op": "[M ] REX.W FF /3" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "lea w:r16, mem" , "op": "[RM] 67 8D /r"}, + {"any": "lea W:r32, mem" , "op": "[RM] 8D /r"}, + {"any": "lea W:r64, mem" , "op": "[RM] REX.W 8D /r"}, + {"any": "leave" , "op": "[OP]C9" , "volatile": true}, + {"x86": "ljmp imm16, imm16" , "op": "[OP] 66 EA iw iw"}, + {"x86": "ljmp imm16, imm32" , "op": "[OP] EA id iw"}, + {"any": "ljmp R:m16_16" , "op": "[M ] 66 FF /5"}, + {"any": "ljmp R:m16_32" , "op": "[M ] FF /5"}, + {"any": "ljmp R:m16_64" , "op": "[M ] REX.W FF /5"}, + {"any": "[rep] lods w:al, R:m8(ds:zsi)" , "op": "[OP] AC" , "io": "DF=R"}, + {"any": "[rep] lods w:ax, R:m16(ds:zsi)" , "op": "[OP] 66 AD" , "io": "DF=R"}, + {"any": "[rep] lods W:eax, R:m32(ds:zsi)" , "op": "[OP] AD" , "io": "DF=R"}, + {"any": "[rep] lods W:rax, R:m64(ds:zsi)" , "op": "[OP] REX.W AD" , "io": "DF=R"}, + {"x86": "loop x:, rel8" , "op": "[OP] 67 E2 cb"}, + {"x86": "loop X:, rel8" , "op": "[OP] E2 cb"}, + {"x64": "loop X:, rel8" , "op": "[OP] 67 E2 cb"}, + {"x64": "loop X:, rel8" , "op": "[OP] E2 cb"}, + {"x86": "loope x:, rel8" , "op": "[OP] 67 E1 cb" , "io": "ZF=R"}, + {"x86": "loope X:, rel8" , "op": "[OP] E1 cb" , "io": "ZF=R"}, + {"x64": "loope X:, rel8" , "op": "[OP] 67 E1 cb" , "io": "ZF=R"}, + {"x64": "loope X:, rel8" , "op": "[OP] E1 cb" , "io": "ZF=R"}, + {"x86": "loopne x:, rel8" , "op": "[OP] 67 E0 cb" , "io": "ZF=R"}, + {"x86": "loopne X:, rel8" , "op": "[OP] E0 cb" , "io": "ZF=R"}, + {"x64": "loopne X:, rel8" , "op": "[OP] 67 E0 cb" , "io": "ZF=R"}, + {"x64": "loopne X:, rel8" , "op": "[OP] E0 cb" , "io": "ZF=R"}, + {"any": "[xrelease] mov w:r8/m8, r8" , "op": "[MR] 88 /r"}, + {"any": "[xrelease] mov w:rv/mv, rv" , "op": "[MR] 89 /r"}, + {"any": "[xrelease] mov w:r8/m8, imm8" , "op": "[M ] C6 /0 ib"}, + {"any": "[xrelease] mov w:rv/mv, immv" , "op": "[M ] C7 /0 iv"}, + {"any": "mov w:r8, r8/m8" , "op": "[RM] 8A /r"}, + {"any": "mov w:rv, rv/mv" , "op": "[RM] 8B /r"}, + {"any": "mov w:r8, imm8" , "op": "[OP] B0+r ib"}, + {"any": "mov w:r16, imm16" , "op": "[OP] 66 B8+r iw"}, + {"any": "mov W:r32, imm32" , "op": "[OP] B8+r id"}, + {"any": "mov W:r64, imm64" , "op": "[OP] REX.W B8+r iq"}, + {"any": "mov w:r16/m16, sreg" , "op": "[MR] 66 8C /r"}, + {"any": "mov W:r32/m16, sreg" , "op": "[MR] 8C /r"}, + {"any": "mov W:r64/m16, sreg" , "op": "[MR] REX.W 8C /r"}, + {"any": "mov W:sreg, r16/m16" , "op": "[RM] 66 8E /r"}, + {"any": "mov W:sreg, r32/m16" , "op": "[RM] 8E /r"}, + {"any": "mov W:sreg, r64/m16" , "op": "[RM] REX.W 8E /r"}, + {"any": "mov w:al, moff8" , "op": "[OP] A0 moff"}, + {"any": "mov w:ax, moff16" , "op": "[OP] 66 A1 moff"}, + {"any": "mov W:eax, moff32" , "op": "[OP] A1 moff"}, + {"any": "mov W:rax, moff64" , "op": "[OP] REX.W A1 moff"}, + {"any": "mov W:moff8, al" , "op": "[OP] A2 moff"}, + {"any": "mov W:moff16, ax" , "op": "[OP] 66 A3 moff"}, + {"any": "mov W:moff32, eax" , "op": "[OP] A3 moff"}, + {"any": "mov W:moff64, rax" , "op": "[OP] REX.W A3 moff"}, + {"x86": "mov W:r32, creg" , "op": "[MR] 0F 20 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, + {"x64": "mov W:r64, creg" , "op": "[MR] 0F 20 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, + {"x86": "mov W:creg, r32" , "op": "[RM] 0F 22 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, + {"x64": "mov W:creg, r64" , "op": "[RM] 0F 22 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, + {"x86": "mov W:r32, dreg" , "op": "[MR] 0F 21 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, + {"x64": "mov W:r64, dreg" , "op": "[MR] 0F 21 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, + {"x86": "mov W:dreg, r32" , "op": "[RM] 0F 23 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, + {"x64": "mov W:dreg, r64" , "op": "[RM] 0F 23 /r" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U", "privilege": "L0"}, + {"any": "movabs W:r64, imm64" , "op": "[OP] REX.W B8+r iq"}, + {"any": "movabs w:al, moff8" , "op": "[OP] A0 moff"}, + {"any": "movabs w:ax, moff16" , "op": "[OP] 66 A1 moff"}, + {"any": "movabs W:eax, moff32" , "op": "[OP] A1 moff"}, + {"any": "movabs W:rax, moff64" , "op": "[OP] REX.W A1 moff"}, + {"any": "movabs W:moff8, al" , "op": "[OP] A2 moff"}, + {"any": "movabs W:moff16, ax" , "op": "[OP] 66 A3 moff"}, + {"any": "movabs W:moff32, eax" , "op": "[OP] A3 moff"}, + {"any": "movabs W:moff64, rax" , "op": "[OP] REX.W A3 moff"}, + {"any": "[rep] movs W:m8(es:zdi), R:m8(ds:zsi)" , "op": "[OP] A4" , "io": "DF=R"}, + {"any": "[rep] movs W:m16(es:zdi), R:m16(ds:zsi)" , "op": "[OP] 66 A5" , "io": "DF=R"}, + {"any": "[rep] movs W:m32(es:zdi), R:m32(ds:zsi)" , "op": "[OP] A5" , "io": "DF=R"}, + {"any": "[rep] movs W:m64(es:zdi), R:m64(ds:zsi)" , "op": "[OP] REX.W A5" , "io": "DF=R"}, + {"any": "movsx w:rv, r8/m8" , "op": "[RM] 0F BE /r"}, + {"any": "movsx W:ry, r16/m16" , "op": "[RM] 0F BF /r"}, + {"x64": "movsxd W:r16, r16/m16" , "op": "[RM] 66 63 /r"}, + {"x64": "movsxd W:r32, r32/m32" , "op": "[RM] 63 /r"}, + {"x64": "movsxd W:r64, r32/m32" , "op": "[RM] REX.W 63 /r"}, + {"any": "movzx w:rv, r8/m8" , "op": "[RM] 0F B6 /r"}, + {"any": "movzx W:r32, r16/m16" , "op": "[RM] 0F B7 /r"}, + {"any": "movzx W:r64, r16/m16" , "op": "[RM] REX.W 0F B7 /r"}, + {"any": "mul x:, r8/m8" , "op": "[M ] F6 /4" , "io": "OF=W SF=U ZF=U AF=U PF=U CF=W"}, + {"any": "mul w:, x:, rv/mv" , "op": "[M ] F7 /4" , "io": "OF=W SF=U ZF=U AF=U PF=U CF=W"}, + {"any": "[lock|xacqrel] neg x:r8/m8" , "op": "[M ] F6 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] neg x:rv/mv" , "op": "[M ] F7 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "nop" , "op": "[OP] 90"}, + {"any": "nop R:rv/mv" , "op": "[M ] 0F 1F /0"}, + {"any": "nop R:rv/mv, rv" , "op": "[MR] 0F 1F /r"}, + {"any": "[lock|xacqrel] not x:r8/m8" , "op": "[M ] F6 /2"}, + {"any": "[lock|xacqrel] not x:rv/mv" , "op": "[M ] F7 /2"}, + {"any": "or x:al, imm8" , "alt": true, "op": "[OP] 0C ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "or x:axv, immv" , "alt": true, "op": "[OP] 0D iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] or x:~r8/m8, ~r8" , "op": "[MR] 08 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] or x:~rv/mv, ~rv" , "op": "[MR] 09 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] or x:r8/m8, imm8" , "op": "[M ] 80 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] or x:rv/mv, immv" , "op": "[M ] 81 /1 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] or x:rv/mv, imms8" , "op": "[M ] 83 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "or x:~r8, ~r8/m8" , "op": "[RM] 0A /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "or x:~rv, ~rv/mv" , "op": "[RM] 0B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "pop w:r16/m16" , "op": "[M ] 66 8F /0"}, + {"x86": "pop W:r32/m32" , "op": "[M ] 8F /0"}, + {"x64": "pop W:r64/m64" , "op": "[M ] 8F /0"}, + {"any": "pop w:r16" , "op": "[OP] 66 58+r"}, + {"x86": "pop W:r32" , "op": "[OP] 58+r"}, + {"x64": "pop W:r64" , "op": "[OP] 58+r"}, + {"x86": "pop W:ds" , "op": "[OP] 1F"}, + {"x86": "pop W:es" , "op": "[OP] 07"}, + {"x86": "pop W:ss" , "op": "[OP] 17"}, + {"any": "pop W:fs" , "op": "[OP] 0F A1"}, + {"any": "pop W:gs" , "op": "[OP] 0F A9"}, + {"any": "popf" , "op": "[OP] 66 9D" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=W IF=W TF=W"}, + {"x86": "popfd" , "op": "[OP] 9D" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=W IF=W TF=W"}, + {"x64": "popfq" , "op": "[OP] 9D" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=W IF=W TF=W"}, + {"any": "push R:r16/m16" , "op": "[M ] 66 FF /6"}, + {"x86": "push R:r32/m32" , "op": "[M ] FF /6"}, + {"x64": "push R:r64/m64" , "op": "[M ] FF /6"}, + {"any": "push R:r16" , "op": "[OP] 66 50+r"}, + {"x86": "push R:r32" , "op": "[OP] 50+r"}, + {"x64": "push R:r64" , "op": "[OP] 50+r"}, + {"x86": "push R:cs" , "op": "[OP] 0E"}, + {"x86": "push R:ss" , "op": "[OP] 16"}, + {"x86": "push R:ds" , "op": "[OP] 1E"}, + {"x86": "push R:es" , "op": "[OP] 06"}, + {"any": "push R:fs" , "op": "[OP] 0F A0"}, + {"any": "push R:gs" , "op": "[OP] 0F A8"}, + {"any": "push imm8" , "op": "[OP] 6A ib"}, + {"any": "push imm16" , "op": "[OP] 66 68 iw"}, + {"x86": "push imm32" , "op": "[OP] 68 id"}, + {"x64": "push imms32" , "op": "[OP] 68 id"}, + {"any": "pushf" , "op": "[OP] 66 9C" , "io": "OF=R SF=R ZF=R AF=R PF=R CF=R DF=R IF=R TF=R"}, + {"x86": "pushfd" , "op": "[OP] 9C" , "io": "OF=R SF=R ZF=R AF=R PF=R CF=R DF=R IF=R TF=R"}, + {"x64": "pushfq" , "op": "[OP] 9C" , "io": "OF=R SF=R ZF=R AF=R PF=R CF=R DF=R IF=R TF=R"}, + {"any": "pushw imm16" , "op": "[OP] 66 68 iw"}, + {"any": "rcl x:r8/m8, cl" , "op": "[M ] D2 /2" , "io": "CF=X OF=X"}, + {"any": "rcl x:rv/mv, cl" , "op": "[M ] D3 /2" , "io": "CF=X OF=X"}, + {"any": "rcl x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /2" , "io": "CF=X OF=X"}, + {"any": "rcl x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /2" , "io": "CF=X OF=X"}, + {"any": "rcl x:r8/m8, imm8" , "op": "[M ] C0 /2 ib" , "io": "CF=X OF=X"}, + {"any": "rcl x:rv/mv, imm8" , "op": "[M ] C1 /2 ib" , "io": "CF=X OF=X"}, + {"any": "rcr x:r8/m8, cl" , "op": "[M ] D2 /3" , "io": "CF=X OF=X"}, + {"any": "rcr x:rv/mv, cl" , "op": "[M ] D3 /3" , "io": "CF=X OF=X"}, + {"any": "rcr x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /3" , "io": "CF=X OF=X"}, + {"any": "rcr x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /3" , "io": "CF=X OF=X"}, + {"any": "rcr x:r8/m8, imm8" , "op": "[M ] C0 /3 ib" , "io": "CF=X OF=X"}, + {"any": "rcr x:rv/mv, imm8" , "op": "[M ] C1 /3 ib" , "io": "CF=X OF=X"}, + {"any": "[bnd|repIgnore] ret" , "op": "[OP] C3"}, + {"any": "[bnd|repIgnore] ret immu16" , "op": "[OP] C2 iw"}, + {"any": "retf" , "op": "[OP] CB"}, + {"any": "retf immu16" , "op": "[OP] CA iw"}, + {"any": "rol x:r8/m8, cl" , "op": "[M ] D2 /0" , "io": "CF=W OF=W"}, + {"any": "rol x:rv/mv, cl" , "op": "[M ] D3 /0" , "io": "CF=W OF=W"}, + {"any": "rol x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /0" , "io": "CF=W OF=W"}, + {"any": "rol x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /0" , "io": "CF=W OF=W"}, + {"any": "rol x:r8/m8, imm8" , "op": "[M ] C0 /0 ib" , "io": "CF=W OF=W"}, + {"any": "rol x:rv/mv, imm8" , "op": "[M ] C1 /0 ib" , "io": "CF=W OF=W"}, + {"any": "ror x:r8/m8, cl" , "op": "[M ] D2 /1" , "io": "CF=W OF=W"}, + {"any": "ror x:rv/mv, cl" , "op": "[M ] D3 /1" , "io": "CF=W OF=W"}, + {"any": "ror x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /1" , "io": "CF=W OF=W"}, + {"any": "ror x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /1" , "io": "CF=W OF=W"}, + {"any": "ror x:r8/m8, imm8" , "op": "[M ] C0 /1 ib" , "io": "CF=W OF=W"}, + {"any": "ror x:rv/mv, imm8" , "op": "[M ] C1 /1 ib" , "io": "CF=W OF=W"}, + {"any": "sar x:r8/m8, cl" , "op": "[M ] D2 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "sar x:rv/mv, cl" , "op": "[M ] D3 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "sar x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "sar x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "sar x:r8/m8, imm8" , "op": "[M ] C0 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "sar x:rv/mv, imm8" , "op": "[M ] C1 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "sbb x:al, imm8" , "alt": true, "op": "[OP] 1C ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "sbb x:axv, immv" , "alt": true, "op": "[OP] 1D iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "[lock|xacqrel] sbb x:r8/m8, r8" , "op": "[MR] 18 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "[lock|xacqrel] sbb x:rv/mv, rv" , "op": "[MR] 19 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "[lock|xacqrel] sbb x:r8/m8, imm8" , "op": "[M ] 80 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "[lock|xacqrel] sbb x:rv/mv, imms8" , "op": "[M ] 83 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "[lock|xacqrel] sbb x:rv/mv, immv" , "op": "[M ] 81 /3 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "sbb x:r8, r8/m8" , "op": "[RM] 1A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "sbb x:rv, rv/mv" , "op": "[RM] 1B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"any": "[rep|repne] scas R:al, R:m8(es:zdi)" , "op": "[OP] AE" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, + {"any": "[rep|repne] scas R:ax, R:m16(es:zdi)" , "op": "[OP] 66 AF" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, + {"any": "[rep|repne] scas R:eax, R:m32(es:zdi)" , "op": "[OP] AF" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, + {"any": "[rep|repne] scas R:rax, R:m64(es:zdi)" , "op": "[OP] REX.W AF" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W DF=R"}, + {"any": "setb w:r8/m8" , "op": "[M ] 0F 92 /r" , "io": "CF=R"}, + {"any": "setbe w:r8/m8" , "op": "[M ] 0F 96 /r" , "io": "CF=R ZF=R"}, + {"any": "setl w:r8/m8" , "op": "[M ] 0F 9C /r" , "io": "SF=R OF=R"}, + {"any": "setle w:r8/m8" , "op": "[M ] 0F 9E /r" , "io": "ZF=R SF=R OF=R"}, + {"any": "setnb w:r8/m8" , "op": "[M ] 0F 93 /r" , "io": "CF=R"}, + {"any": "setnbe w:r8/m8" , "op": "[M ] 0F 97 /r" , "io": "CF=R ZF=R"}, + {"any": "setnl w:r8/m8" , "op": "[M ] 0F 9D /r" , "io": "SF=R OF=R"}, + {"any": "setnle w:r8/m8" , "op": "[M ] 0F 9F /r" , "io": "ZF=R SF=R OF=R"}, + {"any": "setno w:r8/m8" , "op": "[M ] 0F 91 /r" , "io": "OF=R"}, + {"any": "setnp w:r8/m8" , "op": "[M ] 0F 9B /r" , "io": "PF=R"}, + {"any": "setns w:r8/m8" , "op": "[M ] 0F 99 /r" , "io": "SF=R"}, + {"any": "setnz w:r8/m8" , "op": "[M ] 0F 95 /r" , "io": "ZF=R"}, + {"any": "seto w:r8/m8" , "op": "[M ] 0F 90 /r" , "io": "OF=R"}, + {"any": "setp w:r8/m8" , "op": "[M ] 0F 9A /r" , "io": "PF=R"}, + {"any": "sets w:r8/m8" , "op": "[M ] 0F 98 /r" , "io": "SF=R"}, + {"any": "setz w:r8/m8" , "op": "[M ] 0F 94 /r" , "io": "ZF=R"}, + {"any": "shl x:r8/m8, cl" , "op": "[M ] D2 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shl x:rv/mv, cl" , "op": "[M ] D3 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shl x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shl x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shl x:r8/m8, imm8" , "op": "[M ] C0 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shl x:rv/mv, imm8" , "op": "[M ] C1 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shld x:rv/mv, rv, cl" , "op": "[MR] 0F A5 /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"any": "shld x:rv/mv, rv, imm8" , "op": "[MR] 0F A4 /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"any": "shr x:r8/m8, cl" , "op": "[M ] D2 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shr x:rv/mv, cl" , "op": "[M ] D3 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shr x:r8/m8, 1" , "alt": true, "op": "[M ] D0 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shr x:rv/mv, 1" , "alt": true, "op": "[M ] D1 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shr x:r8/m8, imm8" , "op": "[M ] C0 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shr x:rv/mv, imm8" , "op": "[M ] C1 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "shrd x:rv/mv, rv, cl" , "op": "[MR] 0F AD /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"any": "shrd x:rv/mv, rv, imm8" , "op": "[MR] 66 0F AC /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"any": "stc" , "op": "[OP] F9" , "io": "CF=1"}, + {"any": "std" , "op": "[OP] FD" , "io": "DF=1"}, + {"any": "[rep] stos W:m8(es:zdi), R:al" , "op": "[OP] AA" , "io": "DF=R"}, + {"any": "[rep] stos W:m16(es:zdi), R:ax" , "op": "[OP] 66 AB" , "io": "DF=R"}, + {"any": "[rep] stos W:m32(es:zdi), R:eax" , "op": "[OP] AB" , "io": "DF=R"}, + {"any": "[rep] stos W:m64(es:zdi), R:rax" , "op": "[OP] REX.W AB" , "io": "DF=R"}, + {"any": "sub x:al, imm8" , "alt": true, "op": "[OP] 2C ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "sub x:axv, immv" , "alt": true, "op": "[OP] 2D iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] sub x:r8/m8, r8" , "op": "[MR] 28 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] sub x:rv/mv, rv" , "op": "[MR] 29 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] sub x:r8/m8, imm8" , "op": "[M ] 80 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] sub x:rv/mv, imms8" , "op": "[M ] 83 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] sub x:rv/mv, immv" , "op": "[M ] 81 /5 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "sub x:r8, r8/m8" , "op": "[RM] 2A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "sub x:rv, rv/mv" , "op": "[RM] 2B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "test R:~r8/m8, ~r8" , "op": "[MR] 84 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "test R:~rv/mv, ~rv" , "op": "[MR] 85 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "test R:al, imm8" , "alt": true, "op": "[OP] A8 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "test R:axv, immv" , "alt": true, "op": "[OP] A9 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "test R:r8/m8, imm8" , "op": "[M ] F6 /0 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "test R:rv/mv, immv" , "op": "[M ] F7 /0 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "ud0 r32, r32/m32" , "op": "[RM] 0F FF /r"}, + {"any": "ud1 r32, r32/m32" , "op": "[RM] 0F B9 /r"}, + {"any": "ud2" , "op": "[OP] 0F 0B"}, + {"any": "xchg x:~ax, x:~r16" , "alt": true, "op": "[OP] 66 90+r"}, + {"any": "xchg X:~eax, X:~r32" , "alt": true, "op": "[OP] 90+r"}, + {"any": "xchg X:~rax, X:~r64" , "alt": true, "op": "[OP] REX.W 90+r"}, + {"any": "xchg x:~r16, x:~ax" , "alt": true, "op": "[OP] 66 90+r"}, + {"any": "xchg X:~r32, X:~eax" , "alt": true, "op": "[OP] 90+r"}, + {"any": "xchg X:~r64, X:~rax" , "alt": true, "op": "[OP] REX.W 90+r"}, + {"any": "[ilock|xacquire] xchg x:~r8/m8, x:~r8" , "op": "[MR] 86 /r"}, + {"any": "[ilock|xacquire] xchg x:~rv/mv, x:~rv" , "op": "[MR] 87 /r"}, + {"any": "[ilock|xacquire] xchg x:~r8, x:~r8/m8" , "op": "[RM] 86 /r"}, + {"any": "[ilock|xacquire] xchg x:~rv, x:~rv/mv" , "op": "[RM] 87 /r"}, + {"any": "xor x:al, imm8" , "alt": true, "op": "[OP] 34 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "xor x:axv, immv" , "alt": true, "op": "[OP] 35 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] xor x:~r8/m8, ~r8" , "op": "[MR] 30 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] xor x:~rv/mv, ~rv" , "op": "[MR] 31 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] xor x:r8/m8, imm8" , "op": "[M ] 80 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] xor x:rv/mv, imms8" , "op": "[M ] 83 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "[lock|xacqrel] xor x:rv/mv, immv" , "op": "[M ] 81 /6 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "xor x:~r8, ~r8/m8" , "op": "[RM] 32 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"any": "xor x:~rv, ~rv/mv" , "op": "[RM] 33 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"} + ]}, + + {"category": "GP GP_IN_OUT", "volatile": true, "instructions": [ + {"any": "in w:al, imm8" , "op": "E4 ib"}, + {"any": "in w:ax, imm8" , "op": "66 E5 ib"}, + {"any": "in W:eax, imm8" , "op": "E5 ib"}, + {"any": "in w:al, dx" , "op": "EC"}, + {"any": "in w:ax, dx" , "op": "66 ED"}, + {"any": "in W:eax, dx" , "op": "ED"}, + {"any": "[rep] ins W:m8(es:zdi), dx" , "op": "6C"}, + {"any": "[rep] ins W:m16(es:zdi), dx" , "op": "66 6D"}, + {"any": "[rep] ins W:m32(es:zdi), dx" , "op": "6D"}, + {"any": "out imm8, al" , "op": "E6 ib"}, + {"any": "out imm8, ax" , "op": "66 E7 ib"}, + {"any": "out imm8, eax" , "op": "E7 ib"}, + {"any": "out R:dx, R:al" , "op": "EE"}, + {"any": "out R:dx, R:ax" , "op": "66 EF"}, + {"any": "out R:dx, R:eax" , "op": "EF"}, + {"any": "[rep] outs R:dx, R:m8(ds:zsi)" , "op": "6E"}, + {"any": "[rep] outs R:dx, R:m16(ds:zsi)" , "op": "66 6F"}, + {"any": "[rep] outs R:dx, R:m32(ds:zsi)" , "op": "6F"} + ]}, + + {"category": "GP GP_EXT", "ext": "I486", "instructions": [ + {"any": "[lock|xacqrel] cmpxchg x:r8/m8, r8, " , "op": "[MR] 0F B0 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] cmpxchg x:rv/mv, rv, " , "op": "[MR] 0F B1 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "cpuid X:, W:, X:, W:" , "op": "[OP] 0F A2" , "volatile": true}, + {"any": "[lock|xacqrel] xadd x:r8/m8, x:r8" , "op": "[MR] 0F C0 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"any": "[lock|xacqrel] xadd x:rv/mv, x:rv" , "op": "[MR] 0F C1 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"} + ]}, + + {"category": "GP GP_EXT", "ext": "3DNOW", "volatile": true, "instructions": [ + {"any": "prefetch R:mem" , "op": "0F 0D /0"} + ]}, + + {"category": "GP GP_EXT", "ext": "ADX", "instructions": [ + {"any": "adcx X:~ry, R:~ry/my" , "op": "[RM] 66 0F 38 F6 /r" , "io": "CF=X"}, + {"any": "adox X:~ry, R:~ry/my" , "op": "[RM] F3 0F 38 F6 /r" , "io": "OF=X"} + ]}, + + {"category": "GP GP_EXT", "ext": "BMI", "instructions": [ + {"any": "andn W:ry, R:ry, R:ry/my" , "op": "[RVM] VEX.LZ.0F38.Wy F2 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=0"}, + {"any": "bextr W:ry, R:ry/my, R:ry" , "op": "[RMV] VEX.LZ.0F38.Wy F7 /r" , "io": "OF=0 SF=U ZF=W AF=U PF=U CF=0"}, + {"any": "blsi W:ry, R:ry/my" , "op": "[VM ] VEX.LZ.0F38.Wy F3 /3" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, + {"any": "blsmsk W:ry, R:ry/my" , "op": "[VM ] VEX.LZ.0F38.Wy F3 /2" , "io": "OF=0 SF=W ZF=0 AF=U PF=U CF=W"}, + {"any": "blsr W:ry, R:ry/my" , "op": "[VM ] VEX.LZ.0F38.Wy F3 /1" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, + {"any": "tzcnt w:rv, rv/mv" , "op": "[RM] F3 0F BC /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"} + ]}, + + {"category": "GP GP_EXT", "ext": "BMI2", "instructions": [ + {"any": "bzhi W:ry, R:ry/my, R:ry" , "op": "[RMV] VEX.LZ.0F38.Wy F5 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, + {"any": "mulx W:ry, W:ry, ~ry/my, ~" , "op": "[RVM] VEX.LZ.F2.0F38.Wy F6 /r"}, + {"any": "pdep W:ry, ry, ry/my" , "op": "[RVM] VEX.LZ.F2.0F38.Wy F5 /r"}, + {"any": "pext W:ry, ry, ry/my" , "op": "[RVM] VEX.LZ.F3.0F38.Wy F5 /r"}, + {"any": "rorx W:ry, ry/my, imm8" , "op": "[RM ] VEX.LZ.F2.0F3A.Wy F0 /r ib"}, + {"any": "sarx W:ry, ry/my, ry" , "op": "[RMV] VEX.LZ.F3.0F38.Wy F7 /r"}, + {"any": "shlx W:ry, ry/my, ry" , "op": "[RMV] VEX.LZ.66.0F38.Wy F7 /r"}, + {"any": "shrx W:ry, ry/my, ry" , "op": "[RMV] VEX.LZ.F2.0F38.Wy F7 /r"} + ]}, + + {"category": "GP GP_EXT", "ext": "CET_SS", "volatile": true, "instructions": [ + {"any": "incsspd R:r32[7:0]" , "op": "F3 0F AE /5"}, + {"x64": "incsspq R:r64[7:0]" , "op": "F3 REX.W 0F AE /5"}, + {"any": "rdsspd W:r32" , "op": "F3 0F 1E /1"}, + {"any": "rdsspq W:r64" , "op": "F3 REX.W 0F 1E /1"}, + {"any": "rstorssp R:m64" , "op": "F3 0F 01 /5" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}, + {"any": "saveprevssp" , "op": "F3 0F 01 EA" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"} + ]}, + + {"category": "GP GP_EXT", "ext": "CLDEMOTE", "instructions": [ + {"any": "cldemote R:mem" , "op": "[M ] NP 0F 1C /0"} + ]}, + + {"category": "GP GP_EXT", "ext": "CLFLUSH", "instructions": [ + {"any": "clflush R:mem" , "op": "[M ] NP 0F AE /7"} + ]}, + + {"category": "GP GP_EXT", "ext": "CLFLUSHOPT", "instructions": [ + {"any": "clflushopt R:mem" , "op": "[M ] NFx 66 0F AE /7"} + ]}, + + {"category": "GP GP_EXT", "ext": "CLWB", "instructions": [ + {"any": "clwb R:mem" , "op": "[M ] 66 0F AE /6"} ]}, - {"category": "GP GP_EXT", "ext": "LZCNT", "data": [ - {"inst": "lzcnt w:r16, r16/m16" , "op": "RM: 66 F3 0F BD /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"}, - {"inst": "lzcnt W:r32, r32/m32" , "op": "RM: F3 0F BD /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"}, - {"inst": "lzcnt W:r64, r64/m64" , "op": "RM: REX.W F3 0F BD /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"} + {"category": "GP GP_EXT", "ext": "CLZERO", "instructions": [ + {"any": "clzero R:" , "op": "[OP] NP 0F 01 FC"} ]}, - {"category": "GP GP_EXT", "ext": "MONITORX", "volatile": true, "data": [ - {"inst": "monitorx R:, R:, R:" , "op": "0F 01 FA"}, - {"inst": "mwaitx R:, R:, R:" , "op": "0F 01 FB"} + {"category": "GP GP_EXT", "ext": "CMOV", "instructions": [ + {"any": "cmovb x:rv, rv/mv" , "op": "[RM] 0F 42 /r" , "io": "CF=R"}, + {"any": "cmovbe x:rv, rv/mv" , "op": "[RM] 0F 46 /r" , "io": "CF=R ZF=R"}, + {"any": "cmovl x:rv, rv/mv" , "op": "[RM] 0F 4C /r" , "io": "SF=R OF=R"}, + {"any": "cmovle x:rv, rv/mv" , "op": "[RM] 0F 4E /r" , "io": "ZF=R SF=R OF=R"}, + {"any": "cmovnb x:rv, rv/mv" , "op": "[RM] 0F 43 /r" , "io": "CF=R"}, + {"any": "cmovnbe x:rv, rv/mv" , "op": "[RM] 0F 47 /r" , "io": "CF=R ZF=R"}, + {"any": "cmovnl x:rv, rv/mv" , "op": "[RM] 0F 4D /r" , "io": "SF=R OF=R"}, + {"any": "cmovnle x:rv, rv/mv" , "op": "[RM] 0F 4F /r" , "io": "ZF=R SF=R OF=R"}, + {"any": "cmovno x:rv, rv/mv" , "op": "[RM] 0F 41 /r" , "io": "OF=R"}, + {"any": "cmovnp x:rv, rv/mv" , "op": "[RM] 0F 4B /r" , "io": "PF=R"}, + {"any": "cmovns x:rv, rv/mv" , "op": "[RM] 0F 49 /r" , "io": "SF=R"}, + {"any": "cmovnz x:rv, rv/mv" , "op": "[RM] 0F 45 /r" , "io": "ZF=R"}, + {"any": "cmovo x:rv, rv/mv" , "op": "[RM] 0F 40 /r" , "io": "OF=R"}, + {"any": "cmovp x:rv, rv/mv" , "op": "[RM] 0F 4A /r" , "io": "PF=R"}, + {"any": "cmovs x:rv, rv/mv" , "op": "[RM] 0F 48 /r" , "io": "SF=R"}, + {"any": "cmovz x:rv, rv/mv" , "op": "[RM] 0F 44 /r" , "io": "ZF=R"} ]}, - {"category": "GP GP_EXT", "ext": "MCOMMIT", "data": [ - {"inst": "mcommit" , "op": "F3 0F 01 FA" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"} + {"category": "GP GP_EXT", "ext": "CMPCCXADD", "instructions": [ + {"any": "cmpbxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy E2 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpbexadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy E6 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmplxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy EC !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmplexadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy EE !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpnbxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy E3 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpnbexadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy E7 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpnlxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy ED !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpnlexadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy EF !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpnoxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy E1 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpnpxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy EB !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpnsxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy E9 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpnzxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy E5 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpoxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy E0 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmppxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy EA !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpsxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy E8 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "cmpzxadd X:my, X:ry, R:ry" , "op": "[MVR] VEX.128.66.0F38.Wy E4 !(11):rrr:bbb" , "io": "CF=W OF=W SF=W ZF=W AF=W PF=W"} ]}, - {"category": "GP GP_EXT", "ext": "MOVBE", "data": [ - {"inst": "movbe w:r16, m16" , "op": "RM: 66 0F 38 F0 /r"}, - {"inst": "movbe W:r32, m32" , "op": "RM: 0F 38 F0 /r"}, - {"inst": "movbe W:r64, m64" , "op": "RM: REX.W 0F 38 F0 /r"}, - {"inst": "movbe W:m16, r16" , "op": "MR: 66 0F 38 F1 /r"}, - {"inst": "movbe W:m32, r32" , "op": "MR: 0F 38 F1 /r"}, - {"inst": "movbe W:m64, r64" , "op": "MR: REX.W 0F 38 F1 /r"} + {"category": "GP GP_EXT", "ext": "CMPXCHG8B", "instructions": [ + {"any": "[lock|xacqrel] cmpxchg8b X:m64,X:,X:,," , "op": "[OP] 0F C7 /1" , "io": "ZF=W"} ]}, - {"category": "GP GP_EXT", "ext": "MOVDIRI", "data": [ - {"inst": "movdiri W:m32, r32" , "op": "MR: 0F 38 F9 /r"}, - {"inst": "movdiri W:m64, r64" , "op": "MR: REX.W 0F 38 F9 /r"} + {"category": "GP GP_EXT", "ext": "CMPXCHG16B", "instructions": [ + {"any": "[lock|xacqrel] cmpxchg16b X:m128,X:,X:,,","op": "[OP] REX.W 0F C7 /1" , "io": "ZF=W"} ]}, - {"category": "GP GP_EXT", "ext": "MOVDIR64B", "data": [ - {"inst": "movdir64b W:m512(es:r32), m512" , "op": "RM: 66 0F 38 F8 /r"}, - {"inst": "movdir64b W:m512(es:r64), m512" , "op": "RM: 66 0F 38 F8 /r"} + {"category": "GP GP_EXT", "ext": "FSGSBASE", "volatile": true, "instructions": [ + {"x64": "rdfsbase W:ry" , "op": "[M ] F3 0F AE /0"}, + {"x64": "rdgsbase W:ry" , "op": "[M ] F3 0F AE /1"}, + {"x64": "wrfsbase R:ry" , "op": "[M ] F3 0F AE /2"}, + {"x64": "wrgsbase R:ry" , "op": "[M ] F3 0F AE /3"} ]}, - {"category": "GP GP_EXT", "ext": "PCONFIG", "volatile": true, "data": [ - {"inst": "pconfig" , "op": "0F 01 C5"} + {"category": "GP GP_EXT", "ext": "FXSR", "volatile": true, "instructions": [ + {"any": "fxrstor R:mem" , "op": "[M ] 0F AE /1" , "io": "C0=W C1=W C2=W C3=W"}, + {"any": "fxrstor64 R:mem" , "op": "[M ] REX.W 0F AE /1" , "io": "C0=W C1=W C2=W C3=W"}, + {"any": "fxsave W:mem" , "op": "[M ] 0F AE /0" , "io": "C0=R C1=R C2=R C3=R"}, + {"any": "fxsave64 W:mem" , "op": "[M ] REX.W 0F AE /0" , "io": "C0=R C1=R C2=R C3=R"} ]}, - {"category": "GP GP_EXT", "ext": "POPCNT", "data": [ - {"inst": "popcnt w:r16, r16/m16" , "op": "RM: 66 F3 0F B8 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}, - {"inst": "popcnt W:r32, r32/m32" , "op": "RM: F3 0F B8 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}, - {"inst": "popcnt W:r64, r64/m64" , "op": "RM: REX.W F3 0F B8 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"} + {"category": "GP GP_EXT", "ext": "LAHFSAHF", "instructions": [ + {"any": "lahf w:" , "op": "[OP] 9F" , "io": "SF=R ZF=R AF=R PF=R CF=R"}, + {"any": "sahf R:" , "op": "[OP] 9E" , "io": "SF=W ZF=W AF=W PF=W CF=W"} ]}, - {"category": "GP GP_EXT", "ext": "OSPKE", "data": [ - {"inst": "rdpkru W:, W:, R:" , "op": "0F 01 EE"} + {"category": "GP GP_EXT", "ext": "LWP", "volatile": true, "instructions": [ + {"any": "llwpcb R:r32" , "op": "[M ] XOP.L0.P0.MAP9.W0 12 /0"}, + {"any": "llwpcb R:r64" , "op": "[M ] XOP.L0.P0.MAP9.W1 12 /0"}, + {"any": "lwpins R:r32, R:r32/m32, imm32" , "op": "[VM ] XOP.L0.P0.MAPA.W0 12 /0 id"}, + {"any": "lwpins R:r64, R:r32/m32, imm32" , "op": "[VM ] XOP.L0.P0.MAPA.W1 12 /0 id"}, + {"any": "lwpval R:r32, R:r32/m32, imm32" , "op": "[VM ] XOP.L0.P0.MAPA.W0 12 /1 id"}, + {"any": "lwpval R:r64, R:r32/m32, imm32" , "op": "[VM ] XOP.L0.P0.MAPA.W1 12 /1 id"}, + {"any": "slwpcb W:r32" , "op": "[M ] XOP.L0.P0.MAP9.W0 12 /1"}, + {"any": "slwpcb W:r64" , "op": "[M ] XOP.L0.P0.MAP9.W1 12 /1"} ]}, - {"category": "GP GP_EXT", "ext": "PREFETCHI", "arch": "X64", "volatile": true, "data": [ - {"inst": "prefetchit0 R:mem" , "op": "0F 18 /7"}, - {"inst": "prefetchit1 R:mem" , "op": "0F 18 /6"} + {"category": "GP GP_EXT", "ext": "LZCNT", "instructions": [ + {"any": "lzcnt w:rv, rv/mv" , "op": "[RM] F3 0F BD /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"} ]}, - {"category": "GP GP_EXT", "ext": "PREFETCHW", "volatile": true, "data": [ - {"inst": "prefetchw R:mem" , "op": "0F 0D /1" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"} + {"category": "GP GP_EXT", "ext": "MONITORX", "volatile": true, "instructions": [ + {"any": "monitorx R:, R:, R:" , "op": "0F 01 FA"}, + {"any": "mwaitx R:, R:, R:" , "op": "0F 01 FB"} ]}, - {"category": "GP GP_EXT", "ext": "PREFETCHWT1", "volatile": true, "data": [ - {"inst": "prefetchwt1 R:mem" , "op": "0F 0D /2" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"} + {"category": "GP GP_EXT", "ext": "MCOMMIT", "instructions": [ + {"any": "mcommit" , "op": "F3 0F 01 FA" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"} ]}, - {"category": "GP GP_EXT", "ext": "PTWRITE", "volatile": true, "data": [ - {"inst": "ptwrite R:r32/m32" , "op": "F3 0F AE /4"}, - {"inst": "ptwrite R:r64/m64" , "op": "REX.W F3 0F AE /4"} + {"category": "GP GP_EXT", "ext": "MOVBE", "instructions": [ + {"any": "movbe w:rv, R:mv" , "op": "[RM] 0F 38 F0 /r"}, + {"any": "movbe W:mv, R:rv" , "op": "[MR] 0F 38 F1 /r"} ]}, - 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ib/ub" , "op": "M: 0F 71 /4 ib"}, - {"inst": "psraw X:mm, mm/m64" , "op": "RM: 0F E1 /r"}, - {"inst": "psrld X:mm, ib/ub" , "op": "M: 0F 72 /2 ib"}, - {"inst": "psrld X:mm, mm/m64" , "op": "RM: 0F D2 /r"}, - {"inst": "psrlq X:mm, ib/ub" , "op": "M: 0F 73 /2 ib"}, - {"inst": "psrlq X:mm, mm/m64" , "op": "RM: 0F D3 /r"}, - {"inst": "psrlw X:mm, ib/ub" , "op": "M: 0F 71 /2 ib"}, - {"inst": "psrlw X:mm, mm/m64" , "op": "RM: 0F D1 /r"}, - {"inst": "psubb X:mm, mm/m64" , "op": "RM: 0F F8 /r"}, - {"inst": "psubd X:mm, mm/m64" , "op": "RM: 0F FA /r"}, - {"inst": "psubsb X:mm, mm/m64" , "op": "RM: 0F E8 /r"}, - {"inst": "psubsw X:mm, mm/m64" , "op": "RM: 0F E9 /r"}, - {"inst": "psubusb X:mm, mm/m64" , "op": "RM: 0F D8 /r"}, - {"inst": "psubusw X:mm, mm/m64" , "op": "RM: 0F D9 /r"}, - {"inst": "psubw X:mm, mm/m64" , "op": "RM: 0F F9 /r"}, - {"inst": "punpckhbw X:mm, mm/m64" , "op": "RM: 0F 68 /r"}, - {"inst": "punpckhdq X:mm, mm/m64" , "op": "RM: 0F 6A /r"}, - {"inst": "punpckhwd X:mm, mm/m64" , "op": "RM: 0F 69 /r"}, - {"inst": "punpcklbw X:mm, mm/m32" , "op": "RM: 0F 60 /r"}, - {"inst": "punpckldq X:mm, mm/m32" , "op": "RM: 0F 62 /r"}, - {"inst": "punpcklwd X:mm, mm/m32" , "op": "RM: 0F 61 /r"}, - {"inst": "pxor X:~mm, ~mm/m64" , "op": "RM: 0F EF /r"} - ]}, - - {"category": "MMX SIMD", "ext": "MMX2", "deprecated": true, "data": [ - {"inst": "maskmovq R:mm, mm, X:" , "op": "RM: 0F F7 /r"}, - {"inst": "movntq W:m64, mm" , "op": "MR: 0F E7 /r"}, - {"inst": "pavgb X:~mm, ~mm/m64" , "op": "RM: 0F E0 /r"}, - {"inst": "pavgw X:~mm, ~mm/m64" , "op": "RM: 0F E3 /r"}, - {"inst": "pextrw W:r32[15:0], mm, ib/ub" , "op": "RM: 0F C5 /r ib"}, - {"inst": "pinsrw X:mm, r32[15:0]/m16, ib/ub" , "op": "RM: 0F C4 /r ib"}, - {"inst": "pmaxsw X:~mm, ~mm/m64" , "op": "RM: 0F EE /r"}, - {"inst": "pmaxub X:~mm, ~mm/m64" , "op": "RM: 0F DE /r"}, - {"inst": "pminsw X:~mm, ~mm/m64" , "op": "RM: 0F EA /r"}, - {"inst": "pminub X:~mm, ~mm/m64" , "op": "RM: 0F DA /r"}, - {"inst": "pmovmskb W:r32[7:0], mm" , "op": "RM: 0F D7 /r"}, - {"inst": "pmulhuw X:~mm, ~mm/m64" , "op": "RM: 0F E4 /r"}, - {"inst": "psadbw X:~mm, ~mm/m64" , "op": "RM: 0F F6 /r"}, - {"inst": "pshufw W:mm, mm/m64, ib/ub" , "op": "RM: 0F 70 /r ib"} - ]}, - - {"category": "MMX SIMD", "ext": "3DNOW", "deprecated": true, "data": [ - {"inst": "pavgusb X:mm, mm/m64" , "op": "RM: 0F 0F /r BF"}, - {"inst": "pf2id W:mm, mm/m64" , "op": "RM: 0F 0F /r 1D"}, - {"inst": "pfacc X:mm, mm/m64" , "op": "RM: 0F 0F /r AE"}, - {"inst": "pfadd X:mm, mm/m64" , "op": "RM: 0F 0F /r 9E"}, - {"inst": "pfcmpeq X:mm, mm/m64" , "op": "RM: 0F 0F /r B0"}, - {"inst": "pfcmpge X:mm, mm/m64" , "op": "RM: 0F 0F /r 90"}, - {"inst": "pfcmpgt X:mm, mm/m64" , "op": "RM: 0F 0F /r A0"}, - {"inst": "pfmax X:mm, mm/m64" , "op": "RM: 0F 0F /r A4"}, - {"inst": "pfmin X:mm, mm/m64" , "op": "RM: 0F 0F /r 94"}, - {"inst": "pfmul X:mm, mm/m64" , "op": "RM: 0F 0F /r B4"}, - {"inst": "pfrcp W:mm, mm/m64" , "op": "RM: 0F 0F /r 96"}, - {"inst": "pfrcpit1 X:mm, mm/m64" , "op": "RM: 0F 0F /r A6"}, - {"inst": "pfrcpit2 X:mm, mm/m64" , "op": "RM: 0F 0F /r B6"}, - {"inst": "pfrsqit1 W:mm, mm/m64" , "op": "RM: 0F 0F /r A7"}, - {"inst": "pfrsqrt W:mm, mm/m64" , "op": "RM: 0F 0F /r 97"}, - {"inst": "pfsub X:mm, mm/m64" , "op": "RM: 0F 0F /r 9A"}, - {"inst": "pfsubr X:mm, mm/m64" , "op": "RM: 0F 0F /r AA"}, - {"inst": "pi2fd W:mm, mm/m64" , "op": "RM: 0F 0F /r 0D"}, - {"inst": "pmulhrw X:mm, mm/m64" , "op": "RM: 0F 0F /r B7"} - ]}, - - {"category": "MMX SIMD", "ext": "3DNOW2", "deprecated": true, "data": [ - {"inst": "pf2iw W:mm, mm/m64" , "op": "RM: 0F 0F /r 1C"}, - {"inst": "pfnacc X:mm, mm/m64" , "op": "RM: 0F 0F /r 8A"}, - {"inst": "pfpnacc X:mm, mm/m64" , "op": "RM: 0F 0F /r 8E"}, - {"inst": "pi2fw W:mm, mm/m64" , "op": "RM: 0F 0F /r 0C"}, - {"inst": "pswapd W:mm, mm/m64" , "op": "RM: 0F 0F /r BB"} - ]}, - - {"category": "MMX SIMD", "ext": "GEODE", "deprecated": true, "data": [ - {"inst": "pfrcpv X:mm, mm/m64" , "op": "RM: 0F 0F /r 86"}, - {"inst": "pfrsqrtv X:mm, mm/m64" , "op": "RM: 0F 0F /r 87"} - ]}, - - {"category": "SSE STATE", "ext": "SSE", "data": [ - {"inst": "ldmxcsr R:m32" , "op": "0F AE /2", "io": "MXCSR=W"}, - {"inst": "stmxcsr W:m32" , "op": "0F AE /3", "io": "MXCSR=R"} - ]}, - - {"category": "SSE SCALAR", "ext": "SSE", "data": [ - {"inst": "addss x:xmm[31:0], xmm[31:0]/m32" , "op": "RM: F3 0F 58 /r"}, - {"inst": "cmpss x:xmm[31:0], xmm[31:0]/m32, ib/ub" , "op": "RM: F3 0F C2 /r ib"}, - {"inst": "comiss R:xmm[31:0], xmm[31:0]/m32" , "op": "RM: 0F 2F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, - {"inst": "cvtsi2ss w:xmm[31:0], r64/m64" , "op": "RM: REX.W F3 0F 2A /r"}, - {"inst": "cvtsi2ss w:xmm[31:0], r32/m32" , "op": "RM: F3 0F 2A /r"}, - {"inst": "cvtss2si W:r32, xmm[31:0]/m32" , "op": "RM: F3 0F 2D /r"}, - {"inst": "cvtss2si W:r64, xmm[31:0]/m32" , "op": "RM: REX.W F3 0F 2D /r"}, - {"inst": "cvttss2si W:r64, xmm[31:0]/m32" , "op": "RM: REX.W F3 0F 2C /r"}, - {"inst": "cvttss2si W:r32, xmm[31:0]/m32" , "op": "RM: F3 0F 2C /r"}, - {"inst": "divss x:xmm[31:0], xmm[31:0]/m32" , "op": "RM: F3 0F 5E /r"}, - {"inst": "maxss x:xmm[31:0], xmm[31:0]/m32" , "op": "RM: F3 0F 5F /r"}, - {"inst": "minss x:xmm[31:0], xmm[31:0]/m32" , "op": "RM: F3 0F 5D /r"}, - {"inst": "movss w:xmm[31:0], xmm[31:0]" , "op": "RM: F3 0F 10 /r"}, - {"inst": "movss W:xmm[31:0], m32" , "op": "RM: F3 0F 10 /r"}, - {"inst": "movss W:m32, xmm[31:0]" , "op": "MR: F3 0F 11 /r"}, - {"inst": "mulss x:xmm[31:0], xmm[31:0]/m32" , "op": "RM: F3 0F 59 /r"}, - {"inst": "rcpss w:xmm[31:0], xmm[31:0]/m32" , "op": "RM: F3 0F 53 /r"}, - {"inst": "rsqrtss w:xmm[31:0], xmm[31:0]/m32" , "op": "RM: F3 0F 52 /r"}, - {"inst": "sqrtss w:xmm[31:0], xmm[31:0]/m32" , "op": "RM: F3 0F 51 /r"}, - {"inst": "subss x:xmm[31:0], xmm[31:0]/m32" , "op": "RM: F3 0F 5C /r"}, - {"inst": "ucomiss R:xmm[31:0], xmm[31:0]/m32" , "op": "RM: 0F 2E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"} - ]}, - - {"category": "SSE SIMD", "ext": "SSE", "data": [ - {"inst": "addps X:~xmm, ~xmm/m128" , "op": "RM: 0F 58 /r"}, - {"inst": "andnps X:xmm, xmm/m128" , "op": "RM: 0F 55 /r"}, - {"inst": "andps X:~xmm, ~xmm/m128" , "op": "RM: 0F 54 /r"}, - {"inst": "cmpps X:xmm, xmm/m128, ib/ub" , "op": "RM: 0F C2 /r ib"}, - {"inst": "cvtpi2ps w:xmm[63:0], mm/m64" , "op": "RM: 0F 2A /r"}, - {"inst": "cvtps2pi W:mm, xmm[63:0]/m64" , "op": "RM: 0F 2D /r"}, - {"inst": "cvttps2pi W:mm, xmm[63:0]/m64" , "op": "RM: 0F 2C /r"}, - {"inst": "divps X:xmm, xmm/m128" , "op": "RM: 0F 5E /r"}, - {"inst": "maxps X:xmm, xmm/m128" , "op": "RM: 0F 5F /r"}, - {"inst": "minps X:xmm, xmm/m128" , "op": "RM: 0F 5D /r"}, - {"inst": "movaps W:xmm, xmm/m128" , "op": "RM: 0F 28 /r"}, - {"inst": "movaps W:xmm/m128, xmm" , "op": "MR: 0F 29 /r"}, - {"inst": "movhlps w:xmm[63:0], xmm[127:64]" , "op": "RM: 0F 12 /r"}, - {"inst": "movhps W:m64, xmm[127:64]" , "op": "MR: 0F 17 /r"}, - {"inst": "movhps w:xmm[127:64], m64" , "op": "RM: 0F 16 /r"}, - {"inst": "movlhps w:xmm[127:64], xmm[63:0]" , "op": "RM: 0F 16 /r"}, - {"inst": "movlps W:m64, xmm[63:0]" , "op": "MR: 0F 13 /r"}, - {"inst": "movlps w:xmm[63:0], m64" , "op": "RM: 0F 12 /r"}, - {"inst": "movmskps W:r32[3:0], xmm" , "op": "RM: 0F 50 /r"}, - {"inst": "movntps W:m128, xmm" , "op": "MR: 0F 2B /r"}, - {"inst": "movups W:xmm, xmm/m128" , "op": "RM: 0F 10 /r"}, - {"inst": "movups W:xmm/m128, xmm" , "op": "MR: 0F 11 /r"}, - {"inst": "mulps X:~xmm, ~xmm/m128" , "op": "RM: 0F 59 /r"}, - {"inst": "orps X:~xmm, ~xmm/m128" , "op": "RM: 0F 56 /r"}, - {"inst": "rcpps W:xmm, xmm/m128" , "op": "RM: 0F 53 /r"}, - {"inst": "rsqrtps W:xmm, xmm/m128" , "op": "RM: 0F 52 /r"}, - {"inst": "shufps X:xmm, xmm/m128, ib/ub" , "op": "RM: 0F C6 /r ib"}, - {"inst": "sqrtps W:xmm, xmm/m128" , "op": "RM: 0F 51 /r"}, - {"inst": "subps X:xmm, xmm/m128" , "op": "RM: 0F 5C /r"}, - {"inst": "unpckhps X:xmm, xmm/m128" , "op": "RM: 0F 15 /r"}, - {"inst": "unpcklps X:xmm, xmm/m128" , "op": "RM: 0F 14 /r"}, - {"inst": "xorps X:~xmm, ~xmm/m128" , "op": "RM: 0F 57 /r"} - ]}, - - {"category": "SSE SCALAR", "ext": "SSE2", "data": [ - {"inst": "addsd x:xmm[63:0], xmm[63:0]/m64" , "op": "RM: F2 0F 58 /r"}, - {"inst": "cmpsd x:xmm[63:0], xmm[63:0]/m64, ib/ub" , "op": "RM: F2 0F C2 /r ib"}, - {"inst": "comisd R:xmm[63:0], xmm[63:0]/m64" , "op": "RM: 66 0F 2F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, - {"inst": "cvtsd2si W:r32, xmm[63:0]/m64" , "op": "RM: F2 0F 2D /r"}, - {"inst": "cvtsd2si W:r64, xmm[63:0]/m64" , "op": "RM: REX.W F2 0F 2D /r"}, - {"inst": "cvtsd2ss w:xmm[31:0], xmm[63:0]/m64" , "op": "RM: F2 0F 5A /r"}, - {"inst": "cvtsi2sd w:xmm[63:0], r32/m32" , "op": "RM: F2 0F 2A /r"}, - {"inst": "cvtsi2sd w:xmm[63:0], r64/m64" , "op": "RM: REX.W F2 0F 2A /r"}, - {"inst": "cvtss2sd w:xmm[63:0], xmm[31:0]/m32" , "op": "RM: F3 0F 5A /r"}, - {"inst": "cvttsd2si W:r32, xmm[63:0]/m64" , "op": "RM: F2 0F 2C /r"}, - {"inst": "cvttsd2si W:r64, xmm[63:0]/m64" , "op": "RM: REX.W F2 0F 2C /r"}, - {"inst": "divsd x:xmm[63:0], xmm[63:0]/m64" , "op": "RM: F2 0F 5E /r"}, - {"inst": "maxsd x:xmm[63:0], xmm[63:0]/m64" , "op": "RM: F2 0F 5F /r"}, - {"inst": "minsd x:xmm[63:0], xmm[63:0]/m64" , "op": "RM: F2 0F 5D /r"}, - {"inst": "movsd w:xmm[63:0], xmm[63:0]" , "op": "RM: F2 0F 10 /r"}, - {"inst": "movsd W:xmm[63:0], m64" , "op": "RM: F2 0F 10 /r"}, - {"inst": "movsd W:m64, xmm[63:0]" , "op": "MR: F2 0F 11 /r"}, - {"inst": "mulsd x:xmm[63:0], xmm[63:0]/m64" , "op": "RM: F2 0F 59 /r"}, - {"inst": "sqrtsd w:xmm[63:0], xmm[63:0]/m64" , "op": "RM: F2 0F 51 /r"}, - {"inst": "subsd x:xmm[63:0], xmm[63:0]/m64" , "op": "RM: F2 0F 5C /r"}, - {"inst": "ucomisd R:xmm[63:0], xmm[63:0]/m64" , "op": "RM: 66 0F 2E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"} - ]}, - - {"category": "SSE SIMD", "ext": "SSE2", "data": [ - {"inst": "addpd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 58 /r"}, - {"inst": "andnpd X:xmm, xmm/m128" , "op": "RM: 66 0F 55 /r"}, - {"inst": "andpd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 54 /r"}, - {"inst": "cmppd X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F C2 /r ib"}, - {"inst": "cvtdq2pd W:xmm, xmm[63:0]/m64" , "op": "RM: F3 0F E6 /r"}, - {"inst": "cvtdq2ps W:xmm, xmm/m128" , "op": "RM: 0F 5B /r"}, - {"inst": "cvtpd2dq W:xmm[63:0], xmm/m128" , "op": "RM: F2 0F E6 /r"}, - {"inst": "cvtpd2pi W:mm, xmm/m128" , "op": "RM: 66 0F 2D /r"}, - {"inst": "cvtpd2ps W:xmm[63:0], xmm/m128" , "op": "RM: 66 0F 5A /r"}, - {"inst": "cvtpi2pd W:xmm, R:mm[63:0]/m64" , "op": "RM: 66 0F 2A /r"}, - {"inst": "cvtps2dq W:xmm, xmm/m128" , "op": "RM: 66 0F 5B /r"}, - {"inst": "cvtps2pd W:xmm, xmm[63:0]/m64" , "op": "RM: 0F 5A /r"}, - {"inst": "cvttpd2dq W:xmm[63:0], xmm/m128" , "op": "RM: 66 0F E6 /r"}, - {"inst": "cvttpd2pi W:mm, xmm/m128" , "op": "RM: 66 0F 2C /r"}, - {"inst": "cvttps2dq W:xmm, xmm/m128" , "op": "RM: F3 0F 5B /r"}, - {"inst": "divpd X:xmm, xmm/m128" , "op": "RM: 66 0F 5E /r"}, - {"inst": "maskmovdqu R:xmm, xmm, X:" , "op": "RM: 66 0F F7 /r"}, - {"inst": "maxpd X:xmm, xmm/m128" , "op": "RM: 66 0F 5F /r"}, - {"inst": "minpd X:xmm, xmm/m128" , "op": "RM: 66 0F 5D /r"}, - {"inst": "movapd W:xmm, xmm/m128" , "op": "RM: 66 0F 28 /r"}, - {"inst": "movapd W:xmm/m128, xmm" , "op": "MR: 66 0F 29 /r"}, - {"inst": "movd W:r32[31:0]/m32, xmm[31:0]" , "op": "MR: 66 0F 7E /r"}, - {"inst": "movd W:xmm[31:0], R:r32[31:0]/m32" , "op": "RM: 66 0F 6E /r"}, - {"inst": "movdq2q W:mm, xmm[63:0]" , "op": "RM: F2 0F D6 /r"}, - {"inst": "movdqa W:xmm, xmm/m128" , "op": "RM: 66 0F 6F /r"}, - {"inst": "movdqa W:xmm/m128, xmm" , "op": "MR: 66 0F 7F /r"}, - {"inst": "movdqu W:xmm, xmm/m128" , "op": "RM: F3 0F 6F /r"}, - {"inst": "movdqu W:xmm/m128, xmm" , "op": "MR: F3 0F 7F /r"}, - {"inst": "movhpd W:m64, xmm[127:64]" , "op": "MR: 66 0F 17 /r"}, - {"inst": "movhpd w:xmm[127:64], m64" , "op": "RM: 66 0F 16 /r"}, - {"inst": "movlpd W:m64, xmm[63:0]" , "op": "MR: 66 0F 13 /r"}, - {"inst": "movlpd w:xmm[63:0], m64" , "op": "RM: 66 0F 12 /r"}, - {"inst": "movmskpd W:r32[1:0], xmm" , "op": "RM: 66 0F 50 /r"}, - {"inst": "movntdq W:m128, xmm" , "op": "MR: 66 0F E7 /r"}, - {"inst": "movntpd W:m128, xmm" , "op": "MR: 66 0F 2B /r"}, - {"inst": "movq W:r64/m64, xmm[63:0]" , "op": "MR: REX.W 66 0F 7E /r"}, - {"inst": "movq W:xmm[63:0], r64[63:0]/m64" , "op": "RM: REX.W 66 0F 6E /r"}, - {"inst": "movq W:xmm[63:0], xmm[63:0]/m64" , "op": "RM: F3 0F 7E /r"}, - {"inst": "movq W:xmm[63:0]/m64, xmm[63:0]" , "op": "MR: 66 0F D6 /r"}, - {"inst": "movq2dq W:xmm[63:0], mm" , "op": "RM: F3 0F D6 /r"}, - {"inst": "movupd W:xmm, xmm/m128" , "op": "RM: 66 0F 10 /r"}, - {"inst": "movupd W:xmm/m128, xmm" , "op": "MR: 66 0F 11 /r"}, - {"inst": "mulpd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 59 /r"}, - {"inst": "orpd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 56 /r"}, - {"inst": "packssdw X:xmm, xmm/m128" , "op": "RM: 66 0F 6B /r"}, - {"inst": "packsswb X:xmm, xmm/m128" , "op": "RM: 66 0F 63 /r"}, - {"inst": "packuswb X:xmm, xmm/m128" , "op": "RM: 66 0F 67 /r"}, - {"inst": "paddb X:~xmm, ~xmm/m128" , "op": "RM: 66 0F FC /r"}, - {"inst": "paddd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F FE /r"}, - {"inst": "paddq X:~mm, ~mm/m64" , "op": "RM: 0F D4 /r"}, - {"inst": "paddq X:~xmm, ~xmm/m128" , "op": "RM: 66 0F D4 /r"}, - {"inst": "paddsb X:~xmm, ~xmm/m128" , "op": "RM: 66 0F EC /r"}, - {"inst": "paddsw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F ED /r"}, - {"inst": "paddusb X:~xmm, ~xmm/m128" , "op": "RM: 66 0F DC /r"}, - {"inst": "paddusw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F DD /r"}, - {"inst": "paddw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F FD /r"}, - {"inst": "pand X:~xmm, ~xmm/m128" , "op": "RM: 66 0F DB /r"}, - {"inst": "pandn X:xmm, xmm/m128" , "op": "RM: 66 0F DF /r"}, - {"inst": "pavgb X:~xmm, ~xmm/m128" , "op": "RM: 66 0F E0 /r"}, - {"inst": "pavgw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F E3 /r"}, - {"inst": "pcmpeqb X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 74 /r"}, - {"inst": "pcmpeqd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 76 /r"}, - {"inst": "pcmpeqw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 75 /r"}, - {"inst": "pcmpgtb X:xmm, xmm/m128" , "op": "RM: 66 0F 64 /r"}, - {"inst": "pcmpgtd X:xmm, xmm/m128" , "op": "RM: 66 0F 66 /r"}, - {"inst": "pcmpgtw X:xmm, xmm/m128" , "op": "RM: 66 0F 65 /r"}, - {"inst": "pextrw W:r32[15:0], xmm, ib/ub" , "op": "RM: 66 0F C5 /r ib"}, - {"inst": "pinsrw X:xmm, r32[15:0]/m16, ib/ub" , "op": "RM: 66 0F C4 /r ib"}, - {"inst": "pmaddwd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F F5 /r"}, - {"inst": "pmaxsw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F EE /r"}, - {"inst": "pmaxub X:~xmm, ~xmm/m128" , "op": "RM: 66 0F DE /r"}, - {"inst": "pminsw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F EA /r"}, - {"inst": "pminub X:~xmm, ~xmm/m128" , "op": "RM: 66 0F DA /r"}, - {"inst": "pmovmskb W:r32[15:0], xmm" , "op": "RM: 66 0F D7 /r"}, - {"inst": "pmulhuw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F E4 /r"}, - {"inst": "pmulhw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F E5 /r"}, - {"inst": "pmullw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F D5 /r"}, - {"inst": "pmuludq X:~mm, ~mm/m64" , "op": "RM: 0F F4 /r"}, - {"inst": "pmuludq X:~xmm, ~xmm/m128" , "op": "RM: 66 0F F4 /r"}, - {"inst": "por X:~xmm, ~xmm/m128" , "op": "RM: 66 0F EB /r"}, - {"inst": "psadbw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F F6 /r"}, - {"inst": "pshufd W:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 70 /r ib"}, - {"inst": "pshufhw W:xmm, xmm/m128, ib/ub" , "op": "RM: F3 0F 70 /r ib"}, - {"inst": "pshuflw W:xmm, xmm/m128, ib/ub" , "op": "RM: F2 0F 70 /r ib"}, - {"inst": "pslld X:xmm, ib/ub" , "op": "M: 66 0F 72 /6 ib"}, - {"inst": "pslld X:xmm, xmm/m128" , "op": "RM: 66 0F F2 /r"}, - {"inst": "pslldq X:xmm, ib/ub" , "op": "M: 66 0F 73 /7 ib"}, - {"inst": "psllq X:xmm, ib/ub" , "op": "M: 66 0F 73 /6 ib"}, - {"inst": "psllq X:xmm, xmm/m128" , "op": "RM: 66 0F F3 /r"}, - {"inst": "psllw X:xmm, ib/ub" , "op": "M: 66 0F 71 /6 ib"}, - {"inst": "psllw X:xmm, xmm/m128" , "op": "RM: 66 0F F1 /r"}, - {"inst": "psrad X:xmm, ib/ub" , "op": "M: 66 0F 72 /4 ib"}, - {"inst": "psrad X:xmm, xmm/m128" , "op": "RM: 66 0F E2 /r"}, - {"inst": "psraw X:xmm, ib/ub" , "op": "M: 66 0F 71 /4 ib"}, - {"inst": "psraw X:xmm, xmm/m128" , "op": "RM: 66 0F E1 /r"}, - {"inst": "psrld X:xmm, ib/ub" , "op": "M: 66 0F 72 /2 ib"}, - {"inst": "psrld X:xmm, xmm/m128" , "op": "RM: 66 0F D2 /r"}, - {"inst": "psrldq X:xmm, ib/ub" , "op": "M: 66 0F 73 /3 ib"}, - {"inst": "psrlq X:xmm, ib/ub" , "op": "M: 66 0F 73 /2 ib"}, - {"inst": "psrlq X:xmm, xmm/m128" , "op": "RM: 66 0F D3 /r"}, - {"inst": "psrlw X:xmm, ib/ub" , "op": "M: 66 0F 71 /2 ib"}, - {"inst": "psrlw X:xmm, xmm/m128" , "op": "RM: 66 0F D1 /r"}, - {"inst": "psubb X:xmm, xmm/m128" , "op": "RM: 66 0F F8 /r"}, - {"inst": "psubd X:xmm, xmm/m128" , "op": "RM: 66 0F FA /r"}, - {"inst": "psubq X:mm, mm/m64" , "op": "RM: 0F FB /r"}, - {"inst": "psubq X:xmm, xmm/m128" , "op": "RM: 66 0F FB /r"}, - {"inst": "psubsb X:xmm, xmm/m128" , "op": "RM: 66 0F E8 /r"}, - {"inst": "psubsw X:xmm, xmm/m128" , "op": "RM: 66 0F E9 /r"}, - {"inst": "psubusb X:xmm, xmm/m128" , "op": "RM: 66 0F D8 /r"}, - {"inst": "psubusw X:xmm, xmm/m128" , "op": "RM: 66 0F D9 /r"}, - {"inst": "psubw X:xmm, xmm/m128" , "op": "RM: 66 0F F9 /r"}, - {"inst": "punpckhbw X:xmm, xmm/m128" , "op": "RM: 66 0F 68 /r"}, - {"inst": "punpckhdq X:xmm, xmm/m128" , "op": "RM: 66 0F 6A /r"}, - {"inst": "punpckhqdq X:xmm, xmm/m128" , "op": "RM: 66 0F 6D /r"}, - {"inst": "punpckhwd X:xmm, xmm/m128" , "op": "RM: 66 0F 69 /r"}, - {"inst": "punpcklbw X:xmm, xmm/m128" , "op": "RM: 66 0F 60 /r"}, - {"inst": "punpckldq X:xmm, xmm/m128" , "op": "RM: 66 0F 62 /r"}, - {"inst": "punpcklqdq X:xmm, xmm/m128" , "op": "RM: 66 0F 6C /r"}, - {"inst": "punpcklwd X:xmm, xmm/m128" , "op": "RM: 66 0F 61 /r"}, - {"inst": "pxor X:~xmm, ~xmm/m128" , "op": "RM: 66 0F EF /r"}, - {"inst": "shufpd X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F C6 /r ib"}, - {"inst": "sqrtpd W:xmm, xmm/m128" , "op": "RM: 66 0F 51 /r"}, - {"inst": "subpd X:xmm, xmm/m128" , "op": "RM: 66 0F 5C /r"}, - {"inst": "unpckhpd X:xmm, xmm/m128" , "op": "RM: 66 0F 15 /r"}, - {"inst": "unpcklpd X:xmm, xmm/m128" , "op": "RM: 66 0F 14 /r"}, - {"inst": "xorpd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 57 /r"} - ]}, - - {"category": "SSE SIMD", "ext": "SSE3", "data": [ - {"inst": "addsubpd X:xmm, xmm/m128" , "op": "RM: 66 0F D0 /r"}, - {"inst": "addsubps X:xmm, xmm/m128" , "op": "RM: F2 0F D0 /r"}, - {"inst": "haddpd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 7C /r"}, - {"inst": "haddps X:~xmm, ~xmm/m128" , "op": "RM: F2 0F 7C /r"}, - {"inst": "hsubpd X:xmm, xmm/m128" , "op": "RM: 66 0F 7D /r"}, - {"inst": "hsubps X:xmm, xmm/m128" , "op": "RM: F2 0F 7D /r"}, - {"inst": "lddqu W:xmm, m128" , "op": "RM: F2 0F F0 /r"}, - {"inst": "movddup W:xmm, xmm[63:0]/m64" , "op": "RM: F2 0F 12 /r"}, - {"inst": "movshdup W:xmm, xmm/m128" , "op": "RM: F3 0F 16 /r"}, - {"inst": "movsldup W:xmm, xmm/m128" , "op": "RM: F3 0F 12 /r"} - ]}, - - {"category": "SSE SIMD", "ext": "SSSE3", "data": [ - {"inst": "pabsb W:mm, mm/m64" , "op": "RM: 0F 38 1C /r"}, - {"inst": "pabsb W:xmm, xmm/m128" , "op": "RM: 66 0F 38 1C /r"}, - {"inst": "pabsd W:mm, mm/m64" , "op": "RM: 0F 38 1E /r"}, - {"inst": "pabsd W:xmm, xmm/m128" , "op": "RM: 66 0F 38 1E /r"}, - {"inst": "pabsw W:mm, mm/m64" , "op": "RM: 0F 38 1D /r"}, - {"inst": "pabsw W:xmm, xmm/m128" , "op": "RM: 66 0F 38 1D /r"}, - {"inst": "palignr X:mm, mm/m64, ib/ub" , "op": "RM: 0F 3A 0F /r ib"}, - {"inst": "palignr X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A 0F /r ib"}, - {"inst": "phaddd X:~mm, ~mm/m64" , "op": "RM: 0F 38 02 /r"}, - {"inst": "phaddd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 02 /r"}, - {"inst": "phaddsw X:~mm, ~mm/m64" , "op": "RM: 0F 38 03 /r"}, - {"inst": "phaddsw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 03 /r"}, - {"inst": "phaddw X:~mm, ~mm/m64" , "op": "RM: 0F 38 01 /r"}, - {"inst": "phaddw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 01 /r"}, - {"inst": "phsubd X:mm, mm/m64" , "op": "RM: 0F 38 06 /r"}, - {"inst": "phsubd X:xmm, xmm/m128" , "op": "RM: 66 0F 38 06 /r"}, - {"inst": "phsubsw X:mm, mm/m64" , "op": "RM: 0F 38 07 /r"}, - {"inst": "phsubsw X:xmm, xmm/m128" , "op": "RM: 66 0F 38 07 /r"}, - {"inst": "phsubw X:mm, mm/m64" , "op": "RM: 0F 38 05 /r"}, - {"inst": "phsubw X:xmm, xmm/m128" , "op": "RM: 66 0F 38 05 /r"}, - {"inst": "pmaddubsw X:~mm, ~mm/m64" , "op": "RM: 0F 38 04 /r"}, - {"inst": "pmaddubsw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 04 /r"}, - {"inst": "pmulhrsw X:~mm, ~mm/m64" , "op": "RM: 0F 38 0B /r"}, - {"inst": "pmulhrsw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 0B /r"}, - {"inst": "pshufb X:mm, mm/m64" , "op": "RM: 0F 38 00 /r"}, - {"inst": "pshufb X:xmm, xmm/m128" , "op": "RM: 66 0F 38 00 /r"}, - {"inst": "psignb X:mm, mm/m64" , "op": "RM: 0F 38 08 /r"}, - {"inst": "psignb X:xmm, xmm/m128" , "op": "RM: 66 0F 38 08 /r"}, - {"inst": "psignd X:mm, mm/m64" , "op": "RM: 0F 38 0A /r"}, - {"inst": "psignd X:xmm, xmm/m128" , "op": "RM: 66 0F 38 0A /r"}, - {"inst": "psignw X:mm, mm/m64" , "op": "RM: 0F 38 09 /r"}, - {"inst": "psignw X:xmm, xmm/m128" , "op": "RM: 66 0F 38 09 /r"} - ]}, - - {"category": "SSE SCALAR", "ext": "SSE4_1", "data": [ - {"inst": "roundsd w:xmm[63:0], xmm[63:0]/m64, ib/ub" , "op": "RM: 66 0F 3A 0B /r ib"}, - {"inst": "roundss w:xmm[31:0], xmm[31:0]/m32, ib/ub" , "op": "RM: 66 0F 3A 0A /r ib"} - ]}, - - {"category": "SSE SIMD", "ext": "SSE4_1", "data": [ - {"inst": "blendpd X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A 0D /r ib"}, - {"inst": "blendps X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A 0C /r ib"}, - {"inst": "blendvpd X:xmm, xmm/m128, " , "op": "RM: 66 0F 38 15 /r"}, - {"inst": "blendvps X:xmm, xmm/m128, " , "op": "RM: 66 0F 38 14 /r"}, - {"inst": "dppd X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A 41 /r ib"}, - {"inst": "dpps X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A 40 /r ib"}, - {"inst": "extractps W:r32/m32, xmm, ib/ub" , "op": "MR: 66 0F 3A 17 /r ib"}, - {"inst": "insertps X:xmm, xmm[31:0]/m32, ib/ub" , "op": "RM: 66 0F 3A 21 /r ib"}, - {"inst": "movntdqa W:xmm, m128" , "op": "RM: 66 0F 38 2A /r"}, - {"inst": "mpsadbw X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A 42 /r ib"}, - {"inst": "packusdw X:xmm, xmm/m128" , "op": "RM: 66 0F 38 2B /r"}, - {"inst": "pblendvb X:xmm, xmm/m128, " , "op": "RM: 66 0F 38 10 /r"}, - {"inst": "pblendw X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A 0E /r ib"}, - {"inst": "pcmpeqq X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 29 /r"}, - {"inst": "pextrb W:r32[7:0]/m8, xmm, ib/ub" , "op": "MR: 66 0F 3A 14 /r ib"}, - {"inst": "pextrd W:r32[31:0]/m32, xmm, ib/ub" , "op": "MR: 66 0F 3A 16 /r ib"}, - {"inst": "pextrq W:r64/m64, xmm, ib/ub" , "op": "MR: REX.W 66 0F 3A 16 /r ib"}, - {"inst": "pextrw W:r32[15:0]/m16, xmm, ib/ub" , "op": "MR: 66 0F 3A 15 /r ib"}, - {"inst": "phminposuw W:xmm[18:0], xmm/m128" , "op": "RM: 66 0F 38 41 /r"}, - {"inst": "pinsrb X:xmm, r32[7:0]/m8, ib/ub" , "op": "RM: 66 0F 3A 20 /r ib"}, - {"inst": "pinsrd X:xmm, r32[31:0]/m32, ib/ub" , "op": "RM: 66 0F 3A 22 /r ib"}, - {"inst": "pinsrq X:xmm, r64/m64, ib/ub" , "op": "RM: REX.W 66 0F 3A 22 /r ib"}, - {"inst": "pmaxsb X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 3C /r"}, - {"inst": "pmaxsd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 3D /r"}, - {"inst": "pmaxud X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 3F /r"}, - {"inst": "pmaxuw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 3E /r"}, - {"inst": "pminsb X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 38 /r"}, - {"inst": "pminsd X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 39 /r"}, - {"inst": "pminud X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 3B /r"}, - {"inst": "pminuw X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 3A /r"}, - {"inst": "pmovsxbd W:xmm, xmm[31:0]/m32" , "op": "RM: 66 0F 38 21 /r"}, - {"inst": "pmovsxbq W:xmm, xmm[15:0]/m16" , "op": "RM: 66 0F 38 22 /r"}, - {"inst": "pmovsxbw W:xmm, xmm[63:0]/m64" , "op": "RM: 66 0F 38 20 /r"}, - {"inst": "pmovsxdq W:xmm, xmm[63:0]/m64" , "op": "RM: 66 0F 38 25 /r"}, - {"inst": "pmovsxwd W:xmm, xmm[63:0]/m64" , "op": "RM: 66 0F 38 23 /r"}, - {"inst": "pmovsxwq W:xmm, xmm[31:0]/m32" , "op": "RM: 66 0F 38 24 /r"}, - {"inst": "pmovzxbd W:xmm, xmm[31:0]/m32" , "op": "RM: 66 0F 38 31 /r"}, - {"inst": "pmovzxbq W:xmm, xmm[15:0]/m16" , "op": "RM: 66 0F 38 32 /r"}, - {"inst": "pmovzxbw W:xmm, xmm[63:0]/m64" , "op": "RM: 66 0F 38 30 /r"}, - {"inst": "pmovzxdq W:xmm, xmm[63:0]/m64" , "op": "RM: 66 0F 38 35 /r"}, - {"inst": "pmovzxwd W:xmm, xmm[63:0]/m64" , "op": "RM: 66 0F 38 33 /r"}, - {"inst": "pmovzxwq W:xmm, xmm[31:0]/m32" , "op": "RM: 66 0F 38 34 /r"}, - {"inst": "pmuldq X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 28 /r"}, - {"inst": "pmulld X:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 40 /r"}, - {"inst": "ptest R:~xmm, ~xmm/m128" , "op": "RM: 66 0F 38 17 /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "roundpd W:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A 09 /r ib"}, - {"inst": "roundps W:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A 08 /r ib"} - ]}, - - {"category": "SSE SIMD", "ext": "SSE4_2", "data": [ - {"inst": "pcmpestri R:xmm, xmm/m128, ib/ub, W:,," , "op": "RM: 66 0F 3A 61 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, - {"inst": "pcmpestrm R:xmm, xmm/m128, ib/ub, W:,," , "op": "RM: 66 0F 3A 60 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, - {"inst": "pcmpgtq X:xmm, xmm/m128" , "op": "RM: 66 0F 38 37 /r"}, - {"inst": "pcmpistri R:xmm, xmm/m128, ib/ub, W:" , "op": "RM: 66 0F 3A 63 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, - {"inst": "pcmpistrm R:xmm, xmm/m128, ib/ub, W:" , "op": "RM: 66 0F 3A 62 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"} - ]}, - - {"category": "SSE SCALAR", "ext": "SSE4A", "data": [ - {"inst": "movntsd W:m64, xmm[63:0]" , "op": "RM: F2 0F 2B /r"}, - {"inst": "movntss W:m32, xmm[31:0]" , "op": "RM: F3 0F 2B /r"} - ]}, - - {"category": "SSE SIMD", "ext": "SSE4A", "data": [ - {"inst": "extrq X:xmm, ib/ub, ib/ub" , "op": "R: 66 0F 78 /0 ib ib"}, - {"inst": "extrq X:xmm, xmm" , "op": "RM: 66 0F 79 /r"}, - {"inst": "insertq X:xmm, xmm" , "op": "RM: F2 0F 79 /r"}, - {"inst": "insertq X:xmm, xmm, ib/ub, ib/ub" , "op": "RM: F2 0F 78 /r ib ib"} - ]}, - - {"category": "SSE SIMD CRYPTO_HASH", "ext": "AESNI", "data": [ - {"inst": "aesdec X:xmm, xmm/m128" , "op": "RM: 66 0F 38 DE /r"}, - {"inst": "aesdeclast X:xmm, xmm/m128" , "op": "RM: 66 0F 38 DF /r"}, - {"inst": "aesenc X:xmm, xmm/m128" , "op": "RM: 66 0F 38 DC /r"}, - {"inst": "aesenclast X:xmm, xmm/m128" , "op": "RM: 66 0F 38 DD /r"}, - {"inst": "aesimc W:xmm, xmm/m128" , "op": "RM: 66 0F 38 DB /r"}, - {"inst": "aeskeygenassist W:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A DF /r ib"} - ]}, - - {"category": "SSE SIMD", "ext": "GFNI", "data": [ - {"inst": "gf2p8affineinvqb X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A CF /r ib"}, - {"inst": "gf2p8affineqb X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A CE /r ib"}, - {"inst": "gf2p8mulb X:xmm, xmm/m128" , "op": "RM: 66 0F 38 CF /r"} - ]}, - - {"category": "SSE SIMD", "ext": "PCLMULQDQ", "data": [ - {"inst": "pclmulqdq X:xmm, xmm/m128, ib/ub" , "op": "RM: 66 0F 3A 44 /r ib"} - ]}, - - {"category": "SSE SIMD CRYPTO_HASH", "ext": "SHA", "data": [ - {"inst": "sha1msg1 xmm, xmm/m128" , "op": "RM: 0F 38 C9 /r"}, - {"inst": "sha1msg2 xmm, xmm/m128" , "op": "RM: 0F 38 CA /r"}, - {"inst": "sha1nexte xmm, xmm/m128" , "op": "RM: 0F 38 C8 /r"}, - {"inst": "sha1rnds4 xmm, xmm/m128, ib/ub" , "op": "RM: 0F 3A CC /r ib"}, - {"inst": "sha256msg1 xmm, xmm/m128" , "op": "RM: 0F 38 CC /r"}, - {"inst": "sha256msg2 xmm, xmm/m128" , "op": "RM: 0F 38 CD /r"}, - {"inst": "sha256rnds2 xmm, xmm/m128, " , "op": "RM: 0F 38 CB /r"} - ]}, - - {"category": "AVX STATE", "ext": "AVX", "data": [ - {"inst": "vldmxcsr R:m32" , "op": "VEX.LZ.0F.WIG AE /2", "io": "MXCSR=W"}, - {"inst": "vstmxcsr W:m32" , "op": "VEX.LZ.0F.WIG AE /3", "io": "MXCSR=R"}, - {"inst": "vzeroall" , "op": "VEX.256.0F.WIG 77", "volatile": true}, - {"inst": "vzeroupper" , "op": "VEX.128.0F.WIG 77", "volatile": true} - ]}, - - {"category": "AVX SCALAR", "ext": "AVX", "data": [ - {"inst": "vaddsd W:xmm, xmm, xmm[63:0]/m64" , "op": "RVM: VEX.LIG.F2.0F.WIG 58 /r"}, - {"inst": "vaddss W:xmm, xmm, xmm[31:0]/m32" , "op": "RVM: VEX.LIG.F3.0F.WIG 58 /r"}, - {"inst": "vcmpsd W:xmm, xmm, xmm[63:0]/m64, ib/ub" , "op": "RVM: VEX.LIG.F2.0F.WIG C2 /r ib"}, - {"inst": "vcmpss W:xmm, xmm, xmm[31:0]/m32, ib/ub" , "op": "RVM: VEX.LIG.F3.0F.WIG C2 /r ib"}, - {"inst": "vcomisd R:xmm[63:0], xmm[63:0]/m64" , "op": "RM: VEX.LIG.66.0F.WIG 2F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, - {"inst": "vcomiss R:xmm[31:0], xmm[31:0]/m32" , "op": "RM: VEX.LIG.0F.WIG 2F /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, - {"inst": "vcvtsd2si W:r32, xmm[63:0]/m64" , "op": "RM: VEX.LIG.F2.0F.W0 2D /r"}, - {"inst": "vcvtsd2si W:r64, xmm[63:0]/m64" , "op": "RM: VEX.LIG.F2.0F.W1 2D /r"}, - {"inst": "vcvtsd2ss W:xmm, xmm[127:32], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.F2.0F.WIG 5A /r"}, - {"inst": "vcvtsi2sd W:xmm, xmm[127:64], r32/m32" , "op": "RVM: VEX.LIG.F2.0F.W0 2A /r"}, - {"inst": "vcvtsi2sd W:xmm, xmm[127:64], r64/m64" , "op": "RVM: VEX.LIG.F2.0F.W1 2A /r"}, - {"inst": "vcvtsi2ss W:xmm, xmm[127:32], r32/m32" , "op": "RVM: VEX.LIG.F3.0F.W0 2A /r"}, - {"inst": "vcvtsi2ss W:xmm, xmm[127:32], r64/m64" , "op": "RVM: VEX.LIG.F3.0F.W1 2A /r"}, - {"inst": "vcvtss2sd W:xmm, xmm[127:64], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.F3.0F.WIG 5A /r"}, - {"inst": "vcvtss2si W:r32, xmm[31:0]/m32" , "op": "RM: VEX.LIG.F3.0F.W0 2D /r"}, - {"inst": "vcvtss2si W:r64, xmm[31:0]/m32" , "op": "RM: VEX.LIG.F3.0F.W1 2D /r"}, - {"inst": "vcvttsd2si W:r32, xmm[63:0]/m64" , "op": "RM: VEX.LIG.F2.0F.W0 2C /r"}, - {"inst": "vcvttsd2si W:r64, xmm[63:0]/m64" , "op": "RM: VEX.LIG.F2.0F.W1 2C /r"}, - {"inst": "vcvttss2si W:r32, xmm[31:0]/m32" , "op": "RM: VEX.LIG.F3.0F.W0 2C /r"}, - {"inst": "vcvttss2si W:r64, xmm[31:0]/m32" , "op": "RM: VEX.LIG.F3.0F.W1 2C /r"}, - {"inst": "vdivsd W:xmm, xmm, xmm[63:0]/m64" , "op": "RVM: VEX.LIG.F2.0F.WIG 5E /r"}, - {"inst": "vdivss W:xmm, xmm, xmm[31:0]/m32" , "op": "RVM: VEX.LIG.F3.0F.WIG 5E /r"}, - {"inst": "vmaxsd W:xmm, xmm, xmm[63:0]/m64" , "op": "RVM: VEX.LIG.F2.0F.WIG 5F /r"}, - {"inst": "vmaxss W:xmm, xmm, xmm[31:0]/m32" , "op": "RVM: VEX.LIG.F3.0F.WIG 5F /r"}, - {"inst": "vminsd W:xmm, xmm, xmm[63:0]/m64" , "op": "RVM: VEX.LIG.F2.0F.WIG 5D /r"}, - {"inst": "vminss W:xmm, xmm, xmm[31:0]/m32" , "op": "RVM: VEX.LIG.F3.0F.WIG 5D /r"}, - {"inst": "vmovsd W:m64, xmm[63:0]" , "op": "MR: VEX.LIG.F2.0F.WIG 11 /r"}, - {"inst": "vmovsd W:xmm[63:0], m64" , "op": "RM: VEX.LIG.F2.0F.WIG 10 /r"}, - {"inst": "vmovsd W:xmm, xmm[127:64], xmm[63:0]" , "op": "MVR: VEX.LIG.F2.0F.WIG 11 /r"}, - {"inst": "vmovsd W:xmm, xmm[127:64], xmm[63:0]" , "op": "RVM: VEX.LIG.F2.0F.WIG 10 /r"}, - {"inst": "vmovss W:m32, xmm[31:0]" , "op": "MR: VEX.LIG.F3.0F.WIG 11 /r"}, - {"inst": "vmovss W:xmm[31:0], m32" , "op": "RM: VEX.LIG.F3.0F.WIG 10 /r"}, - {"inst": "vmovss W:xmm, xmm[127:32], xmm[31:0]" , "op": "MVR: VEX.LIG.F3.0F.WIG 11 /r"}, - {"inst": "vmovss W:xmm, xmm[127:32], xmm[31:0]" , "op": "RVM: VEX.LIG.F3.0F.WIG 10 /r"}, - {"inst": "vmulsd W:xmm, xmm, xmm[63:0]/m64" , "op": "RVM: VEX.LIG.F2.0F.WIG 59 /r"}, - {"inst": "vmulss W:xmm, xmm, xmm[31:0]/m32" , "op": "RVM: VEX.LIG.F3.0F.WIG 59 /r"}, - {"inst": "vrcpss W:xmm, xmm[127:32], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.F3.0F.WIG 53 /r"}, - {"inst": "vroundsd W:xmm, xmm[127:64], xmm[63:0]/m64, ib/ub" , "op": "RVM: VEX.LIG.66.0F3A.WIG 0B /r ib"}, - {"inst": "vroundss W:xmm, xmm[127:32], xmm[31:0]/m32, ib/ub" , "op": "RVM: VEX.LIG.66.0F3A.WIG 0A /r ib"}, - {"inst": "vrsqrtss W:xmm, xmm[127:32], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.F3.0F.WIG 52 /r"}, - {"inst": "vsqrtsd W:xmm, xmm[127:64], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.F2.0F.WIG 51 /r"}, - {"inst": "vsqrtss W:xmm, xmm[127:32], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.F3.0F.WIG 51 /r"}, - {"inst": "vsubsd W:xmm, xmm, xmm[63:0]/m64" , "op": "RVM: VEX.LIG.F2.0F.WIG 5C /r"}, - {"inst": "vsubss W:xmm, xmm, xmm[31:0]/m32" , "op": "RVM: VEX.LIG.F3.0F.WIG 5C /r"}, - {"inst": "vucomisd R:xmm[63:0], xmm[63:0]/m64" , "op": "RM: VEX.LIG.66.0F.WIG 2E /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, - {"inst": "vucomiss R:xmm[31:0], xmm[31:0]/m32" , "op": "RM: VEX.LIG.0F.WIG 2E /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX", "data": [ - {"inst": "vaddpd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 58 /r"}, - {"inst": "vaddpd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 58 /r"}, - {"inst": "vaddps W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.0F.WIG 58 /r"}, - {"inst": "vaddps W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.0F.WIG 58 /r"}, - {"inst": "vaddsubpd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG D0 /r"}, - {"inst": "vaddsubpd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG D0 /r"}, - {"inst": "vaddsubps W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.F2.0F.WIG D0 /r"}, - {"inst": "vaddsubps W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.F2.0F.WIG D0 /r"}, - {"inst": "vandnpd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 55 /r"}, - {"inst": "vandnpd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 55 /r"}, - {"inst": "vandnps W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.0F.WIG 55 /r"}, - {"inst": "vandnps W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.0F.WIG 55 /r"}, - {"inst": "vandpd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 54 /r"}, - {"inst": "vandpd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 54 /r"}, - {"inst": "vandps W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.0F.WIG 54 /r"}, - {"inst": "vandps W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.0F.WIG 54 /r"}, - {"inst": "vblendpd W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.WIG 0D /r ib"}, - {"inst": "vblendpd W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.WIG 0D /r ib"}, - {"inst": "vblendps W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.WIG 0C /r ib"}, - {"inst": "vblendps W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.WIG 0C /r ib"}, - {"inst": "vblendvpd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 4B /r /is4"}, - {"inst": "vblendvpd W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 4B /r /is4"}, - {"inst": "vblendvps W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 4A /r /is4"}, - {"inst": "vblendvps W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 4A /r /is4"}, - {"inst": "vbroadcastf128 W:ymm, m128" , "op": "RM: VEX.256.66.0F38.W0 1A /r"}, - {"inst": "vbroadcastsd W:ymm, m64" , "op": "RM: VEX.256.66.0F38.W0 19 /r"}, - {"inst": "vbroadcastss W:xmm, m32" , "op": "RM: VEX.128.66.0F38.W0 18 /r"}, - {"inst": "vbroadcastss W:ymm, m32" , "op": "RM: VEX.256.66.0F38.W0 18 /r"}, - {"inst": "vcmppd W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F.WIG C2 /r ib"}, - {"inst": "vcmppd W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F.WIG C2 /r ib"}, - {"inst": "vcmpps W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.0F.WIG C2 /r ib"}, - {"inst": "vcmpps W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.0F.WIG C2 /r ib"}, - {"inst": "vcvtdq2pd W:xmm, xmm[63:0]/m64" , "op": "RM: VEX.128.F3.0F.WIG E6 /r"}, - {"inst": "vcvtdq2pd W:ymm, xmm/m128" , "op": "RM: VEX.256.F3.0F.WIG E6 /r"}, - {"inst": "vcvtdq2ps W:xmm, xmm/m128" , "op": "RM: VEX.128.0F.WIG 5B /r"}, - {"inst": "vcvtdq2ps W:ymm, ymm/m256" , "op": "RM: VEX.256.0F.WIG 5B /r"}, - {"inst": "vcvtpd2dq W:xmm[63:0], xmm/m128" , "op": "RM: VEX.128.F2.0F.WIG E6 /r"}, - {"inst": "vcvtpd2dq W:xmm, ymm/m256" , "op": "RM: VEX.256.F2.0F.WIG E6 /r"}, - {"inst": "vcvtpd2ps W:xmm[63:0], xmm/m128" , "op": "RM: VEX.128.66.0F.WIG 5A /r"}, - {"inst": "vcvtpd2ps W:xmm, ymm/m256" , "op": "RM: VEX.256.66.0F.WIG 5A /r"}, - {"inst": "vcvtps2dq W:xmm, xmm/m128" , "op": "RM: VEX.128.66.0F.WIG 5B /r"}, - {"inst": "vcvtps2dq W:ymm, ymm/m256" , "op": "RM: VEX.256.66.0F.WIG 5B /r"}, - {"inst": "vcvtps2pd W:xmm, xmm[63:0]/m64" , "op": "RM: VEX.128.0F.WIG 5A /r"}, - {"inst": "vcvtps2pd W:ymm, xmm/m128" , "op": "RM: VEX.256.0F.WIG 5A /r"}, - {"inst": "vcvttpd2dq W:xmm[63:0], xmm/m128" , "op": "RM: VEX.128.66.0F.WIG E6 /r"}, - {"inst": "vcvttpd2dq W:xmm, ymm/m256" , "op": "RM: VEX.256.66.0F.WIG E6 /r"}, - {"inst": "vcvttps2dq W:xmm, xmm/m128" , "op": "RM: VEX.128.F3.0F.WIG 5B /r"}, - {"inst": "vcvttps2dq W:ymm, ymm/m256" , "op": "RM: VEX.256.F3.0F.WIG 5B /r"}, - {"inst": "vdivpd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 5E /r"}, - {"inst": "vdivpd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 5E /r"}, - {"inst": "vdivps W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.0F.WIG 5E /r"}, - {"inst": "vdivps W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.0F.WIG 5E /r"}, - {"inst": "vdppd W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.WIG 41 /r ib"}, - {"inst": "vdpps W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.WIG 40 /r ib"}, - {"inst": "vdpps W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.WIG 40 /r ib"}, - {"inst": "vextractps W:r32[31:0]/m32, xmm, ib/ub" , "op": "MR: VEX.128.66.0F3A.WIG 17 /r ib"}, - {"inst": "vextractf128 W:xmm/m128, ymm, ib/ub" , "op": "MR: VEX.256.66.0F3A.W0 19 /r ib"}, - {"inst": "vhaddpd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 7C /r"}, - {"inst": "vhaddpd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 7C /r"}, - {"inst": "vhaddps W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.F2.0F.WIG 7C /r"}, - {"inst": "vhaddps W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.F2.0F.WIG 7C /r"}, - {"inst": "vhsubpd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 7D /r"}, - {"inst": "vhsubpd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 7D /r"}, - {"inst": "vhsubps W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.F2.0F.WIG 7D /r"}, - {"inst": "vhsubps W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.F2.0F.WIG 7D /r"}, - {"inst": "vinsertf128 W:ymm, ymm, xmm/m128, ib/ub" , "op": "RVM: VEX.256.66.0F3A.W0 18 /r ib"}, - {"inst": "vinsertps W:xmm, xmm, xmm[31:0]/m32, ib/ub" , "op": "RVM: VEX.128.66.0F3A.WIG 21 /r ib"}, - {"inst": "vlddqu W:xmm, m128" , "op": "RM: VEX.128.F2.0F.WIG F0 /r"}, - {"inst": "vlddqu W:ymm, m256" , "op": "RM: VEX.256.F2.0F.WIG F0 /r"}, - {"inst": "vmaskmovdqu R:xmm, xmm, X:" , "op": "RM: VEX.128.66.0F.WIG F7 /r"}, - {"inst": "vmaskmovpd X:m128, xmm, xmm" , "op": "MVR: VEX.128.66.0F38.W0 2F /r"}, - {"inst": "vmaskmovpd X:m256, ymm, ymm" , "op": "MVR: VEX.256.66.0F38.W0 2F /r"}, - {"inst": "vmaskmovpd W:xmm, xmm, m128" , "op": "RVM: VEX.128.66.0F38.W0 2D /r"}, - {"inst": "vmaskmovpd W:ymm, ymm, m256" , "op": "RVM: VEX.256.66.0F38.W0 2D /r"}, - {"inst": "vmaskmovps X:m128, xmm, xmm" , "op": "MVR: VEX.128.66.0F38.W0 2E /r"}, - {"inst": "vmaskmovps X:m256, ymm, ymm" , "op": "MVR: VEX.256.66.0F38.W0 2E /r"}, - {"inst": "vmaskmovps W:xmm, xmm, m128" , "op": "RVM: VEX.128.66.0F38.W0 2C /r"}, - {"inst": "vmaskmovps W:ymm, ymm, m256" , "op": "RVM: VEX.256.66.0F38.W0 2C /r"}, - {"inst": "vmaxpd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 5F /r"}, - {"inst": "vmaxpd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 5F /r"}, - {"inst": "vmaxps W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.0F.WIG 5F /r"}, - {"inst": "vmaxps W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.0F.WIG 5F /r"}, - {"inst": "vminpd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 5D /r"}, - {"inst": "vminpd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 5D /r"}, - {"inst": "vminps W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.0F.WIG 5D /r"}, - {"inst": "vminps W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.0F.WIG 5D /r"}, - {"inst": "vmovapd W:xmm, xmm/m128" , "op": "RM: VEX.128.66.0F.WIG 28 /r"}, - {"inst": "vmovapd W:xmm/m128, xmm" , "op": "MR: VEX.128.66.0F.WIG 29 /r"}, - {"inst": "vmovapd W:ymm, ymm/m256" , "op": "RM: VEX.256.66.0F.WIG 28 /r"}, - {"inst": "vmovapd W:ymm/m256, ymm" , "op": "MR: VEX.256.66.0F.WIG 29 /r"}, - {"inst": "vmovaps W:xmm, xmm/m128" , "op": "RM: VEX.128.0F.WIG 28 /r"}, - {"inst": "vmovaps W:xmm/m128, xmm" , "op": "MR: VEX.128.0F.WIG 29 /r"}, - {"inst": "vmovaps W:ymm, ymm/m256" , "op": "RM: VEX.256.0F.WIG 28 /r"}, - {"inst": "vmovaps W:ymm/m256, ymm" , "op": "MR: VEX.256.0F.WIG 29 /r"}, - {"inst": "vmovd W:r32[31:0]/m32, xmm[31:0]" , "op": "MR: VEX.128.66.0F.W0 7E /r"}, - {"inst": "vmovd W:xmm[31:0], r32[31:0]/m32" , "op": "RM: VEX.128.66.0F.W0 6E /r"}, - {"inst": "vmovddup W:xmm, xmm[63:0]/m64" , "op": "RM: VEX.128.F2.0F.WIG 12 /r"}, - {"inst": "vmovddup W:ymm, ymm/m256" , "op": "RM: VEX.256.F2.0F.WIG 12 /r"}, - {"inst": "vmovdqa W:xmm, xmm/m128" , "op": "RM: VEX.128.66.0F.WIG 6F /r"}, - {"inst": "vmovdqa W:xmm/m128, xmm" , "op": "MR: VEX.128.66.0F.WIG 7F /r"}, - {"inst": "vmovdqa W:ymm, ymm/m256" , "op": "RM: VEX.256.66.0F.WIG 6F /r"}, - {"inst": "vmovdqa W:ymm/m256, ymm" , "op": "MR: VEX.256.66.0F.WIG 7F /r"}, - {"inst": "vmovdqu W:xmm, xmm/m128" , "op": "RM: VEX.128.F3.0F.WIG 6F /r"}, - {"inst": "vmovdqu W:xmm/m128, xmm" , "op": "MR: VEX.128.F3.0F.WIG 7F /r"}, - {"inst": "vmovdqu W:ymm, ymm/m256" , "op": "RM: VEX.256.F3.0F.WIG 6F /r"}, - {"inst": "vmovdqu W:ymm/m256, ymm" , "op": "MR: VEX.256.F3.0F.WIG 7F /r"}, - {"inst": "vmovhlps W:xmm, xmm[127:64], xmm[127:64]" , "op": "RVM: VEX.128.0F.WIG 12 /r"}, - {"inst": "vmovhpd W:m64, xmm[127:64]" , "op": "MR: VEX.128.66.0F.WIG 17 /r"}, - {"inst": "vmovhpd W:xmm, xmm[63:0], m64" , "op": "RVM: VEX.128.66.0F.WIG 16 /r"}, - {"inst": "vmovhps W:m64, xmm[127:64]" , "op": "MR: VEX.128.0F.WIG 17 /r"}, - {"inst": "vmovhps W:xmm, xmm[63:0], m64" , "op": "RVM: VEX.128.0F.WIG 16 /r"}, - {"inst": "vmovlhps W:xmm, xmm[63:0], xmm[63:0]" , "op": "RVM: VEX.128.0F.WIG 16 /r"}, - {"inst": "vmovlpd W:m64, xmm[63:0]" , "op": "MR: VEX.128.66.0F.WIG 13 /r"}, - {"inst": "vmovlpd W:xmm, xmm[127:64], m64" , "op": "RVM: VEX.128.66.0F.WIG 12 /r"}, - {"inst": "vmovlps W:m64, xmm[63:0]" , "op": "MR: VEX.128.0F.WIG 13 /r"}, - {"inst": "vmovlps W:xmm, xmm[127:64], m64" , "op": "RVM: VEX.128.0F.WIG 12 /r"}, - {"inst": "vmovmskpd W:r32[1:0], xmm" , "op": "RM: VEX.128.66.0F.WIG 50 /r"}, - {"inst": "vmovmskpd W:r32[3:0], ymm" , "op": "RM: VEX.256.66.0F.WIG 50 /r"}, - {"inst": "vmovmskps W:r32[3:0], xmm" , "op": "RM: VEX.128.0F.WIG 50 /r"}, - {"inst": "vmovmskps W:r32[7:0], ymm" , "op": "RM: VEX.256.0F.WIG 50 /r"}, - {"inst": "vmovntdq W:m128, xmm" , "op": "MR: VEX.128.66.0F.WIG E7 /r"}, - {"inst": "vmovntdq W:m256, ymm" , "op": "MR: VEX.256.66.0F.WIG E7 /r"}, - {"inst": "vmovntdqa W:xmm, m128" , "op": "RM: VEX.128.66.0F38.WIG 2A /r"}, - {"inst": "vmovntpd W:m128, xmm" , "op": "MR: VEX.128.66.0F.WIG 2B /r"}, - {"inst": "vmovntpd W:m256, ymm" , "op": "MR: VEX.256.66.0F.WIG 2B /r"}, - {"inst": "vmovntps W:m128, xmm" , "op": "MR: VEX.128.0F.WIG 2B /r"}, - {"inst": "vmovntps W:m256, ymm" , "op": "MR: VEX.256.0F.WIG 2B /r"}, - {"inst": "vmovq W:r64/m64, xmm[63:0]" , "op": "MR: VEX.128.66.0F.W1 7E /r"}, - {"inst": "vmovq W:xmm[63:0], xmm[63:0]/m64" , "op": "RM: VEX.128.F3.0F.WIG 7E /r"}, - {"inst": "vmovq W:xmm[63:0], r64/m64" , "op": "RM: VEX.128.66.0F.W1 6E /r"}, - {"inst": "vmovq W:xmm[63:0]/m64, xmm[63:0]" , "op": "MR: VEX.128.66.0F.WIG D6 /r"}, - {"inst": "vmovshdup W:xmm, xmm/m128" , "op": "RM: VEX.128.F3.0F.WIG 16 /r"}, - {"inst": "vmovshdup W:ymm, ymm/m256" , "op": "RM: VEX.256.F3.0F.WIG 16 /r"}, - {"inst": "vmovsldup W:xmm, xmm/m128" , "op": "RM: VEX.128.F3.0F.WIG 12 /r"}, - {"inst": "vmovsldup W:ymm, ymm/m256" , "op": "RM: VEX.256.F3.0F.WIG 12 /r"}, - {"inst": "vmovupd W:xmm, xmm/m128" , "op": "RM: VEX.128.0F.WIG 10 /r"}, - {"inst": "vmovupd W:xmm/m128, xmm" , "op": "MR: VEX.128.0F.WIG 11 /r"}, - {"inst": "vmovupd W:ymm, ymm/m256" , "op": "RM: VEX.256.0F.WIG 10 /r"}, - {"inst": "vmovupd W:ymm/m256, ymm" , "op": "MR: VEX.256.0F.WIG 11 /r"}, - {"inst": "vmovups W:xmm, xmm/m128" , "op": "RM: VEX.128.66.0F.WIG 10 /r"}, - {"inst": "vmovups W:xmm/m128, xmm" , "op": "MR: VEX.128.66.0F.WIG 11 /r"}, - {"inst": "vmovups W:ymm, ymm/m256" , "op": "RM: VEX.256.66.0F.WIG 10 /r"}, - {"inst": "vmovups W:ymm/m256, ymm" , "op": "MR: VEX.256.66.0F.WIG 11 /r"}, - {"inst": "vmpsadbw W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.WIG 42 /r ib"}, - {"inst": "vmulpd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 59 /r"}, - {"inst": "vmulpd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 59 /r"}, - {"inst": "vmulps W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.0F.WIG 59 /r"}, - {"inst": "vmulps W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.0F.WIG 59 /r"}, - {"inst": "vorpd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 56 /r"}, - {"inst": "vorpd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 56 /r"}, - {"inst": "vorps W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.0F.WIG 56 /r"}, - {"inst": "vorps W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.0F.WIG 56 /r"}, - {"inst": "vpabsb W:xmm, xmm/m128" , "op": "RM: VEX.128.66.0F38.WIG 1C /r"}, - {"inst": "vpabsd W:xmm, xmm/m128" , "op": "RM: VEX.128.66.0F38.WIG 1E /r"}, - {"inst": "vpabsw W:xmm, xmm/m128" , "op": "RM: VEX.128.66.0F38.WIG 1D /r"}, - {"inst": "vpackssdw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 6B /r"}, - {"inst": "vpacksswb W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 63 /r"}, - {"inst": "vpackusdw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 2B /r"}, - {"inst": "vpackuswb W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 67 /r"}, - {"inst": "vpaddb W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG FC /r"}, - {"inst": "vpaddd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG FE /r"}, - {"inst": "vpaddq W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG D4 /r"}, - {"inst": "vpaddsb W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG EC /r"}, - {"inst": "vpaddsw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG ED /r"}, - {"inst": "vpaddusb W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG DC /r"}, - {"inst": "vpaddusw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG DD /r"}, - {"inst": "vpaddw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG FD /r"}, - {"inst": "vpalignr W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.WIG 0F /r ib"}, - {"inst": "vpand W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG DB /r"}, - {"inst": "vpandn W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG DF /r"}, - {"inst": "vpavgb W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG E0 /r"}, - {"inst": "vpavgw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG E3 /r"}, - {"inst": "vpblendvb W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 4C /r /is4"}, - {"inst": "vpblendw W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.WIG 0E /r ib"}, - {"inst": "vpcmpeqb W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 74 /r"}, - {"inst": "vpcmpeqd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 76 /r"}, - {"inst": "vpcmpeqq W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 29 /r"}, - {"inst": "vpcmpeqw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 75 /r"}, - {"inst": "vpcmpestri R:xmm, xmm/m128, ib/ub, W:,," , "op": "RM: VEX.128.66.0F3A.WIG 61 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, - {"inst": "vpcmpestrm R:xmm, xmm/m128, ib/ub, W:,," , "op": "RM: VEX.128.66.0F3A.WIG 60 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, - {"inst": "vpcmpgtb W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 64 /r"}, - {"inst": "vpcmpgtd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 66 /r"}, - {"inst": "vpcmpgtq W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 37 /r"}, - {"inst": "vpcmpgtw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 65 /r"}, - {"inst": "vpcmpistri R:xmm, xmm/m128, ib/ub, W:" , "op": "RM: VEX.128.66.0F3A.WIG 63 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, - {"inst": "vpcmpistrm R:xmm, xmm/m128, ib/ub, W:" , "op": "RM: VEX.128.66.0F3A.WIG 62 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, - {"inst": "vperm2f128 W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.W0 06 /r ib"}, - {"inst": "vpermilpd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 0D /r"}, - {"inst": "vpermilpd W:xmm, xmm/m128, ib/ub" , "op": "RM: VEX.128.66.0F3A.W0 05 /r ib"}, - {"inst": "vpermilpd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 0D /r"}, - {"inst": "vpermilpd W:ymm, ymm/m256, ib/ub" , "op": "RM: VEX.256.66.0F3A.W0 05 /r ib"}, - {"inst": "vpermilps W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 0C /r"}, - {"inst": "vpermilps W:xmm, xmm/m128, ib/ub" , "op": "RM: VEX.128.66.0F3A.W0 04 /r ib"}, - {"inst": "vpermilps W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 0C /r"}, - {"inst": "vpermilps W:ymm, ymm/m256, ib/ub" , "op": "RM: VEX.256.66.0F3A.W0 04 /r ib"}, - {"inst": "vpextrb W:r32[7:0]/m8, xmm, ib/ub" , "op": "MR: VEX.128.66.0F3A.W0 14 /r ib"}, - {"inst": "vpextrd W:r32/m32, xmm, ib/ub" , "op": "MR: VEX.128.66.0F3A.W0 16 /r ib"}, - {"inst": "vpextrq W:r64/m64, xmm, ib/ub" , "op": "MR: VEX.128.66.0F3A.W1 16 /r ib"}, - {"inst": "vpextrw W:r32[15:0], xmm, ib/ub" , "op": "RM: VEX.128.66.0F.W0 C5 /r ib"}, - {"inst": "vpextrw W:r32[15:0]/m16, xmm, ib/ub" , "op": "MR: VEX.128.66.0F3A.W0 15 /r ib"}, - {"inst": "vphaddd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 02 /r"}, - {"inst": "vphaddsw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 03 /r"}, - {"inst": "vphaddw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 01 /r"}, - {"inst": "vphminposuw W:xmm[18:0], xmm/m128" , "op": "RM: VEX.128.66.0F38.WIG 41 /r"}, - {"inst": "vphsubd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 06 /r"}, - {"inst": "vphsubsw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 07 /r"}, - {"inst": "vphsubw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 05 /r"}, - {"inst": "vpinsrb W:xmm, xmm, r32[7:0]/m8, ib/ub" , "op": "RVM: VEX.128.66.0F3A.W0 20 /r ib"}, - {"inst": "vpinsrd W:xmm, xmm, r32/m32, ib/ub" , "op": "RVM: VEX.128.66.0F3A.W0 22 /r ib"}, - {"inst": "vpinsrq W:xmm, xmm, r64/m64, ib/ub" , "op": "RVM: VEX.128.66.0F3A.W1 22 /r ib"}, - {"inst": "vpinsrw W:xmm, xmm, r32[15:0]/m16, ib/ub" , "op": "RVM: VEX.128.66.0F.W0 C4 /r ib"}, - {"inst": "vpmaddubsw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 04 /r"}, - {"inst": "vpmaddwd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG F5 /r"}, - {"inst": "vpmaxsb W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 3C /r"}, - {"inst": "vpmaxsd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 3D /r"}, - {"inst": "vpmaxsw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG EE /r"}, - {"inst": "vpmaxub W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG DE /r"}, - {"inst": "vpmaxud W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 3F /r"}, - {"inst": "vpmaxuw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 3E /r"}, - {"inst": "vpminsb W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 38 /r"}, - {"inst": "vpminsd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 39 /r"}, - {"inst": "vpminsw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG EA /r"}, - {"inst": "vpminub W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG DA /r"}, - {"inst": "vpminud W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 3B /r"}, - {"inst": "vpminuw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 3A /r"}, - {"inst": "vpmovmskb W:r32[15:0], xmm" , "op": "RVM: VEX.128.66.0F.WIG D7 /r"}, - {"inst": "vpmovsxwq W:xmm, xmm[31:0]/m32" , "op": "RM: VEX.128.66.0F38.WIG 24 /r"}, - {"inst": "vpmovsxbd W:xmm, xmm[31:0]/m32" , "op": "RM: VEX.128.66.0F38.WIG 21 /r"}, - {"inst": "vpmovsxbq W:xmm, xmm[15:0]/m16" , "op": "RM: VEX.128.66.0F38.WIG 22 /r"}, - {"inst": "vpmovsxbw W:xmm, xmm[63:0]/m64" , "op": "RM: VEX.128.66.0F38.WIG 20 /r"}, - {"inst": "vpmovsxdq W:xmm, xmm[63:0]/m64" , "op": "RM: VEX.128.66.0F38.WIG 25 /r"}, - {"inst": "vpmovsxwd W:xmm, xmm[63:0]/m64" , "op": "RM: VEX.128.66.0F38.WIG 23 /r"}, - {"inst": "vpmovzxbd W:xmm, xmm[31:0]/m32" , "op": "RM: VEX.128.66.0F38.WIG 31 /r"}, - {"inst": "vpmovzxbq W:xmm, xmm[15:0]/m16" , "op": "RM: VEX.128.66.0F38.WIG 32 /r"}, - {"inst": "vpmovzxbw W:xmm, xmm[63:0]/m64" , "op": "RM: VEX.128.66.0F38.WIG 30 /r"}, - {"inst": "vpmovzxdq W:xmm, xmm[63:0]/m64" , "op": "RM: VEX.128.66.0F38.WIG 35 /r"}, - {"inst": "vpmovzxwd W:xmm, xmm[63:0]/m64" , "op": "RM: VEX.128.66.0F38.WIG 33 /r"}, - {"inst": "vpmovzxwq W:xmm, xmm[31:0]/m32" , "op": "RM: VEX.128.66.0F38.WIG 34 /r"}, - {"inst": "vpmuldq W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 28 /r"}, - {"inst": "vpmulhrsw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 0B /r"}, - {"inst": "vpmulhuw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG E4 /r"}, - {"inst": "vpmulhw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG E5 /r"}, - {"inst": "vpmulld W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 40 /r"}, - {"inst": "vpmullw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG D5 /r"}, - {"inst": "vpmuludq W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG F4 /r"}, - {"inst": "vpor W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG EB /r"}, - {"inst": "vpsadbw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG F6 /r"}, - {"inst": "vpshufb W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 00 /r"}, - {"inst": "vpshufd W:xmm, xmm/m128, ib/ub" , "op": "RM: VEX.128.66.0F.WIG 70 /r ib"}, - {"inst": "vpshufhw W:xmm, xmm/m128, ib/ub" , "op": "RM: VEX.128.F3.0F.WIG 70 /r ib"}, - {"inst": "vpshuflw W:xmm, xmm/m128, ib/ub" , "op": "RM: VEX.128.F2.0F.WIG 70 /r ib"}, - {"inst": "vpsignb W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 08 /r"}, - {"inst": "vpsignd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 0A /r"}, - {"inst": "vpsignw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG 09 /r"}, - {"inst": "vpslld W:xmm, xmm, ib/ub" , "op": "VM: VEX.128.66.0F.WIG 72 /6 ib"}, - {"inst": "vpslld W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG F2 /r"}, - {"inst": "vpslldq W:xmm, xmm, ib/ub" , "op": "VM: VEX.128.66.0F.WIG 73 /7 ib"}, - {"inst": "vpsllq W:xmm, xmm, ib/ub" , "op": "VM: VEX.128.66.0F.WIG 73 /6 ib"}, - {"inst": "vpsllq W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG F3 /r"}, - {"inst": "vpsllw W:xmm, xmm, ib/ub" , "op": "VM: VEX.128.66.0F.WIG 71 /6 ib"}, - {"inst": "vpsllw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG F1 /r"}, - {"inst": "vpsrad W:xmm, xmm, ib/ub" , "op": "VM: VEX.128.66.0F.WIG 72 /4 ib"}, - {"inst": "vpsrad W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG E2 /r"}, - {"inst": "vpsraw W:xmm, xmm, ib/ub" , "op": "VM: VEX.128.66.0F.WIG 71 /4 ib"}, - {"inst": "vpsraw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG E1 /r"}, - {"inst": "vpsrld W:xmm, xmm, ib/ub" , "op": "VM: VEX.128.66.0F.WIG 72 /2 ib"}, - {"inst": "vpsrld W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG D2 /r"}, - {"inst": "vpsrldq W:xmm, xmm, ib/ub" , "op": "VM: VEX.128.66.0F.WIG 73 /3 ib"}, - {"inst": "vpsrlq W:xmm, xmm, ib/ub" , "op": "VM: VEX.128.66.0F.WIG 73 /2 ib"}, - {"inst": "vpsrlq W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG D3 /r"}, - {"inst": "vpsrlw W:xmm, xmm, ib/ub" , "op": "VM: VEX.128.66.0F.WIG 71 /2 ib"}, - {"inst": "vpsrlw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG D1 /r"}, - {"inst": "vpsubb W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG F8 /r"}, - {"inst": "vpsubd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG FA /r"}, - {"inst": "vpsubq W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG FB /r"}, - {"inst": "vpsubsb W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG E8 /r"}, - {"inst": "vpsubsw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG E9 /r"}, - {"inst": "vpsubusb W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG D8 /r"}, - {"inst": "vpsubusw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG D9 /r"}, - {"inst": "vpsubw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG F9 /r"}, - {"inst": "vptest R:~xmm, ~xmm/m128" , "op": "RM: VEX.128.66.0F38.WIG 17 /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "vptest R:~ymm, ~ymm/m256" , "op": "RM: VEX.256.66.0F38.WIG 17 /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "vpunpckhbw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 68 /r"}, - {"inst": "vpunpckhdq W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 6A /r"}, - {"inst": "vpunpckhqdq W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 6D /r"}, - {"inst": "vpunpckhwd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 69 /r"}, - {"inst": "vpunpcklbw W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 60 /r"}, - {"inst": "vpunpckldq W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 62 /r"}, - {"inst": "vpunpcklqdq W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 6C /r"}, - {"inst": "vpunpcklwd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 61 /r"}, - {"inst": "vpxor W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG EF /r"}, - {"inst": "vrcpps W:xmm, xmm/m128" , "op": "RM: VEX.128.0F.WIG 53 /r"}, - {"inst": "vrcpps W:ymm, ymm/m256" , "op": "RM: VEX.256.0F.WIG 53 /r"}, - {"inst": "vroundpd W:xmm, xmm/m128, ib/ub" , "op": "RM: VEX.128.66.0F3A.WIG 09 /r ib"}, - {"inst": "vroundpd W:ymm, ymm/m256, ib/ub" , "op": "RM: VEX.256.66.0F3A.WIG 09 /r ib"}, - {"inst": "vroundps W:xmm, xmm/m128, ib/ub" , "op": "RM: VEX.128.66.0F3A.WIG 08 /r ib"}, - {"inst": "vroundps W:ymm, ymm/m256, ib/ub" , "op": "RM: VEX.256.66.0F3A.WIG 08 /r ib"}, - {"inst": "vrsqrtps W:xmm, xmm/m128" , "op": "RM: VEX.128.0F.WIG 52 /r"}, - {"inst": "vrsqrtps W:ymm, ymm/m256" , "op": "RM: VEX.256.0F.WIG 52 /r"}, - {"inst": "vshufpd W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F.WIG C6 /r ib"}, - {"inst": "vshufpd W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F.WIG C6 /r ib"}, - {"inst": "vshufps W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.0F.WIG C6 /r ib"}, - {"inst": "vshufps W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.0F.WIG C6 /r ib"}, - {"inst": "vsqrtpd W:xmm, xmm/m128" , "op": "RM: VEX.128.66.0F.WIG 51 /r"}, - {"inst": "vsqrtpd W:ymm, ymm/m256" , "op": "RM: VEX.256.66.0F.WIG 51 /r"}, - {"inst": "vsqrtps W:xmm, xmm/m128" , "op": "RM: VEX.128.0F.WIG 51 /r"}, - {"inst": "vsqrtps W:ymm, ymm/m256" , "op": "RM: VEX.256.0F.WIG 51 /r"}, - {"inst": "vsubpd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 5C /r"}, - {"inst": "vsubpd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 5C /r"}, - {"inst": "vsubps W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.0F.WIG 5C /r"}, - {"inst": "vsubps W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.0F.WIG 5C /r"}, - {"inst": "vtestpd R:~xmm, ~xmm/m128" , "op": "RM: VEX.128.66.0F38.W0 0F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "vtestpd R:~ymm, ~ymm/m256" , "op": "RM: VEX.256.66.0F38.W0 0F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "vtestps R:~xmm, ~xmm/m128" , "op": "RM: VEX.128.66.0F38.W0 0E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "vtestps R:~ymm, ~ymm/m256" , "op": "RM: VEX.256.66.0F38.W0 0E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "vunpckhpd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 15 /r"}, - {"inst": "vunpckhpd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 15 /r"}, - {"inst": "vunpckhps W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.0F.WIG 15 /r"}, - {"inst": "vunpckhps W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.0F.WIG 15 /r"}, - {"inst": "vunpcklpd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 14 /r"}, - {"inst": "vunpcklpd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 14 /r"}, - {"inst": "vunpcklps W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.0F.WIG 14 /r"}, - {"inst": "vunpcklps W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.0F.WIG 14 /r"}, - {"inst": "vxorpd W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.66.0F.WIG 57 /r"}, - {"inst": "vxorpd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 57 /r"}, - {"inst": "vxorps W:xmm, ~xmm, ~xmm/m128" , "op": "RVM: VEX.128.0F.WIG 57 /r"}, - {"inst": "vxorps W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.0F.WIG 57 /r"} - ]}, - - {"category": "AVX SIMD CRYPTO_HASH", "ext": "AVX AESNI", "data": [ - {"inst": "vaesdec W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG DE /r"}, - {"inst": "vaesdeclast W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG DF /r"}, - {"inst": "vaesenc W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG DC /r"}, - {"inst": "vaesenclast W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG DD /r"}, - {"inst": "vaesimc W:xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.WIG DB /r"}, - {"inst": "vaeskeygenassist W:xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.WIG DF /r ib"} - ]}, - - {"category": "AVX SIMD CRYPTO_HASH", "ext": "VAES", "data": [ - {"inst": "vaesdec W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG DE /r"}, - {"inst": "vaesdeclast W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG DF /r"}, - {"inst": "vaesenc W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG DC /r"}, - {"inst": "vaesenclast W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG DD /r"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX GFNI", "data": [ - {"inst": "vgf2p8affineinvqb W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.W1 CF /r ib"}, - {"inst": "vgf2p8affineinvqb W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.W1 CF /r ib"}, - {"inst": "vgf2p8affineqb W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.W1 CE /r ib"}, - {"inst": "vgf2p8affineqb W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.W1 CE /r ib"}, - {"inst": "vgf2p8mulb W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 CF /r"}, - {"inst": "vgf2p8mulb W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 CF /r"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX PCLMULQDQ", "data": [ - {"inst": "vpclmulqdq W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.WIG 44 /r ib"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX2", "data": [ - {"inst": "vbroadcasti128 W:ymm, m128" , "op": "RM: VEX.256.66.0F38.W0 5A /r"}, - {"inst": "vbroadcastsd W:ymm, xmm[63:0]" , "op": "RM: VEX.256.66.0F38.W0 19 /r"}, - {"inst": "vbroadcastss W:xmm, xmm[31:0]" , "op": "RM: VEX.128.66.0F38.W0 18 /r"}, - {"inst": "vbroadcastss W:ymm, xmm[31:0]" , "op": "RM: VEX.256.66.0F38.W0 18 /r"}, - {"inst": "vextracti128 W:xmm/m128, ymm, ib/ub" , "op": "MR: VEX.256.66.0F3A.W0 39 /r ib"}, - {"inst": "vgatherdpd X:xmm, vm32x, X:xmm" , "op": "RMV: VEX.128.66.0F38.W1 92 /r"}, - {"inst": "vgatherdpd X:ymm, vm32x, X:ymm" , "op": "RMV: VEX.256.66.0F38.W1 92 /r"}, - {"inst": "vgatherdps X:xmm, vm32x, X:xmm" , "op": "RMV: VEX.128.66.0F38.W0 92 /r"}, - {"inst": "vgatherdps X:ymm, vm32y, X:ymm" , "op": "RMV: VEX.256.66.0F38.W0 92 /r"}, - {"inst": "vgatherqpd X:xmm, vm64x, X:xmm" , "op": "RMV: VEX.128.66.0F38.W1 93 /r"}, - {"inst": "vgatherqpd X:ymm, vm64y, X:ymm" , "op": "RMV: VEX.256.66.0F38.W1 93 /r"}, - {"inst": "vgatherqps X:xmm, vm64x, X:xmm" , "op": "RMV: VEX.128.66.0F38.W0 93 /r"}, - {"inst": "vgatherqps X:xmm, vm64y, X:xmm" , "op": "RMV: VEX.256.66.0F38.W0 93 /r"}, - {"inst": "vinserti128 W:ymm, ymm, xmm/m128, ib/ub" , "op": "RVM: VEX.256.66.0F3A.W0 38 /r ib"}, - {"inst": "vmovntdqa W:ymm, m256" , "op": "RM: VEX.256.66.0F38.WIG 2A /r"}, - {"inst": "vmpsadbw W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.WIG 42 /r ib"}, - {"inst": "vpabsb W:ymm, ymm/m256" , "op": "RM: VEX.256.66.0F38.WIG 1C /r"}, - {"inst": "vpabsd W:ymm, ymm/m256" , "op": "RM: VEX.256.66.0F38.WIG 1E /r"}, - {"inst": "vpabsw W:ymm, ymm/m256" , "op": "RM: VEX.256.66.0F38.WIG 1D /r"}, - {"inst": "vpackssdw W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 6B /r"}, - {"inst": "vpacksswb W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 63 /r"}, - {"inst": "vpackusdw W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 2B /r"}, - {"inst": "vpackuswb W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 67 /r"}, - {"inst": "vpaddb W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG FC /r"}, - {"inst": "vpaddd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG FE /r"}, - {"inst": "vpaddq W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG D4 /r"}, - {"inst": "vpaddsb W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG EC /r"}, - {"inst": "vpaddsw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG ED /r"}, - {"inst": "vpaddusb W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG DC /r"}, - {"inst": "vpaddusw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG DD /r"}, - {"inst": "vpaddw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG FD /r"}, - {"inst": "vpalignr W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.WIG 0F /r ib"}, - {"inst": "vpand W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG DB /r"}, - {"inst": "vpandn W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG DF /r"}, - {"inst": "vpavgb W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG E0 /r"}, - {"inst": "vpavgw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG E3 /r"}, - {"inst": "vpblendd W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.W0 02 /r ib"}, - {"inst": "vpblendd W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.W0 02 /r ib"}, - {"inst": "vpblendvb W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 4C /r /is4"}, - {"inst": "vpblendw W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.WIG 0E /r ib"}, - {"inst": "vpbroadcastb W:xmm, xmm[7:0]/m8" , "op": "RM: VEX.128.66.0F38.W0 78 /r"}, - {"inst": "vpbroadcastb W:ymm, xmm[7:0]/m8" , "op": "RM: VEX.256.66.0F38.W0 78 /r"}, - {"inst": "vpbroadcastd W:xmm, xmm[31:0]/m32" , "op": "RM: VEX.128.66.0F38.W0 58 /r"}, - {"inst": "vpbroadcastd W:ymm, xmm[31:0]/m32" , "op": "RM: VEX.256.66.0F38.W0 58 /r"}, - {"inst": "vpbroadcastq W:xmm, xmm[63:0]/m64" , "op": "RM: VEX.128.66.0F38.W0 59 /r"}, - {"inst": "vpbroadcastq W:ymm, xmm[63:0]/m64" , "op": "RM: VEX.256.66.0F38.W0 59 /r"}, - {"inst": "vpbroadcastw W:xmm, xmm[15:0]/m16" , "op": "RM: VEX.128.66.0F38.W0 79 /r"}, - {"inst": "vpbroadcastw W:ymm, xmm[15:0]/m16" , "op": "RM: VEX.256.66.0F38.W0 79 /r"}, - {"inst": "vpcmpeqb W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 74 /r"}, - {"inst": "vpcmpeqd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 76 /r"}, - {"inst": "vpcmpeqq W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 29 /r"}, - {"inst": "vpcmpeqw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 75 /r"}, - {"inst": "vpcmpgtb W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 64 /r"}, - {"inst": "vpcmpgtd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 66 /r"}, - {"inst": "vpcmpgtq W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 37 /r"}, - {"inst": "vpcmpgtw W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 65 /r"}, - {"inst": "vperm2i128 W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.W0 46 /r ib"}, - {"inst": "vpermd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 36 /r"}, - {"inst": "vpermpd W:ymm, ymm/m256, ib/ub" , "op": "RM: VEX.256.66.0F3A.W1 01 /r ib"}, - {"inst": "vpermps W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 16 /r"}, - {"inst": "vpermq W:ymm, ymm/m256, ib/ub" , "op": "RM: VEX.256.66.0F3A.W1 00 /r ib"}, - {"inst": "vpgatherdd X:xmm, vm32x, X:xmm" , "op": "RMV: VEX.128.66.0F38.W0 90 /r"}, - {"inst": "vpgatherdd X:ymm, vm32y, X:ymm" , "op": "RMV: VEX.256.66.0F38.W0 90 /r"}, - {"inst": "vpgatherdq X:xmm, vm32x, X:xmm" , "op": "RMV: VEX.128.66.0F38.W1 90 /r"}, - {"inst": "vpgatherdq X:ymm, vm32x, X:ymm" , "op": "RMV: VEX.256.66.0F38.W1 90 /r"}, - {"inst": "vpgatherqd X:xmm, vm64x, X:xmm" , "op": "RMV: VEX.128.66.0F38.W0 91 /r"}, - {"inst": "vpgatherqd X:xmm, vm64y, X:xmm" , "op": "RMV: VEX.256.66.0F38.W0 91 /r"}, - {"inst": "vpgatherqq X:xmm, vm64x, X:xmm" , "op": "RMV: VEX.128.66.0F38.W1 91 /r"}, - {"inst": "vpgatherqq X:ymm, vm64y, X:ymm" , "op": "RMV: VEX.256.66.0F38.W1 91 /r"}, - {"inst": "vphaddd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 02 /r"}, - {"inst": "vphaddsw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 03 /r"}, - {"inst": "vphaddw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 01 /r"}, - {"inst": "vphsubd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 06 /r"}, - {"inst": "vphsubsw W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 07 /r"}, - {"inst": "vphsubw W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 05 /r"}, - {"inst": "vpmaddubsw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 04 /r"}, - {"inst": "vpmaddwd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG F5 /r"}, - {"inst": "vpmaskmovd X:m128, xmm, xmm" , "op": "MVR: VEX.128.66.0F38.W0 8E /r"}, - {"inst": "vpmaskmovd X:m256, ymm, ymm" , "op": "MVR: VEX.256.66.0F38.W0 8E /r"}, - {"inst": "vpmaskmovd W:xmm, xmm, m128" , "op": "RVM: VEX.128.66.0F38.W0 8C /r"}, - {"inst": "vpmaskmovd W:ymm, ymm, m256" , "op": "RVM: VEX.256.66.0F38.W0 8C /r"}, - {"inst": "vpmaskmovq X:m128, xmm, xmm" , "op": "MVR: VEX.128.66.0F38.W1 8E /r"}, - {"inst": "vpmaskmovq X:m256, ymm, ymm" , "op": "MVR: VEX.256.66.0F38.W1 8E /r"}, - {"inst": "vpmaskmovq W:xmm, xmm, m128" , "op": "RVM: VEX.128.66.0F38.W1 8C /r"}, - {"inst": "vpmaskmovq W:ymm, ymm, m256" , "op": "RVM: VEX.256.66.0F38.W1 8C /r"}, - {"inst": "vpmaxsb W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 3C /r"}, - {"inst": "vpmaxsd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 3D /r"}, - {"inst": "vpmaxsw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG EE /r"}, - {"inst": "vpmaxub W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG DE /r"}, - {"inst": "vpmaxud W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 3F /r"}, - {"inst": "vpmaxuw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 3E /r"}, - {"inst": "vpminsb W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 38 /r"}, - {"inst": "vpminsd W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 39 /r"}, - {"inst": "vpminsw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG EA /r"}, - {"inst": "vpminub W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG DA /r"}, - {"inst": "vpminud W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 3B /r"}, - {"inst": "vpminuw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 3A /r"}, - {"inst": "vpmovmskb W:r32[31:0], ymm" , "op": "RVM: VEX.256.66.0F.WIG D7 /r"}, - {"inst": "vpmovsxbd W:ymm, xmm[63:0]/m64" , "op": "RM: VEX.256.66.0F38.WIG 21 /r"}, - {"inst": "vpmovsxbq W:ymm, xmm[31:0]/m32" , "op": "RM: VEX.256.66.0F38.WIG 22 /r"}, - {"inst": "vpmovsxbw W:ymm, xmm/m128" , "op": "RM: VEX.256.66.0F38.WIG 20 /r"}, - {"inst": "vpmovsxdq W:ymm, xmm/m128" , "op": "RM: VEX.256.66.0F38.WIG 25 /r"}, - {"inst": "vpmovsxwd W:ymm, xmm/m128" , "op": "RM: VEX.256.66.0F38.WIG 23 /r"}, - {"inst": "vpmovsxwq W:ymm, xmm[63:0]/m64" , "op": "RM: VEX.256.66.0F38.WIG 24 /r"}, - {"inst": "vpmovzxbd W:ymm, xmm[63:0]/m64" , "op": "RM: VEX.256.66.0F38.WIG 31 /r"}, - {"inst": "vpmovzxbq W:ymm, xmm[31:0]/m32" , "op": "RM: VEX.256.66.0F38.WIG 32 /r"}, - {"inst": "vpmovzxbw W:ymm, xmm/m128" , "op": "RM: VEX.256.66.0F38.WIG 30 /r"}, - {"inst": "vpmovzxdq W:ymm, xmm/m128" , "op": "RM: VEX.256.66.0F38.WIG 35 /r"}, - {"inst": "vpmovzxwd W:ymm, xmm/m128" , "op": "RM: VEX.256.66.0F38.WIG 33 /r"}, - {"inst": "vpmovzxwq W:ymm, xmm[63:0]/m64" , "op": "RM: VEX.256.66.0F38.WIG 34 /r"}, - {"inst": "vpmuldq W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 28 /r"}, - {"inst": "vpmulhrsw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 0B /r"}, - {"inst": "vpmulhuw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG E4 /r"}, - {"inst": "vpmulhw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG E5 /r"}, - {"inst": "vpmulld W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 40 /r"}, - {"inst": "vpmullw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG D5 /r"}, - {"inst": "vpmuludq W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG F4 /r"}, - {"inst": "vpor W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG EB /r"}, - {"inst": "vpsadbw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG F6 /r"}, - {"inst": "vpshufb W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 00 /r"}, - {"inst": "vpshufd W:ymm, ymm/m256, ib/ub" , "op": "RM: VEX.256.66.0F.WIG 70 /r ib"}, - {"inst": "vpshufhw W:ymm, ymm/m256, ib/ub" , "op": "RM: VEX.256.F3.0F.WIG 70 /r ib"}, - {"inst": "vpshuflw W:ymm, ymm/m256, ib/ub" , "op": "RM: VEX.256.F2.0F.WIG 70 /r ib"}, - {"inst": "vpsignb W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 08 /r"}, - {"inst": "vpsignd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 0A /r"}, - {"inst": "vpsignw W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.WIG 09 /r"}, - {"inst": "vpslld W:ymm, ymm, ib/ub" , "op": "VM: VEX.256.66.0F.WIG 72 /6 ib"}, - {"inst": "vpslld W:ymm, ymm, xmm/m128" , "op": "RVM: VEX.256.66.0F.WIG F2 /r"}, - {"inst": "vpslldq W:ymm, ymm, ib/ub" , "op": "VM: VEX.256.66.0F.WIG 73 /7 ib"}, - {"inst": "vpsllq W:ymm, ymm, ib/ub" , "op": "VM: VEX.256.66.0F.WIG 73 /6 ib"}, - {"inst": "vpsllq W:ymm, ymm, xmm/m128" , "op": "RVM: VEX.256.66.0F.WIG F3 /r"}, - {"inst": "vpsllvd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 47 /r"}, - {"inst": "vpsllvd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 47 /r"}, - {"inst": "vpsllvq W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 47 /r"}, - {"inst": "vpsllvq W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 47 /r"}, - {"inst": "vpsllw W:ymm, ymm, ib/ub" , "op": "VM: VEX.256.66.0F.WIG 71 /6 ib"}, - {"inst": "vpsllw W:ymm, ymm, xmm/m128" , "op": "RVM: VEX.256.66.0F.WIG F1 /r"}, - {"inst": "vpsrad W:ymm, ymm, ib/ub" , "op": "VM: VEX.256.66.0F.WIG 72 /4 ib"}, - {"inst": "vpsrad W:ymm, ymm, xmm/m128" , "op": "RVM: VEX.256.66.0F.WIG E2 /r"}, - {"inst": "vpsravd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 46 /r"}, - {"inst": "vpsravd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 46 /r"}, - {"inst": "vpsraw W:ymm, ymm, ib/ub" , "op": "VM: VEX.256.66.0F.WIG 71 /4 ib"}, - {"inst": "vpsraw W:ymm, ymm, xmm/m128" , "op": "RVM: VEX.256.66.0F.WIG E1 /r"}, - {"inst": "vpsrld W:ymm, ymm, ib/ub" , "op": "VM: VEX.256.66.0F.WIG 72 /2 ib"}, - {"inst": "vpsrld W:ymm, ymm, xmm/m128" , "op": "RVM: VEX.256.66.0F.WIG D2 /r"}, - {"inst": "vpsrldq W:ymm, ymm, ib/ub" , "op": "VM: VEX.256.66.0F.WIG 73 /3 ib"}, - {"inst": "vpsrlq W:ymm, ymm, ib/ub" , "op": "VM: VEX.256.66.0F.WIG 73 /2 ib"}, - {"inst": "vpsrlq W:ymm, ymm, xmm/m128" , "op": "RVM: VEX.256.66.0F.WIG D3 /r"}, - {"inst": "vpsrlvd W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 45 /r"}, - {"inst": "vpsrlvd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 45 /r"}, - {"inst": "vpsrlvq W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 45 /r"}, - {"inst": "vpsrlvq W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 45 /r"}, - {"inst": "vpsrlw W:ymm, ymm, ib/ub" , "op": "VM: VEX.256.66.0F.WIG 71 /2 ib"}, - {"inst": "vpsrlw W:ymm, ymm, xmm/m128" , "op": "RVM: VEX.256.66.0F.WIG D1 /r"}, - {"inst": "vpsubb W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG F8 /r"}, - {"inst": "vpsubd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG FA /r"}, - {"inst": "vpsubq W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG FB /r"}, - {"inst": "vpsubsb W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG E8 /r"}, - {"inst": "vpsubsw W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG E9 /r"}, - {"inst": "vpsubusb W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG D8 /r"}, - {"inst": "vpsubusw W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG D9 /r"}, - {"inst": "vpsubw W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG F9 /r"}, - {"inst": "vpunpckhbw W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 68 /r"}, - {"inst": "vpunpckhdq W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 6A /r"}, - {"inst": "vpunpckhqdq W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 6D /r"}, - {"inst": "vpunpckhwd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 69 /r"}, - {"inst": "vpunpcklbw W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 60 /r"}, - {"inst": "vpunpckldq W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 62 /r"}, - {"inst": "vpunpcklqdq W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 6C /r"}, - {"inst": "vpunpcklwd W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG 61 /r"}, - {"inst": "vpxor W:ymm, ~ymm, ~ymm/m256" , "op": "RVM: VEX.256.66.0F.WIG EF /r"} - ]}, - - {"category": "AVX SIMD", "ext": "F16C", "data": [ - {"inst": "vcvtph2ps W:xmm, xmm[63:0]/m64" , "op": "RM: VEX.128.66.0F38.W0 13 /r"}, - {"inst": "vcvtph2ps W:ymm, xmm/m128" , "op": "RM: VEX.256.66.0F38.W0 13 /r"}, - {"inst": "vcvtps2ph W:xmm[63:0]/m64, xmm, ib/ub" , "op": "MR: VEX.128.66.0F3A.W0 1D /r ib"}, - {"inst": "vcvtps2ph W:xmm/m128, ymm, ib/ub" , "op": "MR: VEX.256.66.0F3A.W0 1D /r ib"} - ]}, - - {"category": "AVX SCALAR", "ext": "FMA", "data": [ - {"inst": "vfmadd132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 99 /r"}, - {"inst": "vfmadd132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 99 /r"}, - {"inst": "vfmadd213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 A9 /r"}, - {"inst": "vfmadd213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 A9 /r"}, - {"inst": "vfmadd231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 B9 /r"}, - {"inst": "vfmadd231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 B9 /r"}, - {"inst": "vfmsub132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 9B /r"}, - {"inst": "vfmsub132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 9B /r"}, - {"inst": "vfmsub213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 AB /r"}, - {"inst": "vfmsub213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 AB /r"}, - {"inst": "vfmsub231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 BB /r"}, - {"inst": "vfmsub231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 BB /r"}, - {"inst": "vfnmadd132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 9D /r"}, - {"inst": "vfnmadd132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 9D /r"}, - {"inst": "vfnmadd213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 AD /r"}, - {"inst": "vfnmadd213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 AD /r"}, - {"inst": "vfnmadd231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 BD /r"}, - {"inst": "vfnmadd231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 BD /r"}, - {"inst": "vfnmsub132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 9F /r"}, - {"inst": "vfnmsub132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 9F /r"}, - {"inst": "vfnmsub213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 AF /r"}, - {"inst": "vfnmsub213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 AF /r"}, - {"inst": "vfnmsub231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "RVM: VEX.LIG.66.0F38.W1 BF /r"}, - {"inst": "vfnmsub231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "RVM: VEX.LIG.66.0F38.W0 BF /r"} - ]}, - - {"category": "AVX SIMD", "ext": "FMA", "data": [ - {"inst": "vfmadd132pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 98 /r"}, - {"inst": "vfmadd132pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 98 /r"}, - {"inst": "vfmadd132ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 98 /r"}, - {"inst": "vfmadd132ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 98 /r"}, - {"inst": "vfmadd213pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 A8 /r"}, - {"inst": "vfmadd213pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 A8 /r"}, - {"inst": "vfmadd213ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 A8 /r"}, - {"inst": "vfmadd213ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 A8 /r"}, - {"inst": "vfmadd231pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 B8 /r"}, - {"inst": "vfmadd231pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 B8 /r"}, - {"inst": "vfmadd231ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 B8 /r"}, - {"inst": "vfmadd231ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 B8 /r"}, - {"inst": "vfmaddsub132pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 96 /r"}, - {"inst": "vfmaddsub132pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 96 /r"}, - {"inst": "vfmaddsub132ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 96 /r"}, - {"inst": "vfmaddsub132ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 96 /r"}, - {"inst": "vfmaddsub213pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 A6 /r"}, - {"inst": "vfmaddsub213pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 A6 /r"}, - {"inst": "vfmaddsub213ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 A6 /r"}, - {"inst": "vfmaddsub213ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 A6 /r"}, - {"inst": "vfmaddsub231pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 B6 /r"}, - {"inst": "vfmaddsub231pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 B6 /r"}, - {"inst": "vfmaddsub231ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 B6 /r"}, - {"inst": "vfmaddsub231ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 B6 /r"}, - {"inst": "vfmsub132pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 9A /r"}, - {"inst": "vfmsub132pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 9A /r"}, - {"inst": "vfmsub132ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 9A /r"}, - {"inst": "vfmsub132ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 9A /r"}, - {"inst": "vfmsub213pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 AA /r"}, - {"inst": "vfmsub213pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 AA /r"}, - {"inst": "vfmsub213ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 AA /r"}, - {"inst": "vfmsub213ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 AA /r"}, - {"inst": "vfmsub231pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 BA /r"}, - {"inst": "vfmsub231pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 BA /r"}, - {"inst": "vfmsub231ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 BA /r"}, - {"inst": "vfmsub231ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 BA /r"}, - {"inst": "vfmsubadd132pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 97 /r"}, - {"inst": "vfmsubadd132pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 97 /r"}, - {"inst": "vfmsubadd132ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 97 /r"}, - {"inst": "vfmsubadd132ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 97 /r"}, - {"inst": "vfmsubadd213pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 A7 /r"}, - {"inst": "vfmsubadd213pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 A7 /r"}, - {"inst": "vfmsubadd213ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 A7 /r"}, - {"inst": "vfmsubadd213ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 A7 /r"}, - {"inst": "vfmsubadd231pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 B7 /r"}, - {"inst": "vfmsubadd231pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 B7 /r"}, - {"inst": "vfmsubadd231ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 B7 /r"}, - {"inst": "vfmsubadd231ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 B7 /r"}, - {"inst": "vfnmadd132pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 9C /r"}, - {"inst": "vfnmadd132pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 9C /r"}, - {"inst": "vfnmadd132ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 9C /r"}, - {"inst": "vfnmadd132ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 9C /r"}, - {"inst": "vfnmadd213pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 AC /r"}, - {"inst": "vfnmadd213pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 AC /r"}, - {"inst": "vfnmadd213ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 AC /r"}, - {"inst": "vfnmadd213ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 AC /r"}, - {"inst": "vfnmadd231pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 BC /r"}, - {"inst": "vfnmadd231pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 BC /r"}, - {"inst": "vfnmadd231ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 BC /r"}, - {"inst": "vfnmadd231ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 BC /r"}, - {"inst": "vfnmsub132pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 9E /r"}, - {"inst": "vfnmsub132pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 9E /r"}, - {"inst": "vfnmsub132ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 9E /r"}, - {"inst": "vfnmsub132ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 9E /r"}, - {"inst": "vfnmsub213pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 AE /r"}, - {"inst": "vfnmsub213pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 AE /r"}, - {"inst": "vfnmsub213ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 AE /r"}, - {"inst": "vfnmsub213ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 AE /r"}, - {"inst": "vfnmsub231pd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 BE /r"}, - {"inst": "vfnmsub231pd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 BE /r"}, - {"inst": "vfnmsub231ps X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 BE /r"}, - {"inst": "vfnmsub231ps X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 BE /r"} - ]}, - - {"category": "AVX SCALAR", "ext": "FMA4", "deprecated": true, "data": [ - {"inst": "vfmaddsd W:xmm[63:0], xmm[63:0], xmm[63:0],xmm[63:0]/m64" , "op": "RVSM: VEX.128.66.0F3A.W1 6b /r /is4"}, - {"inst": "vfmaddsd W:xmm[63:0], xmm[63:0], xmm[63:0]/m64,xmm[63:0]" , "op": "RVMS: VEX.128.66.0F3A.W0 6b /r /is4"}, - {"inst": "vfmaddss W:xmm[31:0], xmm[31:0], xmm[31:0],xmm[31:0]/m32" , "op": "RVSM: VEX.128.66.0F3A.W1 6a /r /is4"}, - {"inst": "vfmaddss W:xmm[31:0], xmm[31:0], xmm[31:0]/m32,xmm[31:0]" , "op": "RVMS: VEX.128.66.0F3A.W0 6a /r /is4"}, - {"inst": "vfmsubsd W:xmm[63:0], xmm[63:0], xmm[63:0],xmm[63:0]/m64" , "op": "RVSM: VEX.128.66.0F3A.W1 6F /r /is4"}, - {"inst": "vfmsubsd W:xmm[63:0], xmm[63:0], xmm[63:0]/m64,xmm[63:0]" , "op": "RVMS: VEX.128.66.0F3A.W0 6F /r /is4"}, - {"inst": "vfmsubss W:xmm[31:0], xmm[31:0], xmm[31:0],xmm[31:0]/m32" , "op": "RVSM: VEX.128.66.0F3A.W1 6E /r /is4"}, - {"inst": "vfmsubss W:xmm[31:0], xmm[31:0], xmm[31:0]/m32,xmm[31:0]" , "op": "RVMS: VEX.128.66.0F3A.W0 6E /r /is4"}, - {"inst": "vfnmaddsd W:xmm[63:0], xmm[63:0],xmm[63:0],xmm[63:0]/m64" , "op": "RVSM: VEX.128.66.0F3A.W1 7B /r /is4"}, - {"inst": "vfnmaddsd W:xmm[63:0], xmm[63:0],xmm[63:0]/m64,xmm[63:0]" , "op": "RVMS: VEX.128.66.0F3A.W0 7B /r /is4"}, - {"inst": "vfnmaddss W:xmm[31:0], xmm[31:0],xmm[31:0],xmm[31:0]/m32" , "op": "RVSM: VEX.128.66.0F3A.W1 7A /r /is4"}, - {"inst": "vfnmaddss W:xmm[31:0], xmm[31:0],xmm[31:0]/m32,xmm[31:0]" , "op": "RVMS: VEX.128.66.0F3A.W0 7A /r /is4"}, - {"inst": "vfnmsubsd W:xmm[63:0], xmm[63:0],xmm[63:0],xmm[63:0]/m64" , "op": "RVSM: VEX.128.66.0F3A.W1 7F /r /is4"}, - {"inst": "vfnmsubsd W:xmm[63:0], xmm[63:0],xmm[63:0]/m64,xmm[63:0]" , "op": "RVMS: VEX.128.66.0F3A.W0 7F /r /is4"}, - {"inst": "vfnmsubss W:xmm[31:0], xmm[31:0],xmm[31:0],xmm[31:0]/m32" , "op": "RVSM: VEX.128.66.0F3A.W1 7E /r /is4"}, - {"inst": "vfnmsubss W:xmm[31:0], xmm[31:0],xmm[31:0]/m32,xmm[31:0]" , "op": "RVMS: VEX.128.66.0F3A.W0 7E /r /is4"} - ]}, - - {"category": "AVX SIMD", "ext": "FMA4", "deprecated": true, "data": [ - {"inst": "vfmaddpd W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 69 /r /is4"}, - {"inst": "vfmaddpd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 69 /r /is4"}, - {"inst": "vfmaddpd W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 69 /r /is4"}, - {"inst": "vfmaddpd W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 69 /r /is4"}, - {"inst": "vfmaddps W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 68 /r /is4"}, - {"inst": "vfmaddps W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 68 /r /is4"}, - {"inst": "vfmaddps W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 68 /r /is4"}, - {"inst": "vfmaddps W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 68 /r /is4"}, - {"inst": "vfmaddsubpd W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 5D /r /is4"}, - {"inst": "vfmaddsubpd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 5D /r /is4"}, - {"inst": "vfmaddsubpd W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 5D /r /is4"}, - {"inst": "vfmaddsubpd W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 5D /r /is4"}, - {"inst": "vfmaddsubps W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 5C /r /is4"}, - {"inst": "vfmaddsubps W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 5C /r /is4"}, - {"inst": "vfmaddsubps W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 5C /r /is4"}, - {"inst": "vfmaddsubps W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 5C /r /is4"}, - {"inst": "vfmsubaddpd W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 5F /r /is4"}, - {"inst": "vfmsubaddpd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 5F /r /is4"}, - {"inst": "vfmsubaddpd W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 5F /r /is4"}, - {"inst": "vfmsubaddpd W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 5F /r /is4"}, - {"inst": "vfmsubaddps W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 5E /r /is4"}, - {"inst": "vfmsubaddps W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 5E /r /is4"}, - {"inst": "vfmsubaddps W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 5E /r /is4"}, - {"inst": "vfmsubaddps W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 5E /r /is4"}, - {"inst": "vfmsubpd W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 6D /r /is4"}, - {"inst": "vfmsubpd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 6D /r /is4"}, - {"inst": "vfmsubpd W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 6D /r /is4"}, - {"inst": "vfmsubpd W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 6D /r /is4"}, - {"inst": "vfmsubps W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 6C /r /is4"}, - {"inst": "vfmsubps W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 6C /r /is4"}, - {"inst": "vfmsubps W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 6C /r /is4"}, - {"inst": "vfmsubps W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 6C /r /is4"}, - {"inst": "vfnmaddpd W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 79 /r /is4"}, - {"inst": "vfnmaddpd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 79 /r /is4"}, - {"inst": "vfnmaddpd W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 79 /r /is4"}, - {"inst": "vfnmaddpd W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 79 /r /is4"}, - {"inst": "vfnmaddps W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 78 /r /is4"}, - {"inst": "vfnmaddps W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 78 /r /is4"}, - {"inst": "vfnmaddps W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 78 /r /is4"}, - {"inst": "vfnmaddps W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 78 /r /is4"}, - {"inst": "vfnmsubpd W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 7D /r /is4"}, - {"inst": "vfnmsubpd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 7D /r /is4"}, - {"inst": "vfnmsubpd W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 7D /r /is4"}, - {"inst": "vfnmsubpd W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 7D /r /is4"}, - {"inst": "vfnmsubps W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: VEX.128.66.0F3A.W1 7C /r /is4"}, - {"inst": "vfnmsubps W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: VEX.128.66.0F3A.W0 7C /r /is4"}, - {"inst": "vfnmsubps W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: VEX.256.66.0F3A.W1 7C /r /is4"}, - {"inst": "vfnmsubps W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: VEX.256.66.0F3A.W0 7C /r /is4"} - ]}, - - {"category": "AVX SCALAR", "ext": "XOP", "deprecated": true, "data": [ - {"inst": "vfrczsd W:xmm[63:0], xmm[63:0]/m64" , "op": "RM: XOP.L0.P0.M09.W0 83 /r"}, - {"inst": "vfrczss W:xmm[31:0], xmm[31:0]/m32" , "op": "RM: XOP.L0.P0.M09.W0 82 /r"} - ]}, - - {"category": "AVX SIMD", "ext": "XOP", "deprecated": true, "data": [ - {"inst": "vfrczpd W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 81 /r"}, - {"inst": "vfrczpd W:ymm, ymm/m256" , "op": "RM: XOP.L1.P0.M09.W0 81 /r"}, - {"inst": "vfrczps W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 80 /r"}, - {"inst": "vfrczps W:ymm, ymm/m256" , "op": "RM: XOP.L1.P0.M09.W0 80 /r"}, - {"inst": "vpcmov W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: XOP.L0.P0.M08.W1 A2 /r /is4"}, - {"inst": "vpcmov W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 A2 /r /is4"}, - {"inst": "vpcmov W:ymm, ymm, ymm, ymm/m256" , "op": "RVSM: XOP.L1.P0.M08.W1 A2 /r /is4"}, - {"inst": "vpcmov W:ymm, ymm, ymm/m256, ymm" , "op": "RVMS: XOP.L1.P0.M08.W0 A2 /r /is4"}, - {"inst": "vpcomb W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: XOP.L0.P0.M08.W0 CC /r ib"}, - {"inst": "vpcomd W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: XOP.L0.P0.M08.W0 CE /r ib"}, - {"inst": "vpcomq W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: XOP.L0.P0.M08.W0 CF /r ib"}, - {"inst": "vpcomub W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: XOP.L0.P0.M08.W0 EC /r ib"}, - {"inst": "vpcomud W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: XOP.L0.P0.M08.W0 EE /r ib"}, - {"inst": "vpcomuq W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: XOP.L0.P0.M08.W0 EF /r ib"}, - {"inst": "vpcomuw W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: XOP.L0.P0.M08.W0 ED /r ib"}, - {"inst": "vpcomw W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: XOP.L0.P0.M08.W0 CD /r ib"}, - {"inst": "vpermil2pd W:xmm, xmm, xmm/m128, xmm, i4/u4" , "op": "RVMS: VEX.L0.66.0F3A.W0 49 /r /is4"}, - {"inst": "vpermil2pd W:xmm, xmm, xmm, xmm/m128, i4/u4" , "op": "RVSM: VEX.L0.66.0F3A.W1 49 /r /is4"}, - {"inst": "vpermil2pd W:ymm, ymm, ymm/m256, ymm, i4/u4" , "op": "RVMS: VEX.L1.66.0F3A.W0 49 /r /is4"}, - {"inst": "vpermil2pd W:ymm, ymm, ymm, ymm/m256, i4/u4" , "op": "RVSM: VEX.L1.66.0F3A.W1 49 /r /is4"}, - {"inst": "vpermil2ps W:xmm, xmm, xmm/m128, xmm, i4/u4" , "op": "RVMS: VEX.L0.66.0F3A.W0 48 /r /is4"}, - {"inst": "vpermil2ps W:xmm, xmm, xmm, xmm/m128, i4/u4" , "op": "RVSM: VEX.L0.66.0F3A.W1 48 /r /is4"}, - {"inst": "vpermil2ps W:ymm, ymm, ymm/m256, ymm, i4/u4" , "op": "RVMS: VEX.L1.66.0F3A.W0 48 /r /is4"}, - {"inst": "vpermil2ps W:ymm, ymm, ymm, ymm/m256, i4/u4" , "op": "RVSM: VEX.L1.66.0F3A.W1 48 /r /is4"}, - {"inst": "vphaddbd W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 C2 /r"}, - {"inst": "vphaddbq W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 C3 /r"}, - {"inst": "vphaddbw W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 C1 /r"}, - {"inst": "vphadddq W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 CB /r"}, - {"inst": "vphaddubd W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 D2 /r"}, - {"inst": "vphaddubq W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 D3 /r"}, - {"inst": "vphaddubw W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 D1 /r"}, - {"inst": "vphaddudq W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 DB /r"}, - {"inst": "vphadduwd W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 D6 /r"}, - {"inst": "vphadduwq W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 D7 /r"}, - {"inst": "vphaddwd W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 C6 /r"}, - {"inst": "vphaddwq W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 C7 /r"}, - {"inst": "vphsubbw W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 E1 /r"}, - {"inst": "vphsubdq W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 E3 /r"}, - {"inst": "vphsubwd W:xmm, xmm/m128" , "op": "RM: XOP.L0.P0.M09.W0 E2 /r"}, - {"inst": "vpmacsdd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 9E /r /is4"}, - {"inst": "vpmacsdqh W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 9F /r /is4"}, - {"inst": "vpmacsdql W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 97 /r /is4"}, - {"inst": "vpmacssdd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 8E /r /is4"}, - {"inst": "vpmacssdqh W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 8F /r /is4"}, - {"inst": "vpmacssdql W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 87 /r /is4"}, - {"inst": "vpmacsswd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 86 /r /is4"}, - {"inst": "vpmacssww W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 85 /r /is4"}, - {"inst": "vpmacswd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 96 /r /is4"}, - {"inst": "vpmacsww W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 95 /r /is4"}, - {"inst": "vpmadcsswd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 A6 /r /is4"}, - {"inst": "vpmadcswd W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 B6 /r /is4"}, - {"inst": "vpperm W:xmm, xmm, xmm, xmm/m128" , "op": "RVSM: XOP.L0.P0.M08.W1 A3 /r /is4"}, - {"inst": "vpperm W:xmm, xmm, xmm/m128, xmm" , "op": "RVMS: XOP.L0.P0.M08.W0 A3 /r /is4"}, - {"inst": "vprotb W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 90 /r"}, - {"inst": "vprotb W:xmm, xmm/m128, ib/ub" , "op": "RM: XOP.L0.P0.M08.W0 C0 /r ib"}, - {"inst": "vprotb W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 90 /r"}, - {"inst": "vprotd W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 92 /r"}, - {"inst": "vprotd W:xmm, xmm/m128, ib/ub" , "op": "RM: XOP.L0.P0.M08.W0 C2 /r ib"}, - {"inst": "vprotd W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 92 /r"}, - {"inst": "vprotq W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 93 /r"}, - {"inst": "vprotq W:xmm, xmm/m128, ib/ub" , "op": "RM: XOP.L0.P0.M08.W0 C3 /r ib"}, - {"inst": "vprotq W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 93 /r"}, - {"inst": "vprotw W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 91 /r"}, - {"inst": "vprotw W:xmm, xmm/m128, ib/ub" , "op": "RM: XOP.L0.P0.M08.W0 C1 /r ib"}, - {"inst": "vprotw W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 91 /r"}, - {"inst": "vpshab W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 98 /r"}, - {"inst": "vpshab W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 98 /r"}, - {"inst": "vpshad W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 9A /r"}, - {"inst": "vpshad W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 9A /r"}, - {"inst": "vpshaq W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 9B /r"}, - {"inst": "vpshaq W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 9B /r"}, - {"inst": "vpshaw W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 99 /r"}, - {"inst": "vpshaw W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 99 /r"}, - {"inst": "vpshlb W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 94 /r"}, - {"inst": "vpshlb W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 94 /r"}, - {"inst": "vpshld W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 96 /r"}, - {"inst": "vpshld W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 96 /r"}, - {"inst": "vpshlq W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 97 /r"}, - {"inst": "vpshlq W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 97 /r"}, - {"inst": "vpshlw W:xmm, xmm, xmm/m128" , "op": "RVM: XOP.L0.P0.M09.W1 95 /r"}, - {"inst": "vpshlw W:xmm, xmm/m128, xmm" , "op": "RMV: XOP.L0.P0.M09.W0 95 /r"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX_IFMA", "data": [ - {"inst": "vpmadd52huq X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 B5 /r"}, - {"inst": "vpmadd52huq X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 B5 /r"}, - {"inst": "vpmadd52luq X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W1 B4 /r"}, - {"inst": "vpmadd52luq X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W1 B4 /r"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX_NE_CONVERT", "data": [ - {"inst": "vbcstnebf162ps W:xmm, m16" , "op": "RM: VEX.128.F3.0F38.W0 B1 /r"}, - {"inst": "vbcstnebf162ps W:ymm, m16" , "op": "RM: VEX.256.F3.0F38.W0 B1 /r"}, - {"inst": "vbcstnesh2ps W:xmm, m16" , "op": "RM: VEX.128.66.0F38.W0 B1 /r"}, - {"inst": "vbcstnesh2ps W:ymm, m16" , "op": "RM: VEX.256.66.0F38.W0 B1 /r"}, - {"inst": "vcvtneebf162ps W:xmm, m128" , "op": "RM: VEX.128.F3.0F38.W0 B0 /r"}, - {"inst": "vcvtneebf162ps W:ymm, m256" , "op": "RM: VEX.256.F3.0F38.W0 B0 /r"}, - {"inst": "vcvtneeph2ps W:xmm, m128" , "op": "RM: VEX.128.66.0F38.W0 B0 /r"}, - {"inst": "vcvtneeph2ps W:ymm, m256" , "op": "RM: VEX.256.66.0F38.W0 B0 /r"}, - {"inst": "vcvtneobf162ps W:xmm, m128" , "op": "RM: VEX.128.F2.0F38.W0 B0 /r"}, - {"inst": "vcvtneobf162ps W:ymm, m256" , "op": "RM: VEX.256.F2.0F38.W0 B0 /r"}, - {"inst": "vcvtneoph2ps W:xmm, m128" , "op": "RM: VEX.128.NP.0F38.W0 B0 /r"}, - {"inst": "vcvtneoph2ps W:ymm, m256" , "op": "RM: VEX.256.NP.0F38.W0 B0 /r"}, - {"inst": "vcvtneps2bf16 W:xmm, xmm/m128" , "op": "RM: VEX.128.F3.0F38.W0 72 /r"}, - {"inst": "vcvtneps2bf16 W:xmm, ymm/m256" , "op": "RM: VEX.256.F3.0F38.W0 72 /r"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX SHA512", "data": [ - {"inst": "vsha512msg1 X:ymm, xmm" , "op": "RM: VEX.256.F2.0F38.W0 CC /r"}, - {"inst": "vsha512msg2 X:ymm, ymm" , "op": "RM: VEX.256.F2.0F38.W0 CD /r"}, - {"inst": "vsha512rnds2 X:ymm, ymm, xmm" , "op": "RVM: VEX.256.F2.0F38.W0 CB /r"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX SM3", "data": [ - {"inst": "vsm3msg1 X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.NP.0F38.W0 DA /r"}, - {"inst": "vsm3msg2 X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 DA /r"}, - {"inst": "vsm3rnds2 X:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.W0 DE /r ib"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX SM4", "data": [ - {"inst": "vsm4key4 W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.F3.0F38.W0 DA /r"}, - {"inst": "vsm4key4 W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.F3.0F38.W0 DA /r"}, - {"inst": "vsm4rnds4 W:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.F2.0F38.W0 DA /r"}, - {"inst": "vsm4rnds4 W:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.F2.0F38.W0 DA /r"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX_VNNI", "data": [ - {"inst": "vpdpbusd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 50 /r"}, - {"inst": "vpdpbusd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 50 /r"}, - {"inst": "vpdpbusds X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 51 /r"}, - {"inst": "vpdpbusds X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 51 /r"}, - {"inst": "vpdpwssd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 52 /r"}, - {"inst": "vpdpwssd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 52 /r"}, - {"inst": "vpdpwssds X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 53 /r"}, - {"inst": "vpdpwssds X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 53 /r"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX_VNNI_INT8", "data": [ - {"inst": "vpdpbssd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.F2.0F38.W0 50 /r"}, - {"inst": "vpdpbssd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.F2.0F38.W0 50 /r"}, - {"inst": "vpdpbssds X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.F2.0F38.W0 51 /r"}, - {"inst": "vpdpbssds X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.F2.0F38.W0 51 /r"}, - {"inst": "vpdpbsud X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.F3.0F38.W0 50 /r"}, - {"inst": "vpdpbsud X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.F3.0F38.W0 50 /r"}, - {"inst": "vpdpbsuds X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.F3.0F38.W0 51 /r"}, - {"inst": "vpdpbsuds X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.F3.0F38.W0 51 /r"}, - {"inst": "vpdpbuud X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.NP.0F38.W0 50 /r"}, - {"inst": "vpdpbuud X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.NP.0F38.W0 50 /r"}, - {"inst": "vpdpbuuds X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.NP.0F38.W0 51 /r"}, - {"inst": "vpdpbuuds X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.NP.0F38.W0 51 /r"} - ]}, - - {"category": "AVX SIMD", "ext": "AVX_VNNI_INT16", "data": [ - {"inst": "vpdpwsud X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.F3.0F38.W0 D2 /r"}, - {"inst": "vpdpwsud X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.F3.0F38.W0 D2 /r"}, - {"inst": "vpdpwsuds X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.F3.0F38.W0 D3 /r"}, - {"inst": "vpdpwsuds X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.F3.0F38.W0 D3 /r"}, - {"inst": "vpdpwusd X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 D2 /r"}, - {"inst": "vpdpwusd X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 D2 /r"}, - {"inst": "vpdpwusds X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 D3 /r"}, - {"inst": "vpdpwusds X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.66.0F38.W0 D3 /r"}, - {"inst": "vpdpwuud X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.NP.0F38.W0 D2 /r"}, - {"inst": "vpdpwuud X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.NP.0F38.W0 D2 /r"}, - {"inst": "vpdpwuuds X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.NP.0F38.W0 D3 /r"}, - {"inst": "vpdpwuuds X:ymm, ymm, ymm/m256" , "op": "RVM: VEX.256.NP.0F38.W0 D3 /r"} - ]}, - - {"category": "AVX SIMD", "ext": "VPCLMULQDQ", "data": [ - {"inst": "vpclmulqdq W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM: VEX.256.66.0F3A.WIG 44 /r ib"} - ]}, - - {"category": "AVX512 MASK", "ext": "AVX512_F", "data": [ - {"inst": "kandnw W:k[15:0], k[15:0], k[15:0]" , "op": "RVM: VEX.L1.0F.W0 42 /r"}, - {"inst": "kandw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "RVM: VEX.L1.0F.W0 41 /r"}, - {"inst": "kmovw W:k[15:0], k[15:0]/m16" , "op": "RM: VEX.L0.0F.W0 90 /r"}, - {"inst": "kmovw W:k[15:0], r32[15:0]" , "op": "RM: VEX.L0.0F.W0 92 /r"}, - {"inst": "kmovw W:m16, k[15:0]" , "op": "MR: VEX.L0.0F.W0 91 /r"}, - {"inst": "kmovw W:r32[15:0], k[15:0]" , "op": "RM: VEX.L0.0F.W0 93 /r"}, - {"inst": "knotw W:k[15:0], k[15:0]" , "op": "RM: VEX.L0.0F.W0 44 /r"}, - {"inst": "kortestw R:~k[15:0], ~k[15:0]" , "op": "RM: VEX.L0.0F.W0 98 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "korw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "RVM: VEX.L1.0F.W0 45 /r"}, - {"inst": "kshiftlw W:k[15:0], k[15:0], ib/ub" , "op": "RM: VEX.L0.66.0F3A.W1 32 /r ib"}, - {"inst": "kshiftrw W:k[15:0], k[15:0], ib/ub" , "op": "RM: VEX.L0.66.0F3A.W1 30 /r ib"}, - {"inst": "kunpckbw W:k[15:0], k[7:0], k[7:0]" , "op": "RVM: VEX.L1.66.0F.W0 4B /r"}, - {"inst": "kxnorw W:k[15:0], k[15:0], k[15:0]" , "op": "RVM: VEX.L1.0F.W0 46 /r"}, - {"inst": "kxorw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "RVM: VEX.L1.0F.W0 47 /r"} - ]}, - - {"category": "AVX512 MASK", "ext": "AVX512_DQ", "data": [ - {"inst": "kaddb W:k[7:0], ~k[7:0], ~k[7:0]" , "op": "RVM: VEX.L1.66.0F.W0 4A /r"}, - {"inst": "kaddw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "RVM: VEX.L1.0F.W0 4A /r"}, - {"inst": "kandb W:k[7:0], ~k[7:0], ~k[7:0]" , "op": "RVM: VEX.L1.66.0F.W0 41 /r"}, - {"inst": "kandnb W:k[7:0], k[7:0], k[7:0]" , "op": "RVM: VEX.L1.66.0F.W0 42 /r"}, - {"inst": "kmovb W:k[7:0], k[7:0]/m8" , "op": "RM: VEX.L0.66.0F.W0 90 /r"}, - {"inst": "kmovb W:k[7:0], r32[7:0]" , "op": "RM: VEX.L0.66.0F.W0 92 /r"}, - {"inst": "kmovb W:m8, k[7:0]" , "op": "MR: VEX.L0.66.0F.W0 91 /r"}, - {"inst": "kmovb W:r32[7:0], k[7:0]" , "op": "RM: VEX.L0.66.0F.W0 93 /r"}, - {"inst": "knotb W:k[7:0], k[7:0]" , "op": "RM: VEX.L0.66.0F.W0 44 /r"}, - {"inst": "korb W:k[7:0], ~k[7:0], ~k[7:0]" , "op": "RVM: VEX.L1.66.0F.W0 45 /r"}, - {"inst": "kortestb R:~k[7:0], ~k[7:0]" , "op": "RM: VEX.L0.66.0F.W0 98 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "kshiftlb W:k[7:0], k[7:0], ib/ub" , "op": "RM: VEX.L0.66.0F3A.W0 32 /r ib"}, - {"inst": "kshiftrb W:k[7:0], k[7:0], ib/ub" , "op": "RM: VEX.L0.66.0F3A.W0 30 /r ib"}, - {"inst": "ktestb R:~k[7:0], ~k[7:0]" , "op": "RM: VEX.L0.66.0F.W0 99 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "ktestw R:~k[15:0], ~k[15:0]" , "op": "RM: VEX.L0.0F.W0 99 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "kxnorb W:k[7:0], k[7:0], k[7:0]" , "op": "RVM: VEX.L1.66.0F.W0 46 /r"}, - {"inst": "kxorb W:k[7:0], ~k[7:0], ~k[7:0]" , "op": "RVM: VEX.L1.66.0F.W0 47 /r"} - ]}, - - {"category": "AVX512 MASK", "ext": "AVX512_BW", "data": [ - {"inst": "kaddd W:k[31:0], ~k[31:0], ~k[31:0]" , "op": "RVM: VEX.L1.66.0F.W1 4A /r"}, - {"inst": "kaddq W:k[63:0], ~k[63:0], ~k[63:0]" , "op": "RVM: VEX.L1.0F.W1 4A /r"}, - {"inst": "kandd W:k[31:0], ~k[31:0], ~k[31:0]" , "op": "RVM: VEX.L1.66.0F.W1 41 /r"}, - {"inst": "kandnd W:k[31:0], k[31:0], k[31:0]" , "op": "RVM: VEX.L1.66.0F.W1 42 /r"}, - {"inst": "kandnq W:k[63:0], k[63:0], k[63:0]" , "op": "RVM: VEX.L1.0F.W1 42 /r"}, - {"inst": "kandq W:k[63:0], ~k[63:0], ~k[63:0]" , "op": "RVM: VEX.L1.0F.W1 41 /r"}, - {"inst": "kmovd W:k[31:0], k[31:0]/m32" , "op": "RM: VEX.L0.66.0F.W1 90 /r"}, - {"inst": "kmovd W:k[31:0], r32[31:0]" , "op": "RM: VEX.L0.F2.0F.W0 92 /r"}, - {"inst": "kmovd W:m32, k[31:0]" , "op": "MR: VEX.L0.66.0F.W1 91 /r"}, - {"inst": "kmovd W:r32[31:0], k[31:0]" , "op": "RM: VEX.L0.F2.0F.W0 93 /r"}, - {"inst": "kmovq W:k[63:0], k[63:0]/m64" , "op": "RM: VEX.L0.0F.W1 90 /r"}, - {"inst": "kmovq W:k[63:0], r64" , "op": "RM: VEX.L0.F2.0F.W1 92 /r"}, - {"inst": "kmovq W:m64, k[63:0]" , "op": "MR: VEX.L0.0F.W1 91 /r"}, - {"inst": "kmovq W:r64, k[63:0]" , "op": "RM: VEX.L0.F2.0F.W1 93 /r"}, - {"inst": "knotd W:k[31:0], k[31:0]" , "op": "RM: VEX.L0.66.0F.W1 44 /r"}, - {"inst": "knotq W:k[63:0], k[63:0]" , "op": "RM: VEX.L0.0F.W1 44 /r"}, - {"inst": "kord W:k[31:0], ~k[31:0], ~k[31:0]" , "op": "RVM: VEX.L1.66.0F.W1 45 /r"}, - {"inst": "korq W:k[63:0], ~k[63:0], ~k[63:0]" , "op": "RVM: VEX.L1.0F.W1 45 /r"}, - {"inst": "kortestd R:~k[31:0], ~k[31:0]" , "op": "RM: VEX.L0.66.0F.W1 98 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "kortestq R:~k[63:0], ~k[63:0]" , "op": "RM: VEX.L0.0F.W1 98 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "kshiftld W:k[31:0], k[31:0], ib/ub" , "op": "RM: VEX.L0.66.0F3A.W0 33 /r ib"}, - {"inst": "kshiftlq W:k[63:0], k[63:0], ib/ub" , "op": "RM: VEX.L0.66.0F3A.W1 33 /r ib"}, - {"inst": "kshiftrd W:k[31:0], k[31:0], ib/ub" , "op": "RM: VEX.L0.66.0F3A.W0 31 /r ib"}, - {"inst": "kshiftrq W:k[63:0], k[63:0], ib/ub" , "op": "RM: VEX.L0.66.0F3A.W1 31 /r ib"}, - {"inst": "ktestd R:~k[31:0], ~k[31:0]" , "op": "RM: VEX.L0.66.0F.W1 99 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "ktestq R:~k[63:0], ~k[63:0]" , "op": "RM: VEX.L0.0F.W1 99 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, - {"inst": "kunpckdq W:k[63:0], k[31:0], k[31:0]" , "op": "RVM: VEX.L1.0F.W1 4B /r"}, - {"inst": "kunpckwd W:k[31:0], k[15:0], k[15:0]" , "op": "RVM: VEX.L1.0F.W0 4B /r"}, - {"inst": "kxnord W:k[31:0], k[31:0], k[31:0]" , "op": "RVM: VEX.L1.66.0F.W1 46 /r"}, - {"inst": "kxnorq W:k[63:0], k[63:0], k[63:0]" , "op": "RVM: VEX.L1.0F.W1 46 /r"}, - {"inst": "kxord W:k[31:0], ~k[31:0], ~k[31:0]" , "op": "RVM: VEX.L1.66.0F.W1 47 /r"}, - {"inst": "kxorq W:k[63:0], ~k[63:0], ~k[63:0]" , "op": "RVM: VEX.L1.0F.W1 47 /r"} - ]}, - - {"category": "AVX512 SCALAR", "ext": "AVX512_F", "data": [ - {"inst": "vaddsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W1 58 /r" , "vl": 0}, - {"inst": "vaddss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W0 58 /r" , "vl": 0}, - {"inst": "vcmpsd W:k {k}, xmm, xmm[63:0]/m64, ib/ub {sae}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W1 C2 /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vcmpss W:k {k}, xmm, xmm[31:0]/m32, ib/ub {sae}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W0 C2 /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vcomisd R:xmm[63:0], xmm[63:0]/m64 {sae}" , "op": "RM-T1S: EVEX.LIG.66.0F.W1 2F /r" , "vl": 0, "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, - {"inst": "vcomiss R:xmm[31:0], xmm[31:0]/m32 {sae}" , "op": "RM-T1S: EVEX.LIG.0F.W0 2F /r" , "vl": 0, "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, - {"inst": "vcvtsd2si W:r32, xmm[63:0]/m64 {er}" , "op": "RM-T1F: EVEX.LIG.F2.0F.W0 2D /r" , "vl": 0}, - {"inst": "vcvtsd2si W:r64, xmm[63:0]/m64 {er}" , "op": "RM-T1F: EVEX.LIG.F2.0F.W1 2D /r" , "vl": 0}, - {"inst": "vcvtsd2ss W:xmm {kz}, xmm[127:32], xmm[63:0]/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W1 5A /r" , "vl": 0}, - {"inst": "vcvtsd2usi W:r32, xmm[63:0]/m64 {er}" , "op": "RM-T1F: EVEX.LIG.F2.0F.W0 79 /r" , "vl": 0}, - {"inst": "vcvtsd2usi W:r64, xmm[63:0]/m64 {er}" , "op": "RM-T1F: EVEX.LIG.F2.0F.W1 79 /r" , "vl": 0}, - {"inst": "vcvtsi2sd W:xmm, xmm[127:64], r32/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W0 2A /r" , "vl": 0}, - {"inst": "vcvtsi2sd W:xmm, xmm[127:64], r64/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W1 2A /r" , "vl": 0}, - {"inst": "vcvtsi2ss W:xmm, xmm[127:32], r32/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W0 2A /r" , "vl": 0}, - {"inst": "vcvtsi2ss W:xmm, xmm[127:32], r64/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W1 2A /r" , "vl": 0}, - {"inst": "vcvtss2sd W:xmm {kz}, xmm[127:64], xmm[31:0]/m32 {sae}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W0 5A /r" , "vl": 0}, - {"inst": "vcvtss2si W:r32, xmm[31:0]/m32 {er}" , "op": "RM-T1F: EVEX.LIG.F3.0F.W0 2D /r" , "vl": 0}, - {"inst": "vcvtss2si W:r64, xmm[31:0]/m32 {er}" , "op": "RM-T1F: EVEX.LIG.F3.0F.W1 2D /r" , "vl": 0}, - {"inst": "vcvtss2usi W:r32, xmm[31:0]/m32 {er}" , "op": "RM-T1F: EVEX.LIG.F3.0F.W0 79 /r" , "vl": 0}, - {"inst": "vcvtss2usi W:r64, xmm[31:0]/m32 {er}" , "op": "RM-T1F: EVEX.LIG.F3.0F.W1 79 /r" , "vl": 0}, - {"inst": "vcvttsd2si W:r32, xmm[63:0]/m64 {sae}" , "op": "RM-T1F: EVEX.LIG.F2.0F.W0 2C /r" , "vl": 0}, - {"inst": "vcvttsd2si W:r64, xmm[63:0]/m64 {sae}" , "op": "RM-T1F: EVEX.LIG.F2.0F.W1 2C /r" , "vl": 0}, - {"inst": "vcvttsd2usi W:r32, xmm[63:0]/m64 {sae}" , "op": "RM-T1F: EVEX.LIG.F2.0F.W0 78 /r" , "vl": 0}, - {"inst": "vcvttsd2usi W:r64, xmm[63:0]/m64 {sae}" , "op": "RM-T1F: EVEX.LIG.F2.0F.W1 78 /r" , "vl": 0}, - {"inst": "vcvttss2si W:r32, xmm[31:0]/m32 {sae}" , "op": "RM-T1F: EVEX.LIG.F3.0F.W0 2C /r" , "vl": 0}, - {"inst": "vcvttss2si W:r64, xmm[31:0]/m32 {sae}" , "op": "RM-T1F: EVEX.LIG.F3.0F.W1 2C /r" , "vl": 0}, - {"inst": "vcvttss2usi W:r32, xmm[31:0]/m32 {sae}" , "op": "RM-T1F: EVEX.LIG.F3.0F.W0 78 /r" , "vl": 0}, - {"inst": "vcvttss2usi W:r64, xmm[31:0]/m32 {sae}" , "op": "RM-T1F: EVEX.LIG.F3.0F.W1 78 /r" , "vl": 0}, - {"inst": "vcvtusi2sd W:xmm, xmm[127:64], r32/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W0 7B /r" , "vl": 0}, - {"inst": "vcvtusi2sd W:xmm, xmm[127:64], r64/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W1 7B /r" , "vl": 0}, - {"inst": "vcvtusi2ss W:xmm, xmm[127:32], r32/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W0 7B /r" , "vl": 0}, - {"inst": "vcvtusi2ss W:xmm, xmm[127:32], r64/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W1 7B /r" , "vl": 0}, - {"inst": "vdivsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W1 5E /r" , "vl": 0}, - {"inst": "vdivss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W0 5E /r" , "vl": 0}, - {"inst": "vfixupimmsd X:xmm {kz},xmm[127:64],xmm[63:0]/m64,ib/ub {sae}","op": "RVM-T1S: EVEX.LIG.66.0F3A.W1 55 /r ib" , "vl": 0}, - {"inst": "vfixupimmss X:xmm {kz},xmm[127:32],xmm[31:0]/m32,ib/ub {sae}","op": "RVM-T1S: EVEX.LIG.66.0F3A.W0 55 /r ib" , "vl": 0}, - {"inst": "vfmadd132sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 99 /r" , "vl": 0}, - {"inst": "vfmadd132ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 99 /r" , "vl": 0}, - {"inst": "vfmadd213sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 A9 /r" , "vl": 0}, - {"inst": "vfmadd213ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 A9 /r" , "vl": 0}, - {"inst": "vfmadd231sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 B9 /r" , "vl": 0}, - {"inst": "vfmadd231ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 B9 /r" , "vl": 0}, - {"inst": "vfmsub132sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 9B /r" , "vl": 0}, - {"inst": "vfmsub132ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 9B /r" , "vl": 0}, - {"inst": "vfmsub213sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 AB /r" , "vl": 0}, - {"inst": "vfmsub213ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 AB /r" , "vl": 0}, - {"inst": "vfmsub231sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 BB /r" , "vl": 0}, - {"inst": "vfmsub231ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 BB /r" , "vl": 0}, - {"inst": "vfnmadd132sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 9D /r" , "vl": 0}, - {"inst": "vfnmadd132ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 9D /r" , "vl": 0}, - {"inst": "vfnmadd213sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 AD /r" , "vl": 0}, - {"inst": "vfnmadd213ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 AD /r" , "vl": 0}, - {"inst": "vfnmadd231sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 BD /r" , "vl": 0}, - {"inst": "vfnmadd231ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 BD /r" , "vl": 0}, - {"inst": "vfnmsub132sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 9F /r" , "vl": 0}, - {"inst": "vfnmsub132ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 9F /r" , "vl": 0}, - {"inst": "vfnmsub213sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 AF /r" , "vl": 0}, - {"inst": "vfnmsub213ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 AF /r" , "vl": 0}, - {"inst": "vfnmsub231sd X:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 BF /r" , "vl": 0}, - {"inst": "vfnmsub231ss X:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 BF /r" , "vl": 0}, - {"inst": "vgetexpsd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64 {sae}" , "op": "RM-T1S: EVEX.LIG.66.0F38.W1 43 /r" , "vl": 0}, - {"inst": "vgetexpss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32 {sae}" , "op": "RM-T1S: EVEX.LIG.66.0F38.W0 43 /r" , "vl": 0}, - {"inst": "vgetmantsd W:xmm {kz},xmm[127:64],xmm[63:0]/m64,ib/ub {sae}", "op": "RM-T1S: EVEX.LIG.66.0F3A.W1 27 /r ib" , "vl": 0}, - {"inst": "vgetmantss W:xmm {kz},xmm[127:32],xmm[31:0]/m32,ib/ub {sae}", "op": "RM-T1S: EVEX.LIG.66.0F3A.W0 27 /r ib" , "vl": 0}, - {"inst": "vmaxsd W:xmm {kz}, xmm, xmm[63:0]/m64 {sae}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W1 5F /r" , "vl": 0}, - {"inst": "vmaxss W:xmm {kz}, xmm, xmm[31:0]/m32 {sae}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W0 5F /r" , "vl": 0}, - {"inst": "vminsd W:xmm {kz}, xmm, xmm[63:0]/m64 {sae}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W1 5D /r" , "vl": 0}, - {"inst": "vminss W:xmm {kz}, xmm, xmm[31:0]/m32 {sae}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W0 5D /r" , "vl": 0}, - {"inst": "vmovsd W:m64, xmm[63:0]" , "op": "MR-T1S: EVEX.LIG.F2.0F.W1 11 /r" , "vl": 0}, - {"inst": "vmovsd W:xmm[63:0] {kz}, m64" , "op": "MR-T1S: EVEX.LIG.F2.0F.W1 10 /r" , "vl": 0}, - {"inst": "vmovsd W:xmm {kz}, xmm[127:64], xmm[63:0]" , "op": "MVR: EVEX.LIG.F2.0F.W1 11 /r" , "vl": 0}, - {"inst": "vmovsd W:xmm {kz}, xmm[127:64], xmm[63:0]" , "op": "RVM: EVEX.LIG.F2.0F.W1 10 /r" , "vl": 0}, - {"inst": "vmovss W:m32, xmm[31:0]" , "op": "MR-T1S: EVEX.LIG.F3.0F.W0 11 /r" , "vl": 0}, - {"inst": "vmovss W:xmm[31:0] {kz}, m32" , "op": "MR-T1S: EVEX.LIG.F3.0F.W0 10 /r" , "vl": 0}, - {"inst": "vmovss W:xmm {kz}, xmm[127:32], xmm[31:0]" , "op": "MVR: EVEX.LIG.F3.0F.W0 11 /r" , "vl": 0}, - {"inst": "vmovss W:xmm {kz}, xmm[127:32], xmm[31:0]" , "op": "RVM: EVEX.LIG.F3.0F.W0 10 /r" , "vl": 0}, - {"inst": "vmulsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W1 59 /r" , "vl": 0}, - {"inst": "vmulss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W0 59 /r" , "vl": 0}, - {"inst": "vrcp14sd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64" , "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 4D /r" , "vl": 0}, - {"inst": "vrcp14ss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32" , "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 4D /r" , "vl": 0}, - {"inst": "vrndscalesd W:xmm {kz},xmm[127:64],xmm[63:0]/m64,ib/ub {sae}","op": "RVM-T1S: EVEX.LIG.66.0F3A.W1 0B /r ib" , "vl": 0}, - {"inst": "vrndscaless W:xmm {kz},xmm[127:32],xmm[31:0]/m32,ib/ub {sae}","op": "RVM-T1S: EVEX.LIG.66.0F3A.W0 0A /r ib" , "vl": 0}, - {"inst": "vrsqrt14sd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64" , "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 4F /r" , "vl": 0}, - {"inst": "vrsqrt14ss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32" , "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 4F /r" , "vl": 0}, - {"inst": "vscalefsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 2D /r" , "vl": 0}, - {"inst": "vscalefss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 2D /r" , "vl": 0}, - {"inst": "vsqrtsd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W1 51 /r" , "vl": 0}, - {"inst": "vsqrtss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W0 51 /r" , "vl": 0}, - {"inst": "vsubsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.0F.W1 5C /r" , "vl": 0}, - {"inst": "vsubss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.0F.W0 5C /r" , "vl": 0}, - {"inst": "vucomisd R:xmm[63:0], xmm[63:0]/m64 {sae}" , "op": "RM-T1S: EVEX.LIG.66.0F.W1 2E /r" , "vl": 0, "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, - {"inst": "vucomiss R:xmm[31:0], xmm[31:0]/m32 {sae}" , "op": "RM-T1S: EVEX.LIG.0F.W0 2E /r" , "vl": 0, "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_F", "data": [ - {"inst": "vaddpd W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 58 /r" , "vl": 1}, - {"inst": "vaddpd W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 58 /r" , "vl": 1}, - {"inst": "vaddpd W:zmm {kz}, ~zmm, ~zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F.W1 58 /r" , "vl": 0}, - {"inst": "vaddps W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.0F.W0 58 /r" , "vl": 1}, - {"inst": "vaddps W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.0F.W0 58 /r" , "vl": 1}, - {"inst": "vaddps W:zmm {kz}, ~zmm, ~zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.0F.W0 58 /r" , "vl": 0}, - {"inst": "valignd W:xmm {kz}, xmm, xmm/m128/b32, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W0 03 /r ib" , "vl": 1}, - {"inst": "valignd W:ymm {kz}, ymm, ymm/m256/b32, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W0 03 /r ib" , "vl": 1}, - {"inst": "valignd W:zmm {kz}, zmm, zmm/m512/b32, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W0 03 /r ib" , "vl": 0}, - {"inst": "valignq W:xmm {kz}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W1 03 /r ib" , "vl": 1}, - {"inst": "valignq W:ymm {kz}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W1 03 /r ib" , "vl": 1}, - {"inst": "valignq W:zmm {kz}, zmm, zmm/m512/b64, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W1 03 /r ib" , "vl": 0}, - {"inst": "vblendmpd W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 65 /r" , "vl": 1, "k": "blend"}, - {"inst": "vblendmpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 65 /r" , "vl": 1, "k": "blend"}, - {"inst": "vblendmpd W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 65 /r" , "vl": 0, "k": "blend"}, - {"inst": "vblendmps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 65 /r" , "vl": 1, "k": "blend"}, - {"inst": "vblendmps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 65 /r" , "vl": 1, "k": "blend"}, - {"inst": "vblendmps W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 65 /r" , "vl": 0, "k": "blend"}, - {"inst": "vbroadcastf32x4 W:ymm {kz}, m128" , "op": "RM-T4: EVEX.256.66.0F38.W0 1A /r" , "vl": 0}, - {"inst": "vbroadcastf32x4 W:zmm {kz}, m128" , "op": "RM-T4: EVEX.512.66.0F38.W0 1A /r" , "vl": 0}, - {"inst": "vbroadcastf64x4 W:zmm {kz}, m256" , "op": "RM-T4: EVEX.512.66.0F38.W1 1B /r" , "vl": 0}, - {"inst": "vbroadcasti32x4 W:ymm {kz}, m128" , "op": "RM-T4: EVEX.256.66.0F38.W0 5A /r" , "vl": 1}, - {"inst": "vbroadcasti32x4 W:zmm {kz}, m128" , "op": "RM-T4: EVEX.512.66.0F38.W0 5A /r" , "vl": 0}, - {"inst": "vbroadcasti64x4 W:zmm {kz}, m256" , "op": "RM-T4: EVEX.512.66.0F38.W1 5B /r" , "vl": 0}, - {"inst": "vbroadcastsd W:ymm {kz}, xmm[63:0]/m64" , "op": "RM-T1S: EVEX.256.66.0F38.W1 19 /r" , "vl": 1}, - {"inst": "vbroadcastsd W:zmm {kz}, xmm[63:0]/m64" , "op": "RM-T1S: EVEX.512.66.0F38.W1 19 /r" , "vl": 0}, - {"inst": "vbroadcastss W:xmm {kz}, xmm[31:0]/m32" , "op": "RM-T1S: EVEX.128.66.0F38.W0 18 /r" , "vl": 1}, - {"inst": "vbroadcastss W:ymm {kz}, xmm[31:0]/m32" , "op": "RM-T1S: EVEX.256.66.0F38.W0 18 /r" , "vl": 1}, - {"inst": "vbroadcastss W:zmm {kz}, xmm[31:0]/m32" , "op": "RM-T1S: EVEX.512.66.0F38.W0 18 /r" , "vl": 0}, - {"inst": "vcmppd W:k {k}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F.W1 C2 /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vcmppd W:k {k}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F.W1 C2 /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vcmppd W:k {k}, zmm, zmm/m512/b64, ib/ub {sae}" , "op": "RVM-FV: EVEX.512.66.0F.W1 C2 /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vcmpps W:k {k}, xmm, xmm/m128/b32, ib/ub" , "op": "RVM-FV: EVEX.128.0F.W0 C2 /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vcmpps W:k {k}, ymm, ymm/m256/b32, ib/ub" , "op": "RVM-FV: EVEX.256.0F.W0 C2 /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vcmpps W:k {k}, zmm, zmm/m512/b32, ib/ub {sae}" , "op": "RVM-FV: EVEX.512.0F.W0 C2 /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vcompresspd W:xmm/m128 {kz}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W1 8A /r" , "vl": 1}, - {"inst": "vcompresspd W:ymm/m256 {kz}, ymm" , "op": "MR-T1S: EVEX.256.66.0F38.W1 8A /r" , "vl": 1}, - {"inst": "vcompresspd W:zmm/m512 {kz}, zmm" , "op": "MR-T1S: EVEX.512.66.0F38.W1 8A /r" , "vl": 0}, - {"inst": "vcompressps W:xmm/m128 {kz}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W0 8A /r" , "vl": 1}, - {"inst": "vcompressps W:ymm/m256 {kz}, ymm" , "op": "MR-T1S: EVEX.256.66.0F38.W0 8A /r" , "vl": 1}, - {"inst": "vcompressps W:zmm/m512 {kz}, zmm" , "op": "MR-T1S: EVEX.512.66.0F38.W0 8A /r" , "vl": 0}, - {"inst": "vcvtdq2pd W:xmm {kz}, xmm[63:0]/m64/b32" , "op": "RM-HV: EVEX.128.F3.0F.W0 E6 /r" , "vl": 1}, - {"inst": "vcvtdq2pd W:ymm {kz}, xmm/m128/b32" , "op": "RM-HV: EVEX.256.F3.0F.W0 E6 /r" , "vl": 1}, - {"inst": "vcvtdq2pd W:zmm {kz}, ymm/m256/b32" , "op": "RM-HV: EVEX.512.F3.0F.W0 E6 /r" , "vl": 0}, - {"inst": "vcvtdq2ps W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.0F.W0 5B /r" , "vl": 1}, - {"inst": "vcvtdq2ps W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.0F.W0 5B /r" , "vl": 1}, - {"inst": "vcvtdq2ps W:zmm {kz}, zmm/m512/b32 {er}" , "op": "RM-FV: EVEX.512.0F.W0 5B /r" , "vl": 0}, - {"inst": "vcvtpd2ps W:xmm[63:0] {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F.W1 5A /r" , "vl": 1}, - {"inst": "vcvtpd2ps W:xmm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F.W1 5A /r" , "vl": 1}, - {"inst": "vcvtpd2ps W:ymm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.66.0F.W1 5A /r" , "vl": 0}, - {"inst": "vcvtpd2dq W:xmm[63:0] {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.F2.0F.W1 E6 /r" , "vl": 1}, - {"inst": "vcvtpd2dq W:xmm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.F2.0F.W1 E6 /r" , "vl": 1}, - {"inst": "vcvtpd2dq W:ymm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.F2.0F.W1 E6 /r" , "vl": 0}, - {"inst": "vcvtpd2udq W:xmm[63:0] {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.0F.W1 79 /r" , "vl": 1}, - {"inst": "vcvtpd2udq W:xmm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.0F.W1 79 /r" , "vl": 1}, - {"inst": "vcvtpd2udq W:ymm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.0F.W1 79 /r" , "vl": 0}, - {"inst": "vcvtph2ps W:xmm {kz}, xmm[63:0]/m64" , "op": "RM-HVM: EVEX.128.66.0F38.W0 13 /r" , "vl": 1}, - {"inst": "vcvtph2ps W:ymm {kz}, xmm/m128" , "op": "RM-HVM: EVEX.256.66.0F38.W0 13 /r" , "vl": 1}, - {"inst": "vcvtph2ps W:zmm {kz}, ymm/m256 {sae}" , "op": "RM-HVM: EVEX.512.66.0F38.W0 13 /r" , "vl": 0}, - {"inst": "vcvtps2dq W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.66.0F.W0 5B /r" , "vl": 1}, - {"inst": "vcvtps2dq W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.66.0F.W0 5B /r" , "vl": 1}, - {"inst": "vcvtps2dq W:zmm {kz}, zmm/m512/b32 {er}" , "op": "RM-FV: EVEX.512.66.0F.W0 5B /r" , "vl": 0}, - {"inst": "vcvtps2pd W:xmm {kz}, xmm[63:0]/m64/b32" , "op": "RM-HV: EVEX.128.0F.W0 5A /r" , "vl": 1}, - {"inst": "vcvtps2pd W:ymm {kz}, xmm/m128/b32" , "op": "RM-HV: EVEX.256.0F.W0 5A /r" , "vl": 1}, - {"inst": "vcvtps2pd W:zmm {kz}, ymm/m256/b32 {er}" , "op": "RM-HV: EVEX.512.0F.W0 5A /r" , "vl": 0}, - {"inst": "vcvtps2ph W:xmm[63:0]/m64 {kz}, xmm, ib/ub" , "op": "MR-HVM: EVEX.128.66.0F3A.W0 1D /r ib" , "vl": 1}, - {"inst": "vcvtps2ph W:xmm/m128 {kz}, ymm, ib/ub" , "op": "MR-HVM: EVEX.256.66.0F3A.W0 1D /r ib" , "vl": 1}, - {"inst": "vcvtps2ph W:ymm/m256 {kz}, zmm, ib/ub {sae}" , "op": "MR-HVM: EVEX.512.66.0F3A.W0 1D /r ib" , "vl": 0}, - {"inst": "vcvtps2udq W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.0F.W0 79 /r" , "vl": 1}, - {"inst": "vcvtps2udq W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.0F.W0 79 /r" , "vl": 1}, - {"inst": "vcvtps2udq W:zmm {kz}, zmm/m512/b32 {er}" , "op": "RM-FV: EVEX.512.0F.W0 79 /r" , "vl": 0}, - {"inst": "vcvttpd2dq W:xmm[63:0] {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F.W1 E6 /r" , "vl": 1}, - {"inst": "vcvttpd2dq W:xmm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F.W1 E6 /r" , "vl": 1}, - {"inst": "vcvttpd2dq W:ymm {kz}, zmm/m512/b64 {sae}" , "op": "RM-FV: EVEX.512.66.0F.W1 E6 /r" , "vl": 0}, - {"inst": "vcvttpd2qq W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F.W1 7A /r" , "vl": 1}, - {"inst": "vcvttpd2qq W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F.W1 7A /r" , "vl": 1}, - {"inst": "vcvttpd2qq W:zmm {kz}, zmm/m512/b64 {sae}" , "op": "RM-FV: EVEX.512.66.0F.W1 7A /r" , "vl": 0}, - {"inst": "vcvttpd2udq W:xmm[63:0] {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.0F.W1 78 /r" , "vl": 1}, - {"inst": "vcvttpd2udq W:xmm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.0F.W1 78 /r" , "vl": 1}, - {"inst": "vcvttpd2udq W:ymm {kz}, zmm/m512/b64 {sae}" , "op": "RM-FV: EVEX.512.0F.W1 78 /r" , "vl": 0}, - {"inst": "vcvttps2dq W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.F3.0F.W0 5B /r" , "vl": 1}, - {"inst": "vcvttps2dq W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.F3.0F.W0 5B /r" , "vl": 1}, - {"inst": "vcvttps2dq W:zmm {kz}, zmm/m512/b32 {sae}" , "op": "RM-FV: EVEX.512.F3.0F.W0 5B /r" , "vl": 0}, - {"inst": "vcvttps2udq W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.0F.W0 78 /r" , "vl": 1}, - {"inst": "vcvttps2udq W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.0F.W0 78 /r" , "vl": 1}, - {"inst": "vcvttps2udq W:zmm {kz}, zmm/m512/b32 {sae}" , "op": "RM-FV: EVEX.512.0F.W0 78 /r" , "vl": 0}, - {"inst": "vcvtudq2pd W:xmm {kz}, xmm[63:0]/m64/b32" , "op": "RM-HV: EVEX.128.F3.0F.W0 7A /r" , "vl": 1}, - {"inst": "vcvtudq2pd W:ymm {kz}, xmm/m128/b32" , "op": "RM-HV: EVEX.256.F3.0F.W0 7A /r" , "vl": 1}, - {"inst": "vcvtudq2pd W:zmm {kz}, ymm/m256/b32" , "op": "RM-HV: EVEX.512.F3.0F.W0 7A /r" , "vl": 0}, - {"inst": "vcvtudq2ps W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.F2.0F.W0 7A /r" , "vl": 1}, - {"inst": "vcvtudq2ps W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.F2.0F.W0 7A /r" , "vl": 1}, - {"inst": "vcvtudq2ps W:zmm {kz}, zmm/m512/b32 {er}" , "op": "RM-FV: EVEX.512.F2.0F.W0 7A /r" , "vl": 0}, - {"inst": "vdivpd W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 5E /r" , "vl": 1}, - {"inst": "vdivpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 5E /r" , "vl": 1}, - {"inst": "vdivpd W:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F.W1 5E /r" , "vl": 0}, - {"inst": "vdivps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.0F.W0 5E /r" , "vl": 1}, - {"inst": "vdivps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.0F.W0 5E /r" , "vl": 1}, - {"inst": "vdivps W:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.0F.W0 5E /r" , "vl": 0}, - {"inst": "vexpandpd W:xmm {kz}, xmm/m128" , "op": "RM-T1S: EVEX.128.66.0F38.W1 88 /r" , "vl": 1}, - {"inst": "vexpandpd W:ymm {kz}, ymm/m256" , "op": "RM-T1S: EVEX.256.66.0F38.W1 88 /r" , "vl": 1}, - {"inst": "vexpandpd W:zmm {kz}, zmm/m512" , "op": "RM-T1S: EVEX.512.66.0F38.W1 88 /r" , "vl": 0}, - {"inst": "vexpandps W:xmm {kz}, xmm/m128" , "op": "RM-T1S: EVEX.128.66.0F38.W0 88 /r" , "vl": 1}, - {"inst": "vexpandps W:ymm {kz}, ymm/m256" , "op": "RM-T1S: EVEX.256.66.0F38.W0 88 /r" , "vl": 1}, - {"inst": "vexpandps W:zmm {kz}, zmm/m512" , "op": "RM-T1S: EVEX.512.66.0F38.W0 88 /r" , "vl": 0}, - {"inst": "vextractf32x4 W:xmm/m128 {kz}, ymm, ib/ub" , "op": "MR-T4: EVEX.256.66.0F3A.W0 19 /r ib" , "vl": 1}, - {"inst": "vextractf32x4 W:xmm/m128 {kz}, zmm, ib/ub" , "op": "MR-T4: EVEX.512.66.0F3A.W0 19 /r ib" , "vl": 0}, - {"inst": "vextractf64x4 W:ymm/m256 {kz}, zmm, ib/ub" , "op": "MR-T4: EVEX.512.66.0F3A.W1 1B /r ib" , "vl": 0}, - {"inst": "vextracti32x4 W:xmm/m128 {kz}, ymm, ib/ub" , "op": "MR-T4: EVEX.256.66.0F3A.W0 39 /r ib" , "vl": 1}, - {"inst": "vextracti32x4 W:xmm/m128 {kz}, zmm, ib/ub" , "op": "MR-T4: EVEX.512.66.0F3A.W0 39 /r ib" , "vl": 0}, - {"inst": "vextracti64x4 W:ymm/m256 {kz}, zmm, ib/ub" , "op": "MR-T4: EVEX.512.66.0F3A.W1 3B /r ib" , "vl": 0}, - {"inst": "vextractps W:r32[31:0]/m32, xmm, ib/ub" , "op": "MR-T1S: EVEX.128.66.0F3A.WIG 17 /r ib" , "vl": 0}, - {"inst": "vfixupimmpd X:xmm {kz}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W1 54 /r ib" , "vl": 1}, - {"inst": "vfixupimmpd X:ymm {kz}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W1 54 /r ib" , "vl": 1}, - {"inst": "vfixupimmpd X:zmm {kz}, zmm, zmm/m512/b64, ib/ub {sae}" , "op": "RVM-FV: EVEX.512.66.0F3A.W1 54 /r ib" , "vl": 0}, - {"inst": "vfixupimmps X:xmm {kz}, xmm, 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"op": "RVM-FV: EVEX.512.66.0F38.W0 96 /r" , "vl": 0}, - {"inst": "vfmaddsub213pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 A6 /r" , "vl": 1}, - {"inst": "vfmaddsub213pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 A6 /r" , "vl": 1}, - {"inst": "vfmaddsub213pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 A6 /r" , "vl": 0}, - {"inst": "vfmaddsub213ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 A6 /r" , "vl": 1}, - {"inst": "vfmaddsub213ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 A6 /r" , "vl": 1}, - {"inst": "vfmaddsub213ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 A6 /r" , "vl": 0}, - {"inst": "vfmaddsub231pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 B6 /r" , "vl": 1}, - {"inst": "vfmaddsub231pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 B6 /r" , "vl": 1}, - {"inst": "vfmaddsub231pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 B6 /r" , "vl": 0}, - {"inst": "vfmaddsub231ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 B6 /r" , "vl": 1}, - {"inst": "vfmaddsub231ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 B6 /r" , "vl": 1}, - {"inst": "vfmaddsub231ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 B6 /r" , "vl": 0}, - {"inst": "vfmsub132pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 9A /r" , "vl": 1}, - {"inst": "vfmsub132pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 9A /r" , "vl": 1}, - {"inst": "vfmsub132pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 9A /r" , "vl": 0}, - {"inst": "vfmsub132ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 9A /r" , "vl": 1}, - {"inst": "vfmsub132ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 9A /r" , "vl": 1}, - {"inst": "vfmsub132ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 9A /r" , "vl": 0}, - {"inst": "vfmsub213pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 AA /r" , "vl": 1}, - {"inst": "vfmsub213pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 AA /r" , "vl": 1}, - {"inst": "vfmsub213pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 AA /r" , "vl": 0}, - {"inst": "vfmsub213ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 AA /r" , "vl": 1}, - {"inst": "vfmsub213ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 AA /r" , "vl": 1}, - {"inst": "vfmsub213ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 AA /r" , "vl": 0}, - {"inst": "vfmsub231pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 BA /r" , "vl": 1}, - {"inst": "vfmsub231pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 BA /r" , "vl": 1}, - {"inst": "vfmsub231pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 BA /r" , "vl": 0}, - {"inst": "vfmsub231ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 BA /r" , "vl": 1}, - {"inst": "vfmsub231ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 BA /r" , "vl": 1}, - {"inst": "vfmsub231ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 BA /r" , "vl": 0}, - {"inst": "vfmsubadd132pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 97 /r" , "vl": 1}, - {"inst": "vfmsubadd132pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 97 /r" , "vl": 1}, - {"inst": "vfmsubadd132pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 97 /r" , "vl": 0}, - {"inst": "vfmsubadd132ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 97 /r" , "vl": 1}, - {"inst": "vfmsubadd132ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 97 /r" , "vl": 1}, - {"inst": "vfmsubadd132ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 97 /r" , "vl": 0}, - {"inst": "vfmsubadd213pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 A7 /r" , "vl": 1}, - {"inst": "vfmsubadd213pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 A7 /r" , "vl": 1}, - {"inst": "vfmsubadd213pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 A7 /r" , "vl": 0}, - {"inst": "vfmsubadd213ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 A7 /r" , "vl": 1}, - {"inst": "vfmsubadd213ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 A7 /r" , "vl": 1}, - {"inst": "vfmsubadd213ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 A7 /r" , "vl": 0}, - {"inst": "vfmsubadd231pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 B7 /r" , "vl": 1}, - {"inst": "vfmsubadd231pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 B7 /r" , "vl": 1}, - {"inst": "vfmsubadd231pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 B7 /r" , "vl": 0}, - {"inst": "vfmsubadd231ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 B7 /r" , "vl": 1}, - {"inst": "vfmsubadd231ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 B7 /r" , "vl": 1}, - {"inst": "vfmsubadd231ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 B7 /r" , "vl": 0}, - {"inst": "vfnmadd132pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 9C /r" , "vl": 1}, - {"inst": "vfnmadd132pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 9C /r" , "vl": 1}, - {"inst": "vfnmadd132pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 9C /r" , "vl": 0}, - {"inst": "vfnmadd132ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 9C /r" , "vl": 1}, - {"inst": "vfnmadd132ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 9C /r" , "vl": 1}, - {"inst": "vfnmadd132ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 9C /r" , "vl": 0}, - {"inst": "vfnmadd213pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 AC /r" , "vl": 1}, - {"inst": "vfnmadd213pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 AC /r" , "vl": 1}, - {"inst": "vfnmadd213pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 AC /r" , "vl": 0}, - {"inst": "vfnmadd213ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 AC /r" , "vl": 1}, - {"inst": "vfnmadd213ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 AC /r" , "vl": 1}, - {"inst": "vfnmadd213ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 AC /r" , "vl": 0}, - {"inst": "vfnmadd231pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 BC /r" , "vl": 1}, - {"inst": "vfnmadd231pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 BC /r" , "vl": 1}, - {"inst": "vfnmadd231pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 BC /r" , "vl": 0}, - {"inst": "vfnmadd231ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 BC /r" , "vl": 1}, - {"inst": "vfnmadd231ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 BC /r" , "vl": 1}, - {"inst": "vfnmadd231ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 BC /r" , "vl": 0}, - {"inst": "vfnmsub132pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 9E /r" , "vl": 1}, - {"inst": "vfnmsub132pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 9E /r" , "vl": 1}, - {"inst": "vfnmsub132pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 9E /r" , "vl": 0}, - {"inst": "vfnmsub132ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 9E /r" , "vl": 1}, - {"inst": "vfnmsub132ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 9E /r" , "vl": 1}, - {"inst": "vfnmsub132ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 9E /r" , "vl": 0}, - {"inst": "vfnmsub213pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 AE /r" , "vl": 1}, - {"inst": "vfnmsub213pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 AE /r" , "vl": 1}, - {"inst": "vfnmsub213pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 AE /r" , "vl": 0}, - {"inst": "vfnmsub213ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 AE /r" , "vl": 1}, - {"inst": "vfnmsub213ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 AE /r" , "vl": 1}, - {"inst": "vfnmsub213ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 AE /r" , "vl": 0}, - {"inst": "vfnmsub231pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 BE /r" , "vl": 1}, - {"inst": "vfnmsub231pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 BE /r" , "vl": 1}, - {"inst": "vfnmsub231pd X:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 BE /r" , "vl": 0}, - {"inst": "vfnmsub231ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 BE /r" , "vl": 1}, - {"inst": "vfnmsub231ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 BE /r" , "vl": 1}, - {"inst": "vfnmsub231ps X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 BE /r" , "vl": 0}, - {"inst": "vgatherdpd X:xmm {k}, vm32x" , "op": "RM-T1S: EVEX.128.66.0F38.W1 92 /r" , "vl": 1}, - {"inst": "vgatherdpd X:ymm {k}, vm32x" , "op": "RM-T1S: EVEX.256.66.0F38.W1 92 /r" , "vl": 1}, - {"inst": "vgatherdpd X:zmm {k}, vm32y" , "op": "RM-T1S: EVEX.512.66.0F38.W1 92 /r" , "vl": 0}, - {"inst": "vgatherdps X:xmm {k}, vm32x" , "op": "RM-T1S: EVEX.128.66.0F38.W0 92 /r" , "vl": 1}, - {"inst": "vgatherdps X:ymm {k}, vm32y" , "op": "RM-T1S: EVEX.256.66.0F38.W0 92 /r" , "vl": 1}, - {"inst": "vgatherdps X:zmm {k}, vm32z" , "op": "RM-T1S: EVEX.512.66.0F38.W0 92 /r" , "vl": 0}, - {"inst": "vgatherqpd X:xmm {k}, vm64x" , "op": "RM-T1S: EVEX.128.66.0F38.W1 93 /r" , "vl": 1}, - {"inst": "vgatherqpd X:ymm {k}, vm64y" , "op": "RM-T1S: EVEX.256.66.0F38.W1 93 /r" , "vl": 1}, - {"inst": "vgatherqpd X:zmm {k}, vm64z" , "op": "RM-T1S: EVEX.512.66.0F38.W1 93 /r" , "vl": 0}, - {"inst": "vgatherqps X:xmm {k}, vm64x" , "op": "RM-T1S: EVEX.128.66.0F38.W0 93 /r" , "vl": 1}, - {"inst": "vgatherqps X:xmm {k}, vm64y" , "op": "RM-T1S: EVEX.256.66.0F38.W0 93 /r" , "vl": 1}, - {"inst": "vgatherqps X:ymm {k}, vm64z" , "op": "RM-T1S: EVEX.512.66.0F38.W0 93 /r" , "vl": 0}, - {"inst": "vgetexppd W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F38.W1 42 /r" , "vl": 1}, - {"inst": "vgetexppd W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F38.W1 42 /r" , "vl": 1}, - {"inst": "vgetexppd W:zmm {kz}, zmm/m512/b64 {sae}" , "op": "RM-FV: EVEX.512.66.0F38.W1 42 /r" , "vl": 0}, - {"inst": "vgetexpps W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.66.0F38.W0 42 /r" , "vl": 1}, - {"inst": "vgetexpps W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.66.0F38.W0 42 /r" , "vl": 1}, - {"inst": "vgetexpps W:zmm {kz}, zmm/m512/b32 {sae}" , "op": "RM-FV: EVEX.512.66.0F38.W0 42 /r" , "vl": 0}, - {"inst": "vgetmantpd W:xmm {kz}, xmm/m128/b64, ib/ub" , "op": "RM-FV: EVEX.128.66.0F3A.W1 26 /r ib" , "vl": 1}, - {"inst": "vgetmantpd W:ymm {kz}, ymm/m256/b64, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W1 26 /r ib" , "vl": 1}, - {"inst": "vgetmantpd W:zmm {kz}, zmm/m512/b64, ib/ub {sae}" , "op": "RM-FV: EVEX.512.66.0F3A.W1 26 /r ib" , "vl": 0}, - {"inst": "vgetmantps W:xmm {kz}, xmm/m128/b32, ib/ub" , "op": "RM-FV: EVEX.128.66.0F3A.W0 26 /r ib" , "vl": 1}, - {"inst": "vgetmantps W:ymm {kz}, ymm/m256/b32, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W0 26 /r ib" , "vl": 1}, - {"inst": "vgetmantps W:zmm {kz}, zmm/m512/b32, ib/ub {sae}" , "op": "RM-FV: EVEX.512.66.0F3A.W0 26 /r ib" , "vl": 0}, - {"inst": "vinsertf32x4 W:ymm {kz}, ymm, xmm/m128, ib/ub" , "op": "RVM-T4: EVEX.256.66.0F3A.W0 18 /r ib" , "vl": 1}, - {"inst": "vinsertf32x4 W:zmm {kz}, zmm, xmm/m128, ib/ub" , "op": "RVM-T4: EVEX.512.66.0F3A.W0 18 /r ib" , "vl": 0}, - {"inst": "vinsertf64x4 W:zmm {kz}, zmm, ymm/m256, ib/ub" , "op": "RVM-T4: EVEX.512.66.0F3A.W1 1A /r ib" , "vl": 0}, - {"inst": "vinserti32x4 W:ymm {kz}, ymm, xmm/m128, ib/ub" , "op": "RVM-T4: EVEX.256.66.0F3A.W0 38 /r ib" , "vl": 1}, - {"inst": "vinserti32x4 W:zmm {kz}, zmm, xmm/m128, ib/ub" , "op": "RVM-T4: EVEX.512.66.0F3A.W0 38 /r ib" , "vl": 0}, - {"inst": "vinserti64x4 W:zmm {kz}, zmm, ymm/m256, ib/ub" , "op": "RVM-T4: EVEX.512.66.0F3A.W1 3A /r ib" , "vl": 0}, - {"inst": "vinsertps W:xmm, xmm, xmm[31:0]/m32, ib/ub" , "op": "RVM-T1S: EVEX.128.66.0F3A.W0 21 /r ib" , "vl": 0}, - {"inst": "vmaxpd W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 5F /r" , "vl": 1}, - {"inst": "vmaxpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 5F /r" , "vl": 1}, - {"inst": "vmaxpd W:zmm {kz}, zmm, zmm/m512/b64 {sae}" , "op": "RVM-FV: EVEX.512.66.0F.W1 5F /r" , "vl": 0}, - {"inst": "vmaxps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.0F.W0 5F /r" , "vl": 1}, - {"inst": "vmaxps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.0F.W0 5F /r" , "vl": 1}, - {"inst": "vmaxps W:zmm {kz}, zmm, zmm/m512/b32 {sae}" , "op": "RVM-FV: EVEX.512.0F.W0 5F /r" , "vl": 0}, - {"inst": "vminpd W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 5D /r" , "vl": 1}, - {"inst": "vminpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 5D /r" , "vl": 1}, - {"inst": "vminpd W:zmm {kz}, zmm, zmm/m512/b64 {sae}" , "op": "RVM-FV: EVEX.512.66.0F.W1 5D /r" , "vl": 0}, - {"inst": "vminps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.0F.W0 5D /r" , "vl": 1}, - {"inst": "vminps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.0F.W0 5D /r" , "vl": 1}, - {"inst": "vminps W:zmm {kz}, zmm, zmm/m512/b32 {sae}" , "op": "RVM-FV: EVEX.512.0F.W0 5D /r" , "vl": 0}, - {"inst": "vmovapd W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.66.0F.W1 28 /r" , "vl": 1}, - {"inst": "vmovapd W:xmm/m128 {kz}, xmm" , "op": "MR-FVM: EVEX.128.66.0F.W1 29 /r" , "vl": 1}, - {"inst": "vmovapd W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.66.0F.W1 28 /r" , "vl": 1}, - {"inst": "vmovapd W:ymm/m256 {kz}, ymm" , "op": "MR-FVM: EVEX.256.66.0F.W1 29 /r" , "vl": 1}, - {"inst": "vmovapd W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.66.0F.W1 28 /r" , "vl": 0}, - {"inst": "vmovapd W:zmm/m512 {kz}, zmm" , "op": "MR-FVM: EVEX.512.66.0F.W1 29 /r" , "vl": 0}, - {"inst": "vmovaps W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.0F.W0 28 /r" , "vl": 1}, - {"inst": "vmovaps W:xmm/m128 {kz}, xmm" , "op": "MR-FVM: EVEX.128.0F.W0 29 /r" , "vl": 1}, - {"inst": "vmovaps W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.0F.W0 28 /r" , "vl": 1}, - {"inst": "vmovaps W:ymm/m256 {kz}, ymm" , "op": "MR-FVM: EVEX.256.0F.W0 29 /r" , "vl": 1}, - {"inst": "vmovaps W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.0F.W0 28 /r" , "vl": 0}, - {"inst": "vmovaps W:zmm/m512 {kz}, zmm" , "op": "MR-FVM: EVEX.512.0F.W0 29 /r" , "vl": 0}, - {"inst": "vmovd W:r32/m32, xmm[31:0]" , "op": "MR-T1S: EVEX.128.66.0F.W0 7E /r" , "vl": 0}, - {"inst": "vmovd W:xmm[31:0], r32/m32" , "op": "RM-T1S: EVEX.128.66.0F.W0 6E /r" , "vl": 0}, - {"inst": "vmovddup W:xmm {kz}, xmm[63:0]/m64" , "op": "RM-DUP: EVEX.128.F2.0F.W1 12 /r" , "vl": 1}, - {"inst": "vmovddup W:ymm {kz}, ymm/m256" , "op": "RM-DUP: EVEX.256.F2.0F.W1 12 /r" , "vl": 1}, - {"inst": "vmovddup W:zmm {kz}, zmm/m512" , "op": "RM-DUP: EVEX.512.F2.0F.W1 12 /r" , "vl": 0}, - {"inst": "vmovdqa32 W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.66.0F.W0 6F /r" , "vl": 1}, - {"inst": "vmovdqa32 W:xmm/m128 {kz}, xmm" , "op": "MR-FVM: EVEX.128.66.0F.W0 7F /r" , "vl": 1}, - {"inst": "vmovdqa32 W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.66.0F.W0 6F /r" , "vl": 1}, - {"inst": "vmovdqa32 W:ymm/m256 {kz}, ymm" , "op": "MR-FVM: EVEX.256.66.0F.W0 7F /r" , "vl": 1}, - {"inst": "vmovdqa32 W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.66.0F.W0 6F /r" , "vl": 0}, - {"inst": "vmovdqa32 W:zmm/m512 {kz}, zmm" , "op": "MR-FVM: EVEX.512.66.0F.W0 7F /r" , "vl": 0}, - {"inst": "vmovdqa64 W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.66.0F.W1 6F /r" , "vl": 1}, - {"inst": "vmovdqa64 W:xmm/m128 {kz}, xmm" , "op": "MR-FVM: EVEX.128.66.0F.W1 7F /r" , "vl": 1}, - {"inst": "vmovdqa64 W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.66.0F.W1 6F /r" , "vl": 1}, - {"inst": "vmovdqa64 W:ymm/m256 {kz}, ymm" , "op": "MR-FVM: EVEX.256.66.0F.W1 7F /r" , "vl": 1}, - {"inst": "vmovdqa64 W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.66.0F.W1 6F /r" , "vl": 0}, - {"inst": "vmovdqa64 W:zmm/m512 {kz}, zmm" , "op": "MR-FVM: EVEX.512.66.0F.W1 7F /r" , "vl": 0}, - {"inst": "vmovdqu32 W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.F3.0F.W0 6F /r" , "vl": 1}, - {"inst": "vmovdqu32 W:xmm/m128 {kz}, xmm" , "op": "MR-FVM: EVEX.128.F3.0F.W0 7F /r" , "vl": 1}, - {"inst": "vmovdqu32 W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.F3.0F.W0 6F /r" , "vl": 1}, - {"inst": "vmovdqu32 W:ymm/m256 {kz}, ymm" , "op": "MR-FVM: EVEX.256.F3.0F.W0 7F /r" , "vl": 1}, - {"inst": "vmovdqu32 W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.F3.0F.W0 6F /r" , "vl": 0}, - {"inst": "vmovdqu32 W:zmm/m512 {kz}, zmm" , "op": "MR-FVM: EVEX.512.F3.0F.W0 7F /r" , "vl": 0}, - {"inst": "vmovdqu64 W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.F3.0F.W1 6F /r" , "vl": 1}, - {"inst": "vmovdqu64 W:xmm/m128 {kz}, xmm" , "op": "MR-FVM: EVEX.128.F3.0F.W1 7F /r" , "vl": 1}, - {"inst": "vmovdqu64 W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.F3.0F.W1 6F /r" , "vl": 1}, - {"inst": "vmovdqu64 W:ymm/m256 {kz}, ymm" , "op": "MR-FVM: EVEX.256.F3.0F.W1 7F /r" , "vl": 1}, - {"inst": "vmovdqu64 W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.F3.0F.W1 6F /r" , "vl": 0}, - {"inst": "vmovdqu64 W:zmm/m512 {kz}, zmm" , "op": "MR-FVM: EVEX.512.F3.0F.W1 7F /r" , "vl": 0}, - {"inst": "vmovhlps W:xmm, xmm[127:64], xmm[127:64]" , "op": "RVM: EVEX.128.0F.W0 12 /r" , "vl": 0}, - {"inst": "vmovhpd W:m64, xmm[127:64]" , "op": "MR-T1S: EVEX.128.66.0F.W1 17 /r" , "vl": 0}, - {"inst": "vmovhpd W:xmm, xmm[63:0], m64" , "op": "RVM-T1S: EVEX.128.66.0F.W1 16 /r" , "vl": 0}, - {"inst": "vmovhps W:m64, xmm[127:64]" , "op": "MR-T2: EVEX.128.0F.W0 17 /r" , "vl": 0}, - {"inst": "vmovhps W:xmm, xmm[63:0], m64" , "op": "RVM-T2: EVEX.128.0F.W0 16 /r" , "vl": 0}, - {"inst": "vmovlhps W:xmm, xmm[63:0], xmm[63:0]" , "op": "RVM: EVEX.128.0F.W0 16 /r" , "vl": 0}, - {"inst": "vmovlpd W:m64, xmm[63:0]" , "op": "MR-T1S: EVEX.128.66.0F.W1 13 /r" , "vl": 0}, - {"inst": "vmovlpd W:xmm, xmm[127:64], m64" , "op": "RVM-T1S: EVEX.128.66.0F.W1 12 /r" , "vl": 0}, - {"inst": "vmovlps W:m64, xmm[63:0]" , "op": "MR-T2: EVEX.128.0F.W0 13 /r" , "vl": 0}, - {"inst": "vmovlps W:xmm, xmm[127:64], m64" , "op": "RVM-T2: EVEX.128.0F.W0 12 /r" , "vl": 0}, - {"inst": "vmovntdq W:m128, xmm" , "op": "MR-FVM: EVEX.128.66.0F.W0 E7 /r" , "vl": 1}, - {"inst": "vmovntdq W:m256, ymm" , "op": "MR-FVM: EVEX.256.66.0F.W0 E7 /r" , "vl": 1}, - {"inst": "vmovntdq W:m512, zmm" , "op": "MR-FVM: EVEX.512.66.0F.W0 E7 /r" , "vl": 0}, - {"inst": "vmovntdqa W:xmm, m128" , "op": "RM-FVM: EVEX.128.66.0F38.W0 2A /r" , "vl": 1}, - {"inst": "vmovntdqa W:ymm, m256" , "op": "RM-FVM: EVEX.256.66.0F38.W0 2A /r" , "vl": 1}, - {"inst": "vmovntdqa W:zmm, m512" , "op": "RM-FVM: EVEX.512.66.0F38.W0 2A /r" , "vl": 0}, - {"inst": "vmovntpd W:m128, xmm" , "op": "MR-FVM: EVEX.128.66.0F.W1 2B /r" , "vl": 1}, - {"inst": "vmovntpd W:m256, ymm" , "op": "MR-FVM: EVEX.256.66.0F.W1 2B /r" , "vl": 1}, - {"inst": "vmovntpd W:m512, zmm" , "op": "MR-FVM: EVEX.512.66.0F.W1 2B /r" , "vl": 0}, - {"inst": "vmovntps W:m128, xmm" , "op": "MR-FVM: EVEX.128.66.0F.W0 2B /r" , "vl": 1}, - {"inst": "vmovntps W:m256, ymm" , "op": "MR-FVM: EVEX.256.66.0F.W0 2B /r" , "vl": 1}, - {"inst": "vmovntps W:m512, zmm" , "op": "MR-FVM: EVEX.512.0F.W0 2B /r" , "vl": 0}, - {"inst": "vmovq W:r64/m64, xmm[63:0]" , "op": "MR-T1S: EVEX.128.66.0F.W1 7E /r" , "vl": 0}, - {"inst": "vmovq W:xmm[63:0], r64/m64" , "op": "RM-T1S: EVEX.128.66.0F.W1 6E /r" , "vl": 0}, - {"inst": "vmovq W:xmm[63:0], xmm[63:0]/m64" , "op": "RM-T1S: EVEX.128.F3.0F.W1 7E /r" , "vl": 0}, - {"inst": "vmovq W:xmm[63:0]/m64, xmm[63:0]" , "op": "MR-T1S: EVEX.128.66.0F.W1 D6 /r" , "vl": 0}, - {"inst": "vmovshdup W:xmm {kz}, xmm/m128" , "op": "RVM-FVM: EVEX.128.F3.0F.W0 16 /r" , "vl": 1}, - {"inst": "vmovshdup W:ymm {kz}, ymm/m256" , "op": "RVM-FVM: EVEX.256.F3.0F.W0 16 /r" , "vl": 1}, - {"inst": "vmovshdup W:zmm {kz}, zmm/m512" , "op": "RVM-FVM: EVEX.512.F3.0F.W0 16 /r" , "vl": 0}, - {"inst": "vmovsldup W:xmm {kz}, xmm/m128" , "op": "RVM-FVM: EVEX.128.F3.0F.W0 12 /r" , "vl": 1}, - {"inst": "vmovsldup W:ymm {kz}, ymm/m256" , "op": "RVM-FVM: EVEX.256.F3.0F.W0 12 /r" , "vl": 1}, - {"inst": "vmovsldup W:zmm {kz}, zmm/m512" , "op": "RVM-FVM: EVEX.512.F3.0F.W0 12 /r" , "vl": 0}, - {"inst": "vmovupd W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.66.0F.W1 10 /r" , "vl": 1}, - {"inst": "vmovupd W:xmm/m128 {kz}, xmm" , "op": "MR-FVM: EVEX.128.66.0F.W1 11 /r" , "vl": 1}, - {"inst": "vmovupd W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.66.0F.W1 11 /r" , "vl": 1}, - {"inst": "vmovupd W:ymm/m256 {kz}, ymm" , "op": "MR-FVM: EVEX.256.66.0F.W1 10 /r" , "vl": 1}, - {"inst": "vmovupd W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.66.0F.W1 10 /r" , "vl": 0}, - {"inst": "vmovupd W:zmm/m512 {kz}, zmm" , "op": "MR-FVM: EVEX.512.66.0F.W1 11 /r" , "vl": 0}, - {"inst": "vmovups W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.0F.W0 10 /r" , "vl": 1}, - {"inst": "vmovups W:xmm/m128 {kz}, xmm" , "op": "MR-FVM: EVEX.128.0F.W0 11 /r" , "vl": 1}, - {"inst": "vmovups W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.0F.W0 10 /r" , "vl": 1}, - {"inst": "vmovups W:ymm/m256 {kz}, ymm" , "op": "MR-FVM: EVEX.256.0F.W0 11 /r" , "vl": 1}, - {"inst": "vmovups W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.0F.W0 10 /r" , "vl": 0}, - {"inst": "vmovups W:zmm/m512 {kz}, zmm" , "op": "MR-FVM: EVEX.512.0F.W0 11 /r" , "vl": 0}, - {"inst": "vmulpd W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 59 /r" , "vl": 1}, - {"inst": "vmulpd W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 59 /r" , "vl": 1}, - {"inst": "vmulpd W:zmm {kz}, ~zmm, ~zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F.W1 59 /r" , "vl": 0}, - {"inst": "vmulps W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.0F.W0 59 /r" , "vl": 1}, - {"inst": "vmulps W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.0F.W0 59 /r" , "vl": 1}, - {"inst": "vmulps W:zmm {kz}, ~zmm, ~zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.0F.W0 59 /r" , "vl": 0}, - {"inst": "vpabsd W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.66.0F38.W0 1E /r" , "vl": 1}, - {"inst": "vpabsd W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.66.0F38.W0 1E /r" , "vl": 1}, - {"inst": "vpabsd W:zmm {kz}, zmm/m512/b32" , "op": "RM-FV: EVEX.512.66.0F38.W0 1E /r" , "vl": 0}, - {"inst": "vpabsq W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F38.W1 1F /r" , "vl": 1}, - {"inst": "vpabsq W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F38.W1 1F /r" , "vl": 1}, - {"inst": "vpabsq W:zmm {kz}, zmm/m512/b64" , "op": "RM-FV: EVEX.512.66.0F38.W1 1F /r" , "vl": 0}, - {"inst": "vpaddd W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F.W0 FE /r" , "vl": 1}, - {"inst": "vpaddd W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F.W0 FE /r" , "vl": 1}, - {"inst": "vpaddd W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F.W0 FE /r" , "vl": 0}, - {"inst": "vpaddq W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 D4 /r" , "vl": 1}, - {"inst": "vpaddq W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 D4 /r" , "vl": 1}, - {"inst": "vpaddq W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 D4 /r" , "vl": 0}, - {"inst": "vpandd W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F.W0 DB /r" , "vl": 1}, - {"inst": "vpandd W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F.W0 DB /r" , "vl": 1}, - {"inst": "vpandd W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F.W0 DB /r" , "vl": 0}, - {"inst": "vpandnd W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F.W0 DF /r" , "vl": 1}, - {"inst": "vpandnd W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F.W0 DF /r" , "vl": 1}, - {"inst": "vpandnd W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F.W0 DF /r" , "vl": 0}, - {"inst": "vpandnq W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 DF /r" , "vl": 1}, - {"inst": "vpandnq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 DF /r" , "vl": 1}, - {"inst": "vpandnq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 DF /r" , "vl": 0}, - {"inst": "vpandq W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 DB /r" , "vl": 1}, - {"inst": "vpandq W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 DB /r" , "vl": 1}, - {"inst": "vpandq W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 DB /r" , "vl": 0}, - {"inst": "vpblendmd W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 64 /r" , "vl": 1, "k": "blend"}, - {"inst": "vpblendmd W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 64 /r" , "vl": 1, "k": "blend"}, - {"inst": "vpblendmd W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 64 /r" , "vl": 0, "k": "blend"}, - {"inst": "vpblendmq W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 64 /r" , "vl": 1, "k": "blend"}, - {"inst": "vpblendmq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 64 /r" , "vl": 1, "k": "blend"}, - {"inst": "vpblendmq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 64 /r" , "vl": 0, "k": "blend"}, - {"inst": "vpbroadcastd W:xmm {kz}, r32[31:0]" , "op": "RM-T1S: EVEX.128.66.0F38.W0 7C /r" , "vl": 1}, - {"inst": "vpbroadcastd W:xmm {kz}, xmm[31:0]/m32" , "op": "RM-T1S: EVEX.128.66.0F38.W0 58 /r" , "vl": 1}, - {"inst": "vpbroadcastd W:ymm {kz}, r32[31:0]" , "op": "RM-T1S: EVEX.256.66.0F38.W0 7C /r" , "vl": 1}, - {"inst": "vpbroadcastd W:ymm {kz}, xmm[31:0]/m32" , "op": "RM-T1S: EVEX.256.66.0F38.W0 58 /r" , "vl": 1}, - {"inst": "vpbroadcastd W:zmm {kz}, r32[31:0]" , "op": "RM-T1S: EVEX.512.66.0F38.W0 7C /r" , "vl": 0}, - {"inst": "vpbroadcastd W:zmm {kz}, xmm[31:0]/m32" , "op": "RM-T1S: EVEX.512.66.0F38.W0 58 /r" , "vl": 0}, - {"inst": "vpbroadcastq W:xmm {kz}, r64" , "op": "RM-T1S: EVEX.128.66.0F38.W1 7C /r" , "vl": 1}, - {"inst": "vpbroadcastq W:xmm {kz}, xmm[63:0]/m64" , "op": "RM-T1S: EVEX.128.66.0F38.W1 59 /r" , "vl": 1}, - {"inst": "vpbroadcastq W:ymm {kz}, r64" , "op": "RM-T1S: EVEX.256.66.0F38.W1 7C /r" , "vl": 1}, - {"inst": "vpbroadcastq W:ymm {kz}, xmm[63:0]/m64" , "op": "RM-T1S: EVEX.256.66.0F38.W1 59 /r" , "vl": 1}, - {"inst": "vpbroadcastq W:zmm {kz}, r64" , "op": "RM-T1S: EVEX.512.66.0F38.W1 7C /r" , "vl": 0}, - {"inst": "vpbroadcastq W:zmm {kz}, xmm[63:0]/m64" , "op": "RM-T1S: EVEX.512.66.0F38.W1 59 /r" , "vl": 0}, - {"inst": "vpcmpd W:k {k}, xmm, xmm/m128/b32, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W0 1F /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpd W:k {k}, ymm, ymm/m256/b32, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W0 1F /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpd W:k {k}, zmm, zmm/m512/b32, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W0 1F /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpeqd W:k {k}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FVM: EVEX.128.66.0F.W0 76 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpeqd W:k {k}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FVM: EVEX.256.66.0F.W0 76 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpeqd W:k {k}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FVM: EVEX.512.66.0F.W0 76 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpeqq W:k {k}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 29 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpeqq W:k {k}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 29 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpeqq W:k {k}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 29 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpgtd W:k {k}, xmm, xmm/m128/b32" , "op": "RVM-FVM: EVEX.128.66.0F.W0 66 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpgtd W:k {k}, ymm, ymm/m256/b32" , "op": "RVM-FVM: EVEX.256.66.0F.W0 66 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpgtd W:k {k}, zmm, zmm/m512/b32" , "op": "RVM-FVM: EVEX.512.66.0F.W0 66 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpgtq W:k {k}, xmm, xmm/m128/b64" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 37 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpgtq W:k {k}, ymm, ymm/m256/b64" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 37 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpgtq W:k {k}, zmm, zmm/m512/b64" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 37 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpq W:k {k}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W1 1F /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpq W:k {k}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W1 1F /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpq W:k {k}, zmm, zmm/m512/b64, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W1 1F /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpud W:k {k}, xmm, xmm/m128/b32, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W0 1E /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpud W:k {k}, ymm, ymm/m256/b32, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W0 1E /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpud W:k {k}, zmm, zmm/m512/b32, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W0 1E /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpuq W:k {k}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W1 1E /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpuq W:k {k}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W1 1E /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpuq W:k {k}, zmm, zmm/m512/b64, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W1 1E /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcompressd W:xmm/m128 {kz}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W0 8B /r" , "vl": 1}, - {"inst": "vpcompressd W:ymm/m256 {kz}, ymm" , "op": "MR-T1S: EVEX.256.66.0F38.W0 8B /r" , "vl": 1}, - {"inst": "vpcompressd W:zmm/m512 {kz}, zmm" , "op": "MR-T1S: EVEX.512.66.0F38.W0 8B /r" , "vl": 0}, - {"inst": "vpcompressq W:xmm/m128 {kz}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W1 8B /r" , "vl": 1}, - {"inst": "vpcompressq W:ymm/m256 {kz}, ymm" , "op": "MR-T1S: EVEX.256.66.0F38.W1 8B /r" , "vl": 1}, - {"inst": "vpcompressq W:zmm/m512 {kz}, zmm" , "op": "MR-T1S: EVEX.512.66.0F38.W1 8B /r" , "vl": 0}, - {"inst": "vpermd W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 36 /r" , "vl": 1}, - {"inst": "vpermd W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 36 /r" , "vl": 0}, - {"inst": "vpermi2d X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 76 /r" , "vl": 1}, - {"inst": "vpermi2d X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 76 /r" , "vl": 1}, - {"inst": "vpermi2d X:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 76 /r" , "vl": 0}, - {"inst": "vpermi2pd W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 77 /r" , "vl": 1}, - {"inst": "vpermi2pd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 77 /r" , "vl": 1}, - {"inst": "vpermi2pd W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 77 /r" , "vl": 0}, - {"inst": "vpermi2ps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 77 /r" , "vl": 1}, - {"inst": "vpermi2ps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 77 /r" , "vl": 1}, - {"inst": "vpermi2ps W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 77 /r" , "vl": 0}, - {"inst": "vpermi2q X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 76 /r" , "vl": 1}, - {"inst": "vpermi2q X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 76 /r" , "vl": 1}, - {"inst": "vpermi2q X:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 76 /r" , "vl": 0}, - {"inst": "vpermilpd W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 0D /r" , "vl": 1}, - {"inst": "vpermilpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 0D /r" , "vl": 1}, - {"inst": "vpermilpd W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 0D /r" , "vl": 0}, - {"inst": "vpermilpd W:xmm {kz}, xmm/m128/b64, ib/ub" , "op": "RM-FV: EVEX.128.66.0F3A.W1 05 /r ib" , "vl": 1}, - {"inst": "vpermilpd W:ymm {kz}, ymm/m256/b64, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W1 05 /r ib" , "vl": 1}, - {"inst": "vpermilpd W:zmm {kz}, zmm/m512/b64, ib/ub" , "op": "RM-FV: EVEX.512.66.0F3A.W1 05 /r ib" , "vl": 0}, - {"inst": "vpermilps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 0C /r" , "vl": 1}, - {"inst": "vpermilps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 0C /r" , "vl": 1}, - {"inst": "vpermilps W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 0C /r" , "vl": 0}, - {"inst": "vpermilps W:xmm {kz}, xmm/m128/b32, ib/ub" , "op": "RM-FV: EVEX.128.66.0F3A.W0 04 /r ib" , "vl": 1}, - {"inst": "vpermilps W:ymm {kz}, ymm/m256/b32, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W0 04 /r ib" , "vl": 1}, - {"inst": "vpermilps W:zmm {kz}, zmm/m512/b32, ib/ub" , "op": "RM-FV: EVEX.512.66.0F3A.W0 04 /r ib" , "vl": 0}, - {"inst": "vpermpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 16 /r" , "vl": 1}, - {"inst": "vpermpd W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 16 /r" , "vl": 0}, - {"inst": "vpermpd W:ymm {kz}, ymm/m256/b64, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W1 01 /r ib" , "vl": 1}, - {"inst": "vpermpd W:zmm {kz}, zmm/m512/b64, ib/ub" , "op": "RM-FV: EVEX.512.66.0F3A.W1 01 /r ib" , "vl": 0}, - {"inst": "vpermps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 16 /r" , "vl": 1}, - {"inst": "vpermps W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 16 /r" , "vl": 0}, - {"inst": "vpermq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 36 /r" , "vl": 1}, - {"inst": "vpermq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 36 /r" , "vl": 0}, - {"inst": "vpermq W:ymm {kz}, ymm/m256/b64, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W1 00 /r ib" , "vl": 1}, - {"inst": "vpermq W:zmm {kz}, zmm/m512/b64, ib/ub" , "op": "RM-FV: EVEX.512.66.0F3A.W1 00 /r ib" , "vl": 0}, - {"inst": "vpermt2d X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 7E /r" , "vl": 1}, - {"inst": "vpermt2d X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 7E /r" , "vl": 1}, - {"inst": "vpermt2d X:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 7E /r" , "vl": 0}, - {"inst": "vpermt2pd X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 7F /r" , "vl": 1}, - {"inst": "vpermt2pd X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 7F /r" , "vl": 1}, - {"inst": "vpermt2pd X:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 7F /r" , "vl": 0}, - {"inst": "vpermt2ps X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 7F /r" , "vl": 1}, - {"inst": "vpermt2ps X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 7F /r" , "vl": 1}, - {"inst": "vpermt2ps X:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 7F /r" , "vl": 0}, - {"inst": "vpermt2q X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 7E /r" , "vl": 1}, - {"inst": "vpermt2q X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 7E /r" , "vl": 1}, - {"inst": "vpermt2q X:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 7E /r" , "vl": 0}, - {"inst": "vpexpandd W:xmm {kz}, xmm/m128" , "op": "RM-T1S: EVEX.128.66.0F38.W0 89 /r" , "vl": 1}, - {"inst": "vpexpandd W:ymm {kz}, ymm/m256" , "op": "RM-T1S: EVEX.256.66.0F38.W0 89 /r" , "vl": 1}, - {"inst": "vpexpandd W:zmm {kz}, zmm/m512" , "op": "RM-T1S: EVEX.512.66.0F38.W0 89 /r" , "vl": 0}, - {"inst": "vpexpandq W:xmm {kz}, xmm/m128" , "op": "RM-T1S: EVEX.128.66.0F38.W1 89 /r" , "vl": 1}, - {"inst": "vpexpandq W:ymm {kz}, ymm/m256" , "op": "RM-T1S: EVEX.256.66.0F38.W1 89 /r" , "vl": 1}, - {"inst": "vpexpandq W:zmm {kz}, zmm/m512" , "op": "RM-T1S: EVEX.512.66.0F38.W1 89 /r" , "vl": 0}, - {"inst": "vpgatherdd X:xmm {k}, vm32x" , "op": "RM-T1S: EVEX.128.66.0F38.W0 90" , "vl": 1}, - {"inst": "vpgatherdd X:ymm {k}, vm32y" , "op": "RM-T1S: EVEX.256.66.0F38.W0 90" , "vl": 1}, - {"inst": "vpgatherdd X:zmm {k}, vm32z" , "op": "RM-T1S: EVEX.512.66.0F38.W0 90" , "vl": 0}, - {"inst": "vpgatherdq X:xmm {k}, vm32x" , "op": "RM-T1S: EVEX.128.66.0F38.W1 90" , "vl": 1}, - {"inst": "vpgatherdq X:ymm {k}, vm32x" , "op": "RM-T1S: EVEX.256.66.0F38.W1 90" , "vl": 1}, - {"inst": "vpgatherdq X:zmm {k}, vm32y" , "op": "RM-T1S: EVEX.512.66.0F38.W1 90" , "vl": 0}, - {"inst": "vpgatherqd X:xmm {k}, vm64x" , "op": "RM-T1S: EVEX.128.66.0F38.W0 91" , "vl": 1}, - {"inst": "vpgatherqd X:xmm {k}, vm64y" , "op": "RM-T1S: EVEX.256.66.0F38.W0 91" , "vl": 1}, - {"inst": "vpgatherqd X:ymm {k}, vm64z" , "op": "RM-T1S: EVEX.512.66.0F38.W0 91" , "vl": 0}, - {"inst": "vpgatherqq X:xmm {k}, vm64x" , "op": "RM-T1S: EVEX.128.66.0F38.W1 91" , "vl": 1}, - {"inst": "vpgatherqq X:ymm {k}, vm64y" , "op": "RM-T1S: EVEX.256.66.0F38.W1 91" , "vl": 1}, - {"inst": "vpgatherqq X:zmm {k}, vm64z" , "op": "RM-T1S: EVEX.512.66.0F38.W1 91" , "vl": 0}, - {"inst": "vpmaxsd W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 3D /r" , "vl": 1}, - {"inst": "vpmaxsd W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 3D /r" , "vl": 1}, - {"inst": "vpmaxsd W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 3D /r" , "vl": 0}, - {"inst": "vpmaxsq W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 3D /r" , "vl": 1}, - {"inst": "vpmaxsq W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 3D /r" , "vl": 1}, - {"inst": "vpmaxsq W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 3D /r" , "vl": 0}, - {"inst": "vpmaxud W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 3F /r" , "vl": 1}, - {"inst": "vpmaxud W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 3F /r" , "vl": 1}, - {"inst": "vpmaxud W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 3F /r" , "vl": 0}, - {"inst": "vpmaxuq W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 3F /r" , "vl": 1}, - {"inst": "vpmaxuq W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 3F /r" , "vl": 1}, - {"inst": "vpmaxuq W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 3F /r" , "vl": 0}, - {"inst": "vpminsd W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 39 /r" , "vl": 1}, - {"inst": "vpminsd W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 39 /r" , "vl": 1}, - {"inst": "vpminsd W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 39 /r" , "vl": 0}, - {"inst": "vpminsq W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 39 /r" , "vl": 1}, - {"inst": "vpminsq W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 39 /r" , "vl": 1}, - {"inst": "vpminsq W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 39 /r" , "vl": 0}, - {"inst": "vpminud W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 3B /r" , "vl": 1}, - {"inst": "vpminud W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 3B /r" , "vl": 1}, - {"inst": "vpminud W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 3B /r" , "vl": 0}, - {"inst": "vpminuq W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 3B /r" , "vl": 1}, - {"inst": "vpminuq W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 3B /r" , "vl": 1}, - {"inst": "vpminuq W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 3B /r" , "vl": 0}, - {"inst": "vpmovdb W:xmm[31:0]/m32 {kz}, xmm" , "op": "MR-QVM: EVEX.128.F3.0F38.W0 31 /r" , "vl": 1}, - {"inst": "vpmovdb W:xmm[63:0]/m64 {kz}, ymm" , "op": "MR-QVM: EVEX.256.F3.0F38.W0 31 /r" , "vl": 1}, - {"inst": "vpmovdb W:xmm/m128 {kz}, zmm" , "op": "MR-QVM: EVEX.512.F3.0F38.W0 31 /r" , "vl": 0}, - {"inst": "vpmovdw W:xmm[63:0]/m64 {kz}, xmm" , "op": "MR-HVM: EVEX.128.F3.0F38.W0 33 /r" , "vl": 1}, - {"inst": "vpmovdw W:xmm/m128 {kz}, ymm" , "op": "MR-HVM: EVEX.256.F3.0F38.W0 33 /r" , "vl": 1}, - {"inst": "vpmovdw W:ymm/m256 {kz}, zmm" , "op": "MR-HVM: EVEX.512.F3.0F38.W0 33 /r" , "vl": 0}, - {"inst": "vpmovqb W:xmm[15:0]/m16 {kz}, xmm" , "op": "MR-OVM: EVEX.128.F3.0F38.W0 32 /r" , "vl": 1}, - {"inst": "vpmovqb W:xmm[31:0]/m32 {kz}, ymm" , "op": "MR-OVM: EVEX.256.F3.0F38.W0 32 /r" , "vl": 1}, - {"inst": "vpmovqb W:xmm[63:0]/m64 {kz}, zmm" , "op": "MR-OVM: EVEX.512.F3.0F38.W0 32 /r" , "vl": 0}, - {"inst": "vpmovqd W:xmm[63:0]/m64 {kz}, xmm" , "op": "MR-HVM: EVEX.128.F3.0F38.W0 35 /r" , "vl": 1}, - {"inst": "vpmovqd W:xmm/m128 {kz}, ymm" , "op": "MR-HVM: EVEX.256.F3.0F38.W0 35 /r" , "vl": 1}, - {"inst": "vpmovqd W:ymm/m256 {kz}, zmm" , "op": "MR-HVM: EVEX.512.F3.0F38.W0 35 /r" , "vl": 0}, - {"inst": "vpmovqw W:xmm[31:0]/m32 {kz}, xmm" , "op": "MR-QVM: EVEX.128.F3.0F38.W0 34 /r" , "vl": 1}, - {"inst": "vpmovqw W:xmm[63:0]/m64 {kz}, ymm" , "op": "MR-QVM: EVEX.256.F3.0F38.W0 34 /r" , "vl": 1}, - {"inst": "vpmovqw W:xmm/m128 {kz}, zmm" , "op": "MR-QVM: EVEX.512.F3.0F38.W0 34 /r" , "vl": 0}, - {"inst": "vpmovsdb W:xmm[31:0]/m32 {kz}, xmm" , "op": "MR-QVM: EVEX.128.F3.0F38.W0 21 /r" , "vl": 1}, - {"inst": "vpmovsdb W:xmm[63:0]/m64 {kz}, ymm" , "op": "MR-QVM: EVEX.256.F3.0F38.W0 21 /r" , "vl": 1}, - {"inst": "vpmovsdb W:xmm/m128 {kz}, zmm" , "op": "MR-QVM: EVEX.512.F3.0F38.W0 21 /r" , "vl": 0}, - {"inst": "vpmovsdw W:xmm[63:0]/m64 {kz}, xmm" , "op": "MR-HVM: EVEX.128.F3.0F38.W0 23 /r" , "vl": 1}, - {"inst": "vpmovsdw W:xmm/m128 {kz}, ymm" , "op": "MR-HVM: EVEX.256.F3.0F38.W0 23 /r" , "vl": 1}, - {"inst": "vpmovsdw W:ymm/m256 {kz}, zmm" , "op": "MR-HVM: EVEX.512.F3.0F38.W0 23 /r" , "vl": 0}, - {"inst": "vpmovsqb W:xmm[15:0]/m16 {kz}, xmm" , "op": "MR-OVM: EVEX.128.F3.0F38.W0 22 /r" , "vl": 1}, - {"inst": "vpmovsqb W:xmm[31:0]/m32 {kz}, ymm" , "op": "MR-OVM: EVEX.256.F3.0F38.W0 22 /r" , "vl": 1}, - {"inst": "vpmovsqb W:xmm[63:0]/m64 {kz}, zmm" , "op": "MR-OVM: EVEX.512.F3.0F38.W0 22 /r" , "vl": 0}, - {"inst": "vpmovsqd W:xmm[63:0]/m64 {kz}, xmm" , "op": "MR-HVM: EVEX.128.F3.0F38.W0 25 /r" , "vl": 1}, - {"inst": "vpmovsqd W:xmm/m128 {kz}, ymm" , "op": "MR-HVM: EVEX.256.F3.0F38.W0 25 /r" , "vl": 1}, - {"inst": "vpmovsqd W:ymm/m256 {kz}, zmm" , "op": "MR-HVM: EVEX.512.F3.0F38.W0 25 /r" , "vl": 0}, - {"inst": "vpmovsqw W:xmm[31:0]/m32 {kz}, xmm" , "op": "MR-QVM: EVEX.128.F3.0F38.W0 24 /r" , "vl": 1}, - {"inst": "vpmovsqw W:xmm[63:0]/m64 {kz}, ymm" , "op": "MR-QVM: EVEX.256.F3.0F38.W0 24 /r" , "vl": 1}, - {"inst": "vpmovsqw W:xmm/m128 {kz}, zmm" , "op": "MR-QVM: EVEX.512.F3.0F38.W0 24 /r" , "vl": 0}, - {"inst": "vpmovsxbd W:xmm {kz}, xmm[31:0]/m32" , "op": "RM-QVM: EVEX.128.66.0F38.WIG 21 /r" , "vl": 1}, - {"inst": "vpmovsxbd W:ymm {kz}, xmm[63:0]/m64" , "op": "RM-QVM: EVEX.256.66.0F38.WIG 21 /r" , "vl": 1}, - {"inst": "vpmovsxbd W:zmm {kz}, xmm/m128" , "op": "RM-QVM: EVEX.512.66.0F38.WIG 21 /r" , "vl": 0}, - {"inst": "vpmovsxbq W:xmm {kz}, xmm[15:0]/m16" , "op": "RM-OVM: EVEX.128.66.0F38.WIG 22 /r" , "vl": 1}, - {"inst": "vpmovsxbq W:ymm {kz}, xmm[31:0]/m32" , "op": "RM-OVM: EVEX.256.66.0F38.WIG 22 /r" , "vl": 1}, - {"inst": "vpmovsxbq W:zmm {kz}, xmm[63:0]/m64" , "op": "RM-OVM: EVEX.512.66.0F38.WIG 22 /r" , "vl": 0}, - {"inst": "vpmovsxdq W:xmm {kz}, xmm[63:0]/m64" , "op": "RM-HVM: EVEX.128.66.0F38.W0 25 /r" , "vl": 1}, - {"inst": "vpmovsxdq W:ymm {kz}, xmm/m128" , "op": "RM-HVM: EVEX.256.66.0F38.W0 25 /r" , "vl": 1}, - {"inst": "vpmovsxdq W:zmm {kz}, ymm/m256" , "op": "RM-HVM: EVEX.512.66.0F38.W0 25 /r" , "vl": 0}, - {"inst": "vpmovsxwd W:xmm {kz}, xmm[63:0]/m64" , "op": "RM-HVM: EVEX.128.66.0F38.WIG 23 /r" , "vl": 1}, - {"inst": "vpmovsxwd W:ymm {kz}, xmm/m128" , "op": "RM-HVM: EVEX.256.66.0F38.WIG 23 /r" , "vl": 1}, - {"inst": "vpmovsxwd W:zmm {kz}, ymm/m256" , "op": "RM-HVM: EVEX.512.66.0F38.WIG 23 /r" , "vl": 0}, - {"inst": "vpmovsxwq W:xmm {kz}, xmm[31:0]/m32" , "op": "RM-QVM: EVEX.128.66.0F38.WIG 24 /r" , "vl": 1}, - {"inst": "vpmovsxwq W:ymm {kz}, xmm[63:0]/m64" , "op": "RM-QVM: EVEX.256.66.0F38.WIG 24 /r" , "vl": 1}, - {"inst": "vpmovsxwq W:zmm {kz}, xmm/m128" , "op": "RM-QVM: EVEX.512.66.0F38.WIG 24 /r" , "vl": 0}, - {"inst": "vpmovusdb W:xmm[31:0]/m32 {kz}, xmm" , "op": "MR-QVM: EVEX.128.F3.0F38.W0 11 /r" , "vl": 1}, - {"inst": "vpmovusdb W:xmm[63:0]/m64 {kz}, ymm" , "op": "MR-QVM: EVEX.256.F3.0F38.W0 11 /r" , "vl": 1}, - {"inst": "vpmovusdb W:xmm/m128 {kz}, zmm" , "op": "MR-QVM: EVEX.512.F3.0F38.W0 11 /r" , "vl": 0}, - {"inst": "vpmovusdw W:xmm[63:0]/m64 {kz}, xmm" , "op": "MR-HVM: EVEX.128.F3.0F38.W0 13 /r" , "vl": 1}, - {"inst": "vpmovusdw W:xmm/m128 {kz}, ymm" , "op": "MR-HVM: EVEX.256.F3.0F38.W0 13 /r" , "vl": 1}, - {"inst": "vpmovusdw W:ymm/m256 {kz}, zmm" , "op": "MR-HVM: EVEX.512.F3.0F38.W0 13 /r" , "vl": 0}, - {"inst": "vpmovusqb W:xmm[15:0]/m16 {kz}, xmm" , "op": "MR-OVM: EVEX.128.F3.0F38.W0 12 /r" , "vl": 1}, - {"inst": "vpmovusqb W:xmm[31:0]/m32 {kz}, ymm" , "op": "MR-OVM: EVEX.256.F3.0F38.W0 12 /r" , "vl": 1}, - {"inst": "vpmovusqb W:xmm[63:0]/m64 {kz}, zmm" , "op": "MR-OVM: EVEX.512.F3.0F38.W0 12 /r" , "vl": 0}, - {"inst": "vpmovusqd W:xmm[63:0]/m64 {kz}, xmm" , "op": "MR-HVM: EVEX.128.F3.0F38.W0 15 /r" , "vl": 1}, - {"inst": "vpmovusqd W:xmm/m128 {kz}, ymm" , "op": "MR-HVM: EVEX.256.F3.0F38.W0 15 /r" , "vl": 1}, - {"inst": "vpmovusqd W:ymm/m256 {kz}, zmm" , "op": "MR-HVM: EVEX.512.F3.0F38.W0 15 /r" , "vl": 0}, - {"inst": "vpmovusqw W:xmm[31:0]/m32 {kz}, xmm" , "op": "MR-QVM: EVEX.128.F3.0F38.W0 14 /r" , "vl": 1}, - {"inst": "vpmovusqw W:xmm[63:0]/m64 {kz}, ymm" , "op": "MR-QVM: EVEX.256.F3.0F38.W0 14 /r" , "vl": 1}, - {"inst": "vpmovusqw W:xmm/m128 {kz}, zmm" , "op": "MR-QVM: EVEX.512.F3.0F38.W0 14 /r" , "vl": 0}, - {"inst": "vpmovzxbd W:xmm {kz}, xmm[31:0]/m32" , "op": "RM-QVM: EVEX.128.66.0F38.WIG 31 /r" , "vl": 1}, - {"inst": "vpmovzxbd W:ymm {kz}, xmm[63:0]/m64" , "op": "RM-QVM: EVEX.256.66.0F38.WIG 31 /r" , "vl": 1}, - {"inst": "vpmovzxbd W:zmm {kz}, xmm/m128" , "op": "RM-QVM: EVEX.512.66.0F38.WIG 31 /r" , "vl": 0}, - {"inst": "vpmovzxbq W:xmm {kz}, xmm[15:0]/m16" , "op": "RM-OVM: EVEX.128.66.0F38.WIG 32 /r" , "vl": 1}, - {"inst": "vpmovzxbq W:ymm {kz}, xmm[31:0]/m32" , "op": "RM-OVM: EVEX.256.66.0F38.WIG 32 /r" , "vl": 1}, - {"inst": "vpmovzxbq W:zmm {kz}, xmm[63:0]/m64" , "op": "RM-OVM: EVEX.512.66.0F38.WIG 32 /r" , "vl": 0}, - {"inst": "vpmovzxdq W:xmm {kz}, xmm[63:0]/m64" , "op": "RM-HVM: EVEX.128.66.0F38.W0 35 /r" , "vl": 1}, - {"inst": "vpmovzxdq W:ymm {kz}, xmm/m128" , "op": "RM-HVM: EVEX.256.66.0F38.W0 35 /r" , "vl": 1}, - {"inst": "vpmovzxdq W:zmm {kz}, ymm/m256" , "op": "RM-HVM: EVEX.512.66.0F38.W0 35 /r" , "vl": 0}, - {"inst": "vpmovzxwd W:xmm {kz}, xmm[63:0]/m64" , "op": "RM-HVM: EVEX.128.66.0F38.WIG 33 /r" , "vl": 1}, - {"inst": "vpmovzxwd W:ymm {kz}, xmm/m128" , "op": "RM-HVM: EVEX.256.66.0F38.WIG 33 /r" , "vl": 1}, - {"inst": "vpmovzxwd W:zmm {kz}, ymm/m256" , "op": "RM-HVM: EVEX.512.66.0F38.WIG 33 /r" , "vl": 0}, - {"inst": "vpmovzxwq W:xmm {kz}, xmm[31:0]/m32" , "op": "RM-QVM: EVEX.128.66.0F38.WIG 34 /r" , "vl": 1}, - {"inst": "vpmovzxwq W:ymm {kz}, xmm[63:0]/m64" , "op": "RM-QVM: EVEX.256.66.0F38.WIG 34 /r" , "vl": 1}, - {"inst": "vpmovzxwq W:zmm {kz}, xmm/m128" , "op": "RM-QVM: EVEX.512.66.0F38.WIG 34 /r" , "vl": 0}, - {"inst": "vpmuldq W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 28 /r" , "vl": 1}, - {"inst": "vpmuldq W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 28 /r" , "vl": 1}, - {"inst": "vpmuldq W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 28 /r" , "vl": 0}, - {"inst": "vpmulld W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 40 /r" , "vl": 1}, - {"inst": "vpmulld W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 40 /r" , "vl": 1}, - {"inst": "vpmulld W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 40 /r" , "vl": 0}, - {"inst": "vpmuludq W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 F4 /r" , "vl": 1}, - {"inst": "vpmuludq W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 F4 /r" , "vl": 1}, - {"inst": "vpmuludq W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 F4 /r" , "vl": 0}, - {"inst": "vpord W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F.W0 EB /r" , "vl": 1}, - {"inst": "vpord W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F.W0 EB /r" , "vl": 1}, - {"inst": "vpord W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F.W0 EB /r" , "vl": 0}, - {"inst": "vporq W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 EB /r" , "vl": 1}, - {"inst": "vporq W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 EB /r" , "vl": 1}, - {"inst": "vporq W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 EB /r" , "vl": 0}, - {"inst": "vprold W:xmm {kz}, xmm/m128/b32, ib/ub" , "op": "VM-FV: EVEX.128.66.0F.W0 72 /1 ib" , "vl": 1}, - {"inst": "vprold W:ymm {kz}, ymm/m256/b32, ib/ub" , "op": "VM-FV: EVEX.256.66.0F.W0 72 /1 ib" , "vl": 1}, - {"inst": "vprold W:zmm {kz}, zmm/m512/b32, ib/ub" , "op": "VM-FV: EVEX.512.66.0F.W0 72 /1 ib" , "vl": 0}, - {"inst": "vprolq W:xmm {kz}, xmm/m128/b64, ib/ub" , "op": "VM-FV: EVEX.128.66.0F.W1 72 /1 ib" , "vl": 1}, - {"inst": "vprolq W:ymm {kz}, ymm/m256/b64, ib/ub" , "op": "VM-FV: EVEX.256.66.0F.W1 72 /1 ib" , "vl": 1}, - {"inst": "vprolq W:zmm {kz}, zmm/m512/b64, ib/ub" , "op": "VM-FV: EVEX.512.66.0F.W1 72 /1 ib" , "vl": 0}, - {"inst": "vprolvd W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 15 /r" , "vl": 1}, - {"inst": "vprolvd W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 15 /r" , "vl": 1}, - {"inst": "vprolvd W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 15 /r" , "vl": 0}, - {"inst": "vprolvq W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 15 /r" , "vl": 1}, - {"inst": "vprolvq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 15 /r" , "vl": 1}, - {"inst": "vprolvq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 15 /r" , "vl": 0}, - {"inst": "vprord W:xmm {kz}, xmm/m128/b32, ib/ub" , "op": "VM-FV: EVEX.128.66.0F.W0 72 /0 ib" , "vl": 1}, - {"inst": "vprord W:ymm {kz}, ymm/m256/b32, ib/ub" , "op": "VM-FV: EVEX.256.66.0F.W0 72 /0 ib" , "vl": 1}, - {"inst": "vprord W:zmm {kz}, zmm/m512/b32, ib/ub" , "op": "VM-FV: EVEX.512.66.0F.W0 72 /0 ib" , "vl": 0}, - {"inst": "vprorq W:xmm {kz}, xmm/m128/b64, ib/ub" , "op": "VM-FV: EVEX.128.66.0F.W1 72 /0 ib" , "vl": 1}, - {"inst": "vprorq W:ymm {kz}, ymm/m256/b64, ib/ub" , "op": "VM-FV: EVEX.256.66.0F.W1 72 /0 ib" , "vl": 1}, - {"inst": "vprorq W:zmm {kz}, zmm/m512/b64, ib/ub" , "op": "VM-FV: EVEX.512.66.0F.W1 72 /0 ib" , "vl": 0}, - {"inst": "vprorvd W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 14 /r" , "vl": 1}, - {"inst": "vprorvd W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 14 /r" , "vl": 1}, - {"inst": "vprorvd W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 14 /r" , "vl": 0}, - {"inst": "vprorvq W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 14 /r" , "vl": 1}, - {"inst": "vprorvq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 14 /r" , "vl": 1}, - {"inst": "vprorvq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 14 /r" , "vl": 0}, - {"inst": "vpscatterdd W:vm32x {k}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W0 A0 /r" , "vl": 1}, - {"inst": "vpscatterdd W:vm32y {k}, ymm" , "op": "MR-T1S: EVEX.256.66.0F38.W0 A0 /r" , "vl": 1}, - {"inst": "vpscatterdd W:vm32z {k}, zmm" , "op": "MR-T1S: EVEX.512.66.0F38.W0 A0 /r" , "vl": 0}, - {"inst": "vpscatterdq W:vm32x {k}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W1 A0 /r" , "vl": 1}, - {"inst": "vpscatterdq W:vm32x {k}, ymm" , "op": "MR-T1S: EVEX.256.66.0F38.W1 A0 /r" , "vl": 1}, - {"inst": "vpscatterdq W:vm32y {k}, zmm" , "op": "MR-T1S: EVEX.512.66.0F38.W1 A0 /r" , "vl": 0}, - {"inst": "vpscatterqd W:vm64x {k}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W0 A1 /r" , "vl": 1}, - {"inst": "vpscatterqd W:vm64y {k}, xmm" , "op": "MR-T1S: EVEX.256.66.0F38.W0 A1 /r" , "vl": 1}, - {"inst": "vpscatterqd W:vm64z {k}, ymm" , "op": "MR-T1S: EVEX.512.66.0F38.W0 A1 /r" , "vl": 0}, - {"inst": "vpscatterqq W:vm64x {k}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W1 A1 /r" , "vl": 1}, - {"inst": "vpscatterqq W:vm64y {k}, ymm" , "op": "MR-T1S: EVEX.256.66.0F38.W1 A1 /r" , "vl": 1}, - {"inst": "vpscatterqq W:vm64z {k}, zmm" , "op": "MR-T1S: EVEX.512.66.0F38.W1 A1 /r" , "vl": 0}, - {"inst": "vpshufd W:xmm {kz}, xmm/m128/b32, ib/ub" , "op": "RM-FV: EVEX.128.66.0F.W0 70 /r ib" , "vl": 1}, - {"inst": "vpshufd W:ymm {kz}, ymm/m256/b32, ib/ub" , "op": "RM-FV: EVEX.256.66.0F.W0 70 /r ib" , "vl": 1}, - {"inst": "vpshufd W:zmm {kz}, zmm/m512/b32, ib/ub" , "op": "RM-FV: EVEX.512.66.0F.W0 70 /r ib" , "vl": 0}, - {"inst": "vpslld W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-M128: EVEX.128.66.0F.W0 F2 /r" , "vl": 1}, - {"inst": "vpslld W:xmm {kz}, xmm/m128/b32, ib/ub" , "op": "VM-FV: EVEX.128.66.0F.W0 72 /6 ib" , "vl": 1}, - {"inst": "vpslld W:ymm {kz}, ymm, xmm/m128" , "op": "RVM-M128: EVEX.256.66.0F.W0 F2 /r" , "vl": 1}, - {"inst": "vpslld W:ymm {kz}, ymm/m256/b32, ib/ub" , "op": "VM-FV: EVEX.256.66.0F.W0 72 /6 ib" , "vl": 1}, - {"inst": "vpslld W:zmm {kz}, zmm, xmm/m128" , "op": "RVM-M128: EVEX.512.66.0F.W0 F2 /r" , "vl": 0}, - {"inst": "vpslld W:zmm {kz}, zmm/m512/b32, ib/ub" , "op": "VM-FV: EVEX.512.66.0F.W0 72 /6 ib" , "vl": 0}, - {"inst": "vpsllq W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-M128: EVEX.128.66.0F.W1 F3 /r" , "vl": 1}, - {"inst": "vpsllq W:xmm {kz}, xmm/m128/b64, ib/ub" , "op": "VM-FV: EVEX.128.66.0F.W1 73 /6 ib" , "vl": 1}, - {"inst": "vpsllq W:ymm {kz}, ymm, xmm/m128" , "op": "RVM-M128: EVEX.256.66.0F.W1 F3 /r" , "vl": 1}, - {"inst": "vpsllq W:ymm {kz}, ymm/m256/b64, ib/ub" , "op": "VM-FV: EVEX.256.66.0F.W1 73 /6 ib" , "vl": 1}, - {"inst": "vpsllq W:zmm {kz}, zmm, xmm/m128" , "op": "RVM-M128: EVEX.512.66.0F.W1 F3 /r" , "vl": 0}, - {"inst": "vpsllq W:zmm {kz}, zmm/m512/b64, ib/ub" , "op": "VM-FV: EVEX.512.66.0F.W1 73 /6 ib" , "vl": 0}, - {"inst": "vpsllvd W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 47 /r" , "vl": 1}, - {"inst": "vpsllvd W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 47 /r" , "vl": 1}, - {"inst": "vpsllvd W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 47 /r" , "vl": 0}, - {"inst": "vpsllvq W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 47 /r" , "vl": 1}, - {"inst": "vpsllvq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 47 /r" , "vl": 1}, - {"inst": "vpsllvq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 47 /r" , "vl": 0}, - {"inst": "vpsrad W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-M128: EVEX.128.66.0F.W0 E2 /r" , "vl": 1}, - {"inst": "vpsrad W:xmm {kz}, xmm/m128/b32, ib/ub" , "op": "VM-FV: EVEX.128.66.0F.W0 72 /4 ib" , "vl": 1}, - {"inst": "vpsrad W:ymm {kz}, ymm, xmm/m128" , "op": "RVM-M128: EVEX.256.66.0F.W0 E2 /r" , "vl": 1}, - {"inst": "vpsrad W:ymm {kz}, ymm/m256/b32, ib/ub" , "op": "VM-FV: EVEX.256.66.0F.W0 72 /4 ib" , "vl": 1}, - {"inst": "vpsrad W:zmm {kz}, zmm, xmm/m128" , "op": "RVM-M128: EVEX.512.66.0F.W0 E2 /r" , "vl": 0}, - {"inst": "vpsrad W:zmm {kz}, zmm/m512/b32, ib/ub" , "op": "VM-FV: EVEX.512.66.0F.W0 72 /4 ib" , "vl": 0}, - {"inst": "vpsraq W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-M128: EVEX.128.66.0F.W1 E2 /r" , "vl": 1}, - {"inst": "vpsraq W:xmm {kz}, xmm/m128/b64, ib/ub" , "op": "VM-FV: EVEX.128.66.0F.W1 72 /4 ib" , "vl": 1}, - {"inst": "vpsraq W:ymm {kz}, ymm, xmm/m128" , "op": "RVM-M128: EVEX.256.66.0F.W1 E2 /r" , "vl": 1}, - {"inst": "vpsraq W:ymm {kz}, ymm/m256/b64, ib/ub" , "op": "VM-FV: EVEX.256.66.0F.W1 72 /4 ib" , "vl": 1}, - {"inst": "vpsraq W:zmm {kz}, zmm, xmm/m128" , "op": "RVM-M128: EVEX.512.66.0F.W1 E2 /r" , "vl": 0}, - {"inst": "vpsraq W:zmm {kz}, zmm/m512/b64, ib/ub" , "op": "VM-FV: EVEX.512.66.0F.W1 72 /4 ib" , "vl": 0}, - {"inst": "vpsravd W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 46 /r" , "vl": 1}, - {"inst": "vpsravd W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 46 /r" , "vl": 1}, - {"inst": "vpsravd W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 46 /r" , "vl": 0}, - {"inst": "vpsravq W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 46 /r" , "vl": 1}, - {"inst": "vpsravq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 46 /r" , "vl": 1}, - {"inst": "vpsravq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 46 /r" , "vl": 0}, - {"inst": "vpsrld W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-M128: EVEX.128.66.0F.W0 D2 /r" , "vl": 1}, - {"inst": "vpsrld W:xmm {kz}, xmm/m128/b32, ib/ub" , "op": "VM-FV: EVEX.128.66.0F.W0 72 /2 ib" , "vl": 1}, - {"inst": "vpsrld W:ymm {kz}, ymm, xmm/m128" , "op": "RVM-M128: EVEX.256.66.0F.W0 D2 /r" , "vl": 1}, - {"inst": "vpsrld W:ymm {kz}, ymm/m256/b32, ib/ub" , "op": "VM-FV: EVEX.256.66.0F.W0 72 /2 ib" , "vl": 1}, - {"inst": "vpsrld W:zmm {kz}, zmm, xmm/m128" , "op": "RVM-M128: EVEX.512.66.0F.W0 D2 /r" , "vl": 0}, - {"inst": "vpsrld W:zmm {kz}, zmm/m512/b32, ib/ub" , "op": "VM-FV: EVEX.512.66.0F.W0 72 /2 ib" , "vl": 0}, - {"inst": "vpsrlq W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-M128: EVEX.128.66.0F.W1 D3 /r" , "vl": 1}, - {"inst": "vpsrlq W:xmm {kz}, xmm/m128/b64, ib/ub" , "op": "VM-FV: EVEX.128.66.0F.W1 73 /2 ib" , "vl": 1}, - {"inst": "vpsrlq W:ymm {kz}, ymm, xmm/m128" , "op": "RVM-M128: EVEX.256.66.0F.W1 D3 /r" , "vl": 1}, - {"inst": "vpsrlq W:ymm {kz}, ymm/m256/b64, ib/ub" , "op": "VM-FV: EVEX.256.66.0F.W1 73 /2 ib" , "vl": 1}, - {"inst": "vpsrlq W:zmm {kz}, zmm, xmm/m128" , "op": "RVM-M128: EVEX.512.66.0F.W1 D3 /r" , "vl": 0}, - {"inst": "vpsrlq W:zmm {kz}, zmm/m512/b64, ib/ub" , "op": "VM-FV: EVEX.512.66.0F.W1 73 /2 ib" , "vl": 0}, - {"inst": "vpsrlvd W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 45 /r" , "vl": 1}, - {"inst": "vpsrlvd W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 45 /r" , "vl": 1}, - {"inst": "vpsrlvd W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 45 /r" , "vl": 0}, - {"inst": "vpsrlvq W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 45 /r" , "vl": 1}, - {"inst": "vpsrlvq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 45 /r" , "vl": 1}, - {"inst": "vpsrlvq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 45 /r" , "vl": 0}, - {"inst": "vpsubd W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F.W0 FA /r" , "vl": 1}, - {"inst": "vpsubd W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F.W0 FA /r" , "vl": 1}, - {"inst": "vpsubd W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F.W0 FA /r" , "vl": 0}, - {"inst": "vpsubq W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 FB /r" , "vl": 1}, - {"inst": "vpsubq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 FB /r" , "vl": 1}, - {"inst": "vpsubq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 FB /r" , "vl": 0}, - {"inst": "vpternlogd X:xmm {kz}, xmm, xmm/m128/b32, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W0 25 /r ib" , "vl": 1}, - {"inst": "vpternlogd X:ymm {kz}, ymm, ymm/m256/b32, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W0 25 /r ib" , "vl": 1}, - {"inst": "vpternlogd X:zmm {kz}, zmm, zmm/m512/b32, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W0 25 /r ib" , "vl": 0}, - {"inst": "vpternlogq X:xmm {kz}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W1 25 /r ib" , "vl": 1}, - {"inst": "vpternlogq X:ymm {kz}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W1 25 /r ib" , "vl": 1}, - {"inst": "vpternlogq X:zmm {kz}, zmm, zmm/m512/b64, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W1 25 /r ib" , "vl": 0}, - {"inst": "vptestmd W:k {k}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 27 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestmd W:k {k}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 27 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestmd W:k {k}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 27 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vptestmq W:k {k}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 27 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestmq W:k {k}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 27 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestmq W:k {k}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 27 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vptestnmd W:k {k}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.F3.0F38.W0 27 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestnmd W:k {k}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.F3.0F38.W0 27 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestnmd W:k {k}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.F3.0F38.W0 27 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vptestnmq W:k {k}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.F3.0F38.W1 27 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestnmq W:k {k}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.F3.0F38.W1 27 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestnmq W:k {k}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.F3.0F38.W1 27 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vpunpckhdq W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F.W0 6A /r" , "vl": 1}, - {"inst": "vpunpckhdq W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F.W0 6A /r" , "vl": 1}, - {"inst": "vpunpckhdq W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F.W0 6A /r" , "vl": 0}, - {"inst": "vpunpckhqdq W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 6D /r" , "vl": 1}, - {"inst": "vpunpckhqdq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 6D /r" , "vl": 1}, - {"inst": "vpunpckhqdq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 6D /r" , "vl": 0}, - {"inst": "vpunpckldq W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F.W0 62 /r" , "vl": 1}, - {"inst": "vpunpckldq W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F.W0 62 /r" , "vl": 1}, - {"inst": "vpunpckldq W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F.W0 62 /r" , "vl": 0}, - {"inst": "vpunpcklqdq W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 6C /r" , "vl": 1}, - {"inst": "vpunpcklqdq W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 6C /r" , "vl": 1}, - {"inst": "vpunpcklqdq W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 6C /r" , "vl": 0}, - {"inst": "vpxord W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F.W0 EF /r" , "vl": 1}, - {"inst": "vpxord W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F.W0 EF /r" , "vl": 1}, - {"inst": "vpxord W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F.W0 EF /r" , "vl": 0}, - {"inst": "vpxorq W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 EF /r" , "vl": 1}, - {"inst": "vpxorq W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 EF /r" , "vl": 1}, - {"inst": "vpxorq W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 EF /r" , "vl": 0}, - {"inst": "vrcp14pd W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F38.W1 4C /r" , "vl": 1}, - {"inst": "vrcp14pd W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F38.W1 4C /r" , "vl": 1}, - {"inst": "vrcp14pd W:zmm {kz}, zmm/m512/b64" , "op": "RM-FV: EVEX.512.66.0F38.W1 4C /r" , "vl": 0}, - {"inst": "vrcp14ps W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.66.0F38.W0 4C /r" , "vl": 1}, - {"inst": "vrcp14ps W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.66.0F38.W0 4C /r" , "vl": 1}, - {"inst": "vrcp14ps W:zmm {kz}, zmm/m512/b32" , "op": "RM-FV: EVEX.512.66.0F38.W0 4C /r" , "vl": 0}, - {"inst": "vrndscalepd W:xmm {kz}, xmm/m128/b64, ib/ub" , "op": "RM-FV: EVEX.128.66.0F3A.W1 09 /r ib" , "vl": 1}, - {"inst": "vrndscalepd W:ymm {kz}, ymm/m256/b64, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W1 09 /r ib" , "vl": 1}, - {"inst": "vrndscalepd W:zmm {kz}, zmm/m512/b64, ib/ub {sae}" , "op": "RM-FV: EVEX.512.66.0F3A.W1 09 /r ib" , "vl": 0}, - {"inst": "vrndscaleps W:xmm {kz}, xmm/m128/b32, ib/ub" , "op": "RM-FV: EVEX.128.66.0F3A.W0 08 /r ib" , "vl": 1}, - {"inst": "vrndscaleps W:ymm {kz}, ymm/m256/b32, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W0 08 /r ib" , "vl": 1}, - {"inst": "vrndscaleps W:zmm {kz}, zmm/m512/b32, ib/ub {sae}" , "op": "RM-FV: EVEX.512.66.0F3A.W0 08 /r ib" , "vl": 0}, - {"inst": "vrsqrt14pd W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F38.W1 4E /r" , "vl": 1}, - {"inst": "vrsqrt14pd W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F38.W1 4E /r" , "vl": 1}, - {"inst": "vrsqrt14pd W:zmm {kz}, zmm/m512/b64" , "op": "RM-FV: EVEX.512.66.0F38.W1 4E /r" , "vl": 0}, - {"inst": "vrsqrt14ps W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.66.0F38.W0 4E /r" , "vl": 1}, - {"inst": "vrsqrt14ps W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.66.0F38.W0 4E /r" , "vl": 1}, - {"inst": "vrsqrt14ps W:zmm {kz}, zmm/m512/b32" , "op": "RM-FV: EVEX.512.66.0F38.W0 4E /r" , "vl": 0}, - {"inst": "vscalefpd W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 2C /r" , "vl": 1}, - {"inst": "vscalefpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 2C /r" , "vl": 1}, - {"inst": "vscalefpd W:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W1 2C /r" , "vl": 0}, - {"inst": "vscalefps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 2C /r" , "vl": 1}, - {"inst": "vscalefps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 2C /r" , "vl": 1}, - {"inst": "vscalefps W:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.66.0F38.W0 2C /r" , "vl": 0}, - {"inst": "vscatterdpd W:vm32x {k}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W1 A2 /r" , "vl": 1}, - {"inst": "vscatterdpd W:vm32x {k}, ymm" , "op": "MR-T1S: EVEX.256.66.0F38.W1 A2 /r" , "vl": 1}, - {"inst": "vscatterdpd W:vm32y {k}, zmm" , "op": "MR-T1S: EVEX.512.66.0F38.W1 A2 /r" , "vl": 0}, - {"inst": "vscatterdps W:vm32x {k}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W0 A2 /r" , "vl": 1}, - {"inst": "vscatterdps W:vm32y {k}, ymm" , "op": "MR-T1S: EVEX.256.66.0F38.W0 A2 /r" , "vl": 1}, - {"inst": "vscatterdps W:vm32z {k}, zmm" , "op": "MR-T1S: EVEX.512.66.0F38.W0 A2 /r" , "vl": 0}, - {"inst": "vscatterqpd W:vm64x {k}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W1 A3" , "vl": 1}, - {"inst": "vscatterqpd W:vm64y {k}, ymm" , "op": "MR-T1S: EVEX.256.66.0F38.W1 A3" , "vl": 1}, - {"inst": "vscatterqpd W:vm64z {k}, zmm" , "op": "MR-T1S: EVEX.512.66.0F38.W1 A3" , "vl": 0}, - {"inst": "vscatterqps W:vm64x {k}, xmm" , "op": "MR-T1S: EVEX.128.66.0F38.W0 A3" , "vl": 1}, - {"inst": "vscatterqps W:vm64y {k}, xmm" , "op": "MR-T1S: EVEX.256.66.0F38.W0 A3" , "vl": 1}, - {"inst": "vscatterqps W:vm64z {k}, ymm" , "op": "MR-T1S: EVEX.512.66.0F38.W0 A3" , "vl": 0}, - {"inst": "vshuff32x4 W:ymm {kz}, ymm, ymm/m256/b32, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W0 23 /r ib" , "vl": 1}, - {"inst": "vshuff32x4 W:zmm {kz}, zmm, zmm/m512/b32, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W0 23 /r ib" , "vl": 0}, - {"inst": "vshuff64x2 W:ymm {kz}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W1 23 /r ib" , "vl": 1}, - {"inst": "vshuff64x2 W:zmm {kz}, zmm, zmm/m512/b64, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W1 23 /r ib" , "vl": 0}, - {"inst": "vshufi32x4 W:ymm {kz}, ymm, ymm/m256/b32, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W0 43 /r ib" , "vl": 1}, - {"inst": "vshufi32x4 W:zmm {kz}, zmm, zmm/m512/b32, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W0 43 /r ib" , "vl": 0}, - {"inst": "vshufi64x2 W:ymm {kz}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W1 43 /r ib" , "vl": 1}, - {"inst": "vshufi64x2 W:zmm {kz}, zmm, zmm/m512/b64, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W1 43 /r ib" , "vl": 0}, - {"inst": "vshufpd W:xmm {kz}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F.W1 C6 /r ib" , "vl": 1}, - {"inst": "vshufpd W:ymm {kz}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F.W1 C6 /r ib" , "vl": 1}, - {"inst": "vshufpd W:zmm {kz}, zmm, zmm/m512/b64, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F.W1 C6 /r ib" , "vl": 0}, - {"inst": "vshufps W:xmm {kz}, xmm, xmm/m128/b32, ib/ub" , "op": "RVM-FV: EVEX.128.0F.W0 C6 /r ib" , "vl": 1}, - {"inst": "vshufps W:ymm {kz}, ymm, ymm/m256/b32, ib/ub" , "op": "RVM-FV: EVEX.256.0F.W0 C6 /r ib" , "vl": 1}, - {"inst": "vshufps W:zmm {kz}, zmm, zmm/m512/b32, ib/ub" , "op": "RVM-FV: EVEX.512.0F.W0 C6 /r ib" , "vl": 0}, - {"inst": "vsqrtpd W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F.W1 51 /r" , "vl": 1}, - {"inst": "vsqrtpd W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F.W1 51 /r" , "vl": 1}, - {"inst": "vsqrtpd W:zmm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.66.0F.W1 51 /r" , "vl": 0}, - {"inst": "vsqrtps W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.0F.W0 51 /r" , "vl": 1}, - {"inst": "vsqrtps W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.0F.W0 51 /r" , "vl": 1}, - {"inst": "vsqrtps W:zmm {kz}, zmm/m512/b32 {er}" , "op": "RM-FV: EVEX.512.0F.W0 51 /r" , "vl": 0}, - {"inst": "vsubpd W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 5C /r" , "vl": 1}, - {"inst": "vsubpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 5C /r" , "vl": 1}, - {"inst": "vsubpd W:zmm {kz}, zmm, zmm/m512/b64 {er}" , "op": "RVM-FV: EVEX.512.66.0F.W1 5C /r" , "vl": 0}, - {"inst": "vsubps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.0F.W0 5C /r" , "vl": 1}, - {"inst": "vsubps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.0F.W0 5C /r" , "vl": 1}, - {"inst": "vsubps W:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.0F.W0 5C /r" , "vl": 0}, - {"inst": "vunpckhpd W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 15 /r" , "vl": 1}, - {"inst": "vunpckhpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 15 /r" , "vl": 1}, - {"inst": "vunpckhpd W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 15 /r" , "vl": 0}, - {"inst": "vunpckhps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.0F.W0 15 /r" , "vl": 1}, - {"inst": "vunpckhps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.0F.W0 15 /r" , "vl": 1}, - {"inst": "vunpckhps W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.0F.W0 15 /r" , "vl": 0}, - {"inst": "vunpcklpd W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 14 /r" , "vl": 1}, - {"inst": "vunpcklpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 14 /r" , "vl": 1}, - {"inst": "vunpcklpd W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 14 /r" , "vl": 0}, - {"inst": "vunpcklps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.0F.W0 14 /r" , "vl": 1}, - {"inst": "vunpcklps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.0F.W0 14 /r" , "vl": 1}, - {"inst": "vunpcklps W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.0F.W0 14 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD CRYPTO_HASH", "ext": "AVX512_F VAES", "data": [ - {"inst": "vaesdec W:xmm, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.WIG DE /r" , "vl": 1}, - {"inst": "vaesdec W:ymm, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.WIG DE /r" , "vl": 1}, - {"inst": "vaesdec W:zmm, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.WIG DE /r" , "vl": 0}, - {"inst": "vaesdeclast W:xmm, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.WIG DF /r" , "vl": 1}, - {"inst": "vaesdeclast W:ymm, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.WIG DF /r" , "vl": 1}, - {"inst": "vaesdeclast W:zmm, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.WIG DF /r" , "vl": 0}, - {"inst": "vaesenc W:xmm, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.WIG DC /r" , "vl": 1}, - {"inst": "vaesenc W:ymm, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.WIG DC /r" , "vl": 1}, - {"inst": "vaesenc W:zmm, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.WIG DC /r" , "vl": 0}, - {"inst": "vaesenclast W:xmm, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.WIG DD /r" , "vl": 1}, - {"inst": "vaesenclast W:ymm, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.WIG DD /r" , "vl": 1}, - {"inst": "vaesenclast W:zmm, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.WIG DD /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_F GFNI", "data": [ - {"inst": "vgf2p8affineinvqb W:xmm {kz}, xmm, xmm/m128, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.W1 CF /r ib" , "vl": 1}, - {"inst": "vgf2p8affineinvqb W:ymm {kz}, ymm, ymm/m256, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.W1 CF /r ib" , "vl": 1}, - {"inst": "vgf2p8affineinvqb W:zmm {kz}, zmm, zmm/m512, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.W1 CF /r ib" , "vl": 0}, - {"inst": "vgf2p8affineqb W:xmm {kz}, xmm, xmm/m128, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.W1 CE /r ib" , "vl": 1}, - {"inst": "vgf2p8affineqb W:ymm {kz}, ymm, ymm/m256, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.W1 CE /r ib" , "vl": 1}, - {"inst": "vgf2p8affineqb W:zmm {kz}, zmm, zmm/m512, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.W1 CE /r ib" , "vl": 0}, - {"inst": "vgf2p8mulb W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W0 CF /r" , "vl": 1}, - {"inst": "vgf2p8mulb W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W0 CF /r" , "vl": 1}, - {"inst": "vgf2p8mulb W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W0 CF /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_F VPCLMULQDQ", "data": [ - {"inst": "vpclmulqdq W:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.WIG 44 /r ib" , "vl": 1}, - {"inst": "vpclmulqdq W:ymm, ymm, ymm/m256, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.WIG 44 /r ib" , "vl": 1}, - {"inst": "vpclmulqdq W:zmm, zmm, zmm/m512, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.WIG 44 /r ib" , "vl": 0} - ]}, - - {"category": "AVX512 SCALAR", "ext": "AVX512_DQ", "data": [ - {"inst": "vfpclasssd W:k {k}, xmm[63:0]/m64, ib/ub" , "op": "RM-T1S: EVEX.LIG.66.0F3A.W1 67 /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vfpclassss W:k {k}, xmm[31:0]/m32, ib/ub" , "op": "RM-T1S: EVEX.LIG.66.0F3A.W0 67 /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vrangesd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64,ib/ub {sae}", "op": "RVM-T1S: EVEX.LIG.66.0F3A.W1 51 /r ib" , "vl": 0}, - {"inst": "vrangess W:xmm {kz}, xmm[127:32], xmm[31:0]/m32,ib/ub {sae}", "op": "RVM-T1S: EVEX.LIG.66.0F3A.W0 51 /r ib" , "vl": 0}, - {"inst": "vreducesd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64, ib/ub" , "op": "RVM-T1S: EVEX.LIG.66.0F3A.W1 57 /r ib" , "vl": 0}, - {"inst": "vreducess W:xmm {kz}, xmm[127:32], xmm[31:0]/m32, ib/ub" , "op": "RVM-T1S: EVEX.LIG.66.0F3A.W0 57 /r ib" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_DQ", "data": [ - {"inst": "vandnpd W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 55 /r" , "vl": 1}, - {"inst": "vandnpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 55 /r" , "vl": 1}, - {"inst": "vandnpd W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 55 /r" , "vl": 0}, - {"inst": "vandnps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.W0 55 /r" , "vl": 1}, - {"inst": "vandnps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.W0 55 /r" , "vl": 1}, - {"inst": "vandnps W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.W0 55 /r" , "vl": 0}, - {"inst": "vandpd W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 54 /r" , "vl": 1}, - {"inst": "vandpd W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 54 /r" , "vl": 1}, - {"inst": "vandpd W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 54 /r" , "vl": 0}, - {"inst": "vandps W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.0F.W0 54 /r" , "vl": 1}, - {"inst": "vandps W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.0F.W0 54 /r" , "vl": 1}, - {"inst": "vandps W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.0F.W0 54 /r" , "vl": 0}, - {"inst": "vbroadcastf32x2 W:ymm {kz}, xmm[63:0]/m64" , "op": "RM-T2: EVEX.256.66.0F38.W0 19 /r" , "vl": 1}, - {"inst": "vbroadcastf32x2 W:zmm {kz}, xmm[63:0]/m64" , "op": "RM-T2: EVEX.512.66.0F38.W0 19 /r" , "vl": 0}, - {"inst": "vbroadcastf32x8 W:zmm {kz}, m256" , "op": "RM-T8: EVEX.512.66.0F38.W0 1B /r" , "vl": 0}, - {"inst": "vbroadcastf64x2 W:ymm {kz}, m128" , "op": "RM-T2: EVEX.256.66.0F38.W1 1A /r" , "vl": 1}, - {"inst": "vbroadcastf64x2 W:zmm {kz}, m128" , "op": "RM-T2: EVEX.512.66.0F38.W1 1A /r" , "vl": 0}, - {"inst": "vbroadcasti32x2 W:xmm {kz}, xmm[63:0]/m64" , "op": "RM-T2: EVEX.128.66.0F38.W0 59 /r" , "vl": 1}, - {"inst": "vbroadcasti32x2 W:ymm {kz}, xmm[63:0]/m64" , "op": "RM-T2: EVEX.256.66.0F38.W0 59 /r" , "vl": 1}, - {"inst": "vbroadcasti32x2 W:zmm {kz}, xmm[63:0]/m64" , "op": "RM-T2: EVEX.512.66.0F38.W0 59 /r" , "vl": 0}, - {"inst": "vbroadcasti32x8 W:zmm {kz}, m256" , "op": "RM-T8: EVEX.512.66.0F38.W0 5B /r" , "vl": 0}, - {"inst": "vbroadcasti64x2 W:ymm {kz}, m128" , "op": "RM-T2: EVEX.256.66.0F38.W1 5A /r" , "vl": 1}, - {"inst": "vbroadcasti64x2 W:zmm {kz}, m128" , "op": "RM-T2: EVEX.512.66.0F38.W1 5A /r" , "vl": 0}, - {"inst": "vcvtpd2qq W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F.W1 7B /r" , "vl": 1}, - {"inst": "vcvtpd2qq W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F.W1 7B /r" , "vl": 1}, - {"inst": "vcvtpd2qq W:zmm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.66.0F.W1 7B /r" , "vl": 0}, - {"inst": "vcvtpd2uqq W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F.W1 79 /r" , "vl": 1}, - {"inst": "vcvtpd2uqq W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F.W1 79 /r" , "vl": 1}, - {"inst": "vcvtpd2uqq W:zmm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.66.0F.W1 79 /r" , "vl": 0}, - {"inst": "vcvtps2qq W:xmm {kz}, xmm[63:0]/m64/b32" , "op": "RM-HV: EVEX.128.66.0F.W0 7B /r" , "vl": 1}, - {"inst": "vcvtps2qq W:ymm {kz}, xmm/m128/b32" , "op": "RM-HV: EVEX.256.66.0F.W0 7B /r" , "vl": 1}, - {"inst": "vcvtps2qq W:zmm {kz}, ymm/m256/b32 {er}" , "op": "RM-HV: EVEX.512.66.0F.W0 7B /r" , "vl": 0}, - {"inst": "vcvtps2uqq W:xmm {kz}, xmm[63:0]/m64/b32" , "op": "RM-HV: EVEX.128.66.0F.W0 79 /r" , "vl": 1}, - {"inst": "vcvtps2uqq W:ymm {kz}, xmm/m128/b32" , "op": "RM-HV: EVEX.256.66.0F.W0 79 /r" , "vl": 1}, - {"inst": "vcvtps2uqq W:zmm {kz}, ymm/m256/b32 {er}" , "op": "RM-HV: EVEX.512.66.0F.W0 79 /r" , "vl": 0}, - {"inst": "vcvtqq2pd W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.F3.0F.W1 E6 /r" , "vl": 1}, - {"inst": "vcvtqq2pd W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.F3.0F.W1 E6 /r" , "vl": 1}, - {"inst": "vcvtqq2pd W:zmm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.F3.0F.W1 E6 /r" , "vl": 0}, - {"inst": "vcvtqq2ps W:xmm[63:0] {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.0F.W1 5B /r" , "vl": 1}, - {"inst": "vcvtqq2ps W:xmm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.0F.W1 5B /r" , "vl": 1}, - {"inst": "vcvtqq2ps W:ymm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.0F.W1 5B /r" , "vl": 0}, - {"inst": "vcvttpd2uqq W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F.W1 78 /r" , "vl": 1}, - {"inst": "vcvttpd2uqq W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F.W1 78 /r" , "vl": 1}, - {"inst": "vcvttpd2uqq W:zmm {kz}, zmm/m512/b64 {sae}" , "op": "RM-FV: EVEX.512.66.0F.W1 78 /r" , "vl": 0}, - {"inst": "vcvttps2qq W:xmm {kz}, xmm[63:0]/m64/b32" , "op": "RM-HV: EVEX.128.66.0F.W0 7A /r" , "vl": 1}, - {"inst": "vcvttps2qq W:ymm {kz}, xmm/m128/b32" , "op": "RM-HV: EVEX.256.66.0F.W0 7A /r" , "vl": 1}, - {"inst": "vcvttps2qq W:zmm {kz}, ymm/m256/b32 {sae}" , "op": "RM-HV: EVEX.512.66.0F.W0 7A /r" , "vl": 0}, - {"inst": "vcvttps2uqq W:xmm {kz}, xmm[63:0]/m64/b32" , "op": "RM-HV: EVEX.128.66.0F.W0 78 /r" , "vl": 1}, - {"inst": "vcvttps2uqq W:ymm {kz}, xmm/m128/b32" , "op": "RM-HV: EVEX.256.66.0F.W0 78 /r" , "vl": 1}, - {"inst": "vcvttps2uqq W:zmm {kz}, ymm/m256/b32 {sae}" , "op": "RM-HV: EVEX.512.66.0F.W0 78 /r" , "vl": 0}, - {"inst": "vcvtuqq2pd W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.F3.0F.W1 7A /r" , "vl": 1}, - {"inst": "vcvtuqq2pd W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.F3.0F.W1 7A /r" , "vl": 1}, - {"inst": "vcvtuqq2pd W:zmm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.F3.0F.W1 7A /r" , "vl": 0}, - {"inst": "vcvtuqq2ps W:xmm[63:0] {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.F2.0F.W1 7A /r" , "vl": 1}, - {"inst": "vcvtuqq2ps W:xmm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.F2.0F.W1 7A /r" , "vl": 1}, - {"inst": "vcvtuqq2ps W:ymm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.F2.0F.W1 7A /r" , "vl": 0}, - {"inst": "vextractf32x8 W:ymm/m256 {kz}, zmm, ib/ub" , "op": "MR-T8: EVEX.512.66.0F3A.W0 1B /r ib" , "vl": 0}, - {"inst": "vextractf64x2 W:xmm/m128 {kz}, ymm, ib/ub" , "op": "MR-T2: EVEX.256.66.0F3A.W1 19 /r ib" , "vl": 1}, - {"inst": "vextractf64x2 W:xmm/m128 {kz}, zmm, ib/ub" , "op": "MR-T2: EVEX.512.66.0F3A.W1 19 /r ib" , "vl": 0}, - {"inst": "vextracti32x8 W:ymm/m256 {kz}, zmm, ib/ub" , "op": "MR-T8: EVEX.512.66.0F3A.W0 3B /r ib" , "vl": 0}, - {"inst": "vextracti64x2 W:xmm/m128 {kz}, ymm, ib/ub" , "op": "MR-T2: EVEX.256.66.0F3A.W1 39 /r ib" , "vl": 1}, - {"inst": "vextracti64x2 W:xmm/m128 {kz}, zmm, ib/ub" , "op": "MR-T2: EVEX.512.66.0F3A.W1 39 /r ib" , "vl": 0}, - {"inst": "vfpclasspd W:k {k}, xmm/m128/b64, ib/ub" , "op": "RM-FV: EVEX.128.66.0F3A.W1 66 /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vfpclasspd W:k {k}, ymm/m256/b64, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W1 66 /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vfpclasspd W:k {k}, zmm/m512/b64, ib/ub" , "op": "RM-FV: EVEX.512.66.0F3A.W1 66 /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vfpclassps W:k {k}, xmm/m128/b32, ib/ub" , "op": "RM-FV: EVEX.128.66.0F3A.W0 66 /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vfpclassps W:k {k}, ymm/m256/b32, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W0 66 /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vfpclassps W:k {k}, zmm/m512/b32, ib/ub" , "op": "RM-FV: EVEX.512.66.0F3A.W0 66 /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vinsertf32x8 W:zmm {kz}, zmm, ymm/m256, ib/ub" , "op": "RVM-T8: EVEX.512.66.0F3A.W0 1A /r ib" , "vl": 0}, - {"inst": "vinsertf64x2 W:ymm {kz}, ymm, xmm/m128, ib/ub" , "op": "RVM-T2: EVEX.256.66.0F3A.W1 18 /r ib" , "vl": 1}, - {"inst": "vinsertf64x2 W:zmm {kz}, zmm, xmm/m128, ib/ub" , "op": "RVM-T2: EVEX.512.66.0F3A.W1 18 /r ib" , "vl": 0}, - {"inst": "vinserti32x8 W:zmm {kz}, zmm, ymm/m256, ib/ub" , "op": "RVM-T8: EVEX.512.66.0F3A.W0 3A /r ib" , "vl": 0}, - {"inst": "vinserti64x2 W:ymm {kz}, ymm, xmm/m128, ib/ub" , "op": "RVM-T2: EVEX.256.66.0F3A.W1 38 /r ib" , "vl": 1}, - {"inst": "vinserti64x2 W:zmm {kz}, zmm, xmm/m128, ib/ub" , "op": "RVM-T2: EVEX.512.66.0F3A.W1 38 /r ib" , "vl": 0}, - {"inst": "vorpd W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 56 /r" , "vl": 1}, - {"inst": "vorpd W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 56 /r" , "vl": 1}, - {"inst": "vorpd W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 56 /r" , "vl": 0}, - {"inst": "vorps W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.0F.W0 56 /r" , "vl": 1}, - {"inst": "vorps W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.0F.W0 56 /r" , "vl": 1}, - {"inst": "vorps W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.0F.W0 56 /r" , "vl": 0}, - {"inst": "vpextrd W:r32/m32, xmm, ib/ub" , "op": "MR-T1S: EVEX.128.66.0F3A.W0 16 /r ib" , "vl": 0}, - {"inst": "vpextrq W:r64/m64, xmm, ib/ub" , "op": "MR-T1S: EVEX.128.66.0F3A.W1 16 /r ib" , "vl": 0}, - {"inst": "vpinsrd W:xmm {kz}, xmm, r32/m32, ib/ub" , "op": "RVM-T1S: EVEX.128.66.0F3A.W0 22 /r ib" , "vl": 0}, - {"inst": "vpinsrq W:xmm {kz}, xmm, r64/m64, ib/ub" , "op": "RVM-T1S: EVEX.128.66.0F3A.W1 22 /r ib" , "vl": 0}, - {"inst": "vpmovd2m W:k, xmm" , "op": "RM: EVEX.128.F3.0F38.W0 39 /r" , "vl": 1}, - {"inst": "vpmovd2m W:k, ymm" , "op": "RM: EVEX.256.F3.0F38.W0 39 /r" , "vl": 1}, - {"inst": "vpmovd2m W:k, zmm" , "op": "RM: EVEX.512.F3.0F38.W0 39 /r" , "vl": 0}, - {"inst": "vpmovm2d W:xmm, k" , "op": "RM: EVEX.128.F3.0F38.W0 38 /r" , "vl": 1}, - {"inst": "vpmovm2d W:ymm, k" , "op": "RM: EVEX.256.F3.0F38.W0 38 /r" , "vl": 1}, - {"inst": "vpmovm2d W:zmm, k" , "op": "RM: EVEX.512.F3.0F38.W0 38 /r" , "vl": 0}, - {"inst": "vpmovm2q W:xmm, k" , "op": "RM: EVEX.128.F3.0F38.W1 38 /r" , "vl": 1}, - {"inst": "vpmovm2q W:ymm, k" , "op": "RM: EVEX.256.F3.0F38.W1 38 /r" , "vl": 1}, - {"inst": "vpmovm2q W:zmm, k" , "op": "RM: EVEX.512.F3.0F38.W1 38 /r" , "vl": 0}, - {"inst": "vpmovq2m W:k, xmm" , "op": "RM: EVEX.128.F3.0F38.W1 39 /r" , "vl": 1}, - {"inst": "vpmovq2m W:k, ymm" , "op": "RM: EVEX.256.F3.0F38.W1 39 /r" , "vl": 1}, - {"inst": "vpmovq2m W:k, zmm" , "op": "RM: EVEX.512.F3.0F38.W1 39 /r" , "vl": 0}, - {"inst": "vpmullq W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 40 /r" , "vl": 1}, - {"inst": "vpmullq W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 40 /r" , "vl": 1}, - {"inst": "vpmullq W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 40 /r" , "vl": 0}, - {"inst": "vrangepd W:xmm {kz}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W1 50 /r ib" , "vl": 1}, - {"inst": "vrangepd W:ymm {kz}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W1 50 /r ib" , "vl": 1}, - {"inst": "vrangepd W:zmm {kz}, zmm, zmm/m512/b64, ib/ub {sae}" , "op": "RVM-FV: EVEX.512.66.0F3A.W1 50 /r ib" , "vl": 0}, - {"inst": "vrangeps W:xmm {kz}, xmm, xmm/m128/b32, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W0 50 /r ib" , "vl": 1}, - {"inst": "vrangeps W:ymm {kz}, ymm, ymm/m256/b32, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W0 50 /r ib" , "vl": 1}, - {"inst": "vrangeps W:zmm {kz}, zmm, zmm/m512/b32, ib/ub {sae}" , "op": "RVM-FV: EVEX.512.66.0F3A.W0 50 /r ib" , "vl": 0}, - {"inst": "vreducepd W:xmm {kz}, xmm/m128/b64, ib/ub" , "op": "RM-FV: EVEX.128.66.0F3A.W1 56 /r ib" , "vl": 1}, - {"inst": "vreducepd W:ymm {kz}, ymm/m256/b64, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W1 56 /r ib" , "vl": 1}, - {"inst": "vreducepd W:zmm {kz}, zmm/m512/b64, ib/ub" , "op": "RM-FV: EVEX.512.66.0F3A.W1 56 /r ib" , "vl": 0}, - {"inst": "vreduceps W:xmm {kz}, xmm/m128/b32, ib/ub" , "op": "RM-FV: EVEX.128.66.0F3A.W0 56 /r ib" , "vl": 1}, - {"inst": "vreduceps W:ymm {kz}, ymm/m256/b32, ib/ub" , "op": "RM-FV: EVEX.256.66.0F3A.W0 56 /r ib" , "vl": 1}, - {"inst": "vreduceps W:zmm {kz}, zmm/m512/b32, ib/ub" , "op": "RM-FV: EVEX.512.66.0F3A.W0 56 /r ib" , "vl": 0}, - {"inst": "vxorpd W:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F.W1 57 /r" , "vl": 1}, - {"inst": "vxorpd W:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F.W1 57 /r" , "vl": 1}, - {"inst": "vxorpd W:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F.W1 57 /r" , "vl": 0}, - {"inst": "vxorps W:xmm {kz}, ~xmm, ~xmm/m128/b32" , "op": "RVM-FV: EVEX.128.0F.W0 57 /r" , "vl": 1}, - {"inst": "vxorps W:ymm {kz}, ~ymm, ~ymm/m256/b32" , "op": "RVM-FV: EVEX.256.0F.W0 57 /r" , "vl": 1}, - {"inst": "vxorps W:zmm {kz}, ~zmm, ~zmm/m512/b32" , "op": "RVM-FV: EVEX.512.0F.W0 57 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_BW", "data": [ - {"inst": "vdbpsadbw W:xmm {kz}, xmm, xmm/m128, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.W0 42 /r ib" , "vl": 1}, - {"inst": "vdbpsadbw W:ymm {kz}, ymm, ymm/m256, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.W0 42 /r ib" , "vl": 1}, - {"inst": "vdbpsadbw W:zmm {kz}, zmm, zmm/m512, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.W0 42 /r ib" , "vl": 0}, - {"inst": "vmovdqu16 W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.F2.0F.W1 6F /r" , "vl": 1}, - {"inst": "vmovdqu16 W:xmm/m128 {kz}, xmm" , "op": "MR-FVM: EVEX.128.F2.0F.W1 7F /r" , "vl": 1}, - {"inst": "vmovdqu16 W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.F2.0F.W1 6F /r" , "vl": 1}, - {"inst": "vmovdqu16 W:ymm/m256 {kz}, ymm" , "op": "MR-FVM: EVEX.256.F2.0F.W1 7F /r" , "vl": 1}, - {"inst": "vmovdqu16 W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.F2.0F.W1 6F /r" , "vl": 0}, - {"inst": "vmovdqu16 W:zmm/m512 {kz}, zmm" , "op": "MR-FVM: EVEX.512.F2.0F.W1 7F /r" , "vl": 0}, - {"inst": "vmovdqu8 W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.F2.0F.W0 6F /r" , "vl": 1}, - {"inst": "vmovdqu8 W:xmm/m128 {kz}, xmm" , "op": "MR-FVM: EVEX.128.F2.0F.W0 7F /r" , "vl": 1}, - {"inst": "vmovdqu8 W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.F2.0F.W0 6F /r" , "vl": 1}, - {"inst": "vmovdqu8 W:ymm/m256 {kz}, ymm" , "op": "MR-FVM: EVEX.256.F2.0F.W0 7F /r" , "vl": 1}, - {"inst": "vmovdqu8 W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.F2.0F.W0 6F /r" , "vl": 0}, - {"inst": "vmovdqu8 W:zmm/m512 {kz}, zmm" , "op": "MR-FVM: EVEX.512.F2.0F.W0 7F /r" , "vl": 0}, - {"inst": "vpabsb W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.66.0F38 1C /r" , "vl": 1}, - {"inst": "vpabsb W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.66.0F38 1C /r" , "vl": 1}, - {"inst": "vpabsb W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.66.0F38 1C /r" , "vl": 0}, - {"inst": "vpabsw W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.66.0F38 1D /r" , "vl": 1}, - {"inst": "vpabsw W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.66.0F38 1D /r" , "vl": 1}, - {"inst": "vpabsw W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.66.0F38 1D /r" , "vl": 0}, - {"inst": "vpackssdw W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F.W0 6B /r" , "vl": 1}, - {"inst": "vpackssdw W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F.W0 6B /r" , "vl": 1}, - {"inst": "vpackssdw W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F.W0 6B /r" , "vl": 0}, - {"inst": "vpacksswb W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG 63 /r" , "vl": 1}, - {"inst": "vpacksswb W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG 63 /r" , "vl": 1}, - {"inst": "vpacksswb W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG 63 /r" , "vl": 0}, - {"inst": "vpackusdw W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 2B /r" , "vl": 1}, - {"inst": "vpackusdw W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 2B /r" , "vl": 1}, - {"inst": "vpackusdw W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 2B /r" , "vl": 0}, - {"inst": "vpackuswb W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG 67 /r" , "vl": 1}, - {"inst": "vpackuswb W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG 67 /r" , "vl": 1}, - {"inst": "vpackuswb W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG 67 /r" , "vl": 0}, - {"inst": "vpaddb W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG FC /r" , "vl": 1}, - {"inst": "vpaddb W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG FC /r" , "vl": 1}, - {"inst": "vpaddb W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG FC /r" , "vl": 0}, - {"inst": "vpaddsb W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG EC /r" , "vl": 1}, - {"inst": "vpaddsb W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG EC /r" , "vl": 1}, - {"inst": "vpaddsb W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG EC /r" , "vl": 0}, - {"inst": "vpaddsw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG ED /r" , "vl": 1}, - {"inst": "vpaddsw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG ED /r" , "vl": 1}, - {"inst": "vpaddsw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG ED /r" , "vl": 0}, - {"inst": "vpaddusb W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG DC /r" , "vl": 1}, - {"inst": "vpaddusb W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG DC /r" , "vl": 1}, - {"inst": "vpaddusb W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG DC /r" , "vl": 0}, - {"inst": "vpaddusw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG DD /r" , "vl": 1}, - {"inst": "vpaddusw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG DD /r" , "vl": 1}, - {"inst": "vpaddusw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG DD /r" , "vl": 0}, - {"inst": "vpaddw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG FD /r" , "vl": 1}, - {"inst": "vpaddw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG FD /r" , "vl": 1}, - {"inst": "vpaddw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG FD /r" , "vl": 0}, - {"inst": "vpalignr W:xmm {kz}, xmm, xmm/m128, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.WIG 0F /r ib" , "vl": 1}, - {"inst": "vpalignr W:ymm {kz}, ymm, ymm/m256, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.WIG 0F /r ib" , "vl": 1}, - {"inst": "vpalignr W:zmm {kz}, zmm, zmm/m512, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.WIG 0F /r ib" , "vl": 0}, - {"inst": "vpavgb W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG E0 /r" , "vl": 1}, - {"inst": "vpavgb W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG E0 /r" , "vl": 1}, - {"inst": "vpavgb W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG E0 /r" , "vl": 0}, - {"inst": "vpavgw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG E3 /r" , "vl": 1}, - {"inst": "vpavgw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG E3 /r" , "vl": 1}, - {"inst": "vpavgw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG E3 /r" , "vl": 0}, - {"inst": "vpblendmb W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W0 66 /r" , "vl": 1, "k": "blend"}, - {"inst": "vpblendmb W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W0 66 /r" , "vl": 1, "k": "blend"}, - {"inst": "vpblendmb W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W0 66 /r" , "vl": 0, "k": "blend"}, - {"inst": "vpblendmw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 66 /r" , "vl": 1, "k": "blend"}, - {"inst": "vpblendmw W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 66 /r" , "vl": 1, "k": "blend"}, - {"inst": "vpblendmw W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 66 /r" , "vl": 0, "k": "blend"}, - {"inst": "vpbroadcastb W:xmm {kz}, r32[7:0]" , "op": "RM-T1S: EVEX.128.66.0F38.W0 7A /r" , "vl": 1}, - {"inst": "vpbroadcastb W:xmm {kz}, xmm[7:0]/m8" , "op": "RM-T1S: EVEX.128.66.0F38.W0 78 /r" , "vl": 1}, - {"inst": "vpbroadcastb W:ymm {kz}, r32[7:0]" , "op": "RM-T1S: EVEX.256.66.0F38.W0 7A /r" , "vl": 1}, - {"inst": "vpbroadcastb W:ymm {kz}, xmm[7:0]/m8" , "op": "RM-T1S: EVEX.256.66.0F38.W0 78 /r" , "vl": 1}, - {"inst": "vpbroadcastb W:zmm {kz}, r32[7:0]" , "op": "RM-T1S: EVEX.512.66.0F38.W0 7A /r" , "vl": 0}, - {"inst": "vpbroadcastb W:zmm {kz}, xmm[7:0]/m8" , "op": "RM-T1S: EVEX.512.66.0F38.W0 78 /r" , "vl": 0}, - {"inst": "vpbroadcastw W:xmm {kz}, r32[15:0]" , "op": "RM-T1S: EVEX.128.66.0F38.W0 7B /r" , "vl": 1}, - {"inst": "vpbroadcastw W:xmm {kz}, xmm[15:0]/m16" , "op": "RM-T1S: EVEX.128.66.0F38.W0 79 /r" , "vl": 1}, - {"inst": "vpbroadcastw W:ymm {kz}, r32[15:0]" , "op": "RM-T1S: EVEX.256.66.0F38.W0 7B /r" , "vl": 1}, - {"inst": "vpbroadcastw W:ymm {kz}, xmm[15:0]/m16" , "op": "RM-T1S: EVEX.256.66.0F38.W0 79 /r" , "vl": 1}, - {"inst": "vpbroadcastw W:zmm {kz}, r32[15:0]" , "op": "RM-T1S: EVEX.512.66.0F38.W0 7B /r" , "vl": 0}, - {"inst": "vpbroadcastw W:zmm {kz}, xmm[15:0]/m16" , "op": "RM-T1S: EVEX.512.66.0F38.W0 79 /r" , "vl": 0}, - {"inst": "vpcmpb W:k {k}, xmm, xmm/m128, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.W0 3F /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpb W:k {k}, ymm, ymm/m256, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.W0 3F /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpb W:k {k}, zmm, zmm/m512, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.W0 3F /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpeqb W:k {k}, ~xmm, ~xmm/m128" , "op": "RVM-FV: EVEX.128.66.0F.WIG 74 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpeqb W:k {k}, ~ymm, ~ymm/m256" , "op": "RVM-FV: EVEX.256.66.0F.WIG 74 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpeqb W:k {k}, ~zmm, ~zmm/m512" , "op": "RVM-FV: EVEX.512.66.0F.WIG 74 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpeqw W:k {k}, ~xmm, ~xmm/m128" , "op": "RVM-FV: EVEX.128.66.0F.WIG 75 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpeqw W:k {k}, ~ymm, ~ymm/m256" , "op": "RVM-FV: EVEX.256.66.0F.WIG 75 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpeqw W:k {k}, ~zmm, ~zmm/m512" , "op": "RVM-FV: EVEX.512.66.0F.WIG 75 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpgtb W:k {k}, xmm, xmm/m128" , "op": "RVM-FV: EVEX.128.66.0F.WIG 64 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpgtb W:k {k}, ymm, ymm/m256" , "op": "RVM-FV: EVEX.256.66.0F.WIG 64 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpgtb W:k {k}, zmm, zmm/m512" , "op": "RVM-FV: EVEX.512.66.0F.WIG 64 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpgtw W:k {k}, xmm, xmm/m128" , "op": "RVM-FV: EVEX.128.66.0F.WIG 65 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpgtw W:k {k}, ymm, ymm/m256" , "op": "RVM-FV: EVEX.256.66.0F.WIG 65 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpgtw W:k {k}, zmm, zmm/m512" , "op": "RVM-FV: EVEX.512.66.0F.WIG 65 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpub W:k {k}, xmm, xmm/m128, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.W0 3E /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpub W:k {k}, ymm, ymm/m256, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.W0 3E /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpub W:k {k}, zmm, zmm/m512, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.W0 3E /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpuw W:k {k}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.W1 3E /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpuw W:k {k}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.W1 3E /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpuw W:k {k}, zmm, zmm/m512/b64, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.W1 3E /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vpcmpw W:k {k}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.W1 3F /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpw W:k {k}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.W1 3F /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vpcmpw W:k {k}, zmm, zmm/m512/b64, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.W1 3F /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vpermi2w X:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 75 /r" , "vl": 1}, - {"inst": "vpermi2w X:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 75 /r" , "vl": 1}, - {"inst": "vpermi2w X:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 75 /r" , "vl": 0}, - {"inst": "vpermt2w X:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 7D /r" , "vl": 1}, - {"inst": "vpermt2w X:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 7D /r" , "vl": 1}, - {"inst": "vpermt2w X:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 7D /r" , "vl": 0}, - {"inst": "vpermw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 8D /r" , "vl": 1}, - {"inst": "vpermw W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 8D /r" , "vl": 1}, - {"inst": "vpermw W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 8D /r" , "vl": 0}, - {"inst": "vpextrb W:r32[7:0]/m8 , xmm, ib/ub" , "op": "MR-T1S: EVEX.128.66.0F3A.WIG 14 /r ib" , "vl": 0}, - {"inst": "vpextrw W:r32[15:0], xmm, ib/ub" , "op": "RM: EVEX.128.66.0F.WIG C5 /r ib" , "vl": 0}, - {"inst": "vpextrw W:r32[15:0]/m16, xmm, ib/ub" , "op": "MR-T1S: EVEX.128.66.0F3A.WIG 15 /r ib" , "vl": 0}, - {"inst": "vpinsrb W:xmm {kz}, xmm, r32[7:0]/m8, ib/ub" , "op": "RVM-T1S: EVEX.128.66.0F3A.WIG 20 /r ib" , "vl": 0}, - {"inst": "vpinsrw W:xmm {kz}, xmm, r32[15:0]/m16, ib/ub" , "op": "RVM-T1S: EVEX.128.66.0F.WIG C4 /r ib" , "vl": 0}, - {"inst": "vpmaddubsw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.WIG 04 /r" , "vl": 1}, - {"inst": "vpmaddubsw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.WIG 04 /r" , "vl": 1}, - {"inst": "vpmaddubsw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.WIG 04 /r" , "vl": 0}, - {"inst": "vpmaddwd W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG F5 /r" , "vl": 1}, - {"inst": "vpmaddwd W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG F5 /r" , "vl": 1}, - {"inst": "vpmaddwd W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG F5 /r" , "vl": 0}, - {"inst": "vpmaxsb W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.WIG 3C /r" , "vl": 1}, - {"inst": "vpmaxsb W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.WIG 3C /r" , "vl": 1}, - {"inst": "vpmaxsb W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.WIG 3C /r" , "vl": 0}, - {"inst": "vpmaxsw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG EE /r" , "vl": 1}, - {"inst": "vpmaxsw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG EE /r" , "vl": 1}, - {"inst": "vpmaxsw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG EE /r" , "vl": 0}, - {"inst": "vpmaxub W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG DE /r" , "vl": 1}, - {"inst": "vpmaxub W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG DE /r" , "vl": 1}, - {"inst": "vpmaxub W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG DE /r" , "vl": 0}, - {"inst": "vpmaxuw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.WIG 3E /r" , "vl": 1}, - {"inst": "vpmaxuw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.WIG 3E /r" , "vl": 1}, - {"inst": "vpmaxuw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.WIG 3E /r" , "vl": 0}, - {"inst": "vpminsb W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.WIG 38 /r" , "vl": 1}, - {"inst": "vpminsb W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.WIG 38 /r" , "vl": 1}, - {"inst": "vpminsb W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.WIG 38 /r" , "vl": 0}, - {"inst": "vpminsw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG EA /r" , "vl": 1}, - {"inst": "vpminsw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG EA /r" , "vl": 1}, - {"inst": "vpminsw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG EA /r" , "vl": 0}, - {"inst": "vpminub W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F DA /r" , "vl": 1}, - {"inst": "vpminub W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F DA /r" , "vl": 1}, - {"inst": "vpminub W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F DA /r" , "vl": 0}, - {"inst": "vpminuw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38 3A /r" , "vl": 1}, - {"inst": "vpminuw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38 3A /r" , "vl": 1}, - {"inst": "vpminuw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38 3A /r" , "vl": 0}, - {"inst": "vpmovb2m W:k, xmm" , "op": "RM: EVEX.128.F3.0F38.W0 29 /r" , "vl": 1}, - {"inst": "vpmovb2m W:k, ymm" , "op": "RM: EVEX.256.F3.0F38.W0 29 /r" , "vl": 1}, - {"inst": "vpmovb2m W:k, zmm" , "op": "RM: EVEX.512.F3.0F38.W0 29 /r" , "vl": 0}, - {"inst": "vpmovm2b W:xmm, k" , "op": "RM: EVEX.128.F3.0F38.W0 28 /r" , "vl": 1}, - {"inst": "vpmovm2b W:ymm, k" , "op": "RM: EVEX.256.F3.0F38.W0 28 /r" , "vl": 1}, - {"inst": "vpmovm2b W:zmm, k" , "op": "RM: EVEX.512.F3.0F38.W0 28 /r" , "vl": 0}, - {"inst": "vpmovm2w W:xmm, k" , "op": "RM: EVEX.128.F3.0F38.W1 28 /r" , "vl": 1}, - {"inst": "vpmovm2w W:ymm, k" , "op": "RM: EVEX.256.F3.0F38.W1 28 /r" , "vl": 1}, - {"inst": "vpmovm2w W:zmm, k" , "op": "RM: EVEX.512.F3.0F38.W1 28 /r" , "vl": 0}, - {"inst": "vpmovswb W:xmm[63:0]/m64 {kz}, xmm" , "op": "MR-HVM: EVEX.128.F3.0F38.W0 20 /r" , "vl": 1}, - {"inst": "vpmovswb W:xmm/m128 {kz}, ymm" , "op": "MR-HVM: EVEX.256.F3.0F38.W0 20 /r" , "vl": 1}, - {"inst": "vpmovswb W:ymm/m256 {kz}, zmm" , "op": "MR-HVM: EVEX.512.F3.0F38.W0 20 /r" , "vl": 0}, - {"inst": "vpmovsxbw W:xmm {kz}, xmm[63:0]/m64" , "op": "RM-HVM: EVEX.128.66.0F38.WIG 20 /r" , "vl": 1}, - {"inst": "vpmovsxbw W:ymm {kz}, xmm/m128" , "op": "RM-HVM: EVEX.256.66.0F38.WIG 20 /r" , "vl": 1}, - {"inst": "vpmovsxbw W:zmm {kz}, ymm/m256" , "op": "RM-HVM: EVEX.512.66.0F38.WIG 20 /r" , "vl": 0}, - {"inst": "vpmovuswb W:xmm[63:0]/m64 {kz}, xmm" , "op": "MR-HVM: EVEX.128.F3.0F38.W0 10 /r" , "vl": 1}, - {"inst": "vpmovuswb W:xmm/m128 {kz}, ymm" , "op": "MR-HVM: EVEX.256.F3.0F38.W0 10 /r" , "vl": 1}, - {"inst": "vpmovuswb W:ymm/m256 {kz}, zmm" , "op": "MR-HVM: EVEX.512.F3.0F38.W0 10 /r" , "vl": 0}, - {"inst": "vpmovw2m W:k, xmm" , "op": "RM: EVEX.128.F3.0F38.W1 29 /r" , "vl": 1}, - {"inst": "vpmovw2m W:k, ymm" , "op": "RM: EVEX.256.F3.0F38.W1 29 /r" , "vl": 1}, - {"inst": "vpmovw2m W:k, zmm" , "op": "RM: EVEX.512.F3.0F38.W1 29 /r" , "vl": 0}, - {"inst": "vpmovwb W:xmm[63:0]/m64 {kz}, xmm" , "op": "MR-HVM: EVEX.128.F3.0F38.W0 30 /r" , "vl": 1}, - {"inst": "vpmovwb W:xmm/m128 {kz}, ymm" , "op": "MR-HVM: EVEX.256.F3.0F38.W0 30 /r" , "vl": 1}, - {"inst": "vpmovwb W:ymm/m256 {kz}, zmm" , "op": "MR-HVM: EVEX.512.F3.0F38.W0 30 /r" , "vl": 0}, - {"inst": "vpmovzxbw W:xmm {kz}, xmm[63:0]/m64" , "op": "RM-HVM: EVEX.128.66.0F38.WIG 30 /r" , "vl": 1}, - {"inst": "vpmovzxbw W:ymm {kz}, xmm/m128" , "op": "RM-HVM: EVEX.256.66.0F38.WIG 30 /r" , "vl": 1}, - {"inst": "vpmovzxbw W:zmm {kz}, ymm/m256" , "op": "RM-HVM: EVEX.512.66.0F38.WIG 30 /r" , "vl": 0}, - {"inst": "vpmulhrsw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.WIG 0B /r" , "vl": 1}, - {"inst": "vpmulhrsw W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.WIG 0B /r" , "vl": 1}, - {"inst": "vpmulhrsw W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.WIG 0B /r" , "vl": 0}, - {"inst": "vpmulhuw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG E4 /r" , "vl": 1}, - {"inst": "vpmulhuw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG E4 /r" , "vl": 1}, - {"inst": "vpmulhuw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG E4 /r" , "vl": 0}, - {"inst": "vpmulhw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG E5 /r" , "vl": 1}, - {"inst": "vpmulhw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG E5 /r" , "vl": 1}, - {"inst": "vpmulhw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG E5 /r" , "vl": 0}, - {"inst": "vpmullw W:xmm {kz}, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG D5 /r" , "vl": 1}, - {"inst": "vpmullw W:ymm {kz}, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG D5 /r" , "vl": 1}, - {"inst": "vpmullw W:zmm {kz}, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG D5 /r" , "vl": 0}, - {"inst": "vpsadbw W:xmm, ~xmm, ~xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG F6 /r" , "vl": 1}, - {"inst": "vpsadbw W:ymm, ~ymm, ~ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG F6 /r" , "vl": 1}, - {"inst": "vpsadbw W:zmm, ~zmm, ~zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG F6 /r" , "vl": 0}, - {"inst": "vpshufb W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.WIG 00 /r" , "vl": 1}, - {"inst": "vpshufb W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.WIG 00 /r" , "vl": 1}, - {"inst": "vpshufb W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.WIG 00 /r" , "vl": 0}, - {"inst": "vpshufhw W:xmm {kz}, xmm/m128, ib/ub" , "op": "RM-FVM: EVEX.128.F3.0F.WIG 70 /r ib" , "vl": 1}, - {"inst": "vpshufhw W:ymm {kz}, ymm/m256, ib/ub" , "op": "RM-FVM: EVEX.256.F3.0F.WIG 70 /r ib" , "vl": 1}, - {"inst": "vpshufhw W:zmm {kz}, zmm/m512, ib/ub" , "op": "RM-FVM: EVEX.512.F3.0F.WIG 70 /r ib" , "vl": 0}, - {"inst": "vpshuflw W:xmm {kz}, xmm/m128, ib/ub" , "op": "RM-FVM: EVEX.128.F2.0F.WIG 70 /r ib" , "vl": 1}, - {"inst": "vpshuflw W:ymm {kz}, ymm/m256, ib/ub" , "op": "RM-FVM: EVEX.256.F2.0F.WIG 70 /r ib" , "vl": 1}, - {"inst": "vpshuflw W:zmm {kz}, zmm/m512, ib/ub" , "op": "RM-FVM: EVEX.512.F2.0F.WIG 70 /r ib" , "vl": 0}, - {"inst": "vpslldq W:xmm, xmm/m128, ib/ub" , "op": "VM-FVM: EVEX.128.66.0F.WIG 73 /7 ib" , "vl": 1}, - {"inst": "vpslldq W:ymm, ymm/m256, ib/ub" , "op": "VM-FVM: EVEX.256.66.0F.WIG 73 /7 ib" , "vl": 1}, - {"inst": "vpslldq W:zmm, zmm/m512, ib/ub" , "op": "VM-FVM: EVEX.512.66.0F.WIG 73 /7 ib" , "vl": 0}, - {"inst": "vpsllvw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 12 /r" , "vl": 1}, - {"inst": "vpsllvw W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 12 /r" , "vl": 1}, - {"inst": "vpsllvw W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 12 /r" , "vl": 0}, - {"inst": "vpsllw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-M128: EVEX.128.66.0F.WIG F1 /r" , "vl": 1}, - {"inst": "vpsllw W:xmm {kz}, xmm/m128, ib/ub" , "op": "VM-FVM: EVEX.128.66.0F.WIG 71 /6 ib" , "vl": 1}, - {"inst": "vpsllw W:ymm {kz}, ymm, xmm/m128" , "op": "RVM-M128: EVEX.256.66.0F.WIG F1 /r" , "vl": 1}, - {"inst": "vpsllw W:ymm {kz}, ymm/m256, ib/ub" , "op": "VM-FVM: EVEX.256.66.0F.WIG 71 /6 ib" , "vl": 1}, - {"inst": "vpsllw W:zmm {kz}, zmm, xmm/m128" , "op": "RVM-M128: EVEX.512.66.0F.WIG F1 /r" , "vl": 0}, - {"inst": "vpsllw W:zmm {kz}, zmm/m512, ib/ub" , "op": "VM-FVM: EVEX.512.66.0F.WIG 71 /6 ib" , "vl": 0}, - {"inst": "vpsravw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 11 /r" , "vl": 1}, - {"inst": "vpsravw W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 11 /r" , "vl": 1}, - {"inst": "vpsravw W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 11 /r" , "vl": 0}, - {"inst": "vpsraw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-M128: EVEX.128.66.0F.WIG E1 /r" , "vl": 1}, - {"inst": "vpsraw W:xmm {kz}, xmm/m128, ib/ub" , "op": "VM-FVM: EVEX.128.66.0F.WIG 71 /4 ib" , "vl": 1}, - {"inst": "vpsraw W:ymm {kz}, ymm, xmm/m128" , "op": "RVM-M128: EVEX.256.66.0F.WIG E1 /r" , "vl": 1}, - {"inst": "vpsraw W:ymm {kz}, ymm/m256, ib/ub" , "op": "VM-FVM: EVEX.256.66.0F.WIG 71 /4 ib" , "vl": 1}, - {"inst": "vpsraw W:zmm {kz}, zmm, xmm/m128" , "op": "RVM-M128: EVEX.512.66.0F.WIG E1 /r" , "vl": 0}, - {"inst": "vpsraw W:zmm {kz}, zmm/m512, ib/ub" , "op": "VM-FVM: EVEX.512.66.0F.WIG 71 /4 ib" , "vl": 0}, - {"inst": "vpsrldq W:xmm, xmm/m128, ib/ub" , "op": "VM-FVM: EVEX.128.66.0F.WIG 73 /3 ib" , "vl": 1}, - {"inst": "vpsrldq W:ymm, ymm/m256, ib/ub" , "op": "VM-FVM: EVEX.256.66.0F.WIG 73 /3 ib" , "vl": 1}, - {"inst": "vpsrldq W:zmm, zmm/m512, ib/ub" , "op": "VM-FVM: EVEX.512.66.0F.WIG 73 /3 ib" , "vl": 0}, - {"inst": "vpsrlvw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 10 /r" , "vl": 1}, - {"inst": "vpsrlvw W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 10 /r" , "vl": 1}, - {"inst": "vpsrlvw W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 10 /r" , "vl": 0}, - {"inst": "vpsrlw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-M128: EVEX.128.66.0F.WIG D1 /r" , "vl": 1}, - {"inst": "vpsrlw W:xmm {kz}, xmm/m128, ib/ub" , "op": "VM-FVM: EVEX.128.66.0F.WIG 71 /2 ib" , "vl": 1}, - {"inst": "vpsrlw W:ymm {kz}, ymm, xmm/m128" , "op": "RVM-M128: EVEX.256.66.0F.WIG D1 /r" , "vl": 1}, - {"inst": "vpsrlw W:ymm {kz}, ymm/m256, ib/ub" , "op": "VM-FVM: EVEX.256.66.0F.WIG 71 /2 ib" , "vl": 1}, - {"inst": "vpsrlw W:zmm {kz}, zmm, xmm/m128" , "op": "RVM-M128: EVEX.512.66.0F.WIG D1 /r" , "vl": 0}, - {"inst": "vpsrlw W:zmm {kz}, zmm/m512, ib/ub" , "op": "VM-FVM: EVEX.512.66.0F.WIG 71 /2 ib" , "vl": 0}, - {"inst": "vpsubb W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG F8 /r" , "vl": 1}, - {"inst": "vpsubb W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG F8 /r" , "vl": 1}, - {"inst": "vpsubb W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG F8 /r" , "vl": 0}, - {"inst": "vpsubsb W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG E8 /r" , "vl": 1}, - {"inst": "vpsubsb W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG E8 /r" , "vl": 1}, - {"inst": "vpsubsb W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG E8 /r" , "vl": 0}, - {"inst": "vpsubsw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG E9 /r" , "vl": 1}, - {"inst": "vpsubsw W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG E9 /r" , "vl": 1}, - {"inst": "vpsubsw W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG E9 /r" , "vl": 0}, - {"inst": "vpsubusb W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG D8 /r" , "vl": 1}, - {"inst": "vpsubusb W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG D8 /r" , "vl": 1}, - {"inst": "vpsubusb W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG D8 /r" , "vl": 0}, - {"inst": "vpsubusw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG D9 /r" , "vl": 1}, - {"inst": "vpsubusw W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG D9 /r" , "vl": 1}, - {"inst": "vpsubusw W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG D9 /r" , "vl": 0}, - {"inst": "vpsubw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG F9 /r" , "vl": 1}, - {"inst": "vpsubw W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG F9 /r" , "vl": 1}, - {"inst": "vpsubw W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG F9 /r" , "vl": 0}, - {"inst": "vptestmb W:k {k}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W0 26 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestmb W:k {k}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W0 26 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestmb W:k {k}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W0 26 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vptestmw W:k {k}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 26 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestmw W:k {k}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 26 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestmw W:k {k}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 26 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vptestnmb W:k {k}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.F3.0F38.W0 26 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestnmb W:k {k}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.F3.0F38.W0 26 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestnmb W:k {k}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.F3.0F38.W0 26 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vptestnmw W:k {k}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.F3.0F38.W1 26 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestnmw W:k {k}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.F3.0F38.W1 26 /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vptestnmw W:k {k}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.F3.0F38.W1 26 /r" , "vl": 0, "k": "zeroing"}, - {"inst": "vpunpckhbw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG 68 /r" , "vl": 1}, - {"inst": "vpunpckhbw W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG 68 /r" , "vl": 1}, - {"inst": "vpunpckhbw W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG 68 /r" , "vl": 0}, - {"inst": "vpunpckhwd W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG 69 /r" , "vl": 1}, - {"inst": "vpunpckhwd W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG 69 /r" , "vl": 1}, - {"inst": "vpunpckhwd W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG 69 /r" , "vl": 0}, - {"inst": "vpunpcklbw W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG 60 /r" , "vl": 1}, - {"inst": "vpunpcklbw W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG 60 /r" , "vl": 1}, - {"inst": "vpunpcklbw W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG 60 /r" , "vl": 0}, - {"inst": "vpunpcklwd W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F.WIG 61 /r" , "vl": 1}, - {"inst": "vpunpcklwd W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F.WIG 61 /r" , "vl": 1}, - {"inst": "vpunpcklwd W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F.WIG 61 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_CD", "data": [ - {"inst": "vpbroadcastmb2q W:xmm, k" , "op": "RM: EVEX.128.F3.0F38.W1 2A /r" , "vl": 1}, - {"inst": "vpbroadcastmb2q W:ymm, k" , "op": "RM: EVEX.256.F3.0F38.W1 2A /r" , "vl": 1}, - {"inst": "vpbroadcastmb2q W:zmm, k" , "op": "RM: EVEX.512.F3.0F38.W1 2A /r" , "vl": 0}, - {"inst": "vpbroadcastmw2d W:xmm, k" , "op": "RM: EVEX.128.F3.0F38.W0 3A /r" , "vl": 1}, - {"inst": "vpbroadcastmw2d W:ymm, k" , "op": "RM: EVEX.256.F3.0F38.W0 3A /r" , "vl": 1}, - {"inst": "vpbroadcastmw2d W:zmm, k" , "op": "RM: EVEX.512.F3.0F38.W0 3A /r" , "vl": 0}, - {"inst": "vpconflictd W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.66.0F38.W0 C4 /r" , "vl": 1}, - {"inst": "vpconflictd W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.66.0F38.W0 C4 /r" , "vl": 1}, - {"inst": "vpconflictd W:zmm {kz}, zmm/m512/b32" , "op": "RM-FV: EVEX.512.66.0F38.W0 C4 /r" , "vl": 0}, - {"inst": "vpconflictq W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.66.0F38.W1 C4 /r" , "vl": 1}, - {"inst": "vpconflictq W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.66.0F38.W1 C4 /r" , "vl": 1}, - {"inst": "vpconflictq W:zmm {kz}, zmm/m512/b32" , "op": "RM-FV: EVEX.512.66.0F38.W1 C4 /r" , "vl": 0}, - {"inst": "vplzcntd W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.66.0F38.W0 44 /r" , "vl": 1}, - {"inst": "vplzcntd W:ymm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.66.0F38.W0 44 /r" , "vl": 1}, - {"inst": "vplzcntd W:zmm {kz}, zmm/m512/b32" , "op": "RM-FV: EVEX.512.66.0F38.W0 44 /r" , "vl": 0}, - {"inst": "vplzcntq W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.0F38.W1 44 /r" , "vl": 1}, - {"inst": "vplzcntq W:ymm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.0F38.W1 44 /r" , "vl": 1}, - {"inst": "vplzcntq W:zmm {kz}, zmm/m512/b64" , "op": "RM-FV: EVEX.512.66.0F38.W1 44 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SCALAR", "ext": "AVX512_ER", "data": [ - {"inst": "vrcp28sd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64 {sae}" , "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 CB /r"}, - {"inst": "vrcp28ss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32 {sae}" , "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 CB /r"}, - {"inst": "vrsqrt28sd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64 {sae}" , "op": "RVM-T1S: EVEX.LIG.66.0F38.W1 CD /r"}, - {"inst": "vrsqrt28ss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32 {sae}" , "op": "RVM-T1S: EVEX.LIG.66.0F38.W0 CD /r"} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_ER", "data": [ - {"inst": "vrcp28pd W:zmm {kz}, zmm/m512/b64 {sae}" , "op": "RM-FV: EVEX.512.66.0F38.W1 CA /r"}, - {"inst": "vrcp28ps W:zmm {kz}, zmm/m512/b32 {sae}" , "op": "RM-FV: EVEX.512.66.0F38.W0 CA /r"}, - {"inst": "vrsqrt28pd W:zmm {kz}, zmm/m512/b64 {sae}" , "op": "RM-FV: EVEX.512.66.0F38.W1 CC /r"}, - {"inst": "vrsqrt28ps W:zmm {kz}, zmm/m512/b32 {sae}" , "op": "RM-FV: EVEX.512.66.0F38.W0 CC /r"}, - {"inst": "vexp2pd W:zmm {kz}, zmm/m512/b64 {sae}" , "op": "RM-FV: EVEX.512.66.0F38.W1 C8 /r"}, - {"inst": "vexp2ps W:zmm {kz}, zmm/m512/b32 {sae}" , "op": "RM-FV: EVEX.512.66.0F38.W0 C8 /r"} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_PF", "data": [ - {"inst": "vgatherpf0dpd R:vm32y {k}" , "op": "M-T1S: EVEX.512.66.0F38.W1 C6 /1"}, - {"inst": "vgatherpf0dps R:vm32z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W0 C6 /1"}, - {"inst": "vgatherpf0qpd R:vm64z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W1 C7 /1"}, - {"inst": "vgatherpf0qps R:vm64z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W0 C7 /1"}, - {"inst": "vgatherpf1dpd R:vm32y {k}" , "op": "M-T1S: EVEX.512.66.0F38.W1 C6 /2"}, - {"inst": "vgatherpf1dps R:vm32z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W0 C6 /2"}, - {"inst": "vgatherpf1qpd R:vm64z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W1 C7 /2"}, - {"inst": "vgatherpf1qps R:vm64z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W0 C7 /2"}, - {"inst": "vscatterpf0dpd R:vm32y {k}" , "op": "M-T1S: EVEX.512.66.0F38.W1 C6 /5"}, - {"inst": "vscatterpf0dps R:vm32z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W0 C6 /5"}, - {"inst": "vscatterpf0qpd R:vm64z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W1 C7 /5"}, - {"inst": "vscatterpf0qps R:vm64z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W0 C7 /5"}, - {"inst": "vscatterpf1dpd R:vm32y {k}" , "op": "M-T1S: EVEX.512.66.0F38.W1 C6 /6"}, - {"inst": "vscatterpf1dps R:vm32z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W0 C6 /6"}, - {"inst": "vscatterpf1qpd R:vm64z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W1 C7 /6"}, - {"inst": "vscatterpf1qps R:vm64z {k}" , "op": "M-T1S: EVEX.512.66.0F38.W0 C7 /6"} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_IFMA", "data": [ - {"inst": "vpmadd52luq X:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 B4 /r" , "vl": 1}, - {"inst": "vpmadd52luq X:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 B4 /r" , "vl": 1}, - {"inst": "vpmadd52luq X:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 B4 /r" , "vl": 0}, - {"inst": "vpmadd52huq X:xmm {kz}, ~xmm, ~xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 B5 /r" , "vl": 1}, - {"inst": "vpmadd52huq X:ymm {kz}, ~ymm, ~ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 B5 /r" , "vl": 1}, - {"inst": "vpmadd52huq X:zmm {kz}, ~zmm, ~zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 B5 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_VPOPCNTDQ", "data": [ - {"inst": "vpopcntd W:xmm {kz}, xmm/m128/b32" , "op": "RM-FVM: EVEX.128.66.0F38.W0 55 /r" , "vl": 1}, - {"inst": "vpopcntd W:ymm {kz}, ymm/m256/b32" , "op": "RM-FVM: EVEX.256.66.0F38.W0 55 /r" , "vl": 1}, - {"inst": "vpopcntd W:zmm {kz}, zmm/m512/b32" , "op": "RM-FVM: EVEX.512.66.0F38.W0 55 /r" , "vl": 0}, - {"inst": "vpopcntq W:xmm {kz}, xmm/m128/b64" , "op": "RM-FVM: EVEX.128.66.0F38.W1 55 /r" , "vl": 1}, - {"inst": "vpopcntq W:ymm {kz}, ymm/m256/b64" , "op": "RM-FVM: EVEX.256.66.0F38.W1 55 /r" , "vl": 1}, - {"inst": "vpopcntq W:zmm {kz}, zmm/m512/b64" , "op": "RM-FVM: EVEX.512.66.0F38.W1 55 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_VBMI", "data": [ - {"inst": "vpermb W:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W0 8D /r" , "vl": 1}, - {"inst": "vpermb W:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W0 8D /r" , "vl": 1}, - {"inst": "vpermb W:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W0 8D /r" , "vl": 0}, - {"inst": "vpermi2b X:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W0 75 /r" , "vl": 1}, - {"inst": "vpermi2b X:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W0 75 /r" , "vl": 1}, - {"inst": "vpermi2b X:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W0 75 /r" , "vl": 0}, - {"inst": "vpermt2b X:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FVM: EVEX.128.66.0F38.W0 7D /r" , "vl": 1}, - {"inst": "vpermt2b X:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FVM: EVEX.256.66.0F38.W0 7D /r" , "vl": 1}, - {"inst": "vpermt2b X:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FVM: EVEX.512.66.0F38.W0 7D /r" , "vl": 0}, - {"inst": "vpmultishiftqb W:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FV: EVEX.128.66.0F38.W1 83 /r" , "vl": 1}, - {"inst": "vpmultishiftqb W:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FV: EVEX.256.66.0F38.W1 83 /r" , "vl": 1}, - {"inst": "vpmultishiftqb W:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FV: EVEX.512.66.0F38.W1 83 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_VBMI2", "data": [ - {"inst": "vpcompressb W:xmm/m128 {kz}, xmm" , "op": "RVM-T1S: EVEX.128.66.0F38.W0 63 /r" , "vl": 1}, - {"inst": "vpcompressb W:ymm/m256 {kz}, ymm" , "op": "RVM-T1S: EVEX.256.66.0F38.W0 63 /r" , "vl": 1}, - {"inst": "vpcompressb W:zmm/m512 {kz}, zmm" , "op": "RVM-T1S: EVEX.512.66.0F38.W0 63 /r" , "vl": 0}, - {"inst": "vpcompressw W:xmm/m128 {kz}, xmm" , "op": "RVM-T1S: EVEX.128.66.0F38.W1 63 /r" , "vl": 1}, - {"inst": "vpcompressw W:ymm/m256 {kz}, ymm" , "op": "RVM-T1S: EVEX.256.66.0F38.W1 63 /r" , "vl": 1}, - {"inst": "vpcompressw W:zmm/m512 {kz}, zmm" , "op": "RVM-T1S: EVEX.512.66.0F38.W1 63 /r" , "vl": 0}, - {"inst": "vpexpandb W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.66.0F38.W0 62 /r" , "vl": 1}, - {"inst": "vpexpandb W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.66.0F38.W0 62 /r" , "vl": 1}, - {"inst": "vpexpandb W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.66.0F38.W0 62 /r" , "vl": 0}, - {"inst": "vpexpandw W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.66.0F38.W1 62 /r" , "vl": 1}, - {"inst": "vpexpandw W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.66.0F38.W1 62 /r" , "vl": 1}, - {"inst": "vpexpandw W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.66.0F38.W1 62 /r" , "vl": 0}, - {"inst": "vpshldd W:xmm {kz}, xmm, xmm/m128/b32, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.W0 71 /r ib" , "vl": 1}, - {"inst": "vpshldd W:ymm {kz}, ymm, ymm/m256/b32, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.W0 71 /r ib" , "vl": 1}, - {"inst": "vpshldd W:zmm {kz}, zmm, zmm/m512/b32, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.W0 71 /r ib" , "vl": 0}, - {"inst": "vpshldq W:xmm {kz}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.W1 71 /r ib" , "vl": 1}, - {"inst": "vpshldq W:ymm {kz}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.W1 71 /r ib" , "vl": 1}, - {"inst": "vpshldq W:zmm {kz}, zmm, zmm/m512/b64, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.W1 71 /r ib" , "vl": 0}, - {"inst": "vpshldvd X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FVM: EVEX.128.66.0F38.W0 71 /r" , "vl": 1}, - {"inst": "vpshldvd X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FVM: EVEX.256.66.0F38.W0 71 /r" , "vl": 1}, - {"inst": "vpshldvd X:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FVM: EVEX.512.66.0F38.W0 71 /r" , "vl": 0}, - {"inst": "vpshldvq X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 71 /r" , "vl": 1}, - {"inst": "vpshldvq X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 71 /r" , "vl": 1}, - {"inst": "vpshldvq X:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 71 /r" , "vl": 0}, - {"inst": "vpshldvw X:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FV: EVEX.128.66.0F38.W1 70 /r" , "vl": 1}, - {"inst": "vpshldvw X:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FV: EVEX.256.66.0F38.W1 70 /r" , "vl": 1}, - {"inst": "vpshldvw X:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FV: EVEX.512.66.0F38.W1 70 /r" , "vl": 0}, - {"inst": "vpshldw W:xmm {kz}, xmm, xmm/m128, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W1 70 /r ib" , "vl": 1}, - {"inst": "vpshldw W:ymm {kz}, ymm, ymm/m256, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W1 70 /r ib" , "vl": 1}, - {"inst": "vpshldw W:zmm {kz}, zmm, zmm/m512, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W1 70 /r ib" , "vl": 0}, - {"inst": "vpshrdd W:xmm {kz}, xmm, xmm/m128/b32, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.W0 73 /r ib" , "vl": 1}, - {"inst": "vpshrdd W:ymm {kz}, ymm, ymm/m256/b32, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.W0 73 /r ib" , "vl": 1}, - {"inst": "vpshrdd W:zmm {kz}, zmm, zmm/m512/b32, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.W0 73 /r ib" , "vl": 0}, - {"inst": "vpshrdq W:xmm {kz}, xmm, xmm/m128/b64, ib/ub" , "op": "RVM-FVM: EVEX.128.66.0F3A.W1 73 /r ib" , "vl": 1}, - {"inst": "vpshrdq W:ymm {kz}, ymm, ymm/m256/b64, ib/ub" , "op": "RVM-FVM: EVEX.256.66.0F3A.W1 73 /r ib" , "vl": 1}, - {"inst": "vpshrdq W:zmm {kz}, zmm, zmm/m512/b64, ib/ub" , "op": "RVM-FVM: EVEX.512.66.0F3A.W1 73 /r ib" , "vl": 0}, - {"inst": "vpshrdvd X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FVM: EVEX.128.66.0F38.W0 73 /r" , "vl": 1}, - {"inst": "vpshrdvd X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FVM: EVEX.256.66.0F38.W0 73 /r" , "vl": 1}, - {"inst": "vpshrdvd X:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FVM: EVEX.512.66.0F38.W0 73 /r" , "vl": 0}, - {"inst": "vpshrdvq X:xmm {kz}, xmm, xmm/m128/b64" , "op": "RVM-FVM: EVEX.128.66.0F38.W1 73 /r" , "vl": 1}, - {"inst": "vpshrdvq X:ymm {kz}, ymm, ymm/m256/b64" , "op": "RVM-FVM: EVEX.256.66.0F38.W1 73 /r" , "vl": 1}, - {"inst": "vpshrdvq X:zmm {kz}, zmm, zmm/m512/b64" , "op": "RVM-FVM: EVEX.512.66.0F38.W1 73 /r" , "vl": 0}, - {"inst": "vpshrdvw X:xmm {kz}, xmm, xmm/m128" , "op": "RVM-FV: EVEX.128.66.0F38.W1 72 /r" , "vl": 1}, - {"inst": "vpshrdvw X:ymm {kz}, ymm, ymm/m256" , "op": "RVM-FV: EVEX.256.66.0F38.W1 72 /r" , "vl": 1}, - {"inst": "vpshrdvw X:zmm {kz}, zmm, zmm/m512" , "op": "RVM-FV: EVEX.512.66.0F38.W1 72 /r" , "vl": 0}, - {"inst": "vpshrdw W:xmm {kz}, xmm, xmm/m128, ib/ub" , "op": "RVM-FV: EVEX.128.66.0F3A.W1 72 /r ib" , "vl": 1}, - {"inst": "vpshrdw W:ymm {kz}, ymm, ymm/m256, ib/ub" , "op": "RVM-FV: EVEX.256.66.0F3A.W1 72 /r ib" , "vl": 1}, - {"inst": "vpshrdw W:zmm {kz}, zmm, zmm/m512, ib/ub" , "op": "RVM-FV: EVEX.512.66.0F3A.W1 72 /r ib" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_4FMAPS", "data": [ - {"inst": "v4fmaddps X:zmm {kz}, zmm, zmm+1, zmm+2, zmm+3, m128" , "op": "RM-T1_4X: EVEX.512.F2.0F38.W0 9A /r" , "vl": 0}, - {"inst": "v4fmaddss X:xmm {kz}, xmm, xmm+1, xmm+2, xmm+3, m128" , "op": "RM-T1_4X: EVEX.LIG.F2.0F38.W0 9B /r" , "vl": 0}, - {"inst": "v4fnmaddps X:zmm {kz}, zmm, zmm+1, zmm+2, zmm+3, m128" , "op": "RM-T1_4X: EVEX.512.F2.0F38.W0 AA /r" , "vl": 0}, - {"inst": "v4fnmaddss X:xmm {kz}, xmm, xmm+1, xmm+2, xmm+3, m128" , "op": "RM-T1_4X: EVEX.LIG.F2.0F38.W0 AB /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_4VNNIW", "data": [ - {"inst": "vp4dpwssd W:zmm {kz}, zmm, zmm+1, zmm+2, zmm+3, m128" , "op": "RM-T1_4X: EVEX.512.F2.0F38.W0 52 /r" , "vl": 0}, - {"inst": "vp4dpwssds W:zmm {kz}, zmm, zmm+1, zmm+2, zmm+3, m128" , "op": "RM-T1_4X: EVEX.512.F2.0F38.W0 53 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_VNNI", "data": [ - {"inst": "vpdpbusd X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 50 /r" , "vl": 1}, - {"inst": "vpdpbusd X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 50 /r" , "vl": 1}, - {"inst": "vpdpbusd X:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 50 /r" , "vl": 0}, - {"inst": "vpdpbusds X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 51 /r" , "vl": 1}, - {"inst": "vpdpbusds X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 51 /r" , "vl": 1}, - {"inst": "vpdpbusds X:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 51 /r" , "vl": 0}, - {"inst": "vpdpwssd X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 52 /r" , "vl": 1}, - {"inst": "vpdpwssd X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 52 /r" , "vl": 1}, - {"inst": "vpdpwssd X:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 52 /r" , "vl": 0}, - {"inst": "vpdpwssds X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.66.0F38.W0 53 /r" , "vl": 1}, - {"inst": "vpdpwssds X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.66.0F38.W0 53 /r" , "vl": 1}, - {"inst": "vpdpwssds X:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.66.0F38.W0 53 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_BITALG", "data": [ - {"inst": "vpopcntb W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.66.0F38.W0 54 /r" , "vl": 1}, - {"inst": "vpopcntb W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.66.0F38.W0 54 /r" , "vl": 1}, - {"inst": "vpopcntb W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.66.0F38.W0 54 /r" , "vl": 0}, - {"inst": "vpopcntw W:xmm {kz}, xmm/m128" , "op": "RM-FVM: EVEX.128.66.0F38.W1 54 /r" , "vl": 1}, - {"inst": "vpopcntw W:ymm {kz}, ymm/m256" , "op": "RM-FVM: EVEX.256.66.0F38.W1 54 /r" , "vl": 1}, - {"inst": "vpopcntw W:zmm {kz}, zmm/m512" , "op": "RM-FVM: EVEX.512.66.0F38.W1 54 /r" , "vl": 0}, - {"inst": "vpshufbitqmb W:k {k}, xmm, xmm/m128" , "op": "RM-FVM: EVEX.128.66.0F38.W0 8F /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpshufbitqmb W:k {k}, ymm, ymm/m256" , "op": "RM-FVM: EVEX.256.66.0F38.W0 8F /r" , "vl": 1, "k": "zeroing"}, - {"inst": "vpshufbitqmb W:k {k}, zmm, zmm/m512" , "op": "RM-FVM: EVEX.512.66.0F38.W0 8F /r" , "vl": 0, "k": "zeroing"} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_VP2INTERSECT", "data": [ - {"inst": "vp2intersectd W:k, W:k+1, xmm, xmm/m128/b32" , "op": "RVM: EVEX.128.F2.0F38.W0 68 /r" , "vl": 1}, - {"inst": "vp2intersectd W:k, W:k+1, ymm, ymm/m256/b32" , "op": "RVM: EVEX.256.F2.0F38.W0 68 /r" , "vl": 1}, - {"inst": "vp2intersectd W:k, W:k+1, zmm, zmm/m512/b32" , "op": "RVM: EVEX.512.F2.0F38.W0 68 /r" , "vl": 0}, - {"inst": "vp2intersectq W:k, W:k+1, xmm, xmm/m128/b64" , "op": "RVM: EVEX.128.F2.0F38.W1 68 /r" , "vl": 1}, - {"inst": "vp2intersectq W:k, W:k+1, ymm, ymm/m256/b64" , "op": "RVM: EVEX.256.F2.0F38.W1 68 /r" , "vl": 1}, - {"inst": "vp2intersectq W:k, W:k+1, zmm, zmm/m512/b64" , "op": "RVM: EVEX.512.F2.0F38.W1 68 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_BF16", "data": [ - {"inst": "vcvtne2ps2bf16 W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.F2.0F38.W0 72 /r" , "vl": 1}, - {"inst": "vcvtne2ps2bf16 W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.F2.0F38.W0 72 /r" , "vl": 1}, - {"inst": "vcvtne2ps2bf16 W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.F2.0F38.W0 72 /r" , "vl": 0}, - {"inst": "vcvtneps2bf16 W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.F3.0F38.W0 72 /r" , "vl": 1}, - {"inst": "vcvtneps2bf16 W:xmm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.F3.0F38.W0 72 /r" , "vl": 1}, - {"inst": "vcvtneps2bf16 W:ymm {kz}, zmm/m512/b32" , "op": "RM-FV: EVEX.512.F3.0F38.W0 72 /r" , "vl": 0}, - {"inst": "vdpbf16ps W:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.F3.0F38.W0 52 /r" , "vl": 1}, - {"inst": "vdpbf16ps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.F3.0F38.W0 52 /r" , "vl": 1}, - {"inst": "vdpbf16ps W:zmm {kz}, zmm, zmm/m512/b32" , "op": "RVM-FV: EVEX.512.F3.0F38.W0 52 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SCALAR", "ext": "AVX512_FP16", "data": [ - {"inst": "vaddsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W0 58 /r" , "vl": 0}, - {"inst": "vcmpsh W:k {k}, xmm[15:0], xmm[15:0]/m16, ib/ub {sae}" , "op": "RVM-T1S: EVEX.LIG.F3.0F3A.W0 C2 /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vcomish R:xmm[15:0], xmm[15:0]/m16 {sae}" , "op": "RM-T1S: EVEX.LIG.NP.MAP5.W0 2F /r" , "vl": 0, "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, - {"inst": "vcvtsd2sh W:xmm {kz}, xmm, xmm/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.MAP5.W1 5A /r" , "vl": 0}, - {"inst": "vcvtsh2sd W:xmm {kz}, xmm, xmm/m16 {sae}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W0 5A /r" , "vl": 0}, - {"inst": "vcvtsh2si W:r32, xmm/m16 {er}" , "op": "RM-T1S: EVEX.LIG.F3.MAP5.W0 2D /r" , "vl": 0}, - {"inst": "vcvtsh2si W:r64, xmm/m16 {er}" , "op": "RM-T1S: EVEX.LIG.F3.MAP5.W1 2D /r" , "vl": 0}, - {"inst": "vcvtsh2ss W:xmm {kz}, xmm, xmm/m16 {sae}" , "op": "RVM-T1S: EVEX.LIG.NP.MAP6.W0 13 /r" , "vl": 0}, - {"inst": "vcvtsh2usi W:r32, xmm/m16 {er}" , "op": "RM-T1S: EVEX.LIG.F3.MAP5.W0 79 /r" , "vl": 0}, - {"inst": "vcvtsh2usi W:r64, xmm/m16 {er}" , "op": "RM-T1S: EVEX.LIG.F3.MAP5.W1 79 /r" , "vl": 0}, - {"inst": "vcvtsi2sh W:xmm, xmm, r32/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W0 2A /r" , "vl": 0}, - {"inst": "vcvtsi2sh W:xmm, xmm, r64/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W1 2A /r" , "vl": 0}, - {"inst": "vcvtss2sh W:xmm {kz}, xmm, xmm/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.NP.MAP5.W0 1D /r" , "vl": 0}, - {"inst": "vcvttsh2si W:r32, xmm/m16 {sae}" , "op": "RM-T1S: EVEX.LIG.F3.MAP5.W0 2C /r" , "vl": 0}, - {"inst": "vcvttsh2si W:r64, xmm/m16 {sae}" , "op": "RM-T1S: EVEX.LIG.F3.MAP5.W1 2C /r" , "vl": 0}, - {"inst": "vcvttsh2usi W:r32, xmm/m16 {sae}" , "op": "RM-T1S: EVEX.LIG.F3.MAP5.W0 78 /r" , "vl": 0}, - {"inst": "vcvttsh2usi W:r64, xmm/m16 {sae}" , "op": "RM-T1S: EVEX.LIG.F3.MAP5.W1 78 /r" , "vl": 0}, - {"inst": "vcvtusi2sh W:xmm, xmm, r32/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W0 7B /r" , "vl": 0}, - {"inst": "vcvtusi2sh W:xmm, xmm, r64/m64 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W1 7B /r" , "vl": 0}, - {"inst": "vdivsh W:xmm {kz}, xmm, xmm/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W0 5E /r" , "vl": 0}, - {"inst": "vfmadd132sh X:xmm {kz}, xmm, xmm/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 99 /r" , "vl": 0}, - {"inst": "vfmadd213sh X:xmm {kz}, xmm, xmm/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 A9 /r" , "vl": 0}, - {"inst": "vfmadd231sh X:xmm {kz}, xmm, xmm/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 B9 /r" , "vl": 0}, - {"inst": "vfmsub132sh X:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 9B /r" , "vl": 0}, - {"inst": "vfmsub213sh X:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 AB /r" , "vl": 0}, - {"inst": "vfmsub231sh X:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 BB /r" , "vl": 0}, - {"inst": "vfnmadd132sh X:xmm {kz}, xmm, xmm/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 9D /r" , "vl": 0}, - {"inst": "vfnmadd213sh X:xmm {kz}, xmm, xmm/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 AD /r" , "vl": 0}, - {"inst": "vfnmadd231sh X:xmm {kz}, xmm, xmm/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 BD /r" , "vl": 0}, - {"inst": "vfnmsub132sh X:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 9F /r" , "vl": 0}, - {"inst": "vfnmsub213sh X:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 AF /r" , "vl": 0}, - {"inst": "vfnmsub231sh X:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 BF /r" , "vl": 0}, - {"inst": "vfpclasssh W:k {k}, xmm[15:0]/m16, ib/ub" , "op": "RM-T1S: EVEX.LIG.NP.0F3A.W0 67 /r ib" , "vl": 0}, - {"inst": "vgetexpsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16 {sae}" , "op": "RM-T1S: EVEX.LIG.66.MAP6.W0 43 /r" , "vl": 0}, - {"inst": "vgetmantsh W:xmm {kz},xmm[127:16],xmm[15:0]/m16,ib/ub {sae}", "op": "RM-T1S: EVEX.LIG.NP.0F3A.W0 27 /r ib" , "vl": 0}, - {"inst": "vmaxsh W:xmm {kz}, xmm, xmm[15:0]/m16 {sae}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W0 5F /r" , "vl": 0}, - {"inst": "vminsh W:xmm {kz}, xmm, xmm[15:0]/m16 {sae}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W0 5D /r" , "vl": 0}, - {"inst": "vmovsh W:m16, xmm[15:0]" , "op": "MR-T1S: EVEX.LIG.F3.MAP5.W0 11 /r" , "vl": 0}, - {"inst": "vmovsh W:xmm[15:0] {kz}, m16" , "op": "RM-T1S: EVEX.LIG.F3.MAP5.W0 10 /r" , "vl": 0}, - {"inst": "vmovsh W:xmm {kz}, xmm[127:16], xmm[15:0]" , "op": "MVR: EVEX.LIG.F3.MAP5.W0 11 /r" , "vl": 0}, - {"inst": "vmovsh W:xmm {kz}, xmm[127:16], xmm[15:0]" , "op": "RVM: EVEX.LIG.F3.MAP5.W0 10 /r" , "vl": 0}, - {"inst": "vmulsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W0 59 /r" , "vl": 0}, - {"inst": "vrcpsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 4D /r" , "vl": 0}, - {"inst": "vreducesh W:xmm {kz},xmm[127:16],xmm[15:0]/m16,ib/ub {sae}" , "op": "RVM-T1S: EVEX.LIG.NP.0F3A.W0 57 /r ib" , "vl": 0}, - {"inst": "vrndscalesh W:xmm {kz},xmm[127:16],xmm[15:0]/m16,ib/ub {sae}","op": "RVM-T1S: EVEX.LIG.NP.0F3A.W0 0A /r ib" , "vl": 0}, - {"inst": "vrsqrtsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 4F /r" , "vl": 0}, - {"inst": "vscalefsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.66.MAP6.W0 2D /r" , "vl": 0}, - {"inst": "vsqrtsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W0 51 /r" , "vl": 0}, - {"inst": "vsubsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP5.W0 5C /r" , "vl": 0}, - {"inst": "vucomish R:xmm[15:0], xmm[15:0]/m16 {sae}" , "op": "RM-T1S: EVEX.LIG.NP.MAP5.W0 2E /r" , "vl": 0, "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, - {"inst": "vfcmaddcsh X:xmm {kz}, xmm, xmm/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.MAP6.W0 57 /r" , "vl": 0}, - {"inst": "vfcmulcsh X:xmm {kz}, xmm, xmm/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F2.MAP6.W0 D7 /r" , "vl": 0}, - {"inst": "vfmaddcsh X:xmm {kz}, xmm, xmm/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP6.W0 57 /r" , "vl": 0} - ]}, - - {"category": "AVX512 SIMD", "ext": "AVX512_FP16", "data": [ - {"inst": "vaddph W:xmm {kz}, ~xmm, ~xmm/m128/b16" , "op": "RVM-FV: EVEX.128.NP.MAP5.W0 58 /r" , "vl": 1}, - {"inst": "vaddph W:ymm {kz}, ~ymm, ~ymm/m256/b16" , "op": "RVM-FV: EVEX.256.NP.MAP5.W0 58 /r" , "vl": 1}, - {"inst": "vaddph W:zmm {kz}, ~zmm, ~zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.NP.MAP5.W0 58 /r" , "vl": 0}, - {"inst": "vcmpph W:k {k}, xmm, xmm/m128/b16, ib/ub" , "op": "RVM-FV: EVEX.128.NP.0F3A.W0 C2 /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vcmpph W:k {k}, ymm, ymm/m256/b16, ib/ub" , "op": "RVM-FV: EVEX.256.NP.0F3A.W0 C2 /r ib" , "vl": 1, "k": "zeroing"}, - {"inst": "vcmpph W:k {k}, zmm, zmm/m512/b16, ib/ub {sae}" , "op": "RVM-FV: EVEX.512.NP.0F3A.W0 C2 /r ib" , "vl": 0, "k": "zeroing"}, - {"inst": "vcvtdq2ph W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.NP.MAP5.W0 5B /r" , "vl": 1}, - {"inst": "vcvtdq2ph W:xmm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.NP.MAP5.W0 5B /r" , "vl": 1}, - {"inst": "vcvtdq2ph W:ymm {kz}, zmm/m512/b32 {er}" , "op": "RM-FV: EVEX.512.NP.MAP5.W0 5B /r" , "vl": 0}, - {"inst": "vcvtpd2ph W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.66.MAP5.W1 5A /r" , "vl": 1}, - {"inst": "vcvtpd2ph W:xmm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.66.MAP5.W1 5A /r" , "vl": 1}, - {"inst": "vcvtpd2ph W:xmm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.66.MAP5.W1 5A /r" , "vl": 0}, - {"inst": "vcvtph2dq W:xmm {kz}, xmm/m64/b16" , "op": "RM-HV: EVEX.128.66.MAP5.W0 5B /r" , "vl": 1}, - {"inst": "vcvtph2dq W:ymm {kz}, xmm/m128/b16" , "op": "RM-HV: EVEX.256.66.MAP5.W0 5B /r" , "vl": 1}, - {"inst": "vcvtph2dq W:zmm {kz}, ymm/m256/b16 {er}" , "op": "RM-HV: EVEX.512.66.MAP5.W0 5B /r" , "vl": 0}, - {"inst": "vcvtph2pd W:xmm {kz}, xmm/m32/b16" , "op": "RM-QV: EVEX.128.NP.MAP5.W0 5A /r" , "vl": 1}, - {"inst": "vcvtph2pd W:ymm {kz}, xmm/m64/b16" , "op": "RM-QV: EVEX.256.NP.MAP5.W0 5A /r" , "vl": 1}, - {"inst": "vcvtph2pd W:zmm {kz}, xmm/m128/b16 {sae}" , "op": "RM-QV: EVEX.512.NP.MAP5.W0 5A /r" , "vl": 0}, - {"inst": "vcvtph2psx W:xmm {kz}, xmm/m64/b16" , "op": "RM-HV: EVEX.128.66.MAP6.W0 13 /r" , "vl": 1}, - {"inst": "vcvtph2psx W:ymm {kz}, xmm/m128/b16" , "op": "RM-HV: EVEX.256.66.MAP6.W0 13 /r" , "vl": 1}, - {"inst": "vcvtph2psx W:zmm {kz}, ymm/m256/b16 {sae}" , "op": "RM-HV: EVEX.512.66.MAP6.W0 13 /r" , "vl": 0}, - {"inst": "vcvtph2qq W:xmm {kz}, xmm/m32/b16" , "op": "RM-QV: EVEX.128.66.MAP5.W0 7B /r" , "vl": 1}, - {"inst": "vcvtph2qq W:ymm {kz}, xmm/m64/b16" , "op": "RM-QV: EVEX.256.66.MAP5.W0 7B /r" , "vl": 1}, - {"inst": "vcvtph2qq W:zmm {kz}, xmm/m128/b16 {er}" , "op": "RM-QV: EVEX.512.66.MAP5.W0 7B /r" , "vl": 0}, - {"inst": "vcvtph2udq W:xmm {kz}, xmm/m64/b16" , "op": "RM-HV: EVEX.128.NP.MAP5.W0 79 /r" , "vl": 1}, - {"inst": "vcvtph2udq W:ymm {kz}, xmm/m128/b16" , "op": "RM-HV: EVEX.256.NP.MAP5.W0 79 /r" , "vl": 1}, - {"inst": "vcvtph2udq W:zmm {kz}, ymm/m256/b16 {er}" , "op": "RM-HV: EVEX.512.NP.MAP5.W0 79 /r" , "vl": 0}, - {"inst": "vcvtph2uqq W:xmm {kz}, xmm/m32/b16" , "op": "RM-QV: EVEX.128.66.MAP5.W0 79 /r" , "vl": 1}, - {"inst": "vcvtph2uqq W:ymm {kz}, xmm/m64/b16" , "op": "RM-QV: EVEX.256.66.MAP5.W0 79 /r" , "vl": 1}, - {"inst": "vcvtph2uqq W:zmm {kz}, xmm/m128/b16 {er}" , "op": "RM-QV: EVEX.512.66.MAP5.W0 79 /r" , "vl": 0}, - {"inst": "vcvtph2uw W:xmm {kz}, xmm/m128/b16" , "op": "RM-FV: EVEX.128.NP.MAP5.W0 7D /r" , "vl": 1}, - {"inst": "vcvtph2uw W:ymm {kz}, ymm/m256/b16" , "op": "RM-FV: EVEX.256.NP.MAP5.W0 7D /r" , "vl": 1}, - {"inst": "vcvtph2uw W:zmm {kz}, zmm/m512/b16 {er}" , "op": "RM-FV: EVEX.512.NP.MAP5.W0 7D /r" , "vl": 0}, - {"inst": "vcvtph2w W:xmm {kz}, xmm/m128/b16" , "op": "RM-FV: EVEX.128.66.MAP5.W0 7D /r" , "vl": 1}, - {"inst": "vcvtph2w W:ymm {kz}, ymm/m256/b16" , "op": "RM-FV: EVEX.256.66.MAP5.W0 7D /r" , "vl": 1}, - {"inst": "vcvtph2w W:zmm {kz}, zmm/m512/b16 {er}" , "op": "RM-FV: EVEX.512.66.MAP5.W0 7D /r" , "vl": 0}, - {"inst": "vcvtps2phx W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.66.MAP5.W0 1D /r" , "vl": 1}, - {"inst": "vcvtps2phx W:xmm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.66.MAP5.W0 1D /r" , "vl": 1}, - {"inst": "vcvtps2phx W:ymm {kz}, zmm/m512/b32 {er}" , "op": "RM-FV: EVEX.512.66.MAP5.W0 1D /r" , "vl": 0}, - {"inst": "vcvtqq2ph W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.NP.MAP5.W1 5B /r" , "vl": 1}, - {"inst": "vcvtqq2ph W:xmm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.NP.MAP5.W1 5B /r" , "vl": 1}, - {"inst": "vcvtqq2ph W:xmm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.NP.MAP5.W1 5B /r" , "vl": 0}, - {"inst": "vcvttph2dq W:xmm {kz}, xmm/m64/b16" , "op": "RM-HV: EVEX.128.F3.MAP5.W0 5B /r" , "vl": 1}, - {"inst": "vcvttph2dq W:ymm {kz}, xmm/m128/b16" , "op": "RM-HV: EVEX.256.F3.MAP5.W0 5B /r" , "vl": 1}, - {"inst": "vcvttph2dq W:zmm {kz}, ymm/m256/b16 {sae}" , "op": "RM-HV: EVEX.512.F3.MAP5.W0 5B /r" , "vl": 0}, - {"inst": "vcvttph2qq W:xmm {kz}, xmm/m32/b16" , "op": "RM-QV: EVEX.128.66.MAP5.W0 7A /r" , "vl": 1}, - {"inst": "vcvttph2qq W:ymm {kz}, xmm/m64/b16" , "op": "RM-QV: EVEX.256.66.MAP5.W0 7A /r" , "vl": 1}, - {"inst": "vcvttph2qq W:zmm {kz}, xmm/m128/b16 {sae}" , "op": "RM-QV: EVEX.512.66.MAP5.W0 7A /r" , "vl": 0}, - {"inst": "vcvttph2udq W:xmm {kz}, xmm/m64/b16" , "op": "RM-HV: EVEX.128.NP.MAP5.W0 78 /r" , "vl": 1}, - {"inst": "vcvttph2udq W:ymm {kz}, xmm/m128/b16" , "op": "RM-HV: EVEX.256.NP.MAP5.W0 78 /r" , "vl": 1}, - {"inst": "vcvttph2udq W:zmm {kz}, ymm/m256/b16 {sae}" , "op": "RM-HV: EVEX.512.NP.MAP5.W0 78 /r" , "vl": 0}, - {"inst": "vcvttph2uqq W:xmm {kz}, xmm/m32/b16" , "op": "RM-QV: EVEX.128.66.MAP5.W0 78 /r" , "vl": 1}, - {"inst": "vcvttph2uqq W:ymm {kz}, xmm/m64/b16" , "op": "RM-QV: EVEX.256.66.MAP5.W0 78 /r" , "vl": 1}, - {"inst": "vcvttph2uqq W:zmm {kz}, xmm/m128/b16 {sae}" , "op": "RM-QV: EVEX.512.66.MAP5.W0 78 /r" , "vl": 0}, - {"inst": "vcvttph2uw W:xmm {kz}, xmm/m128/b16" , "op": "RM-FV: EVEX.128.NP.MAP5.W0 7C /r" , "vl": 1}, - {"inst": "vcvttph2uw W:ymm {kz}, ymm/m256/b16" , "op": "RM-FV: EVEX.256.NP.MAP5.W0 7C /r" , "vl": 1}, - {"inst": "vcvttph2uw W:zmm {kz}, zmm/m512/b16 {sae}" , "op": "RM-FV: EVEX.512.NP.MAP5.W0 7C /r" , "vl": 0}, - {"inst": "vcvttph2w W:xmm {kz}, xmm/m128/b16" , "op": "RM-FV: EVEX.128.66.MAP5.W0 7C /r" , "vl": 1}, - {"inst": "vcvttph2w W:ymm {kz}, ymm/m256/b16" , "op": "RM-FV: EVEX.256.66.MAP5.W0 7C /r" , "vl": 1}, - {"inst": "vcvttph2w W:zmm {kz}, zmm/m512/b16 {sae}" , "op": "RM-FV: EVEX.512.66.MAP5.W0 7C /r" , "vl": 0}, - {"inst": "vcvtudq2ph W:xmm {kz}, xmm/m128/b32" , "op": "RM-FV: EVEX.128.F2.MAP5.W0 7A /r" , "vl": 1}, - {"inst": "vcvtudq2ph W:xmm {kz}, ymm/m256/b32" , "op": "RM-FV: EVEX.256.F2.MAP5.W0 7A /r" , "vl": 1}, - {"inst": "vcvtudq2ph W:ymm {kz}, zmm/m512/b32 {er}" , "op": "RM-FV: EVEX.512.F2.MAP5.W0 7A /r" , "vl": 0}, - {"inst": "vcvtuqq2ph W:xmm {kz}, xmm/m128/b64" , "op": "RM-FV: EVEX.128.F2.MAP5.W1 7A /r" , "vl": 1}, - {"inst": "vcvtuqq2ph W:xmm {kz}, ymm/m256/b64" , "op": "RM-FV: EVEX.256.F2.MAP5.W1 7A /r" , "vl": 1}, - {"inst": "vcvtuqq2ph W:xmm {kz}, zmm/m512/b64 {er}" , "op": "RM-FV: EVEX.512.F2.MAP5.W1 7A /r" , "vl": 0}, - {"inst": "vcvtuw2ph W:xmm {kz}, xmm/m128/b16" , "op": "RM-FV: EVEX.128.F2.MAP5.W0 7D /r" , "vl": 1}, - {"inst": "vcvtuw2ph W:ymm {kz}, ymm/m256/b16" , "op": "RM-FV: EVEX.256.F2.MAP5.W0 7D /r" , "vl": 1}, - {"inst": "vcvtuw2ph W:zmm {kz}, zmm/m512/b16 {er}" , "op": "RM-FV: EVEX.512.F2.MAP5.W0 7D /r" , "vl": 0}, - {"inst": "vcvtw2ph W:xmm {kz}, xmm/m128/b16" , "op": "RM-FV: EVEX.128.F3.MAP5.W0 7D /r" , "vl": 1}, - {"inst": "vcvtw2ph W:ymm {kz}, ymm/m256/b16" , "op": "RM-FV: EVEX.256.F3.MAP5.W0 7D /r" , "vl": 1}, - {"inst": "vcvtw2ph W:zmm {kz}, zmm/m512/b16 {er}" , "op": "RM-FV: EVEX.512.F3.MAP5.W0 7D /r" , "vl": 0}, - {"inst": "vdivph W:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.NP.MAP5.W0 5E /r" , "vl": 1}, - {"inst": "vdivph W:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.NP.MAP5.W0 5E /r" , "vl": 1}, - {"inst": "vdivph W:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.NP.MAP5.W0 5E /r" , "vl": 0}, - {"inst": "vfcmaddcph X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.F2.MAP6.W0 56 /r" , "vl": 1}, - {"inst": "vfcmaddcph X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.F2.MAP6.W0 56 /r" , "vl": 1}, - {"inst": "vfcmaddcph X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.F2.MAP6.W0 56 /r" , "vl": 0}, - {"inst": "vfcmulcph X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.F2.MAP6.W0 D6 /r" , "vl": 1}, - {"inst": "vfcmulcph X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.F2.MAP6.W0 D6 /r" , "vl": 1}, - {"inst": "vfcmulcph X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.F2.MAP6.W0 D6 /r" , "vl": 0}, - {"inst": "vfmadd132ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 98 /r" , "vl": 1}, - {"inst": "vfmadd132ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 98 /r" , "vl": 1}, - {"inst": "vfmadd132ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 98 /r" , "vl": 0}, - {"inst": "vfmadd213ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 A8 /r" , "vl": 1}, - {"inst": "vfmadd213ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 A8 /r" , "vl": 1}, - {"inst": "vfmadd213ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 A8 /r" , "vl": 0}, - {"inst": "vfmadd231ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 B8 /r" , "vl": 1}, - {"inst": "vfmadd231ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 B8 /r" , "vl": 1}, - {"inst": "vfmadd231ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 B8 /r" , "vl": 0}, - {"inst": "vfmaddcph X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.F3.MAP6.W0 56 /r" , "vl": 1}, - {"inst": "vfmaddcph X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.F3.MAP6.W0 56 /r" , "vl": 1}, - {"inst": "vfmaddcph X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.F3.MAP6.W0 56 /r" , "vl": 0}, - {"inst": "vfmaddsub132ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 96 /r" , "vl": 1}, - {"inst": "vfmaddsub132ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 96 /r" , "vl": 1}, - {"inst": "vfmaddsub132ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 96 /r" , "vl": 0}, - {"inst": "vfmaddsub213ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 A6 /r" , "vl": 1}, - {"inst": "vfmaddsub213ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 A6 /r" , "vl": 1}, - {"inst": "vfmaddsub213ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 A6 /r" , "vl": 0}, - {"inst": "vfmaddsub231ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 B6 /r" , "vl": 1}, - {"inst": "vfmaddsub231ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 B6 /r" , "vl": 1}, - {"inst": "vfmaddsub231ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 B6 /r" , "vl": 0}, - {"inst": "vfmsub132ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 9A /r" , "vl": 1}, - {"inst": "vfmsub132ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 9A /r" , "vl": 1}, - {"inst": "vfmsub132ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 9A /r" , "vl": 0}, - {"inst": "vfmsub213ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 AA /r" , "vl": 1}, - {"inst": "vfmsub213ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 AA /r" , "vl": 1}, - {"inst": "vfmsub213ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 AA /r" , "vl": 0}, - {"inst": "vfmsub231ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 BA /r" , "vl": 1}, - {"inst": "vfmsub231ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 BA /r" , "vl": 1}, - {"inst": "vfmsub231ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 BA /r" , "vl": 0}, - {"inst": "vfmsubadd132ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 97 /r" , "vl": 1}, - {"inst": "vfmsubadd132ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 97 /r" , "vl": 1}, - {"inst": "vfmsubadd132ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 97 /r" , "vl": 0}, - {"inst": "vfmsubadd213ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 A7 /r" , "vl": 1}, - {"inst": "vfmsubadd213ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 A7 /r" , "vl": 1}, - {"inst": "vfmsubadd213ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 A7 /r" , "vl": 0}, - {"inst": "vfmsubadd231ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 B7 /r" , "vl": 1}, - {"inst": "vfmsubadd231ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 B7 /r" , "vl": 1}, - {"inst": "vfmsubadd231ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 B7 /r" , "vl": 0}, - {"inst": "vfmulcph X:xmm {kz}, xmm, xmm/m128/b32" , "op": "RVM-FV: EVEX.128.F3.MAP6.W0 D6 /r" , "vl": 1}, - {"inst": "vfmulcph X:ymm {kz}, ymm, ymm/m256/b32" , "op": "RVM-FV: EVEX.256.F3.MAP6.W0 D6 /r" , "vl": 1}, - {"inst": "vfmulcph X:zmm {kz}, zmm, zmm/m512/b32 {er}" , "op": "RVM-FV: EVEX.512.F3.MAP6.W0 D6 /r" , "vl": 0}, - {"inst": "vfmulcsh X:xmm {kz}, xmm, xmm/m32 {er}" , "op": "RVM-T1S: EVEX.LIG.F3.MAP6.W0 D7 /r" , "vl": 1}, - {"inst": "vfnmadd132ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 9C /r" , "vl": 1}, - {"inst": "vfnmadd132ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 9C /r" , "vl": 1}, - {"inst": "vfnmadd132ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 9C /r" , "vl": 0}, - {"inst": "vfnmadd213ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 AC /r" , "vl": 1}, - {"inst": "vfnmadd213ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 AC /r" , "vl": 1}, - {"inst": "vfnmadd213ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 AC /r" , "vl": 0}, - {"inst": "vfnmadd231ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 BC /r" , "vl": 1}, - {"inst": "vfnmadd231ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 BC /r" , "vl": 1}, - {"inst": "vfnmadd231ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 BC /r" , "vl": 0}, - {"inst": "vfnmsub132ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 9E /r" , "vl": 1}, - {"inst": "vfnmsub132ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 9E /r" , "vl": 1}, - {"inst": "vfnmsub132ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 9E /r" , "vl": 0}, - {"inst": "vfnmsub213ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 AE /r" , "vl": 1}, - {"inst": "vfnmsub213ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 AE /r" , "vl": 1}, - {"inst": "vfnmsub213ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 AE /r" , "vl": 0}, - {"inst": "vfnmsub231ph X:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 BE /r" , "vl": 1}, - {"inst": "vfnmsub231ph X:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 BE /r" , "vl": 1}, - {"inst": "vfnmsub231ph X:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 BE /r" , "vl": 0}, - {"inst": "vfpclassph W:k {k}, xmm/m128/b16, ib/ub" , "op": "RM-FV: EVEX.128.NP.0F3A.W0 66 /r ib" , "vl": 1}, - {"inst": "vfpclassph W:k {k}, ymm/m256/b16, ib/ub" , "op": "RM-FV: EVEX.256.NP.0F3A.W0 66 /r ib" , "vl": 1}, - {"inst": "vfpclassph W:k {k}, zmm/m512/b16, ib/ub" , "op": "RM-FV: EVEX.512.NP.0F3A.W0 66 /r ib" , "vl": 0}, - {"inst": "vgetexpph W:xmm {kz}, xmm/m128/b16" , "op": "RM-FV: EVEX.128.66.MAP6.W0 42 /r" , "vl": 1}, - {"inst": "vgetexpph W:ymm {kz}, ymm/m256/b16" , "op": "RM-FV: EVEX.256.66.MAP6.W0 42 /r" , "vl": 1}, - {"inst": "vgetexpph W:zmm {kz}, zmm/m512/b16 {sae}" , "op": "RM-FV: EVEX.512.66.MAP6.W0 42 /r" , "vl": 0}, - {"inst": "vgetmantph W:xmm {kz}, xmm/m128/b16, ib/ub" , "op": "RM-FV: EVEX.128.NP.0F3A.W0 26 /r ib" , "vl": 1}, - {"inst": "vgetmantph W:ymm {kz}, ymm/m256/b16, ib/ub" , "op": "RM-FV: EVEX.256.NP.0F3A.W0 26 /r ib" , "vl": 1}, - {"inst": "vgetmantph W:zmm {kz}, zmm/m512/b16, ib/ub {sae}" , "op": "RM-FV: EVEX.512.NP.0F3A.W0 26 /r ib" , "vl": 0}, - {"inst": "vmaxph W:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.NP.MAP5.W0 5F /r" , "vl": 1}, - {"inst": "vmaxph W:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.NP.MAP5.W0 5F /r" , "vl": 1}, - {"inst": "vmaxph W:zmm {kz}, zmm, zmm/m512/b16 {sae}" , "op": "RVM-FV: EVEX.512.NP.MAP5.W0 5F /r" , "vl": 0}, - {"inst": "vminph W:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.NP.MAP5.W0 5D /r" , "vl": 1}, - {"inst": "vminph W:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.NP.MAP5.W0 5D /r" , "vl": 1}, - {"inst": "vminph W:zmm {kz}, zmm, zmm/m512/b16 {sae}" , "op": "RVM-FV: EVEX.512.NP.MAP5.W0 5D /r" , "vl": 0}, - {"inst": "vmovw W:r32[15:0]/m16, xmm[15:0]" , "op": "MR-T1S: EVEX.128.66.MAP5.WIG 7E /r" , "vl": 0}, - {"inst": "vmovw W:xmm[15:0] {kz}, r32[15:0]/m16" , "op": "RM-T1S: EVEX.128.66.MAP5.WIG 6E /r" , "vl": 0}, - {"inst": "vmulph W:xmm {kz}, ~xmm, ~xmm/m128/b16" , "op": "RVM-FV: EVEX.128.NP.MAP5.W0 59 /r" , "vl": 1}, - {"inst": "vmulph W:ymm {kz}, ~ymm, ~ymm/m256/b16" , "op": "RVM-FV: EVEX.256.NP.MAP5.W0 59 /r" , "vl": 1}, - {"inst": "vmulph W:zmm {kz}, ~zmm, ~zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.NP.MAP5.W0 59 /r" , "vl": 0}, - {"inst": "vrcpph W:xmm {kz}, xmm/m128/b16" , "op": "RM-FV: EVEX.128.66.MAP6.W0 4C /r" , "vl": 0}, - {"inst": "vrcpph W:ymm {kz}, ymm/m256/b16" , "op": "RM-FV: EVEX.256.66.MAP6.W0 4C /r" , "vl": 0}, - {"inst": "vrcpph W:zmm {kz}, zmm/m512/b16" , "op": "RM-FV: EVEX.512.66.MAP6.W0 4C /r" , "vl": 0}, - {"inst": "vreduceph W:xmm {kz}, xmm/m128/b16, ib/ub" , "op": "RM-FV: EVEX.128.NP.0F3A.W0 56 /r ib" , "vl": 1}, - {"inst": "vreduceph W:ymm {kz}, ymm/m256/b16, ib/ub" , "op": "RM-FV: EVEX.256.NP.0F3A.W0 56 /r ib" , "vl": 1}, - {"inst": "vreduceph W:zmm {kz}, zmm/m512/b16, ib/ub {sae}" , "op": "RM-FV: EVEX.512.NP.0F3A.W0 56 /r ib" , "vl": 0}, - {"inst": "vrndscaleph W:xmm {kz}, xmm/m128/b16, ib/ub" , "op": "RM-FV: EVEX.128.NP.0F3A.W0 08 /r ib" , "vl": 1}, - {"inst": "vrndscaleph W:ymm {kz}, ymm/m256/b16, ib/ub" , "op": "RM-FV: EVEX.256.NP.0F3A.W0 08 /r ib" , "vl": 1}, - {"inst": "vrndscaleph W:zmm {kz}, zmm/m512/b16, ib/ub {sae}" , "op": "RM-FV: EVEX.512.NP.0F3A.W0 08 /r ib" , "vl": 0}, - {"inst": "vrsqrtph W:xmm {kz}, xmm/m128/b16" , "op": "RM-FV: EVEX.128.66.MAP6.W0 4E /r" , "vl": 1}, - {"inst": "vrsqrtph W:ymm {kz}, ymm/m256/b16" , "op": "RM-FV: EVEX.256.66.MAP6.W0 4E /r" , "vl": 1}, - {"inst": "vrsqrtph W:zmm {kz}, zmm/m512/b16" , "op": "RM-FV: EVEX.512.66.MAP6.W0 4E /r" , "vl": 0}, - {"inst": "vscalefph W:xmm {kz}, xmm, xmm/m128/b16" , "op": "RVM-FV: EVEX.128.66.MAP6.W0 2C /r" , "vl": 1}, - {"inst": "vscalefph W:ymm {kz}, ymm, ymm/m256/b16" , "op": "RVM-FV: EVEX.256.66.MAP6.W0 2C /r" , "vl": 1}, - {"inst": "vscalefph W:zmm {kz}, zmm, zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.66.MAP6.W0 2C /r" , "vl": 0}, - {"inst": "vsqrtph W:xmm {kz}, xmm/m128/b16" , "op": "RM-FV: EVEX.128.NP.MAP5.W0 51 /r" , "vl": 1}, - {"inst": "vsqrtph W:ymm {kz}, ymm/m256/b16" , "op": "RM-FV: EVEX.256.NP.MAP5.W0 51 /r" , "vl": 1}, - {"inst": "vsqrtph W:zmm {kz}, zmm/m512/b16 {er}" , "op": "RM-FV: EVEX.512.NP.MAP5.W0 51 /r" , "vl": 0}, - {"inst": "vsubph W:xmm {kz}, ~xmm, ~xmm/m128/b16" , "op": "RVM-FV: EVEX.128.NP.MAP5.W0 5C /r" , "vl": 1}, - {"inst": "vsubph W:ymm {kz}, ~ymm, ~ymm/m256/b16" , "op": "RVM-FV: EVEX.256.NP.MAP5.W0 5C /r" , "vl": 1}, - {"inst": "vsubph W:zmm {kz}, ~zmm, ~zmm/m512/b16 {er}" , "op": "RVM-FV: EVEX.512.NP.MAP5.W0 5C /r" , "vl": 0} - ]}, - - {"category": "AMX", "ext": "AMX_TILE", "arch": "X64", "data": [ - {"inst": "ldtilecfg R:m512" , "op": "VEX.128.0F38.W0 49 /0"}, - {"inst": "sttilecfg W:m512" , "op": "VEX.128.66.0F38.W0 49 /0"}, - {"inst": "tileloadd W:tmm, tmem" , "op": "RM: VEX.128.F2.0F38.W0 4B /r"}, - {"inst": "tileloaddt1 W:tmm, tmem" , "op": "RM: VEX.128.66.0F38.W0 4B /r"}, - {"inst": "tilerelease" , "op": "VEX.128.0F38.W0 49 /0"}, - {"inst": "tilestored W:tmem, tmm" , "op": "MR: VEX.128.F3.0F38.W0 4B /r"}, - {"inst": "tilezero W:tmm" , "op": "R: VEX.128.F2.0F38.W0 49 /r"} - ]}, - - {"category": "AMX", "ext": "AMX_BF16", "arch": "X64", "data": [ - {"inst": "tdpbf16ps X:tmm, tmm, tmm" , "op": "RMV: VEX.128.F3.0F38.W0 5C /r"} - ]}, - - {"category": "AMX", "ext": "AMX_COMPLEX", "arch": "X64", "data": [ - {"inst": "tcmmimfp16ps X:tmm, tmm, tmm" , "op": "RMV: VEX.128.66.0F38.W0 6C /r"}, - {"inst": "tcmmrlfp16ps X:tmm, tmm, tmm" , "op": "RMV: VEX.128.NP.0F38.W0 6C /r"} - ]}, - - {"category": "AMX", "ext": "AMX_FP16", "arch": "X64", "data": [ - {"inst": "tdpfp16ps X:tmm, tmm, tmm" , "op": "RMV: VEX.128.F2.0F38.W0 5C /r"} - ]}, - - {"category": "AMX", "ext": "AMX_INT8", "arch": "X64", "data": [ - {"inst": "tdpbssd X:tmm, tmm, tmm" , "op": "RMV: VEX.128.F2.0F38.W0 5E /r"}, - {"inst": "tdpbsud X:tmm, tmm, tmm" , "op": "RMV: VEX.128.F3.0F38.W0 5E /r"}, - {"inst": "tdpbusd X:tmm, tmm, tmm" , "op": "RMV: VEX.128.66.0F38.W0 5E /r"}, - {"inst": "tdpbuud X:tmm, tmm, tmm" , "op": "RMV: VEX.128.0F38.W0 5E /r"} + + {"category": "GP GP_EXT", "ext": "RDTSCP", "instructions": [ + {"any": "rdtscp W:, W:, W:" , "op": "0F 01 F9"} + ]}, + + {"category": "GP GP_EXT", "ext": "RTM", "deprecated": true, "volatile": true, "instructions": [ + {"any": "xabort imm8" , "op": "C6 /7 ib"}, + {"any": "xbegin rel16" , "op": "66 C7 /7 cw"}, + {"any": "xbegin rel32" , "op": "C7 /7 cd"}, + {"any": "xend" , "op": "0F 01 D5"}, + {"any": "xtest" , "op": "0F 01 D6" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"} + ]}, + + {"category": "GP GP_EXT", "ext": "SERIALIZE", "volatile": true, "instructions": [ + {"any": "serialize" , "op": "0F 01 E8"} + ]}, + + {"category": "GP GP_EXT", "ext": "SSE", "volatile": true, "instructions": [ + {"any": "prefetchnta R:mem" , "op": "[M ] 0F 18 /0"}, + {"any": "prefetcht0 R:mem" , "op": "[M ] 0F 18 /1"}, + {"any": "prefetcht1 R:mem" , "op": "[M ] 0F 18 /2"}, + {"any": "prefetcht2 R:mem" , "op": "[M ] 0F 18 /3"}, + {"any": "sfence" , "op": "[OP] NP 0F AE F8"} + ]}, + + {"category": "GP GP_EXT", "ext": "SSE2", "volatile": true, "instructions": [ + {"any": "lfence" , "op": "[OP] NP 0F AE E8"}, + {"any": "mfence" , "op": "[OP] NP 0F AE F0"}, + {"any": "movnti W:my, ry" , "op": "[MR] NP 0F C3 /r"} + ]}, + + {"category": "GP GP_EXT CRYPTO_HASH", "ext": "SSE4_2", "instructions": [ + {"any": "crc32 X:r32, R:r8/m8" , "op": "[RM] F2 0F 38 F0 /r"}, + {"any": "crc32 X:r32, R:r16/m16" , "op": "[RM] 66 F2 0F 38 F1 /r"}, + {"any": "crc32 X:r32, R:r32/m32" , "op": "[RM] F2 0F 38 F1 /r"}, + {"any": "crc32 X:r64, R:r8/m8" , "op": "[RM] F2 REX.W 0F 38 F0 /r"}, + {"any": "crc32 X:r64, R:r64/m64" , "op": "[RM] F2 REX.W 0F 38 F1 /r"} + ]}, + + {"category": "GP GP_EXT", "ext": "TSE", "volatile": true, "instructions": [ + {"x64": "pbndkb W:, R:, W:" , "op": "NP 0F 01 C7" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"} + ]}, + + {"category": "GP GP_EXT", "ext": "TSXLDTRK", "volatile": true, "instructions": [ + {"any": "xresldtrk" , "op": "F2 0F 01 E9"}, + {"any": "xsusldtrk" , "op": "F2 0F 01 E8"} + ]}, + + {"category": "GP GP_EXT", "ext": "UINTR", "volatile": true, "instructions": [ + {"x64": "uiret" , "op": "F3 0F 01 EC"}, + {"x64": "clui" , "op": "F3 0F 01 EE"}, + {"x64": "stui" , "op": "F3 0F 01 EF"}, + {"x64": "testui" , "op": "F3 0F 01 ED" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}, + {"x64": "senduipi R:r64" , "op": "[R ] F3 0F C7 /6"} + ]}, + + {"category": "GP GP_EXT", "ext": "WAITPKG", "volatile": true, "instructions": [ + {"any": "tpause R:r32, , " , "op": "66 0F AE /6" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=W"}, + {"x86": "umonitor R:mem(ds:r32)" , "op": "F3 0F AE /6"}, + {"x64": "umonitor R:mem(ds:r64)" , "op": "F3 0F AE /6"}, + {"any": "umwait R:r32, , " , "op": "F2 0F AE /6" , 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+ {"any": "fsubr R:m32fp" , "op": "D8 /5" , "io": "C0=U C1=W C2=U C3=U"}, + {"any": "fsubr R:m64fp" , "op": "DC /5" , "io": "C0=U C1=W C2=U C3=U"}, + {"any": "fsubr st(0), st(i)" , "op": "D8 E8+i" , "io": "C0=U C1=W C2=U C3=U"}, + {"any": "fsubr st(i), st(0)" , "op": "DC E0+i" , "io": "C0=U C1=W C2=U C3=U"}, + {"any": "fsubrp" , "op": "DE E1" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"}, + {"any": "fsubrp st(i)" , "op": "DE E0+i" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"}, + {"any": "ftst" , "op": "D9 E4" , "io": "C0=W C1=0 C2=W C3=W"}, + {"any": "fucom" , "op": "DD E1" , "io": "C0=W C1=0 C2=W C3=W"}, + {"any": "fucom R:st(i)" , "op": "DD E0+i" , "io": "C0=W C1=0 C2=W C3=W"}, + {"any": "fucomi R:st(i)" , "op": "DB E8+i" , "io": "C1=0 ZF=W PF=W CF=W"}, + {"any": "fucomip R:st(i)" , "op": "DF E8+i" , "io": "C1=0 ZF=W PF=W CF=W", "fpuStack": "pop"}, + {"any": "fucomp" , "op": "DD E9" , "io": "C0=W C1=W C2=W C3=W", "fpuStack": "pop"}, + {"any": "fucomp R:st(i)" , "op": "DD E8+i" , "io": "C0=W C1=W C2=W C3=W", "fpuStack": "pop"}, + {"any": "fucompp" , "op": "DA E9" , "io": "C0=W C1=W C2=W C3=W", "fpuStack": "pop2x"}, + {"any": "fwait" , "op": "9B" , "io": "C0=U C1=U C2=U C3=U"}, + {"any": "fxam" , "op": "D9 E5" , "io": "C0=W C1=W C2=W C3=W"}, + {"any": "fxch" , "op": "D9 C9" , "io": "C0=U C1=0 C2=U C3=U"}, + {"any": "fxch st(i)" , "op": "D9 C8+i" , "io": "C0=U C1=0 C2=U C3=U"}, + {"any": "fxtract" , "op": "D9 F4" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "push"}, + {"any": "fyl2x" , "op": "D9 F1" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"}, + {"any": "fyl2xp1" , "op": "D9 F9" , "io": "C0=U C1=W C2=U C3=U", "fpuStack": "pop"} + ]}, + + {"category": "FPU", "ext": "FPU CMOV", "instructions": [ + {"any": "fcmovb st(i)" , "op": "DA C0+i" , "io": "C0=U C1=W C2=U C3=U CF=R" }, + {"any": "fcmovbe st(i)" , "op": "DA D0+i" , "io": "C0=U C1=W C2=U C3=U CF=R ZF=R"}, + {"any": "fcmove st(i)" , "op": "DA C8+i" , "io": "C0=U C1=W C2=U C3=U ZF=R" }, + {"any": "fcmovnb st(i)" , "op": "DB C0+i" , "io": "C0=U C1=W C2=U C3=U CF=R" }, + {"any": "fcmovnbe st(i)" , "op": "DB D0+i" , "io": "C0=U C1=W C2=U C3=U CF=R ZF=R"}, + {"any": "fcmovne st(i)" , "op": "DB C8+i" , "io": "C0=U C1=W C2=U C3=U ZF=R" }, + {"any": "fcmovnu st(i)" , "op": "DB D8+i" , "io": "C0=U C1=W C2=U C3=U PF=R" }, + {"any": "fcmovu st(i)" , "op": "DA D8+i" , "io": "C0=U C1=W C2=U C3=U PF=R" } + ]}, + + {"category": "FPU", "ext": "FPU SSE3", "instructions": [ + {"any": "fisttp W:m16int" , "op": "DF /1" , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop"}, + {"any": "fisttp W:m32int" , "op": "DB /1" , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop"}, + {"any": "fisttp W:m64int" , "op": "DD /1" , "io": "C0=U C1=0 C2=U C3=U", "fpuStack": "pop"} + ]}, + + {"category": "MMX STATE", "deprecated": true, "volatile": true, "instructions": [ + {"any": "emms" , "op": "[OP] 0F 77" , "ext": "MMX"}, + {"any": "femms" , "op": "[OP] 0F 0E" , "ext": "3DNOW"} + ]}, + + {"category": "MMX SIMD", "ext": "MMX", "deprecated": true, "instructions": [ + {"any": "movd W:mm[31:0], R:r32[31:0]/m32" , "op": "[RM] NP 0F 6E /r"}, + {"any": "movd W:r32[31:0]/m32, R:mm[31:0]" , "op": "[MR] NP 0F 7E /r"}, + {"any": "movq W:mm, mm/m64" , "op": "[RM] NP 0F 6F /r"}, + {"x64": "movq W:mm, r64/m64" , "op": "[RM] NP REX.W 0F 6E /r"}, + {"any": "movq W:mm/m64, mm" , "op": "[MR] NP 0F 7F /r"}, + {"x64": "movq W:r64/m64, mm" , "op": "[MR] NP REX.W 0F 7E /r"}, + {"any": "packssdw X:mm, mm/m64" , "op": "[RM] NP 0F 6B /r"}, + {"any": "packsswb X:mm, mm/m64" , "op": "[RM] NP 0F 63 /r"}, + {"any": "packuswb X:mm, mm/m64" , "op": "[RM] NP 0F 67 /r"}, + {"any": "paddb X:~mm, ~mm/m64" , "op": "[RM] NP 0F FC /r"}, + {"any": "paddd X:~mm, ~mm/m64" , "op": "[RM] NP 0F FE /r"}, + {"any": "paddsb X:~mm, ~mm/m64" , "op": "[RM] NP 0F EC /r"}, + {"any": "paddsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F ED /r"}, + {"any": "paddusb X:~mm, ~mm/m64" , "op": "[RM] NP 0F DC /r"}, + {"any": "paddusw X:~mm, ~mm/m64" , "op": "[RM] NP 0F DD /r"}, + {"any": "paddw X:~mm, ~mm/m64" , "op": "[RM] NP 0F FD /r"}, + {"any": "pand X:~mm, ~mm/m64" , "op": "[RM] NP 0F DB /r"}, + {"any": "pandn X:mm, mm/m64" , "op": "[RM] NP 0F DF /r"}, + {"any": "pcmpeqb X:~mm, ~mm/m64" , "op": "[RM] NP 0F 74 /r"}, + {"any": "pcmpeqd X:~mm, ~mm/m64" , "op": "[RM] NP 0F 76 /r"}, + {"any": "pcmpeqw X:~mm, ~mm/m64" , "op": "[RM] NP 0F 75 /r"}, + {"any": "pcmpgtb X:mm, mm/m64" , "op": "[RM] NP 0F 64 /r"}, + {"any": "pcmpgtd X:mm, mm/m64" , "op": "[RM] NP 0F 66 /r"}, + {"any": "pcmpgtw X:mm, mm/m64" , "op": "[RM] NP 0F 65 /r"}, + {"any": "pmaddwd X:~mm, ~mm/m64" , "op": "[RM] NP 0F F5 /r"}, + {"any": "pmulhw X:~mm, ~mm/m64" , "op": "[RM] NP 0F E5 /r"}, + {"any": "pmullw X:~mm, ~mm/m64" , "op": "[RM] NP 0F D5 /r"}, + {"any": "por X:~mm, ~mm/m64" , "op": "[RM] NP 0F EB /r"}, + {"any": "pslld X:mm, mm/m64" , "op": "[RM] NP 0F F2 /r"}, + {"any": "pslld X:mm, imm8" , "op": "[M ] NP 0F 72 /6 ib"}, + {"any": "psllq X:mm, mm/m64" , "op": "[RM] NP 0F F3 /r"}, + {"any": "psllq X:mm, imm8" , "op": "[M ] NP 0F 73 /6 ib"}, + {"any": "psllw X:mm, mm/m64" , "op": "[RM] NP 0F F1 /r"}, + {"any": "psllw X:mm, imm8" , "op": "[M ] NP 0F 71 /6 ib"}, + {"any": "psrad X:mm, mm/m64" , "op": "[RM] NP 0F E2 /r"}, + {"any": "psrad X:mm, imm8" , "op": "[M ] NP 0F 72 /4 ib"}, + {"any": "psraw X:mm, mm/m64" , "op": "[RM] NP 0F E1 /r"}, + {"any": "psraw X:mm, imm8" , "op": "[M ] NP 0F 71 /4 ib"}, + {"any": "psrld X:mm, mm/m64" , "op": "[RM] NP 0F D2 /r"}, + {"any": "psrld X:mm, imm8" , "op": "[M ] NP 0F 72 /2 ib"}, + {"any": "psrlq X:mm, mm/m64" , "op": "[RM] NP 0F D3 /r"}, + {"any": "psrlq X:mm, imm8" , "op": "[M ] NP 0F 73 /2 ib"}, + {"any": "psrlw X:mm, mm/m64" , "op": "[RM] NP 0F D1 /r"}, + {"any": "psrlw X:mm, imm8" , "op": "[M ] NP 0F 71 /2 ib"}, + {"any": "psubb X:mm, mm/m64" , "op": "[RM] NP 0F F8 /r"}, + {"any": "psubd X:mm, mm/m64" , "op": "[RM] NP 0F FA /r"}, + {"any": "psubsb X:mm, mm/m64" , "op": "[RM] NP 0F E8 /r"}, + {"any": "psubsw X:mm, mm/m64" , "op": "[RM] NP 0F E9 /r"}, + {"any": "psubusb X:mm, mm/m64" , "op": "[RM] NP 0F D8 /r"}, + {"any": "psubusw X:mm, mm/m64" , "op": "[RM] NP 0F D9 /r"}, + {"any": "psubw X:mm, mm/m64" , "op": "[RM] NP 0F F9 /r"}, + {"any": "punpckhbw X:mm, mm/m64" , "op": "[RM] NP 0F 68 /r"}, + {"any": "punpckhdq X:mm, mm/m64" , "op": "[RM] NP 0F 6A /r"}, + {"any": "punpckhwd X:mm, mm/m64" , "op": "[RM] NP 0F 69 /r"}, + {"any": "punpcklbw X:mm, mm/m32" , "op": "[RM] NP 0F 60 /r"}, + {"any": "punpckldq X:mm, mm/m32" , "op": "[RM] NP 0F 62 /r"}, + {"any": "punpcklwd X:mm, mm/m32" , "op": "[RM] NP 0F 61 /r"}, + {"any": "pxor X:~mm, ~mm/m64" , "op": "[RM] NP 0F EF /r"} + ]}, + + {"category": "MMX SIMD", "ext": "MMX2", "deprecated": true, "instructions": [ + {"any": "maskmovq R:mm, mm, X:" , "op": "[RM] NP 0F F7 /r"}, + {"any": "movntq W:m64, mm" , "op": "[MR] NP 0F E7 /r"}, + {"any": "pavgb X:~mm, ~mm/m64" , "op": "[RM] NP 0F E0 /r"}, + {"any": "pavgw X:~mm, ~mm/m64" , "op": "[RM] NP 0F E3 /r"}, + {"any": "pextrw W:r32[15:0], mm, imm8" , "op": "[RM] NP 0F C5 /r ib"}, + {"any": "pinsrw X:mm, r32[15:0]/m16, imm8" , "op": "[RM] NP 0F C4 /r ib"}, + {"any": "pmaxsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F EE /r"}, + {"any": "pmaxub X:~mm, ~mm/m64" , "op": "[RM] NP 0F DE /r"}, + {"any": "pminsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F EA /r"}, + {"any": "pminub X:~mm, ~mm/m64" , "op": "[RM] NP 0F DA /r"}, + {"any": "pmovmskb W:r32[7:0], mm" , "op": "[RM] NP 0F D7 /r"}, + {"any": "pmulhuw X:~mm, ~mm/m64" , "op": "[RM] NP 0F E4 /r"}, + {"any": "psadbw X:~mm, ~mm/m64" , "op": "[RM] NP 0F F6 /r"}, + {"any": "pshufw W:mm, mm/m64, imm8" , "op": "[RM] NP 0F 70 /r ib"} + ]}, + + {"category": "MMX SIMD", "ext": "3DNOW", "deprecated": true, "instructions": [ + {"any": "pavgusb X:mm, mm/m64" , "op": "[RM] 0F 0F /r BF"}, + {"any": "pf2id W:mm, mm/m64" , "op": "[RM] 0F 0F /r 1D"}, + {"any": "pfacc X:mm, mm/m64" , "op": "[RM] 0F 0F /r AE"}, + {"any": "pfadd X:mm, mm/m64" , "op": "[RM] 0F 0F /r 9E"}, + {"any": "pfcmpeq X:mm, mm/m64" , "op": "[RM] 0F 0F /r B0"}, + {"any": "pfcmpge X:mm, mm/m64" , "op": "[RM] 0F 0F /r 90"}, + {"any": "pfcmpgt X:mm, mm/m64" , "op": "[RM] 0F 0F /r A0"}, + {"any": "pfmax X:mm, mm/m64" , "op": "[RM] 0F 0F /r A4"}, + {"any": "pfmin X:mm, mm/m64" , "op": "[RM] 0F 0F /r 94"}, + {"any": "pfmul X:mm, mm/m64" , "op": "[RM] 0F 0F /r B4"}, + {"any": "pfrcp W:mm, mm/m64" , "op": "[RM] 0F 0F /r 96"}, + {"any": "pfrcpit1 X:mm, mm/m64" , "op": "[RM] 0F 0F /r A6"}, + {"any": "pfrcpit2 X:mm, mm/m64" , "op": "[RM] 0F 0F /r B6"}, + {"any": "pfrsqit1 W:mm, mm/m64" , "op": "[RM] 0F 0F /r A7"}, + {"any": "pfrsqrt W:mm, mm/m64" , "op": "[RM] 0F 0F /r 97"}, + {"any": "pfsub X:mm, mm/m64" , "op": "[RM] 0F 0F /r 9A"}, + {"any": "pfsubr X:mm, mm/m64" , "op": "[RM] 0F 0F /r AA"}, + {"any": "pi2fd W:mm, mm/m64" , "op": "[RM] 0F 0F /r 0D"}, + {"any": "pmulhrw X:mm, mm/m64" , "op": "[RM] 0F 0F /r B7"} + ]}, + + {"category": "MMX SIMD", "ext": "3DNOW2", "deprecated": true, "instructions": [ + {"any": "pf2iw W:mm, mm/m64" , "op": "[RM] 0F 0F /r 1C"}, + {"any": "pfnacc X:mm, mm/m64" , "op": "[RM] 0F 0F /r 8A"}, + {"any": "pfpnacc X:mm, mm/m64" , "op": "[RM] 0F 0F /r 8E"}, + {"any": "pi2fw W:mm, mm/m64" , "op": "[RM] 0F 0F /r 0C"}, + {"any": "pswapd W:mm, mm/m64" , "op": "[RM] 0F 0F /r BB"} + ]}, + + {"category": "MMX SIMD", "ext": "GEODE", "deprecated": true, "instructions": [ + {"any": "pfrcpv X:mm, mm/m64" , "op": "[RM] 0F 0F /r 86"}, + {"any": "pfrsqrtv X:mm, mm/m64" , "op": "[RM] 0F 0F /r 87"} + ]}, + + {"category": "MMX SIMD", "ext": "SSE", "deprecated": true, "instructions": [ + {"any": "cvtpi2ps w:xmm[63:0], mm/m64" , "op": "[RM] NP 0F 2A /r"}, + {"any": "cvtps2pi W:mm, xmm[63:0]/m64" , "op": "[RM] NP 0F 2D /r"}, + {"any": "cvttps2pi W:mm, xmm[63:0]/m64" , "op": "[RM] NP 0F 2C /r"} + ]}, + + {"category": "MMX SIMD", "ext": "SSE2", "deprecated": true, "instructions": [ + {"any": "cvtpd2pi W:mm, xmm/m128" , "op": "[RM] 66 0F 2D /r"}, + {"any": "cvtpi2pd W:xmm, R:mm[63:0]/m64" , "op": "[RM] 66 0F 2A /r"}, + {"any": "cvttpd2pi W:mm, xmm/m128" , "op": "[RM] 66 0F 2C /r"}, + {"any": "movdq2q W:mm, xmm[63:0]" , "op": "[RM] F2 0F D6 /r"}, + {"any": "movq2dq W:xmm[63:0], mm" , "op": "[RM] F3 0F D6 /r"}, + {"any": "paddq X:~mm, ~mm/m64" , "op": "[RM] NP 0F D4 /r"}, + {"any": "pmuludq X:~mm, ~mm/m64" , "op": "[RM] NP 0F F4 /r"}, + {"any": "psubq X:mm, mm/m64" , "op": "[RM] NP 0F FB /r"} + ]}, + + {"category": "MMX SIMD", "ext": "SSSE3", "deprecated": true, "instructions": [ + {"any": "pabsb W:mm, mm/m64" , "op": "[RM] NP 0F 38 1C /r"}, + {"any": "pabsd W:mm, mm/m64" , "op": "[RM] NP 0F 38 1E /r"}, + {"any": "pabsw W:mm, mm/m64" , "op": "[RM] NP 0F 38 1D /r"}, + {"any": "palignr X:mm, mm/m64, imm8" , "op": "[RM] NP 0F 3A 0F /r ib"}, + {"any": "phaddd X:~mm, ~mm/m64" , "op": "[RM] NP 0F 38 02 /r"}, + {"any": "phaddsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F 38 03 /r"}, + {"any": "phaddw X:~mm, ~mm/m64" , "op": "[RM] NP 0F 38 01 /r"}, + {"any": "phsubd X:mm, mm/m64" , "op": "[RM] NP 0F 38 06 /r"}, + {"any": "phsubsw X:mm, mm/m64" , "op": "[RM] NP 0F 38 07 /r"}, + {"any": "phsubw X:mm, mm/m64" , "op": "[RM] NP 0F 38 05 /r"}, + {"any": "pmaddubsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F 38 04 /r"}, + {"any": "pmulhrsw X:~mm, ~mm/m64" , "op": "[RM] NP 0F 38 0B /r"}, + {"any": "pshufb X:mm, mm/m64" , "op": "[RM] NP 0F 38 00 /r"}, + {"any": "psignb X:mm, mm/m64" , "op": "[RM] NP 0F 38 08 /r"}, + {"any": "psignd X:mm, mm/m64" , "op": "[RM] NP 0F 38 0A /r"}, + {"any": "psignw X:mm, mm/m64" , "op": "[RM] NP 0F 38 09 /r"} + ]}, + + {"category": "SSE STATE", "ext": "SSE", "instructions": [ + {"any": "ldmxcsr R:m32" , "op": "[M ] NP 0F AE /2", "io": "MXCSR=W"}, + {"any": "stmxcsr W:m32" , "op": "[M ] NP 0F AE /3", "io": "MXCSR=R"} + ]}, + + {"category": "SSE SIMD", "ext": "SSE", "instructions": [ + {"any": "addps X:~xmm, ~xmm/m128" , "op": "[RM] NP 0F 58 /r"}, + {"any": "addss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 58 /r"}, + {"any": "andnps X:xmm, xmm/m128" , "op": "[RM] NP 0F 55 /r"}, + {"any": "andps X:~xmm, ~xmm/m128" , "op": "[RM] NP 0F 54 /r"}, + {"any": "cmpps X:xmm, xmm/m128, imm8" , "op": "[RM] NP 0F C2 /r ib"}, + {"any": "cmpss x:xmm[31:0], xmm[31:0]/m32, imm8" , "op": "[RM] F3 0F C2 /r ib"}, + {"any": "comiss R:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] NP 0F 2F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "cvtsi2ss w:xmm[31:0], ry/my" , "op": "[RM] F3 0F 2A /r"}, + {"any": "cvtss2si W:ry, xmm[31:0]/m32" , "op": "[RM] F3 0F 2D /r"}, + {"any": "cvttss2si W:ry, xmm[31:0]/m32" , "op": "[RM] F3 0F 2C /r"}, + {"any": "divps X:xmm, xmm/m128" , "op": "[RM] NP 0F 5E /r"}, + {"any": "divss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 5E /r"}, + {"any": "maxps X:xmm, xmm/m128" , "op": "[RM] NP 0F 5F /r"}, + {"any": "maxss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 5F /r"}, + {"any": "minps X:xmm, xmm/m128" , "op": "[RM] NP 0F 5D /r"}, + {"any": "minss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 5D /r"}, + {"any": "movaps W:xmm, xmm/m128" , "op": "[RM] NP 0F 28 /r"}, + {"any": "movaps W:xmm/m128, xmm" , "op": "[MR] NP 0F 29 /r"}, + {"any": "movhlps w:xmm[63:0], xmm[127:64]" , "op": "[RM] NP 0F 12 /r"}, + {"any": "movhps W:m64, xmm[127:64]" , "op": "[MR] NP 0F 17 /r"}, + {"any": "movhps w:xmm[127:64], m64" , "op": "[RM] NP 0F 16 /r"}, + {"any": "movlhps w:xmm[127:64], xmm[63:0]" , "op": "[RM] NP 0F 16 /r"}, + {"any": "movlps W:m64, xmm[63:0]" , "op": "[MR] NP 0F 13 /r"}, + {"any": "movlps w:xmm[63:0], m64" , "op": "[RM] NP 0F 12 /r"}, + {"any": "movmskps W:r32[3:0], xmm" , "op": "[RM] NP 0F 50 /r"}, + {"any": "movntps W:m128, xmm" , "op": "[MR] NP 0F 2B /r"}, + {"any": "movss w:xmm[31:0], xmm[31:0]" , "op": "[RM] F3 0F 10 /r"}, + {"any": "movss W:xmm[31:0], m32" , "op": "[RM] F3 0F 10 /r"}, + {"any": "movss W:m32, xmm[31:0]" , "op": "[MR] F3 0F 11 /r"}, + {"any": "movups W:xmm, xmm/m128" , "op": "[RM] NP 0F 10 /r"}, + {"any": "movups W:xmm/m128, xmm" , "op": "[MR] NP 0F 11 /r"}, + {"any": "mulps X:~xmm, ~xmm/m128" , "op": "[RM] NP 0F 59 /r"}, + {"any": "mulss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 59 /r"}, + {"any": "orps X:~xmm, ~xmm/m128" , "op": "[RM] NP 0F 56 /r"}, + {"any": "rcpps W:xmm, xmm/m128" , "op": "[RM] NP 0F 53 /r"}, + {"any": "rcpss w:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 53 /r"}, + {"any": "rsqrtps W:xmm, xmm/m128" , "op": "[RM] NP 0F 52 /r"}, + {"any": "rsqrtss w:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 52 /r"}, + {"any": "shufps X:xmm, xmm/m128, imm8" , "op": "[RM] NP 0F C6 /r ib"}, + {"any": "sqrtps W:xmm, xmm/m128" , "op": "[RM] NP 0F 51 /r"}, + {"any": "sqrtss w:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 51 /r"}, + {"any": "subps X:xmm, xmm/m128" , "op": "[RM] NP 0F 5C /r"}, + {"any": "subss x:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 5C /r"}, + {"any": "ucomiss R:xmm[31:0], xmm[31:0]/m32" , "op": "[RM] NP 0F 2E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "unpckhps X:xmm, xmm/m128" , "op": "[RM] NP 0F 15 /r"}, + {"any": "unpcklps X:xmm, xmm/m128" , "op": "[RM] NP 0F 14 /r"}, + {"any": "xorps X:~xmm, ~xmm/m128" , "op": "[RM] NP 0F 57 /r"} + ]}, + + {"category": "SSE SIMD", "ext": "SSE2", "instructions": [ + {"any": "addpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 58 /r"}, + {"any": "addsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 58 /r"}, + {"any": "andnpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 55 /r"}, + {"any": "andpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 54 /r"}, + {"any": "cmppd X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F C2 /r ib"}, + {"any": "cmpsd x:xmm[63:0], xmm[63:0]/m64, imm8" , "op": "[RM] F2 0F C2 /r ib"}, + {"any": "comisd R:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] 66 0F 2F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "cvtdq2pd W:xmm, xmm[63:0]/m64" , "op": "[RM] F3 0F E6 /r"}, + {"any": "cvtdq2ps W:xmm, xmm/m128" , "op": "[RM] NP 0F 5B /r"}, + {"any": "cvtpd2dq W:xmm[63:0], xmm/m128" , "op": "[RM] F2 0F E6 /r"}, + {"any": "cvtpd2ps W:xmm[63:0], xmm/m128" , "op": "[RM] 66 0F 5A /r"}, + {"any": "cvtps2dq W:xmm, xmm/m128" , "op": "[RM] 66 0F 5B /r"}, + {"any": "cvtps2pd W:xmm, xmm[63:0]/m64" , "op": "[RM] NP 0F 5A /r"}, + {"any": "cvtsd2si W:ry, xmm[63:0]/m64" , "op": "[RM] F2 0F 2D /r"}, + {"any": "cvtsd2ss w:xmm[31:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 5A /r"}, + {"any": "cvtsi2sd w:xmm[63:0], ry/my" , "op": "[RM] F2 0F 2A /r"}, + {"any": "cvtss2sd w:xmm[63:0], xmm[31:0]/m32" , "op": "[RM] F3 0F 5A /r"}, + {"any": "cvttpd2dq W:xmm[63:0], xmm/m128" , "op": "[RM] 66 0F E6 /r"}, + {"any": "cvttps2dq W:xmm, xmm/m128" , "op": "[RM] F3 0F 5B /r"}, + {"any": "cvttsd2si W:ry, xmm[63:0]/m64" , "op": "[RM] F2 0F 2C /r"}, + {"any": "divpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 5E /r"}, + {"any": "divsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 5E /r"}, + {"any": "maskmovdqu R:xmm, xmm, X:" , "op": "[RM] 66 0F F7 /r"}, + {"any": "maxpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 5F /r"}, + {"any": "maxsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 5F /r"}, + {"any": "minpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 5D /r"}, + {"any": "minsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 5D /r"}, + {"any": "movapd W:xmm, xmm/m128" , "op": "[RM] 66 0F 28 /r"}, + {"any": "movapd W:xmm/m128, xmm" , "op": "[MR] 66 0F 29 /r"}, + {"any": "movd W:r32[31:0]/m32, xmm[31:0]" , "op": "[MR] 66 0F 7E /r"}, + {"any": "movd W:xmm[31:0], R:r32[31:0]/m32" , "op": "[RM] 66 0F 6E /r"}, + {"any": "movdqa W:xmm, xmm/m128" , "op": "[RM] 66 0F 6F /r"}, + {"any": "movdqa W:xmm/m128, xmm" , "op": "[MR] 66 0F 7F /r"}, + {"any": "movdqu W:xmm, xmm/m128" , "op": "[RM] F3 0F 6F /r"}, + {"any": "movdqu W:xmm/m128, xmm" , "op": "[MR] F3 0F 7F /r"}, + {"any": "movhpd W:m64, xmm[127:64]" , "op": "[MR] 66 0F 17 /r"}, + {"any": "movhpd w:xmm[127:64], m64" , "op": "[RM] 66 0F 16 /r"}, + {"any": "movlpd W:m64, xmm[63:0]" , "op": "[MR] 66 0F 13 /r"}, + {"any": "movlpd w:xmm[63:0], m64" , "op": "[RM] 66 0F 12 /r"}, + {"any": "movmskpd W:r32[1:0], xmm" , "op": "[RM] 66 0F 50 /r"}, + {"any": "movntdq W:m128, xmm" , "op": "[MR] 66 0F E7 /r"}, + {"any": "movntpd W:m128, xmm" , "op": "[MR] 66 0F 2B /r"}, + {"x64": "movq W:r64/m64, xmm[63:0]" , "op": "[MR] REX.W 66 0F 7E /r"}, + {"x64": "movq W:xmm[63:0], r64[63:0]/m64" , "op": "[RM] REX.W 66 0F 6E /r"}, + {"any": "movq W:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F3 0F 7E /r"}, + {"any": "movq W:xmm[63:0]/m64, xmm[63:0]" , "op": "[MR] 66 0F D6 /r"}, + {"any": "movsd w:xmm[63:0], xmm[63:0]" , "op": "[RM] F2 0F 10 /r"}, + {"any": "movsd W:xmm[63:0], m64" , "op": "[RM] F2 0F 10 /r"}, + {"any": "movsd W:m64, xmm[63:0]" , "op": "[MR] F2 0F 11 /r"}, + {"any": "movupd W:xmm, xmm/m128" , "op": "[RM] 66 0F 10 /r"}, + {"any": "movupd W:xmm/m128, xmm" , "op": "[MR] 66 0F 11 /r"}, + {"any": "mulpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 59 /r"}, + {"any": "mulsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 59 /r"}, + {"any": "orpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 56 /r"}, + {"any": "packssdw X:xmm, xmm/m128" , "op": "[RM] 66 0F 6B /r"}, + {"any": "packsswb X:xmm, xmm/m128" , "op": "[RM] 66 0F 63 /r"}, + {"any": "packuswb X:xmm, xmm/m128" , "op": "[RM] 66 0F 67 /r"}, + {"any": "paddb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F FC /r"}, + {"any": "paddd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F FE /r"}, + {"any": "paddq X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F D4 /r"}, + {"any": "paddsb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F EC /r"}, + {"any": "paddsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F ED /r"}, + {"any": "paddusb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F DC /r"}, + {"any": "paddusw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F DD /r"}, + {"any": "paddw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F FD /r"}, + {"any": "pand X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F DB /r"}, + {"any": "pandn X:xmm, xmm/m128" , "op": "[RM] 66 0F DF /r"}, + {"any": "pavgb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F E0 /r"}, + {"any": "pavgw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F E3 /r"}, + {"any": "pcmpeqb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 74 /r"}, + {"any": "pcmpeqd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 76 /r"}, + {"any": "pcmpeqw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 75 /r"}, + {"any": "pcmpgtb X:xmm, xmm/m128" , "op": "[RM] 66 0F 64 /r"}, + {"any": "pcmpgtd X:xmm, xmm/m128" , "op": "[RM] 66 0F 66 /r"}, + {"any": "pcmpgtw X:xmm, xmm/m128" , "op": "[RM] 66 0F 65 /r"}, + {"any": "pextrw W:r32[15:0], xmm, imm8" , "op": "[RM] 66 0F C5 /r ib"}, + {"any": "pinsrw X:xmm, r32[15:0]/m16, imm8" , "op": "[RM] 66 0F C4 /r ib"}, + {"any": "pmaddwd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F F5 /r"}, + {"any": "pmaxsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F EE /r"}, + {"any": "pmaxub X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F DE /r"}, + {"any": "pminsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F EA /r"}, + {"any": "pminub X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F DA /r"}, + {"any": "pmovmskb W:r32[15:0], xmm" , "op": "[RM] 66 0F D7 /r"}, + {"any": "pmulhuw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F E4 /r"}, + {"any": "pmulhw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F E5 /r"}, + {"any": "pmullw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F D5 /r"}, + {"any": "pmuludq X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F F4 /r"}, + {"any": "por X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F EB /r"}, + {"any": "psadbw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F F6 /r"}, + {"any": "pshufd W:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 70 /r ib"}, + {"any": "pshufhw W:xmm, xmm/m128, imm8" , "op": "[RM] F3 0F 70 /r ib"}, + {"any": "pshuflw W:xmm, xmm/m128, imm8" , "op": "[RM] F2 0F 70 /r ib"}, + {"any": "pslld X:xmm, xmm/m128" , "op": "[RM] 66 0F F2 /r"}, + {"any": "pslld X:xmm, imm8" , "op": "[M ] 66 0F 72 /6 ib"}, + {"any": "pslldq X:xmm, imm8" , "op": "[M ] 66 0F 73 /7 ib"}, + {"any": "psllq X:xmm, xmm/m128" , "op": "[RM] 66 0F F3 /r"}, + {"any": "psllq X:xmm, imm8" , "op": "[M ] 66 0F 73 /6 ib"}, + {"any": "psllw X:xmm, xmm/m128" , "op": "[RM] 66 0F F1 /r"}, + {"any": "psllw X:xmm, imm8" , "op": "[M ] 66 0F 71 /6 ib"}, + {"any": "psrad X:xmm, xmm/m128" , "op": "[RM] 66 0F E2 /r"}, + {"any": "psrad X:xmm, imm8" , "op": "[M ] 66 0F 72 /4 ib"}, + {"any": "psraw X:xmm, xmm/m128" , "op": "[RM] 66 0F E1 /r"}, + {"any": "psraw X:xmm, imm8" , "op": "[M ] 66 0F 71 /4 ib"}, + {"any": "psrld X:xmm, xmm/m128" , "op": "[RM] 66 0F D2 /r"}, + {"any": "psrld X:xmm, imm8" , "op": "[M ] 66 0F 72 /2 ib"}, + {"any": "psrldq X:xmm, imm8" , "op": "[M ] 66 0F 73 /3 ib"}, + {"any": "psrlq X:xmm, xmm/m128" , "op": "[RM] 66 0F D3 /r"}, + {"any": "psrlq X:xmm, imm8" , "op": "[M ] 66 0F 73 /2 ib"}, + {"any": "psrlw X:xmm, imm8" , "op": "[M ] 66 0F 71 /2 ib"}, + {"any": "psrlw X:xmm, xmm/m128" , "op": "[RM] 66 0F D1 /r"}, + {"any": "psubb X:xmm, xmm/m128" , "op": "[RM] 66 0F F8 /r"}, + {"any": "psubd X:xmm, xmm/m128" , "op": "[RM] 66 0F FA /r"}, + {"any": "psubq X:xmm, xmm/m128" , "op": "[RM] 66 0F FB /r"}, + {"any": "psubsb X:xmm, xmm/m128" , "op": "[RM] 66 0F E8 /r"}, + {"any": "psubsw X:xmm, xmm/m128" , "op": "[RM] 66 0F E9 /r"}, + {"any": "psubusb X:xmm, xmm/m128" , "op": "[RM] 66 0F D8 /r"}, + {"any": "psubusw X:xmm, xmm/m128" , "op": "[RM] 66 0F D9 /r"}, + {"any": "psubw X:xmm, xmm/m128" , "op": "[RM] 66 0F F9 /r"}, + {"any": "punpckhbw X:xmm, xmm/m128" , "op": "[RM] 66 0F 68 /r"}, + {"any": "punpckhdq X:xmm, xmm/m128" , "op": "[RM] 66 0F 6A /r"}, + {"any": "punpckhqdq X:xmm, xmm/m128" , "op": "[RM] 66 0F 6D /r"}, + {"any": "punpckhwd X:xmm, xmm/m128" , "op": "[RM] 66 0F 69 /r"}, + {"any": "punpcklbw X:xmm, xmm/m128" , "op": "[RM] 66 0F 60 /r"}, + {"any": "punpckldq X:xmm, xmm/m128" , "op": "[RM] 66 0F 62 /r"}, + {"any": "punpcklqdq X:xmm, xmm/m128" , "op": "[RM] 66 0F 6C /r"}, + {"any": "punpcklwd X:xmm, xmm/m128" , "op": "[RM] 66 0F 61 /r"}, + {"any": "pxor X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F EF /r"}, + {"any": "shufpd X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F C6 /r ib"}, + {"any": "sqrtpd W:xmm, xmm/m128" , "op": "[RM] 66 0F 51 /r"}, + {"any": "sqrtsd w:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 51 /r"}, + {"any": "subpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 5C /r"}, + {"any": "subsd x:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] F2 0F 5C /r"}, + {"any": "ucomisd R:xmm[63:0], xmm[63:0]/m64" , "op": "[RM] 66 0F 2E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "unpckhpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 15 /r"}, + {"any": "unpcklpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 14 /r"}, + {"any": "xorpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 57 /r"} + ]}, + + {"category": "SSE SIMD", "ext": "SSE3", "instructions": [ + {"any": "addsubpd X:xmm, xmm/m128" , "op": "[RM] 66 0F D0 /r"}, + {"any": "addsubps X:xmm, xmm/m128" , "op": "[RM] F2 0F D0 /r"}, + {"any": "haddpd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 7C /r"}, + {"any": "haddps X:~xmm, ~xmm/m128" , "op": "[RM] F2 0F 7C /r"}, + {"any": "hsubpd X:xmm, xmm/m128" , "op": "[RM] 66 0F 7D /r"}, + {"any": "hsubps X:xmm, xmm/m128" , "op": "[RM] F2 0F 7D /r"}, + {"any": "lddqu W:xmm, m128" , "op": "[RM] F2 0F F0 /r"}, + {"any": "movddup W:xmm, xmm[63:0]/m64" , "op": "[RM] F2 0F 12 /r"}, + {"any": "movshdup W:xmm, xmm/m128" , "op": "[RM] F3 0F 16 /r"}, + {"any": "movsldup W:xmm, xmm/m128" , "op": "[RM] F3 0F 12 /r"} + ]}, + + {"category": "SSE SIMD", "ext": "SSSE3", "instructions": [ + {"any": "pabsb W:xmm, xmm/m128" , "op": "[RM] 66 0F 38 1C /r"}, + {"any": "pabsd W:xmm, xmm/m128" , "op": "[RM] 66 0F 38 1E /r"}, + {"any": "pabsw W:xmm, xmm/m128" , "op": "[RM] 66 0F 38 1D /r"}, + {"any": "palignr X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 0F /r ib"}, + {"any": "phaddd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 02 /r"}, + {"any": "phaddsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 03 /r"}, + {"any": "phaddw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 01 /r"}, + {"any": "phsubd X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 06 /r"}, + {"any": "phsubsw X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 07 /r"}, + {"any": "phsubw X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 05 /r"}, + {"any": "pmaddubsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 04 /r"}, + {"any": "pmulhrsw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 0B /r"}, + {"any": "pshufb X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 00 /r"}, + {"any": "psignb X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 08 /r"}, + {"any": "psignd X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 0A /r"}, + {"any": "psignw X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 09 /r"} + ]}, + + {"category": "SSE SIMD", "ext": "SSE4_1", "instructions": [ + {"any": "blendpd X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 0D /r ib"}, + {"any": "blendps X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 0C /r ib"}, + {"any": "blendvpd X:xmm, xmm/m128, " , "op": "[RM] 66 0F 38 15 /r"}, + {"any": "blendvps X:xmm, xmm/m128, " , "op": "[RM] 66 0F 38 14 /r"}, + {"any": "dppd X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 41 /r ib"}, + {"any": "dpps X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 40 /r ib"}, + {"any": "extractps W:r32/m32, xmm, imm8" , "op": "[MR] 66 0F 3A 17 /r ib"}, + {"any": "insertps X:xmm, xmm[31:0]/m32, imm8" , "op": "[RM] 66 0F 3A 21 /r ib"}, + {"any": "movntdqa W:xmm, m128" , "op": "[RM] 66 0F 38 2A /r"}, + {"any": "mpsadbw X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 42 /r ib"}, + {"any": "packusdw X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 2B /r"}, + {"any": "pblendvb X:xmm, xmm/m128, " , "op": "[RM] 66 0F 38 10 /r"}, + {"any": "pblendw X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 0E /r ib"}, + {"any": "pcmpeqq X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 29 /r"}, + {"any": "pextrb W:r32[7:0]/m8, xmm, imm8" , "op": "[MR] 66 0F 3A 14 /r ib"}, + {"any": "pextrd W:r32[31:0]/m32, xmm, imm8" , "op": "[MR] 66 0F 3A 16 /r ib"}, + {"any": "pextrq W:r64/m64, xmm, imm8" , "op": "[MR] REX.W 66 0F 3A 16 /r ib"}, + {"any": "pextrw W:r32[15:0]/m16, xmm, imm8" , "op": "[MR] 66 0F 3A 15 /r ib"}, + {"any": "phminposuw W:xmm[18:0], xmm/m128" , "op": "[RM] 66 0F 38 41 /r"}, + {"any": "pinsrb X:xmm, r32[7:0]/m8, imm8" , "op": "[RM] 66 0F 3A 20 /r ib"}, + {"any": "pinsrd X:xmm, r32[31:0]/m32, imm8" , "op": "[RM] 66 0F 3A 22 /r ib"}, + {"any": "pinsrq X:xmm, r64/m64, imm8" , "op": "[RM] REX.W 66 0F 3A 22 /r ib"}, + {"any": "pmaxsb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3C /r"}, + {"any": "pmaxsd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3D /r"}, + {"any": "pmaxud X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3F /r"}, + {"any": "pmaxuw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3E /r"}, + {"any": "pminsb X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 38 /r"}, + {"any": "pminsd X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 39 /r"}, + {"any": "pminud X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3B /r"}, + {"any": "pminuw X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 3A /r"}, + {"any": "pmovsxbd W:xmm, xmm[31:0]/m32" , "op": "[RM] 66 0F 38 21 /r"}, + {"any": "pmovsxbq W:xmm, xmm[15:0]/m16" , "op": "[RM] 66 0F 38 22 /r"}, + {"any": "pmovsxbw W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 20 /r"}, + {"any": "pmovsxdq W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 25 /r"}, + {"any": "pmovsxwd W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 23 /r"}, + {"any": "pmovsxwq W:xmm, xmm[31:0]/m32" , "op": "[RM] 66 0F 38 24 /r"}, + {"any": "pmovzxbd W:xmm, xmm[31:0]/m32" , "op": "[RM] 66 0F 38 31 /r"}, + {"any": "pmovzxbq W:xmm, xmm[15:0]/m16" , "op": "[RM] 66 0F 38 32 /r"}, + {"any": "pmovzxbw W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 30 /r"}, + {"any": "pmovzxdq W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 35 /r"}, + {"any": "pmovzxwd W:xmm, xmm[63:0]/m64" , "op": "[RM] 66 0F 38 33 /r"}, + {"any": "pmovzxwq W:xmm, xmm[31:0]/m32" , "op": "[RM] 66 0F 38 34 /r"}, + {"any": "pmuldq X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 28 /r"}, + {"any": "pmulld X:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 40 /r"}, + {"any": "ptest R:~xmm, ~xmm/m128" , "op": "[RM] 66 0F 38 17 /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, + {"any": "roundpd W:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 09 /r ib"}, + {"any": "roundps W:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 08 /r ib"}, + {"any": "roundsd w:xmm[63:0], xmm[63:0]/m64, imm8" , "op": "[RM] 66 0F 3A 0B /r ib"}, + {"any": "roundss w:xmm[31:0], xmm[31:0]/m32, imm8" , "op": "[RM] 66 0F 3A 0A /r ib"} + ]}, + + {"category": "SSE SIMD", "ext": "SSE4_2", "instructions": [ + {"any": "pcmpestri R:xmm, xmm/m128, imm8, W:, , " , "op": "[RM] 66 0F 3A 61 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, + {"any": "pcmpestrm R:xmm, xmm/m128, imm8, W:, , " , "op": "[RM] 66 0F 3A 60 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, + {"any": "pcmpgtq X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 37 /r"}, + {"any": "pcmpistri R:xmm, xmm/m128, imm8, W:" , "op": "[RM] 66 0F 3A 63 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, + {"any": "pcmpistrm R:xmm, xmm/m128, imm8, W:" , "op": "[RM] 66 0F 3A 62 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"} + ]}, + + {"category": "SSE SIMD", "ext": "SSE4A", "instructions": [ + {"any": "extrq X:xmm, imm8, imm8" , "op": "[R ] 66 0F 78 /0 ib ib"}, + {"any": "extrq X:xmm, xmm" , "op": "[RM] 66 0F 79 /r"}, + {"any": "insertq X:xmm, xmm" , "op": "[RM] F2 0F 79 /r"}, + {"any": "insertq X:xmm, xmm, imm8, imm8" , "op": "[RM] F2 0F 78 /r ib ib"}, + {"any": "movntsd W:m64, xmm[63:0]" , "op": "[RM] F2 0F 2B /r"}, + {"any": "movntss W:m32, xmm[31:0]" , "op": "[RM] F3 0F 2B /r"} + ]}, + + {"category": "SSE SIMD CRYPTO_HASH", "ext": "KL", "instructions": [ + {"any": "loadiwkey R:xmm, R:xmm, R:, R:" , "op": "[RM] F3 0F 38 DC 11:rrr:bbb" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"} + ]}, + + {"category": "SSE SIMD CRYPTO_HASH", "ext": "AESKLE", "instructions": [ + {"any": "aesdec128kl X:xmm, R:m384" , "op": "[RM] F3 0F 38 DD !(11):rrr:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}, + {"any": "aesdec256kl X:xmm, R:m512" , "op": "[RM] F3 0F 38 DF !(11):rrr:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}, + {"any": "aesenc128kl X:xmm, R:m384" , "op": "[RM] F3 0F 38 DC !(11):rrr:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}, + {"any": "aesenc256kl X:xmm, R:m512" , "op": "[RM] F3 0F 38 DE !(11):rrr:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}, + {"___": "encodekey128 W:r32, R:r32, X:, W:" , "op": "[RM] F3 0F 38 FA 11:rrr:bbb" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=0"}, + {"___": "encodekey256 W:r32, R:r32, X:, W:" , "op": "[RM] F3 0F 38 FB 11:rrr:bbb" , "io": "OF=0 SF=0 ZF=0 AF=0 PF=0 CF=0"} + ]}, + + {"category": "SSE SIMD CRYPTO_HASH", "ext": "AESKLEWIDE_KL", "instructions": [ + {"___": "aesdecwide128kl R:m384, X:" , "op": "[RM] F3 0F 38 D8 !(11):001:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}, + {"___": "aesdecwide256kl R:m512, X:" , "op": "[RM] F3 0F 38 D8 !(11):011:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}, + {"___": "aesencwide128kl R:m384, X:" , "op": "[RM] F3 0F 38 D8 !(11):000:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}, + {"___": "aesencwide256kl R:m512, X:" , "op": "[RM] F3 0F 38 D8 !(11):010:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"} + ]}, + + {"category": "SSE SIMD CRYPTO_HASH", "ext": "AESNI", "instructions": [ + {"any": "aesdec X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 DE /r"}, + {"any": "aesdeclast X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 DF /r"}, + {"any": "aesenc X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 DC /r"}, + {"any": "aesenclast X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 DD /r"}, + {"any": "aesimc W:xmm, xmm/m128" , "op": "[RM] 66 0F 38 DB /r"}, + {"any": "aeskeygenassist W:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A DF /r ib"} + ]}, + + {"category": "SSE SIMD", "ext": "GFNI", "instructions": [ + {"any": "gf2p8affineinvqb X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A CF /r ib"}, + {"any": "gf2p8affineqb X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A CE /r ib"}, + {"any": "gf2p8mulb X:xmm, xmm/m128" , "op": "[RM] 66 0F 38 CF /r"} + ]}, + + {"category": "SSE SIMD", "ext": "PCLMULQDQ", "instructions": [ + {"any": "pclmulqdq X:xmm, xmm/m128, imm8" , "op": "[RM] 66 0F 3A 44 /r ib"} + ]}, + + {"category": "SSE SIMD CRYPTO_HASH", "ext": "SHA", "instructions": [ + {"any": "sha1msg1 xmm, xmm/m128" , "op": "[RM] NP 0F 38 C9 /r"}, + {"any": "sha1msg2 xmm, xmm/m128" , "op": "[RM] NP 0F 38 CA /r"}, + {"any": "sha1nexte xmm, xmm/m128" , "op": "[RM] NP 0F 38 C8 /r"}, + {"any": "sha1rnds4 xmm, xmm/m128, imm8" , "op": "[RM] NP 0F 3A CC /r ib"}, + {"any": "sha256msg1 xmm, xmm/m128" , "op": "[RM] NP 0F 38 CC /r"}, + {"any": "sha256msg2 xmm, xmm/m128" , "op": "[RM] NP 0F 38 CD /r"}, + {"any": "sha256rnds2 xmm, xmm/m128, " , "op": "[RM] NP 0F 38 CB /r"} + ]}, + + {"category": "AVX STATE", "ext": "AVX", "instructions": [ + {"any": "vldmxcsr R:m32" , "op": "[M ] VEX.LZ.NP.0F.WIG AE /2", "io": "MXCSR=W"}, + {"any": "vstmxcsr W:m32" , "op": "[M ] VEX.LZ.NP.0F.WIG AE /3", "io": "MXCSR=R"}, + {"any": "vzeroall" , "op": "[OP ] VEX.256.NP.0F.WIG 77", "volatile": true}, + {"any": "vzeroupper" , "op": "[OP ] VEX.128.NP.0F.WIG 77", "volatile": true} + ]}, + + {"category": "AVX SIMD", "ext": "AVX", "instructions": [ + {"any": "vaddpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 58 /r"}, + {"any": "vaddps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 58 /r"}, + {"any": "vaddsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 58 /r"}, + {"any": "vaddss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 58 /r"}, + {"any": "vaddsubpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG D0 /r"}, + {"any": "vaddsubps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F.WIG D0 /r"}, + {"any": "vandnpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 55 /r"}, + {"any": "vandnps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 55 /r"}, + {"any": "vandpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 54 /r"}, + {"any": "vandps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 54 /r"}, + {"any": "vblendpd W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F3A.WIG 0D /r ib"}, + {"any": "vblendps W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F3A.WIG 0C /r ib"}, + {"any": "vblendvpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS]VEX.Lxy.66.0F3A.W0 4B /r /is4"}, + {"any": "vblendvps W:xy, xy, xy/mxy, xy" , "op": "[RVMS]VEX.Lxy.66.0F3A.W0 4A /r /is4"}, + {"any": "vbroadcastf128 W:ymm, m128" , "op": "[RM ] VEX.256.66.0F38.W0 1A /r"}, + {"any": "vbroadcastsd W:ymm, m64" , "op": "[RM ] VEX.256.66.0F38.W0 19 /r"}, + {"any": "vbroadcastss W:xy, m32" , "op": "[RM ] VEX.Lxy.66.0F38.W0 18 /r"}, + {"any": "vcmppd W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F.WIG C2 /r ib"}, + {"any": "vcmpps W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.NP.0F.WIG C2 /r ib"}, + {"any": "vcmpsd W:xmm, xmm, xmm[63:0]/m64, imm8" , "op": "[RVM] VEX.LIG.F2.0F.WIG C2 /r ib"}, + {"any": "vcmpss W:xmm, xmm, xmm[31:0]/m32, imm8" , "op": "[RVM] VEX.LIG.F3.0F.WIG C2 /r ib"}, + {"any": "vcomisd R:xmm[63:0], xmm[63:0]/m64" , "op": "[RM ] VEX.LIG.66.0F.WIG 2F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "vcomiss R:xmm[31:0], xmm[31:0]/m32" , "op": "[RM ] VEX.LIG.NP.0F.WIG 2F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "vcvtdq2pd W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.F3.0F.WIG E6 /r"}, + {"any": "vcvtdq2pd W:ymm, xmm/m128" , "op": "[RM ] VEX.256.F3.0F.WIG E6 /r"}, + {"any": "vcvtdq2ps W:xmm, xmm/m128" , "op": "[RM ] VEX.128.NP.0F.WIG 5B /r"}, + {"any": "vcvtdq2ps W:ymm, ymm/m256" , "op": "[RM ] VEX.256.NP.0F.WIG 5B /r"}, + {"any": "vcvtpd2dq W:xmm[63:0], xmm/m128" , "op": "[RM ] VEX.128.F2.0F.WIG E6 /r"}, + {"any": "vcvtpd2dq W:xmm, ymm/m256" , "op": "[RM ] VEX.256.F2.0F.WIG E6 /r"}, + {"any": "vcvtpd2ps W:xmm[63:0], xmm/m128" , "op": "[RM ] VEX.128.66.0F.WIG 5A /r"}, + {"any": "vcvtpd2ps W:xmm, ymm/m256" , "op": "[RM ] VEX.256.66.0F.WIG 5A /r"}, + {"any": "vcvtps2dq W:xmm, xmm/m128" , "op": "[RM ] VEX.128.66.0F.WIG 5B /r"}, + {"any": "vcvtps2dq W:ymm, ymm/m256" , "op": "[RM ] VEX.256.66.0F.WIG 5B /r"}, + {"any": "vcvtps2pd W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.NP.0F.WIG 5A /r"}, + {"any": "vcvtps2pd W:ymm, xmm/m128" , "op": "[RM ] VEX.256.NP.0F.WIG 5A /r"}, + {"any": "vcvtsd2si W:ry, xmm[63:0]/m64" , "op": "[RM ] VEX.LIG.F2.0F.Wy 2D /r"}, + {"any": "vcvtsd2ss W:xmm, xmm[127:32], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 5A /r"}, + {"any": "vcvtsi2sd W:xmm, xmm[127:64], ry/my" , "op": "[RVM] VEX.LIG.F2.0F.Wy 2A /r"}, + {"any": "vcvtsi2ss W:xmm, xmm[127:32], ry/my" , "op": "[RVM] VEX.LIG.F3.0F.Wy 2A /r"}, + {"any": "vcvtss2sd W:xmm, xmm[127:64], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 5A /r"}, + {"any": "vcvtss2si W:ry, xmm[31:0]/m32" , "op": "[RM ] VEX.LIG.F3.0F.Wy 2D /r"}, + {"any": "vcvttpd2dq W:xmm[63:0], xmm/m128" , "op": "[RM ] VEX.128.66.0F.WIG E6 /r"}, + {"any": "vcvttpd2dq W:xmm, ymm/m256" , "op": "[RM ] VEX.256.66.0F.WIG E6 /r"}, + {"any": "vcvttps2dq W:xmm, xmm/m128" , "op": "[RM ] VEX.128.F3.0F.WIG 5B /r"}, + {"any": "vcvttps2dq W:ymm, ymm/m256" , "op": "[RM ] VEX.256.F3.0F.WIG 5B /r"}, + {"any": "vcvttsd2si W:ry, xmm[63:0]/m64" , "op": "[RM ] VEX.LIG.F2.0F.Wy 2C /r"}, + {"any": "vcvttss2si W:ry, xmm[31:0]/m32" , "op": "[RM ] VEX.LIG.F3.0F.Wy 2C /r"}, + {"any": "vdivpd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 5E /r"}, + {"any": "vdivpd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 5E /r"}, + {"any": "vdivps W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.NP.0F.WIG 5E /r"}, + {"any": "vdivps W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.NP.0F.WIG 5E /r"}, + {"any": "vdivsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 5E /r"}, + {"any": "vdivss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 5E /r"}, + {"any": "vdppd W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 41 /r ib"}, + {"any": "vdpps W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F3A.WIG 40 /r ib"}, + {"any": "vextractps W:r32[31:0]/m32, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.WIG 17 /r ib"}, + {"any": "vextractf128 W:xmm/m128, ymm, imm8" , "op": "[MR ] VEX.256.66.0F3A.W0 19 /r ib"}, + {"any": "vhaddpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 7C /r"}, + {"any": "vhaddps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F.WIG 7C /r"}, + {"any": "vhsubpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 7D /r"}, + {"any": "vhsubps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F.WIG 7D /r"}, + {"any": "vinsertf128 W:ymm, ymm, xmm/m128, imm8" , "op": "[RVM] VEX.256.66.0F3A.W0 18 /r ib"}, + {"any": "vinsertps W:xmm, xmm, xmm[31:0]/m32, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 21 /r ib"}, + {"any": "vlddqu W:xy, mxy" , "op": "[RM ] VEX.Lxy.F2.0F.WIG F0 /r"}, + {"any": "vmaskmovdqu R:xmm, xmm, X:" , "op": "[RM ] VEX.128.66.0F.WIG F7 /r"}, + {"any": "vmaskmovpd X:mxy, xy, xy" , "op": "[MVR] VEX.Lxy.66.0F38.W0 2F /r"}, + {"any": "vmaskmovpd W:xy, xy, mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 2D /r"}, + {"any": "vmaskmovps X:mxy, xy, xy" , "op": "[MVR] VEX.Lxy.66.0F38.W0 2E /r"}, + {"any": "vmaskmovps W:xy, xy, mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 2C /r"}, + {"any": "vmaxpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 5F /r"}, + {"any": "vmaxps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 5F /r"}, + {"any": "vmaxsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 5F /r"}, + {"any": "vmaxss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 5F /r"}, + {"any": "vminpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 5D /r"}, + {"any": "vminps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 5D /r"}, + {"any": "vminsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 5D /r"}, + {"any": "vminss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 5D /r"}, + {"any": "vmovapd W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F.WIG 28 /r"}, + {"any": "vmovapd W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.66.0F.WIG 29 /r"}, + {"any": "vmovaps W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.NP.0F.WIG 28 /r"}, + {"any": "vmovaps W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.NP.0F.WIG 29 /r"}, + {"any": "vmovd W:r32[31:0]/m32, xmm[31:0]" , "op": "[MR ] VEX.128.66.0F.W0 7E /r"}, + {"any": "vmovd W:xmm[31:0], r32[31:0]/m32" , "op": "[RM ] VEX.128.66.0F.W0 6E /r"}, + {"any": "vmovddup W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.F2.0F.WIG 12 /r"}, + {"any": "vmovddup W:ymm, ymm/m256" , "op": "[RM ] VEX.256.F2.0F.WIG 12 /r"}, + {"any": "vmovdqa W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F.WIG 6F /r"}, + {"any": "vmovdqa W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.66.0F.WIG 7F /r"}, + {"any": "vmovdqu W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.F3.0F.WIG 6F /r"}, + {"any": "vmovdqu W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.F3.0F.WIG 7F /r"}, + {"any": "vmovhlps W:xmm, xmm[127:64], xmm[127:64]" , "op": "[RVM] VEX.128.NP.0F.WIG 12 /r"}, + {"any": "vmovhpd W:m64, xmm[127:64]" , "op": "[MR ] VEX.128.66.0F.WIG 17 /r"}, + {"any": "vmovhpd W:xmm, xmm[63:0], m64" , "op": "[RVM] VEX.128.66.0F.WIG 16 /r"}, + {"any": "vmovhps W:m64, xmm[127:64]" , "op": "[MR ] VEX.128.NP.0F.WIG 17 /r"}, + {"any": "vmovhps W:xmm, xmm[63:0], m64" , "op": "[RVM] VEX.128.NP.0F.WIG 16 /r"}, + {"any": "vmovlhps W:xmm, xmm[63:0], xmm[63:0]" , "op": "[RVM] VEX.128.NP.0F.WIG 16 /r"}, + {"any": "vmovlpd W:m64, xmm[63:0]" , "op": "[MR ] VEX.128.66.0F.WIG 13 /r"}, + {"any": "vmovlpd W:xmm, xmm[127:64], m64" , "op": "[RVM] VEX.128.66.0F.WIG 12 /r"}, + {"any": "vmovlps W:m64, xmm[63:0]" , "op": "[MR ] VEX.128.NP.0F.WIG 13 /r"}, + {"any": "vmovlps W:xmm, xmm[127:64], m64" , "op": "[RVM] VEX.128.NP.0F.WIG 12 /r"}, + {"any": "vmovmskpd W:r32[1:0], xmm" , "op": "[RM ] VEX.128.66.0F.WIG 50 /r"}, + {"any": "vmovmskpd W:r32[3:0], ymm" , "op": "[RM ] VEX.256.66.0F.WIG 50 /r"}, + {"any": "vmovmskps W:r32[3:0], xmm" , "op": "[RM ] VEX.128.NP.0F.WIG 50 /r"}, + {"any": "vmovmskps W:r32[7:0], ymm" , "op": "[RM ] VEX.256.NP.0F.WIG 50 /r"}, + {"any": "vmovntdq W:mxy, xy" , "op": "[MR ] VEX.Lxy.66.0F.WIG E7 /r"}, + {"any": "vmovntdqa W:xmm, m128" , "op": "[RM ] VEX.128.66.0F38.WIG 2A /r"}, + {"any": "vmovntpd W:mxy, xy" , "op": "[MR ] VEX.Lxy.66.0F.WIG 2B /r"}, + {"any": "vmovntps W:mxy, xy" , "op": "[MR ] VEX.Lxy.NP.0F.WIG 2B /r"}, + {"any": "vmovq W:r64/m64, xmm[63:0]" , "op": "[MR ] VEX.128.66.0F.W1 7E /r"}, + {"any": "vmovq W:xmm[63:0], xmm[63:0]/m64" , "op": "[RM ] VEX.128.F3.0F.WIG 7E /r"}, + {"any": "vmovq W:xmm[63:0], r64/m64" , "op": "[RM ] VEX.128.66.0F.W1 6E /r"}, + {"any": "vmovq W:xmm[63:0]/m64, xmm[63:0]" , "op": "[MR ] VEX.128.66.0F.WIG D6 /r"}, + {"any": "vmovsd W:m64, xmm[63:0]" , "op": "[MR ] VEX.LIG.F2.0F.WIG 11 /r"}, + {"any": "vmovsd W:xmm[63:0], m64" , "op": "[RM ] VEX.LIG.F2.0F.WIG 10 /r"}, + {"any": "vmovsd W:xmm, xmm[127:64], xmm[63:0]" , "op": "[MVR] VEX.LIG.F2.0F.WIG 11 /r"}, + {"any": "vmovsd W:xmm, xmm[127:64], xmm[63:0]" , "op": "[RVM] VEX.LIG.F2.0F.WIG 10 /r"}, + {"any": "vmovshdup W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.F3.0F.WIG 16 /r"}, + {"any": "vmovsldup W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.F3.0F.WIG 12 /r"}, + {"any": "vmovss W:m32, xmm[31:0]" , "op": "[MR ] VEX.LIG.F3.0F.WIG 11 /r"}, + {"any": "vmovss W:xmm[31:0], m32" , "op": "[RM ] VEX.LIG.F3.0F.WIG 10 /r"}, + {"any": "vmovss W:xmm, xmm[127:32], xmm[31:0]" , "op": "[MVR] VEX.LIG.F3.0F.WIG 11 /r"}, + {"any": "vmovss W:xmm, xmm[127:32], xmm[31:0]" , "op": "[RVM] VEX.LIG.F3.0F.WIG 10 /r"}, + {"any": "vmovupd W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.NP.0F.WIG 10 /r"}, + {"any": "vmovupd W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.NP.0F.WIG 11 /r"}, + {"any": "vmovups W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F.WIG 10 /r"}, + {"any": "vmovups W:xy/mxy, xy" , "op": "[MR ] VEX.Lxy.66.0F.WIG 11 /r"}, + {"any": "vmpsadbw W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 42 /r ib"}, + {"any": "vmulpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 59 /r"}, + {"any": "vmulps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 59 /r"}, + {"any": "vmulsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 59 /r"}, + {"any": "vmulss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 59 /r"}, + {"any": "vorpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 56 /r"}, + {"any": "vorps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 56 /r"}, + {"any": "vpabsb W:xmm, xmm/m128" , "op": "[RM ] VEX.128.66.0F38.WIG 1C /r"}, + {"any": "vpabsd W:xmm, xmm/m128" , "op": "[RM_] VEX.128.66.0F38.WIG 1E /r"}, + {"any": "vpabsw W:xmm, xmm/m128" , "op": "[RM ] VEX.128.66.0F38.WIG 1D /r"}, + {"any": "vpackssdw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 6B /r"}, + {"any": "vpacksswb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 63 /r"}, + {"any": "vpackusdw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 2B /r"}, + {"any": "vpackuswb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 67 /r"}, + {"any": "vpaddb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG FC /r"}, + {"any": "vpaddd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG FE /r"}, + {"any": "vpaddq W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D4 /r"}, + {"any": "vpaddsb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG EC /r"}, + {"any": "vpaddsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG ED /r"}, + {"any": "vpaddusb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DC /r"}, + {"any": "vpaddusw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DD /r"}, + {"any": "vpaddw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG FD /r"}, + {"any": "vpalignr W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 0F /r ib"}, + {"any": "vpand W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DB /r"}, + {"any": "vpandn W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DF /r"}, + {"any": "vpavgb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E0 /r"}, + {"any": "vpavgw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E3 /r"}, + {"any": "vpblendvb W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]VEX.128.66.0F3A.W0 4C /r /is4"}, + {"any": "vpblendw W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 0E /r ib"}, + {"any": "vpcmpeqb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 74 /r"}, + {"any": "vpcmpeqd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 76 /r"}, + {"any": "vpcmpeqq W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 29 /r"}, + {"any": "vpcmpeqw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 75 /r"}, + {"any": "vpcmpestri R:xmm, xmm/m128, imm8, W:, , " , "op": "[RM ] VEX.128.66.0F3A.WIG 61 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, + {"any": "vpcmpestrm R:xmm, xmm/m128, imm8, W:, , " , "op": "[RM ] VEX.128.66.0F3A.WIG 60 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, + {"any": "vpcmpgtb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 64 /r"}, + {"any": "vpcmpgtd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 66 /r"}, + {"any": "vpcmpgtq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 37 /r"}, + {"any": "vpcmpgtw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 65 /r"}, + {"any": "vpcmpistri R:xmm, xmm/m128, imm8, W:" , "op": "[RM ] VEX.128.66.0F3A.WIG 63 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, + {"any": "vpcmpistrm R:xmm, xmm/m128, imm8, W:" , "op": "[RM ] VEX.128.66.0F3A.WIG 62 /r ib", "io": "OF=W SF=W ZF=W AF=0 PF=0 CF=W"}, + {"any": "vperm2f128 W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.W0 06 /r ib"}, + {"any": "vpermilpd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 0D /r"}, + {"any": "vpermilpd W:xmm, xmm/m128, imm8" , "op": "[RM ] VEX.128.66.0F3A.W0 05 /r ib"}, + {"any": "vpermilpd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 0D /r"}, + {"any": "vpermilpd W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.66.0F3A.W0 05 /r ib"}, + {"any": "vpermilps W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 0C /r"}, + {"any": "vpermilps W:xmm, xmm/m128, imm8" , "op": "[RM ] VEX.128.66.0F3A.W0 04 /r ib"}, + {"any": "vpermilps W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 0C /r"}, + {"any": "vpermilps W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.66.0F3A.W0 04 /r ib"}, + {"any": "vpextrb W:r32[7:0]/m8, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.W0 14 /r ib"}, + {"any": "vpextrd W:r32/m32, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.W0 16 /r ib"}, + {"any": "vpextrq W:r64/m64, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.W1 16 /r ib"}, + {"any": "vpextrw W:r32[15:0], xmm, imm8" , "op": "[RM ] VEX.128.66.0F.W0 C5 /r ib"}, + {"any": "vpextrw W:r32[15:0]/m16, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.W0 15 /r ib"}, + {"any": "vphaddd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 02 /r"}, + {"any": "vphaddsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 03 /r"}, + {"any": "vphaddw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 01 /r"}, + {"any": "vphminposuw W:xmm[18:0], xmm/m128" , "op": "[RM ] VEX.128.66.0F38.WIG 41 /r"}, + {"any": "vphsubd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 06 /r"}, + {"any": "vphsubsw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 07 /r"}, + {"any": "vphsubw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 05 /r"}, + {"any": "vpinsrb W:xmm, xmm, r32[7:0]/m8, imm8" , "op": "[RVM] VEX.128.66.0F3A.W0 20 /r ib"}, + {"any": "vpinsrd W:xmm, xmm, r32/m32, imm8" , "op": "[RVM] VEX.128.66.0F3A.W0 22 /r ib"}, + {"any": "vpinsrq W:xmm, xmm, r64/m64, imm8" , "op": "[RVM] VEX.128.66.0F3A.W1 22 /r ib"}, + {"any": "vpinsrw W:xmm, xmm, r32[15:0]/m16, imm8" , "op": "[RVM] VEX.128.66.0F.W0 C4 /r ib"}, + {"any": "vpmaddubsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 04 /r"}, + {"any": "vpmaddwd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F5 /r"}, + {"any": "vpmaxsb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3C /r"}, + {"any": "vpmaxsd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3D /r"}, + {"any": "vpmaxsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG EE /r"}, + {"any": "vpmaxub W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DE /r"}, + {"any": "vpmaxud W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3F /r"}, + {"any": "vpmaxuw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3E /r"}, + {"any": "vpminsb W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 38 /r"}, + {"any": "vpminsd W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 39 /r"}, + {"any": "vpminsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG EA /r"}, + {"any": "vpminub W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG DA /r"}, + {"any": "vpminud W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3B /r"}, + {"any": "vpminuw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 3A /r"}, + {"any": "vpmovmskb W:r32[15:0], xmm" , "op": "[RVM] VEX.128.66.0F.WIG D7 /r"}, + {"any": "vpmovsxwq W:xmm, xmm[31:0]/m32" , "op": "[RM ] VEX.128.66.0F38.WIG 24 /r"}, + {"any": "vpmovsxbd W:xmm, xmm[31:0]/m32" , "op": "[RM ] VEX.128.66.0F38.WIG 21 /r"}, + {"any": "vpmovsxbq W:xmm, xmm[15:0]/m16" , "op": "[RM ] VEX.128.66.0F38.WIG 22 /r"}, + {"any": "vpmovsxbw W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 20 /r"}, + {"any": "vpmovsxdq W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 25 /r"}, + {"any": "vpmovsxwd W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 23 /r"}, + {"any": "vpmovzxbd W:xmm, xmm[31:0]/m32" , "op": "[RM ] VEX.128.66.0F38.WIG 31 /r"}, + {"any": "vpmovzxbq W:xmm, xmm[15:0]/m16" , "op": "[RM ] VEX.128.66.0F38.WIG 32 /r"}, + {"any": "vpmovzxbw W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 30 /r"}, + {"any": "vpmovzxdq W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 35 /r"}, + {"any": "vpmovzxwd W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.WIG 33 /r"}, + {"any": "vpmovzxwq W:xmm, xmm[31:0]/m32" , "op": "[RM ] VEX.128.66.0F38.WIG 34 /r"}, + {"any": "vpmuldq W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 28 /r"}, + {"any": "vpmulhrsw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 0B /r"}, + {"any": "vpmulhuw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E4 /r"}, + {"any": "vpmulhw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E5 /r"}, + {"any": "vpmulld W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 40 /r"}, + {"any": "vpmullw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D5 /r"}, + {"any": "vpmuludq W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F4 /r"}, + {"any": "vpor W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG EB /r"}, + {"any": "vpsadbw W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F6 /r"}, + {"any": "vpshufb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 00 /r"}, + {"any": "vpshufd W:xmm, xmm/m128, imm8" , "op": "[RM ] VEX.128.66.0F.WIG 70 /r ib"}, + {"any": "vpshufhw W:xmm, xmm/m128, imm8" , "op": "[RM ] VEX.128.F3.0F.WIG 70 /r ib"}, + {"any": "vpshuflw W:xmm, xmm/m128, imm8" , "op": "[RM ] VEX.128.F2.0F.WIG 70 /r ib"}, + {"any": "vpsignb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 08 /r"}, + {"any": "vpsignd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 0A /r"}, + {"any": "vpsignw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG 09 /r"}, + {"any": "vpslld W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F2 /r"}, + {"any": "vpslld W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 72 /6 ib"}, + {"any": "vpslldq W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 73 /7 ib"}, + {"any": "vpsllq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F3 /r"}, + {"any": "vpsllq W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 73 /6 ib"}, + {"any": "vpsllw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F1 /r"}, + {"any": "vpsllw W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 71 /6 ib"}, + {"any": "vpsrad W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E2 /r"}, + {"any": "vpsrad W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 72 /4 ib"}, + {"any": "vpsraw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E1 /r"}, + {"any": "vpsraw W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 71 /4 ib"}, + {"any": "vpsrld W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D2 /r"}, + {"any": "vpsrld W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 72 /2 ib"}, + {"any": "vpsrldq W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 73 /3 ib"}, + {"any": "vpsrlq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D3 /r"}, + {"any": "vpsrlq W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 73 /2 ib"}, + {"any": "vpsrlw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D1 /r"}, + {"any": "vpsrlw W:xmm, xmm, imm8" , "op": "[VM ] VEX.128.66.0F.WIG 71 /2 ib"}, + {"any": "vpsubb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F8 /r"}, + {"any": "vpsubd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG FA /r"}, + {"any": "vpsubq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG FB /r"}, + {"any": "vpsubsb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E8 /r"}, + {"any": "vpsubsw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG E9 /r"}, + {"any": "vpsubusb W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D8 /r"}, + {"any": "vpsubusw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG D9 /r"}, + {"any": "vpsubw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG F9 /r"}, + {"any": "vptest R:~xy, ~xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F38.WIG 17 /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, + {"any": "vpunpckhbw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 68 /r"}, + {"any": "vpunpckhdq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 6A /r"}, + {"any": "vpunpckhqdq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 6D /r"}, + {"any": "vpunpckhwd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 69 /r"}, + {"any": "vpunpcklbw W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 60 /r"}, + {"any": "vpunpckldq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 62 /r"}, + {"any": "vpunpcklqdq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 6C /r"}, + {"any": "vpunpcklwd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG 61 /r"}, + {"any": "vpxor W:xmm, ~xmm, ~xmm/m128" , "op": "[RVM] VEX.128.66.0F.WIG EF /r"}, + {"any": "vrcpps W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.NP.0F.WIG 53 /r"}, + {"any": "vrcpss W:xmm, xmm[127:32], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 53 /r"}, + {"any": "vroundpd W:xy, xy/mxy, imm8" , "op": "[RM ] VEX.Lxy.66.0F3A.WIG 09 /r ib"}, + {"any": "vroundps W:xy, xy/mxy, imm8" , "op": "[RM ] VEX.Lxy.66.0F3A.WIG 08 /r ib"}, + {"any": "vroundsd W:xmm, xmm[127:64], xmm[63:0]/m64, imm8" , "op": "[RVM] VEX.LIG.66.0F3A.WIG 0B /r ib"}, + {"any": "vroundss W:xmm, xmm[127:32], xmm[31:0]/m32, imm8" , "op": "[RVM] VEX.LIG.66.0F3A.WIG 0A /r ib"}, + {"any": "vrsqrtps W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.NP.0F.WIG 52 /r"}, + {"any": "vrsqrtss W:xmm, xmm[127:32], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 52 /r"}, + {"any": "vshufpd W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F.WIG C6 /r ib"}, + {"any": "vshufps W:xy, xy, xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.NP.0F.WIG C6 /r ib"}, + {"any": "vsqrtpd W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F.WIG 51 /r"}, + {"any": "vsqrtps W:xy, xy/mxy" , "op": "[RM ] VEX.Lxy.NP.0F.WIG 51 /r"}, + {"any": "vsqrtsd W:xmm, xmm[127:64], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 51 /r"}, + {"any": "vsqrtss W:xmm, xmm[127:32], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 51 /r"}, + {"any": "vsubpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 5C /r"}, + {"any": "vsubps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 5C /r"}, + {"any": "vsubsd W:xmm, xmm, xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.F2.0F.WIG 5C /r"}, + {"any": "vsubss W:xmm, xmm, xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.F3.0F.WIG 5C /r"}, + {"any": "vtestpd R:~xy, ~xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F38.W0 0F /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, + {"any": "vtestps R:~xy, ~xy/mxy" , "op": "[RM ] VEX.Lxy.66.0F38.W0 0E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, + {"any": "vucomisd R:xmm[63:0], xmm[63:0]/m64" , "op": "[RM ] VEX.LIG.66.0F.WIG 2E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "vucomiss R:xmm[31:0], xmm[31:0]/m32" , "op": "[RM ] VEX.LIG.NP.0F.WIG 2E /r", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "vunpckhpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 15 /r"}, + {"any": "vunpckhps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 15 /r"}, + {"any": "vunpcklpd W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 14 /r"}, + {"any": "vunpcklps W:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 14 /r"}, + {"any": "vxorpd W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F.WIG 57 /r"}, + {"any": "vxorps W:xy, ~xy, ~xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F.WIG 57 /r"} + ]}, + + {"category": "AVX SIMD CRYPTO_HASH", "ext": "AVX AESNI", "instructions": [ + {"any": "vaesdec W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG DE /r"}, + {"any": "vaesdeclast W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG DF /r"}, + {"any": "vaesenc W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG DC /r"}, + {"any": "vaesenclast W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG DD /r"}, + {"any": "vaesimc W:xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.WIG DB /r"}, + {"any": "vaeskeygenassist W:xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG DF /r ib"} + ]}, + + {"category": "AVX SIMD CRYPTO_HASH", "ext": "VAES", "instructions": [ + {"any": "vaesdec W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG DE /r"}, + {"any": "vaesdeclast W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG DF /r"}, + {"any": "vaesenc W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG DC /r"}, + {"any": "vaesenclast W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG DD /r"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX GFNI", "instructions": [ + {"any": "vgf2p8affineinvqb W:xy, R:xy, R:xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F3A.W1 CF /r ib"}, + {"any": "vgf2p8affineqb W:xy, R:xy, R:xy/mxy, imm8" , "op": "[RVM] VEX.Lxy.66.0F3A.W1 CE /r ib"}, + {"any": "vgf2p8mulb W:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 CF /r"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX2", "instructions": [ + {"any": "vbroadcasti128 W:ymm, m128" , "op": "[RM ] VEX.256.66.0F38.W0 5A /r"}, + {"any": "vbroadcastsd W:ymm, xmm[63:0]" , "op": "[RM ] VEX.256.66.0F38.W0 19 /r"}, + {"any": "vbroadcastss W:xmm, xmm[31:0]" , "op": "[RM ] VEX.128.66.0F38.W0 18 /r"}, + {"any": "vbroadcastss W:ymm, xmm[31:0]" , "op": "[RM ] VEX.256.66.0F38.W0 18 /r"}, + {"any": "vextracti128 W:xmm/m128, ymm, imm8" , "op": "[MR ] VEX.256.66.0F3A.W0 39 /r ib"}, + {"any": "vgatherdpd X:xmm, vm32x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W1 92 /r"}, + {"any": "vgatherdpd X:ymm, vm32x, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W1 92 /r"}, + {"any": "vgatherdps X:xmm, vm32x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W0 92 /r"}, + {"any": "vgatherdps X:ymm, vm32y, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W0 92 /r"}, + {"any": "vgatherqpd X:xmm, vm64x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W1 93 /r"}, + {"any": "vgatherqpd X:ymm, vm64y, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W1 93 /r"}, + {"any": "vgatherqps X:xmm, vm64x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W0 93 /r"}, + {"any": "vgatherqps X:xmm, vm64y, X:xmm" , "op": "[RMV] VEX.256.66.0F38.W0 93 /r"}, + {"any": "vinserti128 W:ymm, ymm, xmm/m128, imm8" , "op": "[RVM] VEX.256.66.0F3A.W0 38 /r ib"}, + {"any": "vmovntdqa W:ymm, m256" , "op": "[RM ] VEX.256.66.0F38.WIG 2A /r"}, + {"any": "vmpsadbw W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.WIG 42 /r ib"}, + {"any": "vpabsb W:ymm, ymm/m256" , "op": "[RM ] VEX.256.66.0F38.WIG 1C /r"}, + {"any": "vpabsd W:ymm, ymm/m256" , "op": "[RM ] VEX.256.66.0F38.WIG 1E /r"}, + {"any": "vpabsw W:ymm, ymm/m256" , "op": "[RM ] VEX.256.66.0F38.WIG 1D /r"}, + {"any": "vpackssdw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 6B /r"}, + {"any": "vpacksswb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 63 /r"}, + {"any": "vpackusdw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 2B /r"}, + {"any": "vpackuswb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 67 /r"}, + {"any": "vpaddb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG FC /r"}, + {"any": "vpaddd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG FE /r"}, + {"any": "vpaddq W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG D4 /r"}, + {"any": "vpaddsb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG EC /r"}, + {"any": "vpaddsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG ED /r"}, + {"any": "vpaddusb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DC /r"}, + {"any": "vpaddusw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DD /r"}, + {"any": "vpaddw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG FD /r"}, + {"any": "vpalignr W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.WIG 0F /r ib"}, + {"any": "vpand W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DB /r"}, + {"any": "vpandn W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DF /r"}, + {"any": "vpavgb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E0 /r"}, + {"any": "vpavgw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E3 /r"}, + {"any": "vpblendd W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.W0 02 /r ib"}, + {"any": "vpblendd W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.W0 02 /r ib"}, + {"any": "vpblendvb W:ymm, ymm, ymm/m256, ymm" , "op": "[RVMS]VEX.256.66.0F3A.W0 4C /r /is4"}, + {"any": "vpblendw W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.WIG 0E /r ib"}, + {"any": "vpbroadcastb W:xmm, xmm[7:0]/m8" , "op": "[RM ] VEX.128.66.0F38.W0 78 /r"}, + {"any": "vpbroadcastb W:ymm, xmm[7:0]/m8" , "op": "[RM ] VEX.256.66.0F38.W0 78 /r"}, + {"any": "vpbroadcastd W:xmm, xmm[31:0]/m32" , "op": "[RM ] VEX.128.66.0F38.W0 58 /r"}, + {"any": "vpbroadcastd W:ymm, xmm[31:0]/m32" , "op": "[RM ] VEX.256.66.0F38.W0 58 /r"}, + {"any": "vpbroadcastq W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.W0 59 /r"}, + {"any": "vpbroadcastq W:ymm, xmm[63:0]/m64" , "op": "[RM ] VEX.256.66.0F38.W0 59 /r"}, + {"any": "vpbroadcastw W:xmm, xmm[15:0]/m16" , "op": "[RM ] VEX.128.66.0F38.W0 79 /r"}, + {"any": "vpbroadcastw W:ymm, xmm[15:0]/m16" , "op": "[RM ] VEX.256.66.0F38.W0 79 /r"}, + {"any": "vpcmpeqb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 74 /r"}, + {"any": "vpcmpeqd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 76 /r"}, + {"any": "vpcmpeqq W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 29 /r"}, + {"any": "vpcmpeqw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 75 /r"}, + {"any": "vpcmpgtb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 64 /r"}, + {"any": "vpcmpgtd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 66 /r"}, + {"any": "vpcmpgtq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 37 /r"}, + {"any": "vpcmpgtw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 65 /r"}, + {"any": "vperm2i128 W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.W0 46 /r ib"}, + {"any": "vpermd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 36 /r"}, + {"any": "vpermpd W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.66.0F3A.W1 01 /r ib"}, + {"any": "vpermps W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 16 /r"}, + {"any": "vpermq W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.66.0F3A.W1 00 /r ib"}, + {"any": "vpgatherdd X:xmm, vm32x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W0 90 /r"}, + {"any": "vpgatherdd X:ymm, vm32y, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W0 90 /r"}, + {"any": "vpgatherdq X:xmm, vm32x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W1 90 /r"}, + {"any": "vpgatherdq X:ymm, vm32x, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W1 90 /r"}, + {"any": "vpgatherqd X:xmm, vm64x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W0 91 /r"}, + {"any": "vpgatherqd X:xmm, vm64y, X:xmm" , "op": "[RMV] VEX.256.66.0F38.W0 91 /r"}, + {"any": "vpgatherqq X:xmm, vm64x, X:xmm" , "op": "[RMV] VEX.128.66.0F38.W1 91 /r"}, + {"any": "vpgatherqq X:ymm, vm64y, X:ymm" , "op": "[RMV] VEX.256.66.0F38.W1 91 /r"}, + {"any": "vphaddd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 02 /r"}, + {"any": "vphaddsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 03 /r"}, + {"any": "vphaddw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 01 /r"}, + {"any": "vphsubd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 06 /r"}, + {"any": "vphsubsw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 07 /r"}, + {"any": "vphsubw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 05 /r"}, + {"any": "vpmaddubsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 04 /r"}, + {"any": "vpmaddwd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG F5 /r"}, + {"any": "vpmaskmovd X:m128, xmm, xmm" , "op": "[MVR] VEX.128.66.0F38.W0 8E /r"}, + {"any": "vpmaskmovd X:m256, ymm, ymm" , "op": "[MVR] VEX.256.66.0F38.W0 8E /r"}, + {"any": "vpmaskmovd W:xmm, xmm, m128" , "op": "[RVM] VEX.128.66.0F38.W0 8C /r"}, + {"any": "vpmaskmovd W:ymm, ymm, m256" , "op": "[RVM] VEX.256.66.0F38.W0 8C /r"}, + {"any": "vpmaskmovq X:m128, xmm, xmm" , "op": "[MVR] VEX.128.66.0F38.W1 8E /r"}, + {"any": "vpmaskmovq X:m256, ymm, ymm" , "op": "[MVR] VEX.256.66.0F38.W1 8E /r"}, + {"any": "vpmaskmovq W:xmm, xmm, m128" , "op": "[RVM] VEX.128.66.0F38.W1 8C /r"}, + {"any": "vpmaskmovq W:ymm, ymm, m256" , "op": "[RVM] VEX.256.66.0F38.W1 8C /r"}, + {"any": "vpmaxsb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3C /r"}, + {"any": "vpmaxsd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3D /r"}, + {"any": "vpmaxsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG EE /r"}, + {"any": "vpmaxub W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DE /r"}, + {"any": "vpmaxud W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3F /r"}, + {"any": "vpmaxuw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3E /r"}, + {"any": "vpminsb W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 38 /r"}, + {"any": "vpminsd W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 39 /r"}, + {"any": "vpminsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG EA /r"}, + {"any": "vpminub W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG DA /r"}, + {"any": "vpminud W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3B /r"}, + {"any": "vpminuw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 3A /r"}, + {"any": "vpmovmskb W:r32[31:0], ymm" , "op": "[RVM] VEX.256.66.0F.WIG D7 /r"}, + {"any": "vpmovsxbd W:ymm, xmm[63:0]/m64" , "op": "[RM ] VEX.256.66.0F38.WIG 21 /r"}, + {"any": "vpmovsxbq W:ymm, xmm[31:0]/m32" , "op": "[RM ] VEX.256.66.0F38.WIG 22 /r"}, + {"any": "vpmovsxbw W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 20 /r"}, + {"any": "vpmovsxdq W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 25 /r"}, + {"any": "vpmovsxwd W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 23 /r"}, + {"any": "vpmovsxwq W:ymm, xmm[63:0]/m64" , "op": "[RM ] VEX.256.66.0F38.WIG 24 /r"}, + {"any": "vpmovzxbd W:ymm, xmm[63:0]/m64" , "op": "[RM ] VEX.256.66.0F38.WIG 31 /r"}, + {"any": "vpmovzxbq W:ymm, xmm[31:0]/m32" , "op": "[RM ] VEX.256.66.0F38.WIG 32 /r"}, + {"any": "vpmovzxbw W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 30 /r"}, + {"any": "vpmovzxdq W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 35 /r"}, + {"any": "vpmovzxwd W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.WIG 33 /r"}, + {"any": "vpmovzxwq W:ymm, xmm[63:0]/m64" , "op": "[RM ] VEX.256.66.0F38.WIG 34 /r"}, + {"any": "vpmuldq W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 28 /r"}, + {"any": "vpmulhrsw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 0B /r"}, + {"any": "vpmulhuw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E4 /r"}, + {"any": "vpmulhw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E5 /r"}, + {"any": "vpmulld W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 40 /r"}, + {"any": "vpmullw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG D5 /r"}, + {"any": "vpmuludq W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG F4 /r"}, + {"any": "vpor W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG EB /r"}, + {"any": "vpsadbw W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG F6 /r"}, + {"any": "vpshufb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 00 /r"}, + {"any": "vpshufd W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.66.0F.WIG 70 /r ib"}, + {"any": "vpshufhw W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.F3.0F.WIG 70 /r ib"}, + {"any": "vpshuflw W:ymm, ymm/m256, imm8" , "op": "[RM ] VEX.256.F2.0F.WIG 70 /r ib"}, + {"any": "vpsignb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 08 /r"}, + {"any": "vpsignd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 0A /r"}, + {"any": "vpsignw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.WIG 09 /r"}, + {"any": "vpslld W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG F2 /r"}, + {"any": "vpslld W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 72 /6 ib"}, + {"any": "vpslldq W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 73 /7 ib"}, + {"any": "vpsllq W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG F3 /r"}, + {"any": "vpsllq W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 73 /6 ib"}, + {"any": "vpsllvd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 47 /r"}, + {"any": "vpsllvd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 47 /r"}, + {"any": "vpsllvq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W1 47 /r"}, + {"any": "vpsllvq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W1 47 /r"}, + {"any": "vpsllw W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG F1 /r"}, + {"any": "vpsllw W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 71 /6 ib"}, + {"any": "vpsrad W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG E2 /r"}, + {"any": "vpsrad W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 72 /4 ib"}, + {"any": "vpsravd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 46 /r"}, + {"any": "vpsravd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 46 /r"}, + {"any": "vpsraw W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG E1 /r"}, + {"any": "vpsraw W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 71 /4 ib"}, + {"any": "vpsrld W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG D2 /r"}, + {"any": "vpsrld W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 72 /2 ib"}, + {"any": "vpsrldq W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 73 /3 ib"}, + {"any": "vpsrlq W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG D3 /r"}, + {"any": "vpsrlq W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 73 /2 ib"}, + {"any": "vpsrlvd W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 45 /r"}, + {"any": "vpsrlvd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W0 45 /r"}, + {"any": "vpsrlvq W:xmm, xmm, xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W1 45 /r"}, + {"any": "vpsrlvq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F38.W1 45 /r"}, + {"any": "vpsrlw W:ymm, ymm, xmm/m128" , "op": "[RVM] VEX.256.66.0F.WIG D1 /r"}, + {"any": "vpsrlw W:ymm, ymm, imm8" , "op": "[VM ] VEX.256.66.0F.WIG 71 /2 ib"}, + {"any": "vpsubb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG F8 /r"}, + {"any": "vpsubd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG FA /r"}, + {"any": "vpsubq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG FB /r"}, + {"any": "vpsubsb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E8 /r"}, + {"any": "vpsubsw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG E9 /r"}, + {"any": "vpsubusb W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG D8 /r"}, + {"any": "vpsubusw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG D9 /r"}, + {"any": "vpsubw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG F9 /r"}, + {"any": "vpunpckhbw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 68 /r"}, + {"any": "vpunpckhdq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 6A /r"}, + {"any": "vpunpckhqdq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 6D /r"}, + {"any": "vpunpckhwd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 69 /r"}, + {"any": "vpunpcklbw W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 60 /r"}, + {"any": "vpunpckldq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 62 /r"}, + {"any": "vpunpcklqdq W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 6C /r"}, + {"any": "vpunpcklwd W:ymm, ymm, ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG 61 /r"}, + {"any": "vpxor W:ymm, ~ymm, ~ymm/m256" , "op": "[RVM] VEX.256.66.0F.WIG EF /r"} + ]}, + + {"category": "AVX SIMD", "ext": "F16C", "instructions": [ + {"any": "vcvtph2ps W:xmm, xmm[63:0]/m64" , "op": "[RM ] VEX.128.66.0F38.W0 13 /r"}, + {"any": "vcvtph2ps W:ymm, xmm/m128" , "op": "[RM ] VEX.256.66.0F38.W0 13 /r"}, + {"any": "vcvtps2ph W:xmm[63:0]/m64, xmm, imm8" , "op": "[MR ] VEX.128.66.0F3A.W0 1D /r ib"}, + {"any": "vcvtps2ph W:xmm/m128, ymm, imm8" , "op": "[MR ] VEX.256.66.0F3A.W0 1D /r ib"} + ]}, + + {"category": "AVX SIMD", "ext": "FMA", "instructions": [ + {"any": "vfmadd132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 98 /r"}, + {"any": "vfmadd132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 98 /r"}, + {"any": "vfmadd132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 99 /r"}, + {"any": "vfmadd132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 99 /r"}, + {"any": "vfmadd213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 A8 /r"}, + {"any": "vfmadd213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 A8 /r"}, + {"any": "vfmadd213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 A9 /r"}, + {"any": "vfmadd213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 A9 /r"}, + {"any": "vfmadd231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 B8 /r"}, + {"any": "vfmadd231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 B8 /r"}, + {"any": "vfmadd231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 B9 /r"}, + {"any": "vfmadd231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 B9 /r"}, + {"any": "vfmaddsub132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 96 /r"}, + {"any": "vfmaddsub132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 96 /r"}, + {"any": "vfmaddsub213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 A6 /r"}, + {"any": "vfmaddsub213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 A6 /r"}, + {"any": "vfmaddsub231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 B6 /r"}, + {"any": "vfmaddsub231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 B6 /r"}, + {"any": "vfmsub132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 9A /r"}, + {"any": "vfmsub132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 9A /r"}, + {"any": "vfmsub132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 9B /r"}, + {"any": "vfmsub132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 9B /r"}, + {"any": "vfmsub213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 AA /r"}, + {"any": "vfmsub213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 AA /r"}, + {"any": "vfmsub213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 AB /r"}, + {"any": "vfmsub213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 AB /r"}, + {"any": "vfmsub231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 BA /r"}, + {"any": "vfmsub231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 BA /r"}, + {"any": "vfmsub231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 BB /r"}, + {"any": "vfmsub231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 BB /r"}, + {"any": "vfmsubadd132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 97 /r"}, + {"any": "vfmsubadd132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 97 /r"}, + {"any": "vfmsubadd213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 A7 /r"}, + {"any": "vfmsubadd213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 A7 /r"}, + {"any": "vfmsubadd231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 B7 /r"}, + {"any": "vfmsubadd231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 B7 /r"}, + {"any": "vfnmadd132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 9C /r"}, + {"any": "vfnmadd132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 9C /r"}, + {"any": "vfnmadd132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 9D /r"}, + {"any": "vfnmadd132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 9D /r"}, + {"any": "vfnmadd213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 AC /r"}, + {"any": "vfnmadd213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 AC /r"}, + {"any": "vfnmadd213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 AD /r"}, + {"any": "vfnmadd213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 AD /r"}, + {"any": "vfnmadd231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 BC /r"}, + {"any": "vfnmadd231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 BC /r"}, + {"any": "vfnmadd231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 BD /r"}, + {"any": "vfnmadd231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 BD /r"}, + {"any": "vfnmsub132pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 9E /r"}, + {"any": "vfnmsub132ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 9E /r"}, + {"any": "vfnmsub132sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 9F /r"}, + {"any": "vfnmsub132ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 9F /r"}, + {"any": "vfnmsub213pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 AE /r"}, + {"any": "vfnmsub213ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 AE /r"}, + {"any": "vfnmsub213sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 AF /r"}, + {"any": "vfnmsub213ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 AF /r"}, + {"any": "vfnmsub231pd X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 BE /r"}, + {"any": "vfnmsub231ps X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 BE /r"}, + {"any": "vfnmsub231sd x:xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVM] VEX.LIG.66.0F38.W1 BF /r"}, + {"any": "vfnmsub231ss x:xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVM] VEX.LIG.66.0F38.W0 BF /r"} + ]}, + + {"category": "AVX SIMD", "ext": "FMA4", "deprecated": true, "instructions": [ + {"any": "vfmaddpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 69 /r /is4"}, + {"any": "vfmaddpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 69 /r /is4"}, + {"any": "vfmaddps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 68 /r /is4"}, + {"any": "vfmaddps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 68 /r /is4"}, + {"any": "vfmaddsd W:xmm[63:0], xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVSM] VEX.128.66.0F3A.W1 6b /r /is4"}, + {"any": "vfmaddsd W:xmm[63:0], xmm[63:0], xmm[63:0]/m64, xmm[63:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 6b /r /is4"}, + {"any": "vfmaddss W:xmm[31:0], xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVSM] VEX.128.66.0F3A.W1 6a /r /is4"}, + {"any": "vfmaddss W:xmm[31:0], xmm[31:0], xmm[31:0]/m32, xmm[31:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 6a /r /is4"}, + {"any": "vfmaddsubpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 5D /r /is4"}, + {"any": "vfmaddsubpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 5D /r /is4"}, + {"any": "vfmaddsubps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 5C /r /is4"}, + {"any": "vfmaddsubps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 5C /r /is4"}, + {"any": "vfmsubaddpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 5F /r /is4"}, + {"any": "vfmsubaddpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 5F /r /is4"}, + {"any": "vfmsubaddps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 5E /r /is4"}, + {"any": "vfmsubaddps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 5E /r /is4"}, + {"any": "vfmsubpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 6D /r /is4"}, + {"any": "vfmsubpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 6D /r /is4"}, + {"any": "vfmsubps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 6C /r /is4"}, + {"any": "vfmsubps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 6C /r /is4"}, + {"any": "vfmsubsd W:xmm[63:0], xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVSM] VEX.128.66.0F3A.W1 6F /r /is4"}, + {"any": "vfmsubsd W:xmm[63:0], xmm[63:0], xmm[63:0]/m64, xmm[63:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 6F /r /is4"}, + {"any": "vfmsubss W:xmm[31:0], xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVSM] VEX.128.66.0F3A.W1 6E /r /is4"}, + {"any": "vfmsubss W:xmm[31:0], xmm[31:0], xmm[31:0]/m32, xmm[31:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 6E /r /is4"}, + {"any": "vfnmaddpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 79 /r /is4"}, + {"any": "vfnmaddpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 79 /r /is4"}, + {"any": "vfnmaddps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 78 /r /is4"}, + {"any": "vfnmaddps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 78 /r /is4"}, + {"any": "vfnmaddsd W:xmm[63:0], xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVSM] VEX.128.66.0F3A.W1 7B /r /is4"}, + {"any": "vfnmaddsd W:xmm[63:0], xmm[63:0], xmm[63:0]/m64, xmm[63:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 7B /r /is4"}, + {"any": "vfnmaddss W:xmm[31:0], xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVSM] VEX.128.66.0F3A.W1 7A /r /is4"}, + {"any": "vfnmaddss W:xmm[31:0], xmm[31:0], xmm[31:0]/m32, xmm[31:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 7A /r /is4"}, + {"any": "vfnmsubpd W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 7D /r /is4"}, + {"any": "vfnmsubpd W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 7D /r /is4"}, + {"any": "vfnmsubps W:xy, xy, xy, xy/mxy" , "op": "[RVSM] VEX.Lxy.66.0F3A.W1 7C /r /is4"}, + {"any": "vfnmsubps W:xy, xy, xy/mxy, xy" , "op": "[RVMS] VEX.Lxy.66.0F3A.W0 7C /r /is4"}, + {"any": "vfnmsubsd W:xmm[63:0], xmm[63:0], xmm[63:0], xmm[63:0]/m64" , "op": "[RVSM] VEX.128.66.0F3A.W1 7F /r /is4"}, + {"any": "vfnmsubsd W:xmm[63:0], xmm[63:0], xmm[63:0]/m64, xmm[63:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 7F /r /is4"}, + {"any": "vfnmsubss W:xmm[31:0], xmm[31:0], xmm[31:0], xmm[31:0]/m32" , "op": "[RVSM] VEX.128.66.0F3A.W1 7E /r /is4"}, + {"any": "vfnmsubss W:xmm[31:0], xmm[31:0], xmm[31:0]/m32, xmm[31:0]" , "op": "[RVMS] VEX.128.66.0F3A.W0 7E /r /is4"} + ]}, + + {"category": "AVX SIMD", "ext": "XOP", "deprecated": true, "instructions": [ + {"any": "vfrczpd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 81 /r"}, + {"any": "vfrczpd W:ymm, ymm/m256" , "op": "[RM ] XOP.256.P0.MAP9.W0 81 /r"}, + {"any": "vfrczps W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 80 /r"}, + {"any": "vfrczps W:ymm, ymm/m256" , "op": "[RM ] XOP.256.P0.MAP9.W0 80 /r"}, + {"any": "vfrczsd W:xmm[63:0], xmm[63:0]/m64" , "op": "[RM ] XOP.128.P0.MAP9.W0 83 /r"}, + {"any": "vfrczss W:xmm[31:0], xmm[31:0]/m32" , "op": "[RM ] XOP.128.P0.MAP9.W0 82 /r"}, + {"any": "vpcmov W:xmm, xmm, xmm, xmm/m128" , "op": "[RVSM]XOP.128.P0.MAP8.W1 A2 /r /is4"}, + {"any": "vpcmov W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 A2 /r /is4"}, + {"any": "vpcmov W:ymm, ymm, ymm, ymm/m256" , "op": "[RVSM]XOP.256.P0.MAP8.W1 A2 /r /is4"}, + {"any": "vpcmov W:ymm, ymm, ymm/m256, ymm" , "op": "[RVMS]XOP.256.P0.MAP8.W0 A2 /r /is4"}, + {"any": "vpcomb W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 CC /r ib"}, + {"any": "vpcomd W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 CE /r ib"}, + {"any": "vpcomq W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 CF /r ib"}, + {"any": "vpcomub W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 EC /r ib"}, + {"any": "vpcomud W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 EE /r ib"}, + {"any": "vpcomuq W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 EF /r ib"}, + {"any": "vpcomuw W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 ED /r ib"}, + {"any": "vpcomw W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] XOP.128.P0.MAP8.W0 CD /r ib"}, + {"any": "vpermil2pd W:xmm, xmm, xmm/m128, xmm, imm4" , "op": "[RVMS]VEX.128.66.0F3A.W0 49 /r /is4"}, + {"any": "vpermil2pd W:xmm, xmm, xmm, xmm/m128, imm4" , "op": "[RVSM]VEX.128.66.0F3A.W1 49 /r /is4"}, + {"any": "vpermil2pd W:ymm, ymm, ymm/m256, ymm, imm4" , "op": "[RVMS]VEX.256.66.0F3A.W0 49 /r /is4"}, + {"any": "vpermil2pd W:ymm, ymm, ymm, ymm/m256, imm4" , "op": "[RVSM]VEX.256.66.0F3A.W1 49 /r /is4"}, + {"any": "vpermil2ps W:xmm, xmm, xmm/m128, xmm, imm4" , "op": "[RVMS]VEX.128.66.0F3A.W0 48 /r /is4"}, + {"any": "vpermil2ps W:xmm, xmm, xmm, xmm/m128, imm4" , "op": "[RVSM]VEX.128.66.0F3A.W1 48 /r /is4"}, + {"any": "vpermil2ps W:ymm, ymm, ymm/m256, ymm, imm4" , "op": "[RVMS]VEX.256.66.0F3A.W0 48 /r /is4"}, + {"any": "vpermil2ps W:ymm, ymm, ymm, ymm/m256, imm4" , "op": "[RVSM]VEX.256.66.0F3A.W1 48 /r /is4"}, + {"any": "vphaddbd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 C2 /r"}, + {"any": "vphaddbq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 C3 /r"}, + {"any": "vphaddbw W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 C1 /r"}, + {"any": "vphadddq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 CB /r"}, + {"any": "vphaddubd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 D2 /r"}, + {"any": "vphaddubq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 D3 /r"}, + {"any": "vphaddubw W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 D1 /r"}, + {"any": "vphaddudq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 DB /r"}, + {"any": "vphadduwd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 D6 /r"}, + {"any": "vphadduwq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 D7 /r"}, + {"any": "vphaddwd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 C6 /r"}, + {"any": "vphaddwq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 C7 /r"}, + {"any": "vphsubbw W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 E1 /r"}, + {"any": "vphsubdq W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 E3 /r"}, + {"any": "vphsubwd W:xmm, xmm/m128" , "op": "[RM ] XOP.128.P0.MAP9.W0 E2 /r"}, + {"any": "vpmacsdd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 9E /r /is4"}, + {"any": "vpmacsdqh W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 9F /r /is4"}, + {"any": "vpmacsdql W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 97 /r /is4"}, + {"any": "vpmacssdd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 8E /r /is4"}, + {"any": "vpmacssdqh W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 8F /r /is4"}, + {"any": "vpmacssdql W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 87 /r /is4"}, + {"any": "vpmacsswd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 86 /r /is4"}, + {"any": "vpmacssww W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 85 /r /is4"}, + {"any": "vpmacswd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 96 /r /is4"}, + {"any": "vpmacsww W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 95 /r /is4"}, + {"any": "vpmadcsswd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 A6 /r /is4"}, + {"any": "vpmadcswd W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 B6 /r /is4"}, + {"any": "vpperm W:xmm, xmm, xmm, xmm/m128" , "op": "[RVSM]XOP.128.P0.MAP8.W1 A3 /r /is4"}, + {"any": "vpperm W:xmm, xmm, xmm/m128, xmm" , "op": "[RVMS]XOP.128.P0.MAP8.W0 A3 /r /is4"}, + {"any": "vprotb W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 90 /r"}, + {"any": "vprotb W:xmm, xmm/m128, imm8" , "op": "[RM ] XOP.128.P0.MAP8.W0 C0 /r ib"}, + {"any": "vprotb W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 90 /r"}, + {"any": "vprotd W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 92 /r"}, + {"any": "vprotd W:xmm, xmm/m128, imm8" , "op": "[RM ] XOP.128.P0.MAP8.W0 C2 /r ib"}, + {"any": "vprotd W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 92 /r"}, + {"any": "vprotq W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 93 /r"}, + {"any": "vprotq W:xmm, xmm/m128, imm8" , "op": "[RM ] XOP.128.P0.MAP8.W0 C3 /r ib"}, + {"any": "vprotq W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 93 /r"}, + {"any": "vprotw W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 91 /r"}, + {"any": "vprotw W:xmm, xmm/m128, imm8" , "op": "[RM ] XOP.128.P0.MAP8.W0 C1 /r ib"}, + {"any": "vprotw W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 91 /r"}, + {"any": "vpshab W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 98 /r"}, + {"any": "vpshab W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 98 /r"}, + {"any": "vpshad W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 9A /r"}, + {"any": "vpshad W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 9A /r"}, + {"any": "vpshaq W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 9B /r"}, + {"any": "vpshaq W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 9B /r"}, + {"any": "vpshaw W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 99 /r"}, + {"any": "vpshaw W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 99 /r"}, + {"any": "vpshlb W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 94 /r"}, + {"any": "vpshlb W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 94 /r"}, + {"any": "vpshld W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 96 /r"}, + {"any": "vpshld W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 96 /r"}, + {"any": "vpshlq W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 97 /r"}, + {"any": "vpshlq W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 97 /r"}, + {"any": "vpshlw W:xmm, xmm, xmm/m128" , "op": "[RVM] XOP.128.P0.MAP9.W1 95 /r"}, + {"any": "vpshlw W:xmm, xmm/m128, xmm" , "op": "[RMV] XOP.128.P0.MAP9.W0 95 /r"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX PCLMULQDQ", "instructions": [ + {"any": "vpclmulqdq W:xmm, xmm, xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.WIG 44 /r ib"} + ]}, + + {"category": "AVX SIMD", "ext": "VPCLMULQDQ", "instructions": [ + {"any": "vpclmulqdq W:ymm, ymm, ymm/m256, imm8" , "op": "[RVM] VEX.256.66.0F3A.WIG 44 /r ib"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX_IFMA", "instructions": [ + {"any": "vpmadd52huq X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 B5 /r"}, + {"any": "vpmadd52luq X:xy, xy, xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W1 B4 /r"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX_NE_CONVERT", "instructions": [ + {"any": "vbcstnebf162ps W:xy, m16" , "op": "[RM ] VEX.Lxy.F3.0F38.W0 B1 !(11):rrr:bbb"}, + {"any": "vbcstnesh2ps W:xy, m16" , "op": "[RM ] VEX.Lxy.66.0F38.W0 B1 !(11):rrr:bbb"}, + {"any": "vcvtneebf162ps W:xy, mxy" , "op": "[RM ] VEX.Lxy.F3.0F38.W0 B0 !(11):rrr:bbb"}, + {"any": "vcvtneeph2ps W:xy, mxy" , "op": "[RM ] VEX.Lxy.66.0F38.W0 B0 !(11):rrr:bbb"}, + {"any": "vcvtneobf162ps W:xy, mxy" , "op": "[RM ] VEX.Lxy.F2.0F38.W0 B0 !(11):rrr:bbb"}, + {"any": "vcvtneoph2ps W:xy, mxy" , "op": "[RM ] VEX.Lxy.NP.0F38.W0 B0 !(11):rrr:bbb"}, + {"any": "vcvtneps2bf16 W:xmm[63:0], xmm/m128" , "op": "[RM ] VEX.128.F3.0F38.W0 72 /r"}, + {"any": "vcvtneps2bf16 W:xmm, ymm/m256" , "op": "[RM ] VEX.256.F3.0F38.W0 72 /r"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX SHA512", "instructions": [ + {"any": "vsha512msg1 X:ymm, R:xmm" , "op": "[RM ] VEX.256.F2.0F38.W0 CC 11:rrr:bbb"}, + {"any": "vsha512msg2 X:ymm, R:ymm" , "op": "[RM ] VEX.256.F2.0F38.W0 CD 11:rrr:bbb"}, + {"any": "vsha512rnds2 X:ymm, R:ymm, R:xmm" , "op": "[RVM] VEX.256.F2.0F38.W0 CB 11:rrr:bbb"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX SM3", "instructions": [ + {"any": "vsm3msg1 X:xmm, R:xmm, R:xmm/m128" , "op": "[RVM] VEX.128.NP.0F38.W0 DA /r"}, + {"any": "vsm3msg2 X:xmm, R:xmm, R:xmm/m128" , "op": "[RVM] VEX.128.66.0F38.W0 DA /r"}, + {"any": "vsm3rnds2 X:xmm, R:xmm, R:xmm/m128, imm8" , "op": "[RVM] VEX.128.66.0F3A.W0 DE /r ib"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX SM4", "instructions": [ + {"any": "vsm4key4 W:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F3.0F38.W0 DA /r"}, + {"any": "vsm4rnds4 W:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F38.W0 DA /r"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX10_2 SM4", "instructions": [ + {"any": "vsm4key4 W:xyz, R:xyz, R:xyz/mxyz" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 DA /r"}, + {"any": "vsm4rnds4 W:xyz, R:xyz, R:xyz/mxyz" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 DA /r"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX_VNNI", "instructions": [ + {"any": "vpdpbusd X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 50 /r"}, + {"any": "vpdpbusds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 51 /r"}, + {"any": "vpdpwssd X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 52 /r"}, + {"any": "vpdpwssds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 53 /r"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX_VNNI_INT8", "instructions": [ + {"any": "vpdpbssd X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F38.W0 50 /r"}, + {"any": "vpdpbssds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F2.0F38.W0 51 /r"}, + {"any": "vpdpbsud X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F3.0F38.W0 50 /r"}, + {"any": "vpdpbsuds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F3.0F38.W0 51 /r"}, + {"any": "vpdpbuud X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F38.W0 50 /r"}, + {"any": "vpdpbuuds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F38.W0 51 /r"} + ]}, + + {"category": "AVX SIMD", "ext": "AVX_VNNI_INT16", "instructions": [ + {"any": "vpdpwsud X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F3.0F38.W0 D2 /r"}, + {"any": "vpdpwsuds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.F3.0F38.W0 D3 /r"}, + {"any": "vpdpwusd X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 D2 /r"}, + {"any": "vpdpwusds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.66.0F38.W0 D3 /r"}, + {"any": "vpdpwuud X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F38.W0 D2 /r"}, + {"any": "vpdpwuuds X:xy, R:xy, R:xy/mxy" , "op": "[RVM] VEX.Lxy.NP.0F38.W0 D3 /r"} + ]}, + + {"category": "AVX512 MASK", "ext": "AVX512_F", "instructions": [ + {"any": "kandnw W:k[15:0], k[15:0], k[15:0]" , "op": "[RVM] VEX.L1.0F.W0 42 /r"}, + {"any": "kandw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "[RVM] VEX.L1.0F.W0 41 /r"}, + {"any": "kmovw W:k[15:0], k[15:0]/m16" , "op": "[RM ] VEX.L0.0F.W0 90 /r"}, + {"any": "kmovw W:k[15:0], r32[15:0]" , "op": "[RM ] VEX.L0.0F.W0 92 /r"}, + {"any": "kmovw W:m16, k[15:0]" , "op": "[MR ] VEX.L0.0F.W0 91 /r"}, + {"any": "kmovw W:r32[15:0], k[15:0]" , "op": "[RM ] VEX.L0.0F.W0 93 /r"}, + {"any": "knotw W:k[15:0], k[15:0]" , "op": "[RM ] VEX.L0.0F.W0 44 /r"}, + {"any": "kortestw R:~k[15:0], ~k[15:0]" , "op": "[RM ] VEX.L0.0F.W0 98 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, + {"any": "korw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "[RVM] VEX.L1.0F.W0 45 /r"}, + {"any": "kshiftlw W:k[15:0], k[15:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W1 32 /r ib"}, + {"any": "kshiftrw W:k[15:0], k[15:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W1 30 /r ib"}, + {"any": "kunpckbw W:k[15:0], k[7:0], k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 4B /r"}, + {"any": "kxnorw W:k[15:0], k[15:0], k[15:0]" , "op": "[RVM] VEX.L1.0F.W0 46 /r"}, + {"any": "kxorw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "[RVM] VEX.L1.0F.W0 47 /r"} + ]}, + + {"category": "AVX512 MASK", "ext": "AVX512_DQ", "instructions": [ + {"any": "kaddb W:k[7:0], ~k[7:0], ~k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 4A /r"}, + {"any": "kaddw W:k[15:0], ~k[15:0], ~k[15:0]" , "op": "[RVM] VEX.L1.NP.0F.W0 4A /r"}, + {"any": "kandb W:k[7:0], ~k[7:0], ~k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 41 /r"}, + {"any": "kandnb W:k[7:0], k[7:0], k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 42 /r"}, + {"any": "kmovb W:k[7:0], k[7:0]/m8" , "op": "[RM ] VEX.L0.66.0F.W0 90 /r"}, + {"any": "kmovb W:k[7:0], r32[7:0]" , "op": "[RM ] VEX.L0.66.0F.W0 92 /r"}, + {"any": "kmovb W:m8, k[7:0]" , "op": "[MR ] VEX.L0.66.0F.W0 91 /r"}, + {"any": "kmovb W:r32[7:0], k[7:0]" , "op": "[RM ] VEX.L0.66.0F.W0 93 /r"}, + {"any": "knotb W:k[7:0], k[7:0]" , "op": "[RM ] VEX.L0.66.0F.W0 44 /r"}, + {"any": "korb W:k[7:0], ~k[7:0], ~k[7:0]" , "op": "[RVM] VEX.L1.66.0F.W0 45 /r"}, + {"any": "kortestb R:~k[7:0], ~k[7:0]" , "op": "[RM ] VEX.L0.66.0F.W0 98 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=W"}, + {"any": "kshiftlb W:k[7:0], k[7:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W0 32 /r ib"}, + {"any": "kshiftrb W:k[7:0], k[7:0], imm8" , "op": "[RM ] VEX.L0.66.0F3A.W0 30 /r ib"}, + {"any": "ktestb R:~k[7:0], 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, "vl": "xy"}, + {"any": "vcvtudq2ps W:xyz {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.F2.0F.W0 7A /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtusi2sd W:xmm, xmm[127:64], ry/my {er}" , "op": "[RVM] EVEX.LIG.F2.0F.Wy 7B /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcvtusi2ss W:xmm, xmm[127:32], ry/my {er}" , "op": "[RVM] EVEX.LIG.F3.0F.Wy 7B /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vdivpd W:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F.W1 5E /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vdivps W:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.NP.0F.W0 5E /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vdivsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 5E /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vdivss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 5E /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vexpandpd W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W1 88 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vexpandps W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W0 88 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vextractf32x4 W:xmm/m128 {kz}, ymm, imm8" , "op": "[MR ] EVEX.256.66.0F3A.W0 19 /r ib" , "tt": "t4" , "vl": "xy"}, + {"any": "vextractf32x4 W:xmm/m128 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W0 19 /r ib" , "tt": "t4" , "vl": "xy"}, + {"any": "vextractf64x4 W:ymm/m256 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W1 1B /r ib" , "tt": "t4" , "vl": "xy"}, + {"any": "vextracti32x4 W:xmm/m128 {kz}, ymm, imm8" , "op": "[MR ] EVEX.256.66.0F3A.W0 39 /r ib" , "tt": "t4" , "vl": "xy"}, + {"any": "vextracti32x4 W:xmm/m128 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W0 39 /r ib" , "tt": "t4" , "vl": "xy"}, + {"any": "vextracti64x4 W:ymm/m256 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W1 3B /r ib" , "tt": "t4" , "vl": "xy"}, + {"any": "vextractps W:r32[31:0]/m32, xmm, imm8" , "op": "[MR ] EVEX.128.66.0F3A.WIG 17 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vfixupimmpd X:xyz {kz}, xyz, xyz/mxyz/b64, imm8 {sae}" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 54 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vfixupimmps X:xyz {kz}, xyz, xyz/mxyz/b32, imm8 {sae}" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 54 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vfixupimmsd X:xmm {kz},xmm[127:64],xmm[63:0]/m64,imm8 {sae}", "op": "[RVM] EVEX.LIG.66.0F3A.W1 55 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vfixupimmss X:xmm {kz},xmm[127:32],xmm[31:0]/m32,imm8 {sae}", "op": "[RVM] EVEX.LIG.66.0F3A.W0 55 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmadd132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 98 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmadd132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 98 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmadd132sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 99 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmadd132ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 99 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmadd213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 A8 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmadd213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 A8 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmadd213sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 A9 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmadd213ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 A9 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmadd231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 B8 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmadd231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 B8 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmadd231sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 B9 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmadd231ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 B9 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmaddsub132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 96 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmaddsub132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 96 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmaddsub213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 A6 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmaddsub213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 A6 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmaddsub231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 B6 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmaddsub231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 B6 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsub132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 9A /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsub132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 9A /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsub132sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 9B /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmsub132ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 9B /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmsub213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 AA /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsub213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 AA /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsub213sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 AB /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmsub213ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 AB /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmsub231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 BA /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsub231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 BA /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsub231sd x:xmm[63:0] {kz}, xmm[63:0], xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 BB /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmsub231ss x:xmm[31:0] {kz}, xmm[31:0], xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 BB /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmsubadd132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 97 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsubadd132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 97 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsubadd213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 A7 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsubadd213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 A7 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsubadd231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 B7 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsubadd231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 B7 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmadd132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 9C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmadd132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 9C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmadd132sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 9D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmadd132ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 9D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmadd213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 AC /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmadd213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 AC /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmadd213sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 AD /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmadd213ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 AD /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmadd231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 BC /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmadd231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 BC /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmadd231sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 BD /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmadd231ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 BD /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmsub132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 9E /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmsub132ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 9E /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmsub132sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 9F /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmsub132ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 9F /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmsub213pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 AE /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmsub213ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 AE /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmsub213sd x:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 AF /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmsub213ss x:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 AF /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmsub231pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 BE /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmsub231ps X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 BE /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmsub231sd X:xmm[63:0] {kz}, xmm[63:0],xmm[63:0]/m64 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W1 BF /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmsub231ss X:xmm[31:0] {kz}, xmm[31:0],xmm[31:0]/m32 {er}", "op": "[RVM] EVEX.LIG.66.0F38.W0 BF /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vgatherdpd X:xmm {k}, vm32x" , "op": "[RM ] EVEX.128.66.0F38.W1 92 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgatherdpd X:ymm {k}, vm32x" , "op": "[RM ] EVEX.256.66.0F38.W1 92 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgatherdpd X:zmm {k}, vm32y" , "op": "[RM ] EVEX.512.66.0F38.W1 92 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgatherdps X:xmm {k}, vm32x" , "op": "[RM ] EVEX.128.66.0F38.W0 92 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgatherdps X:ymm {k}, vm32y" , "op": "[RM ] EVEX.256.66.0F38.W0 92 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgatherdps X:zmm {k}, vm32z" , "op": "[RM ] EVEX.512.66.0F38.W0 92 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgatherqpd X:xmm {k}, vm64x" , "op": "[RM ] EVEX.128.66.0F38.W1 93 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgatherqpd X:ymm {k}, vm64y" , "op": "[RM ] EVEX.256.66.0F38.W1 93 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgatherqpd X:zmm {k}, vm64z" , "op": "[RM ] EVEX.512.66.0F38.W1 93 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgatherqps X:xmm {k}, vm64x" , "op": "[RM ] EVEX.128.66.0F38.W0 93 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgatherqps X:xmm {k}, vm64y" , "op": "[RM ] EVEX.256.66.0F38.W0 93 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgatherqps X:ymm {k}, vm64z" , "op": "[RM ] EVEX.512.66.0F38.W0 93 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vgetexppd W:xyz {kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.66.0F38.W1 42 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vgetexpps W:xyz {kz}, xyz/mxyz/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.0F38.W0 42 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vgetexpsd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.66.0F38.W1 43 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vgetexpss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.66.0F38.W0 43 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vgetmantpd W:xyz {kz}, xyz/mxyz/b64, imm8 {sae}" , "op": "[RM ] EVEX.xyz.66.0F3A.W1 26 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vgetmantps W:xyz {kz}, xyz/mxyz/b32, imm8 {sae}" , "op": "[RM ] EVEX.xyz.66.0F3A.W0 26 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vgetmantsd W:xmm {kz}, xmm[127:64],xmm[63:0]/m64,imm8 {sae}", "op": "[RM ] EVEX.LIG.66.0F3A.W1 27 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vgetmantss W:xmm {kz}, xmm[127:32],xmm[31:0]/m32,imm8 {sae}", "op": "[RM ] EVEX.LIG.66.0F3A.W0 27 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vinsertf32x4 W:ymm {kz}, ymm, xmm/m128, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W0 18 /r ib" , "tt": "t4" , "vl": "xy"}, + {"any": "vinsertf32x4 W:zmm {kz}, zmm, xmm/m128, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 18 /r ib" , "tt": "t4" , "vl": "xy"}, + {"any": "vinsertf64x4 W:zmm {kz}, zmm, ymm/m256, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 1A /r ib" , "tt": "t4" , "vl": "xy"}, + {"any": "vinserti32x4 W:ymm {kz}, ymm, xmm/m128, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W0 38 /r ib" , "tt": "t4" , "vl": "xy"}, + {"any": "vinserti32x4 W:zmm {kz}, zmm, xmm/m128, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 38 /r ib" , "tt": "t4" , "vl": "xy"}, + {"any": "vinserti64x4 W:zmm {kz}, zmm, ymm/m256, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 3A /r ib" , "tt": "t2" , "vl": "xy"}, + {"any": "vinsertps W:xmm, xmm, xmm[31:0]/m32, imm8" , "op": "[RVM] EVEX.128.66.0F3A.W0 21 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vmaxpd W:xyz {kz}, xyz, xyz/mxyz/b64 {sae}" , "op": "[RVM] EVEX.xyz.66.0F.W1 5F /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vmaxps W:xyz {kz}, xyz, xyz/mxyz/b32 {sae}" , "op": "[RVM] EVEX.xyz.NP.0F.W0 5F /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vmaxsd W:xmm {kz}, xmm, xmm[63:0]/m64 {sae}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 5F /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmaxss W:xmm {kz}, xmm, xmm[31:0]/m32 {sae}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 5F /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vminpd W:xyz {kz}, xyz, xyz/mxyz/b64 {sae}" , "op": "[RVM] EVEX.xyz.66.0F.W1 5D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vminps W:xyz {kz}, xyz, xyz/mxyz/b32 {sae}" , "op": "[RVM] EVEX.xyz.NP.0F.W0 5D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vminsd W:xmm {kz}, xmm, xmm[63:0]/m64 {sae}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 5D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vminss W:xmm {kz}, xmm, xmm[31:0]/m32 {sae}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 5D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovapd W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F.W1 28 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovapd W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W1 29 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovaps W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.NP.0F.W0 28 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovaps W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.NP.0F.W0 29 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovd W:r32/m32, xmm[31:0]" , "op": "[MR ] EVEX.128.66.0F.W0 7E /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovd W:xmm[31:0], r32/m32" , "op": "[RM ] EVEX.128.66.0F.W0 6E /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovddup W:xmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.128.F2.0F.W1 12 /r" , "tt": "movddup", "vl": "xy"}, + {"any": "vmovddup W:ymm {kz}, ymm/m256" , "op": "[RM ] EVEX.256.F2.0F.W1 12 /r" , "tt": "movddup", "vl": "xy"}, + {"any": "vmovddup W:zmm {kz}, zmm/m512" , "op": "[RM ] EVEX.512.F2.0F.W1 12 /r" , "tt": "movddup", "vl": "xy"}, + {"any": "vmovdqa32 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F.W0 6F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovdqa32 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W0 7F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovdqa64 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F.W1 6F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovdqa64 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W1 7F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovdqu32 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.F3.0F.W0 6F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovdqu32 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F.W0 7F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovdqu64 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.F3.0F.W1 6F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovdqu64 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F.W1 7F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovhlps W:xmm, xmm[127:64], xmm[127:64]" , "op": "[RVM] EVEX.128.NP.0F.W0 12 /r" , "tt": "none" , "vl": "no"}, + {"any": "vmovhpd W:m64, xmm[127:64]" , "op": "[MR ] EVEX.128.66.0F.W1 17 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovhpd W:xmm, xmm[63:0], m64" , "op": "[RVM] EVEX.128.66.0F.W1 16 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovhps W:m64, xmm[127:64]" , "op": "[MR ] EVEX.128.NP.0F.W0 17 /r" , "tt": "t2" , "vl": "no"}, + {"any": "vmovhps W:xmm, xmm[63:0], m64" , "op": "[RVM] EVEX.128.NP.0F.W0 16 /r" , "tt": "t2" , "vl": "no"}, + {"any": "vmovlhps W:xmm, xmm[63:0], xmm[63:0]" , "op": "[RVM] EVEX.128.NP.0F.W0 16 /r" , "tt": "none" , "vl": "no"}, + {"any": "vmovlpd W:m64, xmm[63:0]" , "op": "[MR ] EVEX.128.66.0F.W1 13 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovlpd W:xmm, xmm[127:64], m64" , "op": "[RVM] EVEX.128.66.0F.W1 12 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovlps W:m64, xmm[63:0]" , "op": "[MR ] EVEX.128.NP.0F.W0 13 /r" , "tt": "t2" , "vl": "no"}, + {"any": "vmovlps W:xmm, xmm[127:64], m64" , "op": "[RVM] EVEX.128.NP.0F.W0 12 /r" , "tt": "t2" , "vl": "no"}, + {"any": "vmovntdq W:mxyz, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W0 E7 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovntdqa W:xyz, mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W0 2A /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovntpd W:mxyz, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W1 2B /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovntps W:mxyz, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W0 2B /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovq W:r64/m64, xmm[63:0]" , "op": "[MR ] EVEX.128.66.0F.W1 7E /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovq W:xmm[63:0], r64/m64" , "op": "[RM ] EVEX.128.66.0F.W1 6E /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovq W:xmm[63:0], xmm[63:0]/m64" , "op": "[RM ] EVEX.128.F3.0F.W1 7E /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovq W:xmm[63:0]/m64, xmm[63:0]" , "op": "[MR ] EVEX.128.66.0F.W1 D6 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovsd W:m64, xmm[63:0]" , "op": "[MR ] EVEX.LIG.F2.0F.W1 11 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovsd W:xmm[63:0] {kz}, m64" , "op": "[MR ] EVEX.LIG.F2.0F.W1 10 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovsd W:xmm {kz}, xmm[127:64], xmm[63:0]" , "op": "[MVR] EVEX.LIG.F2.0F.W1 11 /r" , "tt": "none" , "vl": "no"}, + {"any": "vmovsd W:xmm {kz}, xmm[127:64], xmm[63:0]" , "op": "[RVM] EVEX.LIG.F2.0F.W1 10 /r" , "tt": "none" , "vl": "no"}, + {"any": "vmovshdup W:xyz {kz}, xyz/mxyz" , "op": "[RVM] EVEX.xyz.F3.0F.W0 16 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovsldup W:xyz {kz}, xyz/mxyz" , "op": "[RVM] EVEX.xyz.F3.0F.W0 12 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovss W:m32, xmm[31:0]" , "op": "[MR ] EVEX.LIG.F3.0F.W0 11 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovss W:xmm[31:0] {kz}, m32" , "op": "[MR ] EVEX.LIG.F3.0F.W0 10 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovss W:xmm {kz}, xmm[127:32], xmm[31:0]" , "op": "[MVR] EVEX.LIG.F3.0F.W0 11 /r" , "tt": "none" , "vl": "no"}, + {"any": "vmovss W:xmm {kz}, xmm[127:32], xmm[31:0]" , "op": "[RVM] EVEX.LIG.F3.0F.W0 10 /r" , "tt": "none" , "vl": "no"}, + {"any": "vmovupd W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F.W1 10 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovupd W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F.W1 11 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovups W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.0F.W0 10 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovups W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.0F.W0 11 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmulpd W:xyz {kz}, ~xyz, ~xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F.W1 59 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vmulps W:xyz {kz}, ~xyz, ~xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.0F.W0 59 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vmulsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 59 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmulss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 59 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vpabsd W:xyz {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 1E /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpabsq W:xyz {kz}, xyz/mxyz/b64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 1F /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpaddd W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 FE /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpaddq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 D4 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpandd W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 DB /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpandnd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 DF /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpandnq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 DF /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpandq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 DB /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpblendmd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 64 /r" , "tt": "fv" , "vl": "xy", "k": "blend"}, + {"any": "vpblendmq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 64 /r" , "tt": "fv" , "vl": "xy", "k": "blend"}, + {"any": "vpbroadcastd W:xyz {kz}, r32[31:0]" , "op": "[RM ] EVEX.xyz.66.0F38.W0 7C /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpbroadcastd W:xyz {kz}, xmm[31:0]/m32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 58 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpbroadcastq W:xyz {kz}, r64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 7C /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpbroadcastq W:xyz {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 59 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpcmpd W:k {k}, xyz, xyz/mxyz/b32, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 1F /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpeqd W:k {k}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 76 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpeqq W:k {k}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 29 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpgtd W:k {k}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 66 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpgtq W:k {k}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 37 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpq W:k {k}, xyz, xyz/mxyz/b64, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 1F /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpud W:k {k}, xyz, xyz/mxyz/b32, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 1E /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpuq W:k {k}, xyz, xyz/mxyz/b64, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 1E /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcompressd W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F38.W0 8B /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpcompressq W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.66.0F38.W1 8B /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpermd W:ymm {kz}, ymm, ymm/m256/b32" , "op": "[RVM] EVEX.256.66.0F38.W0 36 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermd W:zmm {kz}, zmm, zmm/m512/b32" , "op": "[RVM] EVEX.512.66.0F38.W0 36 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermi2d X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 76 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermi2pd W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 77 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermi2ps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 77 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermi2q X:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 76 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermilpd W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 0D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermilpd W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W1 05 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermilps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 0C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermilps W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W0 04 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermpd W:ymm {kz}, ymm, ymm/m256/b64" , "op": "[RVM] EVEX.256.66.0F38.W1 16 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermpd W:zmm {kz}, zmm, zmm/m512/b64" , "op": "[RVM] EVEX.512.66.0F38.W1 16 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermpd W:ymm {kz}, ymm/m256/b64, imm8" , "op": "[RM ] EVEX.256.66.0F3A.W1 01 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermpd W:zmm {kz}, zmm/m512/b64, imm8" , "op": "[RM ] EVEX.512.66.0F3A.W1 01 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermps W:ymm {kz}, ymm, ymm/m256/b32" , "op": "[RVM] EVEX.256.66.0F38.W0 16 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermps W:zmm {kz}, zmm, zmm/m512/b32" , "op": "[RVM] EVEX.512.66.0F38.W0 16 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpermq W:ymm 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"[RM ] EVEX.xyz.66.0F38.W0 89 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpexpandq W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W1 89 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherdd X:xmm {k}, vm32x" , "op": "[RM ] EVEX.128.66.0F38.W0 90" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherdd X:ymm {k}, vm32y" , "op": "[RM ] EVEX.256.66.0F38.W0 90" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherdd X:zmm {k}, vm32z" , "op": "[RM ] EVEX.512.66.0F38.W0 90" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherdq X:xmm {k}, vm32x" , "op": "[RM ] EVEX.128.66.0F38.W1 90" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherdq X:ymm {k}, vm32x" , "op": "[RM ] EVEX.256.66.0F38.W1 90" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherdq X:zmm {k}, vm32y" , "op": "[RM ] EVEX.512.66.0F38.W1 90" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherqd X:xmm {k}, vm64x" , "op": "[RM ] EVEX.128.66.0F38.W0 91" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherqd X:xmm {k}, vm64y" , "op": "[RM ] EVEX.256.66.0F38.W0 91" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherqd X:ymm {k}, vm64z" , "op": "[RM ] EVEX.512.66.0F38.W0 91" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherqq X:xmm {k}, vm64x" , "op": "[RM ] EVEX.128.66.0F38.W1 91" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherqq X:ymm {k}, vm64y" , "op": "[RM ] EVEX.256.66.0F38.W1 91" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpgatherqq X:zmm {k}, vm64z" , "op": "[RM ] EVEX.512.66.0F38.W1 91" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpmaxsd W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 3D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpmaxsq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 3D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpmaxud W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 3F /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpmaxuq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 3F /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpminsd W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 39 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpminsq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 39 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpminud W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 3B /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpminuq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 3B /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpmovdb W:xxx/mxxx {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 31 /r" , "tt": "qvm" , "vl": "xy"}, + {"any": "vpmovdw W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 33 /r" , "tt": "hvm" , "vl": "xy"}, + {"any": "vpmovqb W:xmm[15:0]/m16 {kz}, xmm" , "op": "[MR ] EVEX.128.F3.0F38.W0 32 /r" , "tt": "ovm" , "vl": "xy"}, + {"any": "vpmovqb W:xmm[31:0]/m32 {kz}, ymm" , "op": "[MR ] EVEX.256.F3.0F38.W0 32 /r" , "tt": "ovm" , "vl": "xy"}, + {"any": "vpmovqb W:xmm[63:0]/m64 {kz}, zmm" , "op": "[MR ] EVEX.512.F3.0F38.W0 32 /r" , "tt": "ovm" , "vl": "xy"}, + {"any": "vpmovqd W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 35 /r" , "tt": "hvm" , "vl": "xy"}, + {"any": "vpmovqw W:xxx/mxxx {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 34 /r" , "tt": "qvm" , "vl": "xy"}, + {"any": "vpmovsdb W:xxx/mxxx {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 21 /r" , "tt": "qvm" , "vl": "xy"}, + {"any": "vpmovsdw W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 23 /r" , "tt": "hvm" , "vl": "xy"}, + {"any": "vpmovsqb W:xmm[15:0]/m16 {kz}, xmm" , "op": "[MR ] EVEX.128.F3.0F38.W0 22 /r" , "tt": "ovm" , "vl": "xy"}, + {"any": "vpmovsqb W:xmm[31:0]/m32 {kz}, ymm" , "op": "[MR ] EVEX.256.F3.0F38.W0 22 /r" , "tt": "ovm" , "vl": "xy"}, + {"any": "vpmovsqb W:xmm[63:0]/m64 {kz}, zmm" , "op": "[MR ] EVEX.512.F3.0F38.W0 22 /r" , "tt": "ovm" , "vl": "xy"}, + {"any": "vpmovsqd W:xxy/mxxy {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 25 /r" , "tt": "hvm" , "vl": "xy"}, + {"any": "vpmovsqw W:xxx/mxxx {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 24 /r" , "tt": "qvm" , "vl": "xy"}, + {"any": "vpmovsxbd W:xyz {kz}, xxx/mxxx" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 21 /r" , "tt": "qvm" , "vl": "xy"}, + {"any": "vpmovsxbq W:xmm {kz}, xmm[15:0]/m16" , "op": "[RM ] EVEX.128.66.0F38.WIG 22 /r" , "tt": "ovm" , "vl": "xy"}, + {"any": "vpmovsxbq W:ymm {kz}, xmm[31:0]/m32" , "op": "[RM ] EVEX.256.66.0F38.WIG 22 /r" , "tt": "ovm" , "vl": "xy"}, + {"any": "vpmovsxbq W:zmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.512.66.0F38.WIG 22 /r" , "tt": "ovm" , "vl": "xy"}, + {"any": "vpmovsxdq W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.66.0F38.W0 25 /r" , "tt": "hvm" , "vl": "xy"}, + {"any": "vpmovsxwd W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 23 /r" , "tt": "hvm" , "vl": "xy"}, + {"any": "vpmovsxwq W:xyz {kz}, xxx/mxxx" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 24 /r" , "tt": "qvm" , "vl": "xy"}, + {"any": "vpmovusdb W:xxx/mxxx {kz}, xyz" , "op": "[MR ] EVEX.xyz.F3.0F38.W0 11 /r" , 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xmm[31:0]/m32" , "op": "[RM ] EVEX.256.66.0F38.WIG 32 /r" , "tt": "ovm" , "vl": "xy"}, + {"any": "vpmovzxbq W:zmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.512.66.0F38.WIG 32 /r" , "tt": "ovm" , "vl": "xy"}, + {"any": "vpmovzxdq W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.66.0F38.W0 35 /r" , "tt": "hvm" , "vl": "xy"}, + {"any": "vpmovzxwd W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 33 /r" , "tt": "hvm" , "vl": "xy"}, + {"any": "vpmovzxwq W:xyz {kz}, xxx/mxxx" , "op": "[RM ] EVEX.xyz.66.0F38.WIG 34 /r" , "tt": "qvm" , "vl": "xy"}, + {"any": "vpmuldq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 28 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpmulld W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 40 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpmuludq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 F4 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpord W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 EB /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vporq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 EB /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vprold W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W0 72 /1 ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vprolq W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W1 72 /1 ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vprolvd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 15 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vprolvq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 15 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vprord W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W0 72 /0 ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vprorq W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W1 72 /0 ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vprorvd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 14 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vprorvq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 14 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpscatterdd W:vm32x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W0 A0 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpscatterdd W:vm32y {k}, ymm" , "op": "[MR ] EVEX.256.66.0F38.W0 A0 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpscatterdd W:vm32z {k}, zmm" , "op": "[MR ] EVEX.512.66.0F38.W0 A0 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpscatterdq W:vm32x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W1 A0 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpscatterdq W:vm32x {k}, ymm" , "op": "[MR ] EVEX.256.66.0F38.W1 A0 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpscatterdq W:vm32y {k}, zmm" , "op": "[MR ] EVEX.512.66.0F38.W1 A0 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpscatterqd W:vm64x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W0 A1 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpscatterqd W:vm64y {k}, xmm" , "op": "[MR ] EVEX.256.66.0F38.W0 A1 /r" , "tt": "t1s" , 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EVEX.xyz.66.0F.W1 73 /6 ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vpsllvd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 47 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpsllvq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 47 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpsrad W:xyz {kz}, xyz, xmm/m128" , "op": "[RVM] EVEX.xyz.66.0F.W0 E2 /r" , "tt": "m128" , "vl": "xy"}, + {"any": "vpsrad W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W0 72 /4 ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vpsraq W:xyz {kz}, xyz, xmm/m128" , "op": "[RVM] EVEX.xyz.66.0F.W1 E2 /r" , "tt": "m128" , "vl": "xy"}, + {"any": "vpsraq W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[VM ] EVEX.xyz.66.0F.W1 72 /4 ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vpsravd W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 46 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpsravq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 46 /r" , "tt": "fv" , "vl": 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xyz/mxyz/b32, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 25 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vpternlogq X:xyz {kz}, xyz, xyz/mxyz/b64, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 25 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vptestmd W:k {k}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 27 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vptestmq W:k {k}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 27 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vptestnmd W:k {k}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 27 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vptestnmq W:k {k}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.F3.0F38.W1 27 /r" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vpunpckhdq W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 6A /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpunpckhqdq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 6D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpunpckldq W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 62 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpunpcklqdq W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 6C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpxord W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 EF /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpxorq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 EF /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vrcp14pd W:xyz {kz}, xyz/mxyz/b64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 4C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vrcp14ps W:xyz {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 4C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vrcp14sd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64" , "op": "[RVM] EVEX.LIG.66.0F38.W1 4D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vrcp14ss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32" , "op": "[RVM] EVEX.LIG.66.0F38.W0 4D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vrndscalepd W:xyz {kz}, xyz/mxyz/b64, imm8 {sae}" , "op": "[RM ] EVEX.xyz.66.0F3A.W1 09 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vrndscaleps W:xyz {kz}, xyz/mxyz/b32, imm8 {sae}" , "op": "[RM ] EVEX.xyz.66.0F3A.W0 08 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vrndscalesd W:xmm {kz},xmm[127:64],xmm[63:0]/m64,imm8 {sae}", "op": "[RVM] EVEX.LIG.66.0F3A.W1 0B /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vrndscaless W:xmm {kz},xmm[127:32],xmm[31:0]/m32,imm8 {sae}", "op": "[RVM] EVEX.LIG.66.0F3A.W0 0A /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vrsqrt14pd W:xyz {kz}, xyz/mxyz/b64" , "op": "[RM ] EVEX.xyz.66.0F38.W1 4E /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vrsqrt14ps W:xyz {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.66.0F38.W0 4E /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vrsqrt14sd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64" , "op": "[RVM] EVEX.LIG.66.0F38.W1 4F /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vrsqrt14ss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32" , "op": "[RVM] EVEX.LIG.66.0F38.W0 4F /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vscalefpd W:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W1 2C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vscalefps W:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 2C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vscalefsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.66.0F38.W1 2D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vscalefss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "[RVM] EVEX.LIG.66.0F38.W0 2D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vscatterdpd W:vm32x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W1 A2 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vscatterdpd W:vm32x {k}, ymm" , "op": "[MR ] EVEX.256.66.0F38.W1 A2 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vscatterdpd W:vm32y {k}, zmm" , "op": "[MR ] EVEX.512.66.0F38.W1 A2 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vscatterdps W:vm32x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W0 A2 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vscatterdps W:vm32y {k}, ymm" , "op": "[MR ] EVEX.256.66.0F38.W0 A2 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vscatterdps W:vm32z {k}, zmm" , "op": "[MR ] EVEX.512.66.0F38.W0 A2 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vscatterqpd W:vm64x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W1 A3" , "tt": "t1s" , "vl": "xy"}, + {"any": "vscatterqpd W:vm64y {k}, ymm" , "op": "[MR ] EVEX.256.66.0F38.W1 A3" , "tt": "t1s" , "vl": "xy"}, + {"any": "vscatterqpd W:vm64z {k}, zmm" , "op": "[MR ] EVEX.512.66.0F38.W1 A3" , "tt": "t1s" , "vl": "xy"}, + {"any": "vscatterqps W:vm64x {k}, xmm" , "op": "[MR ] EVEX.128.66.0F38.W0 A3" , "tt": "t1s" , "vl": "xy"}, + {"any": "vscatterqps W:vm64y {k}, xmm" , "op": "[MR ] EVEX.256.66.0F38.W0 A3" , "tt": "t1s" , "vl": "xy"}, + {"any": "vscatterqps W:vm64z {k}, ymm" , "op": "[MR ] EVEX.512.66.0F38.W0 A3" , "tt": "t1s" , "vl": "xy"}, + {"any": "vshuff32x4 W:ymm {kz}, ymm, ymm/m256/b32, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W0 23 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vshuff32x4 W:zmm {kz}, zmm, zmm/m512/b32, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 23 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vshuff64x2 W:ymm {kz}, ymm, ymm/m256/b64, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W1 23 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vshuff64x2 W:zmm {kz}, zmm, zmm/m512/b64, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 23 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vshufi32x4 W:ymm {kz}, ymm, ymm/m256/b32, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W0 43 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vshufi32x4 W:zmm {kz}, zmm, zmm/m512/b32, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 43 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vshufi64x2 W:ymm {kz}, ymm, ymm/m256/b64, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W1 43 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vshufi64x2 W:zmm {kz}, zmm, zmm/m512/b64, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 43 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vshufpd W:xyz {kz}, xyz, xyz/mxyz/b64, imm8" , "op": "[RVM] EVEX.xyz.66.0F.W1 C6 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vshufps W:xyz {kz}, xyz, xyz/mxyz/b32, imm8" , "op": "[RVM] EVEX.xyz.0F.W0 C6 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vsqrtpd W:xyz {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W1 51 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vsqrtps W:xyz {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.0F.W0 51 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vsqrtsd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 51 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vsqrtss W:xmm {kz}, xmm[127:32], xmm[31:0]/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 51 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vsubpd W:xyz {kz}, xyz, xyz/mxyz/b64 {er}" , "op": "[RVM] EVEX.xyz.66.0F.W1 5C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vsubps W:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.0F.W0 5C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vsubsd W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.0F.W1 5C /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vsubss W:xmm {kz}, xmm, xmm[31:0]/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.0F.W0 5C /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vucomisd R:xmm[63:0], xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.66.0F.W1 2E /r" , "tt": "t1s" , "vl": "no", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "vucomiss R:xmm[31:0], xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.NP.0F.W0 2E /r" , "tt": "t1s" , "vl": "no", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "vunpckhpd W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 15 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vunpckhps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.0F.W0 15 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vunpcklpd W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 14 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vunpcklps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.0F.W0 14 /r" , "tt": "fv" , "vl": "xy"} + ]}, + + {"category": "AVX512 SIMD CRYPTO_HASH", "ext": "AVX512_F VAES", "instructions": [ + {"any": "vaesdec W:xyz, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG DE /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vaesdeclast W:xyz, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG DF /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vaesenc W:xyz, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG DC /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vaesenclast W:xyz, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.WIG DD /r" , "tt": "fvm" , "vl": "xy"} + ]}, + + {"category": "AVX512 SIMD", "ext": "AVX512_F GFNI", "instructions": [ + {"any": "vgf2p8affineinvqb W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 CF /r ib" , "tt": "fvm" , "vl": "xy"}, + {"any": "vgf2p8affineqb W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 CE /r ib" , "tt": "fvm" , "vl": "xy"}, + {"any": "vgf2p8mulb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W0 CF /r" , "tt": "fvm" , "vl": "xy"} + ]}, + + {"category": "AVX512 SIMD", "ext": "AVX512_F VPCLMULQDQ", "instructions": [ + {"any": "vpclmulqdq W:xyz, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.WIG 44 /r ib" , "tt": "fvm" , "vl": "xy"} + ]}, + + {"category": "AVX512 SIMD", "ext": "AVX512_DQ", "instructions": [ + {"any": "vandnpd W:xyz {kz}, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 55 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vandnps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.W0 55 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vandpd W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 54 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vandps W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.0F.W0 54 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vbroadcastf32x2 W:ymm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.256.66.0F38.W0 19 /r" , "tt": "t2" , "vl": "xy"}, + {"any": "vbroadcastf32x2 W:zmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.512.66.0F38.W0 19 /r" , "tt": "t2" , "vl": "xy"}, + {"any": "vbroadcastf32x8 W:zmm {kz}, m256" , "op": "[RM ] EVEX.512.66.0F38.W0 1B /r" , "tt": "t8" , "vl": "xy"}, + {"any": "vbroadcastf64x2 W:ymm {kz}, m128" , "op": "[RM ] EVEX.256.66.0F38.W1 1A /r" , "tt": "t2" , "vl": "xy"}, + {"any": "vbroadcastf64x2 W:zmm {kz}, m128" , "op": "[RM ] EVEX.512.66.0F38.W1 1A /r" , "tt": "t2" , "vl": "xy"}, + {"any": "vbroadcasti32x2 W:xmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.128.66.0F38.W0 59 /r" , "tt": "t2" , "vl": "xy"}, + {"any": "vbroadcasti32x2 W:ymm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.256.66.0F38.W0 59 /r" , "tt": "t2" , "vl": "xy"}, + {"any": "vbroadcasti32x2 W:zmm {kz}, xmm[63:0]/m64" , "op": "[RM ] EVEX.512.66.0F38.W0 59 /r" , "tt": "t2" , "vl": "xy"}, + {"any": "vbroadcasti32x8 W:zmm {kz}, m256" , "op": "[RM ] EVEX.512.66.0F38.W0 5B /r" , "tt": "t8" , "vl": "xy"}, + {"any": "vbroadcasti64x2 W:ymm {kz}, m128" , "op": "[RM ] EVEX.256.66.0F38.W1 5A /r" , "tt": "t2" , "vl": "xy"}, + {"any": "vbroadcasti64x2 W:zmm {kz}, m128" , "op": "[RM ] EVEX.512.66.0F38.W1 5A /r" , "tt": "t2" , "vl": "xy"}, + {"any": "vcvtpd2qq W:xyz {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W1 7B /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtpd2uqq W:xyz {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W1 79 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtps2qq W:xyz {kz}, xxy/mxxy/b32 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W0 7B /r" , "tt": "hv" , "vl": "xy"}, + {"any": "vcvtps2uqq W:xyz {kz}, xxy/mxxy/b32 {er}" , "op": "[RM ] EVEX.xyz.66.0F.W0 79 /r" , "tt": "hv" , "vl": "xy"}, + {"any": "vcvtqq2pd W:xyz {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.F3.0F.W1 E6 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtqq2ps W:xxy {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.NP.0F.W1 5B /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvttpd2uqq W:xyz {kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.66.0F.W1 78 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvttps2qq W:xyz {kz}, xxy/mxxy/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.0F.W0 7A /r" , "tt": "hv" , "vl": "xy"}, + {"any": "vcvttps2uqq W:xyz {kz}, xxy/mxxy/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.0F.W0 78 /r" , "tt": "hv" , "vl": "xy"}, + {"any": "vcvtuqq2pd W:xyz {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.F3.0F.W1 7A /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtuqq2ps W:xxy {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.F2.0F.W1 7A /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vextractf32x8 W:ymm/m256 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W0 1B /r ib" , "tt": "t8" , "vl": "xy"}, + {"any": "vextractf64x2 W:xmm/m128 {kz}, ymm, imm8" , "op": "[MR ] EVEX.256.66.0F3A.W1 19 /r ib" , "tt": "t2" , "vl": "xy"}, + {"any": "vextractf64x2 W:xmm/m128 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W1 19 /r ib" , "tt": "t2" , "vl": "xy"}, + {"any": "vextracti32x8 W:ymm/m256 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W0 3B /r ib" , "tt": "t8" , "vl": "xy"}, + {"any": "vextracti64x2 W:xmm/m128 {kz}, ymm, imm8" , "op": "[MR ] EVEX.256.66.0F3A.W1 39 /r ib" , "tt": "t2" , "vl": "xy"}, + {"any": "vextracti64x2 W:xmm/m128 {kz}, zmm, imm8" , "op": "[MR ] EVEX.512.66.0F3A.W1 39 /r ib" , "tt": "t2" , "vl": "xy"}, + {"any": "vfpclasspd W:k {k}, xyz/mxyz/b64, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W1 66 /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vfpclassps W:k {k}, xyz/mxyz/b32, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W0 66 /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vfpclasssd W:k {k}, xmm[63:0]/m64, imm8" , "op": "[RM ] EVEX.LIG.66.0F3A.W1 67 /r ib" , "tt": "t1s" , "vl": "no", "k": "zeroing"}, + {"any": "vfpclassss W:k {k}, xmm[31:0]/m32, imm8" , "op": "[RM ] EVEX.LIG.66.0F3A.W0 67 /r ib" , "tt": "t1s" , "vl": "no", "k": "zeroing"}, + {"any": "vinsertf32x8 W:zmm {kz}, zmm, ymm/m256, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 1A /r ib" , "tt": "t8" , "vl": "xy"}, + {"any": "vinsertf64x2 W:ymm {kz}, ymm, xmm/m128, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W1 18 /r ib" , "tt": "t2" , "vl": "xy"}, + {"any": "vinsertf64x2 W:zmm {kz}, zmm, xmm/m128, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 18 /r ib" , "tt": "t2" , "vl": "xy"}, + {"any": "vinserti32x8 W:zmm {kz}, zmm, ymm/m256, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W0 3A /r ib" , "tt": "t8" , "vl": "xy"}, + {"any": "vinserti64x2 W:ymm {kz}, ymm, xmm/m128, imm8" , "op": "[RVM] EVEX.256.66.0F3A.W1 38 /r ib" , "tt": "t2" , "vl": "xy"}, + {"any": "vinserti64x2 W:zmm {kz}, zmm, xmm/m128, imm8" , "op": "[RVM] EVEX.512.66.0F3A.W1 38 /r ib" , "tt": "t2" , "vl": "xy"}, + {"any": "vorpd W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 56 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vorps W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F.W0 56 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpextrd W:r32/m32, xmm, imm8" , "op": "[MR ] EVEX.128.66.0F3A.W0 16 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vpextrq W:r64/m64, xmm, imm8" , "op": "[MR ] EVEX.128.66.0F3A.W1 16 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vpinsrd W:xmm {kz}, xmm, r32/m32, imm8" , "op": "[RVM] EVEX.128.66.0F3A.W0 22 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vpinsrq W:xmm {kz}, xmm, r64/m64, imm8" , "op": "[RVM] EVEX.128.66.0F3A.W1 22 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vpmovd2m W:k, xyz" , "op": "[RM ] EVEX.xyz.F3.0F38.W0 39 /r" , "tt": "none" , "vl": "xy"}, + {"any": "vpmovm2d W:xyz, k" , "op": "[RM ] EVEX.xyz.F3.0F38.W0 38 /r" , "tt": "none" , "vl": "xy"}, + {"any": "vpmovm2q W:xyz, k" , "op": "[RM ] EVEX.xyz.F3.0F38.W1 38 /r" , "tt": "none" , "vl": "xy"}, + {"any": "vpmovq2m W:k, xyz" , "op": "[RM ] EVEX.xyz.F3.0F38.W1 39 /r" , "tt": "none" , "vl": "xy"}, + {"any": "vpmullq W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F38.W1 40 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vrangepd W:xyz {kz}, xyz, xyz/mxyz/b64, imm8 {sae}" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 50 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vrangeps W:xyz {kz}, xyz, xyz/mxyz/b32, imm8 {sae}" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 50 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vrangesd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64,imm8 {sae}" , "op": "[RVM] EVEX.LIG.66.0F3A.W1 51 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vrangess W:xmm {kz}, xmm[127:32], xmm[31:0]/m32,imm8 {sae}" , "op": "[RVM] EVEX.LIG.66.0F3A.W0 51 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vreducepd W:xyz {kz}, xyz/mxyz/b64, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W1 56 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vreduceps W:xyz {kz}, xyz/mxyz/b32, imm8" , "op": "[RM ] EVEX.xyz.66.0F3A.W0 56 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vreducesd W:xmm {kz}, xmm[127:64], xmm[63:0]/m64, imm8" , "op": "[RVM] EVEX.LIG.66.0F3A.W1 57 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vreducess W:xmm {kz}, xmm[127:32], xmm[31:0]/m32, imm8" , "op": "[RVM] EVEX.LIG.66.0F3A.W0 57 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vxorpd W:xyz {kz}, ~xyz, ~xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.66.0F.W1 57 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vxorps W:xyz {kz}, ~xyz, ~xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.0F.W0 57 /r" , "tt": "fv" , "vl": "xy"} + ]}, + + {"category": "AVX512 SIMD", "ext": "AVX512_BW", "instructions": [ + {"any": "vdbpsadbw W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 42 /r ib" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovdqu16 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.F2.0F.W1 6F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovdqu16 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.F2.0F.W1 7F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovdqu8 W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.F2.0F.W0 6F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vmovdqu8 W:xyz/mxyz {kz}, xyz" , "op": "[MR ] EVEX.xyz.F2.0F.W0 7F /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpabsb W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38 1C /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpabsw W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38 1D /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpackssdw W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F.W0 6B /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpacksswb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 63 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpackusdw W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 2B /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vpackuswb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 67 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpaddb W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG FC /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpaddsb W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG EC /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpaddsw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG ED /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpaddusb W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG DC /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpaddusw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG DD /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpaddw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG FD /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpalignr W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.WIG 0F /r ib" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpavgb W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG E0 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpavgw W:xyz {kz}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG E3 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpblendmb W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W0 66 /r" , "tt": "fvm" , "vl": "xy", "k": "blend"}, + {"any": "vpblendmw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 66 /r" , "tt": "fvm" , "vl": "xy", "k": "blend"}, + {"any": "vpbroadcastb W:xyz {kz}, r32[7:0]" , "op": "[RM ] EVEX.xyz.66.0F38.W0 7A /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpbroadcastb W:xyz {kz}, xmm[7:0]/m8" , "op": "[RM ] EVEX.xyz.66.0F38.W0 78 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpbroadcastw W:xyz {kz}, r32[15:0]" , "op": "[RM ] EVEX.xyz.66.0F38.W0 7B /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpbroadcastw W:xyz {kz}, xmm[15:0]/m16" , "op": "[RM ] EVEX.xyz.66.0F38.W0 79 /r" , "tt": "t1s" , "vl": "xy"}, + {"any": "vpcmpb W:k {k}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 3F /r ib" , "tt": "fvm" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpeqb W:k {k}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 74 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpeqw W:k {k}, ~xyz, ~xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 75 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpgtb W:k {k}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 64 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpgtw W:k {k}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F.WIG 65 /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpub W:k {k}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 3E /r ib" , "tt": "fvm" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpuw W:k {k}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 3E /r ib" , "tt": "fvm" , "vl": "xy", "k": "zeroing"}, + {"any": "vpcmpw W:k {k}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 3F /r ib" , "tt": "fvm" , "vl": "xy", "k": "zeroing"}, + {"any": "vpermi2w X:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 75 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpermt2w X:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 7D /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpermw W:xyz {kz}, xyz, xyz/mxyz" , "op": "[RVM] EVEX.xyz.66.0F38.W1 8D /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpextrb W:r32[7:0]/m8 , xmm, imm8" , "op": "[MR ] EVEX.128.66.0F3A.WIG 14 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vpextrw W:r32[15:0], xmm, imm8" , "op": "[RM ] EVEX.128.66.0F.WIG C5 /r ib" , "tt": "none" , "vl": "no"}, + {"any": "vpextrw W:r32[15:0]/m16, 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"tt": "fv" , "vl": "xy"} + ]}, + + {"category": "AVX512 SIMD", "ext": "AVX512_BITALG", "instructions": [ + {"any": "vpopcntb W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W0 54 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpopcntw W:xyz {kz}, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W1 54 /r" , "tt": "fvm" , "vl": "xy"}, + {"any": "vpshufbitqmb W:k {k}, xyz, xyz/mxyz" , "op": "[RM ] EVEX.xyz.66.0F38.W0 8F /r" , "tt": "fvm" , "vl": "xy", "k": "zeroing"} + ]}, + + {"category": "AVX512 SIMD", "ext": "AVX512_VP2INTERSECT", "instructions": [ + {"any": "vp2intersectd W:k, W:k+1, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 68 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vp2intersectq W:k, W:k+1, xyz, xyz/mxyz/b64" , "op": "[RVM] EVEX.xyz.F2.0F38.W1 68 /r" , "tt": "fv" , "vl": "xy"} + ]}, + + {"category": "AVX512 SIMD", "ext": "AVX512_BF16", "instructions": [ + {"any": "vcvtne2ps2bf16 W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 72 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtneps2bf16 W:xxy {kz}, xyz/mxyz/b32" , "op": "[RM ] EVEX.xyz.F3.0F38.W0 72 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vdpbf16ps W:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 52 /r" , "tt": "fv" , "vl": "xy"} + ]}, + + {"category": "AVX512 SIMD", "ext": "AVX512_FP16", "instructions": [ + {"any": "vaddph W:xyz {kz}, ~xyz, ~xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 58 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vaddsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 58 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcmpph W:k {k}, xyz, xyz/mxyz/b16, imm8 {sae}" , "op": "[RVM] EVEX.xyz.NP.0F3A.W0 C2 /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vcmpsh W:k {k}, xmm[15:0], xmm[15:0]/m16, imm8 {sae}" , "op": "[RVM] EVEX.LIG.F3.0F3A.W0 C2 /r ib" , "tt": "t1s" , "vl": "no", "k": "zeroing"}, + {"any": "vcomish R:xmm[15:0], xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.NP.MAP5.W0 2F /r" , "tt": "t1s" , "vl": "no", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "vcvtdq2ph W:xxy {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 5B /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtpd2ph W:xxx {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W1 5A /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtph2dq W:xyz {kz}, xxy/mxxy/b16 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 5B /r" , "tt": "hv" , "vl": "xy"}, + {"any": "vcvtph2pd W:xyz {kz}, xxx/mxxx/b16 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 5A /r" , "tt": "qv" , "vl": "xy"}, + {"any": "vcvtph2psx W:xyz {kz}, xxy/mxxy/b16 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP6.W0 13 /r" , "tt": "qv" , "vl": "xy"}, + {"any": "vcvtph2qq W:xyz {kz}, xxx/mxxx/b16 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 7B /r" , "tt": "qv" , "vl": "xy"}, + {"any": "vcvtph2udq W:xyz {kz}, xxy/mxxy/b16 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 79 /r" , "tt": "hv" , "vl": "xy"}, + {"any": "vcvtph2uqq W:xyz {kz}, xxx/mxxx/b16 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 79 /r" , "tt": "qv" , "vl": "xy"}, + {"any": "vcvtph2uw W:xyz {kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 7D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtph2w W:xyz {kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 7D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtps2phx W:xxy {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 1D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtqq2ph W:xmm {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W1 5B /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtsd2sh W:xmm {kz}, xmm, xmm[63:0]/m64 {er}" , "op": "[RVM] EVEX.LIG.F2.MAP5.W1 5A /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcvtsh2sd W:xmm {kz}, xmm, xmm[15:0]/m16 {sae}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 5A /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcvtsh2si W:ry, xmm[15:0]/m16 {er}" , "op": "[RM ] EVEX.LIG.F3.MAP5.Wy 2D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcvtsh2ss W:xmm {kz}, xmm, xmm/m16 {sae}" , "op": "[RVM] EVEX.LIG.NP.MAP6.W0 13 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcvtsh2usi W:ry, xmm[15:0]/m16 {er}" , "op": "[RM ] EVEX.LIG.F3.MAP5.Wy 79 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcvtsi2sh W:xmm, xmm, ry/my {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.Wy 2A /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcvtss2sh W:xmm {kz}, xmm, xmm/m32 {er}" , "op": "[RVM] EVEX.LIG.NP.MAP5.W0 1D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcvttph2dq W:xyz {kz}, xxy/mxxy/b16 {sae}" , "op": "[RM ] EVEX.xyz.F3.MAP5.W0 5B /r" , "tt": "hv" , "vl": "xy"}, + {"any": "vcvttph2qq W:xyz {kz}, xxx/mxxx/b16 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 7A /r" , "tt": "qv" , "vl": "xy"}, + {"any": "vcvttph2udq W:xyz {kz}, xxy/mxxy/b16 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 78 /r" , "tt": "hv" , "vl": "xy"}, + {"any": "vcvttph2uqq W:xyz {kz}, xxx/mxxx/b16 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 78 /r" , "tt": "qv" , "vl": "xy"}, + {"any": "vcvttph2uw W:xyz {kz}, xyz/mxyz/b16 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 7C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvttph2w W:xyz {kz}, xyz/mxyz/b16 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 7C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvttsh2si W:ry, xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.F3.MAP5.Wy 2C /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcvttsh2usi W:ry, xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.F3.MAP5.Wy 78 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcvtudq2ph W:xxy {kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 7A /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtuqq2ph W:xxx {kz}, xyz/mxyz/b64 {er}" , "op": "[RM ] EVEX.xyz.F2.MAP5.W1 7A /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtusi2sh W:xmm, xmm, ry/my {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.Wy 7B /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vcvtuw2ph W:xyz {kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 7D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vcvtw2ph W:xyz {kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.F3.MAP5.W0 7D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vdivph W:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 5E /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vdivsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 5E /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfcmaddcph X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.F2.MAP6.W0 56 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfcmaddcsh x:xmm {kz}, xmm, xmm/m32 {er}" , "op": "[RVM] EVEX.LIG.F2.MAP6.W0 57 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfcmulcph X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.F2.MAP6.W0 D6 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfcmulcsh x:xmm {kz}, xmm, xmm/m32 {er}" , "op": "[RVM] EVEX.LIG.F2.MAP6.W0 D7 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmadd132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 98 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmadd132sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 99 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmadd213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 A8 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmadd213sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 A9 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmadd231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 B8 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmadd231sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 B9 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmaddcph X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.F3.MAP6.W0 56 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmaddcsh x:xmm {kz}, xmm, xmm/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP6.W0 57 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmaddsub132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 96 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmaddsub213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 A6 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmaddsub231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 B6 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsub132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 9A /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsub132sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 9B /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmsub213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 AA /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsub213sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 AB /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmsub231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 BA /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsub231sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 BB /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfmsubadd132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 97 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsubadd213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 A7 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmsubadd231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 B7 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmulcph X:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.F3.MAP6.W0 D6 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfmulcsh X:xmm {kz}, xmm, xmm/m32 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP6.W0 D7 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmadd132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 9C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmadd132sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 9D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmadd213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 AC /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmadd213sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 AD /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmadd231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 BC /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmadd231sh x:xmm {kz}, xmm, xmm/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 BD /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmsub132ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 9E /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmsub132sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 9F /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmsub213ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 AE /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmsub213sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 AF /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfnmsub231ph X:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 BE /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vfnmsub231sh x:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 BF /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vfpclassph W:k {k}, xyz/mxyz/b16, imm8" , "op": "[RM ] EVEX.xyz.NP.0F3A.W0 66 /r ib" , "tt": "fv" , "vl": "xy", "k": "zeroing"}, + {"any": "vfpclasssh W:k {k}, xmm[15:0]/m16, imm8" , "op": "[RM ] EVEX.LIG.NP.0F3A.W0 67 /r ib" , "tt": "t1s" , "vl": "no", "k": "zeroing"}, + {"any": "vgetexpph W:xyz {kz}, xyz/mxyz/b16 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP6.W0 42 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vgetexpsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.66.MAP6.W0 43 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vgetmantph W:xyz {kz}, xyz/mxyz/b16, imm8 {sae}" , "op": "[RM ] EVEX.xyz.NP.0F3A.W0 26 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vgetmantsh W:xmm {kz},xmm[127:16],xmm[15:0]/m16,imm8 {sae}" , "op": "[RM ] EVEX.LIG.NP.0F3A.W0 27 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vmaxph W:xyz {kz}, xyz, xyz/mxyz/b16 {sae}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 5F /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vmaxsh W:xmm {kz}, xmm, xmm[15:0]/m16 {sae}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 5F /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vminph W:xyz {kz}, xyz, xyz/mxyz/b16 {sae}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 5D /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vminsh W:xmm {kz}, xmm, xmm[15:0]/m16 {sae}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 5D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovsh W:m16, xmm[15:0]" , "op": "[MR ] EVEX.LIG.F3.MAP5.W0 11 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovsh W:xmm[15:0] {kz}, m16" , "op": "[RM ] EVEX.LIG.F3.MAP5.W0 10 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovsh W:xmm {kz}, xmm[127:16], xmm[15:0]" , "op": "[MVR] EVEX.LIG.F3.MAP5.W0 11 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovsh W:xmm {kz}, xmm[127:16], xmm[15:0]" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 10 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovw W:r32[15:0]/m16, xmm[15:0]" , "op": "[MR ] EVEX.128.66.MAP5.WIG 7E /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmovw W:xmm[15:0] {kz}, r32[15:0]/m16" , "op": "[RM ] EVEX.128.66.MAP5.WIG 6E /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vmulph W:xyz {kz}, ~xyz, ~xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 59 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vmulsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 59 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vrcpph W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.66.MAP6.W0 4C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vrcpsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 4D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vreduceph W:xyz {kz}, xyz/mxyz/b16, imm8 {sae}" , "op": "[RM ] EVEX.xyz.NP.0F3A.W0 56 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vreducesh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16,imm8 {sae}", "op": "[RVM] EVEX.LIG.NP.0F3A.W0 57 /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vrndscaleph W:xyz {kz}, xyz/mxyz/b16, imm8 {sae}" , "op": "[RM ] EVEX.xyz.NP.0F3A.W0 08 /r ib" , "tt": "fv" , "vl": "xy"}, + {"any": "vrndscalesh W:xmm {kz},xmm[127:16],xmm[15:0]/m16,imm8 {sae}", "op": "[RVM] EVEX.LIG.NP.0F3A.W0 0A /r ib" , "tt": "t1s" , "vl": "no"}, + {"any": "vrsqrtph W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.66.MAP6.W0 4E /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vrsqrtsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 4F /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vscalefph W:xyz {kz}, xyz, xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.66.MAP6.W0 2C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vscalefsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.66.MAP6.W0 2D /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vsqrtph W:xyz {kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 51 /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vsqrtsh W:xmm {kz}, xmm[127:16], xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 51 /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vsubph W:xyz {kz}, ~xyz, ~xyz/mxyz/b16 {er}" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 5C /r" , "tt": "fv" , "vl": "xy"}, + {"any": "vsubsh W:xmm {kz}, xmm, xmm[15:0]/m16 {er}" , "op": "[RVM] EVEX.LIG.F3.MAP5.W0 5C /r" , "tt": "t1s" , "vl": "no"}, + {"any": "vucomish R:xmm[15:0], xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.NP.MAP5.W0 2E /r" , "tt": "t1s" , "vl": "no", "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"} + ]}, + + {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [ + {"any": "vaddnepbf16 W:xyz{kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 58 /r" , "tt": "fv"}, + {"any": "vcmppbf16 W:k {k}, xyz, xyz/mxyz/b16, imm8" , "op": "[RVM] EVEX.xyz.F2.0F3A.W0 C2 /r ib" , "tt": "fv" , "k": "zeroing"}, + {"any": "vcomsbf16 R:xmm, xmm/m16" , "op": "[RM ] EVEX.LIG.66.MAP5.W0 2F /r" , "tt": "t1s" , "io": "OF=0 SF=0 ZF=W AF=0 PF=W CF=W"}, + {"any": "vdivnepbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 5E /r" , "tt": "fv"}, + {"any": "vfmadd132nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 98 /r" , "tt": "fv"}, + {"any": "vfmadd213nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 A8 /r" , "tt": "fv"}, + {"any": "vfmadd231nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 B8 /r" , "tt": "fv"}, + {"any": "vfmsub132nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 9A /r" , "tt": "fv"}, + {"any": "vfmsub213nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 AA /r" , "tt": "fv"}, + {"any": "vfmsub231nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 BA /r" , "tt": "fv"}, + {"any": "vfnmadd132nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 9C /r" , "tt": "fv"}, + {"any": "vfnmadd213nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 AC /r" , "tt": "fv"}, + {"any": "vfnmadd231nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 BC /r" , "tt": "fv"}, + {"any": "vfnmsub132nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 9E /r" , "tt": "fv"}, + {"any": "vfnmsub213nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 AE /r" , "tt": "fv"}, + {"any": "vfnmsub231nepbf16 X:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 BE /r" , "tt": "fv"}, + {"any": "vfpclasspbf16 W:k {k}, xyz/mxyz/b16, imm8" , "op": "[RM ] EVEX.xyz.F2.0F3A.W0 66 /r ib" , "tt": "fv" , "k": "zeroing"}, + {"any": "vgetexppbf16 W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 42 /r" , "tt": "fv"}, + {"any": "vgetmantpbf16 W:xyz {kz}, xyz/mxyz/b16, imm8" , "op": "[RM ] EVEX.xyz.F2.0F3A.W0 26 /r ib" , "tt": "fv"}, + {"any": "vmaxpbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 5F /r" , "tt": "fv"}, + {"any": "vminpbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 5D /r" , "tt": "fv"}, + {"any": "vmulnepbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 59 /r" , "tt": "fv"}, + {"any": "vrcppbf16 W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.NP.MAP6.W0 4C /r" , "tt": "fv"}, + {"any": "vreducenepbf16 W:xyz {kz}, xyz/mxyz/b16, imm8" , "op": "[RM ] EVEX.xyz.F2.0F3A.W0 56 /r ib" , "tt": "fv"}, + {"any": "vrndscalenepbf16 W:xyz {kz}, xyz/mxyz/b16, imm8" , "op": "[RM ] EVEX.xyz.F2.0F3A.W0 08 /r ib" , "tt": "fv"}, + {"any": "vrsqrtpbf16 W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.NP.MAP6.W0 4E /r" , "tt": "fv"}, + {"any": "vscalefpbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP6.W0 2C /r" , "tt": "fv"}, + {"any": "vsqrtnepbf16 W:xyz {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 51 /r " , "tt": "fv"}, + {"any": "vsubnepbf16 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.66.MAP5.W0 5C /r" , "tt": "fv"} + ]}, + + {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [ + {"any": "vcomxsd R:xmm[63:0], R:xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.F3.0F.W1 2F /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"}, + {"any": "vcomxsh R:xmm[15:0], R:xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.F2.MAP5.W0 2F /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"}, + {"any": "vcomxss R:xmm[31:0], R:xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.F2.0F.W0 2F /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"}, + {"any": "vucomxsd R:xmm[63:0], R:xmm[63:0]/m64 {sae}" , "op": "[RM ] EVEX.LIG.F3.0F.W1 2E /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"}, + {"any": "vucomxsh R:xmm[15:0], R:xmm[15:0]/m16 {sae}" , "op": "[RM ] EVEX.LIG.F2.MAP5.W0 2E /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"}, + {"any": "vucomxss R:xmm[31:0], R:xmm[31:0]/m32 {sae}" , "op": "[RM ] EVEX.LIG.F2.0F.W0 2E /r" , "tt": "t1s" , "io": "OF=W SF=W ZF=W AF=0 PF=W CF=W"} + ]}, + + {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [ + {"any": "vcvt2ps2phx W:xyz {kz}, xyz, xyz/mxyz/b32 {er}" , "op": "[RVM] EVEX.xyz.66.0F38.W0 67 /r" , "tt": "fv"}, + {"any": "vcvtbiasph2bf8 W:xxy {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 74 /r" , "tt": "fv"}, + {"any": "vcvtbiasph2bf8s W:xxy {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 74 /r" , "tt": "fv"}, + {"any": "vcvtbiasph2hf8 W:xxy {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 18 /r" , "tt": "fv"}, + {"any": "vcvtbiasph2hf8s W:xxy {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.NP.MAP5.W0 1B /r" , "tt": "fv"}, + {"any": "vcvthf82ph W:xyz {kz}, xxy/mxxy" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 1E /r" , "tt": "hv"}, + {"any": "vcvtne2ph2bf8 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 74 /r" , "tt": "fv"}, + {"any": "vcvtne2ph2bf8s W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.F2.MAP5.W0 74 /r" , "tt": "fv"}, + {"any": "vcvtne2ph2hf8 W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.F2.MAP5.W0 18 /r" , "tt": "fv"}, + {"any": "vcvtne2ph2hf8s W:xyz {kz}, xyz, xyz/mxyz/b16" , "op": "[RVM] EVEX.xyz.F2.MAP5.W0 1B /r" , "tt": "fv"}, + {"any": "vcvtneph2bf8 W:xxy {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F3.0F38.W0 74 /r" , "tt": "fv"}, + {"any": "vcvtneph2bf8s W:xxy {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F3.MAP5.W0 74 /r" , "tt": "fv"}, + {"any": "vcvtneph2hf8 W:xxy {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F3.MAP5.W0 18 /r" , "tt": "fv"}, + {"any": "vcvtneph2hf8s W:xxy {kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F3.MAP5.W0 1B /r" , "tt": "fv"} + ]}, + + {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [ + {"any": "vdpphps X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 52 /r" , "tt": "fv"}, + {"any": "vmpsadbw W:xyz {kz}, xyz, xyz/mxyz, imm8" , "op": "[RVM] EVEX.xyz.F3.0F3A.W0 42 /r ib" , "tt": "fv"}, + {"any": "vpdpbssd X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 50 /r" , "tt": "fv"}, + {"any": "vpdpbssds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F2.0F38.W0 51 /r" , "tt": "fv"}, + {"any": "vpdpbsud X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 50 /r" , "tt": "fv"}, + {"any": "vpdpbsuds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 51 /r" , "tt": "fv"}, + {"any": "vpdpbuud X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 50 /r" , "tt": "fv"}, + {"any": "vpdpbuuds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 51 /r" , "tt": "fv"}, + {"any": "vpdpwsud X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 D2 /r" , "tt": "fv"}, + {"any": "vpdpwsuds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.F3.0F38.W0 D3 /r" , "tt": "fv"}, + {"any": "vpdpwusd X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 D2 /r" , "tt": "fv"}, + {"any": "vpdpwusds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.66.0F38.W0 D3 /r" , "tt": "fv"}, + {"any": "vpdpwuud X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 D2 /r" , "tt": "fv"}, + {"any": "vpdpwuuds X:xyz {kz}, xyz, xyz/mxyz/b32" , "op": "[RVM] EVEX.xyz.NP.0F38.W0 D3 /r" , "tt": "fv"} + ]}, + + {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [ + {"any": "vminmaxnepbf16 W:xyz {kz}, xyz, xyz/mxyz/b16, imm8" , "op": "[RVM] EVEX.xyz.F2.0F3A.W0 52 /r ib" , "tt": "fv"}, + {"any": "vminmaxpd W:xyz {kz}, xyz, xyz/mxyz/b64 {sae}, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W1 52 /r ib" , "tt": "fv"}, + {"any": "vminmaxph W:xyz {kz}, xyz, xyz/mxyz/b16 {sae}, imm8" , "op": "[RVM] EVEX.xyz.NP.0F3A.W0 52 /r ib" , "tt": "fv"}, + {"any": "vminmaxps W:xyz {kz}, xyz, xyz/mxyz/b32 {sae}, imm8" , "op": "[RVM] EVEX.xyz.66.0F3A.W0 52 /r ib" , "tt": "fv"}, + {"any": "vminmaxsd W:xmm {kz}, xmm, xmm/m64 {sae}, imm8" , "op": "[RVM] EVEX.LIG.66.0F3A.W1 53 /r ib" , "tt": "t1s"}, + {"any": "vminmaxsh W:xmm {kz}, xmm, xmm/m16 {sae}, imm8" , "op": "[RVM] EVEX.LIG.NP.0F3A.W0 53 /r ib" , "tt": "t1s"}, + {"any": "vminmaxss W:xmm {kz}, xmm, xmm/m32 {sae}, imm8" , "op": "[RVM] EVEX.LIG.66.0F3A.W0 53 /r ib" , "tt": "t1s"} + ]}, + + {"category": "AVX10_2 SIMD", "ext": "AVX10_2", "instructions": [ + {"any": "vcvtnebf162ibs W:xyz{kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 69 /r" , "tt": "fv"}, + {"any": "vcvtnebf162iubs W:xyz{kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 6B /r" , "tt": "fv"}, + {"any": "vcvttnebf162ibs W:xyz{kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 68 /r" , "tt": "fv"}, + {"any": "vcvttnebf162iubs W:xyz{kz}, xyz/mxyz/b16" , "op": "[RM ] EVEX.xyz.F2.MAP5.W0 6A /r" , "tt": "fv"}, + {"any": "vcvttpd2dqs W:xxy{kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W1 6D /r" , "tt": "fv"}, + {"any": "vcvttpd2qqs W:xyz{kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W1 6D /r" , "tt": "fv"}, + {"any": "vcvttpd2udqs W:xxy{kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W1 6C /r" , "tt": "fv"}, + {"any": "vcvttpd2uqqs W:xyz{kz}, xyz/mxyz/b64 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W1 6C /r" , "tt": "fv"}, + {"any": "vcvtph2ibs W:xyz{kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 69 /r" , "tt": "fv"}, + {"any": "vcvtph2iubs W:xyz{kz}, xyz/mxyz/b16 {er}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 6B /r" , "tt": "fv"}, + {"any": "vcvttph2ibs W:xyz{kz}, xyz/mxyz/b16 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 68 /r" , "tt": "fv"}, + {"any": "vcvttph2iubs W:xyz{kz}, xyz/mxyz/b16 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 6A /r" , "tt": "fv"}, + {"any": "vcvttps2dqs W:xyz{kz}, xyz/mxyz/b32 {sae}" , "op": "[RM ] EVEX.xyz.NP.MAP5.W0 6D /r" , "tt": "fv"}, + {"any": "vcvtps2ibs W:xyz{kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 69 /r" , "tt": "fv"}, + {"any": "vcvtps2iubs W:xyz{kz}, xyz/mxyz/b32 {er}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 6B /r" , "tt": "fv"}, + {"any": "vcvttps2ibs W:xyz{kz}, xyz/mxyz/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 68 /r" , "tt": "fv"}, + {"any": "vcvttps2iubs W:xyz{kz}, xyz/mxyz/b32 {sae}" , "op": "[RM ] EVEX.xyz.66.MAP5.W0 6A /r" , "tt": "fv"}, + {"any": "vcvttps2qqs W:xyz{kz}, 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"[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 21 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "and{nf} W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 22 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "and{nf} W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 23 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "and{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "and{nf} W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /4 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "and{nf} W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /4 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "cmovb W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 42 /r" , "io": "CF=R"}, + {"apx": "cmovbe W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 46 /r" , "io": "CF=R ZF=R"}, + {"apx": "cmovl W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4C /r" , "io": "SF=R OF=R"}, + {"apx": "cmovle W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4E /r" , "io": "ZF=R SF=R OF=R"}, + {"apx": "cmovnb W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 43 /r" , "io": "CF=R"}, + {"apx": "cmovnbe W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 47 /r" , "io": "CF=R ZF=R"}, + {"apx": "cmovnl W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4D /r" , "io": "SF=R OF=R"}, + {"apx": "cmovnle W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4F /r" , "io": "ZF=R SF=R OF=R"}, + {"apx": "cmovno W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 41 /r" , "io": "OF=R"}, + {"apx": "cmovnp W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4B /r" , "io": "PF=R"}, + {"apx": "cmovns W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 49 /r" , "io": "SF=R"}, + {"apx": "cmovnz W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 45 /r" , "io": "ZF=R"}, + {"apx": "cmovo W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 40 /r" , "io": "OF=R"}, + {"apx": "cmovp W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 4A /r" , "io": "PF=R"}, + {"apx": "cmovs W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 48 /r" , "io": "SF=R"}, + {"apx": "cmovz W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 44 /r" , "io": "ZF=R"}, + {"any": "crc32 X:r32, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.W0 F0 /r"}, + {"any": "crc32 X:r64, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.W1 F0 /r"}, + {"any": "crc32 X:r32, R:r16/m16" , "op": "[RM ] EVEX.ND=0.LLZ.66.MAP4.W0 F1 /r"}, + {"any": "crc32 X:r32, R:r32/m32" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.W0 F1 /r"}, + {"any": "crc32 X:r64, R:r64/m64" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.W1 F1 /r"}, + {"apx": "dec{nf} X:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG FE /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"apx": "dec{nf} X:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv FF /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"apx": "dec{nf} W:r8, R:r8/m8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG FE /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"apx": "dec{nf} W:rv, R:rv/mv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv FF /1" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"apx": "inc{nf} X:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG FE /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"apx": "inc{nf} X:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv FF /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"apx": "inc{nf} W:r8, R:r8/m8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG FE /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"apx": "inc{nf} W:rv, R:rv/mv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv FF /0" , "io": "OF=W SF=W ZF=W AF=W PF=W"}, + {"any": "div{nf} x:, R:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"any": "div{nf} x:, x:, R:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /6" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"apx": "idiv{nf} x:, R:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"apx": "idiv{nf} x:, x:, R:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /7" , "io": "OF=U SF=U ZF=U AF=U PF=U CF=U"}, + {"apx": "imul{nf} x:, R:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"apx": "imul{nf} w:, x:, R:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /5" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"apx": "imul{nf} x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv AF /r" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"apx": "imul{nf} W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv AF /r" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"apx": "imul{nf} w:rv, R:rv/mv, imms8" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 6B /r ib" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"apx": "imul{nf} w:rv, R:rv/mv, immv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 69 /r iv" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"apx": "imulzu{nf} W:r16, R:r16/m16, imms8" , "op": "[RM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 6B /r ib" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"apx": "imulzu{nf} W:r16, R:r16/m16, imm16" , "op": "[RM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 69 /r iv" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"apx": "mul{nf} x:, R:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /4" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"apx": "mul{nf} w:, x:, rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /4" , "io": "OF=W SF=W ZF=U AF=U PF=U CF=W"}, + {"apx": "neg{nf} X:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "neg{nf} X:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "neg{nf} W:r8, R:r8/m8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG F6 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "neg{nf} W:rv, R:rv/mv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv F7 /3" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "not{nf} X:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG F6 /2"}, + {"apx": "not{nf} X:rv/mv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F7 /2"}, + {"apx": "not{nf} W:r8, R:r8/m8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG F6 /2"}, + {"apx": "not{nf} W:rv, R:rv/mv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv F7 /2"}, + {"apx": "or{nf} x:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.WIG 08 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} x:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 09 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} x:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.WIG 0A /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 0B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG 80 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} x:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 83 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} x:rv/mv, immv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 81 /1 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} W:r8, R:r8/m8, R:r8" , "op": "[VMR] EVEX.ND=1.LLZ.NP.MAP4.WIG 08 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} W:rv, R:rv/mv, R:rv" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 09 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 0A /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 0B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /1 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "or{nf} W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /1 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "rcl x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /2" , "io": "CF=X OF=X"}, + {"apx": "rcl x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /2" , "io": "CF=X OF=X"}, + {"apx": "rcl x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /2" , "io": "CF=X OF=X"}, + {"apx": "rcl x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /2" , "io": "CF=X OF=X"}, + {"apx": "rcl x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /2 ib" , "io": "CF=X OF=X"}, + {"apx": "rcl x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /2 ib" , "io": "CF=X OF=X"}, + {"apx": "rcl W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /2" , "io": "CF=X OF=X"}, + {"apx": "rcl W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /2" , "io": "CF=X OF=X"}, + {"apx": "rcl W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /2" , "io": "CF=X OF=X"}, + {"apx": "rcl W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /2" , "io": "CF=X OF=X"}, + {"apx": "rcl W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /2 ib" , "io": "CF=X OF=X"}, + {"apx": "rcl W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /2 ib" , "io": "CF=X OF=X"}, + {"apx": "rcr x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /3" , "io": "CF=X OF=X"}, + {"apx": "rcr x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /3" , "io": "CF=X OF=X"}, + {"apx": "rcr x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /3" , "io": "CF=X OF=X"}, + {"apx": "rcr x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /3" , "io": "CF=X OF=X"}, + {"apx": "rcr x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /3 ib" , "io": "CF=X OF=X"}, + {"apx": "rcr x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /3 ib" , "io": "CF=X OF=X"}, + {"apx": "rcr W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /3" , "io": "CF=X OF=X"}, + {"apx": "rcr W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /3" , "io": "CF=X OF=X"}, + {"apx": "rcr W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /3" , "io": "CF=X OF=X"}, + {"apx": "rcr W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /3" , "io": "CF=X OF=X"}, + {"apx": "rcr W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /3 ib" , "io": "CF=X OF=X"}, + {"apx": "rcr W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /3 ib" , "io": "CF=X OF=X"}, + {"apx": "rol{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /0" , "io": "CF=W OF=W"}, + {"apx": "rol{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /0" , "io": "CF=W OF=W"}, + {"apx": "rol{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /0" , "io": "CF=W OF=W"}, + {"apx": "rol{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /0" , "io": "CF=W OF=W"}, + {"apx": "rol{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /0 ib" , "io": "CF=W OF=W"}, + {"apx": "rol{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /0 ib" , "io": "CF=W OF=W"}, + {"apx": "rol{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /0" , "io": "CF=W OF=W"}, + {"apx": "rol{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /0" , "io": "CF=W OF=W"}, + {"apx": "rol{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /0" , "io": "CF=W OF=W"}, + {"apx": "rol{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /0" , "io": "CF=W OF=W"}, + {"apx": "rol{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /0 ib" , "io": "CF=W OF=W"}, + {"apx": "rol{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /0 ib" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /1" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /1" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /1" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /1" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /1 ib" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /1 ib" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /1" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /1" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /1" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /1" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /1 ib" , "io": "CF=W OF=W"}, + {"apx": "ror{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /1 ib" , "io": "CF=W OF=W"}, + {"apx": "sar{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sar{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sar{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sar{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sar{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sar{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sar{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sar{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sar{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sar{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /7" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sar{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sar{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /7 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sbb x:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.WIG 18 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb x:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 19 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb x:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.WIG 1A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 1B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG 80 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb x:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 83 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb x:rv/mv, immv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 81 /3 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb W:r8, R:r8/m8, R:r8" , "op": "[VMR] EVEX.ND=1.LLZ.NP.MAP4.WIG 18 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb W:rv, R:rv/mv, R:rv" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 19 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 1A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 1B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /3 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "sbb W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /3 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=X"}, + {"apx": "shl{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /6 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /6 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /4" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /6" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /6 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /4 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shl{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /6 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shld{nf} x:rv/mv, R:rv, R:cl" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv A5 /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"apx": "shld{nf} x:rv/mv, R:rv, imm8" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 24 /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"apx": "shld{nf} W:rv, R:rv/mv, R:rv, R:cl" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv A5 /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"apx": "shld{nf} W:rv, R:rv/mv, R:rv, imm8" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 24 /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"apx": "shr{nf} x:r8/m8, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D2 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shr{nf} x:rv/mv, R:cl" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D3 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shr{nf} x:r8/m8, 1" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG D0 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shr{nf} x:rv/mv, 1" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv D1 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shr{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG C0 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shr{nf} x:rv/mv, imm8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv C1 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shr{nf} W:r8, R:r8/m8, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D2 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shr{nf} W:rv, R:rv/mv, R:cl" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D3 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shr{nf} W:r8, R:r8/m8, 1" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG D0 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shr{nf} W:rv, R:rv/mv, 1" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv D1 /5" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shr{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG C0 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shr{nf} W:rv, R:rv/mv, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv C1 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "shrd{nf} x:rv/mv, R:rv, R:cl" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv AD /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"apx": "shrd{nf} x:rv/mv, R:rv, imm8" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 2C /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"apx": "shrd{nf} W:rv, R:rv/mv, R:rv, R:cl" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv AD /r" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"apx": "shrd{nf} W:rv, R:rv/mv, R:rv, imm8" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 2C /r ib" , "io": "OF=W SF=W ZF=W AF=U PF=W CF=W"}, + {"apx": "sub{nf} x:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.WIG 28 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} x:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 29 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} x:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.WIG 2A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 2B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG 80 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} x:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 83 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} x:rv/mv, immv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 81 /5 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} W:r8, R:r8/m8, R:r8" , "op": "[VMR] EVEX.ND=1.LLZ.NP.MAP4.WIG 28 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} W:rv, R:rv/mv, R:rv" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 29 /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 2A /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 2B /r" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /5 ib" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "sub{nf} W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /5 iv" , "io": "OF=W SF=W ZF=W AF=W PF=W CF=W"}, + {"apx": "xor{nf} x:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.WIG 38 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} x:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 39 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} x:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.LLZ.NP.MAP4.WIG 3A /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} x:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 3B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} x:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.LLZ.NP.MAP4.WIG 80 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} x:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 83 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} x:rv/mv, immv" , "op": "[M ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 81 /6 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} W:r8, R:r8/m8, R:r8" , "op": "[VMR] EVEX.ND=1.LLZ.NP.MAP4.WIG 38 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} W:rv, R:rv/mv, R:rv" , "op": "[VMR] EVEX.ND=1.LLZ.Pv.MAP4.Wv 39 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} W:r8, R:r8, R:r8/m8" , "op": "[VRM] EVEX.ND=1.LLZ.NP.MAP4.WIG 3A /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} W:rv, R:rv, R:rv/mv" , "op": "[VRM] EVEX.ND=1.LLZ.Pv.MAP4.Wv 3B /r" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} W:r8, R:r8/m8, imm8" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.WIG 80 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} W:rv, R:rv/mv, imms8" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 83 /6 ib" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"}, + {"apx": "xor{nf} W:rv, R:rv/mv, immv" , "op": "[VM ] EVEX.ND=1.LLZ.Pv.MAP4.Wv 81 /6 iv" , "io": "OF=0 SF=W ZF=W AF=U PF=W CF=0"} + ]}, + + {"category": "GP GP_EXT", "ext": "RAO_INT APX_F", "volatile": true, "instructions": [ + {"apx": "aadd X:my, R:ry" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.Wy FC !(11):rrr:bbb"}, + {"apx": "aand X:my, R:ry" , "op": "[MR ] EVEX.ND=0.LLZ.66.MAP4.Wy FC !(11):rrr:bbb"}, + {"apx": "aor X:my, R:ry" , "op": "[MR ] EVEX.ND=0.LLZ.F2.MAP4.Wy FC !(11):rrr:bbb"}, + {"apx": "axor X:my, R:ry" , "op": "[MR ] EVEX.ND=0.LLZ.F3.MAP4.Wy FC !(11):rrr:bbb"} + ]}, + + {"category": "GP GP_EXT", "ext": "ADX APX_F", "instructions": [ + {"apx": "adcx X:ry, R:ry/my" , "op": "[RM ] EVEX.ND=0.LLZ.66.MAP4.Wy 66 /r" , "io": "CF=X"}, + {"apx": "adcx W:ry, R:ry, R:ry/my" , "op": "[VRM] EVEX.ND=1.LLZ.66.MAP4.Wy 66 /r" , "io": "CF=X"}, + {"apx": "adox X:ry, R:ry/my" , "op": "[RM ] EVEX.ND=0.LLZ.F3.MAP4.Wy 66 /r" , "io": "OF=X"}, + {"apx": "adox W:ry, R:ry, R:ry/my" , "op": "[VRM] EVEX.ND=1.LLZ.F3.MAP4.Wy 66 /r" , "io": "OF=X"} + ]}, + + {"category": "GP GP_EXT", "ext": "BMI APX_F", "instructions": [ + {"apx": "andn{nf} W:ry, R:ry, R:my/ry" , "op": "[RVM] EVEX.128.NP.0F38.Wy F2 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=0"}, + {"apx": "bextr{nf} W:ry, R:my/ry, ry" , "op": "[RMV] EVEX.128.NP.0F38.Wy F7 /r" , "io": "OF=0 SF=U ZF=W AF=U PF=U CF=0"}, + {"apx": "blsi{nf} W:ry, R:my/ry" , "op": "[VM ] EVEX.128.NP.0F38.Wy F3 /3" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, + {"apx": "blsmsk{nf} W:ry, R:my/ry" , "op": "[VM ] EVEX.128.NP.0F38.Wy F3 /2" , "io": "OF=0 SF=W ZF=0 AF=U PF=U CF=W"}, + {"apx": "blsr{nf} W:ry, R:my/ry" , "op": "[VM ] EVEX.128.NP.0F38.Wy F3 /1" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, + {"apx": "tzcnt{nf} w:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F4 /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"} + ]}, + + {"category": "GP GP_EXT", "ext": "BMI2 APX_F", "instructions": [ + {"apx": "bzhi{nf} W:ry, R:my/ry, R:ry" , "op": "[RMV] EVEX.128.NP.0F38.Wy F5 /r" , "io": "OF=0 SF=W ZF=W AF=U PF=U CF=W"}, + {"apx": "mulx W:ry, W:ry, R:~my/ry, R:~" , "op": "[RVM] EVEX.128.F2.0F38.Wy F6 /r"}, + {"apx": "pdep W:ry, R:ry, R:my/ry" , "op": "[RVM] EVEX.128.F2.0F38.Wy F5 /r"}, + {"apx": "pext W:ry, R:ry, R:my/ry" , "op": "[RVM] EVEX.128.F3.0F38.Wy F5 /r"}, + {"apx": "rorx W:ry, R:my/ry, imm8" , "op": "[RM ] EVEX.128.F2.0F3A.Wy F0 /r ib"}, + {"apx": "sarx W:ry, R:my/ry, R:ry" , "op": "[RMV] EVEX.128.F3.0F38.Wy F7 /r"}, + {"apx": "shlx W:ry, R:my/ry, R:ry" , "op": "[RMV] EVEX.128.66.0F38.Wy F7 /r"}, + {"apx": "shrx W:ry, R:my/ry, R:ry" , "op": "[RMV] EVEX.128.F2.0F38.Wy F7 /r"} + ]}, + + {"category": "GP GP_EXT", "ext": "CMPCCXADD APX_F", "instructions": [ + {"apx": "cmpbxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E2 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpbexadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E6 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmplxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy EC !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmplexadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy EE !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpnbxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E3 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpnbexadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E7 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpnlxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy ED !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpnlexadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy EF !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpnoxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E1 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpnpxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy EB !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpnsxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E9 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpnzxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E5 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpoxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E0 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmppxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy EA !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpsxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E8 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"}, + {"apx": "cmpzxadd X:my, X:ry, R:ry" , "op": "[MRV] EVEX.128.66.0F38.Wy E4 !(11):rrr:bbb", "io": "OF=W SD=W ZF=W AF=W PF=W CF=W"} + ]}, + + {"category": "GP GP_EXT", "ext": "LZCNT APX_F", "instructions": [ + {"apx": "lzcnt{nf} w:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv F5 /r" , "io": "OF=U SF=U ZF=W AF=U PF=U CF=W"} + ]}, + + {"category": "GP GP_EXT", "ext": "MOVBE APX_F", "instructions": [ + {"apx": "movbe w:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 60 /r"}, + {"apx": "movbe w:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 61 /r"} + ]}, + + {"category": "GP GP_EXT", "ext": "MOVDIR64B APX_F", "instructions": [ + {"apx": "movdir64b W:m512(es:r64), R:m512" , "op": "[RM ] EVEX.LLZ.66.MAP4.W0 F8 !(11):rrr:bbb"} + ]}, + + {"category": "GP GP_EXT", "ext": "MOVDIRI APX_F", "instructions": [ + {"apx": "movdiri W:my, R:ry" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.W0 F9 !(11):rrr:bbb"} + ]}, + + {"category": "GP GP_EXT", "ext": "POPCNT APX_F", "instructions": [ + {"apx": "popcnt{nf} w:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.LLZ.Pv.MAP4.Wv 88 /r" , "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"} + ]}, + + {"category": "GP GP_EXT", "ext": "VMX APX_F", "instructions": [ + {"apx": "invept R:r64, R:m128" , "op": "[RM ] EVEX.ND=0.LLZ.F3.MAP4.WIG F0 !(11):rrr:bbb"}, + {"apx": "invvpid R:r64, R:m128" , "op": "[RM ] EVEX.ND=0.LLZ.F3.MAP4.WIG F1 !(11):rrr:bbb"} + ]}, + + {"category": "GP GP_EXT", "ext": "INVPCID APX_F", "instructions": [ + {"apx": "invpcid R:r64, R:m128" , "op": "[RM ] EVEX.ND=0.LLZ.F3.MAP4.WIG F2 !(11):rrr:bbb"} + ]}, + + {"category": "GP GP_EXT", "ext": "ENQCMD APX_F", "instructions": [ + {"apx": "enqcmd W:m512(es:r64), R:m512" , "op": "[RM ] EVEX.ND=0.LLZ.F2.MAP4.W? F8 !(11):rrr:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"}, + {"apx": "enqcmds W:m512(es:r64), R:m512" , "op": "[RM ] EVEX.ND=0.LLZ.F3.MAP4.W? F8 !(11):rrr:bbb", "io": "OF=0 SF=0 ZF=W AF=0 PF=0 CF=0"} + ]}, + + {"category": "GP GP_EXT", "ext": "USER_MSR", "instructions": [ + {"x64": "urdmsr W:r64, R:r64" , "op": "[MR ] F2 0F 38 F8 11:rrr:bbb"}, + {"x64": "urdmsr W:r64, imm32" , "op": "[M ] VEX.128.F2.MAP7.W0 F8 11:000:bbb id"}, + {"x64": "uwrmsr R:r64, R:r64" , "op": "[RM ] F3 0F 38 F8 11:rrr:bbb"}, + {"x64": "uwrmsr imm32, R:r64" , "op": "[M ] VEX.128.F3.MAP7.W0 F8 11:000:bbb id"} + ]}, + + {"category": "GP GP_EXT", "ext": "USER_MSR APX_F", "instructions": [ + {"apx": "urdmsr r64, r64" , "op": "[MR ] EVEX.ND=0.LLZ.F2.MAP4.W0 F8 11:rrr:bbb"}, + {"apx": "urdmsr r64, imm32" , "op": "[M ] EVEX.128.F2.MAP7.W0 F8 11:000:bbb id"}, + {"apx": "uwrmsr r64, r64" , "op": "[RM ] EVEX.ND=0.LLZ.F3.MAP4.W0 F8 11:rrr:bbb"}, + {"apx": "uwrmsr imm32, r64" , "op": "[M ] EVEX.128.F3.MAP7.W0 F8 11:000:bbb id"} + ]}, + + {"category": "GP GP_EXT", "ext": "CET_SS APX_F", "instructions": [ + {"apx": "wrssd W:m32, R:r32" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.W0 66 !(11):rrr:bbb"}, + {"apx": "wrssq W:m64, R:r64" , "op": "[MR ] EVEX.ND=0.LLZ.NP.MAP4.W1 66 !(11):rrr:bbb"}, + {"apx": "wrussd W:m32, R:r32" , "op": "[MR ] EVEX.ND=0.LLZ.66.MAP4.W0 65 !(11):rrr:bbb"}, + {"apx": "wrussq W:m64, R:r64" , "op": "[MR ] EVEX.ND=0.LLZ.66.MAP4.W1 65 !(11):rrr:bbb"} + ]}, + + {"category": "AVX512 MASK", "ext": "AVX512_F APX_F", "instructions": [ + {"apx": "kmovw W:k[15:0], k[15:0]/m16" , "op": "[RM ] EVEX.128.NP.0F.W0 90 /r"}, + {"apx": "kmovw W:k[15:0], r32[15:0]" , "op": "[RM ] EVEX.128.NP.0F.W0 92 11:rrr:bbb"}, + {"apx": "kmovw W:m16, k[15:0]" , "op": "[MR ] EVEX.128.NP.0F.W0 91 !(11):rrr:bbb"}, + {"apx": "kmovw W:r32[15:0], k[15:0]" , "op": "[RM ] EVEX.128.NP.0F.W0 93 11:rrr:bbb"} + ]}, + + {"category": "AVX512 MASK", "ext": "AVX512_BW APX_F", "instructions": [ + {"apx": "kmovd W:r32, k[31:0]" , "op": "[RM ] EVEX.128.F2.0F.W0 93 11:rrr:bbb"}, + {"apx": "kmovd W:k[31:0], k[31:0]/m32" , "op": "[RM ] EVEX.128.66.0F.W1 90 /r"}, + {"apx": "kmovd W:m32, k[31:0]" , "op": "[MR ] EVEX.128.66.0F.W1 91 !(11):rrr:bbb"}, + {"apx": "kmovd W:k[31:0], r32" , "op": "[RM ] EVEX.128.F2.0F.W0 92 11:rrr:bbb"}, + {"apx": "kmovq W:k, k/m64" , "op": "[RM ] EVEX.128.NP.0F.W1 90 /r"}, + {"apx": "kmovq W:k, r64" , "op": "[RM ] EVEX.128.F2.0F.W1 92 11:rrr:bbb"}, + {"apx": "kmovq W:m64, k" , "op": "[MR ] EVEX.128.NP.0F.W1 91 !(11):rrr:bbb"}, + {"apx": "kmovq W:r64, k" , "op": "[RM ] EVEX.128.F2.0F.W1 93 11:rrr:bbb"} + ]}, + + {"category": "AVX512 MASK", "ext": "AVX512_DQ APX_F", "instructions": [ + {"apx": "kmovb W:k[7:0], k[7:0]/m8" , "op": "[RM ] EVEX.128.66.0F.W0 90 /r"}, + {"apx": "kmovb W:k[7:0], r32[7:0]" , "op": "[RM ] EVEX.128.66.0F.W0 92 11:rrr:bbb"}, + {"apx": "kmovb W:m8, k[7:0]" , "op": "[MR ] EVEX.128.66.0F.W0 91 !(11):rrr:bbb"}, + {"apx": "kmovb W:r32[7:0], k[7:0]" , "op": "[RM ] EVEX.128.66.0F.W0 93 11:rrr:bbb"} + ]}, + + {"category": "GP GP_EXT", "ext": "APX_F", "instructions": [ + {"x64": "ccmpb dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpb dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpb dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpb dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpb dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpbe dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpbe dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpbe dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpbe dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpbe dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpf dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpf dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpf dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpf dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpf dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpf dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpf dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpl dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpl dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpl dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpl dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpl dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmple dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmple dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmple dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmple dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmple dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmple dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmple dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpnb dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpnb dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpnb dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpnb dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpnb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpnb dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpnb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpnbe dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpnbe dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpnbe dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpnbe dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpnbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpnbe dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpnbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpnl dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpnl dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpnl dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpnl dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpnl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpnl dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpnl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpnle dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpnle dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpnle dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpnle dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpnle dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpnle dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpnle dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpno dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpno dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpno dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpno dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpno dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpno dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpno dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpns dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpns dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpns dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpns dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpns dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpns dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpns dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpnz dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpnz dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpnz dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpnz dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpnz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpnz dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpnz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpo dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpo dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpo dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpo dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpo dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpo dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpo dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmps dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmps dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmps dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmps dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmps dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmps dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmps dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpt dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpt dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpt dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpt dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpt dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpt dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpt dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "ccmpz dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG 38 /r" }, + {"x64": "ccmpz dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv 39 /r" }, + {"x64": "ccmpz dfv, R:r8, R:r8/m8" , "op": "[RM ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG 3A /r" }, + {"x64": "ccmpz dfv, R:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv 3B /r" }, + {"x64": "ccmpz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG 80 /7 ib" }, + {"x64": "ccmpz dfv, R:rv/mv, imms8" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv 83 /7 ib" }, + {"x64": "ccmpz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv 81 /7 iv" }, + {"x64": "cfcmovb W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 42 /r" , "io": "CF=R"}, + {"x64": "cfcmovb W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 42 /r" , "io": "CF=R"}, + {"x64": "cfcmovb W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 42 /r" , "io": "CF=R"}, + {"x64": "cfcmovb W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 42 /r" , "io": "CF=R"}, + {"x64": "cfcmovbe W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 46 /r" , "io": "CF=R ZF=R"}, + {"x64": "cfcmovbe W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 46 /r" , "io": "CF=R ZF=R"}, + {"x64": "cfcmovbe W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 46 /r" , "io": "CF=R ZF=R"}, + {"x64": "cfcmovbe W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 46 /r" , "io": "CF=R ZF=R"}, + {"x64": "cfcmovl W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4C /r" , "io": "SF=R OF=R"}, + {"x64": "cfcmovl W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4C /r" , "io": "SF=R OF=R"}, + {"x64": "cfcmovl W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4C /r" , "io": "SF=R OF=R"}, + {"x64": "cfcmovl W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4C /r" , "io": "SF=R OF=R"}, + {"x64": "cfcmovle W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4E /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "cfcmovle W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4E /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "cfcmovle W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4E /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "cfcmovle W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4E /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "cfcmovnb W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 43 /r" , "io": "CF=R"}, + {"x64": "cfcmovnb W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 43 /r" , "io": "CF=R"}, + {"x64": "cfcmovnb W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 43 /r" , "io": "CF=R"}, + {"x64": "cfcmovnb W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 43 /r" , "io": "CF=R"}, + {"x64": "cfcmovnbe W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 47 /r" , "io": "CF=R ZF=R"}, + {"x64": "cfcmovnbe W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 47 /r" , "io": "CF=R ZF=R"}, + {"x64": "cfcmovnbe W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 47 /r" , "io": "CF=R ZF=R"}, + {"x64": "cfcmovnbe W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 47 /r" , "io": "CF=R ZF=R"}, + {"x64": "cfcmovnl W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4D /r" , "io": "SF=R OF=R"}, + {"x64": "cfcmovnl W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4D /r" , "io": "SF=R OF=R"}, + {"x64": "cfcmovnl W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4D /r" , "io": "SF=R OF=R"}, + {"x64": "cfcmovnl W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4D /r" , "io": "SF=R OF=R"}, + {"x64": "cfcmovnle W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4F /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "cfcmovnle W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4F /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "cfcmovnle W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4F /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "cfcmovnle W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4F /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "cfcmovno W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 41 /r" , "io": "OF=R"}, + {"x64": "cfcmovno W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 41 /r" , "io": "OF=R"}, + {"x64": "cfcmovno W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 41 /r" , "io": "OF=R"}, + {"x64": "cfcmovno W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 41 /r" , "io": "OF=R"}, + {"x64": "cfcmovnp W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4B /r" , "io": "PF=R"}, + {"x64": "cfcmovnp W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4B /r" , "io": "PF=R"}, + {"x64": "cfcmovnp W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4B /r" , "io": "PF=R"}, + {"x64": "cfcmovnp W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4B /r" , "io": "PF=R"}, + {"x64": "cfcmovns W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 49 /r" , "io": "SF=R"}, + {"x64": "cfcmovns W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 49 /r" , "io": "SF=R"}, + {"x64": "cfcmovns W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 49 /r" , "io": "SF=R"}, + {"x64": "cfcmovns W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 49 /r" , "io": "SF=R"}, + {"x64": "cfcmovnz W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 45 /r" , "io": "ZF=R"}, + {"x64": "cfcmovnz W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 45 /r" , "io": "ZF=R"}, + {"x64": "cfcmovnz W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 45 /r" , "io": "ZF=R"}, + {"x64": "cfcmovnz W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 45 /r" , "io": "ZF=R"}, + {"x64": "cfcmovo W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 40 /r" , "io": "OF=R"}, + {"x64": "cfcmovo W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 40 /r" , "io": "OF=R"}, + {"x64": "cfcmovo W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 40 /r" , "io": "OF=R"}, + {"x64": "cfcmovo W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 40 /r" , "io": "OF=R"}, + {"x64": "cfcmovp W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 4A /r" , "io": "PF=R"}, + {"x64": "cfcmovp W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4A /r" , "io": "PF=R"}, + {"x64": "cfcmovp W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 4A /r" , "io": "PF=R"}, + {"x64": "cfcmovp W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 4A /r" , "io": "PF=R"}, + {"x64": "cfcmovs W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 48 /r" , "io": "SF=R"}, + {"x64": "cfcmovs W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 48 /r" , "io": "SF=R"}, + {"x64": "cfcmovs W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 48 /r" , "io": "SF=R"}, + {"x64": "cfcmovs W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 48 /r" , "io": "SF=R"}, + {"x64": "cfcmovz W:rv, R:rv/mv" , "op": "[RM ] EVEX.ND=0.NF=0.LLZ.Pv.MAP4.Wv 44 /r" , "io": "ZF=R"}, + {"x64": "cfcmovz W:rv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 44 /r" , "io": "ZF=R"}, + {"x64": "cfcmovz W?:mv, R:rv" , "op": "[MR ] EVEX.ND=0.NF=1.LLZ.Pv.MAP4.Wv 44 /r" , "io": "ZF=R"}, + {"x64": "cfcmovz W:rv, R:rv, R?:rv/mv" , "op": "[VRM] EVEX.ND=1.NF=1.LLZ.Pv.MAP4.Wv 44 /r" , "io": "ZF=R"}, + {"x64": "ctestb dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestb dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=2.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestbe dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestbe dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=6.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestf dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestf dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestf dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestf dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestf dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestf dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=A.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestl dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestl dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=C.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestle dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestle dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestle dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestle dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestle dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestle dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=E.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestnb dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestnb dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestnb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestnb dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestnb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestnb dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=3.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestnbe dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestnbe dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestnbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestnbe dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestnbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestnbe dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=7.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestnl dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestnl dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestnl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestnl dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestnl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestnl dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=D.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestnle dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestnle dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestnle dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestnle dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestnle dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestnle dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=F.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestno dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestno dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestno dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestno dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestno dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestno dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=1.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestns dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestns dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestns dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestns dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestns dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestns dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=9.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestnz dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestnz dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestnz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestnz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestnz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestnz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=5.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctesto dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctesto dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctesto dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctesto dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctesto dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctesto dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=0.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctests dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctests dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctests dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctests dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctests dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctests dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=8.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestt dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestt dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestt dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestt dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestt dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestt dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=B.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "ctestz dfv, R:r8/m8, R:r8" , "op": "[MR ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG 84 /r" }, + {"x64": "ctestz dfv, R:rv/mv, R:rv" , "op": "[MR ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv 85 /r" }, + {"x64": "ctestz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG F6 /0 ib" }, + {"x64": "ctestz dfv, R:r8/m8, imm8" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.NP.MAP4.WIG F6 /1 ib" }, + {"x64": "ctestz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv F7 /0 iv" }, + {"x64": "ctestz dfv, R:rv/mv, immv" , "op": "[M ] EVEX.ND=0.SCC=4.LLZ.Pv.MAP4.Wv F7 /1 iv" }, + {"x64": "jmpabs imm64" , "op": "[OP] NO67 NP REX2.MAP0.W0 A1 iq"}, + {"x64": "pop2 W:r64, W:r64" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.W0 8F 11:000:bbb"}, + {"x64": "pop2p W:r64, W:r64" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.W1 8F 11:000:bbb"}, + {"x64": "popp W:r64" , "op": "[OP] REX2.MAP0.W1 58+r"}, + {"x64": "push2 R:r64, R:r64" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.W0 FF 11:110:bbb"}, + {"x64": "push2p R:r64, R:r64" , "op": "[VM ] EVEX.ND=1.LLZ.NP.MAP4.W1 FF 11:110:bbb"}, + {"x64": "pushp R:r64" , "op": "[OP] REX2.MAP0.W1 50+r"}, + {"x64": "setb w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 42 /r" , "io": "CF=R"}, + {"x64": "setbe w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 46 /r" , "io": "CF=R ZF=R"}, + {"x64": "setl w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4C /r" , "io": "SF=R OF=R"}, + {"x64": "setle w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4E /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "setnb w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 43 /r" , "io": "CF=R"}, + {"x64": "setnbe w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 47 /r" , "io": "CF=R ZF=R"}, + {"x64": "setnl w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4D /r" , "io": "SF=R OF=R"}, + {"x64": "setnle w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4F /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "setno w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 41 /r" , "io": "OF=R"}, + {"x64": "setnp w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4B /r" , "io": "PF=R"}, + {"x64": "setns w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 49 /r" , "io": "SF=R"}, + {"x64": "setnz w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 45 /r" , "io": "ZF=R"}, + {"x64": "seto w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 40 /r" , "io": "OF=R"}, + {"x64": "setp w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 4A /r" , "io": "PF=R"}, + {"x64": "sets w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 48 /r" , "io": "SF=R"}, + {"x64": "setz w:r8/m8" , "op": "[M ] EVEX.ND=0.LLZ.F2.MAP4.WIG 44 /r" , "io": "ZF=R"}, + {"x64": "setzub W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 42 /r" , "io": "CF=R"}, + {"x64": "setzube W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 46 /r" , "io": "CF=R ZF=R"}, + {"x64": "setzul W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4C /r" , "io": "SF=R OF=R"}, + {"x64": "setzule W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4E /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "setzunb W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 43 /r" , "io": "CF=R"}, + {"x64": "setzunbe W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 47 /r" , "io": "CF=R ZF=R"}, + {"x64": "setzunl W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4D /r" , "io": "SF=R OF=R"}, + {"x64": "setzunle W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4F /r" , "io": "ZF=R SF=R OF=R"}, + {"x64": "setzuno W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 41 /r" , "io": "OF=R"}, + {"x64": "setzunp W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4B /r" , "io": "PF=R"}, + {"x64": "setzuns W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 49 /r" , "io": "SF=R"}, + {"x64": "setzunz W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 45 /r" , "io": "ZF=R"}, + {"x64": "setzuo W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 40 /r" , "io": "OF=R"}, + {"x64": "setzup W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 4A /r" , "io": "PF=R"}, + {"x64": "setzus W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 48 /r" , "io": "SF=R"}, + {"x64": "setzuz W:r8" , "op": "[M ] EVEX.ND=1.LLZ.F2.MAP4.WIG 44 /r" , "io": "ZF=R"} + ]}, + + {"category": "AMX", "ext": "AMX_TILE APX_F", "instructions": [ + {"apx": "ldtilecfg R:m512" , "op": "[M ] EVEX.128.NP.0F38.W0 49 !(11):000:bbb"}, + {"apx": "sttilecfg W:m512" , "op": "[M ] EVEX.128.66.0F38.W0 49 !(11):000:bbb"}, + {"apx": "tileloadd W:tmm, R:tmem" , "op": "[RM ] EVEX.128.F2.0F38.W0 4B !(11):rrr:100"}, + {"apx": "tileloaddt1 W:tmm, R:tmem" , "op": "[RM ] EVEX.128.66.0F38.W0 4B !(11):rrr:100"}, + {"apx": "tilestored W:tmem, R:tmm" , "op": "[MR ] EVEX.128.F3.0F38.W0 4B !(11):rrr:100"} ]} ], + "aliases": { + "ccmpb" : {"aliases": ["ccmpnae", "ccmpc" ], "format": "ccmp.b|nae|c" , "sign": "u"}, + "ccmpbe" : {"aliases": ["ccmpna" ], "format": "ccmp.be|na" , "sign": "u"}, + "ccmpl" : {"aliases": ["ccmpnge" ], "format": "ccmp.l|nge" , "sign": "s"}, + "ccmple" : {"aliases": ["ccmpng" ], "format": "ccmp.le|ng" , "sign": "s"}, + "ccmpnb" : {"aliases": ["ccmpae", "ccmpnc" ], "format": "ccmp.nb|ae|nc" , "sign": "u"}, + "ccmpnbe" : {"aliases": ["ccmpa" ], "format": "ccmp.nbe|a" , "sign": "u"}, + "ccmpnl" : {"aliases": ["ccmpge" ], "format": "ccmp.nl|ge" , "sign": "s"}, + "ccmpnle" : {"aliases": ["ccmpg" ], "format": "ccmp.nle|g" , "sign": "s"}, + "ccmpnz" : {"aliases": ["ccmpne" ], "format": "ccmp.nz|ne" , "sign": "_"}, + "ccmpz" : {"aliases": ["ccmpe" ], "format": "ccmp.z|e" , "sign": "_"}, + + "cfcmovb" : {"aliases": ["cfcmovnae", "cfcmovc"], "format": "cfmov.b|nae|c" , "sign": "u"}, + "cfcmovbe" : {"aliases": ["cfcmovna" ], "format": "cfmov.be|na" , "sign": "u"}, + "cfcmovl" : {"aliases": ["cfcmovnge" ], "format": "cfmov.l|nge" , "sign": "s"}, + "cfcmovle" : {"aliases": ["cfcmovng" ], "format": "cfmov.le|ng" , "sign": "s"}, + "cfcmovnb" : {"aliases": ["cfcmovae", "cfcmovnc"], "format": "cfmov.nb|ae|nc" , "sign": "u"}, + "cfcmovnbe": {"aliases": ["cfcmova" ], "format": "cfmov.nbe|a" , "sign": "u"}, + "cfcmovnl" : {"aliases": ["cfcmovge" ], "format": "cfmov.nl|ge" , "sign": "s"}, + "cfcmovnle": {"aliases": ["cfcmovg" ], "format": "cfmov.nle|g" , "sign": "s"}, + "cfcmovnp" : {"aliases": ["cfcmovpo" ], "format": "cfmov.np|po" , "sign": "_"}, + "cfcmovnz" : {"aliases": ["cfcmovne" ], "format": "cfmov.nz|ne" , "sign": "_"}, + "cfcmovp" : {"aliases": ["cfcmovpe" ], "format": "cfmov.p|pe" , "sign": "_"}, + "cfcmovz" : {"aliases": ["cfcmove" ], "format": "cfmov.z|e" , "sign": "_"}, + + "cmovb" : {"aliases": ["cmovnae", "cmovc" ], "format": "cmov.b|nae|c" , "sign": "u"}, + "cmovbe" : {"aliases": ["cmovna" ], "format": "cmov.be|na" , "sign": "u"}, + "cmovl" : {"aliases": ["cmovnge" ], "format": "cmov.l|nge" , "sign": "s"}, + "cmovle" : {"aliases": ["cmovng" ], "format": "cmov.le|ng" , "sign": "s"}, + "cmovnb" : {"aliases": ["cmovae", "cmovnc" ], "format": "cmov.nb|ae|nc" , "sign": "u"}, + "cmovnbe" : {"aliases": ["cmova" ], "format": "cmov.nbe|a" , "sign": "u"}, + "cmovnl" : {"aliases": ["cmovge" ], "format": "cmov.nl|ge" , "sign": "s"}, + "cmovnle" : {"aliases": ["cmovg" ], "format": "cmov.nle|g" , "sign": "s"}, + "cmovnp" : {"aliases": ["cmovpo" ], "format": "cmov.np|po" , "sign": "_"}, + "cmovnz" : {"aliases": ["cmovne" ], "format": "cmov.nz|ne" , "sign": "_"}, + "cmovp" : {"aliases": ["cmovpe" ], "format": "cmov.p|pe" , "sign": "_"}, + "cmovz" : {"aliases": ["cmove" ], "format": "cmov.z|e" , "sign": "_"}, + + "ctestb" : {"aliases": ["ctestnae", "ctestc" ], "format": "ctest.b|nae|c" , "sign": "u"}, + "ctestbe" : {"aliases": ["ctestna" ], "format": "ctest.be|na" , "sign": "u"}, + "ctestl" : {"aliases": ["ctestnge" ], "format": "ctest.l|nge" , "sign": "s"}, + "ctestle" : {"aliases": ["ctestng" ], "format": "ctest.le|ng" , "sign": "s"}, + "ctestnb" : {"aliases": ["ctestae", "ctestnc" ], "format": "ctest.nb|ae|nc" , "sign": "u"}, + "ctestnbe" : {"aliases": ["ctesta" ], "format": "ctest.nbe|a" , "sign": "u"}, + "ctestnl" : {"aliases": ["ctestge" ], "format": "ctest.nl|ge" , "sign": "s"}, + "ctestnle" : {"aliases": ["ctestg" ], "format": "ctest.nle|g" , "sign": "s"}, + "ctestnz" : {"aliases": ["ctestne" ], "format": "ctest.nz|ne" , "sign": "_"}, + "ctestz" : {"aliases": ["cteste" ], "format": "ctest.z|e" , "sign": "_"}, + + "jb" : {"aliases": ["jnae", "jc" ], "format": "jb|jnae|jc" , "sign": "u"}, + "jbe" : {"aliases": ["jna" ], "format": "jbe|jna" , "sign": "u"}, + "jl" : {"aliases": ["jnge" ], "format": "jl|jnge" , "sign": "s"}, + "jle" : {"aliases": ["jng" ], "format": "jle|jng" , "sign": "s"}, + "jnb" : {"aliases": ["jae", "jnc" ], "format": "jnb|jae|jnc" , "sign": "u"}, + "jnbe" : {"aliases": ["ja" ], "format": "jnbe|ja" , "sign": "u"}, + "jnl" : {"aliases": ["jge" ], "format": "jnl|jge" , "sign": "s"}, + "jnle" : {"aliases": ["jg" ], "format": "jnle|jg" , "sign": "s"}, + "jnp" : {"aliases": ["jpo" ], "format": "jnp|jpo" , "sign": "_"}, + "jnz" : {"aliases": ["jne" ], "format": "jnz|jne" , "sign": "_"}, + "jp" : {"aliases": ["jpe" ], "format": "jp|jpe" , "sign": "_"}, + "jz" : {"aliases": ["je" ], "format": "jz|je" , "sign": "_"}, + + "setb" : {"aliases": ["setnae", "setc" ], "format": "set.b|nae|c" , "sign": "u"}, + "setbe" : {"aliases": ["setna" ], "format": "set.be|na" , "sign": "u"}, + "setl" : {"aliases": ["setnge" ], "format": "set.l|nge" , "sign": "s"}, + "setle" : {"aliases": ["setng" ], "format": "set.le|ng" , "sign": "s"}, + "setnb" : {"aliases": ["setae", "setnc" ], "format": "set.nb|ae|nc" , "sign": "u"}, + "setnbe" : {"aliases": ["seta" ], "format": "set.nbe|a" , "sign": "u"}, + "setnl" : {"aliases": ["setge" ], "format": "set.nl|ge" , "sign": "s"}, + "setnle" : {"aliases": ["setg" ], "format": "set.nle|g" , "sign": "s"}, + "setnp" : {"aliases": ["setpo" ], "format": "set.np|po" , "sign": "_"}, + "setnz" : {"aliases": ["setne" ], "format": "set.nz|ne" , "sign": "_"}, + "setp" : {"aliases": ["setpe" ], "format": "set.p|pe" , "sign": "_"}, + "setz" : {"aliases": ["sete" ], "format": "set.z|e" , "sign": "_"}, + + "setzub" : {"aliases": ["setzunae", "setzuc" ], "format": "setzu.b|nae|c" , "sign": "u"}, + "setzube" : {"aliases": ["setzuna" ], "format": "setzu.be|na" , "sign": "u"}, + "setzul" : {"aliases": ["setzunge" ], "format": "setzu.l|nge" , "sign": "s"}, + "setzule" : {"aliases": ["setzung" ], "format": "setzu.le|ng" , "sign": "s"}, + "setzunb" : {"aliases": ["setzuae", "setzunc" ], "format": "setzu.nb|ae|nc" , "sign": "u"}, + "setzunbe" : {"aliases": ["setzua" ], "format": "setzu.nbe|a" , "sign": "u"}, + "setzunl" : {"aliases": ["setzuge" ], "format": "setzu.nl|ge" , "sign": "s"}, + "setzunle" : {"aliases": ["setzug" ], "format": "setzu.nle|g" , "sign": "s"}, + "setzunp" : {"aliases": ["setzupo" ], "format": "setzu.np|po" , "sign": "_"}, + "setzunz" : {"aliases": ["setzune" ], "format": "setzu.nz|ne" , "sign": "_"}, + "setzup" : {"aliases": ["setzupe" ], "format": "setzu.p|pe" , "sign": "_"}, + "setzuz" : {"aliases": ["setzue" ], "format": "setzu.z|e" , "sign": "_"}, + + "fwait" : {"aliases": ["wait" ], "format": "fwait"}, + "shl" : {"aliases": ["sal" ], "format": "shl"} + }, + "postproc": [ {"group": "Control Flow", "instructions": [ - {"inst": "call lcall", "control": "call"}, - {"inst": "iret iretd iretq", "control": "return"}, - {"inst": "jae jnb jnc jo jno jb jnae jc je jz jne jnz jbe jna ja jnbe js jns jp jpe jnp jpo jl jnge jge jnl jle jng jg jnle jecxz", "control": "branch"}, - {"inst": "jmp ljmp", "control": "jump"}, - {"inst": "loop loope loopne", "control": "branch"}, - {"inst": "ret retf", "control": "return"} + {"name": "call lcall", "control": "call"}, + {"name": "iret iretd iretq", "control": "return"}, + {"name": "jb jnb jz jnz jbe jnbe jp jnp jl jnl jle jnle jecxz", "control": "branch"}, + {"name": "jmp jmpabs ljmp", "control": "jump"}, + {"name": "loop loope loopne", "control": "branch"}, + {"name": "ret retf", "control": "return"} ]}, {"group": "Encoding Preference", "instructions": [ - {"inst": "vcvtneps2bf16", "encodingPreference": "EVEX"}, - {"inst": "vpmadd52huq vpmadd52luq", "encodingPreference": "EVEX"}, - {"inst": "vpdpbusd vpdpbusds vpdpwssd vpdpwssds", "encodingPreference": "EVEX"} + {"name": "vcvtneps2bf16", "encodingPreference": "EVEX"}, + {"name": "vpmadd52huq vpmadd52luq", "encodingPreference": "EVEX"}, + {"name": "vpdpbusd vpdpbusds vpdpwssd vpdpwssds", "encodingPreference": "EVEX"} ]} ] } diff --git a/db/isa_x86.md b/db/isa_x86.md new file mode 100644 index 0000000..7a761d7 --- /dev/null +++ b/db/isa_x86.md @@ -0,0 +1,145 @@ +X86 ISA - JSON Database Documentation +------------------------------------- + +This file provides a documentation of isa_x86.json file, which contains a compact X86 and X86_64 instruction database. The database has been created from several manuals from Intel and AMD, which describes the encoding of instructions and other properties. The database tries to keep the instruction and opcode formats compatible with the database, however, in cases where applicable it tries to simplify it (for example merging instructions that all use either XMM, YMM, or ZMM registers, etc...). + +## Instruction Category + +Each set of instructions start with category group, which looks like the following: + +```json +{"category": "", "ext": "", /* flags, */ "instructions": [ + /* (instruction records) */ +]} +``` + +Fields: + + - `category` - describes a single or multiple categories this instruction belongs to. In general the database is written in a way to provide "baseline" and "extended" categories, so have the following categories used to distinguish between different set of instructions: + - `GP` - General purpose instructions. + - `GP_EXT` - Extensions to general purpose instructions (such as BMI, POPCNT, etc...). + - `MMX` - MMX and 3DNOW instructions (in general instructions using MM registers). + - `SSE` - SSE to SSE4.2 instructions, including other extensions that don't use VEX/EVEX prefixes. + - `AVX` - AVX, AVX2, and other instructions that use SIMD registers (XMM, YMM) and VEX prefix. + - `AVX512` - AVX512 instructions. + + - `ext` (optional) - describes extensions required to execute the instruction. When multiple extensions are in the list it means ALL of them must be available. For example `AESNI` means that `AESNI` extension is required, `AVX AESNI` means that both `AVX` and `AESNI` extensions are required. + + - `deprecated` (optional) - deprecation flag (either `true` or `false`), by default instructions are not deprecated. + + - `volatile` (optional) - volatility flag (either `true` or `false`), by default instructions are not volatile (note that volatile flag is used for code generators and in general it says that the instruction should not be reordered and nothing above it should move below and vice versa). + + - `instructions` - array of instruction records, one line per instruction. + +## Instruction Record + +A single instruction record looks like the following: + +```json +{"": "", "op": "[] " /*, */ } +``` + +### Architecture Field + +`` field describes the architecture and optionally `APX_F` promoted instruction: + + - `any` - The instruction can run in both 32-bit and 64-bit mode and shares the encoding. + - `x86` - The instruction can only run in 32-bit mode. This in general may be an indication that the instruction was deprecated in 64-bit mode or that the instruction has a different signature in 64-bit mode (some instructions require 32-bit registers in 32-bit mode and 64-bit registers in 64-bit mode, for example) + - `x64` - The instruction can only run in 64-bit mode. + - `apx` - The instruction can only run in 64-bit mode with `APX_F` extension present. This notation is only used for `APX_F` instructions that provide alternative `EVEX` encoding to existing instructions, but not new `APX_F` only instructions. For example `jmpabs` instruction is a new `APX_F` instruction, thus the arch notation it uses is `x64`. + +Explanation: The database uses this "variable" field name to save space and to avoid defining the architecture elsewhere. + +### Instruction Signature + +Instruction signature is composed of the following components: + +``` +[|] | +``` + + - `[|]` (optional) - prefixes and other options: + - `[bnd]` - instruction supports `bnd` prefix (deprecated). + - `[lock]` - instruction supports `lock` prefix. + - `[xacquire]` - instruction supports `xacquire` prefix. + - `[xacqrel]` - instruction supports both `xacquire` and `xrelease` prefixes. + - `[xrelease]` - instruction supports `xrelease` prefix. + - `[rep]` - instruction supports `rep` prefix (or `repe`). + - `[repne]` - instruction supports `repne` prefix. + - `[repIgnore]` - instruction supports `rep` prefix, which is ignored during execution (to support for example `rep ret`). + + - `|` (required) - the name of the instruction possibly followed by aliases if the instruction has them + - if the instruction has aliases, they will be recognized in AsmJit API (the API will provide aliases), but will not have a separate instruction identifier + - for example `cmovz|cmove` is a `cmovz` instruction that has a `cmove` alias. + + - `` (optional): + - When an instruction has multiple operands, they are separated by comma. + - Registers: + - `r8` - 8-bit general purpose register. + - `r16` - 16-bit general purpose register. + - `r32` - 32-bit general purpose register. + - `r64` - 64-bit general purpose register (x64 only). + - `mm` - 64-bit MM register. + - `xmm` - 128-bit XMM register (SSE). + - `ymm` - 256-bit YMM register (AVX) + - `zmm` - 512-bit ZMM register (AVX512/AVX10). + - `k` - 64-bit K register (AVX512/AVX10). + - `tmm` - TMM register (AMX). + - `creg` - Control register. + - `dreg` - Debug register. + - `st(x)` - FPU register. + - `rip` - Instruction pointer register (used during addressing). + - `bnd` - Bounds register (deprecated). + - Memory: + - `mem` - Memory operand without size specified. + - `m8-m512` - Memory operand of a specified size. + - Immediate values + - `imm4` - Signed or unsigned 4-bit immediate value (only used by instructions where the other 4 bits are used to encode additional register operand). + - `imm8` - Signed or unsigned 8-bit immediate value. + - `imm16` - Signed or unsigned 16-bit immediate value. + - `imm32` - Signed or unsigned 32-bit immediate value. + - `imm64` - Signed or unsigned 64-bit immediate value. + - `imms8` - Signed 8-bit immediate value (instructions that sign-extend the immediate value to 32 or 64 bits). + - `immu8` - Unsigned 8-bit immediate value (instructions that zero-extend the immediate value to 32 or 64 bits). + - `immu16` - Unsigned 16-bit immediate value (instructions that zero-extend the immediate value to 32 or 64 bits). + - `imms32` - Signed 32-bit immediate value (instructions that sign-extend the immediate value to 64 bits). + - `immu32` - Unsigned 32-bit immediate value (instructions that zero-extend the immediate value to 64 bits). + - Relative operands (addressing labels and relative locations in code): + - `rel8` - 8-bit signed relative displacement. + - `rel16` - 16-bit signed relative displacement. + - `rel32` - 32-bit signed relative displacement. + - Combining: + - Register and memory operands can be combined, for example `r8/m8` means either 8-bit register or 8-bit memory operand + - Read/Write access: + - The first operand must be decorated by access in a form `[r|w|x]: `: + - `R:` - read access. + - `W:` - write access (overwrites the whole register). + - `w:` - write access (only overwrites an addressed part of the register - 8-bit and 16-bit GP registers use this access). + - `X:` - read/write access (the final write operation overwrites the whole register). + - `x:` - read/write access (the final write operation only overwrites the addressed part of the register - 16-bit GP access). + - The access of the second operand and following operands is implied to be read-only, when not specified explicitly. + - Grouping: + - If the encoding used for multiple register combinations is the same, multiple instructions can be grouped into a single record. + - `GP` Instructions: + - `ry` - either `r32` or `r64`. + - `my` - either `m32` or `m64`. + - `rv` - either `r16`, `r32`, or `r64`. + - `mv` - either `m16`, `m32`, or `m64`. + - `immv` - either `imm16`, `imm32`, or `simm32`. + - All registers must match, example: `add x:rv, rv/mv` - either all `r16/m16`, `r32/m32`, or `r64/m64`. + - When `rv/mv/immv` is used, the instruction must use `66h` prefix (or 66h part of `VEX/EVEX`) when a 16-bit `r16/m16` is used, and `REX.W` (or `W` part of `VEX/EVEX`) when a 64-bit `r64/m64` is used. The immediate expands to `imm16` for instructions working with 16-bit registers, to `imm32` for instructions working with 32-bit registers, and to `simm32` for instructions working with 64-bit registers (32-bit immediate sign extended to 64 bits). + - When `rv/mv` is used with `w` and `x` access option, it only applies to a 16-bit operation, wider operations would use `W` or `X` (this is an architectural constraint that the tool processing the database must be aware of) + - Why `y` and `v`? `ry/my` and `rv/mv` appeared in initial manuals describing `APX_F` extension, so this database is using exactly this notation to group multiple instructions into a single entry. + - `AVX` Instructions: + - `xy/mxy` - either `xmm/m128` or `ymm/m256` register operand. + - All registers must match, example: `vfmadd132pd X:xy, xy, xy/mxy` - either all `xmm/m128` or all `ymm/m256`. + - Why `xy/mxy`? This notation is not used by instruction manuals, but we have found it easy to use and understand. + - `AVX512` and `AVX10` Instructions: + - `xxx/mxxx` - either `xmm[31:0]/m32`, `xmm[63:0]/m64`, or `xmm/m128` register operand. + - `xxy/mxxy` - either `xmm[63:0]/m64`, `xmm/m128`, or `ymm/m256` register operand. + - `xyz/mxyz` - either `xmm/m128`, `ymm/m256`, or `zmm/m512` register operand. + - All registers must match, example: `vvfmadd132pd X:xyz {kz}, xyz, xyz/mxyz/b64 {er}` - either all `xmm/m128`, `ymm/m256`, or `zmm/m512`. + - Embedded rounding `{er}` and `{sae}` are grouped - in AVX512 case only 512-bit operations can use `{er}/{sae}`; in AVX10.2 case both 256-bit and 512-bit operations can use `{er}/{sae}`, but not 128-bit operations - the assembler or the tool processing this data must be aware of this architectural constraint. + - Why `xyz/mxyz`? This notation is not used by instruction manuals, but we have found it easy to use and understand. + + diff --git a/db/package.json b/db/package.json index 8519aad..8b4f5fc 100644 --- a/db/package.json +++ b/db/package.json @@ -1,7 +1,7 @@ { "name": "asmdb", "version": "0.1.0", - "license": "Unlicense", + "license": "Zlib", "engines": { "node": ">=8" }, "description": "Instructions database and utilities for X86/X64 and ARM (THUMB/A32/A64) architectures.", diff --git a/db/x86.js b/db/x86.js index 3de86a1..02a73b8 100644 --- a/db/x86.js +++ b/db/x86.js @@ -1,17 +1,15 @@ // This file is part of AsmJit project // // See asmjit.h or LICENSE.md for license and copyright information -// SPDX-License-Identifier: (Zlib or Unlicense) +// SPDX-License-Identifier: Zlib (function($scope, $as) { "use strict"; -function FAIL(msg) { throw new Error("[X86] " + msg); } - // Import. const base = $scope.base ? $scope.base : require("./base.js"); -const hasOwn = Object.prototype.hasOwnProperty; +const hasOwn = base.hasOwn; const dict = base.dict; const NONE = base.NONE; const Parsing = base.Parsing; @@ -20,11 +18,91 @@ const MapUtils = base.MapUtils; // Export. const x86 = $scope[$as] = {}; +function FAIL(msg) { throw new Error("[X86] " + msg); } + // Database // ======== x86.dbName = "isa_x86.json"; +// Metadata Tables +// =============== + +const ArchGroupInfo = dict({ + "ry": ["ANY", "X64"], + "rv": ["ANY", "ANY", "X64"] +}); + +// Groups are used by instruction tables to group multiple operand combinations into a single record. In general +// X86 and X86_64 instructions can be divided into GP and SIMD groups, where GP groups use `ry/my` syntax to +// specify operation for 16/32/64 bit registers and "xy/mxy"/"xyz/mxyz" groups to specify a SIMD instruction that +// uses either XMM/YMM (AVX) or XMM/YMM/ZMM registers (AVX-512). +const OperandGroupInfo = dict({ + "ry" : { "group": "ry" , "subst": ["r32", "r64"] }, + "my" : { "group": "ry" , "subst": ["m32", "m64"] }, + "axy" : { "group": "ry" , "subst": ["eax", "rax"] }, + "bxy" : { "group": "ry" , "subst": ["ebx", "rbx"] }, + "cxy" : { "group": "ry" , "subst": ["ecx", "rcx"] }, + "dxy" : { "group": "ry" , "subst": ["edx", "rdx"] }, + + "rv" : { "group": "rv" , "subst": ["r16", "r32", "r64"] }, + "mv" : { "group": "rv" , "subst": ["m16", "m32", "m64"] }, + "axv" : { "group": "rv" , "subst": ["ax", "eax", "rax"] }, + "bxv" : { "group": "rv" , "subst": ["bx", "ebx", "rbx"] }, + "cxv" : { "group": "rv" , "subst": ["cx", "ecx", "rcx"] }, + "dxv" : { "group": "rv" , "subst": ["dx", "edx", "rdx"] }, + "immv" : { "group": "rv" , "subst": ["imm16", "imm32", "imms32"] }, + + "xy" : { "group": "xy" , "subst": ["xmm", "ymm"] }, + "mxy" : { "group": "xy" , "subst": ["m128", "m256"] }, + + "xxx" : { "group": "xyz", "subst": ["xmm[31:0]", "xmm[63:0]", "xmm"] }, + "xxy" : { "group": "xyz", "subst": ["xmm[63:0]", "xmm", "ymm"] }, + "xyz" : { "group": "xyz", "subst": ["xmm", "ymm", "zmm"] }, + "mxxx" : { "group": "xyz", "subst": ["m32", "m64", "m128"] }, + "mxxy" : { "group": "xyz", "subst": ["m64", "m128", "m256"] }, + "mxyz" : { "group": "xyz", "subst": ["m128", "m256", "m512"] } +}); + +const OpcodeGroupInfo = dict({ + "Wy" : { "group": "ry" , "subst": ["W0", "W1"] }, + "iv" : { "group": "rv" , "subst": ["iw", "id", "id"] }, + "Pv" : { "group": "rv" , "subst": ["66", "NP", "NP"] }, + "Wv" : { "group": "rv" , "subst": ["W0", "W0", "W1"] } +}); + +// Instruction tables use various notations to specify L/LL field, which is used by VEX/EVEX/XOP encodings. This +// field has 1 bit (VEX/XOP) and 2 bits (EVEX) and in general the notation used is 128/256/512, which determines +// the size of SIMD operation, and this is also the notation we want to convert everything else into. +const OpcodeLLMapping = dict({ + "128": "128", + "256": "256", + "512": "512", + "LZ" : "128", + "LLZ": "128", + "L0" : "128", + "L1" : "256", + "LIG": "LIG", + "Lxy": "xy", + "xyz": "xyz" +}); + +const RegSize = Object.freeze({ + "r8" : 8, + "r8hi": 8, + "r16" : 16, + "r32" : 32, + "r64" : 64, + "mm" : 64, + "xmm" : 128, + "ymm" : 256, + "zmm" : 512, + "tmm" : 512, // Maximum size (64 bytes). + "bnd" : 128, + "k" : 64, + "st" : 80 +}); + // CpuRegs // ======= @@ -32,29 +110,32 @@ x86.dbName = "isa_x86.json"; function buildCpuRegs(defs) { const map = dict(); - for (var type in defs) { + for (let type in defs) { const def = defs[type]; const kind = def.kind; const names = def.names; + const group = def.group; if (def.any) - map[def.any] = { type: type, kind: kind, index: -1 }; + map[def.any] = { type: type, kind: kind, index: -1, group: group }; - for (var i = 0; i < names.length; i++) { - var name = names[i]; - var m = /^([A-Za-z\(\)]+)(\d+)-(\d+)([A-Za-z\(\)]*)$/.exec(name); + if (names) { + for (let i = 0; i < names.length; i++) { + let name = names[i]; + let m = /^([A-Za-z\(\)]+)(\d+)-(\d+)([A-Za-z\(\)]*)$/.exec(name); - if (m) { - var a = parseInt(m[2], 10); - var b = parseInt(m[3], 10); + if (m) { + let a = parseInt(m[2], 10); + let b = parseInt(m[3], 10); - for (var n = a; n <= b; n++) { - const index = m[1] + n + m[4]; - map[index] = { type: type, kind: kind, index: index }; + for (let n = a; n <= b; n++) { + const index = m[1] + n + m[4]; + map[index] = { type: type, kind: kind, index: index }; + } + } + else { + map[name] = { type: type, kind: kind, index: i }; } - } - else { - map[name] = { type: type, kind: kind, index: i }; } } } @@ -68,7 +149,7 @@ function buildCpuRegs(defs) { return map; } -const kCpuRegisters = buildCpuRegs({ +const CpuRegisters = buildCpuRegs({ "r8" : { "kind": "gp" , "any": "r8" , "names": ["al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", "r8-15b"] }, "r8hi": { "kind": "gp" , "names": ["ah", "ch", "dh", "bh"] }, "r16" : { "kind": "gp" , "any": "r16" , "names": ["ax", "cx", "dx", "bx", "sp", "bp", "si", "di", "r8-15w"] }, @@ -91,24 +172,12 @@ const kCpuRegisters = buildCpuRegs({ // asmdb.x86.Utils // =============== -const RegSize = Object.freeze({ - "r8" : 8, - "r8hi": 8, - "r16" : 16, - "r32" : 32, - "r64" : 64, - "mm" : 64, - "xmm" : 128, - "ymm" : 256, - "zmm" : 512, - "tmm" : 512, // Maximum size (64 bytes). - "bnd" : 128, - "k" : 64, - "st" : 80 -}); - // X86/X64 utilities. class Utils { + static groupOf(op) { + return hasOwn(OperandGroupInfo, op) ? OperandGroupInfo[op].group : null; + } + static splitInstructionSignature(s) { let prefixes = []; if (s.startsWith("[")) { @@ -118,12 +187,17 @@ class Utils { s = s.substring(prefixEnd + 1).trim(); } - const nameEnd = s.indexOf(" "); - const names = s.substring(0, nameEnd === -1 ? s.length : nameEnd).split("|"); - const operands = nameEnd === -1 ? "" : s.substring(nameEnd + 1).trim(); + let nameEnd = s.indexOf(" "); + let names = s.substring(0, nameEnd === -1 ? s.length : nameEnd); + let operands = nameEnd === -1 ? "" : s.substring(nameEnd + 1).trim(); + + if (names.endsWith("{nf}")) { + names = names.substring(0, names.length - 4); + prefixes.nf = true; + } return { - names: names, + names: names.split("|"), prefixes: prefixes, operands: operands } @@ -136,33 +210,33 @@ class Utils { // this function is here for compatibility with other instruction sets. static splitOperands(s) { const array = s.split(","); - for (var i = 0; i < array.length; i++) + for (let i = 0; i < array.length; i++) array[i] = array[i].trim(); return array; } // Get whether the string `s` describes a register operand. - static isRegOp(s) { return s && hasOwn.call(kCpuRegisters, s); } + static isRegOp(s) { return s && hasOwn(CpuRegisters, s); } // Get whether the string `s` describes a memory operand. - static isMemOp(s) { return s && /^(?:mem|mib|tmem|moff|(?:m(?:off)?\d+(?:dec|bcd|fp|int)?)|(?:m16_\d+)|(?:vm\d+(?:x|y|z)))$/.test(s); } + static isMemOp(s) { return s && /^(?:mem|mib|tmem|moff||(?:m(?:off)?\d+(?:dec|bcd|fp|int)?)|(?:m16_\d+)|(?:vm\d+(?:x|y|z)))$/.test(s); } // Get whether the string `s` describes an immediate operand. - static isImmOp(s) { return s && /^(?:1|i4|u4|ib|ub|iw|uw|id|ud|if|iq|uq|p16_16|p16_32)$/.test(s); } + static isImmOp(s) { return s && /^(?:1|imm4|imm8|imm16|imm32|imm64|imms8|imms32|immu16|immu32|immv|if|p16_16|p16_32|dfv)$/.test(s); } // Get whether the string `s` describes a relative displacement (label). static isRelOp(s) { return s && /^rel\d+$/.test(s); } // Get a register type of a `s`, returns `null` if the register is unknown. - static regTypeOf(s) { return hasOwn.call(kCpuRegisters, s) ? kCpuRegisters[s].type : null; } + static regTypeOf(s) { return hasOwn(CpuRegisters, s) ? CpuRegisters[s].type : null; } // Get a register kind of a `s`, returns `null` if the register is unknown. - static regKindOf(s) { return hasOwn.call(kCpuRegisters, s) ? kCpuRegisters[s].kind : null; } + static regKindOf(s) { return hasOwn(CpuRegisters, s) ? CpuRegisters[s].kind : null; } // Get a register type of a `s`, returns `null` if the register is unknown and `-1` // if the given string does only represent a register type, but not a specific reg. - static regIndexOf(s) { return hasOwn.call(kCpuRegisters, s) ? kCpuRegisters[s].index : null; } + static regIndexOf(s) { return hasOwn(CpuRegisters, s) ? CpuRegisters[s].index : null; } static regSize(s) { if (s in RegSize) return RegSize[s]; - const reg = kCpuRegisters[s]; + const reg = CpuRegisters[s]; if (reg && reg.type in RegSize) return RegSize[reg.type]; @@ -174,10 +248,17 @@ class Utils { // Handles "ib", "iw", "id", "if", "iq", and also "/is4". static immSize(s) { switch (s) { - case "1" : return 8; - case "i4" : - case "u4" : case "/is4" : return 4; + case "imm4" : return 4; + case "1" : return 8; + case "imm8" : return 8; + case "imm16" : return 16; + case "imm32" : return 32; + case "imm64" : return 64; + case "imms8" : return 8; + case "imms32": return 32; + case "immu16": return 16; + case "immu32": return 32; case "ib" : case "ub" : return 8; case "iw" : @@ -189,7 +270,12 @@ class Utils { case "p16_16": return 32; case "if" : case "p16_32": return 48; - default : return -1; + + // Influences EVEX encoding, not an immediate byte. + case "dfv" : return 0; + + // Invalid immediate. + default : FAIL(`Invalid immediate ${s}`); } } @@ -210,24 +296,43 @@ x86.Utils = Utils; // X86/X64 operand. class Operand extends base.Operand { - constructor(data, defaultAccess) { - super(data); + constructor() { + super(); + this.groupPattern = ""; // Group pattern in case this operand was created from a group. this.memSegment = ""; // Segment specified with register that is used to perform a memory IO. this.memOff = false; // Memory operand is an absolute offset (only a specific version of MOV). this.memFar = false; // Memory is a far pointer (includes segment in first two bytes). this.vsibReg = ""; // AVX VSIB register type (xmm/ymm/zmm). this.vsibSize = -1; // AVX VSIB register size (32/64). this.bcstSize = -1; // AVX-512 broadcast size. + } + + _substituteGroupOp(op, groupIndex) { + const opPart = op.match(/^([A-Za-z]+)/); + if (opPart) { + const groupPattern = Utils.groupOf(opPart[1]); + if (groupPattern) { + this.groupPattern = groupPattern; + return OperandGroupInfo[opPart[1]].subst[groupIndex] + op.substring(opPart[1].length); + } + } + return op; + } + + assignData(data, defaultAccess, groupIndex) { + let s = data; + this.data = data; const type = []; - var s = data; // Handle RWX decorators prefix "[RWwXx]:". - const mAccess = /^([RWwXx])\:/.exec(s); - if (mAccess) { - this.setAccess(mAccess[1]); - s = s.substring(mAccess[0].length); + let access = defaultAccess; + const access_match = /^(R|W|w|X|x)(\?)?\:/.exec(s); + if (access_match) { + // TODO: Conditional access is ignored at the moment. + access = access_match[1]; + s = s.substring(access_match[0].length); } // Handle commutativity attribute. @@ -251,19 +356,19 @@ class Operand extends base.Operand { s = Parsing.clearImplicit(s); } - // Support multiple operands separated by "/" (only used by r/m and i/u). - var ops = s.split("/"); - var oArr = []; + // Support multiple operands separated by "/" (only used by r/m). + let ops = s.split("/"); + let oArr = []; - for (var i = 0; i < ops.length; i++) { - var origOp = ops[i].trim(); - var op = origOp; + for (let i = 0; i < ops.length; i++) { + let origOp = ops[i].trim(); + let op = this._substituteGroupOp(origOp, groupIndex); // Handle range suffix [A] or [A:B]: const mRange = /\[(\d+)\s*(?:\:\s*(\d+)\s*)?\]$/.exec(op); if (mRange) { - var a = parseInt(mRange[1], 10); - var b = parseInt(mRange[2] || String(a), 10); + const a = parseInt(mRange[1], 10); + const b = parseInt(mRange[2] || String(a), 10); if (a < b) FAIL(`Operand '${origOp}' contains invalid range '[${a}:${b}]'`) @@ -274,8 +379,7 @@ class Operand extends base.Operand { op = op.substring(0, op.length - mRange[0].length); } - // Handle a segment specification if this is an implicit register performing - // memory access. + // Handle a segment specification if this is an implicit register performing memory access. const memSegRegM = op.match(/\((ds|es)\:\s*([\w]+)\)$/); if (memSegRegM) { this.memSegment = memSegRegM[1]; @@ -285,16 +389,23 @@ class Operand extends base.Operand { oArr.push(op); - var regIndexRel = 0; + let regIndexRel = 0; if (op.endsWith("+1") || op.endsWith("+2") || op.endsWith("+3")) { regIndexRel = parseInt(op.substr(op.length - 1, 1)); op = op.substring(0, op.length - 2); } + // Group substitution - when a rv/mv instruction uses 'w' or 'x' access it's only used by + // the 16-bit form, 32-bit and 64-bit always use 'W' and 'X' when used in a 'rv/mv' group. + if (this.groupPattern === "rv" && groupIndex > 0 && access !== "R") { + access = access.toUpperCase(); + } + if (Utils.isRegOp(op)) { this.reg = op; this.regType = Utils.regTypeOf(op); this.regIndexRel = regIndexRel; + this.setAccess(access); type.push("reg"); continue; @@ -302,6 +413,7 @@ class Operand extends base.Operand { if (Utils.isMemOp(op)) { this.mem = op; + this.setAccess(access); // Handle memory size. const mOff = /^m(?:off)?(\d+)/.exec(op); @@ -333,12 +445,9 @@ class Operand extends base.Operand { FAIL(`Immediate size mismatch: ${this.imm} != ${size}`); // Sign-extend / zero-extend. - const sign = op.startsWith("i") ? "signed" : "unsigned"; - - if (!this.immSign) - this.immSign = sign; - else if (this.immType !== sign) - this.immSign = "any"; + const sign = op.startsWith("imms") ? "signed" : + op.startsWith("immu") ? "unsigned" : "any"; + this.immSign = sign; if (op === "1") { this.immValue = 1; @@ -373,9 +482,6 @@ class Operand extends base.Operand { this.rwxWidth = opSize; } } - - if (!mAccess && this.isRegOrMem()) - this.setAccess(defaultAccess); } get regSize() { @@ -422,25 +528,30 @@ x86.Operand = Operand; // X86/X64 instruction. class Instruction extends base.Instruction { - constructor(db, data) { + constructor(db) { super(db); - const semicolon = data.op.indexOf(":"); + this.opcode = dict({ + byte : "", // Opcode byte (a single value specified as HEX string "00-FF"). + ri : false, // Instruction opcode is combined with register, "XX+r" or "XX+i". + _67h : false, // Opcode 67h prefix use. + mm : "", // Opcode MM[MMM] part (map). + pp : "", // Opcode PP part. + w : "", // Opcode W field. + l : "", // EVEX.LL (nothing, 128, 256, 512, LIG). + nd : 0, // EVEX.ND (new dest) field (default is false, specified as ND=0 or ND=1). + nf : 0, // EVEX.NF (no flags) field (default is false, specified as NF=0 or NF=1). + scc : "", // EVEX.SCC field (4 bits - condition flags). + mod : "", // MODRM.MOD part (2 bits) - either "xx", "11" or "!(11)". + modr : "", // MODRM.R part (3 bits) - either "rrr" + modrm: "" // MODRM.R/M part - either "bbb" + }); - this.name = data.name; // Instruction name. - this.privilege = "L3"; // Privilege level required to execute the instruction. this.prefix = ""; // Prefix - "", "3DNOW", "EVEX", "VEX", "XOP". - this.opcodeHex = ""; // A single opcode byte as hexadecimal string "00-FF". + this.privilege = "L3"; // Privilege level required to execute the instruction. + this.groupPattern = ""; // Group pattern in case the instruction was created from a group such as "ry", "rv", "xy", "xyz". + this.groupIndex = -1; // Group index. - this.l = ""; // Opcode L field (nothing, 128, 256, 512). - this.w = ""; // Opcode W field. - this.pp = ""; // Opcode PP part. - this.mm = ""; // Opcode MM[MMM] part. - this._67h = false; // Instruction requires a size override prefix. - - this.modR = ""; // Instruction specific payload in ModRM byte (R part), specified as "/0..7". - this.modRM = ""; // Instruction specific payload in ModRM byte (RM part), specified as another opcode byte. - this.ri = false; // Instruction opcode is combined with register, "XX+r" or "XX+i". this.rel = 0; // Displacement ("cb", "cw", and "cd" parts). this.fpuTop = 0; // FPU top index manipulation [-1, 0, 1, 2]. @@ -464,10 +575,31 @@ class Instruction extends base.Instruction { this.consecutiveLead = 0; // Consecutive register leading N other registers. this.prefixes = dict(); // Allowed prefixes. + } - this._assignOperands(data.operands); - this._assignEncoding(semicolon !== -1 ? data.op.substring(0, semicolon) : "NONE"); - this._assignOpcode(semicolon !== -1 ? data.op.substring(semicolon + 1).trim() : data.op.trim()); + _substituteOpcodePart(op, groupIndex) { + if (hasOwn(OpcodeGroupInfo, op)) { + return OpcodeGroupInfo[op].subst[groupIndex]; + } + else { + return op; + } + } + + assignData(data, groupIndex) { + this.name = data.name; + this.groupIndex = groupIndex; + + if (data.tt) + this.tupleType = data.tt; + + const em = data.op.match(/^\[\s*(\w+)\s*\](.*)$/); + const encodingField = em ? em[1] : "NONE"; + const opcodeField = em ? em[2] : data.op; + + this._assignOperands(data.operands, groupIndex); + this._assignEncoding(encodingField); + this._assignOpcode(opcodeField.trim(), groupIndex); for (let k in data) { if (k === "name" || k === "op" || k === "operands") @@ -517,7 +649,7 @@ class Instruction extends base.Instruction { case "er": this.er = true; - this.sae = true; // fall: {er} implies {sae}. + this.sae = true; // {er} implies {sae}. return; case "sae": @@ -534,14 +666,14 @@ class Instruction extends base.Instruction { } } - _assignOperands(s) { + _assignOperands(s, groupIndex) { if (!s) return; // First remove all flags specified as {...}. We put them into `flags` // map and mix with others. This seems to be the best we can do here. for (;;) { - var a = s.indexOf("{"); - var b = s.indexOf("}"); + let a = s.indexOf("{"); + let b = s.indexOf("}"); if (a === -1 || b === -1) break; @@ -553,82 +685,115 @@ class Instruction extends base.Instruction { // Split into individual operands and push them to `operands`. const arr = Utils.splitOperands(s); - for (var i = 0; i < arr.length; i++) { - const operand = new Operand(arr[i].trim(), i === 0 ? "X" : "R"); - if (operand.mem == "tmem") + for (let i = 0; i < arr.length; i++) { + const operand = new Operand(); + operand.assignData(arr[i].trim(), i === 0 ? "X" : "R", groupIndex); + + if (operand.mem == "tmem") { this.tsib = true; + } + + if (operand.groupPattern && this.groupPattern !== operand.groupPattern) { + if (this.groupPattern) { + FAIL(`Instruction ${this.name}: Operand's group pattern mismatch '${this.groupPattern}' != '${operand.groupPattern}'`); + } + this.groupPattern = operand.groupPattern; + } + this.operands.push(operand); } } _assignEncoding(s) { - // Parse 'TUPLE-TYPE' as defined by AVX-512. - var i = s.indexOf("-"); - if (i !== -1) { - this.tupleType = s.substring(i + 1); - s = s.substring(0, i); - } - this.encoding = s; } - _assignOpcode(s) { + _assignOpcode(s, groupIndex) { this.opcodeString = s; - var parts = s.split(" "); - var prefix, comp; - var i; + let parts = s.split(" "); - if (/^(EVEX|VEX|XOP)\./.test(s)) { - // Parse VEX and EVEX encoded instruction. - prefix = parts[0].split("."); + if (/^(VEX|EVEX|XOP)\./.test(s)) { + // Parse VEX/XOP and EVEX encoded instruction, which looks like ".[APX-DATA]...." + let prefix = parts[0].split("."); + this.prefix = prefix[0]; - for (i = 0; i < prefix.length; i++) { - comp = prefix[i]; + for (let i = 1; i < prefix.length; i++) { + let comp = prefix[i]; - // Ignore NP, it's just a placeholder. - if (comp == "NP") + if (/^(Pv|Wv|Wy)$/.test(comp)) { + comp = OpcodeGroupInfo[comp].subst[groupIndex]; + } + + // Process APX EVEX.ND field - ND=0 or ND=1. + if (/^ND=[01]$/.test(comp)) { + this.opcode.nd = comp === "ND=1"; continue; + } - // Process "EVEX", "VEX", and "XOP" prefixes. - if (/^(?:EVEX|VEX|XOP)$/.test(comp)) { this.prefix = comp; continue; } + // Process APX EVEX.NF field - NF=0 or NF=1. + if (/^NF=[01]$/.test(comp)) { + this.opcode.nf = comp === "NF=1"; + continue; + } - // Process `L` field. - if (/^LIG$/ .test(comp)) { this.l = "LIG"; continue; } - if (/^128|L0|LZ$/.test(comp)) { this.l = "128"; continue; } - if (/^256|L1$/ .test(comp)) { this.l = "256"; continue; } - if (/^512$/ .test(comp)) { this.l = "512"; continue; } + // Process APX EVEX.SCC field - SCC=0-F + if (/^SCC=[0-9A-F]$/.test(comp)) { + this.opcode.scc = comp.charAt(5); + continue; + } - // Process `PP` field - 66/F2/F3. + // Process `L/LL` field. + if (hasOwn(OpcodeLLMapping, comp)) { + this.opcode.l = OpcodeLLMapping[comp]; + continue; + } + + // Process `PP` field - 66/F2/F3/NP (NP means no PP field used) if (comp === "P0") { /* ignored, `P` is zero... */ continue; } - if (/^(?:66|F2|F3)$/.test(comp)) { this.pp = comp; continue; } + if (/^(?:66|F2|F3|NP)$/.test(comp)) { this.opcode.pp = comp; continue; } - // Process `MM` field - 0F/0F3A/0F38/MAP5/MAP6/M8/M9. - if (/^(?:0F|0F3A|0F38|MAP5|MAP6|M08|M09|M0A)$/.test(comp)) { this.mm = comp; continue; } + // Process `MM` field - 0F/0F3A/0F38/MAP4/MAP5/MAP6/M8/M9. + if (/^(?:0F|0F3A|0F38|MAP[4-9A])$/.test(comp)) { this.opcode.mm = comp; continue; } // Process `W` field. - if (/^WIG|W0|W1$/.test(comp)) { this.w = comp; continue; } + if (/^(WIG|W0|W1|)$/.test(comp)) { this.opcode.w = comp; continue; } + + // TODO: Some new APX instructions don't have W specified (ENQCMD/ENQCMDS). + if (comp === "W?") { this.opcode.w = "W0"; continue; } // ERROR. this.report(`'${this.opcodeString}' Unhandled component: ${comp}`); } - for (i = 1; i < parts.length; i++) { - comp = parts[i]; + for (let i = 1; i < parts.length; i++) { + let comp = parts[i]; // Parse opcode. if (/^[0-9A-Fa-f]{2}$/.test(comp)) { - this.opcodeHex = comp.toUpperCase(); + this.opcode.byte = comp.toUpperCase(); continue; } - // Parse "/r" or "/0-7". + // Parse ModR/M field using "/r" or "/0-7" notation. if (/^\/[r0-7]$/.test(comp)) { - this.modR = comp.charAt(1); + this.opcode.mod = "xx"; + this.opcode.modr = comp.charAt(1); + this.opcode.modm = "b"; continue; } + // Parse ModR/M field using "11:xxx:xxx" and "!(11):xxx:xxx" notation. + const m = comp.match(/^(11|!\(11\)):(rrr|[01]{3}):(bbb|[01]{3})$/); + if (m) { + this.opcode.mod = m[1]; + this.opcode.modr = m[2] === "rrr" ? "r" : String(parseInt(m[2], 2)); + this.opcode.modrm = m[3] === "bbb" ? "b" : String(parseInt(m[3], 2)); + continue; + } + // Parse immediate byte, word, dword, or qword. + comp = this._substituteOpcodePart(comp, groupIndex); if (/^(?:ib|iw|id|iq|\/is4)$/.test(comp)) { this.imm += Utils.immSize(comp); continue; @@ -639,33 +804,73 @@ class Instruction extends base.Instruction { } else { // Parse X86/X64 instruction (including legacy MMX/SSE/3DNOW instructions). - for (i = 0; i < parts.length; i++) { - comp = parts[i]; + let rex_parsed = false; - // Parse REX.W prefix. - if (comp === "REX.W") { - this.w = "W1"; - // Instructions that force REX.W prefix are always 64-bit instructions. + for (let i = 0; i < parts.length; i++) { + let comp = parts[i]; + + if (comp === "NFx" || comp === "NOREP" || comp === "NO67") { + // Ignored for now. + continue; + } + + // Parse REX or REX2 prefix. + if (comp.startsWith("REX2.") || comp === "REX.W") { + if (rex_parsed) { + FAIL(`'${this.opcodeString}' Multiple REX prefixes are invalid`); + } + + rex_parsed = true; + + // Instructions that force REX.W prefix or use REX2 prefix are always 64-bit instructions. this.arch = "X64"; + + if (comp === "REX.W") { + this.opcode.w = "W1"; + } + else { + this.prefix = "REX2"; + + // REX2 has always 3 components - "REX2..". + const rex2 = comp.split("."); + if (rex2.length !== 3) { + FAIL(`'${this.opcodeString}' Invalid REX2 prefix - expected exactly 3 REX2 components`); + } + + if (rex2[1] === "MAP0") { + // nothing. + } + else if (rex2[1] === "MAP1") { + this.opcode.mm = "0F"; + } + else { + FAIL(`'${this.opcodeString}' Invalid REX2 prefix - REX2.MAP component could be either MAP0 or MAP1`); + } + + this.opcode.w = rex2[2]; + } + continue; } // Parse `PP` prefixes. - if ((this.mm === "" && ((this.pp === "" && /^(?:66|F2|F3)$/.test(comp)) || - (this.pp === "66" && /^(?:F2|F3)$/ .test(comp))))) { - this.pp += comp; - continue; + if (this.opcode.mm === "") { + if (this.opcode.pp === "" && /^(?:66|F2|F3|NP)$/.test(comp) || + this.opcode.pp === "66" && /^(?:F2|F3)$/.test(comp)) { + this.opcode.pp += comp; + continue; + } } // Parse `MM` prefixes. - if ((this.mm === "" && comp === "0F") || - (this.mm === "0F" && /^(?:01|3A|38)$/.test(comp))) { - this.mm += comp; + if ((this.opcode.mm === "" && comp === "0F") || + (this.opcode.mm === "0F" && /^(?:01|3A|38)$/.test(comp))) { + this.opcode.mm += comp; continue; } // Recognize "0F 0F /r XX" encoding. - if (this.mm === "0F" && comp === "0F") { + if (this.opcode.mm === "0F" && comp === "0F") { this.prefix = "3DNOW"; continue; } @@ -674,7 +879,7 @@ class Instruction extends base.Instruction { if (/^[0-9A-F]{2}(?:\+[ri])?$/.test(comp)) { // Parse "+r" or "+i" suffix. if (comp.length > 2) { - this.ri = true; + this.opcode.ri = true; comp = comp.substring(0, 2); } @@ -683,54 +888,69 @@ class Instruction extends base.Instruction { // instruction tables to allow storing this prefix together with other "MM" // prefixes, currently the unused indexes are used, but if X86 moves forward // and starts using these we can simply use more bits in the opcode DWORD. - if (!this.pp && this.opcodeHex === "9B") { - this.pp = this.opcodeHex; - this.opcodeHex = comp; + if (!this.opcode.pp && this.opcode.byte === "9B") { + this.opcode.pp = this.opcode.byte; + this.opcode.byte = comp; continue; } - if (!this.mm && (/^(?:D8|D9|DA|DB|DC|DD|DE|DF)$/.test(this.opcodeHex))) { - this.mm = this.opcodeHex; - this.opcodeHex = comp; + if (!this.opcode.mm && (/^(?:D8|D9|DA|DB|DC|DD|DE|DF)$/.test(this.opcode.byte))) { + this.opcode.mm = this.opcode.byte; + this.opcode.byte = comp; continue; } - if (this.opcodeHex) { - if (this.opcodeHex === "67") { - this._67h = true; + if (this.opcode.byte) { + if (this.opcode.byte === "67") { + this.opcode._67h = true; } else { - if (!this.modR && !this.modRM) { + if (!this.opcode.modr && !this.opcode.modrm) { const value = parseInt(comp, 16); if ((value & 0xC0) == 0xC0) { - this.modR = String((value >> 3) & 0x7); - this.modRM = String((value >> 0) & 0x7); + this.opcode.mod = "11"; + this.opcode.modr = String((value >> 3) & 0x7); + this.opcode.modrm = String((value >> 0) & 0x7); } else { this.report(`'${this.opcodeString}' Unsupported secondary opcode (MOD/RM) '${comp}' value`); } } else { - this.report(`'${this.opcodeString}' Multiple opcodes, have ${this.opcodeHex}, found ${comp}`); + this.report(`'${this.opcodeString}' Multiple opcodes, have ${this.opcode.byte}, found ${comp}`); } } } - this.opcodeHex = comp; + this.opcode.byte = comp; continue; } - // Parse "/r" or "/0-7". - if (/^\/[r0-7]$/.test(comp) && !this.modR) { - this.modR = comp.charAt(1); + // Parse ModR/M field using "/r" or "/0-7" notation. + if (/^\/[r0-7]$/.test(comp) && !this.opcode.modr) { + this.opcode.mod = "xx"; + this.opcode.modr = comp.charAt(1); + this.opcode.modm = "b"; + continue; + } + + // Parse ModR/M field using "11:xxx:xxx" and "!(11):xxx:xxx" notation. + const m = comp.match(/^(11|!\(11\)):(rrr|[01]{3}):(bbb|[01]{3})$/); + if (m) { + this.opcode.mod = m[1]; + this.opcode.modr = m[2] === "rrr" ? "r" : String(parseInt(m[2], 2)); + this.opcode.modrm = m[3] === "bbb" ? "b" : String(parseInt(m[3], 2)); continue; } // Parse immediate byte, word, dword, fword, or qword. - if (/^(?:ib|iw|id|iq|if)$/.test(comp)) { + if (/^(?:ib|iw|id|iq|iv|if)$/.test(comp)) { + if (comp === "iv") + comp = OpcodeGroupInfo[comp].subst[groupIndex]; this.imm += Utils.immSize(comp); continue; } + if (comp === "moff") { this.moff = true; continue; @@ -750,25 +970,25 @@ class Instruction extends base.Instruction { } // HACK: Fix instructions having opcode "01". - if (this.opcodeHex === "" && this.mm.indexOf("0F01") === this.mm.length - 4) { - this.opcodeHex = "01"; - this.mm = this.mm.substring(0, this.mm.length - 2); + if (this.opcode.byte === "" && this.opcode.mm.indexOf("0F01") === this.opcode.mm.length - 4) { + this.opcode.byte = "01"; + this.opcode.mm = this.opcode.mm.substring(0, this.opcode.mm.length - 2); } - if (this.opcodeHex) - this.opcodeValue = parseInt(this.opcodeHex, 16); + if (this.opcode.byte) + this.opcodeValue = parseInt(this.opcode.byte, 16); - if (!this.opcodeHex) + if (!this.opcode.byte) this.report(`Couldn't parse instruction's opcode '${this.opcodeString}'`); } _updateOperandsInfo() { super._updateOperandsInfo(); - var consecutiveLead = null; - var consecutiveLastIndex = 0; + let consecutiveLead = null; + let consecutiveLastIndex = 0; - for (var i = 0; i < this.operands.length; i++) { + for (let i = 0; i < this.operands.length; i++) { const op = this.operands[i]; // Instructions that use 64-bit GP registers are always 64-bit instructions. @@ -815,10 +1035,20 @@ class Instruction extends base.Instruction { // reported easily, however, if the mistake is just an invalid opcode or // something else it's impossible to detect. _postProcess() { + if (this.groupPattern) { + const archInfo = ArchGroupInfo[this.groupPattern]; + if (this.arch === "ANY" && archInfo && this.arch !== archInfo[this.groupIndex]) { + // TODO: Never triggered, which means it should be removed. + this.arch = archInfo[this.groupIndex]; + } + } + else { + this.groupIndex = -1; + } + if (this.privilege === "L0") this.category.SYSTEM = true; - let isValid = true; let immCount = this.immCount; // Verify that the immediate operand/operands are specified in instruction @@ -831,9 +1061,8 @@ class Instruction extends base.Instruction { } else { // Every immediate should have its imm byte ("ib", "iw", "id", or "iq") in the opcode data. - let m = this.opcodeString.match(/(?:^|\s+)(ib|iw|id|if|iq|\/is4)/g); + let m = this.opcodeString.match(/(?:^|\s+)(ib|iw|id|iq|iv|if|\/is4)/g); if (!m || m.length !== immCount) { - isValid = false; this.report(`Immediate(s) [${immCount}] not found in opcode: ${this.opcodeString}`); } } @@ -845,7 +1074,7 @@ class Instruction extends base.Instruction { isEVEX() { return this.prefix === "EVEX" } getWValue() { - switch (this.w) { + switch (this.opcode.w) { case "W0": return 0; case "W1": return 1; } @@ -854,33 +1083,33 @@ class Instruction extends base.Instruction { // Get signature of the instruction as "ARCH PREFIX ENCODING[:operands]" form. get signature() { - var operands = this.operands; - var sign = this.arch; + let operands = this.operands; + let sign = this.arch; if (this.prefix) { sign += " " + this.prefix; if (this.prefix !== "3DNOW") { - if (this.l === "L1") + if (this.opcode.l === "L1") sign += ".256"; - else if (this.l === "256" || this.l === "512") - sign += `.${this.l}`; + else if (this.opcode.l === "256" || this.opcode.l === "512") + sign += `.${this.opcode.l}`; else sign += ".128"; - if (this.w === "W1") + if (this.opcode.w === "W1") sign += ".W"; } } - else if (this.w === "W1") { + else if (this.opcode.w === "W1") { sign += " REX.W"; } sign += " " + this.encoding; - for (var i = 0; i < operands.length; i++) { + for (let i = 0; i < operands.length; i++) { sign += (i === 0) ? ":" : ","; - var operand = operands[i]; + let operand = operands[i]; if (operand.implicit) sign += `[${operand.reg}]`; else @@ -891,24 +1120,24 @@ class Instruction extends base.Instruction { } get immCount() { - var ops = this.operands; - var n = 0; - for (var i = 0; i < ops.length; i++) + let ops = this.operands; + let n = 0; + for (let i = 0; i < ops.length; i++) if (ops[i].isImm()) n++; return n; } get modRValue() { - if (/^[0-7]$/.test(this.modR)) - return parseInt(this.modR, 10); + if (/^[0-7]$/.test(this.opcode.modr)) + return parseInt(this.opcode.modr, 10); else return 0; } get modRMValue() { - if (/^[0-7]$/.test(this.modRM)) - return parseInt(this.modRM, 10); + if (/^[0-7]$/.test(this.opcode.modrm)) + return parseInt(this.opcode.modrm, 10); else return 0; } @@ -918,11 +1147,23 @@ x86.Instruction = Instruction; // asmdb.x86.ISA // ============= +const ArchKeys = MapUtils.mapFromArray(["any", "x86", "x64", "apx", "___"]); + +function findArch(inst) { + for (let a in ArchKeys) { + if (typeof inst[a] === "string") { + return a; + } + } + + FAIL(`Instruction signature not found in record: ${JSON.stringify(inst)}`); +} + function mergeGroupData(data, group) { for (let k in group) { switch (k) { case "group": - case "data": + case "instructions": break; case "ext": @@ -947,19 +1188,34 @@ class ISA extends base.ISA { _addInstructions(groups) { for (let group of groups) { - for (let inst of group.data) { - const sgn = Utils.splitInstructionSignature(inst.inst); - const data = MapUtils.cloneExcept(inst, { "inst": true }); + for (let record of group.instructions) { + const arch = findArch(record); + + // TODO: Ignore records having this (only used for testing purposes). + if (arch === "___") + continue; + + const sgn = Utils.splitInstructionSignature(record[arch]); + const data = MapUtils.cloneExcept(record, arch); mergeGroupData(data, group) - for (var j = 0; j < sgn.names.length; j++) { + for (let j = 0; j < sgn.names.length; j++) { data.name = sgn.names[j]; data.prefixes = sgn.prefixes; data.operands = sgn.operands; if (j > 0) data.aliasOf = sgn.names[0]; - this._addInstruction(new Instruction(this, data)); + + let groupIndex = 0; + let instruction = null; + do { + instruction = new Instruction(this); + instruction.arch = arch.toUpperCase(); + instruction.assignData(data, groupIndex); + + this._addInstruction(instruction); + } while (instruction.groupPattern && ++groupIndex < OperandGroupInfo[instruction.groupPattern].subst.length); } } } @@ -975,19 +1231,19 @@ x86.ISA = ISA; class X86DataCheck { static checkVexEvex(db) { const map = db.instructionMap; - for (var name in map) { - const insts = map[name]; - for (var i = 0; i < insts.length; i++) { - const instA = insts[i]; - for (var j = i + 1; j < insts.length; j++) { - const instB = insts[j]; + for (let name in map) { + const instructions = map[name]; + for (let i = 0; i < instructions.length; i++) { + const instA = instructions[i]; + for (let j = i + 1; j < instructions.length; j++) { + const instB = instructions[j]; if (instA.operands.join("_") === instB.operands.join("_")) { const vex = instA.prefix === "VEX" ? instA : instB.prefix === "VEX" ? instB : null; const evex = instA.prefix === "EVEX" ? instA : instB.prefix === "EVEX" ? instB : null; - if (vex && evex && vex.opcodeHex === evex.opcodeHex) { + if (vex && evex && vex.opcode.byte === evex.opcode.byte) { // NOTE: There are some false positives, they will be printed as well. - var ok = vex.w === evex.w && vex.l === evex.l; + let ok = vex.opcode.w === evex.opcode.w && vex.opcode.l === evex.opcode.l; if (!ok) { console.log(`Instruction ${name} differs:`); diff --git a/src/asmjit/arm/a64formatter.cpp b/src/asmjit/arm/a64formatter.cpp index 94ef3ee..b687e92 100644 --- a/src/asmjit/arm/a64formatter.cpp +++ b/src/asmjit/arm/a64formatter.cpp @@ -24,17 +24,23 @@ ASMJIT_BEGIN_SUB_NAMESPACE(a64) ASMJIT_FAVOR_SIZE Error FormatterInternal::formatInstruction( String& sb, - FormatFlags flags, + FormatFlags formatFlags, const BaseEmitter* emitter, Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount) noexcept { // Format instruction options and instruction mnemonic. InstId instId = inst.realId(); - if (instId != Inst::kIdNone && instId < Inst::_kIdCount) - ASMJIT_PROPAGATE(InstInternal::instIdToString(instId, sb)); - else + if (instId != Inst::kIdNone && instId < Inst::_kIdCount) { + InstStringifyOptions stringifyOptions = + Support::test(formatFlags, FormatFlags::kShowAliases) + ? InstStringifyOptions::kAliases + : InstStringifyOptions::kNone; + ASMJIT_PROPAGATE(InstInternal::instIdToString(instId, stringifyOptions, sb)); + } + else { ASMJIT_PROPAGATE(sb.appendFormat("[InstId=#%u]", unsigned(instId))); + } CondCode cc = inst.armCondCode(); if (cc != CondCode::kAL) { @@ -44,11 +50,12 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatInstruction( for (uint32_t i = 0; i < opCount; i++) { const Operand_& op = operands[i]; - if (op.isNone()) + if (op.isNone()) { break; + } ASMJIT_PROPAGATE(sb.append(i == 0 ? " " : ", ")); - ASMJIT_PROPAGATE(formatOperand(sb, flags, emitter, arch, op)); + ASMJIT_PROPAGATE(formatOperand(sb, formatFlags, emitter, arch, op)); } return kErrorOk; diff --git a/src/asmjit/arm/a64instapi.cpp b/src/asmjit/arm/a64instapi.cpp index 023be05..2d95993 100644 --- a/src/asmjit/arm/a64instapi.cpp +++ b/src/asmjit/arm/a64instapi.cpp @@ -21,16 +21,28 @@ namespace InstInternal { // ======================== #ifndef ASMJIT_NO_TEXT -Error instIdToString(InstId instId, String& output) noexcept { +Error instIdToString(InstId instId, InstStringifyOptions options, String& output) noexcept { uint32_t realId = instId & uint32_t(InstIdParts::kRealId); if (ASMJIT_UNLIKELY(!Inst::isDefinedId(realId))) return DebugUtils::errored(kErrorInvalidInstruction); - return InstNameUtils::decode(output, InstDB::_instNameIndexTable[realId], InstDB::_instNameStringTable); + return InstNameUtils::decode(InstDB::_instNameIndexTable[realId], options, InstDB::_instNameStringTable, output); } InstId stringToInstId(const char* s, size_t len) noexcept { - return InstNameUtils::find(s, len, InstDB::instNameIndex, InstDB::_instNameIndexTable, InstDB::_instNameStringTable); + if (ASMJIT_UNLIKELY(!s)) { + return BaseInst::kIdNone; + } + + if (len == SIZE_MAX) { + len = strlen(s); + } + + if (len == 0u || len > InstDB::instNameIndex.maxNameLength) { + return BaseInst::kIdNone; + } + + return InstNameUtils::findInstruction(s, len, InstDB::_instNameIndexTable, InstDB::_instNameStringTable, InstDB::instNameIndex); } #endif // !ASMJIT_NO_TEXT diff --git a/src/asmjit/arm/a64instapi_p.h b/src/asmjit/arm/a64instapi_p.h index 535e4bd..f294db6 100644 --- a/src/asmjit/arm/a64instapi_p.h +++ b/src/asmjit/arm/a64instapi_p.h @@ -18,7 +18,7 @@ ASMJIT_BEGIN_SUB_NAMESPACE(a64) namespace InstInternal { #ifndef ASMJIT_NO_TEXT -Error ASMJIT_CDECL instIdToString(InstId instId, String& output) noexcept; +Error ASMJIT_CDECL instIdToString(InstId instId, InstStringifyOptions options, String& output) noexcept; InstId ASMJIT_CDECL stringToInstId(const char* s, size_t len) noexcept; #endif // !ASMJIT_NO_TEXT diff --git a/src/asmjit/core.h b/src/asmjit/core.h index 8d28815..758f26f 100644 --- a/src/asmjit/core.h +++ b/src/asmjit/core.h @@ -275,6 +275,19 @@ namespace asmjit { //! //! \section api_changes API Changes //! +//! ### Changes committed at XXXX-XX-XX +//! +//! Core changes: +//! +//! - Removed AVX512 functionality that was never used on x86 hardware as Xeon Phi was never supported by AsmJit: +//! +//! - AVX512_ER +//! - AVX512_PF +//! - AVX512_4FMAPS +//! - AVX512_4VNNIW +//! +//! - Instruction 'vcvtneps2bf16' no longer accepts memory operand without explicit size (to minimize ambiguity) +//! //! ### Changes committed at 2024-01-01 //! //! Core changes: diff --git a/src/asmjit/core/api-config.h b/src/asmjit/core/api-config.h index 232d5f8..0b603fd 100644 --- a/src/asmjit/core/api-config.h +++ b/src/asmjit/core/api-config.h @@ -16,7 +16,7 @@ #define ASMJIT_LIBRARY_MAKE_VERSION(major, minor, patch) ((major << 16) | (minor << 8) | (patch)) //! AsmJit library version, see \ref ASMJIT_LIBRARY_MAKE_VERSION for a version format reference. -#define ASMJIT_LIBRARY_VERSION ASMJIT_LIBRARY_MAKE_VERSION(1, 14, 0) +#define ASMJIT_LIBRARY_VERSION ASMJIT_LIBRARY_MAKE_VERSION(1, 15, 0) //! \def ASMJIT_ABI_NAMESPACE //! @@ -27,7 +27,7 @@ //! AsmJit default, which makes it possible to use multiple AsmJit libraries within a single project, totally //! controlled by users. This is useful especially in cases in which some of such library comes from third party. #if !defined(ASMJIT_ABI_NAMESPACE) - #define ASMJIT_ABI_NAMESPACE v1_14 + #define ASMJIT_ABI_NAMESPACE v1_15 #endif // !ASMJIT_ABI_NAMESPACE //! \} diff --git a/src/asmjit/core/compiler.h b/src/asmjit/core/compiler.h index 7d4b47c..2414815 100644 --- a/src/asmjit/core/compiler.h +++ b/src/asmjit/core/compiler.h @@ -118,18 +118,6 @@ public: //! Emits a sentinel that marks the end of the current function. ASMJIT_API Error endFunc(); -#if !defined(ASMJIT_NO_DEPRECATED) - inline Error _setArg(size_t argIndex, size_t valueIndex, const BaseReg& reg); - - //! Sets a function argument at `argIndex` to `reg`. - ASMJIT_DEPRECATED("Setting arguments through Compiler is deprecated, use FuncNode->setArg() instead") - inline Error setArg(size_t argIndex, const BaseReg& reg) { return _setArg(argIndex, 0, reg); } - - //! Sets a function argument at `argIndex` at `valueIndex` to `reg`. - ASMJIT_DEPRECATED("Setting arguments through Compiler is deprecated, use FuncNode->setArg() instead") - inline Error setArg(size_t argIndex, size_t valueIndex, const BaseReg& reg) { return _setArg(argIndex, valueIndex, reg); } -#endif - inline Error addRet(const Operand_& o0, const Operand_& o1) { FuncRetNode* node; return addFuncRetNode(&node, o0, o1); @@ -721,18 +709,6 @@ public: //! \} }; -#if !defined(ASMJIT_NO_DEPRECATED) -inline Error BaseCompiler::_setArg(size_t argIndex, size_t valueIndex, const BaseReg& reg) { - FuncNode* func = _func; - - if (ASMJIT_UNLIKELY(!func)) - return reportError(DebugUtils::errored(kErrorInvalidState)); - - func->setArg(argIndex, valueIndex, reg); - return kErrorOk; -} -#endif - //! \} ASMJIT_END_NAMESPACE diff --git a/src/asmjit/core/cpuinfo.cpp b/src/asmjit/core/cpuinfo.cpp index 8ada345..2450543 100644 --- a/src/asmjit/core/cpuinfo.cpp +++ b/src/asmjit/core/cpuinfo.cpp @@ -235,8 +235,8 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept { // We are gonna execute CPUID, which was introduced by I486, so it's the requirement. features.add(Ext::kI486); - // CPUID EAX=0 - // ----------- + // CPUID EAX=0x00 (Basic CPUID Information) + // ---------------------------------------- // Get vendor string/id. cpuidQuery(®s, 0x0); @@ -246,10 +246,10 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept { simplifyCpuVendor(cpu, regs.ebx, regs.edx, regs.ecx); - // CPUID EAX=1 - // ----------- + // CPUID EAX=0x01 (Basic CPUID Information) + // ---------------------------------------- - if (maxId >= 0x1) { + if (maxId >= 0x01u) { // Get feature flags in ECX/EDX and family/model in EAX. cpuidQuery(®s, 0x1); @@ -317,39 +317,35 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept { } constexpr uint32_t kXCR0_AMX_Bits = 0x3u << 17; - bool amxEnabledByOS = (xcr0.eax & kXCR0_AMX_Bits) == kXCR0_AMX_Bits; + bool amxEnabled = (xcr0.eax & kXCR0_AMX_Bits) == kXCR0_AMX_Bits; #if defined(__APPLE__) // Apple platform provides on-demand AVX512 support. When an AVX512 instruction is used the first time it results // in #UD, which would cause the thread being promoted to use AVX512 support by the OS in addition to enabling the // necessary bits in XCR0 register. - bool avx512EnabledByOS = true; + bool avx512Enabled = true; #else // - XCR0[2:1] == 11b - XMM/YMM states need to be enabled by OS. // - XCR0[7:5] == 111b - Upper 256-bit of ZMM0-XMM15 and ZMM16-ZMM31 need to be enabled by OS. constexpr uint32_t kXCR0_AVX512_Bits = (0x3u << 1) | (0x7u << 5); - bool avx512EnabledByOS = (xcr0.eax & kXCR0_AVX512_Bits) == kXCR0_AVX512_Bits; + bool avx512Enabled = (xcr0.eax & kXCR0_AVX512_Bits) == kXCR0_AVX512_Bits; #endif - // CPUID EAX=7 ECX=0 - // ----------------- + bool avx10Enabled = false; - // Detect new features if the processor supports CPUID-07. - bool maybeMPX = false; + // CPUID EAX=0x07 ECX=0 (Structured Extended Feature Flags Enumeration Leaf) + // ------------------------------------------------------------------------- - if (maxId >= 0x7) { + if (maxId >= 0x07u) { cpuidQuery(®s, 0x7); - maybeMPX = bitTest(regs.ebx, 14); maxSubLeafId_0x7 = regs.eax; features.addIf(bitTest(regs.ebx, 0), Ext::kFSGSBASE); features.addIf(bitTest(regs.ebx, 3), Ext::kBMI); - features.addIf(bitTest(regs.ebx, 4), Ext::kHLE); features.addIf(bitTest(regs.ebx, 7), Ext::kSMEP); features.addIf(bitTest(regs.ebx, 8), Ext::kBMI2); features.addIf(bitTest(regs.ebx, 9), Ext::kERMS); - features.addIf(bitTest(regs.ebx, 11), Ext::kRTM); features.addIf(bitTest(regs.ebx, 18), Ext::kRDSEED); features.addIf(bitTest(regs.ebx, 19), Ext::kADX); features.addIf(bitTest(regs.ebx, 20), Ext::kSMAP); @@ -364,6 +360,7 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept { features.addIf(bitTest(regs.ecx, 9), Ext::kVAES); features.addIf(bitTest(regs.ecx, 10), Ext::kVPCLMULQDQ); features.addIf(bitTest(regs.ecx, 22), Ext::kRDPID); + features.addIf(bitTest(regs.ecx, 23), Ext::kKL); features.addIf(bitTest(regs.ecx, 25), Ext::kCLDEMOTE); features.addIf(bitTest(regs.ecx, 27), Ext::kMOVDIRI); features.addIf(bitTest(regs.ecx, 28), Ext::kMOVDIR64B); @@ -375,22 +372,15 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept { features.addIf(bitTest(regs.edx, 18), Ext::kPCONFIG); features.addIf(bitTest(regs.edx, 20), Ext::kCET_IBT); - // Detect 'TSX' - Requires at least one of `HLE` and `RTM` features. - if (features.hasHLE() || features.hasRTM()) { - features.add(Ext::kTSX); - } - if (bitTest(regs.ebx, 5) && features.hasAVX()) { features.add(Ext::kAVX2); } - if (avx512EnabledByOS && bitTest(regs.ebx, 16)) { + if (avx512Enabled && bitTest(regs.ebx, 16)) { features.add(Ext::kAVX512_F); features.addIf(bitTest(regs.ebx, 17), Ext::kAVX512_DQ); features.addIf(bitTest(regs.ebx, 21), Ext::kAVX512_IFMA); - features.addIf(bitTest(regs.ebx, 26), Ext::kAVX512_PF); - features.addIf(bitTest(regs.ebx, 27), Ext::kAVX512_ER); features.addIf(bitTest(regs.ebx, 28), Ext::kAVX512_CD); features.addIf(bitTest(regs.ebx, 30), Ext::kAVX512_BW); features.addIf(bitTest(regs.ebx, 31), Ext::kAVX512_VL); @@ -399,21 +389,19 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept { features.addIf(bitTest(regs.ecx, 11), Ext::kAVX512_VNNI); features.addIf(bitTest(regs.ecx, 12), Ext::kAVX512_BITALG); features.addIf(bitTest(regs.ecx, 14), Ext::kAVX512_VPOPCNTDQ); - features.addIf(bitTest(regs.edx, 2), Ext::kAVX512_4VNNIW); - features.addIf(bitTest(regs.edx, 3), Ext::kAVX512_4FMAPS); features.addIf(bitTest(regs.edx, 8), Ext::kAVX512_VP2INTERSECT); features.addIf(bitTest(regs.edx, 23), Ext::kAVX512_FP16); } - if (amxEnabledByOS) { + if (amxEnabled) { features.addIf(bitTest(regs.edx, 22), Ext::kAMX_BF16); features.addIf(bitTest(regs.edx, 24), Ext::kAMX_TILE); features.addIf(bitTest(regs.edx, 25), Ext::kAMX_INT8); } } - // CPUID EAX=7 ECX=1 - // ----------------- + // CPUID EAX=0x07 ECX=1 (Structured Extended Feature Enumeration Sub-leaf) + // ----------------------------------------------------------------------- if (maxSubLeafId_0x7 >= 1) { cpuidQuery(®s, 0x7, 1); @@ -430,6 +418,8 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept { features.addIf(bitTest(regs.eax, 22), Ext::kHRESET); features.addIf(bitTest(regs.eax, 26), Ext::kLAM); features.addIf(bitTest(regs.eax, 27), Ext::kMSRLIST); + features.addIf(bitTest(regs.eax, 31), Ext::kMOVRS); + features.addIf(bitTest(regs.ecx, 5), Ext::kMSR_IMM); features.addIf(bitTest(regs.ebx, 1), Ext::kTSE); features.addIf(bitTest(regs.edx, 14), Ext::kPREFETCHI); features.addIf(bitTest(regs.edx, 18), Ext::kCET_SSS); @@ -447,22 +437,20 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept { features.addIf(bitTest(regs.eax, 5), Ext::kAVX512_BF16); } - if (amxEnabledByOS) { + if (features.hasAVX512_F()) { + avx10Enabled = Support::bitTest(regs.edx, 19); + } + + if (amxEnabled) { features.addIf(bitTest(regs.eax, 21), Ext::kAMX_FP16); features.addIf(bitTest(regs.edx, 8), Ext::kAMX_COMPLEX); } } - // CPUID EAX=13 ECX=0 - // ------------------ - - if (maxId >= 0xD) { - cpuidQuery(®s, 0xD, 0); - - // Both CPUID result and XCR0 has to be enabled to have support for MPX. - if (((regs.eax & xcr0.eax) & 0x00000018u) == 0x00000018u && maybeMPX) - features.add(Ext::kMPX); + // CPUID EAX=0x0D ECX=1 (Processor Extended State Enumeration Sub-leaf) + // -------------------------------------------------------------------- + if (maxId >= 0x0Du) { cpuidQuery(®s, 0xD, 1); features.addIf(bitTest(regs.eax, 0), Ext::kXSAVEOPT); @@ -470,15 +458,57 @@ static ASMJIT_FAVOR_SIZE void detectX86Cpu(CpuInfo& cpu) noexcept { features.addIf(bitTest(regs.eax, 3), Ext::kXSAVES); } - // CPUID EAX=14 ECX=0 - // ------------------ + // CPUID EAX=0x0E ECX=0 (Processor Trace Enumeration Main Leaf) + // ------------------------------------------------------------ - if (maxId >= 0xE) { - cpuidQuery(®s, 0xE, 0); + if (maxId >= 0x0Eu) { + cpuidQuery(®s, 0x0E, 0); features.addIf(bitTest(regs.ebx, 4), Ext::kPTWRITE); } + // CPUID EAX=0x19 ECX=0 (Key Locker Leaf) + // -------------------------------------- + + if (maxId >= 0x19u && features.hasKL()) { + cpuidQuery(®s, 0x19, 0); + + features.addIf(bitTest(regs.ebx, 0), Ext::kAESKLE); + features.addIf(bitTest(regs.ebx, 0) && bitTest(regs.ebx, 2), Ext::kAESKLEWIDE_KL); + } + + // CPUID EAX=0x1E ECX=1 (TMUL Information Sub-leaf) + // ------------------------------------------------ + + if (maxId >= 0x1Eu && features.hasAMX_TILE()) { + cpuidQuery(®s, 0x1E, 1); + + // NOTE: Some AMX flags are mirrored here from CPUID[0x07, 0x00]. + features.addIf(bitTest(regs.eax, 0), Ext::kAMX_INT8); + features.addIf(bitTest(regs.eax, 1), Ext::kAMX_BF16); + features.addIf(bitTest(regs.eax, 2), Ext::kAMX_COMPLEX); + features.addIf(bitTest(regs.eax, 3), Ext::kAMX_FP16); + features.addIf(bitTest(regs.eax, 4), Ext::kAMX_FP8); + features.addIf(bitTest(regs.eax, 5), Ext::kAMX_TRANSPOSE); + features.addIf(bitTest(regs.eax, 6), Ext::kAMX_TF32); + features.addIf(bitTest(regs.eax, 7), Ext::kAMX_AVX512); + features.addIf(bitTest(regs.eax, 8), Ext::kAMX_MOVRS); + } + + // CPUID EAX=0x24 ECX=0 (AVX10 Information) + // ---------------------------------------- + + if (maxId >= 0x24u && avx10Enabled) { + // EAX output is the maximum supported sub-leaf. + cpuidQuery(®s, 0x24, 0); + + // AVX10 Converged Vector ISA version. + uint32_t ver = regs.ebx & 0xFFu; + + features.addIf(ver >= 1u, Ext::kAVX10_1); + features.addIf(ver >= 2u, Ext::kAVX10_2); + } + // CPUID EAX=0x80000000...maxId // ---------------------------- diff --git a/src/asmjit/core/cpuinfo.h b/src/asmjit/core/cpuinfo.h index fbb91e9..d365618 100644 --- a/src/asmjit/core/cpuinfo.h +++ b/src/asmjit/core/cpuinfo.h @@ -174,11 +174,6 @@ public: //! Tests whether this CPU features data matches `other`. ASMJIT_INLINE_NODEBUG bool equals(const Data& other) const noexcept { return _bits == other._bits; } -#if !defined(ASMJIT_NO_DEPRECATED) - ASMJIT_DEPRECATED("Use CpuFeatures::Data::equals() instead") - ASMJIT_INLINE_NODEBUG bool eq(const Data& other) const noexcept { return equals(other); } -#endif // !ASMJIT_NO_DEPRECATED - //! \} }; @@ -191,42 +186,9 @@ public: kMT, //!< CPU has multi-threading capabilities. kNX, //!< CPU has Not-Execute-Bit aka DEP (data-execution prevention). - k3DNOW, //!< CPU has 3DNOW (3DNOW base instructions) {AMD} (deprecated). - k3DNOW2, //!< CPU has 3DNOW2 (enhanced 3DNOW) {AMD} (deprecated). kADX, //!< CPU has ADX (multi-precision add-carry instruction extensions). - kAESNI, //!< CPU has AESNI (AES encode/decode instructions). kALTMOVCR8, //!< CPU has LOCK MOV R<->CR0 (supports `MOV R<->CR8` via `LOCK MOV R<->CR0` in 32-bit mode) {AMD}. - kAMX_BF16, //!< CPU has AMX_BF16 (AMX-BF16 instructions). - kAMX_COMPLEX, //!< CPU has AMX_COMPLEX (AMX-COMPLEX instructions). - kAMX_FP16, //!< CPU has AMX_FP16 (AMX-FP16 instructions). - kAMX_INT8, //!< CPU has AMX_INT8 (AMX-INT8 instructions). - kAMX_TILE, //!< CPU has AMX_TILE (advanced matrix extensions). kAPX_F, //!< CPU has APX_F (advanced performance extensions - 32 GP registers, REX2 prefix, ...) {X86_64}. - kAVX, //!< CPU has AVX (advanced vector extensions). - kAVX2, //!< CPU has AVX2 (advanced vector extensions 2). - kAVX512_4FMAPS, //!< CPU has AVX512_FMAPS (FMA packed single). - kAVX512_4VNNIW, //!< CPU has AVX512_VNNIW (vector NN instructions word variable precision). - kAVX512_BF16, //!< CPU has AVX512_BF16 (AVX512 BFLOAT16 support instructions). - kAVX512_BITALG, //!< CPU has AVX512_BITALG (AVX512 VPOPCNT[B|W] and VPSHUFBITQMB instructions). - kAVX512_BW, //!< CPU has AVX512_BW (AVX512 integer BYTE|WORD instructions). - kAVX512_CD, //!< CPU has AVX512_CD (AVX512 conflict detection DWORD|QWORD instructions). - kAVX512_DQ, //!< CPU has AVX512_DQ (AVX512 integer DWORD|QWORD instructions). - kAVX512_ER, //!< CPU has AVX512_ER (AVX512 exponential and reciprocal instructions). - kAVX512_F, //!< CPU has AVX512_F (AVX512 foundation). - kAVX512_FP16, //!< CPU has AVX512_FP16 (AVX512 FP16 instructions). - kAVX512_IFMA, //!< CPU has AVX512_IFMA (AVX512 integer fused-multiply-add using 52-bit precision). - kAVX512_PF, //!< CPU has AVX512_PF (AVX512 prefetch instructions). - kAVX512_VBMI, //!< CPU has AVX512_VBMI (AVX152 vector byte manipulation instructions). - kAVX512_VBMI2, //!< CPU has AVX512_VBMI2 (AVX512 vector byte manipulation instructions v2). - kAVX512_VL, //!< CPU has AVX512_VL (AVX512 vector length extensions). - kAVX512_VNNI, //!< CPU has AVX512_VNNI (AVX512 vector neural network instructions). - kAVX512_VP2INTERSECT, //!< CPU has AVX512_VP2INTERSECT - kAVX512_VPOPCNTDQ, //!< CPU has AVX512_VPOPCNTDQ (AVX512 VPOPCNT[D|Q] instructions). - kAVX_IFMA, //!< CPU has AVX_IFMA (AVX/VEX encoding of vpmadd52huq/vpmadd52luq). - kAVX_NE_CONVERT, //!< CPU has AVX_NE_CONVERT. - kAVX_VNNI, //!< CPU has AVX_VNNI (AVX/VEX encoding of vpdpbusd/vpdpbusds/vpdpwssd/vpdpwssds). - kAVX_VNNI_INT16, //!< CPU has AVX_VNNI_INT16. - kAVX_VNNI_INT8, //!< CPU has AVX_VNNI_INT8. kBMI, //!< CPU has BMI (bit manipulation instructions #1). kBMI2, //!< CPU has BMI2 (bit manipulation instructions #2). kCET_IBT, //!< CPU has CET-IBT (indirect branch tracking). @@ -244,10 +206,6 @@ public: kENCLV, //!< CPU has ENCLV. kENQCMD, //!< CPU has ENQCMD (enqueue stores). kERMS, //!< CPU has ERMS (enhanced REP MOVSB/STOSB). - kF16C, //!< CPU has F16C (AVX FP16 conversion instructions). - kFMA, //!< CPU has FMA (AVX fused-multiply-add - 3 operand form). - kFMA4, //!< CPU has FMA4 (AVX fused-multiply-add - 4 operand form) (deprecated). - kFPU, //!< CPU has FPU (FPU support). kFSGSBASE, //!< CPU has FSGSBASE. kFSRM, //!< CPU has FSRM (fast short REP MOVSB). kFSRC, //!< CPU has FSRC (fast short REP CMPSB|SCASB). @@ -255,9 +213,6 @@ public: kFXSR, //!< CPU has FXSR (FXSAVE/FXRSTOR instructions). kFXSROPT, //!< CPU has FXSROTP (FXSAVE/FXRSTOR is optimized). kFZRM, //!< CPU has FZRM (fast zero-length REP MOVSB). - kGEODE, //!< CPU has GEODE extensions (GEODE 3DNOW additions) (deprecated). - kGFNI, //!< CPU has GFNI (galois field instructions). - kHLE, //!< CPU has HLE. kHRESET, //!< CPU has HRESET. kI486, //!< CPU has I486 features (I486+ support). kINVLPGB, //!< CPU has INVLPGB. @@ -266,20 +221,19 @@ public: kLWP, //!< CPU has LWP (lightweight profiling) {AMD}. kLZCNT, //!< CPU has LZCNT (LZCNT instruction). kMCOMMIT, //!< CPU has MCOMMIT (MCOMMIT instruction). - kMMX, //!< CPU has MMX (MMX base instructions) (deprecated). - kMMX2, //!< CPU has MMX2 (MMX2 extensions or initial SSE extensions) (deprecated). kMONITOR, //!< CPU has MONITOR (MONITOR/MWAIT instructions). kMONITORX, //!< CPU has MONITORX (MONITORX/MWAITX instructions). kMOVBE, //!< CPU has MOVBE (move with byte-order swap). kMOVDIR64B, //!< CPU has MOVDIR64B (move 64 bytes as direct store). kMOVDIRI, //!< CPU has MOVDIRI (move dword/qword as direct store). + kMOVRS, //!< CPU has MOVRS (move from shared memory). kMPX, //!< CPU has MPX (memory protection extensions). kMSR, //!< CPU has MSR (RDMSR/WRMSR instructions). kMSRLIST, //!< CPU has MSRLIST. + kMSR_IMM, //!< CPU has MSR_IMM (RDMSR/WRMSR immediate encoding). kMSSE, //!< CPU has MSSE (misaligned SSE support). kOSXSAVE, //!< CPU has OSXSAVE (XSAVE enabled by OS). kOSPKE, //!< CPU has OSPKE (PKE enabled by OS). - kPCLMULQDQ, //!< CPU has PCLMULQDQ (packed carry-less multiplication). kPCONFIG, //!< CPU has PCONFIG (PCONFIG instruction). kPOPCNT, //!< CPU has POPCNT (POPCNT instruction). kPREFETCHI, //!< CPU has PREFETCHI. @@ -294,54 +248,103 @@ public: kRDSEED, //!< CPU has RDSEED (RDSEED instruction). kRDTSC, //!< CPU has RDTSC. kRDTSCP, //!< CPU has RDTSCP. - kRTM, //!< CPU has RTM. + kRTM, //!< CPU has RTM (RTM instructions - deprecated). kSEAM, //!< CPU has SEAM. kSERIALIZE, //!< CPU has SERIALIZE. kSEV, //!< CPU has SEV (secure encrypted virtualization). kSEV_ES, //!< CPU has SEV_ES (SEV encrypted state). kSEV_SNP, //!< CPU has SEV_SNP (SEV secure nested paging). - kSHA, //!< CPU has SHA (SHA-1 and SHA-256 instructions). - kSHA512, //!< CPU has SHA512 (SHA-512 instructions). kSKINIT, //!< CPU has SKINIT (SKINIT/STGI instructions) {AMD}. - kSM3, //!< CPU has SM3 (SM3 hash extensions). - kSM4, //!< CPU has SM4 (SM4 cipher extensions). kSMAP, //!< CPU has SMAP (supervisor-mode access prevention). - kSME , //!< CPU has SME (secure memory encryption). + kSME, //!< CPU has SME (secure memory encryption). kSMEP, //!< CPU has SMEP (supervisor-mode execution prevention). kSMX, //!< CPU has SMX (safer mode extensions). - kSSE, //!< CPU has SSE (SSE instructions). - kSSE2, //!< CPU has SSE2 (SSE2 instructions). - kSSE3, //!< CPU has SSE3 (SSE3 instructions). - kSSE4_1, //!< CPU has SSE4.1 (SSE4.1 instructions). - kSSE4_2, //!< CPU has SSE4.2 (SSE4.2 instructions). - kSSE4A, //!< CPU has SSE4A (SSE4.A instructions) {AMD} (deprecated). - kSSSE3, //!< CPU has SSSE3 (SSSE3 instructions). kSVM, //!< CPU has SVM (virtualization) {AMD}. kTBM, //!< CPU has TBM (trailing bit manipulation) {AMD}. kTSE, //!< CPU has TSE. - kTSX, //!< CPU has TSX. kTSXLDTRK, //!< CPU has TSXLDTRK. kUINTR, //!< CPU has UINTR (user interrupts). - kVAES, //!< CPU has VAES (vector AES 256|512 bit support). kVMX, //!< CPU has VMX (virtualization) {INTEL}. - kVPCLMULQDQ, //!< CPU has VPCLMULQDQ (vector PCLMULQDQ 256|512-bit support). kWAITPKG, //!< CPU has WAITPKG (UMONITOR, UMWAIT, TPAUSE). kWBNOINVD, //!< CPU has WBNOINVD. kWRMSRNS, //!< CPU has WRMSRNS. - kXOP, //!< CPU has XOP (XOP instructions) {AMD} (deprecated). kXSAVE, //!< CPU has XSAVE. kXSAVEC, //!< CPU has XSAVEC. kXSAVEOPT, //!< CPU has XSAVEOPT. kXSAVES, //!< CPU has XSAVES. + + kFPU, //!< CPU has FPU (FPU support). + kMMX, //!< CPU has MMX (MMX base instructions) (deprecated). + kMMX2, //!< CPU has MMX2 (MMX2 extensions or initial SSE extensions) (deprecated). + k3DNOW, //!< CPU has 3DNOW (3DNOW base instructions) {AMD} (deprecated). + k3DNOW2, //!< CPU has 3DNOW2 (enhanced 3DNOW) {AMD} (deprecated). + kGEODE, //!< CPU has GEODE extensions (GEODE 3DNOW additions) (deprecated). + + kSSE, //!< CPU has SSE (SSE instructions). + kSSE2, //!< CPU has SSE2 (SSE2 instructions). + kSSE3, //!< CPU has SSE3 (SSE3 instructions). + kSSSE3, //!< CPU has SSSE3 (SSSE3 instructions). + kSSE4_1, //!< CPU has SSE4.1 (SSE4.1 instructions). + kSSE4_2, //!< CPU has SSE4.2 (SSE4.2 instructions). + kSSE4A, //!< CPU has SSE4A (SSE4.A instructions) {AMD} (deprecated). + kPCLMULQDQ, //!< CPU has PCLMULQDQ (packed carry-less multiplication). + + kAVX, //!< CPU has AVX (advanced vector extensions). + kAVX2, //!< CPU has AVX2 (advanced vector extensions 2). + kAVX_IFMA, //!< CPU has AVX_IFMA (AVX/VEX encoding of vpmadd52huq/vpmadd52luq). + kAVX_NE_CONVERT, //!< CPU has AVX_NE_CONVERT. + kAVX_VNNI, //!< CPU has AVX_VNNI (AVX/VEX encoding of vpdpbusd/vpdpbusds/vpdpwssd/vpdpwssds). + kAVX_VNNI_INT16, //!< CPU has AVX_VNNI_INT16. + kAVX_VNNI_INT8, //!< CPU has AVX_VNNI_INT8. + kF16C, //!< CPU has F16C (AVX FP16 conversion instructions). + kFMA, //!< CPU has FMA (AVX fused-multiply-add - 3 operand form). + kFMA4, //!< CPU has FMA4 (AVX fused-multiply-add - 4 operand form) (deprecated). + kXOP, //!< CPU has XOP (XOP instructions) {AMD} (deprecated). + + kAVX512_BF16, //!< CPU has AVX512_BF16 (AVX512 BFLOAT16 support instructions). + kAVX512_BITALG, //!< CPU has AVX512_BITALG (AVX512 VPOPCNT[B|W] and VPSHUFBITQMB instructions). + kAVX512_BW, //!< CPU has AVX512_BW (AVX512 integer BYTE|WORD instructions). + kAVX512_CD, //!< CPU has AVX512_CD (AVX512 conflict detection DWORD|QWORD instructions). + kAVX512_DQ, //!< CPU has AVX512_DQ (AVX512 integer DWORD|QWORD instructions). + kAVX512_F, //!< CPU has AVX512_F (AVX512 foundation). + kAVX512_FP16, //!< CPU has AVX512_FP16 (AVX512 FP16 instructions). + kAVX512_IFMA, //!< CPU has AVX512_IFMA (AVX512 integer fused-multiply-add using 52-bit precision). + kAVX512_VBMI, //!< CPU has AVX512_VBMI (AVX512 vector byte manipulation instructions). + kAVX512_VBMI2, //!< CPU has AVX512_VBMI2 (AVX512 vector byte manipulation instructions v2). + kAVX512_VL, //!< CPU has AVX512_VL (AVX512 vector length extensions). + kAVX512_VNNI, //!< CPU has AVX512_VNNI (AVX512 vector neural network instructions). + kAVX512_VP2INTERSECT, //!< CPU has AVX512_VP2INTERSECT + kAVX512_VPOPCNTDQ, //!< CPU has AVX512_VPOPCNTDQ (AVX512 VPOPCNT[D|Q] instructions). + + kAESNI, //!< CPU has AESNI (AES encode/decode instructions). + kGFNI, //!< CPU has GFNI (galois field instructions). + kSHA, //!< CPU has SHA (SHA-1 and SHA-256 instructions). + kSHA512, //!< CPU has SHA512 (SHA-512 instructions). + kSM3, //!< CPU has SM3 (SM3 hash extensions). + kSM4, //!< CPU has SM4 (SM4 cipher extensions). + kVAES, //!< CPU has VAES (vector AES 256|512 bit support). + kVPCLMULQDQ, //!< CPU has VPCLMULQDQ (vector PCLMULQDQ 256|512-bit support). + + kKL, //!< CPU has KL (Key Locker). + kAESKLE, //!< CPU has AESKLE (AESKLE). + kAESKLEWIDE_KL, //!< CPU has AESKLE+WIDEKL+KL (AESKLE & WIDEKL instructions and KL enabled) + + kAVX10_1, //!< CPU has AVX10.1/512 (AVX10.1 with 512-bit vectors). + kAVX10_2, //!< CPU has AVX10.2/512 (AVX10.2 with 512-bit vectors). + + kAMX_AVX512, //!< CPU has AMX_AVX512 (AMX-AVX512 instructions). + kAMX_BF16, //!< CPU has AMX_BF16 (AMX-BF16 instructions). + kAMX_COMPLEX, //!< CPU has AMX_COMPLEX (AMX-COMPLEX instructions). + kAMX_FP16, //!< CPU has AMX_FP16 (AMX-FP16 instructions). + kAMX_FP8, //!< CPU has AMX_FP8 (AMX-FP8 instructions). + kAMX_INT8, //!< CPU has AMX_INT8 (AMX-INT8 instructions). + kAMX_MOVRS, //!< CPU has AMX_MOVRS (AMX-MOVRS instructions). + kAMX_TF32, //!< CPU has AMX_TF32 (AMX-TF32 instructions). + kAMX_TILE, //!< CPU has AMX_TILE (advanced matrix extensions). + kAMX_TRANSPOSE, //!< CPU has AMX_TRANSPOSE (AMX-TRANSPOSE instructions). // @EnumValuesEnd@ -#ifndef ASMJIT_NO_DEPRECATED - kAVX512_CDI = kAVX512_CD, - kAVX512_ERI = kAVX512_ER, - kAVX512_PFI = kAVX512_PF, -#endif - - kMaxValue = kXSAVES + kMaxValue = kAMX_TILE }; #define ASMJIT_X86_FEATURE(FEATURE) \ @@ -350,42 +353,9 @@ public: ASMJIT_X86_FEATURE(MT) ASMJIT_X86_FEATURE(NX) - ASMJIT_X86_FEATURE(3DNOW) - ASMJIT_X86_FEATURE(3DNOW2) ASMJIT_X86_FEATURE(ADX) - ASMJIT_X86_FEATURE(AESNI) ASMJIT_X86_FEATURE(ALTMOVCR8) - ASMJIT_X86_FEATURE(AMX_BF16) - ASMJIT_X86_FEATURE(AMX_COMPLEX) - ASMJIT_X86_FEATURE(AMX_FP16) - ASMJIT_X86_FEATURE(AMX_INT8) - ASMJIT_X86_FEATURE(AMX_TILE) ASMJIT_X86_FEATURE(APX_F) - ASMJIT_X86_FEATURE(AVX) - ASMJIT_X86_FEATURE(AVX2) - ASMJIT_X86_FEATURE(AVX512_4FMAPS) - ASMJIT_X86_FEATURE(AVX512_4VNNIW) - ASMJIT_X86_FEATURE(AVX512_BF16) - ASMJIT_X86_FEATURE(AVX512_BITALG) - ASMJIT_X86_FEATURE(AVX512_BW) - ASMJIT_X86_FEATURE(AVX512_CD) - ASMJIT_X86_FEATURE(AVX512_DQ) - ASMJIT_X86_FEATURE(AVX512_ER) - ASMJIT_X86_FEATURE(AVX512_F) - ASMJIT_X86_FEATURE(AVX512_FP16) - ASMJIT_X86_FEATURE(AVX512_IFMA) - ASMJIT_X86_FEATURE(AVX512_PF) - ASMJIT_X86_FEATURE(AVX512_VBMI) - ASMJIT_X86_FEATURE(AVX512_VBMI2) - ASMJIT_X86_FEATURE(AVX512_VL) - ASMJIT_X86_FEATURE(AVX512_VNNI) - ASMJIT_X86_FEATURE(AVX512_VP2INTERSECT) - ASMJIT_X86_FEATURE(AVX512_VPOPCNTDQ) - ASMJIT_X86_FEATURE(AVX_IFMA) - ASMJIT_X86_FEATURE(AVX_NE_CONVERT) - ASMJIT_X86_FEATURE(AVX_VNNI) - ASMJIT_X86_FEATURE(AVX_VNNI_INT16) - ASMJIT_X86_FEATURE(AVX_VNNI_INT8) ASMJIT_X86_FEATURE(BMI) ASMJIT_X86_FEATURE(BMI2) ASMJIT_X86_FEATURE(CET_IBT) @@ -402,10 +372,6 @@ public: ASMJIT_X86_FEATURE(ENCLV) ASMJIT_X86_FEATURE(ENQCMD) ASMJIT_X86_FEATURE(ERMS) - ASMJIT_X86_FEATURE(F16C) - ASMJIT_X86_FEATURE(FMA) - ASMJIT_X86_FEATURE(FMA4) - ASMJIT_X86_FEATURE(FPU) ASMJIT_X86_FEATURE(FSGSBASE) ASMJIT_X86_FEATURE(FSRM) ASMJIT_X86_FEATURE(FSRC) @@ -413,9 +379,6 @@ public: ASMJIT_X86_FEATURE(FXSR) ASMJIT_X86_FEATURE(FXSROPT) ASMJIT_X86_FEATURE(FZRM) - ASMJIT_X86_FEATURE(GEODE) - ASMJIT_X86_FEATURE(GFNI) - ASMJIT_X86_FEATURE(HLE) ASMJIT_X86_FEATURE(HRESET) ASMJIT_X86_FEATURE(I486) ASMJIT_X86_FEATURE(INVLPGB) @@ -424,20 +387,19 @@ public: ASMJIT_X86_FEATURE(LWP) ASMJIT_X86_FEATURE(LZCNT) ASMJIT_X86_FEATURE(MCOMMIT) - ASMJIT_X86_FEATURE(MMX) - ASMJIT_X86_FEATURE(MMX2) ASMJIT_X86_FEATURE(MONITOR) ASMJIT_X86_FEATURE(MONITORX) ASMJIT_X86_FEATURE(MOVBE) ASMJIT_X86_FEATURE(MOVDIR64B) ASMJIT_X86_FEATURE(MOVDIRI) + ASMJIT_X86_FEATURE(MOVRS) ASMJIT_X86_FEATURE(MPX) ASMJIT_X86_FEATURE(MSR) ASMJIT_X86_FEATURE(MSRLIST) + ASMJIT_X86_FEATURE(MSR_IMM) ASMJIT_X86_FEATURE(MSSE) ASMJIT_X86_FEATURE(OSXSAVE) ASMJIT_X86_FEATURE(OSPKE) - ASMJIT_X86_FEATURE(PCLMULQDQ) ASMJIT_X86_FEATURE(PCONFIG) ASMJIT_X86_FEATURE(POPCNT) ASMJIT_X86_FEATURE(PREFETCHI) @@ -458,46 +420,93 @@ public: ASMJIT_X86_FEATURE(SEV) ASMJIT_X86_FEATURE(SEV_ES) ASMJIT_X86_FEATURE(SEV_SNP) - ASMJIT_X86_FEATURE(SHA) ASMJIT_X86_FEATURE(SKINIT) ASMJIT_X86_FEATURE(SMAP) ASMJIT_X86_FEATURE(SMEP) ASMJIT_X86_FEATURE(SMX) - ASMJIT_X86_FEATURE(SSE) - ASMJIT_X86_FEATURE(SSE2) - ASMJIT_X86_FEATURE(SSE3) - ASMJIT_X86_FEATURE(SSE4_1) - ASMJIT_X86_FEATURE(SSE4_2) - ASMJIT_X86_FEATURE(SSE4A) - ASMJIT_X86_FEATURE(SSSE3) ASMJIT_X86_FEATURE(SVM) ASMJIT_X86_FEATURE(TBM) ASMJIT_X86_FEATURE(TSE) - ASMJIT_X86_FEATURE(TSX) ASMJIT_X86_FEATURE(TSXLDTRK) ASMJIT_X86_FEATURE(UINTR) - ASMJIT_X86_FEATURE(VAES) ASMJIT_X86_FEATURE(VMX) - ASMJIT_X86_FEATURE(VPCLMULQDQ) ASMJIT_X86_FEATURE(WAITPKG) ASMJIT_X86_FEATURE(WBNOINVD) ASMJIT_X86_FEATURE(WRMSRNS) - ASMJIT_X86_FEATURE(XOP) ASMJIT_X86_FEATURE(XSAVE) ASMJIT_X86_FEATURE(XSAVEC) ASMJIT_X86_FEATURE(XSAVEOPT) ASMJIT_X86_FEATURE(XSAVES) -#ifndef ASMJIT_NO_DEPRECATED - ASMJIT_DEPRECATED("Use hasAVX512_CD() instead") - ASMJIT_X86_FEATURE(AVX512_CDI) + ASMJIT_X86_FEATURE(FPU) + ASMJIT_X86_FEATURE(MMX) + ASMJIT_X86_FEATURE(MMX2) + ASMJIT_X86_FEATURE(3DNOW) + ASMJIT_X86_FEATURE(3DNOW2) + ASMJIT_X86_FEATURE(GEODE) - ASMJIT_DEPRECATED("Use hasAVX512_ER() instead") - ASMJIT_X86_FEATURE(AVX512_ERI) + ASMJIT_X86_FEATURE(SSE) + ASMJIT_X86_FEATURE(SSE2) + ASMJIT_X86_FEATURE(SSE3) + ASMJIT_X86_FEATURE(SSSE3) + ASMJIT_X86_FEATURE(SSE4_1) + ASMJIT_X86_FEATURE(SSE4_2) + ASMJIT_X86_FEATURE(SSE4A) + ASMJIT_X86_FEATURE(PCLMULQDQ) - ASMJIT_DEPRECATED("Use hasAVX512_PF() instead") - ASMJIT_X86_FEATURE(AVX512_PFI) -#endif + ASMJIT_X86_FEATURE(AVX) + ASMJIT_X86_FEATURE(AVX2) + ASMJIT_X86_FEATURE(AVX_IFMA) + ASMJIT_X86_FEATURE(AVX_NE_CONVERT) + ASMJIT_X86_FEATURE(AVX_VNNI) + ASMJIT_X86_FEATURE(AVX_VNNI_INT16) + ASMJIT_X86_FEATURE(AVX_VNNI_INT8) + ASMJIT_X86_FEATURE(F16C) + ASMJIT_X86_FEATURE(FMA) + ASMJIT_X86_FEATURE(FMA4) + ASMJIT_X86_FEATURE(XOP) + + ASMJIT_X86_FEATURE(AVX512_BF16) + ASMJIT_X86_FEATURE(AVX512_BITALG) + ASMJIT_X86_FEATURE(AVX512_BW) + ASMJIT_X86_FEATURE(AVX512_CD) + ASMJIT_X86_FEATURE(AVX512_DQ) + ASMJIT_X86_FEATURE(AVX512_F) + ASMJIT_X86_FEATURE(AVX512_FP16) + ASMJIT_X86_FEATURE(AVX512_IFMA) + ASMJIT_X86_FEATURE(AVX512_VBMI) + ASMJIT_X86_FEATURE(AVX512_VBMI2) + ASMJIT_X86_FEATURE(AVX512_VL) + ASMJIT_X86_FEATURE(AVX512_VNNI) + ASMJIT_X86_FEATURE(AVX512_VP2INTERSECT) + ASMJIT_X86_FEATURE(AVX512_VPOPCNTDQ) + + ASMJIT_X86_FEATURE(AESNI) + ASMJIT_X86_FEATURE(GFNI) + ASMJIT_X86_FEATURE(SHA) + ASMJIT_X86_FEATURE(SHA512) + ASMJIT_X86_FEATURE(SM3) + ASMJIT_X86_FEATURE(SM4) + ASMJIT_X86_FEATURE(VAES) + ASMJIT_X86_FEATURE(VPCLMULQDQ) + + ASMJIT_X86_FEATURE(KL) + ASMJIT_X86_FEATURE(AESKLE) + ASMJIT_X86_FEATURE(AESKLEWIDE_KL) + + ASMJIT_X86_FEATURE(AVX10_1) + ASMJIT_X86_FEATURE(AVX10_2) + + ASMJIT_X86_FEATURE(AMX_AVX512) + ASMJIT_X86_FEATURE(AMX_BF16) + ASMJIT_X86_FEATURE(AMX_COMPLEX) + ASMJIT_X86_FEATURE(AMX_FP16) + ASMJIT_X86_FEATURE(AMX_FP8) + ASMJIT_X86_FEATURE(AMX_INT8) + ASMJIT_X86_FEATURE(AMX_MOVRS) + ASMJIT_X86_FEATURE(AMX_TF32) + ASMJIT_X86_FEATURE(AMX_TILE) + ASMJIT_X86_FEATURE(AMX_TRANSPOSE) #undef ASMJIT_X86_FEATURE }; @@ -1032,11 +1041,6 @@ public: //! Tests whether this CPU features matches `other`. ASMJIT_INLINE_NODEBUG bool equals(const CpuFeatures& other) const noexcept { return _data.equals(other._data); } -#if !defined(ASMJIT_NO_DEPRECATED) - ASMJIT_DEPRECATED("Use CpuFeatures::equals() instead") - ASMJIT_INLINE_NODEBUG bool eq(const CpuFeatures& other) const noexcept { return equals(other); } -#endif // !ASMJIT_NO_DEPRECATED - //! \} }; diff --git a/src/asmjit/core/formatter.h b/src/asmjit/core/formatter.h index 392e478..d2c7655 100644 --- a/src/asmjit/core/formatter.h +++ b/src/asmjit/core/formatter.h @@ -26,20 +26,25 @@ enum class FormatFlags : uint32_t { //! No formatting flags. kNone = 0u, - //! Show also binary form of each logged instruction (Assembler). + //! Show also a binary representation of each logged instruction (Assembler). kMachineCode = 0x00000001u, + //! Show aliases of some instructions that have them. + //! + //! This option is now mostly for x86/x64 to show aliases of instructions such as `cmov`, `j`, `set`, + //! etc... + kShowAliases = 0x00000008u, //! Show a text explanation of some immediate values. - kExplainImms = 0x00000002u, + kExplainImms = 0x00000010u, //! Use hexadecimal notation of immediate values. - kHexImms = 0x00000004u, + kHexImms = 0x00000020u, //! Use hexadecimal notation of addresses and offsets in addresses. - kHexOffsets = 0x00000008u, - //! Show casts between virtual register types (Compiler output). - kRegCasts = 0x00000010u, - //! Show positions associated with nodes (Compiler output). - kPositions = 0x00000020u, - //! Always format a register type (Compiler output). - kRegType = 0x00000040u + kHexOffsets = 0x00000040u, + //! Show casts between virtual register types (Compiler). + kRegCasts = 0x00000100u, + //! Show positions associated with nodes (Compiler). + kPositions = 0x00000200u, + //! Always format a register type (Compiler). + kRegType = 0x00000400u }; ASMJIT_DEFINE_ENUM_FLAGS(FormatFlags) diff --git a/src/asmjit/core/func.h b/src/asmjit/core/func.h index 79141fa..bb517c3 100644 --- a/src/asmjit/core/func.h +++ b/src/asmjit/core/func.h @@ -95,15 +95,6 @@ enum class CallConvId : uint8_t { //! Maximum value of `CallConvId`. kMaxValue = kX64Windows - - // Deprecated Aliases - // ------------------ - -#if !defined(ASMJIT_NO_DEPRECATED) - , - kNone = kCDecl, - kHost = kCDecl -#endif // !ASMJIT_NO_DEPRECATED }; //! Strategy used by calling conventions to assign registers to function arguments. @@ -536,19 +527,6 @@ struct FuncSignature { //! \} }; -#if !defined(ASMJIT_NO_DEPRECATED) -template -class FuncSignatureT : public FuncSignature { -public: - ASMJIT_DEPRECATED("Use FuncSignature::build() instead") - ASMJIT_INLINE_NODEBUG constexpr FuncSignatureT(CallConvId ccId = CallConvId::kCDecl, uint32_t vaIndex = kNoVarArgs) noexcept - : FuncSignature(ccId, vaIndex, (TypeId(TypeUtils::TypeIdOfT::kTypeId))... ) {} -}; - -ASMJIT_DEPRECATED("Use FuncSignature instead of FuncSignatureBuilder") -typedef FuncSignature FuncSignatureBuilder; -#endif // !ASMJIT_NO_DEPRECATED - //! Argument or return value (or its part) as defined by `FuncSignature`, but with register or stack address //! (and other metadata) assigned. struct FuncValue { diff --git a/src/asmjit/core/inst.cpp b/src/asmjit/core/inst.cpp index ade4ae0..da8a81e 100644 --- a/src/asmjit/core/inst.cpp +++ b/src/asmjit/core/inst.cpp @@ -21,15 +21,17 @@ ASMJIT_BEGIN_NAMESPACE // =========================== #ifndef ASMJIT_NO_TEXT -Error InstAPI::instIdToString(Arch arch, InstId instId, String& output) noexcept { +Error InstAPI::instIdToString(Arch arch, InstId instId, InstStringifyOptions options, String& output) noexcept { #if !defined(ASMJIT_NO_X86) - if (Environment::isFamilyX86(arch)) - return x86::InstInternal::instIdToString(instId, output); + if (Environment::isFamilyX86(arch)) { + return x86::InstInternal::instIdToString(instId, options, output); + } #endif #if !defined(ASMJIT_NO_AARCH64) - if (Environment::isFamilyAArch64(arch)) - return a64::InstInternal::instIdToString(instId, output); + if (Environment::isFamilyAArch64(arch)) { + return a64::InstInternal::instIdToString(instId, options, output); + } #endif return DebugUtils::errored(kErrorInvalidArch); @@ -37,13 +39,15 @@ Error InstAPI::instIdToString(Arch arch, InstId instId, String& output) noexcept InstId InstAPI::stringToInstId(Arch arch, const char* s, size_t len) noexcept { #if !defined(ASMJIT_NO_X86) - if (Environment::isFamilyX86(arch)) + if (Environment::isFamilyX86(arch)) { return x86::InstInternal::stringToInstId(s, len); + } #endif #if !defined(ASMJIT_NO_AARCH64) - if (Environment::isFamilyAArch64(arch)) + if (Environment::isFamilyAArch64(arch)) { return a64::InstInternal::stringToInstId(s, len); + } #endif return 0; @@ -57,16 +61,19 @@ InstId InstAPI::stringToInstId(Arch arch, const char* s, size_t len) noexcept { Error InstAPI::validate(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, ValidationFlags validationFlags) noexcept { #if !defined(ASMJIT_NO_X86) if (Environment::isFamilyX86(arch)) { - if (arch == Arch::kX86) + if (arch == Arch::kX86) { return x86::InstInternal::validateX86(inst, operands, opCount, validationFlags); - else + } + else { return x86::InstInternal::validateX64(inst, operands, opCount, validationFlags); + } } #endif #if !defined(ASMJIT_NO_AARCH64) - if (Environment::isFamilyAArch64(arch)) + if (Environment::isFamilyAArch64(arch)) { return a64::InstInternal::validate(inst, operands, opCount, validationFlags); + } #endif return DebugUtils::errored(kErrorInvalidArch); @@ -78,17 +85,20 @@ Error InstAPI::validate(Arch arch, const BaseInst& inst, const Operand_* operand #ifndef ASMJIT_NO_INTROSPECTION Error InstAPI::queryRWInfo(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, InstRWInfo* out) noexcept { - if (ASMJIT_UNLIKELY(opCount > Globals::kMaxOpCount)) + if (ASMJIT_UNLIKELY(opCount > Globals::kMaxOpCount)) { return DebugUtils::errored(kErrorInvalidArgument); + } #if !defined(ASMJIT_NO_X86) - if (Environment::isFamilyX86(arch)) + if (Environment::isFamilyX86(arch)) { return x86::InstInternal::queryRWInfo(arch, inst, operands, opCount, out); + } #endif #if !defined(ASMJIT_NO_AARCH64) - if (Environment::isFamilyAArch64(arch)) + if (Environment::isFamilyAArch64(arch)) { return a64::InstInternal::queryRWInfo(inst, operands, opCount, out); + } #endif return DebugUtils::errored(kErrorInvalidArch); @@ -101,13 +111,15 @@ Error InstAPI::queryRWInfo(Arch arch, const BaseInst& inst, const Operand_* oper #ifndef ASMJIT_NO_INTROSPECTION Error InstAPI::queryFeatures(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, CpuFeatures* out) noexcept { #if !defined(ASMJIT_NO_X86) - if (Environment::isFamilyX86(arch)) + if (Environment::isFamilyX86(arch)) { return x86::InstInternal::queryFeatures(arch, inst, operands, opCount, out); + } #endif #if !defined(ASMJIT_NO_AARCH64) - if (Environment::isFamilyAArch64(arch)) + if (Environment::isFamilyAArch64(arch)) { return a64::InstInternal::queryFeatures(inst, operands, opCount, out); + } #endif return DebugUtils::errored(kErrorInvalidArch); diff --git a/src/asmjit/core/inst.h b/src/asmjit/core/inst.h index a653fe8..d2b1d80 100644 --- a/src/asmjit/core/inst.h +++ b/src/asmjit/core/inst.h @@ -201,6 +201,21 @@ enum class InstSameRegHint : uint8_t { kWO = 2 }; +//! Options that can be used when converting instruction IDs to strings. +enum class InstStringifyOptions : uint32_t { + //! No options. + kNone = 0x00000000u, + + //! Stringify a full instruction name with known aliases. + //! + //! This option is designed for architectures where instruction aliases are common, for example X86, and where + //! multiple aliases can be used in assembly code to distinguish between intention - for example instructions + //! such as JZ and JE are the same, but the first is used in a context of equality to zero, and the second is + //! used when two values equal (for example JE next to CMP). + kAliases = 0x00000001u +}; +ASMJIT_DEFINE_ENUM_FLAGS(InstStringifyOptions) + //! Instruction id, options, and extraReg in a single structure. This structure exists mainly to simplify analysis //! and validation API that requires `BaseInst` and `Operand[]` array. class BaseInst { @@ -769,11 +784,16 @@ ASMJIT_DEFINE_ENUM_FLAGS(ValidationFlags) namespace InstAPI { #ifndef ASMJIT_NO_TEXT -//! Appends the name of the instruction specified by `instId` and `instOptions` into the `output` string. +//! Appends the name of the instruction specified by `instId` and `options` into the `output` string. //! //! \note Instruction options would only affect instruction prefix & suffix, other options would be ignored. //! If `instOptions` is zero then only raw instruction name (without any additional text) will be appended. -ASMJIT_API Error instIdToString(Arch arch, InstId instId, String& output) noexcept; +ASMJIT_API Error instIdToString(Arch arch, InstId instId, InstStringifyOptions options, String& output) noexcept; + +ASMJIT_DEPRECATED("Use `instIdToString()` with `InstStringifyOptions` parameter") +static inline Error instIdToString(Arch arch, InstId instId, String& output) noexcept { + return instIdToString(arch, instId, InstStringifyOptions::kNone, output); +} //! Parses an instruction name in the given string `s`. Length is specified by `len` argument, which can be //! `SIZE_MAX` if `s` is known to be null terminated. diff --git a/src/asmjit/core/instdb.cpp b/src/asmjit/core/instdb.cpp index cde369f..5fae708 100644 --- a/src/asmjit/core/instdb.cpp +++ b/src/asmjit/core/instdb.cpp @@ -17,11 +17,14 @@ static ASMJIT_FORCE_INLINE char decode5BitChar(uint32_t c) noexcept { return char(base + c); } -static ASMJIT_FORCE_INLINE size_t decodeToBuffer(char nameOut[kBufferSize], uint32_t nameValue, const char* stringTable) noexcept { +static ASMJIT_FORCE_INLINE size_t decodeToBuffer(char nameOut[kBufferSize], uint32_t nameValue, InstStringifyOptions options, const char* stringTable) noexcept { size_t i; if (nameValue & 0x80000000u) { // Small string of 5-bit characters. + // + // NOTE: Small string optimization never provides additional + // aliases formatting, so we don't have to consider `options`. for (i = 0; i < 6; i++, nameValue >>= 5) { uint32_t c = nameValue & 0x1F; if (c == 0) @@ -37,52 +40,61 @@ static ASMJIT_FORCE_INLINE size_t decodeToBuffer(char nameOut[kBufferSize], uint size_t suffixBase = (nameValue >> 16) & 0xFFFu; size_t suffixSize = (nameValue >> 28) & 0x7u; - for (i = 0; i < prefixSize; i++) + if (Support::test(options, InstStringifyOptions::kAliases) && suffixBase == 0xFFFu) { + // Alias formatting immediately follows the instruction name in string table. + // The first character specifies the length and then string data follows. + prefixBase += prefixSize; + prefixSize = uint8_t(stringTable[prefixBase]); + ASMJIT_ASSERT(prefixSize <= kBufferSize); + + prefixBase += 1; // Skip the byte that specifies the length of a formatted alias. + } + + for (i = 0; i < prefixSize; i++) { nameOut[i] = stringTable[prefixBase + i]; + } char* suffixOut = nameOut + prefixSize; - for (i = 0; i < suffixSize; i++) + for (i = 0; i < suffixSize; i++) { suffixOut[i] = stringTable[suffixBase + i]; + } return prefixSize + suffixSize; } } -Error decode(String& output, uint32_t nameValue, const char* stringTable) noexcept { +Error decode(uint32_t nameValue, InstStringifyOptions options, const char* stringTable, String& output) noexcept { char nameData[kBufferSize]; - size_t nameSize = decodeToBuffer(nameData, nameValue, stringTable); + size_t nameSize = decodeToBuffer(nameData, nameValue, options, stringTable); return output.append(nameData, nameSize); } -InstId find(const char* s, size_t len, const InstNameIndex& nameIndex, const uint32_t* nameTable, const char* stringTable) noexcept { - if (ASMJIT_UNLIKELY(!s)) - return BaseInst::kIdNone; +InstId findInstruction(const char* s, size_t len, const uint32_t* nameTable, const char* stringTable, const InstNameIndex& nameIndex) noexcept { + ASMJIT_ASSERT(s != nullptr); + ASMJIT_ASSERT(len > 0u); - if (len == SIZE_MAX) - len = strlen(s); - - if (ASMJIT_UNLIKELY(len == 0 || len > nameIndex.maxNameLength)) - return BaseInst::kIdNone; - - uint32_t prefix = uint32_t(s[0]) - 'a'; - if (ASMJIT_UNLIKELY(prefix > 'z' - 'a')) + uint32_t prefix = uint32_t(s[0]) - uint32_t('a'); + if (ASMJIT_UNLIKELY(prefix > uint32_t('z') - uint32_t('a'))) { return BaseInst::kIdNone; + } size_t base = nameIndex.data[prefix].start; size_t end = nameIndex.data[prefix].end; - if (ASMJIT_UNLIKELY(!base)) + if (ASMJIT_UNLIKELY(!base)) { return BaseInst::kIdNone; + } char nameData[kBufferSize]; for (size_t lim = end - base; lim != 0; lim >>= 1) { size_t instId = base + (lim >> 1); - size_t nameSize = decodeToBuffer(nameData, nameTable[instId], stringTable); + size_t nameSize = decodeToBuffer(nameData, nameTable[instId], InstStringifyOptions::kNone, stringTable); int result = Support::compareStringViews(s, len, nameData, nameSize); - if (result < 0) + if (result < 0) { continue; + } if (result > 0) { base = instId + 1; @@ -96,6 +108,35 @@ InstId find(const char* s, size_t len, const InstNameIndex& nameIndex, const uin return BaseInst::kIdNone; } + +uint32_t findAlias(const char* s, size_t len, const uint32_t* nameTable, const char* stringTable, uint32_t aliasNameCount) noexcept { + ASMJIT_ASSERT(s != nullptr); + ASMJIT_ASSERT(len > 0u); + + size_t base = 0; + char nameData[kBufferSize]; + + for (size_t lim = size_t(aliasNameCount) - base; lim != 0; lim >>= 1) { + size_t index = base + (lim >> 1); + size_t nameSize = decodeToBuffer(nameData, nameTable[index], InstStringifyOptions::kNone, stringTable); + + int result = Support::compareStringViews(s, len, nameData, nameSize); + if (result < 0) { + continue; + } + + if (result > 0) { + base = index + 1; + lim--; + continue; + } + + return uint32_t(index); + } + + return Globals::kInvalidId; +} + } // {InstNameUtils} ASMJIT_END_NAMESPACE diff --git a/src/asmjit/core/instdb_p.h b/src/asmjit/core/instdb_p.h index b5afb72..9360565 100644 --- a/src/asmjit/core/instdb_p.h +++ b/src/asmjit/core/instdb_p.h @@ -27,8 +27,9 @@ struct InstNameIndex { namespace InstNameUtils { -Error decode(String& output, uint32_t nameValue, const char* stringTable) noexcept; -InstId find(const char* s, size_t len, const InstNameIndex& nameIndex, const uint32_t* nameTable, const char* stringTable) noexcept; +Error decode(uint32_t nameValue, InstStringifyOptions options, const char* stringTable, String& output) noexcept; +InstId findInstruction(const char* s, size_t len, const uint32_t* nameTable, const char* stringTable, const InstNameIndex& nameIndex) noexcept; +uint32_t findAlias(const char* s, size_t len, const uint32_t* nameTable, const char* stringTable, uint32_t aliasNameCount) noexcept; } // {InstNameUtils} diff --git a/src/asmjit/core/jitallocator.h b/src/asmjit/core/jitallocator.h index b694f8c..ed0b76b 100644 --- a/src/asmjit/core/jitallocator.h +++ b/src/asmjit/core/jitallocator.h @@ -323,35 +323,6 @@ public: //! If the pointer is matched, the function returns `kErrorOk` and fills `out` with the corresponding span. ASMJIT_API Error query(Span& out, void* rx) const noexcept; -#if !defined(ASMJIT_NO_DEPRECATED) - //! Allocates a new memory block of the requested `size`. - ASMJIT_DEPRECATED("Use alloc(Span& out, size_t size) instead") - ASMJIT_FORCE_INLINE Error alloc(void** rxPtrOut, void** rwPtrOut, size_t size) noexcept { - Span span; - Error err = alloc(span, size); - *rwPtrOut = span.rw(); - *rxPtrOut = span.rx(); - return err; - } - - ASMJIT_DEPRECATED("Use shrink(Span& span, size_t newSize) instead") - ASMJIT_FORCE_INLINE Error shrink(void* rxPtr, size_t newSize) noexcept { - Span span; - ASMJIT_PROPAGATE(query(span, rxPtr)); - return (span.size() > newSize) ? shrink(span, newSize) : Error(kErrorOk); - } - - ASMJIT_DEPRECATED("Use query(Span& out, void* rx) instead") - ASMJIT_FORCE_INLINE Error query(void* rxPtr, void** rxPtrOut, void** rwPtrOut, size_t* sizeOut) const noexcept { - Span span; - Error err = query(span, rxPtr); - *rxPtrOut = span.rx(); - *rwPtrOut = span.rw(); - *sizeOut = span.size(); - return err; - } -#endif - //! \} //! \name Write Operations diff --git a/src/asmjit/core/operand.h b/src/asmjit/core/operand.h index 3626779..01b1cb9 100644 --- a/src/asmjit/core/operand.h +++ b/src/asmjit/core/operand.h @@ -745,17 +745,6 @@ struct Operand_ { ASMJIT_INLINE_NODEBUG constexpr uint32_t x86RmSize() const noexcept { return _signature.size(); } //! \} - -#if !defined(ASMJIT_NO_DEPRECATED) - ASMJIT_DEPRECATED("hasSize() is no longer portable - use x86RmSize() or x86::Mem::hasSize() instead, if your target is X86/X86_64") - ASMJIT_INLINE_NODEBUG constexpr bool hasSize() const noexcept { return x86RmSize() != 0u; } - - ASMJIT_DEPRECATED("hasSize() is no longer portable - use x86RmSize() or x86::Mem::hasSize() instead, if your target is X86/X86_64") - ASMJIT_INLINE_NODEBUG constexpr bool hasSize(uint32_t s) const noexcept { return x86RmSize() == s; } - - ASMJIT_DEPRECATED("size() is no longer portable - use x86RmSize() or x86::Mem::size() instead, if your target is X86/X86_64") - ASMJIT_INLINE_NODEBUG constexpr uint32_t size() const noexcept { return _signature.getField(); } -#endif }; //! Base class representing an operand in AsmJit (default constructed version). @@ -1665,11 +1654,6 @@ public: ASMJIT_INLINE_NODEBUG void resetOffsetLo32() noexcept { setOffsetLo32(0); } //! \} - -#if !defined(ASMJIT_NO_DEPRECATED) - ASMJIT_DEPRECATED("setSize() is no longer portable - use setX86RmSize() or x86::Mem::setSize() instead, if your target is X86/X86_64") - ASMJIT_INLINE_NODEBUG void setSize(uint32_t size) noexcept { _signature.setField(size); } -#endif }; //! Type of the an immediate value. diff --git a/src/asmjit/core/string.h b/src/asmjit/core/string.h index c4dee14..c664820 100644 --- a/src/asmjit/core/string.h +++ b/src/asmjit/core/string.h @@ -55,11 +55,6 @@ union FixedString { inline bool equals(const char* other) const noexcept { return strcmp(str, other) == 0; } -#if !defined(ASMJIT_NO_DEPRECATED) - ASMJIT_DEPRECATED("Use FixedString::equals() instead") - inline bool eq(const char* other) const noexcept { return equals(other); } -#endif // !ASMJIT_NO_DEPRECATED - //! \} }; @@ -318,14 +313,6 @@ public: ASMJIT_API bool equals(const char* other, size_t size = SIZE_MAX) const noexcept; ASMJIT_INLINE_NODEBUG bool equals(const String& other) const noexcept { return equals(other.data(), other.size()); } -#if !defined(ASMJIT_NO_DEPRECATED) - ASMJIT_DEPRECATED("Use String::equals() instead") - ASMJIT_INLINE_NODEBUG bool eq(const char* other, size_t size = SIZE_MAX) const noexcept { return equals(other, size); } - - ASMJIT_DEPRECATED("Use String::equals() instead") - ASMJIT_INLINE_NODEBUG bool eq(const String& other) const noexcept { return equals(other.data(), other.size()); } -#endif // !ASMJIT_NO_DEPRECATED - //! \} //! \name Internal Functions diff --git a/src/asmjit/core/zonevector.h b/src/asmjit/core/zonevector.h index f38dca5..7607613 100644 --- a/src/asmjit/core/zonevector.h +++ b/src/asmjit/core/zonevector.h @@ -690,11 +690,6 @@ public: return true; } -#if !defined(ASMJIT_NO_DEPRECATED) - ASMJIT_DEPRECATED("Use ZoneVector::equals() instead") - ASMJIT_FORCE_INLINE bool eq(const ZoneBitVector& other) const noexcept { return equals(other); } -#endif // !ASMJIT_NO_DEPRECATED - //! \} //! \name Memory Management diff --git a/src/asmjit/x86/x86assembler.cpp b/src/asmjit/x86/x86assembler.cpp index be1607d..2478c6d 100644 --- a/src/asmjit/x86/x86assembler.cpp +++ b/src/asmjit/x86/x86assembler.cpp @@ -2976,13 +2976,6 @@ CaseExtRm: } break; - case InstDB::kEncodingVexM_VM: - if (isign3 == ENC_OPS1(Mem)) { - rmRel = &o0; - goto EmitVexEvexM; - } - break; - case InstDB::kEncodingVexMr_Lx: opcode |= x86OpcodeLBySize(o0.x86RmSize() | o1.x86RmSize()); @@ -3110,28 +3103,6 @@ CaseVexRm: } break; - case InstDB::kEncodingVexRm_T1_4X: { - const Operand_& o3 = opExt[EmitterUtils::kOp3]; - const Operand_& o4 = opExt[EmitterUtils::kOp4]; - const Operand_& o5 = opExt[EmitterUtils::kOp5]; - - if (Reg::isVec(o0) && Reg::isVec(o1) && Reg::isVec(o2) && Reg::isVec(o3) && Reg::isVec(o4) && o5.isMem()) { - // Registers [o1, o2, o3, o4] must start aligned and must be consecutive. - uint32_t i1 = o1.id(); - uint32_t i2 = o2.id(); - uint32_t i3 = o3.id(); - uint32_t i4 = o4.id(); - - if (ASMJIT_UNLIKELY((i1 & 0x3) != 0 || i2 != i1 + 1 || i3 != i1 + 2 || i4 != i1 + 3)) - goto NotConsecutiveRegs; - - opReg = x86PackRegAndVvvvv(o0.id(), i1); - rmRel = &o5; - goto EmitVexEvexM; - } - break; - } - case InstDB::kEncodingVexRmi_Wx: opcode.addWIf(unsigned(Reg::isGpq(o0)) | unsigned(Reg::isGpq(o1))); goto CaseVexRmi; @@ -5000,7 +4971,6 @@ EmitDone: ERROR_HANDLER(InvalidBroadcast) ERROR_HANDLER(OperandSizeMismatch) ERROR_HANDLER(AmbiguousOperandSize) - ERROR_HANDLER(NotConsecutiveRegs) #undef ERROR_HANDLER Failed: diff --git a/src/asmjit/x86/x86emitter.h b/src/asmjit/x86/x86emitter.h index de6178b..47f8ba0 100644 --- a/src/asmjit/x86/x86emitter.h +++ b/src/asmjit/x86/x86emitter.h @@ -580,10 +580,10 @@ public: ASMJIT_INST_2x(sbb, Sbb, Gp, Imm) // ANY ASMJIT_INST_2x(sbb, Sbb, Mem, Gp) // ANY ASMJIT_INST_2x(sbb, Sbb, Mem, Imm) // ANY - ASMJIT_INST_2x(sal, Sal, Gp, Gp_CL) // ANY - ASMJIT_INST_2x(sal, Sal, Mem, Gp_CL) // ANY - ASMJIT_INST_2x(sal, Sal, Gp, Imm) // ANY - ASMJIT_INST_2x(sal, Sal, Mem, Imm) // ANY + ASMJIT_INST_2x(sal, Shl, Gp, Gp_CL) // ANY + ASMJIT_INST_2x(sal, Shl, Mem, Gp_CL) // ANY + ASMJIT_INST_2x(sal, Shl, Gp, Imm) // ANY + ASMJIT_INST_2x(sal, Shl, Mem, Imm) // ANY ASMJIT_INST_2x(sar, Sar, Gp, Gp_CL) // ANY ASMJIT_INST_2x(sar, Sar, Mem, Gp_CL) // ANY ASMJIT_INST_2x(sar, Sar, Gp, Imm) // ANY @@ -2242,10 +2242,6 @@ public: ASMJIT_INST_3x(kxord, Kxord, KReg, KReg, KReg) // AVX512_BW ASMJIT_INST_3x(kxorq, Kxorq, KReg, KReg, KReg) // AVX512_BW ASMJIT_INST_3x(kxorw, Kxorw, KReg, KReg, KReg) // AVX512_F - ASMJIT_INST_6x(v4fmaddps, V4fmaddps, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz} - ASMJIT_INST_6x(v4fmaddss, V4fmaddss, Xmm, Xmm, Xmm, Xmm, Xmm, Mem) // AVX512_4FMAPS{kz} - ASMJIT_INST_6x(v4fnmaddps, V4fnmaddps, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz} - ASMJIT_INST_6x(v4fnmaddss, V4fnmaddss, Xmm, Xmm, Xmm, Xmm, Xmm, Mem) // AVX512_4FMAPS{kz} ASMJIT_INST_3x(vaddpd, Vaddpd, Vec, Vec, Vec) // AVX AVX512_F{kz|b64} ASMJIT_INST_3x(vaddpd, Vaddpd, Vec, Vec, Mem) // AVX AVX512_F{kz|b64} ASMJIT_INST_3x(vaddps, Vaddps, Vec, Vec, Vec) // AVX AVX512_F{kz|b32} @@ -2442,10 +2438,6 @@ public: ASMJIT_INST_4x(vdppd, Vdppd, Vec, Vec, Mem, Imm) // AVX ASMJIT_INST_4x(vdpps, Vdpps, Vec, Vec, Vec, Imm) // AVX ASMJIT_INST_4x(vdpps, Vdpps, Vec, Vec, Mem, Imm) // AVX - ASMJIT_INST_2x(vexp2pd, Vexp2pd, Vec, Vec) // AVX512_ER{kz|sae|b64} - ASMJIT_INST_2x(vexp2pd, Vexp2pd, Vec, Mem) // AVX512_ER{kz|sae|b64} - ASMJIT_INST_2x(vexp2ps, Vexp2ps, Vec, Vec) // AVX512_ER{kz|sae|b32} - ASMJIT_INST_2x(vexp2ps, Vexp2ps, Vec, Mem) // AVX512_ER{kz|sae|b32} ASMJIT_INST_2x(vexpandpd, Vexpandpd, Vec, Vec) // AVX512_F{kz} ASMJIT_INST_2x(vexpandpd, Vexpandpd, Vec, Mem) // AVX512_F{kz} ASMJIT_INST_2x(vexpandps, Vexpandps, Vec, Vec) // AVX512_F{kz} @@ -2612,14 +2604,6 @@ public: ASMJIT_INST_3x(vgatherdpd, Vgatherdpd, Vec, Mem, Vec) // AVX2 ASMJIT_INST_2x(vgatherdps, Vgatherdps, Vec, Mem) // AVX512_F{k} ASMJIT_INST_3x(vgatherdps, Vgatherdps, Vec, Mem, Vec) // AVX2 - ASMJIT_INST_1x(vgatherpf0dpd, Vgatherpf0dpd, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vgatherpf0dps, Vgatherpf0dps, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vgatherpf0qpd, Vgatherpf0qpd, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vgatherpf0qps, Vgatherpf0qps, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vgatherpf1dpd, Vgatherpf1dpd, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vgatherpf1dps, Vgatherpf1dps, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vgatherpf1qpd, Vgatherpf1qpd, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vgatherpf1qps, Vgatherpf1qps, Mem) // AVX512_PF{k} ASMJIT_INST_2x(vgatherqpd, Vgatherqpd, Vec, Mem) // AVX512_F{k} ASMJIT_INST_3x(vgatherqpd, Vgatherqpd, Vec, Mem, Vec) // AVX2 ASMJIT_INST_2x(vgatherqps, Vgatherqps, Vec, Mem) // AVX512_F{k} @@ -2790,8 +2774,6 @@ public: ASMJIT_INST_4x(vp2intersectd, Vp2intersectd, KReg, KReg, Vec, Mem) // AVX512_VP2INTERSECT{kz} ASMJIT_INST_4x(vp2intersectq, Vp2intersectq, KReg, KReg, Vec, Vec) // AVX512_VP2INTERSECT{kz} ASMJIT_INST_4x(vp2intersectq, Vp2intersectq, KReg, KReg, Vec, Mem) // AVX512_VP2INTERSECT{kz} - ASMJIT_INST_6x(vp4dpwssd, Vp4dpwssd, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz} - ASMJIT_INST_6x(vp4dpwssds, Vp4dpwssds, Zmm, Zmm, Zmm, Zmm, Zmm, Mem) // AVX512_4FMAPS{kz} ASMJIT_INST_2x(vpabsb, Vpabsb, Vec, Vec) // AVX+ AVX512_BW{kz} ASMJIT_INST_2x(vpabsb, Vpabsb, Vec, Mem) // AVX+ AVX512_BW{kz} ASMJIT_INST_2x(vpabsd, Vpabsd, Vec, Vec) // AVX+ AVX512_F{kz} @@ -3391,14 +3373,6 @@ public: ASMJIT_INST_3x(vrcp14sd, Vrcp14sd, Xmm, Xmm, Mem) // AVX512_F{kz} ASMJIT_INST_3x(vrcp14ss, Vrcp14ss, Xmm, Xmm, Xmm) // AVX512_F{kz} ASMJIT_INST_3x(vrcp14ss, Vrcp14ss, Xmm, Xmm, Mem) // AVX512_F{kz} - ASMJIT_INST_2x(vrcp28pd, Vrcp28pd, Vec, Vec) // AVX512_ER{kz|sae|b64} - ASMJIT_INST_2x(vrcp28pd, Vrcp28pd, Vec, Mem) // AVX512_ER{kz|sae|b64} - ASMJIT_INST_2x(vrcp28ps, Vrcp28ps, Vec, Vec) // AVX512_ER{kz|sae|b32} - ASMJIT_INST_2x(vrcp28ps, Vrcp28ps, Vec, Mem) // AVX512_ER{kz|sae|b32} - ASMJIT_INST_3x(vrcp28sd, Vrcp28sd, Xmm, Xmm, Xmm) // AVX512_ER{kz|sae} - ASMJIT_INST_3x(vrcp28sd, Vrcp28sd, Xmm, Xmm, Mem) // AVX512_ER{kz|sae} - ASMJIT_INST_3x(vrcp28ss, Vrcp28ss, Xmm, Xmm, Xmm) // AVX512_ER{kz|sae} - ASMJIT_INST_3x(vrcp28ss, Vrcp28ss, Xmm, Xmm, Mem) // AVX512_ER{kz|sae} ASMJIT_INST_2x(vrcpps, Vrcpps, Vec, Vec) // AVX ASMJIT_INST_2x(vrcpps, Vrcpps, Vec, Mem) // AVX ASMJIT_INST_3x(vrcpss, Vrcpss, Xmm, Xmm, Xmm) // AVX @@ -3435,14 +3409,6 @@ public: ASMJIT_INST_3x(vrsqrt14sd, Vrsqrt14sd, Xmm, Xmm, Mem) // AVX512_F{kz} ASMJIT_INST_3x(vrsqrt14ss, Vrsqrt14ss, Xmm, Xmm, Xmm) // AVX512_F{kz} ASMJIT_INST_3x(vrsqrt14ss, Vrsqrt14ss, Xmm, Xmm, Mem) // AVX512_F{kz} - ASMJIT_INST_2x(vrsqrt28pd, Vrsqrt28pd, Vec, Vec) // AVX512_ER{kz|sae|b64} - ASMJIT_INST_2x(vrsqrt28pd, Vrsqrt28pd, Vec, Mem) // AVX512_ER{kz|sae|b64} - ASMJIT_INST_2x(vrsqrt28ps, Vrsqrt28ps, Vec, Vec) // AVX512_ER{kz|sae|b32} - ASMJIT_INST_2x(vrsqrt28ps, Vrsqrt28ps, Vec, Mem) // AVX512_ER{kz|sae|b32} - ASMJIT_INST_3x(vrsqrt28sd, Vrsqrt28sd, Xmm, Xmm, Xmm) // AVX512_ER{kz|sae} - ASMJIT_INST_3x(vrsqrt28sd, Vrsqrt28sd, Xmm, Xmm, Mem) // AVX512_ER{kz|sae} - ASMJIT_INST_3x(vrsqrt28ss, Vrsqrt28ss, Xmm, Xmm, Xmm) // AVX512_ER{kz|sae} - ASMJIT_INST_3x(vrsqrt28ss, Vrsqrt28ss, Xmm, Xmm, Mem) // AVX512_ER{kz|sae} ASMJIT_INST_2x(vrsqrtps, Vrsqrtps, Vec, Vec) // AVX ASMJIT_INST_2x(vrsqrtps, Vrsqrtps, Vec, Mem) // AVX ASMJIT_INST_3x(vrsqrtss, Vrsqrtss, Xmm, Xmm, Xmm) // AVX @@ -3457,14 +3423,6 @@ public: ASMJIT_INST_3x(vscalefss, Vscalefss, Xmm, Xmm, Mem) // AVX512_F{kz|er} ASMJIT_INST_2x(vscatterdpd, Vscatterdpd, Mem, Vec) // AVX512_F{k} ASMJIT_INST_2x(vscatterdps, Vscatterdps, Mem, Vec) // AVX512_F{k} - ASMJIT_INST_1x(vscatterpf0dpd, Vscatterpf0dpd, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vscatterpf0dps, Vscatterpf0dps, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vscatterpf0qpd, Vscatterpf0qpd, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vscatterpf0qps, Vscatterpf0qps, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vscatterpf1dpd, Vscatterpf1dpd, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vscatterpf1dps, Vscatterpf1dps, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vscatterpf1qpd, Vscatterpf1qpd, Mem) // AVX512_PF{k} - ASMJIT_INST_1x(vscatterpf1qps, Vscatterpf1qps, Mem) // AVX512_PF{k} ASMJIT_INST_2x(vscatterqpd, Vscatterqpd, Mem, Vec) // AVX512_F{k} ASMJIT_INST_2x(vscatterqps, Vscatterqps, Mem, Vec) // AVX512_F{k} ASMJIT_INST_4x(vshuff32x4, Vshuff32x4, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32} diff --git a/src/asmjit/x86/x86formatter.cpp b/src/asmjit/x86/x86formatter.cpp index 67b38df..f121225 100644 --- a/src/asmjit/x86/x86formatter.cpp +++ b/src/asmjit/x86/x86formatter.cpp @@ -210,42 +210,9 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept "None\0" "MT\0" "NX\0" - "3DNOW\0" - "3DNOW2\0" "ADX\0" - "AESNI\0" "ALTMOVCR8\0" - "AMX_BF16\0" - "AMX_COMPLEX\0" - "AMX_FP16\0" - "AMX_INT8\0" - "AMX_TILE\0" "APX_F\0" - "AVX\0" - "AVX2\0" - "AVX512_4FMAPS\0" - "AVX512_4VNNIW\0" - "AVX512_BF16\0" - "AVX512_BITALG\0" - "AVX512_BW\0" - "AVX512_CD\0" - "AVX512_DQ\0" - "AVX512_ER\0" - "AVX512_F\0" - "AVX512_FP16\0" - "AVX512_IFMA\0" - "AVX512_PF\0" - "AVX512_VBMI\0" - "AVX512_VBMI2\0" - "AVX512_VL\0" - "AVX512_VNNI\0" - "AVX512_VP2INTERSECT\0" - "AVX512_VPOPCNTDQ\0" - "AVX_IFMA\0" - "AVX_NE_CONVERT\0" - "AVX_VNNI\0" - "AVX_VNNI_INT16\0" - "AVX_VNNI_INT8\0" "BMI\0" "BMI2\0" "CET_IBT\0" @@ -263,10 +230,6 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept "ENCLV\0" "ENQCMD\0" "ERMS\0" - "F16C\0" - "FMA\0" - "FMA4\0" - "FPU\0" "FSGSBASE\0" "FSRM\0" "FSRC\0" @@ -274,9 +237,6 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept "FXSR\0" "FXSROPT\0" "FZRM\0" - "GEODE\0" - "GFNI\0" - "HLE\0" "HRESET\0" "I486\0" "INVLPGB\0" @@ -285,20 +245,19 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept "LWP\0" "LZCNT\0" "MCOMMIT\0" - "MMX\0" - "MMX2\0" "MONITOR\0" "MONITORX\0" "MOVBE\0" "MOVDIR64B\0" "MOVDIRI\0" + "MOVRS\0" "MPX\0" "MSR\0" "MSRLIST\0" + "MSR_IMM\0" "MSSE\0" "OSXSAVE\0" "OSPKE\0" - "PCLMULQDQ\0" "PCONFIG\0" "POPCNT\0" "PREFETCHI\0" @@ -319,52 +278,99 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept "SEV\0" "SEV_ES\0" "SEV_SNP\0" - "SHA\0" - "SHA512\0" "SKINIT\0" - "SM3\0" - "SM4\0" "SMAP\0" "SME\0" "SMEP\0" "SMX\0" - "SSE\0" - "SSE2\0" - "SSE3\0" - "SSE4_1\0" - "SSE4_2\0" - "SSE4A\0" - "SSSE3\0" "SVM\0" "TBM\0" "TSE\0" - "TSX\0" "TSXLDTRK\0" "UINTR\0" - "VAES\0" "VMX\0" - "VPCLMULQDQ\0" "WAITPKG\0" "WBNOINVD\0" "WRMSRNS\0" - "XOP\0" "XSAVE\0" "XSAVEC\0" "XSAVEOPT\0" "XSAVES\0" + "FPU\0" + "MMX\0" + "MMX2\0" + "3DNOW\0" + "3DNOW2\0" + "GEODE\0" + "SSE\0" + "SSE2\0" + "SSE3\0" + "SSSE3\0" + "SSE4_1\0" + "SSE4_2\0" + "SSE4A\0" + "PCLMULQDQ\0" + "AVX\0" + "AVX2\0" + "AVX_IFMA\0" + "AVX_NE_CONVERT\0" + "AVX_VNNI\0" + "AVX_VNNI_INT16\0" + "AVX_VNNI_INT8\0" + "F16C\0" + "FMA\0" + "FMA4\0" + "XOP\0" + "AVX512_BF16\0" + "AVX512_BITALG\0" + "AVX512_BW\0" + "AVX512_CD\0" + "AVX512_DQ\0" + "AVX512_F\0" + "AVX512_FP16\0" + "AVX512_IFMA\0" + "AVX512_VBMI\0" + "AVX512_VBMI2\0" + "AVX512_VL\0" + "AVX512_VNNI\0" + "AVX512_VP2INTERSECT\0" + "AVX512_VPOPCNTDQ\0" + "AESNI\0" + "GFNI\0" + "SHA\0" + "SHA512\0" + "SM3\0" + "SM4\0" + "VAES\0" + "VPCLMULQDQ\0" + "KL\0" + "AESKLE\0" + "AESKLEWIDE_KL\0" + "AVX10_1\0" + "AVX10_2\0" + "AMX_AVX512\0" + "AMX_BF16\0" + "AMX_COMPLEX\0" + "AMX_FP16\0" + "AMX_FP8\0" + "AMX_INT8\0" + "AMX_MOVRS\0" + "AMX_TF32\0" + "AMX_TILE\0" + "AMX_TRANSPOSE\0" "\0"; static const uint16_t sFeatureIndex[] = { - 0, 5, 8, 11, 17, 24, 28, 34, 44, 53, 65, 74, 83, 92, 98, 102, 107, 121, 135, - 147, 161, 171, 181, 191, 201, 210, 222, 234, 244, 256, 269, 279, 291, 311, - 328, 337, 352, 361, 376, 390, 394, 399, 407, 414, 422, 431, 439, 450, 455, - 462, 467, 477, 488, 498, 504, 511, 516, 521, 525, 530, 534, 543, 548, 553, - 558, 563, 571, 576, 582, 587, 591, 598, 603, 611, 620, 624, 628, 634, 642, - 646, 651, 659, 668, 674, 684, 692, 696, 700, 708, 713, 721, 727, 737, 745, - 752, 762, 772, 784, 792, 800, 809, 815, 821, 828, 835, 841, 848, 852, 857, - 867, 871, 878, 886, 890, 897, 904, 908, 912, 917, 921, 926, 930, 934, 939, - 944, 951, 958, 964, 970, 974, 978, 982, 986, 995, 1001, 1006, 1010, 1021, - 1029, 1038, 1046, 1050, 1056, 1063, 1072, 1079 + 0, 5, 8, 11, 15, 25, 31, 35, 40, 48, 55, 63, 72, 80, 91, 96, 103, 108, 118, + 129, 139, 145, 152, 157, 166, 171, 176, 181, 186, 194, 199, 206, 211, 219, + 228, 232, 236, 242, 250, 258, 267, 273, 283, 291, 297, 301, 305, 313, 321, + 326, 334, 340, 348, 355, 365, 375, 387, 395, 403, 412, 418, 424, 431, 438, + 444, 451, 455, 460, 470, 474, 481, 489, 496, 501, 505, 510, 514, 518, 522, + 526, 535, 541, 545, 553, 562, 570, 576, 583, 592, 599, 603, 607, 612, 618, + 625, 631, 635, 640, 645, 651, 658, 665, 671, 681, 685, 690, 699, 714, 723, + 738, 752, 757, 761, 766, 770, 782, 796, 806, 816, 826, 835, 847, 859, 871, + 884, 894, 906, 926, 943, 949, 954, 958, 965, 969, 973, 978, 989, 992, 999, + 1013, 1021, 1029, 1040, 1049, 1061, 1070, 1078, 1087, 1097, 1106, 1115, 1129 }; // @EnumStringEnd@ @@ -929,7 +935,12 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatInstruction( } } - ASMJIT_PROPAGATE(InstInternal::instIdToString(instId, sb)); + InstStringifyOptions stringifyOptions = + Support::test(formatFlags, FormatFlags::kShowAliases) + ? InstStringifyOptions::kAliases + : InstStringifyOptions::kNone; + + ASMJIT_PROPAGATE(InstInternal::instIdToString(instId, stringifyOptions, sb)); } else { ASMJIT_PROPAGATE(sb.appendFormat("[InstId=#%u]", unsigned(instId))); diff --git a/src/asmjit/x86/x86globals.h b/src/asmjit/x86/x86globals.h index 160a04e..71264c5 100644 --- a/src/asmjit/x86/x86globals.h +++ b/src/asmjit/x86/x86globals.h @@ -203,24 +203,12 @@ namespace Inst { kIdClwb, //!< Instruction 'clwb' {CLWB}. kIdClzero, //!< Instruction 'clzero' {CLZERO}. kIdCmc, //!< Instruction 'cmc'. - kIdCmova, //!< Instruction 'cmova' {CMOV}. - kIdCmovae, //!< Instruction 'cmovae' {CMOV}. kIdCmovb, //!< Instruction 'cmovb' {CMOV}. kIdCmovbe, //!< Instruction 'cmovbe' {CMOV}. - kIdCmovc, //!< Instruction 'cmovc' {CMOV}. - kIdCmove, //!< Instruction 'cmove' {CMOV}. - kIdCmovg, //!< Instruction 'cmovg' {CMOV}. - kIdCmovge, //!< Instruction 'cmovge' {CMOV}. kIdCmovl, //!< Instruction 'cmovl' {CMOV}. kIdCmovle, //!< Instruction 'cmovle' {CMOV}. - kIdCmovna, //!< Instruction 'cmovna' {CMOV}. - kIdCmovnae, //!< Instruction 'cmovnae' {CMOV}. kIdCmovnb, //!< Instruction 'cmovnb' {CMOV}. kIdCmovnbe, //!< Instruction 'cmovnbe' {CMOV}. - kIdCmovnc, //!< Instruction 'cmovnc' {CMOV}. - kIdCmovne, //!< Instruction 'cmovne' {CMOV}. - kIdCmovng, //!< Instruction 'cmovng' {CMOV}. - kIdCmovnge, //!< Instruction 'cmovnge' {CMOV}. kIdCmovnl, //!< Instruction 'cmovnl' {CMOV}. kIdCmovnle, //!< Instruction 'cmovnle' {CMOV}. kIdCmovno, //!< Instruction 'cmovno' {CMOV}. @@ -229,8 +217,6 @@ namespace Inst { kIdCmovnz, //!< Instruction 'cmovnz' {CMOV}. kIdCmovo, //!< Instruction 'cmovo' {CMOV}. kIdCmovp, //!< Instruction 'cmovp' {CMOV}. - kIdCmovpe, //!< Instruction 'cmovpe' {CMOV}. - kIdCmovpo, //!< Instruction 'cmovpo' {CMOV}. kIdCmovs, //!< Instruction 'cmovs' {CMOV}. kIdCmovz, //!< Instruction 'cmovz' {CMOV}. kIdCmp, //!< Instruction 'cmp'. @@ -435,26 +421,14 @@ namespace Inst { kIdIret, //!< Instruction 'iret'. kIdIretd, //!< Instruction 'iretd'. kIdIretq, //!< Instruction 'iretq' (X64). - kIdJa, //!< Instruction 'ja'. - kIdJae, //!< Instruction 'jae'. kIdJb, //!< Instruction 'jb'. kIdJbe, //!< Instruction 'jbe'. - kIdJc, //!< Instruction 'jc'. - kIdJe, //!< Instruction 'je'. kIdJecxz, //!< Instruction 'jecxz'. - kIdJg, //!< Instruction 'jg'. - kIdJge, //!< Instruction 'jge'. kIdJl, //!< Instruction 'jl'. kIdJle, //!< Instruction 'jle'. kIdJmp, //!< Instruction 'jmp'. - kIdJna, //!< Instruction 'jna'. - kIdJnae, //!< Instruction 'jnae'. kIdJnb, //!< Instruction 'jnb'. kIdJnbe, //!< Instruction 'jnbe'. - kIdJnc, //!< Instruction 'jnc'. - kIdJne, //!< Instruction 'jne'. - kIdJng, //!< Instruction 'jng'. - kIdJnge, //!< Instruction 'jnge'. kIdJnl, //!< Instruction 'jnl'. kIdJnle, //!< Instruction 'jnle'. kIdJno, //!< Instruction 'jno'. @@ -463,8 +437,6 @@ namespace Inst { kIdJnz, //!< Instruction 'jnz'. kIdJo, //!< Instruction 'jo'. kIdJp, //!< Instruction 'jp'. - kIdJpe, //!< Instruction 'jpe'. - kIdJpo, //!< Instruction 'jpo'. kIdJs, //!< Instruction 'js'. kIdJz, //!< Instruction 'jz'. kIdKaddb, //!< Instruction 'kaddb' {AVX512_DQ}. @@ -802,7 +774,7 @@ namespace Inst { kIdRcr, //!< Instruction 'rcr'. kIdRdfsbase, //!< Instruction 'rdfsbase' {FSGSBASE} (X64). kIdRdgsbase, //!< Instruction 'rdgsbase' {FSGSBASE} (X64). - kIdRdmsr, //!< Instruction 'rdmsr' {MSR}. + kIdRdmsr, //!< Instruction 'rdmsr' {MSR|MSR_IMM}. kIdRdpid, //!< Instruction 'rdpid' {RDPID}. kIdRdpkru, //!< Instruction 'rdpkru' {OSPKE}. kIdRdpmc, //!< Instruction 'rdpmc'. @@ -829,7 +801,6 @@ namespace Inst { kIdRsqrtss, //!< Instruction 'rsqrtss' {SSE}. kIdRstorssp, //!< Instruction 'rstorssp' {CET_SS}. kIdSahf, //!< Instruction 'sahf' {LAHFSAHF}. - kIdSal, //!< Instruction 'sal'. kIdSar, //!< Instruction 'sar'. kIdSarx, //!< Instruction 'sarx' {BMI2}. kIdSaveprevssp, //!< Instruction 'saveprevssp' {CET_SS}. @@ -840,24 +811,12 @@ namespace Inst { kIdSeamret, //!< Instruction 'seamret' {SEAM}. kIdSenduipi, //!< Instruction 'senduipi' {UINTR} (X64). kIdSerialize, //!< Instruction 'serialize' {SERIALIZE}. - kIdSeta, //!< Instruction 'seta'. - kIdSetae, //!< Instruction 'setae'. kIdSetb, //!< Instruction 'setb'. kIdSetbe, //!< Instruction 'setbe'. - kIdSetc, //!< Instruction 'setc'. - kIdSete, //!< Instruction 'sete'. - kIdSetg, //!< Instruction 'setg'. - kIdSetge, //!< Instruction 'setge'. kIdSetl, //!< Instruction 'setl'. kIdSetle, //!< Instruction 'setle'. - kIdSetna, //!< Instruction 'setna'. - kIdSetnae, //!< Instruction 'setnae'. kIdSetnb, //!< Instruction 'setnb'. kIdSetnbe, //!< Instruction 'setnbe'. - kIdSetnc, //!< Instruction 'setnc'. - kIdSetne, //!< Instruction 'setne'. - kIdSetng, //!< Instruction 'setng'. - kIdSetnge, //!< Instruction 'setnge'. kIdSetnl, //!< Instruction 'setnl'. kIdSetnle, //!< Instruction 'setnle'. kIdSetno, //!< Instruction 'setno'. @@ -866,8 +825,6 @@ namespace Inst { kIdSetnz, //!< Instruction 'setnz'. kIdSeto, //!< Instruction 'seto'. kIdSetp, //!< Instruction 'setp'. - kIdSetpe, //!< Instruction 'setpe'. - kIdSetpo, //!< Instruction 'setpo'. kIdSets, //!< Instruction 'sets'. kIdSetssbsy, //!< Instruction 'setssbsy' {CET_SS}. kIdSetz, //!< Instruction 'setz'. @@ -952,16 +909,12 @@ namespace Inst { kIdUnpckhps, //!< Instruction 'unpckhps' {SSE}. kIdUnpcklpd, //!< Instruction 'unpcklpd' {SSE2}. kIdUnpcklps, //!< Instruction 'unpcklps' {SSE}. - kIdV4fmaddps, //!< Instruction 'v4fmaddps' {AVX512_4FMAPS}. - kIdV4fmaddss, //!< Instruction 'v4fmaddss' {AVX512_4FMAPS}. - kIdV4fnmaddps, //!< Instruction 'v4fnmaddps' {AVX512_4FMAPS}. - kIdV4fnmaddss, //!< Instruction 'v4fnmaddss' {AVX512_4FMAPS}. kIdVaddpd, //!< Instruction 'vaddpd' {AVX|AVX512_F+VL}. kIdVaddph, //!< Instruction 'vaddph' {AVX512_FP16+VL}. kIdVaddps, //!< Instruction 'vaddps' {AVX|AVX512_F+VL}. - kIdVaddsd, //!< Instruction 'vaddsd' {AVX|AVX512_F}. - kIdVaddsh, //!< Instruction 'vaddsh' {AVX512_FP16}. - kIdVaddss, //!< Instruction 'vaddss' {AVX|AVX512_F}. + kIdVaddsd, //!< Instruction 'vaddsd' {AVX|AVX512_F+VL}. + kIdVaddsh, //!< Instruction 'vaddsh' {AVX512_FP16+VL}. + kIdVaddss, //!< Instruction 'vaddss' {AVX|AVX512_F+VL}. kIdVaddsubpd, //!< Instruction 'vaddsubpd' {AVX}. kIdVaddsubps, //!< Instruction 'vaddsubps' {AVX}. kIdVaesdec, //!< Instruction 'vaesdec' {AVX|AVX512_F+VL & AESNI|VAES}. @@ -986,27 +939,27 @@ namespace Inst { kIdVblendvps, //!< Instruction 'vblendvps' {AVX}. kIdVbroadcastf128, //!< Instruction 'vbroadcastf128' {AVX}. kIdVbroadcastf32x2, //!< Instruction 'vbroadcastf32x2' {AVX512_DQ+VL}. - kIdVbroadcastf32x4, //!< Instruction 'vbroadcastf32x4' {AVX512_F}. - kIdVbroadcastf32x8, //!< Instruction 'vbroadcastf32x8' {AVX512_DQ}. + kIdVbroadcastf32x4, //!< Instruction 'vbroadcastf32x4' {AVX512_F+VL}. + kIdVbroadcastf32x8, //!< Instruction 'vbroadcastf32x8' {AVX512_DQ+VL}. kIdVbroadcastf64x2, //!< Instruction 'vbroadcastf64x2' {AVX512_DQ+VL}. - kIdVbroadcastf64x4, //!< Instruction 'vbroadcastf64x4' {AVX512_F}. + kIdVbroadcastf64x4, //!< Instruction 'vbroadcastf64x4' {AVX512_F+VL}. kIdVbroadcasti128, //!< Instruction 'vbroadcasti128' {AVX2}. kIdVbroadcasti32x2, //!< Instruction 'vbroadcasti32x2' {AVX512_DQ+VL}. kIdVbroadcasti32x4, //!< Instruction 'vbroadcasti32x4' {AVX512_F+VL}. - kIdVbroadcasti32x8, //!< Instruction 'vbroadcasti32x8' {AVX512_DQ}. + kIdVbroadcasti32x8, //!< Instruction 'vbroadcasti32x8' {AVX512_DQ+VL}. kIdVbroadcasti64x2, //!< Instruction 'vbroadcasti64x2' {AVX512_DQ+VL}. - kIdVbroadcasti64x4, //!< Instruction 'vbroadcasti64x4' {AVX512_F}. + kIdVbroadcasti64x4, //!< Instruction 'vbroadcasti64x4' {AVX512_F+VL}. kIdVbroadcastsd, //!< Instruction 'vbroadcastsd' {AVX|AVX2|AVX512_F+VL}. kIdVbroadcastss, //!< Instruction 'vbroadcastss' {AVX|AVX2|AVX512_F+VL}. kIdVcmppd, //!< Instruction 'vcmppd' {AVX|AVX512_F+VL}. kIdVcmpph, //!< Instruction 'vcmpph' {AVX512_FP16+VL}. kIdVcmpps, //!< Instruction 'vcmpps' {AVX|AVX512_F+VL}. - kIdVcmpsd, //!< Instruction 'vcmpsd' {AVX|AVX512_F}. - kIdVcmpsh, //!< Instruction 'vcmpsh' {AVX512_FP16}. - kIdVcmpss, //!< Instruction 'vcmpss' {AVX|AVX512_F}. - kIdVcomisd, //!< Instruction 'vcomisd' {AVX|AVX512_F}. - kIdVcomish, //!< Instruction 'vcomish' {AVX512_FP16}. - kIdVcomiss, //!< Instruction 'vcomiss' {AVX|AVX512_F}. + kIdVcmpsd, //!< Instruction 'vcmpsd' {AVX|AVX512_F+VL}. + kIdVcmpsh, //!< Instruction 'vcmpsh' {AVX512_FP16+VL}. + kIdVcmpss, //!< Instruction 'vcmpss' {AVX|AVX512_F+VL}. + kIdVcomisd, //!< Instruction 'vcomisd' {AVX|AVX512_F+VL}. + kIdVcomish, //!< Instruction 'vcomish' {AVX512_FP16+VL}. + kIdVcomiss, //!< Instruction 'vcomiss' {AVX|AVX512_F+VL}. kIdVcompresspd, //!< Instruction 'vcompresspd' {AVX512_F+VL}. kIdVcompressps, //!< Instruction 'vcompressps' {AVX512_F+VL}. kIdVcvtdq2pd, //!< Instruction 'vcvtdq2pd' {AVX|AVX512_F+VL}. @@ -1043,21 +996,21 @@ namespace Inst { kIdVcvtqq2pd, //!< Instruction 'vcvtqq2pd' {AVX512_DQ+VL}. kIdVcvtqq2ph, //!< Instruction 'vcvtqq2ph' {AVX512_FP16+VL}. kIdVcvtqq2ps, //!< Instruction 'vcvtqq2ps' {AVX512_DQ+VL}. - kIdVcvtsd2sh, //!< Instruction 'vcvtsd2sh' {AVX512_FP16}. - kIdVcvtsd2si, //!< Instruction 'vcvtsd2si' {AVX|AVX512_F}. - kIdVcvtsd2ss, //!< Instruction 'vcvtsd2ss' {AVX|AVX512_F}. - kIdVcvtsd2usi, //!< Instruction 'vcvtsd2usi' {AVX512_F}. - kIdVcvtsh2sd, //!< Instruction 'vcvtsh2sd' {AVX512_FP16}. - kIdVcvtsh2si, //!< Instruction 'vcvtsh2si' {AVX512_FP16}. - kIdVcvtsh2ss, //!< Instruction 'vcvtsh2ss' {AVX512_FP16}. - kIdVcvtsh2usi, //!< Instruction 'vcvtsh2usi' {AVX512_FP16}. - kIdVcvtsi2sd, //!< Instruction 'vcvtsi2sd' {AVX|AVX512_F}. - kIdVcvtsi2sh, //!< Instruction 'vcvtsi2sh' {AVX512_FP16}. - kIdVcvtsi2ss, //!< Instruction 'vcvtsi2ss' {AVX|AVX512_F}. - kIdVcvtss2sd, //!< Instruction 'vcvtss2sd' {AVX|AVX512_F}. - kIdVcvtss2sh, //!< Instruction 'vcvtss2sh' {AVX512_FP16}. - kIdVcvtss2si, //!< Instruction 'vcvtss2si' {AVX|AVX512_F}. - kIdVcvtss2usi, //!< Instruction 'vcvtss2usi' {AVX512_F}. + kIdVcvtsd2sh, //!< Instruction 'vcvtsd2sh' {AVX512_FP16+VL}. + kIdVcvtsd2si, //!< Instruction 'vcvtsd2si' {AVX|AVX512_F+VL}. + kIdVcvtsd2ss, //!< Instruction 'vcvtsd2ss' {AVX|AVX512_F+VL}. + kIdVcvtsd2usi, //!< Instruction 'vcvtsd2usi' {AVX512_F+VL}. + kIdVcvtsh2sd, //!< Instruction 'vcvtsh2sd' {AVX512_FP16+VL}. + kIdVcvtsh2si, //!< Instruction 'vcvtsh2si' {AVX512_FP16+VL}. + kIdVcvtsh2ss, //!< Instruction 'vcvtsh2ss' {AVX512_FP16+VL}. + kIdVcvtsh2usi, //!< Instruction 'vcvtsh2usi' {AVX512_FP16+VL}. + kIdVcvtsi2sd, //!< Instruction 'vcvtsi2sd' {AVX|AVX512_F+VL}. + kIdVcvtsi2sh, //!< Instruction 'vcvtsi2sh' {AVX512_FP16+VL}. + kIdVcvtsi2ss, //!< Instruction 'vcvtsi2ss' {AVX|AVX512_F+VL}. + kIdVcvtss2sd, //!< Instruction 'vcvtss2sd' {AVX|AVX512_F+VL}. + kIdVcvtss2sh, //!< Instruction 'vcvtss2sh' {AVX512_FP16+VL}. + kIdVcvtss2si, //!< Instruction 'vcvtss2si' {AVX|AVX512_F+VL}. + kIdVcvtss2usi, //!< Instruction 'vcvtss2usi' {AVX512_F+VL}. kIdVcvttpd2dq, //!< Instruction 'vcvttpd2dq' {AVX|AVX512_F+VL}. kIdVcvttpd2qq, //!< Instruction 'vcvttpd2qq' {AVX512_F+VL}. kIdVcvttpd2udq, //!< Instruction 'vcvttpd2udq' {AVX512_F+VL}. @@ -1072,78 +1025,76 @@ namespace Inst { kIdVcvttps2qq, //!< Instruction 'vcvttps2qq' {AVX512_DQ+VL}. kIdVcvttps2udq, //!< Instruction 'vcvttps2udq' {AVX512_F+VL}. kIdVcvttps2uqq, //!< Instruction 'vcvttps2uqq' {AVX512_DQ+VL}. - kIdVcvttsd2si, //!< Instruction 'vcvttsd2si' {AVX|AVX512_F}. - kIdVcvttsd2usi, //!< Instruction 'vcvttsd2usi' {AVX512_F}. - kIdVcvttsh2si, //!< Instruction 'vcvttsh2si' {AVX512_FP16}. - kIdVcvttsh2usi, //!< Instruction 'vcvttsh2usi' {AVX512_FP16}. - kIdVcvttss2si, //!< Instruction 'vcvttss2si' {AVX|AVX512_F}. - kIdVcvttss2usi, //!< Instruction 'vcvttss2usi' {AVX512_F}. + kIdVcvttsd2si, //!< Instruction 'vcvttsd2si' {AVX|AVX512_F+VL}. + kIdVcvttsd2usi, //!< Instruction 'vcvttsd2usi' {AVX512_F+VL}. + kIdVcvttsh2si, //!< Instruction 'vcvttsh2si' {AVX512_FP16+VL}. + kIdVcvttsh2usi, //!< Instruction 'vcvttsh2usi' {AVX512_FP16+VL}. + kIdVcvttss2si, //!< Instruction 'vcvttss2si' {AVX|AVX512_F+VL}. + kIdVcvttss2usi, //!< Instruction 'vcvttss2usi' {AVX512_F+VL}. kIdVcvtudq2pd, //!< Instruction 'vcvtudq2pd' {AVX512_F+VL}. kIdVcvtudq2ph, //!< Instruction 'vcvtudq2ph' {AVX512_FP16+VL}. kIdVcvtudq2ps, //!< Instruction 'vcvtudq2ps' {AVX512_F+VL}. kIdVcvtuqq2pd, //!< Instruction 'vcvtuqq2pd' {AVX512_DQ+VL}. kIdVcvtuqq2ph, //!< Instruction 'vcvtuqq2ph' {AVX512_FP16+VL}. kIdVcvtuqq2ps, //!< Instruction 'vcvtuqq2ps' {AVX512_DQ+VL}. - kIdVcvtusi2sd, //!< Instruction 'vcvtusi2sd' {AVX512_F}. - kIdVcvtusi2sh, //!< Instruction 'vcvtusi2sh' {AVX512_FP16}. - kIdVcvtusi2ss, //!< Instruction 'vcvtusi2ss' {AVX512_F}. + kIdVcvtusi2sd, //!< Instruction 'vcvtusi2sd' {AVX512_F+VL}. + kIdVcvtusi2sh, //!< Instruction 'vcvtusi2sh' {AVX512_FP16+VL}. + kIdVcvtusi2ss, //!< Instruction 'vcvtusi2ss' {AVX512_F+VL}. kIdVcvtuw2ph, //!< Instruction 'vcvtuw2ph' {AVX512_FP16+VL}. kIdVcvtw2ph, //!< Instruction 'vcvtw2ph' {AVX512_FP16+VL}. kIdVdbpsadbw, //!< Instruction 'vdbpsadbw' {AVX512_BW+VL}. kIdVdivpd, //!< Instruction 'vdivpd' {AVX|AVX512_F+VL}. kIdVdivph, //!< Instruction 'vdivph' {AVX512_FP16+VL}. kIdVdivps, //!< Instruction 'vdivps' {AVX|AVX512_F+VL}. - kIdVdivsd, //!< Instruction 'vdivsd' {AVX|AVX512_F}. - kIdVdivsh, //!< Instruction 'vdivsh' {AVX512_FP16}. - kIdVdivss, //!< Instruction 'vdivss' {AVX|AVX512_F}. + kIdVdivsd, //!< Instruction 'vdivsd' {AVX|AVX512_F+VL}. + kIdVdivsh, //!< Instruction 'vdivsh' {AVX512_FP16+VL}. + kIdVdivss, //!< Instruction 'vdivss' {AVX|AVX512_F+VL}. kIdVdpbf16ps, //!< Instruction 'vdpbf16ps' {AVX512_BF16+VL}. kIdVdppd, //!< Instruction 'vdppd' {AVX}. kIdVdpps, //!< Instruction 'vdpps' {AVX}. kIdVerr, //!< Instruction 'verr'. kIdVerw, //!< Instruction 'verw'. - kIdVexp2pd, //!< Instruction 'vexp2pd' {AVX512_ER}. - kIdVexp2ps, //!< Instruction 'vexp2ps' {AVX512_ER}. kIdVexpandpd, //!< Instruction 'vexpandpd' {AVX512_F+VL}. kIdVexpandps, //!< Instruction 'vexpandps' {AVX512_F+VL}. kIdVextractf128, //!< Instruction 'vextractf128' {AVX}. kIdVextractf32x4, //!< Instruction 'vextractf32x4' {AVX512_F+VL}. - kIdVextractf32x8, //!< Instruction 'vextractf32x8' {AVX512_DQ}. + kIdVextractf32x8, //!< Instruction 'vextractf32x8' {AVX512_DQ+VL}. kIdVextractf64x2, //!< Instruction 'vextractf64x2' {AVX512_DQ+VL}. - kIdVextractf64x4, //!< Instruction 'vextractf64x4' {AVX512_F}. + kIdVextractf64x4, //!< Instruction 'vextractf64x4' {AVX512_F+VL}. kIdVextracti128, //!< Instruction 'vextracti128' {AVX2}. kIdVextracti32x4, //!< Instruction 'vextracti32x4' {AVX512_F+VL}. - kIdVextracti32x8, //!< Instruction 'vextracti32x8' {AVX512_DQ}. + kIdVextracti32x8, //!< Instruction 'vextracti32x8' {AVX512_DQ+VL}. kIdVextracti64x2, //!< Instruction 'vextracti64x2' {AVX512_DQ+VL}. - kIdVextracti64x4, //!< Instruction 'vextracti64x4' {AVX512_F}. - kIdVextractps, //!< Instruction 'vextractps' {AVX|AVX512_F}. + kIdVextracti64x4, //!< Instruction 'vextracti64x4' {AVX512_F+VL}. + kIdVextractps, //!< Instruction 'vextractps' {AVX|AVX512_F+VL}. kIdVfcmaddcph, //!< Instruction 'vfcmaddcph' {AVX512_FP16+VL}. - kIdVfcmaddcsh, //!< Instruction 'vfcmaddcsh' {AVX512_FP16}. + kIdVfcmaddcsh, //!< Instruction 'vfcmaddcsh' {AVX512_FP16+VL}. kIdVfcmulcph, //!< Instruction 'vfcmulcph' {AVX512_FP16+VL}. - kIdVfcmulcsh, //!< Instruction 'vfcmulcsh' {AVX512_FP16}. + kIdVfcmulcsh, //!< Instruction 'vfcmulcsh' {AVX512_FP16+VL}. kIdVfixupimmpd, //!< Instruction 'vfixupimmpd' {AVX512_F+VL}. kIdVfixupimmps, //!< Instruction 'vfixupimmps' {AVX512_F+VL}. - kIdVfixupimmsd, //!< Instruction 'vfixupimmsd' {AVX512_F}. - kIdVfixupimmss, //!< Instruction 'vfixupimmss' {AVX512_F}. + kIdVfixupimmsd, //!< Instruction 'vfixupimmsd' {AVX512_F+VL}. + kIdVfixupimmss, //!< Instruction 'vfixupimmss' {AVX512_F+VL}. kIdVfmadd132pd, //!< Instruction 'vfmadd132pd' {FMA|AVX512_F+VL}. kIdVfmadd132ph, //!< Instruction 'vfmadd132ph' {AVX512_FP16+VL}. kIdVfmadd132ps, //!< Instruction 'vfmadd132ps' {FMA|AVX512_F+VL}. - kIdVfmadd132sd, //!< Instruction 'vfmadd132sd' {FMA|AVX512_F}. - kIdVfmadd132sh, //!< Instruction 'vfmadd132sh' {AVX512_FP16}. - kIdVfmadd132ss, //!< Instruction 'vfmadd132ss' {FMA|AVX512_F}. + kIdVfmadd132sd, //!< Instruction 'vfmadd132sd' {FMA|AVX512_F+VL}. + kIdVfmadd132sh, //!< Instruction 'vfmadd132sh' {AVX512_FP16+VL}. + kIdVfmadd132ss, //!< Instruction 'vfmadd132ss' {FMA|AVX512_F+VL}. kIdVfmadd213pd, //!< Instruction 'vfmadd213pd' {FMA|AVX512_F+VL}. kIdVfmadd213ph, //!< Instruction 'vfmadd213ph' {AVX512_FP16+VL}. kIdVfmadd213ps, //!< Instruction 'vfmadd213ps' {FMA|AVX512_F+VL}. - kIdVfmadd213sd, //!< Instruction 'vfmadd213sd' {FMA|AVX512_F}. - kIdVfmadd213sh, //!< Instruction 'vfmadd213sh' {AVX512_FP16}. - kIdVfmadd213ss, //!< Instruction 'vfmadd213ss' {FMA|AVX512_F}. + kIdVfmadd213sd, //!< Instruction 'vfmadd213sd' {FMA|AVX512_F+VL}. + kIdVfmadd213sh, //!< Instruction 'vfmadd213sh' {AVX512_FP16+VL}. + kIdVfmadd213ss, //!< Instruction 'vfmadd213ss' {FMA|AVX512_F+VL}. kIdVfmadd231pd, //!< Instruction 'vfmadd231pd' {FMA|AVX512_F+VL}. kIdVfmadd231ph, //!< Instruction 'vfmadd231ph' {AVX512_FP16+VL}. kIdVfmadd231ps, //!< Instruction 'vfmadd231ps' {FMA|AVX512_F+VL}. - kIdVfmadd231sd, //!< Instruction 'vfmadd231sd' {FMA|AVX512_F}. - kIdVfmadd231sh, //!< Instruction 'vfmadd231sh' {AVX512_FP16}. - kIdVfmadd231ss, //!< Instruction 'vfmadd231ss' {FMA|AVX512_F}. + kIdVfmadd231sd, //!< Instruction 'vfmadd231sd' {FMA|AVX512_F+VL}. + kIdVfmadd231sh, //!< Instruction 'vfmadd231sh' {AVX512_FP16+VL}. + kIdVfmadd231ss, //!< Instruction 'vfmadd231ss' {FMA|AVX512_F+VL}. kIdVfmaddcph, //!< Instruction 'vfmaddcph' {AVX512_FP16+VL}. - kIdVfmaddcsh, //!< Instruction 'vfmaddcsh' {AVX512_FP16}. + kIdVfmaddcsh, //!< Instruction 'vfmaddcsh' {AVX512_FP16+VL}. kIdVfmaddpd, //!< Instruction 'vfmaddpd' {FMA4}. kIdVfmaddps, //!< Instruction 'vfmaddps' {FMA4}. kIdVfmaddsd, //!< Instruction 'vfmaddsd' {FMA4}. @@ -1162,21 +1113,21 @@ namespace Inst { kIdVfmsub132pd, //!< Instruction 'vfmsub132pd' {FMA|AVX512_F+VL}. kIdVfmsub132ph, //!< Instruction 'vfmsub132ph' {AVX512_FP16+VL}. kIdVfmsub132ps, //!< Instruction 'vfmsub132ps' {FMA|AVX512_F+VL}. - kIdVfmsub132sd, //!< Instruction 'vfmsub132sd' {FMA|AVX512_F}. - kIdVfmsub132sh, //!< Instruction 'vfmsub132sh' {AVX512_FP16}. - kIdVfmsub132ss, //!< Instruction 'vfmsub132ss' {FMA|AVX512_F}. + kIdVfmsub132sd, //!< Instruction 'vfmsub132sd' {FMA|AVX512_F+VL}. + kIdVfmsub132sh, //!< Instruction 'vfmsub132sh' {AVX512_FP16+VL}. + kIdVfmsub132ss, //!< Instruction 'vfmsub132ss' {FMA|AVX512_F+VL}. kIdVfmsub213pd, //!< Instruction 'vfmsub213pd' {FMA|AVX512_F+VL}. kIdVfmsub213ph, //!< Instruction 'vfmsub213ph' {AVX512_FP16+VL}. kIdVfmsub213ps, //!< Instruction 'vfmsub213ps' {FMA|AVX512_F+VL}. - kIdVfmsub213sd, //!< Instruction 'vfmsub213sd' {FMA|AVX512_F}. - kIdVfmsub213sh, //!< Instruction 'vfmsub213sh' {AVX512_FP16}. - kIdVfmsub213ss, //!< Instruction 'vfmsub213ss' {FMA|AVX512_F}. + kIdVfmsub213sd, //!< Instruction 'vfmsub213sd' {FMA|AVX512_F+VL}. + kIdVfmsub213sh, //!< Instruction 'vfmsub213sh' {AVX512_FP16+VL}. + kIdVfmsub213ss, //!< Instruction 'vfmsub213ss' {FMA|AVX512_F+VL}. kIdVfmsub231pd, //!< Instruction 'vfmsub231pd' {FMA|AVX512_F+VL}. kIdVfmsub231ph, //!< Instruction 'vfmsub231ph' {AVX512_FP16+VL}. kIdVfmsub231ps, //!< Instruction 'vfmsub231ps' {FMA|AVX512_F+VL}. - kIdVfmsub231sd, //!< Instruction 'vfmsub231sd' {FMA|AVX512_F}. - kIdVfmsub231sh, //!< Instruction 'vfmsub231sh' {AVX512_FP16}. - kIdVfmsub231ss, //!< Instruction 'vfmsub231ss' {FMA|AVX512_F}. + kIdVfmsub231sd, //!< Instruction 'vfmsub231sd' {FMA|AVX512_F+VL}. + kIdVfmsub231sh, //!< Instruction 'vfmsub231sh' {AVX512_FP16+VL}. + kIdVfmsub231ss, //!< Instruction 'vfmsub231ss' {FMA|AVX512_F+VL}. kIdVfmsubadd132pd, //!< Instruction 'vfmsubadd132pd' {FMA|AVX512_F+VL}. kIdVfmsubadd132ph, //!< Instruction 'vfmsubadd132ph' {AVX512_FP16+VL}. kIdVfmsubadd132ps, //!< Instruction 'vfmsubadd132ps' {FMA|AVX512_F+VL}. @@ -1197,21 +1148,21 @@ namespace Inst { kIdVfnmadd132pd, //!< Instruction 'vfnmadd132pd' {FMA|AVX512_F+VL}. kIdVfnmadd132ph, //!< Instruction 'vfnmadd132ph' {AVX512_FP16+VL}. kIdVfnmadd132ps, //!< Instruction 'vfnmadd132ps' {FMA|AVX512_F+VL}. - kIdVfnmadd132sd, //!< Instruction 'vfnmadd132sd' {FMA|AVX512_F}. - kIdVfnmadd132sh, //!< Instruction 'vfnmadd132sh' {AVX512_FP16}. - kIdVfnmadd132ss, //!< Instruction 'vfnmadd132ss' {FMA|AVX512_F}. + kIdVfnmadd132sd, //!< Instruction 'vfnmadd132sd' {FMA|AVX512_F+VL}. + kIdVfnmadd132sh, //!< Instruction 'vfnmadd132sh' {AVX512_FP16+VL}. + kIdVfnmadd132ss, //!< Instruction 'vfnmadd132ss' {FMA|AVX512_F+VL}. kIdVfnmadd213pd, //!< Instruction 'vfnmadd213pd' {FMA|AVX512_F+VL}. kIdVfnmadd213ph, //!< Instruction 'vfnmadd213ph' {AVX512_FP16+VL}. kIdVfnmadd213ps, //!< Instruction 'vfnmadd213ps' {FMA|AVX512_F+VL}. - kIdVfnmadd213sd, //!< Instruction 'vfnmadd213sd' {FMA|AVX512_F}. - kIdVfnmadd213sh, //!< Instruction 'vfnmadd213sh' {AVX512_FP16}. - kIdVfnmadd213ss, //!< Instruction 'vfnmadd213ss' {FMA|AVX512_F}. + kIdVfnmadd213sd, //!< Instruction 'vfnmadd213sd' {FMA|AVX512_F+VL}. + kIdVfnmadd213sh, //!< Instruction 'vfnmadd213sh' {AVX512_FP16+VL}. + kIdVfnmadd213ss, //!< Instruction 'vfnmadd213ss' {FMA|AVX512_F+VL}. kIdVfnmadd231pd, //!< Instruction 'vfnmadd231pd' {FMA|AVX512_F+VL}. kIdVfnmadd231ph, //!< Instruction 'vfnmadd231ph' {AVX512_FP16+VL}. kIdVfnmadd231ps, //!< Instruction 'vfnmadd231ps' {FMA|AVX512_F+VL}. - kIdVfnmadd231sd, //!< Instruction 'vfnmadd231sd' {FMA|AVX512_F}. - kIdVfnmadd231sh, //!< Instruction 'vfnmadd231sh' {AVX512_FP16}. - kIdVfnmadd231ss, //!< Instruction 'vfnmadd231ss' {FMA|AVX512_F}. + kIdVfnmadd231sd, //!< Instruction 'vfnmadd231sd' {FMA|AVX512_F+VL}. + kIdVfnmadd231sh, //!< Instruction 'vfnmadd231sh' {AVX512_FP16+VL}. + kIdVfnmadd231ss, //!< Instruction 'vfnmadd231ss' {FMA|AVX512_F+VL}. kIdVfnmaddpd, //!< Instruction 'vfnmaddpd' {FMA4}. kIdVfnmaddps, //!< Instruction 'vfnmaddps' {FMA4}. kIdVfnmaddsd, //!< Instruction 'vfnmaddsd' {FMA4}. @@ -1219,21 +1170,21 @@ namespace Inst { kIdVfnmsub132pd, //!< Instruction 'vfnmsub132pd' {FMA|AVX512_F+VL}. kIdVfnmsub132ph, //!< Instruction 'vfnmsub132ph' {AVX512_FP16+VL}. kIdVfnmsub132ps, //!< Instruction 'vfnmsub132ps' {FMA|AVX512_F+VL}. - kIdVfnmsub132sd, //!< Instruction 'vfnmsub132sd' {FMA|AVX512_F}. - kIdVfnmsub132sh, //!< Instruction 'vfnmsub132sh' {AVX512_FP16}. - kIdVfnmsub132ss, //!< Instruction 'vfnmsub132ss' {FMA|AVX512_F}. + kIdVfnmsub132sd, //!< Instruction 'vfnmsub132sd' {FMA|AVX512_F+VL}. + kIdVfnmsub132sh, //!< Instruction 'vfnmsub132sh' {AVX512_FP16+VL}. + kIdVfnmsub132ss, //!< Instruction 'vfnmsub132ss' {FMA|AVX512_F+VL}. kIdVfnmsub213pd, //!< Instruction 'vfnmsub213pd' {FMA|AVX512_F+VL}. kIdVfnmsub213ph, //!< Instruction 'vfnmsub213ph' {AVX512_FP16+VL}. kIdVfnmsub213ps, //!< Instruction 'vfnmsub213ps' {FMA|AVX512_F+VL}. - kIdVfnmsub213sd, //!< Instruction 'vfnmsub213sd' {FMA|AVX512_F}. - kIdVfnmsub213sh, //!< Instruction 'vfnmsub213sh' {AVX512_FP16}. - kIdVfnmsub213ss, //!< Instruction 'vfnmsub213ss' {FMA|AVX512_F}. + kIdVfnmsub213sd, //!< Instruction 'vfnmsub213sd' {FMA|AVX512_F+VL}. + kIdVfnmsub213sh, //!< Instruction 'vfnmsub213sh' {AVX512_FP16+VL}. + kIdVfnmsub213ss, //!< Instruction 'vfnmsub213ss' {FMA|AVX512_F+VL}. kIdVfnmsub231pd, //!< Instruction 'vfnmsub231pd' {FMA|AVX512_F+VL}. kIdVfnmsub231ph, //!< Instruction 'vfnmsub231ph' {AVX512_FP16+VL}. kIdVfnmsub231ps, //!< Instruction 'vfnmsub231ps' {FMA|AVX512_F+VL}. - kIdVfnmsub231sd, //!< Instruction 'vfnmsub231sd' {FMA|AVX512_F}. - kIdVfnmsub231sh, //!< Instruction 'vfnmsub231sh' {AVX512_FP16}. - kIdVfnmsub231ss, //!< Instruction 'vfnmsub231ss' {FMA|AVX512_F}. + kIdVfnmsub231sd, //!< Instruction 'vfnmsub231sd' {FMA|AVX512_F+VL}. + kIdVfnmsub231sh, //!< Instruction 'vfnmsub231sh' {AVX512_FP16+VL}. + kIdVfnmsub231ss, //!< Instruction 'vfnmsub231ss' {FMA|AVX512_F+VL}. kIdVfnmsubpd, //!< Instruction 'vfnmsubpd' {FMA4}. kIdVfnmsubps, //!< Instruction 'vfnmsubps' {FMA4}. kIdVfnmsubsd, //!< Instruction 'vfnmsubsd' {FMA4}. @@ -1241,37 +1192,29 @@ namespace Inst { kIdVfpclasspd, //!< Instruction 'vfpclasspd' {AVX512_DQ+VL}. kIdVfpclassph, //!< Instruction 'vfpclassph' {AVX512_FP16+VL}. kIdVfpclassps, //!< Instruction 'vfpclassps' {AVX512_DQ+VL}. - kIdVfpclasssd, //!< Instruction 'vfpclasssd' {AVX512_DQ}. - kIdVfpclasssh, //!< Instruction 'vfpclasssh' {AVX512_FP16}. - kIdVfpclassss, //!< Instruction 'vfpclassss' {AVX512_DQ}. + kIdVfpclasssd, //!< Instruction 'vfpclasssd' {AVX512_DQ+VL}. + kIdVfpclasssh, //!< Instruction 'vfpclasssh' {AVX512_FP16+VL}. + kIdVfpclassss, //!< Instruction 'vfpclassss' {AVX512_DQ+VL}. kIdVfrczpd, //!< Instruction 'vfrczpd' {XOP}. kIdVfrczps, //!< Instruction 'vfrczps' {XOP}. kIdVfrczsd, //!< Instruction 'vfrczsd' {XOP}. kIdVfrczss, //!< Instruction 'vfrczss' {XOP}. kIdVgatherdpd, //!< Instruction 'vgatherdpd' {AVX2|AVX512_F+VL}. kIdVgatherdps, //!< Instruction 'vgatherdps' {AVX2|AVX512_F+VL}. - kIdVgatherpf0dpd, //!< Instruction 'vgatherpf0dpd' {AVX512_PF}. - kIdVgatherpf0dps, //!< Instruction 'vgatherpf0dps' {AVX512_PF}. - kIdVgatherpf0qpd, //!< Instruction 'vgatherpf0qpd' {AVX512_PF}. - kIdVgatherpf0qps, //!< Instruction 'vgatherpf0qps' {AVX512_PF}. - kIdVgatherpf1dpd, //!< Instruction 'vgatherpf1dpd' {AVX512_PF}. - kIdVgatherpf1dps, //!< Instruction 'vgatherpf1dps' {AVX512_PF}. - kIdVgatherpf1qpd, //!< Instruction 'vgatherpf1qpd' {AVX512_PF}. - kIdVgatherpf1qps, //!< Instruction 'vgatherpf1qps' {AVX512_PF}. kIdVgatherqpd, //!< Instruction 'vgatherqpd' {AVX2|AVX512_F+VL}. kIdVgatherqps, //!< Instruction 'vgatherqps' {AVX2|AVX512_F+VL}. kIdVgetexppd, //!< Instruction 'vgetexppd' {AVX512_F+VL}. kIdVgetexpph, //!< Instruction 'vgetexpph' {AVX512_FP16+VL}. kIdVgetexpps, //!< Instruction 'vgetexpps' {AVX512_F+VL}. - kIdVgetexpsd, //!< Instruction 'vgetexpsd' {AVX512_F}. - kIdVgetexpsh, //!< Instruction 'vgetexpsh' {AVX512_FP16}. - kIdVgetexpss, //!< Instruction 'vgetexpss' {AVX512_F}. + kIdVgetexpsd, //!< Instruction 'vgetexpsd' {AVX512_F+VL}. + kIdVgetexpsh, //!< Instruction 'vgetexpsh' {AVX512_FP16+VL}. + kIdVgetexpss, //!< Instruction 'vgetexpss' {AVX512_F+VL}. kIdVgetmantpd, //!< Instruction 'vgetmantpd' {AVX512_F+VL}. kIdVgetmantph, //!< Instruction 'vgetmantph' {AVX512_FP16+VL}. kIdVgetmantps, //!< Instruction 'vgetmantps' {AVX512_F+VL}. - kIdVgetmantsd, //!< Instruction 'vgetmantsd' {AVX512_F}. - kIdVgetmantsh, //!< Instruction 'vgetmantsh' {AVX512_FP16}. - kIdVgetmantss, //!< Instruction 'vgetmantss' {AVX512_F}. + kIdVgetmantsd, //!< Instruction 'vgetmantsd' {AVX512_F+VL}. + kIdVgetmantsh, //!< Instruction 'vgetmantsh' {AVX512_FP16+VL}. + kIdVgetmantss, //!< Instruction 'vgetmantss' {AVX512_F+VL}. kIdVgf2p8affineinvqb, //!< Instruction 'vgf2p8affineinvqb' {AVX|AVX512_F+VL & GFNI}. kIdVgf2p8affineqb, //!< Instruction 'vgf2p8affineqb' {AVX|AVX512_F+VL & GFNI}. kIdVgf2p8mulb, //!< Instruction 'vgf2p8mulb' {AVX|AVX512_F+VL & GFNI}. @@ -1281,15 +1224,15 @@ namespace Inst { kIdVhsubps, //!< Instruction 'vhsubps' {AVX}. kIdVinsertf128, //!< Instruction 'vinsertf128' {AVX}. kIdVinsertf32x4, //!< Instruction 'vinsertf32x4' {AVX512_F+VL}. - kIdVinsertf32x8, //!< Instruction 'vinsertf32x8' {AVX512_DQ}. + kIdVinsertf32x8, //!< Instruction 'vinsertf32x8' {AVX512_DQ+VL}. kIdVinsertf64x2, //!< Instruction 'vinsertf64x2' {AVX512_DQ+VL}. - kIdVinsertf64x4, //!< Instruction 'vinsertf64x4' {AVX512_F}. + kIdVinsertf64x4, //!< Instruction 'vinsertf64x4' {AVX512_F+VL}. kIdVinserti128, //!< Instruction 'vinserti128' {AVX2}. kIdVinserti32x4, //!< Instruction 'vinserti32x4' {AVX512_F+VL}. - kIdVinserti32x8, //!< Instruction 'vinserti32x8' {AVX512_DQ}. + kIdVinserti32x8, //!< Instruction 'vinserti32x8' {AVX512_DQ+VL}. kIdVinserti64x2, //!< Instruction 'vinserti64x2' {AVX512_DQ+VL}. - kIdVinserti64x4, //!< Instruction 'vinserti64x4' {AVX512_F}. - kIdVinsertps, //!< Instruction 'vinsertps' {AVX|AVX512_F}. + kIdVinserti64x4, //!< Instruction 'vinserti64x4' {AVX512_F+VL}. + kIdVinsertps, //!< Instruction 'vinsertps' {AVX|AVX512_F+VL}. kIdVlddqu, //!< Instruction 'vlddqu' {AVX}. kIdVldmxcsr, //!< Instruction 'vldmxcsr' {AVX}. kIdVmaskmovdqu, //!< Instruction 'vmaskmovdqu' {AVX}. @@ -1298,9 +1241,9 @@ namespace Inst { kIdVmaxpd, //!< Instruction 'vmaxpd' {AVX|AVX512_F+VL}. kIdVmaxph, //!< Instruction 'vmaxph' {AVX512_FP16+VL}. kIdVmaxps, //!< Instruction 'vmaxps' {AVX|AVX512_F+VL}. - kIdVmaxsd, //!< Instruction 'vmaxsd' {AVX|AVX512_F}. - kIdVmaxsh, //!< Instruction 'vmaxsh' {AVX512_FP16}. - kIdVmaxss, //!< Instruction 'vmaxss' {AVX|AVX512_F}. + kIdVmaxsd, //!< Instruction 'vmaxsd' {AVX|AVX512_F+VL}. + kIdVmaxsh, //!< Instruction 'vmaxsh' {AVX512_FP16+VL}. + kIdVmaxss, //!< Instruction 'vmaxss' {AVX|AVX512_F+VL}. kIdVmcall, //!< Instruction 'vmcall' {VMX}. kIdVmclear, //!< Instruction 'vmclear' {VMX}. kIdVmfunc, //!< Instruction 'vmfunc' {VMX}. @@ -1308,15 +1251,15 @@ namespace Inst { kIdVminpd, //!< Instruction 'vminpd' {AVX|AVX512_F+VL}. kIdVminph, //!< Instruction 'vminph' {AVX512_FP16+VL}. kIdVminps, //!< Instruction 'vminps' {AVX|AVX512_F+VL}. - kIdVminsd, //!< Instruction 'vminsd' {AVX|AVX512_F}. - kIdVminsh, //!< Instruction 'vminsh' {AVX512_FP16}. - kIdVminss, //!< Instruction 'vminss' {AVX|AVX512_F}. + kIdVminsd, //!< Instruction 'vminsd' {AVX|AVX512_F+VL}. + kIdVminsh, //!< Instruction 'vminsh' {AVX512_FP16+VL}. + kIdVminss, //!< Instruction 'vminss' {AVX|AVX512_F+VL}. kIdVmlaunch, //!< Instruction 'vmlaunch' {VMX}. kIdVmload, //!< Instruction 'vmload' {SVM}. kIdVmmcall, //!< Instruction 'vmmcall' {SVM}. kIdVmovapd, //!< Instruction 'vmovapd' {AVX|AVX512_F+VL}. kIdVmovaps, //!< Instruction 'vmovaps' {AVX|AVX512_F+VL}. - kIdVmovd, //!< Instruction 'vmovd' {AVX|AVX512_F}. + kIdVmovd, //!< Instruction 'vmovd' {AVX|AVX512_F+VL}. kIdVmovddup, //!< Instruction 'vmovddup' {AVX|AVX512_F+VL}. kIdVmovdqa, //!< Instruction 'vmovdqa' {AVX}. kIdVmovdqa32, //!< Instruction 'vmovdqa32' {AVX512_F+VL}. @@ -1326,27 +1269,27 @@ namespace Inst { kIdVmovdqu32, //!< Instruction 'vmovdqu32' {AVX512_F+VL}. kIdVmovdqu64, //!< Instruction 'vmovdqu64' {AVX512_F+VL}. kIdVmovdqu8, //!< Instruction 'vmovdqu8' {AVX512_BW+VL}. - kIdVmovhlps, //!< Instruction 'vmovhlps' {AVX|AVX512_F}. - kIdVmovhpd, //!< Instruction 'vmovhpd' {AVX|AVX512_F}. - kIdVmovhps, //!< Instruction 'vmovhps' {AVX|AVX512_F}. - kIdVmovlhps, //!< Instruction 'vmovlhps' {AVX|AVX512_F}. - kIdVmovlpd, //!< Instruction 'vmovlpd' {AVX|AVX512_F}. - kIdVmovlps, //!< Instruction 'vmovlps' {AVX|AVX512_F}. + kIdVmovhlps, //!< Instruction 'vmovhlps' {AVX|AVX512_F+VL}. + kIdVmovhpd, //!< Instruction 'vmovhpd' {AVX|AVX512_F+VL}. + kIdVmovhps, //!< Instruction 'vmovhps' {AVX|AVX512_F+VL}. + kIdVmovlhps, //!< Instruction 'vmovlhps' {AVX|AVX512_F+VL}. + kIdVmovlpd, //!< Instruction 'vmovlpd' {AVX|AVX512_F+VL}. + kIdVmovlps, //!< Instruction 'vmovlps' {AVX|AVX512_F+VL}. kIdVmovmskpd, //!< Instruction 'vmovmskpd' {AVX}. kIdVmovmskps, //!< Instruction 'vmovmskps' {AVX}. kIdVmovntdq, //!< Instruction 'vmovntdq' {AVX|AVX512_F+VL}. kIdVmovntdqa, //!< Instruction 'vmovntdqa' {AVX|AVX2|AVX512_F+VL}. kIdVmovntpd, //!< Instruction 'vmovntpd' {AVX|AVX512_F+VL}. kIdVmovntps, //!< Instruction 'vmovntps' {AVX|AVX512_F+VL}. - kIdVmovq, //!< Instruction 'vmovq' {AVX|AVX512_F}. - kIdVmovsd, //!< Instruction 'vmovsd' {AVX|AVX512_F}. - kIdVmovsh, //!< Instruction 'vmovsh' {AVX512_FP16}. + kIdVmovq, //!< Instruction 'vmovq' {AVX|AVX512_F+VL}. + kIdVmovsd, //!< Instruction 'vmovsd' {AVX|AVX512_F+VL}. + kIdVmovsh, //!< Instruction 'vmovsh' {AVX512_FP16+VL}. kIdVmovshdup, //!< Instruction 'vmovshdup' {AVX|AVX512_F+VL}. kIdVmovsldup, //!< Instruction 'vmovsldup' {AVX|AVX512_F+VL}. - kIdVmovss, //!< Instruction 'vmovss' {AVX|AVX512_F}. + kIdVmovss, //!< Instruction 'vmovss' {AVX|AVX512_F+VL}. kIdVmovupd, //!< Instruction 'vmovupd' {AVX|AVX512_F+VL}. kIdVmovups, //!< Instruction 'vmovups' {AVX|AVX512_F+VL}. - kIdVmovw, //!< Instruction 'vmovw' {AVX512_FP16}. + kIdVmovw, //!< Instruction 'vmovw' {AVX512_FP16+VL}. kIdVmpsadbw, //!< Instruction 'vmpsadbw' {AVX|AVX2}. kIdVmptrld, //!< Instruction 'vmptrld' {VMX}. kIdVmptrst, //!< Instruction 'vmptrst' {VMX}. @@ -1357,9 +1300,9 @@ namespace Inst { kIdVmulpd, //!< Instruction 'vmulpd' {AVX|AVX512_F+VL}. kIdVmulph, //!< Instruction 'vmulph' {AVX512_FP16+VL}. kIdVmulps, //!< Instruction 'vmulps' {AVX|AVX512_F+VL}. - kIdVmulsd, //!< Instruction 'vmulsd' {AVX|AVX512_F}. - kIdVmulsh, //!< Instruction 'vmulsh' {AVX512_FP16}. - kIdVmulss, //!< Instruction 'vmulss' {AVX|AVX512_F}. + kIdVmulsd, //!< Instruction 'vmulsd' {AVX|AVX512_F+VL}. + kIdVmulsh, //!< Instruction 'vmulsh' {AVX512_FP16+VL}. + kIdVmulss, //!< Instruction 'vmulss' {AVX|AVX512_F+VL}. kIdVmwrite, //!< Instruction 'vmwrite' {VMX}. kIdVmxoff, //!< Instruction 'vmxoff' {VMX}. kIdVmxon, //!< Instruction 'vmxon' {VMX}. @@ -1367,8 +1310,6 @@ namespace Inst { kIdVorps, //!< Instruction 'vorps' {AVX|AVX512_DQ+VL}. kIdVp2intersectd, //!< Instruction 'vp2intersectd' {AVX512_VP2INTERSECT+VL}. kIdVp2intersectq, //!< Instruction 'vp2intersectq' {AVX512_VP2INTERSECT+VL}. - kIdVp4dpwssd, //!< Instruction 'vp4dpwssd' {AVX512_4VNNIW}. - kIdVp4dpwssds, //!< Instruction 'vp4dpwssds' {AVX512_4VNNIW}. kIdVpabsb, //!< Instruction 'vpabsb' {AVX|AVX2|AVX512_BW+VL}. kIdVpabsd, //!< Instruction 'vpabsd' {AVX|AVX2|AVX512_F+VL}. kIdVpabsq, //!< Instruction 'vpabsq' {AVX512_F+VL}. @@ -1487,10 +1428,10 @@ namespace Inst { kIdVpexpandd, //!< Instruction 'vpexpandd' {AVX512_F+VL}. kIdVpexpandq, //!< Instruction 'vpexpandq' {AVX512_F+VL}. kIdVpexpandw, //!< Instruction 'vpexpandw' {AVX512_VBMI2+VL}. - kIdVpextrb, //!< Instruction 'vpextrb' {AVX|AVX512_BW}. - kIdVpextrd, //!< Instruction 'vpextrd' {AVX|AVX512_DQ}. - kIdVpextrq, //!< Instruction 'vpextrq' {AVX|AVX512_DQ} (X64). - kIdVpextrw, //!< Instruction 'vpextrw' {AVX|AVX512_BW}. + kIdVpextrb, //!< Instruction 'vpextrb' {AVX|AVX512_BW+VL}. + kIdVpextrd, //!< Instruction 'vpextrd' {AVX|AVX512_DQ+VL}. + kIdVpextrq, //!< Instruction 'vpextrq' {AVX|AVX512_DQ+VL} (X64). + kIdVpextrw, //!< Instruction 'vpextrw' {AVX|AVX512_BW+VL}. kIdVpgatherdd, //!< Instruction 'vpgatherdd' {AVX2|AVX512_F+VL}. kIdVpgatherdq, //!< Instruction 'vpgatherdq' {AVX2|AVX512_F+VL}. kIdVpgatherqd, //!< Instruction 'vpgatherqd' {AVX2|AVX512_F+VL}. @@ -1517,10 +1458,10 @@ namespace Inst { kIdVphsubsw, //!< Instruction 'vphsubsw' {AVX|AVX2}. kIdVphsubw, //!< Instruction 'vphsubw' {AVX|AVX2}. kIdVphsubwd, //!< Instruction 'vphsubwd' {XOP}. - kIdVpinsrb, //!< Instruction 'vpinsrb' {AVX|AVX512_BW}. - kIdVpinsrd, //!< Instruction 'vpinsrd' {AVX|AVX512_DQ}. - kIdVpinsrq, //!< Instruction 'vpinsrq' {AVX|AVX512_DQ} (X64). - kIdVpinsrw, //!< Instruction 'vpinsrw' {AVX|AVX512_BW}. + kIdVpinsrb, //!< Instruction 'vpinsrb' {AVX|AVX512_BW+VL}. + kIdVpinsrd, //!< Instruction 'vpinsrd' {AVX|AVX512_DQ+VL}. + kIdVpinsrq, //!< Instruction 'vpinsrq' {AVX|AVX512_DQ+VL} (X64). + kIdVpinsrw, //!< Instruction 'vpinsrw' {AVX|AVX512_BW+VL}. kIdVplzcntd, //!< Instruction 'vplzcntd' {AVX512_CD+VL}. kIdVplzcntq, //!< Instruction 'vplzcntq' {AVX512_CD+VL}. kIdVpmacsdd, //!< Instruction 'vpmacsdd' {XOP}. @@ -1710,64 +1651,48 @@ namespace Inst { kIdVpxorq, //!< Instruction 'vpxorq' {AVX512_F+VL}. kIdVrangepd, //!< Instruction 'vrangepd' {AVX512_DQ+VL}. kIdVrangeps, //!< Instruction 'vrangeps' {AVX512_DQ+VL}. - kIdVrangesd, //!< Instruction 'vrangesd' {AVX512_DQ}. - kIdVrangess, //!< Instruction 'vrangess' {AVX512_DQ}. + kIdVrangesd, //!< Instruction 'vrangesd' {AVX512_DQ+VL}. + kIdVrangess, //!< Instruction 'vrangess' {AVX512_DQ+VL}. kIdVrcp14pd, //!< Instruction 'vrcp14pd' {AVX512_F+VL}. kIdVrcp14ps, //!< Instruction 'vrcp14ps' {AVX512_F+VL}. - kIdVrcp14sd, //!< Instruction 'vrcp14sd' {AVX512_F}. - kIdVrcp14ss, //!< Instruction 'vrcp14ss' {AVX512_F}. - kIdVrcp28pd, //!< Instruction 'vrcp28pd' {AVX512_ER}. - kIdVrcp28ps, //!< Instruction 'vrcp28ps' {AVX512_ER}. - kIdVrcp28sd, //!< Instruction 'vrcp28sd' {AVX512_ER}. - kIdVrcp28ss, //!< Instruction 'vrcp28ss' {AVX512_ER}. - kIdVrcpph, //!< Instruction 'vrcpph' {AVX512_FP16}. + kIdVrcp14sd, //!< Instruction 'vrcp14sd' {AVX512_F+VL}. + kIdVrcp14ss, //!< Instruction 'vrcp14ss' {AVX512_F+VL}. + kIdVrcpph, //!< Instruction 'vrcpph' {AVX512_FP16+VL}. kIdVrcpps, //!< Instruction 'vrcpps' {AVX}. - kIdVrcpsh, //!< Instruction 'vrcpsh' {AVX512_FP16}. + kIdVrcpsh, //!< Instruction 'vrcpsh' {AVX512_FP16+VL}. kIdVrcpss, //!< Instruction 'vrcpss' {AVX}. kIdVreducepd, //!< Instruction 'vreducepd' {AVX512_DQ+VL}. kIdVreduceph, //!< Instruction 'vreduceph' {AVX512_FP16+VL}. kIdVreduceps, //!< Instruction 'vreduceps' {AVX512_DQ+VL}. - kIdVreducesd, //!< Instruction 'vreducesd' {AVX512_DQ}. - kIdVreducesh, //!< Instruction 'vreducesh' {AVX512_FP16}. - kIdVreducess, //!< Instruction 'vreducess' {AVX512_DQ}. + kIdVreducesd, //!< Instruction 'vreducesd' {AVX512_DQ+VL}. + kIdVreducesh, //!< Instruction 'vreducesh' {AVX512_FP16+VL}. + kIdVreducess, //!< Instruction 'vreducess' {AVX512_DQ+VL}. kIdVrndscalepd, //!< Instruction 'vrndscalepd' {AVX512_F+VL}. kIdVrndscaleph, //!< Instruction 'vrndscaleph' {AVX512_FP16+VL}. kIdVrndscaleps, //!< Instruction 'vrndscaleps' {AVX512_F+VL}. - kIdVrndscalesd, //!< Instruction 'vrndscalesd' {AVX512_F}. - kIdVrndscalesh, //!< Instruction 'vrndscalesh' {AVX512_FP16}. - kIdVrndscaless, //!< Instruction 'vrndscaless' {AVX512_F}. + kIdVrndscalesd, //!< Instruction 'vrndscalesd' {AVX512_F+VL}. + kIdVrndscalesh, //!< Instruction 'vrndscalesh' {AVX512_FP16+VL}. + kIdVrndscaless, //!< Instruction 'vrndscaless' {AVX512_F+VL}. kIdVroundpd, //!< Instruction 'vroundpd' {AVX}. kIdVroundps, //!< Instruction 'vroundps' {AVX}. kIdVroundsd, //!< Instruction 'vroundsd' {AVX}. kIdVroundss, //!< Instruction 'vroundss' {AVX}. kIdVrsqrt14pd, //!< Instruction 'vrsqrt14pd' {AVX512_F+VL}. kIdVrsqrt14ps, //!< Instruction 'vrsqrt14ps' {AVX512_F+VL}. - kIdVrsqrt14sd, //!< Instruction 'vrsqrt14sd' {AVX512_F}. - kIdVrsqrt14ss, //!< Instruction 'vrsqrt14ss' {AVX512_F}. - kIdVrsqrt28pd, //!< Instruction 'vrsqrt28pd' {AVX512_ER}. - kIdVrsqrt28ps, //!< Instruction 'vrsqrt28ps' {AVX512_ER}. - kIdVrsqrt28sd, //!< Instruction 'vrsqrt28sd' {AVX512_ER}. - kIdVrsqrt28ss, //!< Instruction 'vrsqrt28ss' {AVX512_ER}. + kIdVrsqrt14sd, //!< Instruction 'vrsqrt14sd' {AVX512_F+VL}. + kIdVrsqrt14ss, //!< Instruction 'vrsqrt14ss' {AVX512_F+VL}. kIdVrsqrtph, //!< Instruction 'vrsqrtph' {AVX512_FP16+VL}. kIdVrsqrtps, //!< Instruction 'vrsqrtps' {AVX}. - kIdVrsqrtsh, //!< Instruction 'vrsqrtsh' {AVX512_FP16}. + kIdVrsqrtsh, //!< Instruction 'vrsqrtsh' {AVX512_FP16+VL}. kIdVrsqrtss, //!< Instruction 'vrsqrtss' {AVX}. kIdVscalefpd, //!< Instruction 'vscalefpd' {AVX512_F+VL}. kIdVscalefph, //!< Instruction 'vscalefph' {AVX512_FP16+VL}. kIdVscalefps, //!< Instruction 'vscalefps' {AVX512_F+VL}. - kIdVscalefsd, //!< Instruction 'vscalefsd' {AVX512_F}. - kIdVscalefsh, //!< Instruction 'vscalefsh' {AVX512_FP16}. - kIdVscalefss, //!< Instruction 'vscalefss' {AVX512_F}. + kIdVscalefsd, //!< Instruction 'vscalefsd' {AVX512_F+VL}. + kIdVscalefsh, //!< Instruction 'vscalefsh' {AVX512_FP16+VL}. + kIdVscalefss, //!< Instruction 'vscalefss' {AVX512_F+VL}. kIdVscatterdpd, //!< Instruction 'vscatterdpd' {AVX512_F+VL}. kIdVscatterdps, //!< Instruction 'vscatterdps' {AVX512_F+VL}. - kIdVscatterpf0dpd, //!< Instruction 'vscatterpf0dpd' {AVX512_PF}. - kIdVscatterpf0dps, //!< Instruction 'vscatterpf0dps' {AVX512_PF}. - kIdVscatterpf0qpd, //!< Instruction 'vscatterpf0qpd' {AVX512_PF}. - kIdVscatterpf0qps, //!< Instruction 'vscatterpf0qps' {AVX512_PF}. - kIdVscatterpf1dpd, //!< Instruction 'vscatterpf1dpd' {AVX512_PF}. - kIdVscatterpf1dps, //!< Instruction 'vscatterpf1dps' {AVX512_PF}. - kIdVscatterpf1qpd, //!< Instruction 'vscatterpf1qpd' {AVX512_PF}. - kIdVscatterpf1qps, //!< Instruction 'vscatterpf1qps' {AVX512_PF}. kIdVscatterqpd, //!< Instruction 'vscatterqpd' {AVX512_F+VL}. kIdVscatterqps, //!< Instruction 'vscatterqps' {AVX512_F+VL}. kIdVsha512msg1, //!< Instruction 'vsha512msg1' {AVX & SHA512}. @@ -1787,21 +1712,21 @@ namespace Inst { kIdVsqrtpd, //!< Instruction 'vsqrtpd' {AVX|AVX512_F+VL}. kIdVsqrtph, //!< Instruction 'vsqrtph' {AVX512_FP16+VL}. kIdVsqrtps, //!< Instruction 'vsqrtps' {AVX|AVX512_F+VL}. - kIdVsqrtsd, //!< Instruction 'vsqrtsd' {AVX|AVX512_F}. - kIdVsqrtsh, //!< Instruction 'vsqrtsh' {AVX512_FP16}. - kIdVsqrtss, //!< Instruction 'vsqrtss' {AVX|AVX512_F}. + kIdVsqrtsd, //!< Instruction 'vsqrtsd' {AVX|AVX512_F+VL}. + kIdVsqrtsh, //!< Instruction 'vsqrtsh' {AVX512_FP16+VL}. + kIdVsqrtss, //!< Instruction 'vsqrtss' {AVX|AVX512_F+VL}. kIdVstmxcsr, //!< Instruction 'vstmxcsr' {AVX}. kIdVsubpd, //!< Instruction 'vsubpd' {AVX|AVX512_F+VL}. kIdVsubph, //!< Instruction 'vsubph' {AVX512_FP16+VL}. kIdVsubps, //!< Instruction 'vsubps' {AVX|AVX512_F+VL}. - kIdVsubsd, //!< Instruction 'vsubsd' {AVX|AVX512_F}. - kIdVsubsh, //!< Instruction 'vsubsh' {AVX512_FP16}. - kIdVsubss, //!< Instruction 'vsubss' {AVX|AVX512_F}. + kIdVsubsd, //!< Instruction 'vsubsd' {AVX|AVX512_F+VL}. + kIdVsubsh, //!< Instruction 'vsubsh' {AVX512_FP16+VL}. + kIdVsubss, //!< Instruction 'vsubss' {AVX|AVX512_F+VL}. kIdVtestpd, //!< Instruction 'vtestpd' {AVX}. kIdVtestps, //!< Instruction 'vtestps' {AVX}. - kIdVucomisd, //!< Instruction 'vucomisd' {AVX|AVX512_F}. - kIdVucomish, //!< Instruction 'vucomish' {AVX512_FP16}. - kIdVucomiss, //!< Instruction 'vucomiss' {AVX|AVX512_F}. + kIdVucomisd, //!< Instruction 'vucomisd' {AVX|AVX512_F+VL}. + kIdVucomish, //!< Instruction 'vucomish' {AVX512_FP16+VL}. + kIdVucomiss, //!< Instruction 'vucomiss' {AVX|AVX512_F+VL}. kIdVunpckhpd, //!< Instruction 'vunpckhpd' {AVX|AVX512_F+VL}. kIdVunpckhps, //!< Instruction 'vunpckhps' {AVX|AVX512_F+VL}. kIdVunpcklpd, //!< Instruction 'vunpcklpd' {AVX|AVX512_F+VL}. @@ -1844,8 +1769,54 @@ namespace Inst { kIdXsaves64, //!< Instruction 'xsaves64' {XSAVES} (X64). kIdXsetbv, //!< Instruction 'xsetbv' {XSAVE}. kIdXsusldtrk, //!< Instruction 'xsusldtrk' {TSXLDTRK}. - kIdXtest, //!< Instruction 'xtest' {TSX}. - _kIdCount + kIdXtest, //!< Instruction 'xtest' {RTM}. + _kIdCount, + + // Aliases. + kIdCmovnae = kIdCmovb, + kIdCmovc = kIdCmovb, + kIdCmovna = kIdCmovbe, + kIdCmovnge = kIdCmovl, + kIdCmovng = kIdCmovle, + kIdCmovae = kIdCmovnb, + kIdCmovnc = kIdCmovnb, + kIdCmova = kIdCmovnbe, + kIdCmovge = kIdCmovnl, + kIdCmovg = kIdCmovnle, + kIdCmovpo = kIdCmovnp, + kIdCmovne = kIdCmovnz, + kIdCmovpe = kIdCmovp, + kIdCmove = kIdCmovz, + kIdWait = kIdFwait, + kIdJnae = kIdJb, + kIdJc = kIdJb, + kIdJna = kIdJbe, + kIdJnge = kIdJl, + kIdJng = kIdJle, + kIdJae = kIdJnb, + kIdJnc = kIdJnb, + kIdJa = kIdJnbe, + kIdJge = kIdJnl, + kIdJg = kIdJnle, + kIdJpo = kIdJnp, + kIdJne = kIdJnz, + kIdJpe = kIdJp, + kIdJe = kIdJz, + kIdSetnae = kIdSetb, + kIdSetc = kIdSetb, + kIdSetna = kIdSetbe, + kIdSetnge = kIdSetl, + kIdSetng = kIdSetle, + kIdSetae = kIdSetnb, + kIdSetnc = kIdSetnb, + kIdSeta = kIdSetnbe, + kIdSetge = kIdSetnl, + kIdSetg = kIdSetnle, + kIdSetpo = kIdSetnp, + kIdSetne = kIdSetnz, + kIdSetpe = kIdSetp, + kIdSete = kIdSetz, + kIdSal = kIdShl // ${InstId:End} }; @@ -1854,10 +1825,10 @@ namespace Inst { //! \cond #define ASMJIT_INST_FROM_COND(ID) \ - ID##o, ID##no, ID##b , ID##ae, \ - ID##e, ID##ne, ID##be, ID##a , \ - ID##s, ID##ns, ID##pe, ID##po, \ - ID##l, ID##ge, ID##le, ID##g + ID##o, ID##no, ID##b , ID##nb , \ + ID##z, ID##nz, ID##be, ID##nbe, \ + ID##s, ID##ns, ID##p , ID##np , \ + ID##l, ID##nl, ID##le, ID##nle static constexpr uint16_t _jccTable[] = { ASMJIT_INST_FROM_COND(Inst::kIdJ) }; static constexpr uint16_t _setccTable[] = { ASMJIT_INST_FROM_COND(Inst::kIdSet) }; diff --git a/src/asmjit/x86/x86instapi.cpp b/src/asmjit/x86/x86instapi.cpp index fc17b5c..94cd31b 100644 --- a/src/asmjit/x86/x86instapi.cpp +++ b/src/asmjit/x86/x86instapi.cpp @@ -22,15 +22,37 @@ namespace InstInternal { // ======================== #ifndef ASMJIT_NO_TEXT -Error instIdToString(InstId instId, String& output) noexcept { +Error instIdToString(InstId instId, InstStringifyOptions options, String& output) noexcept { if (ASMJIT_UNLIKELY(!Inst::isDefinedId(instId))) return DebugUtils::errored(kErrorInvalidInstruction); - return InstNameUtils::decode(output, InstDB::_instNameIndexTable[instId], InstDB::_instNameStringTable); + return InstNameUtils::decode(InstDB::_instNameIndexTable[instId], options, InstDB::_instNameStringTable, output); } InstId stringToInstId(const char* s, size_t len) noexcept { - return InstNameUtils::find(s, len, InstDB::instNameIndex, InstDB::_instNameIndexTable, InstDB::_instNameStringTable); + if (ASMJIT_UNLIKELY(!s)) { + return BaseInst::kIdNone; + } + + if (len == SIZE_MAX) { + len = strlen(s); + } + + if (len == 0u || len > InstDB::instNameIndex.maxNameLength) { + return BaseInst::kIdNone; + } + + InstId instId = InstNameUtils::findInstruction(s, len, InstDB::_instNameIndexTable, InstDB::_instNameStringTable, InstDB::instNameIndex); + if (instId != BaseInst::kIdNone) { + return instId; + } + + uint32_t aliasIndex = InstNameUtils::findAlias(s, len, InstDB::_aliasNameIndexTable, InstDB::_aliasNameStringTable, InstDB::kAliasTableSize); + if (aliasIndex != Globals::kInvalidId) { + return InstDB::_aliasIndexToInstId[aliasIndex]; + } + + return BaseInst::kIdNone; } #endif // !ASMJIT_NO_TEXT @@ -1668,12 +1690,12 @@ UNIT(x86_inst_api_text) { INFO("Matching all X86 instructions"); for (uint32_t a = 1; a < Inst::_kIdCount; a++) { StringTmp<128> aName; - EXPECT_EQ(InstInternal::instIdToString(a, aName), kErrorOk) + EXPECT_EQ(InstInternal::instIdToString(a, InstStringifyOptions::kNone, aName), kErrorOk) .message("Failed to get the name of instruction #%u", a); uint32_t b = InstInternal::stringToInstId(aName.data(), aName.size()); StringTmp<128> bName; - InstInternal::instIdToString(b, bName); + InstInternal::instIdToString(b, InstStringifyOptions::kNone, bName); EXPECT_EQ(a, b) .message("Instructions do not match \"%s\" (#%u) != \"%s\" (#%u)", aName.data(), a, bName.data(), b); } diff --git a/src/asmjit/x86/x86instapi_p.h b/src/asmjit/x86/x86instapi_p.h index e0866ea..09df238 100644 --- a/src/asmjit/x86/x86instapi_p.h +++ b/src/asmjit/x86/x86instapi_p.h @@ -18,7 +18,7 @@ ASMJIT_BEGIN_SUB_NAMESPACE(x86) namespace InstInternal { #ifndef ASMJIT_NO_TEXT -Error ASMJIT_CDECL instIdToString(InstId instId, String& output) noexcept; +Error ASMJIT_CDECL instIdToString(InstId instId, InstStringifyOptions options, String& output) noexcept; InstId ASMJIT_CDECL stringToInstId(const char* s, size_t len) noexcept; #endif // !ASMJIT_NO_TEXT diff --git a/src/asmjit/x86/x86instdb.cpp b/src/asmjit/x86/x86instdb.cpp index ef06d58..d2aaac8 100644 --- a/src/asmjit/x86/x86instdb.cpp +++ b/src/asmjit/x86/x86instdb.cpp @@ -127,1648 +127,1573 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Clwb , X86M_Only , O(660F00,AE,6,_,_,_,_,_ ), 0 , 28 , 0 , 32 , 27 ), // #78 INST(Clzero , X86Op_MemZAX , O(000F01,FC,_,_,_,_,_,_ ), 0 , 23 , 0 , 35 , 28 ), // #79 INST(Cmc , X86Op , O(000000,F5,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 29 ), // #80 - INST(Cmova , X86Rm , O(000F00,47,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 30 ), // #81 - INST(Cmovae , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 31 ), // #82 - INST(Cmovb , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 31 ), // #83 - INST(Cmovbe , X86Rm , O(000F00,46,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 30 ), // #84 - INST(Cmovc , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 31 ), // #85 - INST(Cmove , X86Rm , O(000F00,44,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 32 ), // #86 - INST(Cmovg , X86Rm , O(000F00,4F,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 33 ), // #87 - INST(Cmovge , X86Rm , O(000F00,4D,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 34 ), // #88 - INST(Cmovl , X86Rm , O(000F00,4C,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 34 ), // #89 - INST(Cmovle , X86Rm , O(000F00,4E,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 33 ), // #90 - INST(Cmovna , X86Rm , O(000F00,46,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 30 ), // #91 - INST(Cmovnae , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 31 ), // #92 - INST(Cmovnb , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 31 ), // #93 - INST(Cmovnbe , X86Rm , O(000F00,47,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 30 ), // #94 - INST(Cmovnc , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 31 ), // #95 - INST(Cmovne , X86Rm , O(000F00,45,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 32 ), // #96 - INST(Cmovng , X86Rm , O(000F00,4E,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 33 ), // #97 - INST(Cmovnge , X86Rm , O(000F00,4C,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 34 ), // #98 - INST(Cmovnl , X86Rm , O(000F00,4D,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 34 ), // #99 - INST(Cmovnle , X86Rm , O(000F00,4F,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 33 ), // #100 - INST(Cmovno , X86Rm , O(000F00,41,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 35 ), // #101 - INST(Cmovnp , X86Rm , O(000F00,4B,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 36 ), // #102 - INST(Cmovns , X86Rm , O(000F00,49,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 37 ), // #103 - INST(Cmovnz , X86Rm , O(000F00,45,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 32 ), // #104 - INST(Cmovo , X86Rm , O(000F00,40,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 35 ), // #105 - INST(Cmovp , X86Rm , O(000F00,4A,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 36 ), // #106 - INST(Cmovpe , X86Rm , O(000F00,4A,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 36 ), // #107 - INST(Cmovpo , X86Rm , O(000F00,4B,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 36 ), // #108 - INST(Cmovs , X86Rm , O(000F00,48,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 37 ), // #109 - INST(Cmovz , X86Rm , O(000F00,44,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 32 ), // #110 - INST(Cmp , X86Arith , O(000000,38,7,_,x,_,_,_ ), 0 , 29 , 0 , 36 , 1 ), // #111 - INST(Cmpbexadd , VexMvr_Wx , V(660F38,E6,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #112 - INST(Cmpbxadd , VexMvr_Wx , V(660F38,E2,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #113 - INST(Cmplexadd , VexMvr_Wx , V(660F38,EE,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #114 - INST(Cmplxadd , VexMvr_Wx , V(660F38,EC,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #115 - INST(Cmpnbexadd , VexMvr_Wx , V(660F38,E7,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #116 - INST(Cmpnbxadd , VexMvr_Wx , V(660F38,E3,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #117 - INST(Cmpnlexadd , VexMvr_Wx , V(660F38,EF,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #118 - INST(Cmpnlxadd , VexMvr_Wx , V(660F38,ED,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #119 - INST(Cmpnoxadd , VexMvr_Wx , V(660F38,E1,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #120 - INST(Cmpnpxadd , VexMvr_Wx , V(660F38,EB,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #121 - INST(Cmpnsxadd , VexMvr_Wx , V(660F38,E9,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #122 - INST(Cmpnzxadd , VexMvr_Wx , V(660F38,E5,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #123 - INST(Cmpoxadd , VexMvr_Wx , V(660F38,E0,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #124 - INST(Cmppd , ExtRmi , O(660F00,C2,_,_,_,_,_,_ ), 0 , 4 , 0 , 9 , 5 ), // #125 - INST(Cmpps , ExtRmi , O(000F00,C2,_,_,_,_,_,_ ), 0 , 5 , 0 , 9 , 6 ), // #126 - INST(Cmppxadd , VexMvr_Wx , V(660F38,EA,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #127 - INST(Cmps , X86StrMm , O(000000,A6,_,_,_,_,_,_ ), 0 , 0 , 0 , 38 , 39 ), // #128 - INST(Cmpsd , ExtRmi , O(F20F00,C2,_,_,_,_,_,_ ), 0 , 6 , 0 , 39 , 5 ), // #129 - INST(Cmpss , ExtRmi , O(F30F00,C2,_,_,_,_,_,_ ), 0 , 7 , 0 , 40 , 6 ), // #130 - INST(Cmpsxadd , VexMvr_Wx , V(660F38,E8,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #131 - INST(Cmpxchg , X86Cmpxchg , O(000F00,B0,_,_,x,_,_,_ ), 0 , 5 , 0 , 41 , 40 ), // #132 - INST(Cmpxchg16b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,1,_,_,_ ), 0 , 31 , 0 , 42 , 41 ), // #133 - INST(Cmpxchg8b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,_,_,_,_ ), 0 , 32 , 0 , 43 , 42 ), // #134 - INST(Cmpzxadd , VexMvr_Wx , V(660F38,E4,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #135 - INST(Comisd , ExtRm , O(660F00,2F,_,_,_,_,_,_ ), 0 , 4 , 0 , 7 , 43 ), // #136 - INST(Comiss , ExtRm , O(000F00,2F,_,_,_,_,_,_ ), 0 , 5 , 0 , 8 , 44 ), // #137 - INST(Cpuid , X86Op , O(000F00,A2,_,_,_,_,_,_ ), 0 , 5 , 0 , 44 , 45 ), // #138 - INST(Cqo , X86Op_xDX_xAX , O(000000,99,_,_,1,_,_,_ ), 0 , 22 , 0 , 45 , 0 ), // #139 - INST(Crc32 , X86Crc , O(F20F38,F0,_,_,x,_,_,_ ), 0 , 12 , 0 , 46 , 46 ), // #140 - INST(Cvtdq2pd , ExtRm , O(F30F00,E6,_,_,_,_,_,_ ), 0 , 7 , 0 , 7 , 5 ), // #141 - INST(Cvtdq2ps , ExtRm , O(000F00,5B,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 5 ), // #142 - INST(Cvtpd2dq , ExtRm , O(F20F00,E6,_,_,_,_,_,_ ), 0 , 6 , 0 , 6 , 5 ), // #143 - INST(Cvtpd2pi , ExtRm , O(660F00,2D,_,_,_,_,_,_ ), 0 , 4 , 0 , 47 , 5 ), // #144 - INST(Cvtpd2ps , ExtRm , O(660F00,5A,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #145 - INST(Cvtpi2pd , ExtRm , O(660F00,2A,_,_,_,_,_,_ ), 0 , 4 , 0 , 48 , 5 ), // #146 - INST(Cvtpi2ps , ExtRm , O(000F00,2A,_,_,_,_,_,_ ), 0 , 5 , 0 , 48 , 6 ), // #147 - INST(Cvtps2dq , ExtRm , O(660F00,5B,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #148 - INST(Cvtps2pd , ExtRm , O(000F00,5A,_,_,_,_,_,_ ), 0 , 5 , 0 , 7 , 5 ), // #149 - INST(Cvtps2pi , ExtRm , O(000F00,2D,_,_,_,_,_,_ ), 0 , 5 , 0 , 49 , 6 ), // #150 - INST(Cvtsd2si , ExtRm_Wx_GpqOnly , O(F20F00,2D,_,_,x,_,_,_ ), 0 , 6 , 0 , 50 , 5 ), // #151 - INST(Cvtsd2ss , ExtRm , O(F20F00,5A,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #152 - INST(Cvtsi2sd , ExtRm_Wx , O(F20F00,2A,_,_,x,_,_,_ ), 0 , 6 , 0 , 51 , 5 ), // #153 - INST(Cvtsi2ss , ExtRm_Wx , O(F30F00,2A,_,_,x,_,_,_ ), 0 , 7 , 0 , 52 , 6 ), // #154 - INST(Cvtss2sd , ExtRm , O(F30F00,5A,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 5 ), // #155 - INST(Cvtss2si , ExtRm_Wx_GpqOnly , O(F30F00,2D,_,_,x,_,_,_ ), 0 , 7 , 0 , 53 , 6 ), // #156 - INST(Cvttpd2dq , ExtRm , O(660F00,E6,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #157 - INST(Cvttpd2pi , ExtRm , O(660F00,2C,_,_,_,_,_,_ ), 0 , 4 , 0 , 47 , 5 ), // #158 - INST(Cvttps2dq , ExtRm , O(F30F00,5B,_,_,_,_,_,_ ), 0 , 7 , 0 , 6 , 5 ), // #159 - INST(Cvttps2pi , ExtRm , O(000F00,2C,_,_,_,_,_,_ ), 0 , 5 , 0 , 49 , 6 ), // #160 - INST(Cvttsd2si , ExtRm_Wx_GpqOnly , O(F20F00,2C,_,_,x,_,_,_ ), 0 , 6 , 0 , 50 , 5 ), // #161 - INST(Cvttss2si , ExtRm_Wx_GpqOnly , O(F30F00,2C,_,_,x,_,_,_ ), 0 , 7 , 0 , 54 , 6 ), // #162 - INST(Cwd , X86Op_xDX_xAX , O(660000,99,_,_,_,_,_,_ ), 0 , 21 , 0 , 55 , 0 ), // #163 - INST(Cwde , X86Op_xAX , O(000000,98,_,_,_,_,_,_ ), 0 , 0 , 0 , 56 , 0 ), // #164 - INST(Daa , X86Op , O(000000,27,_,_,_,_,_,_ ), 0 , 0 , 0 , 1 , 1 ), // #165 - INST(Das , X86Op , O(000000,2F,_,_,_,_,_,_ ), 0 , 0 , 0 , 1 , 1 ), // #166 - INST(Dec , X86IncDec , O(000000,FE,1,_,x,_,_,_ ), O(000000,48,_,_,x,_,_,_ ), 33 , 6 , 57 , 47 ), // #167 - INST(Div , X86M_GPB_MulDiv , O(000000,F6,6,_,x,_,_,_ ), 0 , 34 , 0 , 58 , 1 ), // #168 - INST(Divpd , ExtRm , O(660F00,5E,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #169 - INST(Divps , ExtRm , O(000F00,5E,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #170 - INST(Divsd , ExtRm , O(F20F00,5E,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #171 - INST(Divss , ExtRm , O(F30F00,5E,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #172 - INST(Dppd , ExtRmi , O(660F3A,41,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #173 - INST(Dpps , ExtRmi , O(660F3A,40,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #174 - INST(Emms , X86Op , O(000F00,77,_,_,_,_,_,_ ), 0 , 5 , 0 , 59 , 48 ), // #175 - INST(Endbr32 , X86Op_Mod11RM , O(F30F00,1E,7,_,_,_,_,3 ), 0 , 35 , 0 , 31 , 49 ), // #176 - INST(Endbr64 , X86Op_Mod11RM , O(F30F00,1E,7,_,_,_,_,2 ), 0 , 36 , 0 , 31 , 49 ), // #177 - INST(Enqcmd , X86EnqcmdMovdir64b , O(F20F38,F8,_,_,_,_,_,_ ), 0 , 12 , 0 , 60 , 50 ), // #178 - INST(Enqcmds , X86EnqcmdMovdir64b , O(F30F38,F8,_,_,_,_,_,_ ), 0 , 8 , 0 , 60 , 50 ), // #179 - INST(Enter , X86Enter , O(000000,C8,_,_,_,_,_,_ ), 0 , 0 , 0 , 61 , 0 ), // #180 - INST(Extractps , ExtExtract , O(660F3A,17,_,_,_,_,_,_ ), 0 , 9 , 0 , 62 , 13 ), // #181 - INST(Extrq , ExtExtrq , O(660F00,79,_,_,_,_,_,_ ), O(660F00,78,0,_,_,_,_,_ ), 4 , 7 , 63 , 51 ), // #182 - INST(F2xm1 , FpuOp , O_FPU(00,D9F0,_) , 0 , 37 , 0 , 31 , 52 ), // #183 - INST(Fabs , FpuOp , O_FPU(00,D9E1,_) , 0 , 37 , 0 , 31 , 52 ), // #184 - INST(Fadd , FpuArith , O_FPU(00,C0C0,0) , 0 , 38 , 0 , 64 , 52 ), // #185 - INST(Faddp , FpuRDef , O_FPU(00,DEC0,_) , 0 , 39 , 0 , 65 , 52 ), // #186 - INST(Fbld , X86M_Only , O_FPU(00,00DF,4) , 0 , 40 , 0 , 66 , 52 ), // #187 - INST(Fbstp , X86M_Only , O_FPU(00,00DF,6) , 0 , 41 , 0 , 66 , 52 ), // #188 - INST(Fchs , FpuOp , O_FPU(00,D9E0,_) , 0 , 37 , 0 , 31 , 52 ), // #189 - INST(Fclex , FpuOp , O_FPU(9B,DBE2,_) , 0 , 42 , 0 , 31 , 52 ), // #190 - INST(Fcmovb , FpuR , O_FPU(00,DAC0,_) , 0 , 43 , 0 , 67 , 53 ), // #191 - INST(Fcmovbe , FpuR , O_FPU(00,DAD0,_) , 0 , 43 , 0 , 67 , 54 ), // #192 - INST(Fcmove , FpuR , O_FPU(00,DAC8,_) , 0 , 43 , 0 , 67 , 55 ), // #193 - INST(Fcmovnb , FpuR , O_FPU(00,DBC0,_) , 0 , 44 , 0 , 67 , 53 ), // #194 - INST(Fcmovnbe , FpuR , O_FPU(00,DBD0,_) , 0 , 44 , 0 , 67 , 54 ), // #195 - INST(Fcmovne , FpuR , O_FPU(00,DBC8,_) , 0 , 44 , 0 , 67 , 55 ), // #196 - INST(Fcmovnu , FpuR , O_FPU(00,DBD8,_) , 0 , 44 , 0 , 67 , 56 ), // #197 - INST(Fcmovu , FpuR , O_FPU(00,DAD8,_) , 0 , 43 , 0 , 67 , 56 ), // #198 - INST(Fcom , FpuCom , O_FPU(00,D0D0,2) , 0 , 45 , 0 , 68 , 52 ), // #199 - INST(Fcomi , FpuR , O_FPU(00,DBF0,_) , 0 , 44 , 0 , 67 , 57 ), // #200 - INST(Fcomip , FpuR , O_FPU(00,DFF0,_) , 0 , 46 , 0 , 67 , 57 ), // #201 - INST(Fcomp , FpuCom , O_FPU(00,D8D8,3) , 0 , 47 , 0 , 68 , 52 ), // #202 - INST(Fcompp , FpuOp , O_FPU(00,DED9,_) , 0 , 39 , 0 , 31 , 52 ), // #203 - INST(Fcos , FpuOp , O_FPU(00,D9FF,_) , 0 , 37 , 0 , 31 , 52 ), // #204 - INST(Fdecstp , FpuOp , O_FPU(00,D9F6,_) , 0 , 37 , 0 , 31 , 52 ), // #205 - INST(Fdiv , FpuArith , O_FPU(00,F0F8,6) , 0 , 48 , 0 , 64 , 52 ), // #206 - INST(Fdivp , FpuRDef , O_FPU(00,DEF8,_) , 0 , 39 , 0 , 65 , 52 ), // #207 - INST(Fdivr , FpuArith , O_FPU(00,F8F0,7) , 0 , 49 , 0 , 64 , 52 ), // #208 - INST(Fdivrp , FpuRDef , O_FPU(00,DEF0,_) , 0 , 39 , 0 , 65 , 52 ), // #209 - INST(Femms , X86Op , O(000F00,0E,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 58 ), // #210 - INST(Ffree , FpuR , O_FPU(00,DDC0,_) , 0 , 50 , 0 , 67 , 52 ), // #211 - INST(Fiadd , FpuM , O_FPU(00,00DA,0) , 0 , 51 , 0 , 69 , 52 ), // #212 - INST(Ficom , FpuM , O_FPU(00,00DA,2) , 0 , 52 , 0 , 69 , 52 ), // #213 - INST(Ficomp , FpuM , O_FPU(00,00DA,3) , 0 , 53 , 0 , 69 , 52 ), // #214 - INST(Fidiv , FpuM , O_FPU(00,00DA,6) , 0 , 41 , 0 , 69 , 52 ), // #215 - INST(Fidivr , FpuM , O_FPU(00,00DA,7) , 0 , 54 , 0 , 69 , 52 ), // #216 - INST(Fild , FpuM , O_FPU(00,00DB,0) , O_FPU(00,00DF,5) , 51 , 8 , 70 , 52 ), // #217 - INST(Fimul , FpuM , O_FPU(00,00DA,1) , 0 , 55 , 0 , 69 , 52 ), // #218 - INST(Fincstp , FpuOp , O_FPU(00,D9F7,_) , 0 , 37 , 0 , 31 , 52 ), // #219 - INST(Finit , FpuOp , O_FPU(9B,DBE3,_) , 0 , 42 , 0 , 31 , 52 ), // #220 - INST(Fist , FpuM , O_FPU(00,00DB,2) , 0 , 52 , 0 , 69 , 52 ), // #221 - INST(Fistp , FpuM , O_FPU(00,00DB,3) , O_FPU(00,00DF,7) , 53 , 9 , 70 , 52 ), // #222 - INST(Fisttp , FpuM , O_FPU(00,00DB,1) , O_FPU(00,00DD,1) , 55 , 10 , 70 , 59 ), // #223 - INST(Fisub , FpuM , O_FPU(00,00DA,4) , 0 , 40 , 0 , 69 , 52 ), // #224 - INST(Fisubr , FpuM , O_FPU(00,00DA,5) , 0 , 56 , 0 , 69 , 52 ), // #225 - INST(Fld , FpuFldFst , O_FPU(00,00D9,0) , O_FPU(00,00DB,5) , 51 , 11 , 71 , 52 ), // #226 - INST(Fld1 , FpuOp , O_FPU(00,D9E8,_) , 0 , 37 , 0 , 31 , 52 ), // #227 - INST(Fldcw , X86M_Only , O_FPU(00,00D9,5) , 0 , 56 , 0 , 72 , 52 ), // #228 - INST(Fldenv , X86M_Only , O_FPU(00,00D9,4) , 0 , 40 , 0 , 32 , 52 ), // #229 - INST(Fldl2e , FpuOp , O_FPU(00,D9EA,_) , 0 , 37 , 0 , 31 , 52 ), // #230 - INST(Fldl2t , FpuOp , O_FPU(00,D9E9,_) , 0 , 37 , 0 , 31 , 52 ), // #231 - INST(Fldlg2 , FpuOp , O_FPU(00,D9EC,_) , 0 , 37 , 0 , 31 , 52 ), // #232 - INST(Fldln2 , FpuOp , O_FPU(00,D9ED,_) , 0 , 37 , 0 , 31 , 52 ), // #233 - INST(Fldpi , FpuOp , O_FPU(00,D9EB,_) , 0 , 37 , 0 , 31 , 52 ), // #234 - INST(Fldz , FpuOp , O_FPU(00,D9EE,_) , 0 , 37 , 0 , 31 , 52 ), // #235 - INST(Fmul , FpuArith , O_FPU(00,C8C8,1) , 0 , 57 , 0 , 64 , 52 ), // #236 - INST(Fmulp , FpuRDef , O_FPU(00,DEC8,_) , 0 , 39 , 0 , 65 , 52 ), // #237 - INST(Fnclex , FpuOp , O_FPU(00,DBE2,_) , 0 , 44 , 0 , 31 , 52 ), // #238 - INST(Fninit , FpuOp , O_FPU(00,DBE3,_) , 0 , 44 , 0 , 31 , 52 ), // #239 - INST(Fnop , FpuOp , O_FPU(00,D9D0,_) , 0 , 37 , 0 , 31 , 52 ), // #240 - INST(Fnsave , X86M_Only , O_FPU(00,00DD,6) , 0 , 41 , 0 , 32 , 52 ), // #241 - INST(Fnstcw , X86M_Only , O_FPU(00,00D9,7) , 0 , 54 , 0 , 72 , 52 ), // #242 - INST(Fnstenv , X86M_Only , O_FPU(00,00D9,6) , 0 , 41 , 0 , 32 , 52 ), // #243 - INST(Fnstsw , FpuStsw , O_FPU(00,00DD,7) , O_FPU(00,DFE0,_) , 54 , 12 , 73 , 52 ), // #244 - INST(Fpatan , FpuOp , O_FPU(00,D9F3,_) , 0 , 37 , 0 , 31 , 52 ), // #245 - INST(Fprem , FpuOp , O_FPU(00,D9F8,_) , 0 , 37 , 0 , 31 , 52 ), // #246 - INST(Fprem1 , FpuOp , O_FPU(00,D9F5,_) , 0 , 37 , 0 , 31 , 52 ), // #247 - INST(Fptan , FpuOp , O_FPU(00,D9F2,_) , 0 , 37 , 0 , 31 , 52 ), // #248 - INST(Frndint , FpuOp , O_FPU(00,D9FC,_) , 0 , 37 , 0 , 31 , 52 ), // #249 - INST(Frstor , X86M_Only , O_FPU(00,00DD,4) , 0 , 40 , 0 , 32 , 52 ), // #250 - INST(Fsave , X86M_Only , O_FPU(9B,00DD,6) , 0 , 58 , 0 , 32 , 52 ), // #251 - INST(Fscale , FpuOp , O_FPU(00,D9FD,_) , 0 , 37 , 0 , 31 , 52 ), // #252 - INST(Fsin , FpuOp , O_FPU(00,D9FE,_) , 0 , 37 , 0 , 31 , 52 ), // #253 - INST(Fsincos , FpuOp , O_FPU(00,D9FB,_) , 0 , 37 , 0 , 31 , 52 ), // #254 - INST(Fsqrt , FpuOp , O_FPU(00,D9FA,_) , 0 , 37 , 0 , 31 , 52 ), // #255 - INST(Fst , FpuFldFst , O_FPU(00,00D9,2) , 0 , 52 , 0 , 74 , 52 ), // #256 - INST(Fstcw , X86M_Only , O_FPU(9B,00D9,7) , 0 , 59 , 0 , 72 , 52 ), // #257 - INST(Fstenv , X86M_Only , O_FPU(9B,00D9,6) , 0 , 58 , 0 , 32 , 52 ), // #258 - INST(Fstp , FpuFldFst , O_FPU(00,00D9,3) , O(000000,DB,7,_,_,_,_,_ ), 53 , 13 , 71 , 52 ), // #259 - INST(Fstsw , FpuStsw , O_FPU(9B,00DD,7) , O_FPU(9B,DFE0,_) , 59 , 14 , 73 , 52 ), // #260 - INST(Fsub , FpuArith , O_FPU(00,E0E8,4) , 0 , 60 , 0 , 64 , 52 ), // #261 - INST(Fsubp , FpuRDef , O_FPU(00,DEE8,_) , 0 , 39 , 0 , 65 , 52 ), // #262 - INST(Fsubr , FpuArith , O_FPU(00,E8E0,5) , 0 , 61 , 0 , 64 , 52 ), // #263 - INST(Fsubrp , FpuRDef , O_FPU(00,DEE0,_) , 0 , 39 , 0 , 65 , 52 ), // #264 - INST(Ftst , FpuOp , O_FPU(00,D9E4,_) , 0 , 37 , 0 , 31 , 52 ), // #265 - INST(Fucom , FpuRDef , O_FPU(00,DDE0,_) , 0 , 50 , 0 , 65 , 52 ), // #266 - INST(Fucomi , FpuR , O_FPU(00,DBE8,_) , 0 , 44 , 0 , 67 , 57 ), // #267 - INST(Fucomip , FpuR , O_FPU(00,DFE8,_) , 0 , 46 , 0 , 67 , 57 ), // #268 - INST(Fucomp , FpuRDef , O_FPU(00,DDE8,_) , 0 , 50 , 0 , 65 , 52 ), // #269 - INST(Fucompp , FpuOp , O_FPU(00,DAE9,_) , 0 , 43 , 0 , 31 , 52 ), // #270 - INST(Fwait , X86Op , O_FPU(00,009B,_) , 0 , 51 , 0 , 31 , 52 ), // #271 - INST(Fxam , FpuOp , O_FPU(00,D9E5,_) , 0 , 37 , 0 , 31 , 52 ), // #272 - INST(Fxch , FpuR , O_FPU(00,D9C8,_) , 0 , 37 , 0 , 65 , 52 ), // #273 - INST(Fxrstor , X86M_Only , O(000F00,AE,1,_,_,_,_,_ ), 0 , 32 , 0 , 32 , 60 ), // #274 - INST(Fxrstor64 , X86M_Only , O(000F00,AE,1,_,1,_,_,_ ), 0 , 31 , 0 , 75 , 60 ), // #275 - INST(Fxsave , X86M_Only , O(000F00,AE,0,_,_,_,_,_ ), 0 , 5 , 0 , 32 , 61 ), // #276 - INST(Fxsave64 , X86M_Only , O(000F00,AE,0,_,1,_,_,_ ), 0 , 62 , 0 , 75 , 61 ), // #277 - INST(Fxtract , FpuOp , O_FPU(00,D9F4,_) , 0 , 37 , 0 , 31 , 52 ), // #278 - INST(Fyl2x , FpuOp , O_FPU(00,D9F1,_) , 0 , 37 , 0 , 31 , 52 ), // #279 - INST(Fyl2xp1 , FpuOp , O_FPU(00,D9F9,_) , 0 , 37 , 0 , 31 , 52 ), // #280 - INST(Getsec , X86Op , O(000F00,37,_,_,_,_,_,_ ), 0 , 5 , 0 , 56 , 62 ), // #281 - INST(Gf2p8affineinvqb , ExtRmi , O(660F3A,CF,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 63 ), // #282 - INST(Gf2p8affineqb , ExtRmi , O(660F3A,CE,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 63 ), // #283 - INST(Gf2p8mulb , ExtRm , O(660F38,CF,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 63 ), // #284 - INST(Haddpd , ExtRm , O(660F00,7C,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 7 ), // #285 - INST(Haddps , ExtRm , O(F20F00,7C,_,_,_,_,_,_ ), 0 , 6 , 0 , 6 , 7 ), // #286 - INST(Hlt , X86Op , O(000000,F4,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 0 ), // #287 - INST(Hreset , X86Op_Mod11RM_I8 , O(F30F3A,F0,0,_,_,_,_,_ ), 0 , 63 , 0 , 76 , 64 ), // #288 - INST(Hsubpd , ExtRm , O(660F00,7D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 7 ), // #289 - INST(Hsubps , ExtRm , O(F20F00,7D,_,_,_,_,_,_ ), 0 , 6 , 0 , 6 , 7 ), // #290 - INST(Idiv , X86M_GPB_MulDiv , O(000000,F6,7,_,x,_,_,_ ), 0 , 29 , 0 , 58 , 1 ), // #291 - INST(Imul , X86Imul , O(000000,F6,5,_,x,_,_,_ ), 0 , 64 , 0 , 77 , 1 ), // #292 - INST(In , X86In , O(000000,EC,_,_,_,_,_,_ ), O(000000,E4,_,_,_,_,_,_ ), 0 , 15 , 78 , 0 ), // #293 - INST(Inc , X86IncDec , O(000000,FE,0,_,x,_,_,_ ), O(000000,40,_,_,x,_,_,_ ), 0 , 16 , 79 , 47 ), // #294 - INST(Incsspd , X86M , O(F30F00,AE,5,_,0,_,_,_ ), 0 , 65 , 0 , 80 , 65 ), // #295 - INST(Incsspq , X86M , O(F30F00,AE,5,_,1,_,_,_ ), 0 , 66 , 0 , 81 , 65 ), // #296 - INST(Ins , X86Ins , O(000000,6C,_,_,_,_,_,_ ), 0 , 0 , 0 , 82 , 0 ), // #297 - INST(Insertps , ExtRmi , O(660F3A,21,_,_,_,_,_,_ ), 0 , 9 , 0 , 40 , 13 ), // #298 - INST(Insertq , ExtInsertq , O(F20F00,79,_,_,_,_,_,_ ), O(F20F00,78,_,_,_,_,_,_ ), 6 , 17 , 83 , 51 ), // #299 - INST(Int , X86Int , O(000000,CD,_,_,_,_,_,_ ), 0 , 0 , 0 , 84 , 0 ), // #300 - INST(Int3 , X86Op , O(000000,CC,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 0 ), // #301 - INST(Into , X86Op , O(000000,CE,_,_,_,_,_,_ ), 0 , 0 , 0 , 85 , 66 ), // #302 - INST(Invd , X86Op , O(000F00,08,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 45 ), // #303 - INST(Invept , X86Rm_NoSize , O(660F38,80,_,_,_,_,_,_ ), 0 , 2 , 0 , 86 , 67 ), // #304 - INST(Invlpg , X86M_Only , O(000F00,01,7,_,_,_,_,_ ), 0 , 24 , 0 , 32 , 45 ), // #305 - INST(Invlpga , X86Op_xAddr , O(000F01,DF,_,_,_,_,_,_ ), 0 , 23 , 0 , 87 , 23 ), // #306 - INST(Invlpgb , X86Op , O(000F01,FE,_,_,_,_,_,_ ), 0 , 23 , 0 , 88 , 68 ), // #307 - INST(Invpcid , X86Rm_NoSize , O(660F38,82,_,_,_,_,_,_ ), 0 , 2 , 0 , 86 , 45 ), // #308 - INST(Invvpid , X86Rm_NoSize , O(660F38,81,_,_,_,_,_,_ ), 0 , 2 , 0 , 86 , 67 ), // #309 - INST(Iret , X86Op , O(660000,CF,_,_,_,_,_,_ ), 0 , 21 , 0 , 89 , 1 ), // #310 - INST(Iretd , X86Op , O(000000,CF,_,_,_,_,_,_ ), 0 , 0 , 0 , 89 , 1 ), // #311 - INST(Iretq , X86Op , O(000000,CF,_,_,1,_,_,_ ), 0 , 22 , 0 , 90 , 1 ), // #312 - INST(Ja , X86Jcc , O(000F00,87,_,_,_,_,_,_ ), O(000000,77,_,_,_,_,_,_ ), 5 , 18 , 91 , 69 ), // #313 - INST(Jae , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 5 , 19 , 91 , 70 ), // #314 - INST(Jb , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 5 , 20 , 91 , 70 ), // #315 - INST(Jbe , X86Jcc , O(000F00,86,_,_,_,_,_,_ ), O(000000,76,_,_,_,_,_,_ ), 5 , 21 , 91 , 69 ), // #316 - INST(Jc , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 5 , 20 , 91 , 70 ), // #317 - INST(Je , X86Jcc , O(000F00,84,_,_,_,_,_,_ ), O(000000,74,_,_,_,_,_,_ ), 5 , 22 , 91 , 71 ), // #318 - INST(Jecxz , X86JecxzLoop , 0 , O(000000,E3,_,_,_,_,_,_ ), 0 , 23 , 92 , 0 ), // #319 - INST(Jg , X86Jcc , O(000F00,8F,_,_,_,_,_,_ ), O(000000,7F,_,_,_,_,_,_ ), 5 , 24 , 91 , 72 ), // #320 - INST(Jge , X86Jcc , O(000F00,8D,_,_,_,_,_,_ ), O(000000,7D,_,_,_,_,_,_ ), 5 , 25 , 91 , 73 ), // #321 - INST(Jl , X86Jcc , O(000F00,8C,_,_,_,_,_,_ ), O(000000,7C,_,_,_,_,_,_ ), 5 , 26 , 91 , 73 ), // #322 - INST(Jle , X86Jcc , O(000F00,8E,_,_,_,_,_,_ ), O(000000,7E,_,_,_,_,_,_ ), 5 , 27 , 91 , 72 ), // #323 - INST(Jmp , X86Jmp , O(000000,FF,4,_,_,_,_,_ ), O(000000,EB,_,_,_,_,_,_ ), 10 , 28 , 93 , 0 ), // #324 - INST(Jna , X86Jcc , O(000F00,86,_,_,_,_,_,_ ), O(000000,76,_,_,_,_,_,_ ), 5 , 21 , 91 , 69 ), // #325 - INST(Jnae , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 5 , 20 , 91 , 70 ), // #326 - INST(Jnb , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 5 , 19 , 91 , 70 ), // #327 - INST(Jnbe , X86Jcc , O(000F00,87,_,_,_,_,_,_ ), O(000000,77,_,_,_,_,_,_ ), 5 , 18 , 91 , 69 ), // #328 - INST(Jnc , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 5 , 19 , 91 , 70 ), // #329 - INST(Jne , X86Jcc , O(000F00,85,_,_,_,_,_,_ ), O(000000,75,_,_,_,_,_,_ ), 5 , 29 , 91 , 71 ), // #330 - INST(Jng , X86Jcc , O(000F00,8E,_,_,_,_,_,_ ), O(000000,7E,_,_,_,_,_,_ ), 5 , 27 , 91 , 72 ), // #331 - INST(Jnge , X86Jcc , O(000F00,8C,_,_,_,_,_,_ ), O(000000,7C,_,_,_,_,_,_ ), 5 , 26 , 91 , 73 ), // #332 - INST(Jnl , X86Jcc , O(000F00,8D,_,_,_,_,_,_ ), O(000000,7D,_,_,_,_,_,_ ), 5 , 25 , 91 , 73 ), // #333 - INST(Jnle , X86Jcc , O(000F00,8F,_,_,_,_,_,_ ), O(000000,7F,_,_,_,_,_,_ ), 5 , 24 , 91 , 72 ), // #334 - INST(Jno , X86Jcc , O(000F00,81,_,_,_,_,_,_ ), O(000000,71,_,_,_,_,_,_ ), 5 , 30 , 91 , 66 ), // #335 - INST(Jnp , X86Jcc , O(000F00,8B,_,_,_,_,_,_ ), O(000000,7B,_,_,_,_,_,_ ), 5 , 31 , 91 , 74 ), // #336 - INST(Jns , X86Jcc , O(000F00,89,_,_,_,_,_,_ ), O(000000,79,_,_,_,_,_,_ ), 5 , 32 , 91 , 75 ), // #337 - INST(Jnz , X86Jcc , O(000F00,85,_,_,_,_,_,_ ), O(000000,75,_,_,_,_,_,_ ), 5 , 29 , 91 , 71 ), // #338 - INST(Jo , X86Jcc , O(000F00,80,_,_,_,_,_,_ ), O(000000,70,_,_,_,_,_,_ ), 5 , 33 , 91 , 66 ), // #339 - INST(Jp , X86Jcc , O(000F00,8A,_,_,_,_,_,_ ), O(000000,7A,_,_,_,_,_,_ ), 5 , 34 , 91 , 74 ), // #340 - INST(Jpe , X86Jcc , O(000F00,8A,_,_,_,_,_,_ ), O(000000,7A,_,_,_,_,_,_ ), 5 , 34 , 91 , 74 ), // #341 - INST(Jpo , X86Jcc , O(000F00,8B,_,_,_,_,_,_ ), O(000000,7B,_,_,_,_,_,_ ), 5 , 31 , 91 , 74 ), // #342 - INST(Js , X86Jcc , O(000F00,88,_,_,_,_,_,_ ), O(000000,78,_,_,_,_,_,_ ), 5 , 35 , 91 , 75 ), // #343 - INST(Jz , X86Jcc , O(000F00,84,_,_,_,_,_,_ ), O(000000,74,_,_,_,_,_,_ ), 5 , 22 , 91 , 71 ), // #344 - INST(Kaddb , VexRvm , V(660F00,4A,_,1,0,_,_,_ ), 0 , 67 , 0 , 94 , 76 ), // #345 - INST(Kaddd , VexRvm , V(660F00,4A,_,1,1,_,_,_ ), 0 , 68 , 0 , 94 , 77 ), // #346 - INST(Kaddq , VexRvm , V(000F00,4A,_,1,1,_,_,_ ), 0 , 69 , 0 , 94 , 77 ), // #347 - INST(Kaddw , VexRvm , V(000F00,4A,_,1,0,_,_,_ ), 0 , 70 , 0 , 94 , 76 ), // #348 - INST(Kandb , VexRvm , V(660F00,41,_,1,0,_,_,_ ), 0 , 67 , 0 , 94 , 76 ), // #349 - INST(Kandd , VexRvm , V(660F00,41,_,1,1,_,_,_ ), 0 , 68 , 0 , 94 , 77 ), // #350 - INST(Kandnb , VexRvm , V(660F00,42,_,1,0,_,_,_ ), 0 , 67 , 0 , 94 , 76 ), // #351 - INST(Kandnd , VexRvm , V(660F00,42,_,1,1,_,_,_ ), 0 , 68 , 0 , 94 , 77 ), // #352 - INST(Kandnq , VexRvm , V(000F00,42,_,1,1,_,_,_ ), 0 , 69 , 0 , 94 , 77 ), // #353 - INST(Kandnw , VexRvm , V(000F00,42,_,1,0,_,_,_ ), 0 , 70 , 0 , 94 , 78 ), // #354 - INST(Kandq , VexRvm , V(000F00,41,_,1,1,_,_,_ ), 0 , 69 , 0 , 94 , 77 ), // #355 - INST(Kandw , VexRvm , V(000F00,41,_,1,0,_,_,_ ), 0 , 70 , 0 , 94 , 78 ), // #356 - INST(Kmovb , VexKmov , V(660F00,90,_,0,0,_,_,_ ), V(660F00,92,_,0,0,_,_,_ ), 71 , 36 , 95 , 79 ), // #357 - INST(Kmovd , VexKmov , V(660F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,0,_,_,_ ), 72 , 37 , 96 , 80 ), // #358 - INST(Kmovq , VexKmov , V(000F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,1,_,_,_ ), 73 , 38 , 97 , 80 ), // #359 - INST(Kmovw , VexKmov , V(000F00,90,_,0,0,_,_,_ ), V(000F00,92,_,0,0,_,_,_ ), 74 , 39 , 98 , 81 ), // #360 - INST(Knotb , VexRm , V(660F00,44,_,0,0,_,_,_ ), 0 , 71 , 0 , 99 , 76 ), // #361 - INST(Knotd , VexRm , V(660F00,44,_,0,1,_,_,_ ), 0 , 72 , 0 , 99 , 77 ), // #362 - INST(Knotq , VexRm , V(000F00,44,_,0,1,_,_,_ ), 0 , 73 , 0 , 99 , 77 ), // #363 - INST(Knotw , VexRm , V(000F00,44,_,0,0,_,_,_ ), 0 , 74 , 0 , 99 , 78 ), // #364 - INST(Korb , VexRvm , V(660F00,45,_,1,0,_,_,_ ), 0 , 67 , 0 , 94 , 76 ), // #365 - INST(Kord , VexRvm , V(660F00,45,_,1,1,_,_,_ ), 0 , 68 , 0 , 94 , 77 ), // #366 - INST(Korq , VexRvm , V(000F00,45,_,1,1,_,_,_ ), 0 , 69 , 0 , 94 , 77 ), // #367 - INST(Kortestb , VexRm , V(660F00,98,_,0,0,_,_,_ ), 0 , 71 , 0 , 99 , 82 ), // #368 - INST(Kortestd , VexRm , V(660F00,98,_,0,1,_,_,_ ), 0 , 72 , 0 , 99 , 83 ), // #369 - INST(Kortestq , VexRm , V(000F00,98,_,0,1,_,_,_ ), 0 , 73 , 0 , 99 , 83 ), // #370 - INST(Kortestw , VexRm , V(000F00,98,_,0,0,_,_,_ ), 0 , 74 , 0 , 99 , 84 ), // #371 - INST(Korw , VexRvm , V(000F00,45,_,1,0,_,_,_ ), 0 , 70 , 0 , 94 , 78 ), // #372 - INST(Kshiftlb , VexRmi , V(660F3A,32,_,0,0,_,_,_ ), 0 , 75 , 0 , 100, 76 ), // #373 - INST(Kshiftld , VexRmi , V(660F3A,33,_,0,0,_,_,_ ), 0 , 75 , 0 , 100, 77 ), // #374 - INST(Kshiftlq , VexRmi , V(660F3A,33,_,0,1,_,_,_ ), 0 , 76 , 0 , 100, 77 ), // #375 - INST(Kshiftlw , VexRmi , V(660F3A,32,_,0,1,_,_,_ ), 0 , 76 , 0 , 100, 78 ), // #376 - INST(Kshiftrb , VexRmi , V(660F3A,30,_,0,0,_,_,_ ), 0 , 75 , 0 , 100, 76 ), // #377 - INST(Kshiftrd , VexRmi , V(660F3A,31,_,0,0,_,_,_ ), 0 , 75 , 0 , 100, 77 ), // #378 - INST(Kshiftrq , VexRmi , V(660F3A,31,_,0,1,_,_,_ ), 0 , 76 , 0 , 100, 77 ), // #379 - INST(Kshiftrw , VexRmi , V(660F3A,30,_,0,1,_,_,_ ), 0 , 76 , 0 , 100, 78 ), // #380 - INST(Ktestb , VexRm , V(660F00,99,_,0,0,_,_,_ ), 0 , 71 , 0 , 99 , 82 ), // #381 - INST(Ktestd , VexRm , V(660F00,99,_,0,1,_,_,_ ), 0 , 72 , 0 , 99 , 83 ), // #382 - INST(Ktestq , VexRm , V(000F00,99,_,0,1,_,_,_ ), 0 , 73 , 0 , 99 , 83 ), // #383 - INST(Ktestw , VexRm , V(000F00,99,_,0,0,_,_,_ ), 0 , 74 , 0 , 99 , 82 ), // #384 - INST(Kunpckbw , VexRvm , V(660F00,4B,_,1,0,_,_,_ ), 0 , 67 , 0 , 94 , 78 ), // #385 - INST(Kunpckdq , VexRvm , V(000F00,4B,_,1,1,_,_,_ ), 0 , 69 , 0 , 94 , 77 ), // #386 - INST(Kunpckwd , VexRvm , V(000F00,4B,_,1,0,_,_,_ ), 0 , 70 , 0 , 94 , 77 ), // #387 - INST(Kxnorb , VexRvm , V(660F00,46,_,1,0,_,_,_ ), 0 , 67 , 0 , 101, 76 ), // #388 - INST(Kxnord , VexRvm , V(660F00,46,_,1,1,_,_,_ ), 0 , 68 , 0 , 101, 77 ), // #389 - INST(Kxnorq , VexRvm , V(000F00,46,_,1,1,_,_,_ ), 0 , 69 , 0 , 101, 77 ), // #390 - INST(Kxnorw , VexRvm , V(000F00,46,_,1,0,_,_,_ ), 0 , 70 , 0 , 101, 78 ), // #391 - INST(Kxorb , VexRvm , V(660F00,47,_,1,0,_,_,_ ), 0 , 67 , 0 , 101, 76 ), // #392 - INST(Kxord , VexRvm , V(660F00,47,_,1,1,_,_,_ ), 0 , 68 , 0 , 101, 77 ), // #393 - INST(Kxorq , VexRvm , V(000F00,47,_,1,1,_,_,_ ), 0 , 69 , 0 , 101, 77 ), // #394 - INST(Kxorw , VexRvm , V(000F00,47,_,1,0,_,_,_ ), 0 , 70 , 0 , 101, 78 ), // #395 - INST(Lahf , X86Op , O(000000,9F,_,_,_,_,_,_ ), 0 , 0 , 0 , 102, 85 ), // #396 - INST(Lar , X86Rm , O(000F00,02,_,_,_,_,_,_ ), 0 , 5 , 0 , 103, 11 ), // #397 - INST(Lcall , X86LcallLjmp , O(000000,FF,3,_,_,_,_,_ ), O(000000,9A,_,_,_,_,_,_ ), 77 , 40 , 104, 1 ), // #398 - INST(Lddqu , ExtRm , O(F20F00,F0,_,_,_,_,_,_ ), 0 , 6 , 0 , 105, 7 ), // #399 - INST(Ldmxcsr , X86M_Only , O(000F00,AE,2,_,_,_,_,_ ), 0 , 78 , 0 , 106, 6 ), // #400 - INST(Lds , X86Rm , O(000000,C5,_,_,_,_,_,_ ), 0 , 0 , 0 , 107, 0 ), // #401 - INST(Ldtilecfg , AmxCfg , V(000F38,49,_,0,0,_,_,_ ), 0 , 11 , 0 , 108, 86 ), // #402 - INST(Lea , X86Lea , O(000000,8D,_,_,x,_,_,_ ), 0 , 0 , 0 , 109, 0 ), // #403 - INST(Leave , X86Op , O(000000,C9,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 0 ), // #404 - INST(Les , X86Rm , O(000000,C4,_,_,_,_,_,_ ), 0 , 0 , 0 , 107, 0 ), // #405 - INST(Lfence , X86Fence , O(000F00,AE,5,_,_,_,_,_ ), 0 , 79 , 0 , 31 , 5 ), // #406 - INST(Lfs , X86Rm , O(000F00,B4,_,_,_,_,_,_ ), 0 , 5 , 0 , 110, 0 ), // #407 - INST(Lgdt , X86M_Only , O(000F00,01,2,_,_,_,_,_ ), 0 , 78 , 0 , 32 , 0 ), // #408 - INST(Lgs , X86Rm , O(000F00,B5,_,_,_,_,_,_ ), 0 , 5 , 0 , 110, 0 ), // #409 - INST(Lidt , X86M_Only , O(000F00,01,3,_,_,_,_,_ ), 0 , 80 , 0 , 32 , 0 ), // #410 - INST(Ljmp , X86LcallLjmp , O(000000,FF,5,_,_,_,_,_ ), O(000000,EA,_,_,_,_,_,_ ), 64 , 41 , 111, 0 ), // #411 - INST(Lldt , X86M_NoSize , O(000F00,00,2,_,_,_,_,_ ), 0 , 78 , 0 , 112, 0 ), // #412 - INST(Llwpcb , VexR_Wx , V(XOP_M9,12,0,0,x,_,_,_ ), 0 , 81 , 0 , 113, 87 ), // #413 - INST(Lmsw , X86M_NoSize , O(000F00,01,6,_,_,_,_,_ ), 0 , 82 , 0 , 112, 0 ), // #414 - INST(Lods , X86StrRm , O(000000,AC,_,_,_,_,_,_ ), 0 , 0 , 0 , 114, 88 ), // #415 - INST(Loop , X86JecxzLoop , 0 , O(000000,E2,_,_,_,_,_,_ ), 0 , 42 , 115, 0 ), // #416 - INST(Loope , X86JecxzLoop , 0 , O(000000,E1,_,_,_,_,_,_ ), 0 , 43 , 115, 71 ), // #417 - INST(Loopne , X86JecxzLoop , 0 , O(000000,E0,_,_,_,_,_,_ ), 0 , 44 , 115, 71 ), // #418 - INST(Lsl , X86Rm , O(000F00,03,_,_,_,_,_,_ ), 0 , 5 , 0 , 116, 11 ), // #419 - INST(Lss , X86Rm , O(000F00,B2,_,_,_,_,_,_ ), 0 , 5 , 0 , 110, 0 ), // #420 - INST(Ltr , X86M_NoSize , O(000F00,00,3,_,_,_,_,_ ), 0 , 80 , 0 , 112, 0 ), // #421 - INST(Lwpins , VexVmi4_Wx , V(XOP_MA,12,0,0,x,_,_,_ ), 0 , 83 , 0 , 117, 87 ), // #422 - INST(Lwpval , VexVmi4_Wx , V(XOP_MA,12,1,0,x,_,_,_ ), 0 , 84 , 0 , 117, 87 ), // #423 - INST(Lzcnt , X86Rm_Raw66H , O(F30F00,BD,_,_,x,_,_,_ ), 0 , 7 , 0 , 23 , 89 ), // #424 - INST(Maskmovdqu , ExtRm_ZDI , O(660F00,F7,_,_,_,_,_,_ ), 0 , 4 , 0 , 118, 5 ), // #425 - INST(Maskmovq , ExtRm_ZDI , O(000F00,F7,_,_,_,_,_,_ ), 0 , 5 , 0 , 119, 90 ), // #426 - INST(Maxpd , ExtRm , O(660F00,5F,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #427 - INST(Maxps , ExtRm , O(000F00,5F,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #428 - INST(Maxsd , ExtRm , O(F20F00,5F,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #429 - INST(Maxss , ExtRm , O(F30F00,5F,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #430 - INST(Mcommit , X86Op , O(F30F01,FA,_,_,_,_,_,_ ), 0 , 27 , 0 , 31 , 91 ), // #431 - INST(Mfence , X86Fence , O(000F00,AE,6,_,_,_,_,_ ), 0 , 82 , 0 , 31 , 5 ), // #432 - INST(Minpd , ExtRm , O(660F00,5D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #433 - INST(Minps , ExtRm , O(000F00,5D,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #434 - INST(Minsd , ExtRm , O(F20F00,5D,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #435 - INST(Minss , ExtRm , O(F30F00,5D,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #436 - INST(Monitor , X86Op , O(000F01,C8,_,_,_,_,_,_ ), 0 , 23 , 0 , 120, 92 ), // #437 - INST(Monitorx , X86Op , O(000F01,FA,_,_,_,_,_,_ ), 0 , 23 , 0 , 120, 93 ), // #438 - INST(Mov , X86Mov , 0 , 0 , 0 , 0 , 121, 94 ), // #439 - INST(Movabs , X86Movabs , 0 , 0 , 0 , 0 , 122, 0 ), // #440 - INST(Movapd , ExtMov , O(660F00,28,_,_,_,_,_,_ ), O(660F00,29,_,_,_,_,_,_ ), 4 , 45 , 123, 95 ), // #441 - INST(Movaps , ExtMov , O(000F00,28,_,_,_,_,_,_ ), O(000F00,29,_,_,_,_,_,_ ), 5 , 46 , 123, 96 ), // #442 - INST(Movbe , ExtMovbe , O(000F38,F0,_,_,x,_,_,_ ), O(000F38,F1,_,_,x,_,_,_ ), 1 , 47 , 124, 97 ), // #443 - INST(Movd , ExtMovd , O(000F00,6E,_,_,_,_,_,_ ), O(000F00,7E,_,_,_,_,_,_ ), 5 , 48 , 125, 98 ), // #444 - INST(Movddup , ExtMov , O(F20F00,12,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 7 ), // #445 - INST(Movdir64b , X86EnqcmdMovdir64b , O(660F38,F8,_,_,_,_,_,_ ), 0 , 2 , 0 , 126, 99 ), // #446 - INST(Movdiri , X86MovntiMovdiri , O(000F38,F9,_,_,_,_,_,_ ), 0 , 1 , 0 , 3 , 100), // #447 - INST(Movdq2q , ExtMov , O(F20F00,D6,_,_,_,_,_,_ ), 0 , 6 , 0 , 127, 5 ), // #448 - INST(Movdqa , ExtMov , O(660F00,6F,_,_,_,_,_,_ ), O(660F00,7F,_,_,_,_,_,_ ), 4 , 49 , 123, 95 ), // #449 - INST(Movdqu , ExtMov , O(F30F00,6F,_,_,_,_,_,_ ), O(F30F00,7F,_,_,_,_,_,_ ), 7 , 50 , 123, 95 ), // #450 - INST(Movhlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), 0 , 5 , 0 , 128, 6 ), // #451 - INST(Movhpd , ExtMov , O(660F00,16,_,_,_,_,_,_ ), O(660F00,17,_,_,_,_,_,_ ), 4 , 51 , 129, 5 ), // #452 - INST(Movhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), O(000F00,17,_,_,_,_,_,_ ), 5 , 52 , 129, 6 ), // #453 - INST(Movlhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), 0 , 5 , 0 , 128, 6 ), // #454 - INST(Movlpd , ExtMov , O(660F00,12,_,_,_,_,_,_ ), O(660F00,13,_,_,_,_,_,_ ), 4 , 53 , 129, 5 ), // #455 - INST(Movlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), O(000F00,13,_,_,_,_,_,_ ), 5 , 54 , 129, 6 ), // #456 - INST(Movmskpd , ExtMov , O(660F00,50,_,_,_,_,_,_ ), 0 , 4 , 0 , 130, 5 ), // #457 - INST(Movmskps , ExtMov , O(000F00,50,_,_,_,_,_,_ ), 0 , 5 , 0 , 130, 6 ), // #458 - INST(Movntdq , ExtMov , 0 , O(660F00,E7,_,_,_,_,_,_ ), 0 , 55 , 131, 5 ), // #459 - INST(Movntdqa , ExtMov , O(660F38,2A,_,_,_,_,_,_ ), 0 , 2 , 0 , 105, 13 ), // #460 - INST(Movnti , X86MovntiMovdiri , O(000F00,C3,_,_,x,_,_,_ ), 0 , 5 , 0 , 3 , 5 ), // #461 - INST(Movntpd , ExtMov , 0 , O(660F00,2B,_,_,_,_,_,_ ), 0 , 56 , 131, 5 ), // #462 - INST(Movntps , ExtMov , 0 , O(000F00,2B,_,_,_,_,_,_ ), 0 , 57 , 131, 6 ), // #463 - INST(Movntq , ExtMov , 0 , O(000F00,E7,_,_,_,_,_,_ ), 0 , 58 , 132, 90 ), // #464 - INST(Movntsd , ExtMov , 0 , O(F20F00,2B,_,_,_,_,_,_ ), 0 , 59 , 133, 51 ), // #465 - INST(Movntss , ExtMov , 0 , O(F30F00,2B,_,_,_,_,_,_ ), 0 , 60 , 134, 51 ), // #466 - INST(Movq , ExtMovq , O(000F00,6E,_,_,x,_,_,_ ), O(000F00,7E,_,_,x,_,_,_ ), 5 , 48 , 135, 101), // #467 - INST(Movq2dq , ExtRm , O(F30F00,D6,_,_,_,_,_,_ ), 0 , 7 , 0 , 136, 5 ), // #468 - INST(Movs , X86StrMm , O(000000,A4,_,_,_,_,_,_ ), 0 , 0 , 0 , 137, 88 ), // #469 - INST(Movsd , ExtMov , O(F20F00,10,_,_,_,_,_,_ ), O(F20F00,11,_,_,_,_,_,_ ), 6 , 61 , 138, 95 ), // #470 - INST(Movshdup , ExtRm , O(F30F00,16,_,_,_,_,_,_ ), 0 , 7 , 0 , 6 , 7 ), // #471 - INST(Movsldup , ExtRm , O(F30F00,12,_,_,_,_,_,_ ), 0 , 7 , 0 , 6 , 7 ), // #472 - INST(Movss , ExtMov , O(F30F00,10,_,_,_,_,_,_ ), O(F30F00,11,_,_,_,_,_,_ ), 7 , 62 , 139, 96 ), // #473 - INST(Movsx , X86MovsxMovzx , O(000F00,BE,_,_,x,_,_,_ ), 0 , 5 , 0 , 140, 0 ), // #474 - INST(Movsxd , X86Rm , O(000000,63,_,_,x,_,_,_ ), 0 , 0 , 0 , 141, 0 ), // #475 - INST(Movupd , ExtMov , O(660F00,10,_,_,_,_,_,_ ), O(660F00,11,_,_,_,_,_,_ ), 4 , 63 , 123, 95 ), // #476 - INST(Movups , ExtMov , O(000F00,10,_,_,_,_,_,_ ), O(000F00,11,_,_,_,_,_,_ ), 5 , 64 , 123, 96 ), // #477 - INST(Movzx , X86MovsxMovzx , O(000F00,B6,_,_,x,_,_,_ ), 0 , 5 , 0 , 140, 0 ), // #478 - INST(Mpsadbw , ExtRmi , O(660F3A,42,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #479 - INST(Mul , X86M_GPB_MulDiv , O(000000,F6,4,_,x,_,_,_ ), 0 , 10 , 0 , 58 , 1 ), // #480 - INST(Mulpd , ExtRm , O(660F00,59,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #481 - INST(Mulps , ExtRm , O(000F00,59,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #482 - INST(Mulsd , ExtRm , O(F20F00,59,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #483 - INST(Mulss , ExtRm , O(F30F00,59,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #484 - INST(Mulx , VexRvm_ZDX_Wx , V(F20F38,F6,_,0,x,_,_,_ ), 0 , 85 , 0 , 142, 102), // #485 - INST(Mwait , X86Op , O(000F01,C9,_,_,_,_,_,_ ), 0 , 23 , 0 , 143, 92 ), // #486 - INST(Mwaitx , X86Op , O(000F01,FB,_,_,_,_,_,_ ), 0 , 23 , 0 , 144, 93 ), // #487 - INST(Neg , X86M_GPB , O(000000,F6,3,_,x,_,_,_ ), 0 , 77 , 0 , 145, 1 ), // #488 - INST(Nop , X86M_Nop , O(000000,90,_,_,_,_,_,_ ), 0 , 0 , 0 , 146, 0 ), // #489 - INST(Not , X86M_GPB , O(000000,F6,2,_,x,_,_,_ ), 0 , 3 , 0 , 145, 0 ), // #490 - INST(Or , X86Arith , O(000000,08,1,_,x,_,_,_ ), 0 , 33 , 0 , 147, 1 ), // #491 - INST(Orpd , ExtRm , O(660F00,56,_,_,_,_,_,_ ), 0 , 4 , 0 , 12 , 5 ), // #492 - INST(Orps , ExtRm , O(000F00,56,_,_,_,_,_,_ ), 0 , 5 , 0 , 12 , 6 ), // #493 - INST(Out , X86Out , O(000000,EE,_,_,_,_,_,_ ), O(000000,E6,_,_,_,_,_,_ ), 0 , 65 , 148, 0 ), // #494 - INST(Outs , X86Outs , O(000000,6E,_,_,_,_,_,_ ), 0 , 0 , 0 , 149, 0 ), // #495 - INST(Pabsb , ExtRm_P , O(000F38,1C,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #496 - INST(Pabsd , ExtRm_P , O(000F38,1E,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #497 - INST(Pabsw , ExtRm_P , O(000F38,1D,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #498 - INST(Packssdw , ExtRm_P , O(000F00,6B,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #499 - INST(Packsswb , ExtRm_P , O(000F00,63,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #500 - INST(Packusdw , ExtRm , O(660F38,2B,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 13 ), // #501 - INST(Packuswb , ExtRm_P , O(000F00,67,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #502 - INST(Paddb , ExtRm_P , O(000F00,FC,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #503 - INST(Paddd , ExtRm_P , O(000F00,FE,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #504 - INST(Paddq , ExtRm_P , O(000F00,D4,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 5 ), // #505 - INST(Paddsb , ExtRm_P , O(000F00,EC,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #506 - INST(Paddsw , ExtRm_P , O(000F00,ED,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #507 - INST(Paddusb , ExtRm_P , O(000F00,DC,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #508 - INST(Paddusw , ExtRm_P , O(000F00,DD,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #509 - INST(Paddw , ExtRm_P , O(000F00,FD,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #510 - INST(Palignr , ExtRmi_P , O(000F3A,0F,_,_,_,_,_,_ ), 0 , 86 , 0 , 151, 103), // #511 - INST(Pand , ExtRm_P , O(000F00,DB,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 98 ), // #512 - INST(Pandn , ExtRm_P , O(000F00,DF,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #513 - INST(Pause , X86Op , O(F30000,90,_,_,_,_,_,_ ), 0 , 87 , 0 , 31 , 0 ), // #514 - INST(Pavgb , ExtRm_P , O(000F00,E0,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 104), // #515 - INST(Pavgusb , Ext3dNow , O(000F0F,BF,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #516 - INST(Pavgw , ExtRm_P , O(000F00,E3,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 104), // #517 - INST(Pblendvb , ExtRm_XMM0 , O(660F38,10,_,_,_,_,_,_ ), 0 , 2 , 0 , 16 , 13 ), // #518 - INST(Pblendw , ExtRmi , O(660F3A,0E,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #519 - INST(Pclmulqdq , ExtRmi , O(660F3A,44,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 105), // #520 - INST(Pcmpeqb , ExtRm_P , O(000F00,74,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #521 - INST(Pcmpeqd , ExtRm_P , O(000F00,76,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #522 - INST(Pcmpeqq , ExtRm , O(660F38,29,_,_,_,_,_,_ ), 0 , 2 , 0 , 155, 13 ), // #523 - INST(Pcmpeqw , ExtRm_P , O(000F00,75,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #524 - INST(Pcmpestri , ExtRmi , O(660F3A,61,_,_,_,_,_,_ ), 0 , 9 , 0 , 156, 106), // #525 - INST(Pcmpestrm , ExtRmi , O(660F3A,60,_,_,_,_,_,_ ), 0 , 9 , 0 , 157, 106), // #526 - INST(Pcmpgtb , ExtRm_P , O(000F00,64,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #527 - INST(Pcmpgtd , ExtRm_P , O(000F00,66,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #528 - INST(Pcmpgtq , ExtRm , O(660F38,37,_,_,_,_,_,_ ), 0 , 2 , 0 , 155, 46 ), // #529 - INST(Pcmpgtw , ExtRm_P , O(000F00,65,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #530 - INST(Pcmpistri , ExtRmi , O(660F3A,63,_,_,_,_,_,_ ), 0 , 9 , 0 , 158, 106), // #531 - INST(Pcmpistrm , ExtRmi , O(660F3A,62,_,_,_,_,_,_ ), 0 , 9 , 0 , 159, 106), // #532 - INST(Pconfig , X86Op , O(000F01,C5,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 107), // #533 - INST(Pdep , VexRvm_Wx , V(F20F38,F5,_,0,x,_,_,_ ), 0 , 85 , 0 , 11 , 102), // #534 - INST(Pext , VexRvm_Wx , V(F30F38,F5,_,0,x,_,_,_ ), 0 , 89 , 0 , 11 , 102), // #535 - INST(Pextrb , ExtExtract , O(000F3A,14,_,_,_,_,_,_ ), 0 , 86 , 0 , 160, 13 ), // #536 - INST(Pextrd , ExtExtract , O(000F3A,16,_,_,_,_,_,_ ), 0 , 86 , 0 , 62 , 13 ), // #537 - INST(Pextrq , ExtExtract , O(000F3A,16,_,_,1,_,_,_ ), 0 , 90 , 0 , 161, 13 ), // #538 - INST(Pextrw , ExtPextrw , O(000F00,C5,_,_,_,_,_,_ ), O(000F3A,15,_,_,_,_,_,_ ), 5 , 66 , 162, 108), // #539 - INST(Pf2id , Ext3dNow , O(000F0F,1D,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #540 - INST(Pf2iw , Ext3dNow , O(000F0F,1C,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 109), // #541 - INST(Pfacc , Ext3dNow , O(000F0F,AE,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #542 - INST(Pfadd , Ext3dNow , O(000F0F,9E,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #543 - INST(Pfcmpeq , Ext3dNow , O(000F0F,B0,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #544 - INST(Pfcmpge , Ext3dNow , O(000F0F,90,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #545 - INST(Pfcmpgt , Ext3dNow , O(000F0F,A0,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #546 - INST(Pfmax , Ext3dNow , O(000F0F,A4,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #547 - INST(Pfmin , Ext3dNow , O(000F0F,94,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #548 - INST(Pfmul , Ext3dNow , O(000F0F,B4,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #549 - INST(Pfnacc , Ext3dNow , O(000F0F,8A,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 109), // #550 - INST(Pfpnacc , Ext3dNow , O(000F0F,8E,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 109), // #551 - INST(Pfrcp , Ext3dNow , O(000F0F,96,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #552 - INST(Pfrcpit1 , Ext3dNow , O(000F0F,A6,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #553 - INST(Pfrcpit2 , Ext3dNow , O(000F0F,B6,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #554 - INST(Pfrcpv , Ext3dNow , O(000F0F,86,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 110), // #555 - INST(Pfrsqit1 , Ext3dNow , O(000F0F,A7,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #556 - INST(Pfrsqrt , Ext3dNow , O(000F0F,97,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #557 - INST(Pfrsqrtv , Ext3dNow , O(000F0F,87,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 110), // #558 - INST(Pfsub , Ext3dNow , O(000F0F,9A,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #559 - INST(Pfsubr , Ext3dNow , O(000F0F,AA,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #560 - INST(Phaddd , ExtRm_P , O(000F38,02,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #561 - INST(Phaddsw , ExtRm_P , O(000F38,03,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #562 - INST(Phaddw , ExtRm_P , O(000F38,01,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #563 - INST(Phminposuw , ExtRm , O(660F38,41,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 13 ), // #564 - INST(Phsubd , ExtRm_P , O(000F38,06,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #565 - INST(Phsubsw , ExtRm_P , O(000F38,07,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #566 - INST(Phsubw , ExtRm_P , O(000F38,05,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #567 - INST(Pi2fd , Ext3dNow , O(000F0F,0D,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #568 - INST(Pi2fw , Ext3dNow , O(000F0F,0C,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 109), // #569 - INST(Pinsrb , ExtRmi , O(660F3A,20,_,_,_,_,_,_ ), 0 , 9 , 0 , 163, 13 ), // #570 - INST(Pinsrd , ExtRmi , O(660F3A,22,_,_,_,_,_,_ ), 0 , 9 , 0 , 164, 13 ), // #571 - INST(Pinsrq , ExtRmi , O(660F3A,22,_,_,1,_,_,_ ), 0 , 91 , 0 , 165, 13 ), // #572 - INST(Pinsrw , ExtRmi_P , O(000F00,C4,_,_,_,_,_,_ ), 0 , 5 , 0 , 166, 104), // #573 - INST(Pmaddubsw , ExtRm_P , O(000F38,04,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #574 - INST(Pmaddwd , ExtRm_P , O(000F00,F5,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #575 - INST(Pmaxsb , ExtRm , O(660F38,3C,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #576 - INST(Pmaxsd , ExtRm , O(660F38,3D,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #577 - INST(Pmaxsw , ExtRm_P , O(000F00,EE,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 104), // #578 - INST(Pmaxub , ExtRm_P , O(000F00,DE,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 104), // #579 - INST(Pmaxud , ExtRm , O(660F38,3F,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #580 - INST(Pmaxuw , ExtRm , O(660F38,3E,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #581 - INST(Pminsb , ExtRm , O(660F38,38,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #582 - INST(Pminsd , ExtRm , O(660F38,39,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #583 - INST(Pminsw , ExtRm_P , O(000F00,EA,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 104), // #584 - INST(Pminub , ExtRm_P , O(000F00,DA,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 104), // #585 - INST(Pminud , ExtRm , O(660F38,3B,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #586 - INST(Pminuw , ExtRm , O(660F38,3A,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #587 - INST(Pmovmskb , ExtRm_P , O(000F00,D7,_,_,_,_,_,_ ), 0 , 5 , 0 , 167, 104), // #588 - INST(Pmovsxbd , ExtRm , O(660F38,21,_,_,_,_,_,_ ), 0 , 2 , 0 , 8 , 13 ), // #589 - INST(Pmovsxbq , ExtRm , O(660F38,22,_,_,_,_,_,_ ), 0 , 2 , 0 , 168, 13 ), // #590 - INST(Pmovsxbw , ExtRm , O(660F38,20,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #591 - INST(Pmovsxdq , ExtRm , O(660F38,25,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #592 - INST(Pmovsxwd , ExtRm , O(660F38,23,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #593 - INST(Pmovsxwq , ExtRm , O(660F38,24,_,_,_,_,_,_ ), 0 , 2 , 0 , 8 , 13 ), // #594 - INST(Pmovzxbd , ExtRm , O(660F38,31,_,_,_,_,_,_ ), 0 , 2 , 0 , 8 , 13 ), // #595 - INST(Pmovzxbq , ExtRm , O(660F38,32,_,_,_,_,_,_ ), 0 , 2 , 0 , 168, 13 ), // #596 - INST(Pmovzxbw , ExtRm , O(660F38,30,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #597 - INST(Pmovzxdq , ExtRm , O(660F38,35,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #598 - INST(Pmovzxwd , ExtRm , O(660F38,33,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #599 - INST(Pmovzxwq , ExtRm , O(660F38,34,_,_,_,_,_,_ ), 0 , 2 , 0 , 8 , 13 ), // #600 - INST(Pmuldq , ExtRm , O(660F38,28,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 13 ), // #601 - INST(Pmulhrsw , ExtRm_P , O(000F38,0B,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #602 - INST(Pmulhrw , Ext3dNow , O(000F0F,B7,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #603 - INST(Pmulhuw , ExtRm_P , O(000F00,E4,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 104), // #604 - INST(Pmulhw , ExtRm_P , O(000F00,E5,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #605 - INST(Pmulld , ExtRm , O(660F38,40,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 13 ), // #606 - INST(Pmullw , ExtRm_P , O(000F00,D5,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #607 - INST(Pmuludq , ExtRm_P , O(000F00,F4,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 5 ), // #608 - INST(Pop , X86Pop , O(000000,8F,0,_,_,_,_,_ ), O(000000,58,_,_,_,_,_,_ ), 0 , 67 , 169, 0 ), // #609 - INST(Popa , X86Op , O(660000,61,_,_,_,_,_,_ ), 0 , 21 , 0 , 85 , 0 ), // #610 - INST(Popad , X86Op , O(000000,61,_,_,_,_,_,_ ), 0 , 0 , 0 , 85 , 0 ), // #611 - INST(Popcnt , X86Rm_Raw66H , O(F30F00,B8,_,_,x,_,_,_ ), 0 , 7 , 0 , 23 , 111), // #612 - INST(Popf , X86Op , O(660000,9D,_,_,_,_,_,_ ), 0 , 21 , 0 , 31 , 112), // #613 - INST(Popfd , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 85 , 112), // #614 - INST(Popfq , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 34 , 112), // #615 - INST(Por , ExtRm_P , O(000F00,EB,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 98 ), // #616 - INST(Prefetch , X86M_Only , O(000F00,0D,0,_,_,_,_,_ ), 0 , 5 , 0 , 32 , 58 ), // #617 - INST(Prefetchit0 , X86M_Only , O(000F00,18,7,_,_,_,_,_ ), 0 , 24 , 0 , 75 , 113), // #618 - INST(Prefetchit1 , X86M_Only , O(000F00,18,6,_,_,_,_,_ ), 0 , 82 , 0 , 75 , 113), // #619 - INST(Prefetchnta , X86M_Only , O(000F00,18,0,_,_,_,_,_ ), 0 , 5 , 0 , 32 , 6 ), // #620 - INST(Prefetcht0 , X86M_Only , O(000F00,18,1,_,_,_,_,_ ), 0 , 32 , 0 , 32 , 6 ), // #621 - INST(Prefetcht1 , X86M_Only , O(000F00,18,2,_,_,_,_,_ ), 0 , 78 , 0 , 32 , 6 ), // #622 - INST(Prefetcht2 , X86M_Only , O(000F00,18,3,_,_,_,_,_ ), 0 , 80 , 0 , 32 , 6 ), // #623 - INST(Prefetchw , X86M_Only , O(000F00,0D,1,_,_,_,_,_ ), 0 , 32 , 0 , 32 , 114), // #624 - INST(Prefetchwt1 , X86M_Only , O(000F00,0D,2,_,_,_,_,_ ), 0 , 78 , 0 , 32 , 115), // #625 - INST(Psadbw , ExtRm_P , O(000F00,F6,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 104), // #626 - INST(Pshufb , ExtRm_P , O(000F38,00,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #627 - INST(Pshufd , ExtRmi , O(660F00,70,_,_,_,_,_,_ ), 0 , 4 , 0 , 9 , 5 ), // #628 - INST(Pshufhw , ExtRmi , O(F30F00,70,_,_,_,_,_,_ ), 0 , 7 , 0 , 9 , 5 ), // #629 - INST(Pshuflw , ExtRmi , O(F20F00,70,_,_,_,_,_,_ ), 0 , 6 , 0 , 9 , 5 ), // #630 - INST(Pshufw , ExtRmi_P , O(000F00,70,_,_,_,_,_,_ ), 0 , 5 , 0 , 170, 90 ), // #631 - INST(Psignb , ExtRm_P , O(000F38,08,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #632 - INST(Psignd , ExtRm_P , O(000F38,0A,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #633 - INST(Psignw , ExtRm_P , O(000F38,09,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #634 - INST(Pslld , ExtRmRi_P , O(000F00,F2,_,_,_,_,_,_ ), O(000F00,72,6,_,_,_,_,_ ), 5 , 68 , 171, 98 ), // #635 - INST(Pslldq , ExtRmRi , 0 , O(660F00,73,7,_,_,_,_,_ ), 0 , 69 , 172, 5 ), // #636 - INST(Psllq , ExtRmRi_P , O(000F00,F3,_,_,_,_,_,_ ), O(000F00,73,6,_,_,_,_,_ ), 5 , 70 , 171, 98 ), // #637 - INST(Psllw , ExtRmRi_P , O(000F00,F1,_,_,_,_,_,_ ), O(000F00,71,6,_,_,_,_,_ ), 5 , 71 , 171, 98 ), // #638 - INST(Psmash , X86Op , O(F30F01,FF,_,_,_,_,_,_ ), 0 , 27 , 0 , 34 , 116), // #639 - INST(Psrad , ExtRmRi_P , O(000F00,E2,_,_,_,_,_,_ ), O(000F00,72,4,_,_,_,_,_ ), 5 , 72 , 171, 98 ), // #640 - INST(Psraw , ExtRmRi_P , O(000F00,E1,_,_,_,_,_,_ ), O(000F00,71,4,_,_,_,_,_ ), 5 , 73 , 171, 98 ), // #641 - INST(Psrld , ExtRmRi_P , O(000F00,D2,_,_,_,_,_,_ ), O(000F00,72,2,_,_,_,_,_ ), 5 , 74 , 171, 98 ), // #642 - INST(Psrldq , ExtRmRi , 0 , O(660F00,73,3,_,_,_,_,_ ), 0 , 75 , 172, 5 ), // #643 - INST(Psrlq , ExtRmRi_P , O(000F00,D3,_,_,_,_,_,_ ), O(000F00,73,2,_,_,_,_,_ ), 5 , 76 , 171, 98 ), // #644 - INST(Psrlw , ExtRmRi_P , O(000F00,D1,_,_,_,_,_,_ ), O(000F00,71,2,_,_,_,_,_ ), 5 , 77 , 171, 98 ), // #645 - INST(Psubb , ExtRm_P , O(000F00,F8,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #646 - INST(Psubd , ExtRm_P , O(000F00,FA,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #647 - INST(Psubq , ExtRm_P , O(000F00,FB,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 5 ), // #648 - INST(Psubsb , ExtRm_P , O(000F00,E8,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #649 - INST(Psubsw , ExtRm_P , O(000F00,E9,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #650 - INST(Psubusb , ExtRm_P , O(000F00,D8,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #651 - INST(Psubusw , ExtRm_P , O(000F00,D9,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #652 - INST(Psubw , ExtRm_P , O(000F00,F9,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #653 - INST(Pswapd , Ext3dNow , O(000F0F,BB,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 109), // #654 - INST(Ptest , ExtRm , O(660F38,17,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 117), // #655 - INST(Ptwrite , X86M , O(F30F00,AE,4,_,_,_,_,_ ), 0 , 92 , 0 , 173, 118), // #656 - INST(Punpckhbw , ExtRm_P , O(000F00,68,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #657 - INST(Punpckhdq , ExtRm_P , O(000F00,6A,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #658 - INST(Punpckhqdq , ExtRm , O(660F00,6D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #659 - INST(Punpckhwd , ExtRm_P , O(000F00,69,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #660 - INST(Punpcklbw , ExtRm_P , O(000F00,60,_,_,_,_,_,_ ), 0 , 5 , 0 , 174, 98 ), // #661 - INST(Punpckldq , ExtRm_P , O(000F00,62,_,_,_,_,_,_ ), 0 , 5 , 0 , 174, 98 ), // #662 - INST(Punpcklqdq , ExtRm , O(660F00,6C,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #663 - INST(Punpcklwd , ExtRm_P , O(000F00,61,_,_,_,_,_,_ ), 0 , 5 , 0 , 174, 98 ), // #664 - INST(Push , X86Push , O(000000,FF,6,_,_,_,_,_ ), O(000000,50,_,_,_,_,_,_ ), 34 , 78 , 175, 0 ), // #665 - INST(Pusha , X86Op , O(660000,60,_,_,_,_,_,_ ), 0 , 21 , 0 , 85 , 0 ), // #666 - INST(Pushad , X86Op , O(000000,60,_,_,_,_,_,_ ), 0 , 0 , 0 , 85 , 0 ), // #667 - INST(Pushf , X86Op , O(660000,9C,_,_,_,_,_,_ ), 0 , 21 , 0 , 31 , 119), // #668 - INST(Pushfd , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 85 , 119), // #669 - INST(Pushfq , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 34 , 119), // #670 - INST(Pushw , X86Pushw , O(000000,FF,6,_,_,_,_,_ ), O(000000,50,_,_,_,_,_,_ ), 34 , 78 , 176, 0 ), // #671 - INST(Pvalidate , X86Op , O(F20F01,FF,_,_,_,_,_,_ ), 0 , 93 , 0 , 31 , 120), // #672 - INST(Pxor , ExtRm_P , O(000F00,EF,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #673 - INST(Rcl , X86Rot , O(000000,D0,2,_,x,_,_,_ ), 0 , 3 , 0 , 177, 121), // #674 - INST(Rcpps , ExtRm , O(000F00,53,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #675 - INST(Rcpss , ExtRm , O(F30F00,53,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #676 - INST(Rcr , X86Rot , O(000000,D0,3,_,x,_,_,_ ), 0 , 77 , 0 , 177, 121), // #677 - INST(Rdfsbase , X86M , O(F30F00,AE,0,_,x,_,_,_ ), 0 , 7 , 0 , 178, 122), // #678 - INST(Rdgsbase , X86M , O(F30F00,AE,1,_,x,_,_,_ ), 0 , 94 , 0 , 178, 122), // #679 - INST(Rdmsr , X86Op , O(000F00,32,_,_,_,_,_,_ ), 0 , 5 , 0 , 179, 123), // #680 - INST(Rdpid , X86R_Native , O(F30F00,C7,7,_,_,_,_,_ ), 0 , 95 , 0 , 180, 124), // #681 - INST(Rdpkru , X86Op , O(000F01,EE,_,_,_,_,_,_ ), 0 , 23 , 0 , 179, 125), // #682 - INST(Rdpmc , X86Op , O(000F00,33,_,_,_,_,_,_ ), 0 , 5 , 0 , 179, 0 ), // #683 - INST(Rdpru , X86Op , O(000F01,FD,_,_,_,_,_,_ ), 0 , 23 , 0 , 179, 126), // #684 - INST(Rdrand , X86M , O(000F00,C7,6,_,x,_,_,_ ), 0 , 82 , 0 , 24 , 127), // #685 - INST(Rdseed , X86M , O(000F00,C7,7,_,x,_,_,_ ), 0 , 24 , 0 , 24 , 128), // #686 - INST(Rdsspd , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 94 , 0 , 80 , 65 ), // #687 - INST(Rdsspq , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 94 , 0 , 81 , 65 ), // #688 - INST(Rdtsc , X86Op , O(000F00,31,_,_,_,_,_,_ ), 0 , 5 , 0 , 29 , 129), // #689 - INST(Rdtscp , X86Op , O(000F01,F9,_,_,_,_,_,_ ), 0 , 23 , 0 , 179, 130), // #690 - INST(Ret , X86Ret , O(000000,C2,_,_,_,_,_,_ ), 0 , 0 , 0 , 181, 0 ), // #691 - INST(Retf , X86Ret , O(000000,CA,_,_,x,_,_,_ ), 0 , 0 , 0 , 182, 0 ), // #692 - INST(Rmpadjust , X86Op , O(F30F01,FE,_,_,_,_,_,_ ), 0 , 27 , 0 , 34 , 116), // #693 - INST(Rmpupdate , X86Op , O(F20F01,FE,_,_,_,_,_,_ ), 0 , 93 , 0 , 34 , 116), // #694 - INST(Rol , X86Rot , O(000000,D0,0,_,x,_,_,_ ), 0 , 0 , 0 , 177, 131), // #695 - INST(Ror , X86Rot , O(000000,D0,1,_,x,_,_,_ ), 0 , 33 , 0 , 177, 131), // #696 - INST(Rorx , VexRmi_Wx , V(F20F3A,F0,_,0,x,_,_,_ ), 0 , 96 , 0 , 183, 102), // #697 - INST(Roundpd , ExtRmi , O(660F3A,09,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #698 - INST(Roundps , ExtRmi , O(660F3A,08,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #699 - INST(Roundsd , ExtRmi , O(660F3A,0B,_,_,_,_,_,_ ), 0 , 9 , 0 , 39 , 13 ), // #700 - INST(Roundss , ExtRmi , O(660F3A,0A,_,_,_,_,_,_ ), 0 , 9 , 0 , 40 , 13 ), // #701 - INST(Rsm , X86Op , O(000F00,AA,_,_,_,_,_,_ ), 0 , 5 , 0 , 85 , 1 ), // #702 - INST(Rsqrtps , ExtRm , O(000F00,52,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #703 - INST(Rsqrtss , ExtRm , O(F30F00,52,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #704 - INST(Rstorssp , X86M_Only , O(F30F00,01,5,_,_,_,_,_ ), 0 , 65 , 0 , 33 , 25 ), // #705 - INST(Sahf , X86Op , O(000000,9E,_,_,_,_,_,_ ), 0 , 0 , 0 , 102, 132), // #706 - INST(Sal , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 10 , 0 , 177, 1 ), // #707 - INST(Sar , X86Rot , O(000000,D0,7,_,x,_,_,_ ), 0 , 29 , 0 , 177, 1 ), // #708 - INST(Sarx , VexRmv_Wx , V(F30F38,F7,_,0,x,_,_,_ ), 0 , 89 , 0 , 14 , 102), // #709 - INST(Saveprevssp , X86Op , O(F30F01,EA,_,_,_,_,_,_ ), 0 , 27 , 0 , 31 , 25 ), // #710 - INST(Sbb , X86Arith , O(000000,18,3,_,x,_,_,_ ), 0 , 77 , 0 , 184, 3 ), // #711 - INST(Scas , X86StrRm , O(000000,AE,_,_,_,_,_,_ ), 0 , 0 , 0 , 185, 39 ), // #712 - INST(Seamcall , X86Op , O(660F01,CF,_,_,_,_,_,_ ), 0 , 97 , 0 , 31 , 133), // #713 - INST(Seamops , X86Op , O(660F01,CE,_,_,_,_,_,_ ), 0 , 97 , 0 , 31 , 133), // #714 - INST(Seamret , X86Op , O(660F01,CD,_,_,_,_,_,_ ), 0 , 97 , 0 , 31 , 133), // #715 - INST(Senduipi , X86M_NoSize , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 26 , 0 , 81 , 26 ), // #716 - INST(Serialize , X86Op , O(000F01,E8,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 134), // #717 - INST(Seta , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 69 ), // #718 - INST(Setae , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 70 ), // #719 - INST(Setb , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 70 ), // #720 - INST(Setbe , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 69 ), // #721 - INST(Setc , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 70 ), // #722 - INST(Sete , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 71 ), // #723 - INST(Setg , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 72 ), // #724 - INST(Setge , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 73 ), // #725 - INST(Setl , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 73 ), // #726 - INST(Setle , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 72 ), // #727 - INST(Setna , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 69 ), // #728 - INST(Setnae , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 70 ), // #729 - INST(Setnb , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 70 ), // #730 - INST(Setnbe , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 69 ), // #731 - INST(Setnc , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 70 ), // #732 - INST(Setne , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 71 ), // #733 - INST(Setng , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 72 ), // #734 - INST(Setnge , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 73 ), // #735 - INST(Setnl , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 73 ), // #736 - INST(Setnle , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 72 ), // #737 - INST(Setno , X86Set , O(000F00,91,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 66 ), // #738 - INST(Setnp , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 74 ), // #739 - INST(Setns , X86Set , O(000F00,99,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 75 ), // #740 - INST(Setnz , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 71 ), // #741 - INST(Seto , X86Set , O(000F00,90,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 66 ), // #742 - INST(Setp , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 74 ), // #743 - INST(Setpe , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 74 ), // #744 - INST(Setpo , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 74 ), // #745 - INST(Sets , X86Set , O(000F00,98,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 75 ), // #746 - INST(Setssbsy , X86Op , O(F30F01,E8,_,_,_,_,_,_ ), 0 , 27 , 0 , 31 , 65 ), // #747 - INST(Setz , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 5 , 0 , 186, 71 ), // #748 - INST(Sfence , X86Fence , O(000F00,AE,7,_,_,_,_,_ ), 0 , 24 , 0 , 31 , 6 ), // #749 - INST(Sgdt , X86M_Only , O(000F00,01,0,_,_,_,_,_ ), 0 , 5 , 0 , 32 , 0 ), // #750 - INST(Sha1msg1 , ExtRm , O(000F38,C9,_,_,_,_,_,_ ), 0 , 1 , 0 , 6 , 135), // #751 - INST(Sha1msg2 , ExtRm , O(000F38,CA,_,_,_,_,_,_ ), 0 , 1 , 0 , 6 , 135), // #752 - INST(Sha1nexte , ExtRm , O(000F38,C8,_,_,_,_,_,_ ), 0 , 1 , 0 , 6 , 135), // #753 - INST(Sha1rnds4 , ExtRmi , O(000F3A,CC,_,_,_,_,_,_ ), 0 , 86 , 0 , 9 , 135), // #754 - INST(Sha256msg1 , ExtRm , O(000F38,CC,_,_,_,_,_,_ ), 0 , 1 , 0 , 6 , 135), // #755 - INST(Sha256msg2 , ExtRm , O(000F38,CD,_,_,_,_,_,_ ), 0 , 1 , 0 , 6 , 135), // #756 - INST(Sha256rnds2 , ExtRm_XMM0 , O(000F38,CB,_,_,_,_,_,_ ), 0 , 1 , 0 , 16 , 135), // #757 - INST(Shl , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 10 , 0 , 177, 1 ), // #758 - INST(Shld , X86ShldShrd , O(000F00,A4,_,_,x,_,_,_ ), 0 , 5 , 0 , 187, 1 ), // #759 - INST(Shlx , VexRmv_Wx , V(660F38,F7,_,0,x,_,_,_ ), 0 , 30 , 0 , 14 , 102), // #760 - INST(Shr , X86Rot , O(000000,D0,5,_,x,_,_,_ ), 0 , 64 , 0 , 177, 1 ), // #761 - INST(Shrd , X86ShldShrd , O(000F00,AC,_,_,x,_,_,_ ), 0 , 5 , 0 , 187, 1 ), // #762 - INST(Shrx , VexRmv_Wx , V(F20F38,F7,_,0,x,_,_,_ ), 0 , 85 , 0 , 14 , 102), // #763 - INST(Shufpd , ExtRmi , O(660F00,C6,_,_,_,_,_,_ ), 0 , 4 , 0 , 9 , 5 ), // #764 - INST(Shufps , ExtRmi , O(000F00,C6,_,_,_,_,_,_ ), 0 , 5 , 0 , 9 , 6 ), // #765 - INST(Sidt , X86M_Only , O(000F00,01,1,_,_,_,_,_ ), 0 , 32 , 0 , 32 , 0 ), // #766 - INST(Skinit , X86Op_xAX , O(000F01,DE,_,_,_,_,_,_ ), 0 , 23 , 0 , 56 , 136), // #767 - INST(Sldt , X86M_NoMemSize , O(000F00,00,0,_,_,_,_,_ ), 0 , 5 , 0 , 188, 0 ), // #768 - INST(Slwpcb , VexR_Wx , V(XOP_M9,12,1,0,x,_,_,_ ), 0 , 13 , 0 , 113, 87 ), // #769 - INST(Smsw , X86M_NoMemSize , O(000F00,01,4,_,_,_,_,_ ), 0 , 98 , 0 , 188, 0 ), // #770 - INST(Sqrtpd , ExtRm , O(660F00,51,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #771 - INST(Sqrtps , ExtRm , O(000F00,51,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #772 - INST(Sqrtsd , ExtRm , O(F20F00,51,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #773 - INST(Sqrtss , ExtRm , O(F30F00,51,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #774 - INST(Stac , X86Op , O(000F01,CB,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 17 ), // #775 - INST(Stc , X86Op , O(000000,F9,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 18 ), // #776 - INST(Std , X86Op , O(000000,FD,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 19 ), // #777 - INST(Stgi , X86Op , O(000F01,DC,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 136), // #778 - INST(Sti , X86Op , O(000000,FB,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 24 ), // #779 - INST(Stmxcsr , X86M_Only , O(000F00,AE,3,_,_,_,_,_ ), 0 , 80 , 0 , 106, 6 ), // #780 - INST(Stos , X86StrMr , O(000000,AA,_,_,_,_,_,_ ), 0 , 0 , 0 , 189, 88 ), // #781 - INST(Str , X86M_NoMemSize , O(000F00,00,1,_,_,_,_,_ ), 0 , 32 , 0 , 188, 0 ), // #782 - INST(Sttilecfg , AmxCfg , V(660F38,49,_,0,0,_,_,_ ), 0 , 30 , 0 , 108, 86 ), // #783 - INST(Stui , X86Op , O(F30F01,EF,_,_,_,_,_,_ ), 0 , 27 , 0 , 34 , 26 ), // #784 - INST(Sub , X86Arith , O(000000,28,5,_,x,_,_,_ ), 0 , 64 , 0 , 184, 1 ), // #785 - INST(Subpd , ExtRm , O(660F00,5C,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #786 - INST(Subps , ExtRm , O(000F00,5C,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #787 - INST(Subsd , ExtRm , O(F20F00,5C,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #788 - INST(Subss , ExtRm , O(F30F00,5C,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #789 - INST(Swapgs , X86Op , O(000F01,F8,_,_,_,_,_,_ ), 0 , 23 , 0 , 34 , 0 ), // #790 - INST(Syscall , X86Op , O(000F00,05,_,_,_,_,_,_ ), 0 , 5 , 0 , 34 , 0 ), // #791 - INST(Sysenter , X86Op , O(000F00,34,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 0 ), // #792 - INST(Sysexit , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 0 ), // #793 - INST(Sysexitq , X86Op , O(000F00,35,_,_,1,_,_,_ ), 0 , 62 , 0 , 34 , 0 ), // #794 - INST(Sysret , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 5 , 0 , 34 , 0 ), // #795 - INST(Sysretq , X86Op , O(000F00,07,_,_,1,_,_,_ ), 0 , 62 , 0 , 34 , 0 ), // #796 - INST(T1mskc , VexVm_Wx , V(XOP_M9,01,7,0,x,_,_,_ ), 0 , 99 , 0 , 15 , 12 ), // #797 - INST(Tcmmimfp16ps , AmxRmv , V(660F38,6C,_,0,0,_,_,_ ), 0 , 30 , 0 , 190, 137), // #798 - INST(Tcmmrlfp16ps , AmxRmv , V(000F38,6C,_,0,0,_,_,_ ), 0 , 11 , 0 , 190, 137), // #799 - INST(Tdcall , X86Op , O(660F01,CC,_,_,_,_,_,_ ), 0 , 97 , 0 , 31 , 133), // #800 - INST(Tdpbf16ps , AmxRmv , V(F30F38,5C,_,0,0,_,_,_ ), 0 , 89 , 0 , 190, 138), // #801 - INST(Tdpbssd , AmxRmv , V(F20F38,5E,_,0,0,_,_,_ ), 0 , 85 , 0 , 190, 139), // #802 - INST(Tdpbsud , AmxRmv , V(F30F38,5E,_,0,0,_,_,_ ), 0 , 89 , 0 , 190, 139), // #803 - INST(Tdpbusd , AmxRmv , V(660F38,5E,_,0,0,_,_,_ ), 0 , 30 , 0 , 190, 139), // #804 - INST(Tdpbuud , AmxRmv , V(000F38,5E,_,0,0,_,_,_ ), 0 , 11 , 0 , 190, 139), // #805 - INST(Tdpfp16ps , AmxRmv , V(F20F38,5C,_,0,0,_,_,_ ), 0 , 85 , 0 , 190, 140), // #806 - INST(Test , X86Test , O(000000,84,_,_,x,_,_,_ ), O(000000,F6,_,_,x,_,_,_ ), 0 , 79 , 191, 1 ), // #807 - INST(Testui , X86Op , O(F30F01,ED,_,_,_,_,_,_ ), 0 , 27 , 0 , 34 , 141), // #808 - INST(Tileloadd , AmxRm , V(F20F38,4B,_,0,0,_,_,_ ), 0 , 85 , 0 , 192, 86 ), // #809 - INST(Tileloaddt1 , AmxRm , V(660F38,4B,_,0,0,_,_,_ ), 0 , 30 , 0 , 192, 86 ), // #810 - INST(Tilerelease , VexOpMod , V(000F38,49,0,0,0,_,_,_ ), 0 , 11 , 0 , 193, 86 ), // #811 - INST(Tilestored , AmxMr , V(F30F38,4B,_,0,0,_,_,_ ), 0 , 89 , 0 , 194, 86 ), // #812 - INST(Tilezero , AmxR , V(F20F38,49,_,0,0,_,_,_ ), 0 , 85 , 0 , 195, 86 ), // #813 - INST(Tlbsync , X86Op , O(000F01,FF,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 68 ), // #814 - INST(Tpause , X86R32_EDX_EAX , O(660F00,AE,6,_,_,_,_,_ ), 0 , 28 , 0 , 196, 142), // #815 - INST(Tzcnt , X86Rm_Raw66H , O(F30F00,BC,_,_,x,_,_,_ ), 0 , 7 , 0 , 23 , 10 ), // #816 - INST(Tzmsk , VexVm_Wx , V(XOP_M9,01,4,0,x,_,_,_ ), 0 , 100, 0 , 15 , 12 ), // #817 - INST(Ucomisd , ExtRm , O(660F00,2E,_,_,_,_,_,_ ), 0 , 4 , 0 , 7 , 43 ), // #818 - INST(Ucomiss , ExtRm , O(000F00,2E,_,_,_,_,_,_ ), 0 , 5 , 0 , 8 , 44 ), // #819 - INST(Ud0 , X86Rm , O(000F00,FF,_,_,_,_,_,_ ), 0 , 5 , 0 , 197, 0 ), // #820 - INST(Ud1 , X86Rm , O(000F00,B9,_,_,_,_,_,_ ), 0 , 5 , 0 , 197, 0 ), // #821 - INST(Ud2 , X86Op , O(000F00,0B,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 0 ), // #822 - INST(Uiret , X86Op , O(F30F01,EC,_,_,_,_,_,_ ), 0 , 27 , 0 , 34 , 26 ), // #823 - INST(Umonitor , X86R_FromM , O(F30F00,AE,6,_,_,_,_,_ ), 0 , 26 , 0 , 198, 143), // #824 - INST(Umwait , X86R32_EDX_EAX , O(F20F00,AE,6,_,_,_,_,_ ), 0 , 101, 0 , 196, 142), // #825 - INST(Unpckhpd , ExtRm , O(660F00,15,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #826 - INST(Unpckhps , ExtRm , O(000F00,15,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #827 - INST(Unpcklpd , ExtRm , O(660F00,14,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #828 - INST(Unpcklps , ExtRm , O(000F00,14,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #829 - INST(V4fmaddps , VexRm_T1_4X , E(F20F38,9A,_,2,_,0,4,T4X), 0 , 102, 0 , 199, 144), // #830 - INST(V4fmaddss , VexRm_T1_4X , E(F20F38,9B,_,0,_,0,4,T4X), 0 , 103, 0 , 200, 144), // #831 - INST(V4fnmaddps , VexRm_T1_4X , E(F20F38,AA,_,2,_,0,4,T4X), 0 , 102, 0 , 199, 144), // #832 - INST(V4fnmaddss , VexRm_T1_4X , E(F20F38,AB,_,0,_,0,4,T4X), 0 , 103, 0 , 200, 144), // #833 - INST(Vaddpd , VexRvm_Lx , V(660F00,58,_,x,I,1,4,FV ), 0 , 104, 0 , 201, 145), // #834 - INST(Vaddph , VexRvm_Lx , E(00MAP5,58,_,_,_,0,4,FV ), 0 , 105, 0 , 202, 146), // #835 - INST(Vaddps , VexRvm_Lx , V(000F00,58,_,x,I,0,4,FV ), 0 , 106, 0 , 203, 145), // #836 - INST(Vaddsd , VexRvm , V(F20F00,58,_,I,I,1,3,T1S), 0 , 107, 0 , 204, 147), // #837 - INST(Vaddsh , VexRvm , E(F3MAP5,58,_,_,_,0,1,T1S), 0 , 108, 0 , 205, 148), // #838 - INST(Vaddss , VexRvm , V(F30F00,58,_,I,I,0,2,T1S), 0 , 109, 0 , 206, 147), // #839 - INST(Vaddsubpd , VexRvm_Lx , V(660F00,D0,_,x,I,_,_,_ ), 0 , 71 , 0 , 207, 149), // #840 - INST(Vaddsubps , VexRvm_Lx , V(F20F00,D0,_,x,I,_,_,_ ), 0 , 110, 0 , 207, 149), // #841 - INST(Vaesdec , VexRvm_Lx , V(660F38,DE,_,x,I,_,4,FVM), 0 , 111, 0 , 208, 150), // #842 - INST(Vaesdeclast , VexRvm_Lx , V(660F38,DF,_,x,I,_,4,FVM), 0 , 111, 0 , 208, 150), // #843 - INST(Vaesenc , VexRvm_Lx , V(660F38,DC,_,x,I,_,4,FVM), 0 , 111, 0 , 208, 150), // #844 - INST(Vaesenclast , VexRvm_Lx , V(660F38,DD,_,x,I,_,4,FVM), 0 , 111, 0 , 208, 150), // #845 - INST(Vaesimc , VexRm , V(660F38,DB,_,0,I,_,_,_ ), 0 , 30 , 0 , 209, 151), // #846 - INST(Vaeskeygenassist , VexRmi , V(660F3A,DF,_,0,I,_,_,_ ), 0 , 75 , 0 , 210, 151), // #847 - INST(Valignd , VexRvmi_Lx , E(660F3A,03,_,x,_,0,4,FV ), 0 , 112, 0 , 211, 152), // #848 - INST(Valignq , VexRvmi_Lx , E(660F3A,03,_,x,_,1,4,FV ), 0 , 113, 0 , 212, 152), // #849 - INST(Vandnpd , VexRvm_Lx , V(660F00,55,_,x,I,1,4,FV ), 0 , 104, 0 , 213, 153), // #850 - INST(Vandnps , VexRvm_Lx , V(000F00,55,_,x,I,0,4,FV ), 0 , 106, 0 , 214, 153), // #851 - INST(Vandpd , VexRvm_Lx , V(660F00,54,_,x,I,1,4,FV ), 0 , 104, 0 , 215, 153), // #852 - INST(Vandps , VexRvm_Lx , V(000F00,54,_,x,I,0,4,FV ), 0 , 106, 0 , 216, 153), // #853 - INST(Vbcstnebf162ps , VexRm_Lx , V(F30F38,B1,_,x,0,_,_,_ ), 0 , 89 , 0 , 217, 154), // #854 - INST(Vbcstnesh2ps , VexRm_Lx , V(660F38,B1,_,x,0,_,_,_ ), 0 , 30 , 0 , 217, 154), // #855 - INST(Vblendmpd , VexRvm_Lx , E(660F38,65,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #856 - INST(Vblendmps , VexRvm_Lx , E(660F38,65,_,x,_,0,4,FV ), 0 , 115, 0 , 219, 152), // #857 - INST(Vblendpd , VexRvmi_Lx , V(660F3A,0D,_,x,I,_,_,_ ), 0 , 75 , 0 , 220, 149), // #858 - INST(Vblendps , VexRvmi_Lx , V(660F3A,0C,_,x,I,_,_,_ ), 0 , 75 , 0 , 220, 149), // #859 - INST(Vblendvpd , VexRvmr_Lx , V(660F3A,4B,_,x,0,_,_,_ ), 0 , 75 , 0 , 221, 149), // #860 - INST(Vblendvps , VexRvmr_Lx , V(660F3A,4A,_,x,0,_,_,_ ), 0 , 75 , 0 , 221, 149), // #861 - INST(Vbroadcastf128 , VexRm , V(660F38,1A,_,1,0,_,_,_ ), 0 , 116, 0 , 222, 149), // #862 - INST(Vbroadcastf32x2 , VexRm_Lx , E(660F38,19,_,x,_,0,3,T2 ), 0 , 117, 0 , 223, 155), // #863 - INST(Vbroadcastf32x4 , VexRm_Lx , E(660F38,1A,_,x,_,0,4,T4 ), 0 , 118, 0 , 224, 78 ), // #864 - INST(Vbroadcastf32x8 , VexRm , E(660F38,1B,_,2,_,0,5,T8 ), 0 , 119, 0 , 225, 76 ), // #865 - INST(Vbroadcastf64x2 , VexRm_Lx , E(660F38,1A,_,x,_,1,4,T2 ), 0 , 120, 0 , 224, 155), // #866 - INST(Vbroadcastf64x4 , VexRm , E(660F38,1B,_,2,_,1,5,T4 ), 0 , 121, 0 , 225, 78 ), // #867 - INST(Vbroadcasti128 , VexRm , V(660F38,5A,_,1,0,_,_,_ ), 0 , 116, 0 , 222, 156), // #868 - INST(Vbroadcasti32x2 , VexRm_Lx , E(660F38,59,_,x,_,0,3,T2 ), 0 , 117, 0 , 226, 155), // #869 - INST(Vbroadcasti32x4 , VexRm_Lx , E(660F38,5A,_,x,_,0,4,T4 ), 0 , 118, 0 , 224, 152), // #870 - INST(Vbroadcasti32x8 , VexRm , E(660F38,5B,_,2,_,0,5,T8 ), 0 , 119, 0 , 225, 76 ), // #871 - INST(Vbroadcasti64x2 , VexRm_Lx , E(660F38,5A,_,x,_,1,4,T2 ), 0 , 120, 0 , 224, 155), // #872 - INST(Vbroadcasti64x4 , VexRm , E(660F38,5B,_,2,_,1,5,T4 ), 0 , 121, 0 , 225, 78 ), // #873 - INST(Vbroadcastsd , VexRm_Lx , V(660F38,19,_,x,0,1,3,T1S), 0 , 122, 0 , 227, 157), // #874 - INST(Vbroadcastss , VexRm_Lx , V(660F38,18,_,x,0,0,2,T1S), 0 , 123, 0 , 228, 157), // #875 - INST(Vcmppd , VexRvmi_Lx_KEvex , V(660F00,C2,_,x,I,1,4,FV ), 0 , 104, 0 , 229, 145), // #876 - INST(Vcmpph , VexRvmi_Lx_KEvex , E(000F3A,C2,_,_,_,0,4,FV ), 0 , 124, 0 , 230, 146), // #877 - INST(Vcmpps , VexRvmi_Lx_KEvex , V(000F00,C2,_,x,I,0,4,FV ), 0 , 106, 0 , 231, 145), // #878 - INST(Vcmpsd , VexRvmi_KEvex , V(F20F00,C2,_,I,I,1,3,T1S), 0 , 107, 0 , 232, 147), // #879 - INST(Vcmpsh , VexRvmi_KEvex , E(F30F3A,C2,_,_,_,0,1,T1S), 0 , 125, 0 , 233, 148), // #880 - INST(Vcmpss , VexRvmi_KEvex , V(F30F00,C2,_,I,I,0,2,T1S), 0 , 109, 0 , 234, 147), // #881 - INST(Vcomisd , VexRm , V(660F00,2F,_,I,I,1,3,T1S), 0 , 126, 0 , 235, 158), // #882 - INST(Vcomish , VexRm , E(00MAP5,2F,_,_,_,0,1,T1S), 0 , 127, 0 , 236, 159), // #883 - INST(Vcomiss , VexRm , V(000F00,2F,_,I,I,0,2,T1S), 0 , 128, 0 , 237, 158), // #884 - INST(Vcompresspd , VexMr_Lx , E(660F38,8A,_,x,_,1,3,T1S), 0 , 129, 0 , 238, 152), // #885 - INST(Vcompressps , VexMr_Lx , E(660F38,8A,_,x,_,0,2,T1S), 0 , 130, 0 , 238, 152), // #886 - INST(Vcvtdq2pd , VexRm_Lx , V(F30F00,E6,_,x,I,0,3,HV ), 0 , 131, 0 , 239, 145), // #887 - INST(Vcvtdq2ph , VexRm_Lx_Narrow , E(00MAP5,5B,_,x,0,0,4,FV ), 0 , 105, 0 , 240, 146), // #888 - INST(Vcvtdq2ps , VexRm_Lx , V(000F00,5B,_,x,I,0,4,FV ), 0 , 106, 0 , 241, 145), // #889 - INST(Vcvtne2ps2bf16 , VexRvm_Lx , E(F20F38,72,_,_,_,0,4,FV ), 0 , 132, 0 , 219, 160), // #890 - INST(Vcvtneebf162ps , VexRm_Lx , V(F30F38,B0,_,x,0,_,_,_ ), 0 , 89 , 0 , 242, 154), // #891 - INST(Vcvtneeph2ps , VexRm_Lx , V(660F38,B0,_,x,0,_,_,_ ), 0 , 30 , 0 , 242, 154), // #892 - INST(Vcvtneobf162ps , VexRm_Lx , V(F20F38,B0,_,x,0,_,_,_ ), 0 , 85 , 0 , 242, 154), // #893 - INST(Vcvtneoph2ps , VexRm_Lx , V(000F38,B0,_,x,0,_,_,_ ), 0 , 11 , 0 , 242, 154), // #894 - INST(Vcvtneps2bf16 , VexRm_Lx_Narrow , V(F30F38,72,_,_,_,0,4,FV ), 0 , 133, 0 , 243, 161), // #895 - INST(Vcvtpd2dq , VexRm_Lx_Narrow , V(F20F00,E6,_,x,I,1,4,FV ), 0 , 134, 0 , 244, 145), // #896 - INST(Vcvtpd2ph , VexRm_Lx , E(66MAP5,5A,_,_,_,1,4,FV ), 0 , 135, 0 , 245, 146), // #897 - INST(Vcvtpd2ps , VexRm_Lx_Narrow , V(660F00,5A,_,x,I,1,4,FV ), 0 , 104, 0 , 244, 145), // #898 - INST(Vcvtpd2qq , VexRm_Lx , E(660F00,7B,_,x,_,1,4,FV ), 0 , 136, 0 , 246, 155), // #899 - INST(Vcvtpd2udq , VexRm_Lx_Narrow , E(000F00,79,_,x,_,1,4,FV ), 0 , 137, 0 , 247, 152), // #900 - INST(Vcvtpd2uqq , VexRm_Lx , E(660F00,79,_,x,_,1,4,FV ), 0 , 136, 0 , 246, 155), // #901 - INST(Vcvtph2dq , VexRm_Lx , E(66MAP5,5B,_,_,_,0,3,HV ), 0 , 138, 0 , 248, 146), // #902 - INST(Vcvtph2pd , VexRm_Lx , E(00MAP5,5A,_,_,_,0,2,QV ), 0 , 139, 0 , 249, 146), // #903 - INST(Vcvtph2ps , VexRm_Lx , V(660F38,13,_,x,0,0,3,HVM), 0 , 140, 0 , 250, 162), // #904 - INST(Vcvtph2psx , VexRm_Lx , E(66MAP6,13,_,_,_,0,3,HV ), 0 , 141, 0 , 251, 146), // #905 - INST(Vcvtph2qq , VexRm_Lx , E(66MAP5,7B,_,_,_,0,2,QV ), 0 , 142, 0 , 252, 146), // #906 - INST(Vcvtph2udq , VexRm_Lx , E(00MAP5,79,_,_,_,0,3,HV ), 0 , 143, 0 , 248, 146), // #907 - INST(Vcvtph2uqq , VexRm_Lx , E(66MAP5,79,_,_,_,0,2,QV ), 0 , 142, 0 , 252, 146), // #908 - INST(Vcvtph2uw , VexRm_Lx , E(00MAP5,7D,_,_,_,0,4,FV ), 0 , 105, 0 , 253, 146), // #909 - INST(Vcvtph2w , VexRm_Lx , E(66MAP5,7D,_,_,_,0,4,FV ), 0 , 144, 0 , 253, 146), // #910 - INST(Vcvtps2dq , VexRm_Lx , V(660F00,5B,_,x,I,0,4,FV ), 0 , 145, 0 , 241, 145), // #911 - INST(Vcvtps2pd , VexRm_Lx , V(000F00,5A,_,x,I,0,3,HV ), 0 , 146, 0 , 254, 145), // #912 - INST(Vcvtps2ph , VexMri_Lx , V(660F3A,1D,_,x,0,0,3,HVM), 0 , 147, 0 , 255, 162), // #913 - INST(Vcvtps2phx , VexRm_Lx_Narrow , E(66MAP5,1D,_,_,_,0,4,FV ), 0 , 144, 0 , 240, 146), // #914 - INST(Vcvtps2qq , VexRm_Lx , E(660F00,7B,_,x,_,0,3,HV ), 0 , 148, 0 , 256, 155), // #915 - INST(Vcvtps2udq , VexRm_Lx , E(000F00,79,_,x,_,0,4,FV ), 0 , 149, 0 , 257, 152), // #916 - INST(Vcvtps2uqq , VexRm_Lx , E(660F00,79,_,x,_,0,3,HV ), 0 , 148, 0 , 256, 155), // #917 - INST(Vcvtqq2pd , VexRm_Lx , E(F30F00,E6,_,x,_,1,4,FV ), 0 , 150, 0 , 246, 155), // #918 - INST(Vcvtqq2ph , VexRm_Lx , E(00MAP5,5B,_,_,_,1,4,FV ), 0 , 151, 0 , 245, 146), // #919 - INST(Vcvtqq2ps , VexRm_Lx_Narrow , E(000F00,5B,_,x,_,1,4,FV ), 0 , 137, 0 , 247, 155), // #920 - INST(Vcvtsd2sh , VexRvm , E(F2MAP5,5A,_,_,_,1,3,T1S), 0 , 152, 0 , 258, 148), // #921 - INST(Vcvtsd2si , VexRm_Wx , V(F20F00,2D,_,I,x,x,3,T1F), 0 , 153, 0 , 259, 147), // #922 - INST(Vcvtsd2ss , VexRvm , V(F20F00,5A,_,I,I,1,3,T1S), 0 , 107, 0 , 204, 147), // #923 - INST(Vcvtsd2usi , VexRm_Wx , E(F20F00,79,_,I,_,x,3,T1F), 0 , 154, 0 , 260, 78 ), // #924 - INST(Vcvtsh2sd , VexRvm , E(F3MAP5,5A,_,_,_,0,1,T1S), 0 , 108, 0 , 261, 148), // #925 - INST(Vcvtsh2si , VexRm_Wx , E(F3MAP5,2D,_,_,_,x,1,T1S), 0 , 108, 0 , 262, 148), // #926 - INST(Vcvtsh2ss , VexRvm , E(00MAP6,13,_,_,_,0,1,T1S), 0 , 155, 0 , 261, 148), // #927 - INST(Vcvtsh2usi , VexRm_Wx , E(F3MAP5,79,_,_,_,x,1,T1S), 0 , 108, 0 , 262, 148), // #928 - INST(Vcvtsi2sd , VexRvm_Wx , V(F20F00,2A,_,I,x,x,2,T1W), 0 , 156, 0 , 263, 147), // #929 - INST(Vcvtsi2sh , VexRvm_Wx , E(F3MAP5,2A,_,_,_,x,2,T1W), 0 , 157, 0 , 264, 148), // #930 - INST(Vcvtsi2ss , VexRvm_Wx , V(F30F00,2A,_,I,x,x,2,T1W), 0 , 158, 0 , 263, 147), // #931 - INST(Vcvtss2sd , VexRvm , V(F30F00,5A,_,I,I,0,2,T1S), 0 , 109, 0 , 265, 147), // #932 - INST(Vcvtss2sh , VexRvm , E(00MAP5,1D,_,_,_,0,2,T1S), 0 , 159, 0 , 266, 148), // #933 - INST(Vcvtss2si , VexRm_Wx , V(F30F00,2D,_,I,x,x,2,T1F), 0 , 109, 0 , 267, 147), // #934 - INST(Vcvtss2usi , VexRm_Wx , E(F30F00,79,_,I,_,x,2,T1F), 0 , 160, 0 , 268, 78 ), // #935 - INST(Vcvttpd2dq , VexRm_Lx_Narrow , V(660F00,E6,_,x,I,1,4,FV ), 0 , 104, 0 , 269, 145), // #936 - INST(Vcvttpd2qq , VexRm_Lx , E(660F00,7A,_,x,_,1,4,FV ), 0 , 136, 0 , 270, 152), // #937 - INST(Vcvttpd2udq , VexRm_Lx_Narrow , E(000F00,78,_,x,_,1,4,FV ), 0 , 137, 0 , 271, 152), // #938 - INST(Vcvttpd2uqq , VexRm_Lx , E(660F00,78,_,x,_,1,4,FV ), 0 , 136, 0 , 270, 155), // #939 - INST(Vcvttph2dq , VexRm_Lx , E(F3MAP5,5B,_,_,_,0,3,HV ), 0 , 161, 0 , 251, 146), // #940 - INST(Vcvttph2qq , VexRm_Lx , E(66MAP5,7A,_,_,_,0,2,QV ), 0 , 142, 0 , 249, 146), // #941 - INST(Vcvttph2udq , VexRm_Lx , E(00MAP5,78,_,_,_,0,3,HV ), 0 , 143, 0 , 251, 146), // #942 - INST(Vcvttph2uqq , VexRm_Lx , E(66MAP5,78,_,_,_,0,2,QV ), 0 , 142, 0 , 249, 146), // #943 - INST(Vcvttph2uw , VexRm_Lx , E(00MAP5,7C,_,_,_,0,4,FV ), 0 , 105, 0 , 272, 146), // #944 - INST(Vcvttph2w , VexRm_Lx , E(66MAP5,7C,_,_,_,0,4,FV ), 0 , 144, 0 , 272, 146), // #945 - INST(Vcvttps2dq , VexRm_Lx , V(F30F00,5B,_,x,I,0,4,FV ), 0 , 162, 0 , 273, 145), // #946 - INST(Vcvttps2qq , VexRm_Lx , E(660F00,7A,_,x,_,0,3,HV ), 0 , 148, 0 , 274, 155), // #947 - INST(Vcvttps2udq , VexRm_Lx , E(000F00,78,_,x,_,0,4,FV ), 0 , 149, 0 , 275, 152), // #948 - INST(Vcvttps2uqq , VexRm_Lx , E(660F00,78,_,x,_,0,3,HV ), 0 , 148, 0 , 274, 155), // #949 - INST(Vcvttsd2si , VexRm_Wx , V(F20F00,2C,_,I,x,x,3,T1F), 0 , 153, 0 , 276, 147), // #950 - INST(Vcvttsd2usi , VexRm_Wx , E(F20F00,78,_,I,_,x,3,T1F), 0 , 154, 0 , 277, 78 ), // #951 - INST(Vcvttsh2si , VexRm_Wx , E(F3MAP5,2C,_,_,_,x,1,T1S), 0 , 108, 0 , 278, 148), // #952 - INST(Vcvttsh2usi , VexRm_Wx , E(F3MAP5,78,_,_,_,x,1,T1S), 0 , 108, 0 , 278, 148), // #953 - INST(Vcvttss2si , VexRm_Wx , V(F30F00,2C,_,I,x,x,2,T1F), 0 , 109, 0 , 279, 147), // #954 - INST(Vcvttss2usi , VexRm_Wx , E(F30F00,78,_,I,_,x,2,T1F), 0 , 160, 0 , 280, 78 ), // #955 - INST(Vcvtudq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,0,3,HV ), 0 , 163, 0 , 281, 152), // #956 - INST(Vcvtudq2ph , VexRm_Lx_Narrow , E(F2MAP5,7A,_,_,_,0,4,FV ), 0 , 164, 0 , 240, 146), // #957 - INST(Vcvtudq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,0,4,FV ), 0 , 165, 0 , 257, 152), // #958 - INST(Vcvtuqq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,1,4,FV ), 0 , 150, 0 , 246, 155), // #959 - INST(Vcvtuqq2ph , VexRm_Lx , E(F2MAP5,7A,_,_,_,1,4,FV ), 0 , 166, 0 , 245, 146), // #960 - INST(Vcvtuqq2ps , VexRm_Lx_Narrow , E(F20F00,7A,_,x,_,1,4,FV ), 0 , 167, 0 , 247, 155), // #961 - INST(Vcvtusi2sd , VexRvm_Wx , E(F20F00,7B,_,I,_,x,2,T1W), 0 , 168, 0 , 282, 78 ), // #962 - INST(Vcvtusi2sh , VexRvm_Wx , E(F3MAP5,7B,_,_,_,x,2,T1W), 0 , 157, 0 , 264, 148), // #963 - INST(Vcvtusi2ss , VexRvm_Wx , E(F30F00,7B,_,I,_,x,2,T1W), 0 , 169, 0 , 282, 78 ), // #964 - INST(Vcvtuw2ph , VexRm_Lx , E(F2MAP5,7D,_,_,_,0,4,FV ), 0 , 164, 0 , 253, 146), // #965 - INST(Vcvtw2ph , VexRm_Lx , E(F3MAP5,7D,_,_,_,0,4,FV ), 0 , 170, 0 , 253, 146), // #966 - INST(Vdbpsadbw , VexRvmi_Lx , E(660F3A,42,_,x,_,0,4,FVM), 0 , 112, 0 , 283, 163), // #967 - INST(Vdivpd , VexRvm_Lx , V(660F00,5E,_,x,I,1,4,FV ), 0 , 104, 0 , 201, 145), // #968 - INST(Vdivph , VexRvm_Lx , E(00MAP5,5E,_,_,_,0,4,FV ), 0 , 105, 0 , 202, 146), // #969 - INST(Vdivps , VexRvm_Lx , V(000F00,5E,_,x,I,0,4,FV ), 0 , 106, 0 , 203, 145), // #970 - INST(Vdivsd , VexRvm , V(F20F00,5E,_,I,I,1,3,T1S), 0 , 107, 0 , 204, 147), // #971 - INST(Vdivsh , VexRvm , E(F3MAP5,5E,_,_,_,0,1,T1S), 0 , 108, 0 , 205, 148), // #972 - INST(Vdivss , VexRvm , V(F30F00,5E,_,I,I,0,2,T1S), 0 , 109, 0 , 206, 147), // #973 - INST(Vdpbf16ps , VexRvm_Lx , E(F30F38,52,_,_,_,0,4,FV ), 0 , 171, 0 , 219, 160), // #974 - INST(Vdppd , VexRvmi_Lx , V(660F3A,41,_,x,I,_,_,_ ), 0 , 75 , 0 , 284, 149), // #975 - INST(Vdpps , VexRvmi_Lx , V(660F3A,40,_,x,I,_,_,_ ), 0 , 75 , 0 , 220, 149), // #976 - INST(Verr , X86M_NoSize , O(000F00,00,4,_,_,_,_,_ ), 0 , 98 , 0 , 112, 11 ), // #977 - INST(Verw , X86M_NoSize , O(000F00,00,5,_,_,_,_,_ ), 0 , 79 , 0 , 112, 11 ), // #978 - INST(Vexp2pd , VexRm , E(660F38,C8,_,2,_,1,4,FV ), 0 , 172, 0 , 285, 164), // #979 - INST(Vexp2ps , VexRm , E(660F38,C8,_,2,_,0,4,FV ), 0 , 173, 0 , 286, 164), // #980 - INST(Vexpandpd , VexRm_Lx , E(660F38,88,_,x,_,1,3,T1S), 0 , 129, 0 , 287, 152), // #981 - INST(Vexpandps , VexRm_Lx , E(660F38,88,_,x,_,0,2,T1S), 0 , 130, 0 , 287, 152), // #982 - INST(Vextractf128 , VexMri , V(660F3A,19,_,1,0,_,_,_ ), 0 , 174, 0 , 288, 149), // #983 - INST(Vextractf32x4 , VexMri_Lx , E(660F3A,19,_,x,_,0,4,T4 ), 0 , 175, 0 , 289, 152), // #984 - INST(Vextractf32x8 , VexMri , E(660F3A,1B,_,2,_,0,5,T8 ), 0 , 176, 0 , 290, 76 ), // #985 - INST(Vextractf64x2 , VexMri_Lx , E(660F3A,19,_,x,_,1,4,T2 ), 0 , 177, 0 , 289, 155), // #986 - INST(Vextractf64x4 , VexMri , E(660F3A,1B,_,2,_,1,5,T4 ), 0 , 178, 0 , 290, 78 ), // #987 - INST(Vextracti128 , VexMri , V(660F3A,39,_,1,0,_,_,_ ), 0 , 174, 0 , 288, 156), // #988 - INST(Vextracti32x4 , VexMri_Lx , E(660F3A,39,_,x,_,0,4,T4 ), 0 , 175, 0 , 289, 152), // #989 - INST(Vextracti32x8 , VexMri , E(660F3A,3B,_,2,_,0,5,T8 ), 0 , 176, 0 , 290, 76 ), // #990 - INST(Vextracti64x2 , VexMri_Lx , E(660F3A,39,_,x,_,1,4,T2 ), 0 , 177, 0 , 289, 155), // #991 - INST(Vextracti64x4 , VexMri , E(660F3A,3B,_,2,_,1,5,T4 ), 0 , 178, 0 , 290, 78 ), // #992 - INST(Vextractps , VexMri , V(660F3A,17,_,0,I,I,2,T1S), 0 , 179, 0 , 291, 147), // #993 - INST(Vfcmaddcph , VexRvm_Lx , E(F2MAP6,56,_,_,_,0,4,FV ), 0 , 180, 0 , 292, 146), // #994 - INST(Vfcmaddcsh , VexRvm , E(F2MAP6,57,_,_,_,0,2,T1S), 0 , 181, 0 , 266, 148), // #995 - INST(Vfcmulcph , VexRvm_Lx , E(F2MAP6,D6,_,_,_,0,4,FV ), 0 , 180, 0 , 292, 146), // #996 - INST(Vfcmulcsh , VexRvm , E(F2MAP6,D7,_,_,_,0,2,T1S), 0 , 181, 0 , 266, 148), // #997 - INST(Vfixupimmpd , VexRvmi_Lx , E(660F3A,54,_,x,_,1,4,FV ), 0 , 113, 0 , 293, 152), // #998 - INST(Vfixupimmps , VexRvmi_Lx , E(660F3A,54,_,x,_,0,4,FV ), 0 , 112, 0 , 294, 152), // #999 - INST(Vfixupimmsd , VexRvmi , E(660F3A,55,_,I,_,1,3,T1S), 0 , 182, 0 , 295, 78 ), // #1000 - INST(Vfixupimmss , VexRvmi , E(660F3A,55,_,I,_,0,2,T1S), 0 , 183, 0 , 296, 78 ), // #1001 - INST(Vfmadd132pd , VexRvm_Lx , V(660F38,98,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1002 - INST(Vfmadd132ph , VexRvm_Lx , E(66MAP6,98,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1003 - INST(Vfmadd132ps , VexRvm_Lx , V(660F38,98,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1004 - INST(Vfmadd132sd , VexRvm , V(660F38,99,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1005 - INST(Vfmadd132sh , VexRvm , E(66MAP6,99,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1006 - INST(Vfmadd132ss , VexRvm , V(660F38,99,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1007 - INST(Vfmadd213pd , VexRvm_Lx , V(660F38,A8,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1008 - INST(Vfmadd213ph , VexRvm_Lx , E(66MAP6,A8,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1009 - INST(Vfmadd213ps , VexRvm_Lx , V(660F38,A8,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1010 - INST(Vfmadd213sd , VexRvm , V(660F38,A9,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1011 - INST(Vfmadd213sh , VexRvm , E(66MAP6,A9,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1012 - INST(Vfmadd213ss , VexRvm , V(660F38,A9,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1013 - INST(Vfmadd231pd , VexRvm_Lx , V(660F38,B8,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1014 - INST(Vfmadd231ph , VexRvm_Lx , E(66MAP6,B8,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1015 - INST(Vfmadd231ps , VexRvm_Lx , V(660F38,B8,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1016 - INST(Vfmadd231sd , VexRvm , V(660F38,B9,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1017 - INST(Vfmadd231sh , VexRvm , E(66MAP6,B9,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1018 - INST(Vfmadd231ss , VexRvm , V(660F38,B9,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1019 - INST(Vfmaddcph , VexRvm_Lx , E(F3MAP6,56,_,_,_,0,4,FV ), 0 , 188, 0 , 292, 146), // #1020 - INST(Vfmaddcsh , VexRvm , E(F3MAP6,57,_,_,_,0,2,T1S), 0 , 189, 0 , 266, 148), // #1021 - INST(Vfmaddpd , Fma4_Lx , V(660F3A,69,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1022 - INST(Vfmaddps , Fma4_Lx , V(660F3A,68,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1023 - INST(Vfmaddsd , Fma4 , V(660F3A,6B,_,0,x,_,_,_ ), 0 , 75 , 0 , 298, 167), // #1024 - INST(Vfmaddss , Fma4 , V(660F3A,6A,_,0,x,_,_,_ ), 0 , 75 , 0 , 299, 167), // #1025 - INST(Vfmaddsub132pd , VexRvm_Lx , V(660F38,96,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1026 - INST(Vfmaddsub132ph , VexRvm_Lx , E(66MAP6,96,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1027 - INST(Vfmaddsub132ps , VexRvm_Lx , V(660F38,96,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1028 - INST(Vfmaddsub213pd , VexRvm_Lx , V(660F38,A6,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1029 - INST(Vfmaddsub213ph , VexRvm_Lx , E(66MAP6,A6,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1030 - INST(Vfmaddsub213ps , VexRvm_Lx , V(660F38,A6,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1031 - INST(Vfmaddsub231pd , VexRvm_Lx , V(660F38,B6,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1032 - INST(Vfmaddsub231ph , VexRvm_Lx , E(66MAP6,B6,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1033 - INST(Vfmaddsub231ps , VexRvm_Lx , V(660F38,B6,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1034 - INST(Vfmaddsubpd , Fma4_Lx , V(660F3A,5D,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1035 - INST(Vfmaddsubps , Fma4_Lx , V(660F3A,5C,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1036 - INST(Vfmsub132pd , VexRvm_Lx , V(660F38,9A,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1037 - INST(Vfmsub132ph , VexRvm_Lx , E(66MAP6,9A,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1038 - INST(Vfmsub132ps , VexRvm_Lx , V(660F38,9A,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1039 - INST(Vfmsub132sd , VexRvm , V(660F38,9B,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1040 - INST(Vfmsub132sh , VexRvm , E(66MAP6,9B,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1041 - INST(Vfmsub132ss , VexRvm , V(660F38,9B,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1042 - INST(Vfmsub213pd , VexRvm_Lx , V(660F38,AA,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1043 - INST(Vfmsub213ph , VexRvm_Lx , E(66MAP6,AA,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1044 - INST(Vfmsub213ps , VexRvm_Lx , V(660F38,AA,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1045 - INST(Vfmsub213sd , VexRvm , V(660F38,AB,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1046 - INST(Vfmsub213sh , VexRvm , E(66MAP6,AB,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1047 - INST(Vfmsub213ss , VexRvm , V(660F38,AB,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1048 - INST(Vfmsub231pd , VexRvm_Lx , V(660F38,BA,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1049 - INST(Vfmsub231ph , VexRvm_Lx , E(66MAP6,BA,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1050 - INST(Vfmsub231ps , VexRvm_Lx , V(660F38,BA,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1051 - INST(Vfmsub231sd , VexRvm , V(660F38,BB,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1052 - INST(Vfmsub231sh , VexRvm , E(66MAP6,BB,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1053 - INST(Vfmsub231ss , VexRvm , V(660F38,BB,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1054 - INST(Vfmsubadd132pd , VexRvm_Lx , V(660F38,97,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1055 - INST(Vfmsubadd132ph , VexRvm_Lx , E(66MAP6,97,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1056 - INST(Vfmsubadd132ps , VexRvm_Lx , V(660F38,97,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1057 - INST(Vfmsubadd213pd , VexRvm_Lx , V(660F38,A7,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1058 - INST(Vfmsubadd213ph , VexRvm_Lx , E(66MAP6,A7,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1059 - INST(Vfmsubadd213ps , VexRvm_Lx , V(660F38,A7,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1060 - INST(Vfmsubadd231pd , VexRvm_Lx , V(660F38,B7,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1061 - INST(Vfmsubadd231ph , VexRvm_Lx , E(66MAP6,B7,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1062 - INST(Vfmsubadd231ps , VexRvm_Lx , V(660F38,B7,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1063 - INST(Vfmsubaddpd , Fma4_Lx , V(660F3A,5F,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1064 - INST(Vfmsubaddps , Fma4_Lx , V(660F3A,5E,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1065 - INST(Vfmsubpd , Fma4_Lx , V(660F3A,6D,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1066 - INST(Vfmsubps , Fma4_Lx , V(660F3A,6C,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1067 - INST(Vfmsubsd , Fma4 , V(660F3A,6F,_,0,x,_,_,_ ), 0 , 75 , 0 , 298, 167), // #1068 - INST(Vfmsubss , Fma4 , V(660F3A,6E,_,0,x,_,_,_ ), 0 , 75 , 0 , 299, 167), // #1069 - INST(Vfmulcph , VexRvm_Lx , E(F3MAP6,D6,_,_,_,0,4,FV ), 0 , 188, 0 , 292, 146), // #1070 - INST(Vfmulcsh , VexRvm , E(F3MAP6,D7,_,_,_,0,2,T1S), 0 , 189, 0 , 266, 146), // #1071 - INST(Vfnmadd132pd , VexRvm_Lx , V(660F38,9C,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1072 - INST(Vfnmadd132ph , VexRvm_Lx , E(66MAP6,9C,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1073 - INST(Vfnmadd132ps , VexRvm_Lx , V(660F38,9C,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1074 - INST(Vfnmadd132sd , VexRvm , V(660F38,9D,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1075 - INST(Vfnmadd132sh , VexRvm , E(66MAP6,9D,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1076 - INST(Vfnmadd132ss , VexRvm , V(660F38,9D,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1077 - INST(Vfnmadd213pd , VexRvm_Lx , V(660F38,AC,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1078 - INST(Vfnmadd213ph , VexRvm_Lx , E(66MAP6,AC,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1079 - INST(Vfnmadd213ps , VexRvm_Lx , V(660F38,AC,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1080 - INST(Vfnmadd213sd , VexRvm , V(660F38,AD,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1081 - INST(Vfnmadd213sh , VexRvm , E(66MAP6,AD,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1082 - INST(Vfnmadd213ss , VexRvm , V(660F38,AD,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1083 - INST(Vfnmadd231pd , VexRvm_Lx , V(660F38,BC,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1084 - INST(Vfnmadd231ph , VexRvm_Lx , E(66MAP6,BC,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1085 - INST(Vfnmadd231ps , VexRvm_Lx , V(660F38,BC,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1086 - INST(Vfnmadd231sd , VexRvm , V(660F38,BD,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1087 - INST(Vfnmadd231sh , VexRvm , E(66MAP6,BD,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1088 - INST(Vfnmadd231ss , VexRvm , V(660F38,BD,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1089 - INST(Vfnmaddpd , Fma4_Lx , V(660F3A,79,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1090 - INST(Vfnmaddps , Fma4_Lx , V(660F3A,78,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1091 - INST(Vfnmaddsd , Fma4 , V(660F3A,7B,_,0,x,_,_,_ ), 0 , 75 , 0 , 298, 167), // #1092 - INST(Vfnmaddss , Fma4 , V(660F3A,7A,_,0,x,_,_,_ ), 0 , 75 , 0 , 299, 167), // #1093 - INST(Vfnmsub132pd , VexRvm_Lx , V(660F38,9E,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1094 - INST(Vfnmsub132ph , VexRvm_Lx , E(66MAP6,9E,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1095 - INST(Vfnmsub132ps , VexRvm_Lx , V(660F38,9E,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1096 - INST(Vfnmsub132sd , VexRvm , V(660F38,9F,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1097 - INST(Vfnmsub132sh , VexRvm , E(66MAP6,9F,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1098 - INST(Vfnmsub132ss , VexRvm , V(660F38,9F,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1099 - INST(Vfnmsub213pd , VexRvm_Lx , V(660F38,AE,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1100 - INST(Vfnmsub213ph , VexRvm_Lx , E(66MAP6,AE,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1101 - INST(Vfnmsub213ps , VexRvm_Lx , V(660F38,AE,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1102 - INST(Vfnmsub213sd , VexRvm , V(660F38,AF,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1103 - INST(Vfnmsub213sh , VexRvm , E(66MAP6,AF,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1104 - INST(Vfnmsub213ss , VexRvm , V(660F38,AF,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1105 - INST(Vfnmsub231pd , VexRvm_Lx , V(660F38,BE,_,x,1,1,4,FV ), 0 , 184, 0 , 201, 165), // #1106 - INST(Vfnmsub231ph , VexRvm_Lx , E(66MAP6,BE,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1107 - INST(Vfnmsub231ps , VexRvm_Lx , V(660F38,BE,_,x,0,0,4,FV ), 0 , 111, 0 , 203, 165), // #1108 - INST(Vfnmsub231sd , VexRvm , V(660F38,BF,_,I,1,1,3,T1S), 0 , 186, 0 , 204, 166), // #1109 - INST(Vfnmsub231sh , VexRvm , E(66MAP6,BF,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1110 - INST(Vfnmsub231ss , VexRvm , V(660F38,BF,_,I,0,0,2,T1S), 0 , 123, 0 , 206, 166), // #1111 - INST(Vfnmsubpd , Fma4_Lx , V(660F3A,7D,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1112 - INST(Vfnmsubps , Fma4_Lx , V(660F3A,7C,_,x,x,_,_,_ ), 0 , 75 , 0 , 297, 167), // #1113 - INST(Vfnmsubsd , Fma4 , V(660F3A,7F,_,0,x,_,_,_ ), 0 , 75 , 0 , 298, 167), // #1114 - INST(Vfnmsubss , Fma4 , V(660F3A,7E,_,0,x,_,_,_ ), 0 , 75 , 0 , 299, 167), // #1115 - INST(Vfpclasspd , VexRmi_Lx , E(660F3A,66,_,x,_,1,4,FV ), 0 , 113, 0 , 300, 155), // #1116 - INST(Vfpclassph , VexRmi_Lx , E(000F3A,66,_,_,_,0,4,FV ), 0 , 124, 0 , 301, 146), // #1117 - INST(Vfpclassps , VexRmi_Lx , E(660F3A,66,_,x,_,0,4,FV ), 0 , 112, 0 , 302, 155), // #1118 - INST(Vfpclasssd , VexRmi , E(660F3A,67,_,I,_,1,3,T1S), 0 , 182, 0 , 303, 76 ), // #1119 - INST(Vfpclasssh , VexRmi , E(000F3A,67,_,_,_,0,1,T1S), 0 , 190, 0 , 304, 148), // #1120 - INST(Vfpclassss , VexRmi , E(660F3A,67,_,I,_,0,2,T1S), 0 , 183, 0 , 305, 76 ), // #1121 - INST(Vfrczpd , VexRm_Lx , V(XOP_M9,81,_,x,0,_,_,_ ), 0 , 81 , 0 , 306, 168), // #1122 - INST(Vfrczps , VexRm_Lx , V(XOP_M9,80,_,x,0,_,_,_ ), 0 , 81 , 0 , 306, 168), // #1123 - INST(Vfrczsd , VexRm , V(XOP_M9,83,_,0,0,_,_,_ ), 0 , 81 , 0 , 307, 168), // #1124 - INST(Vfrczss , VexRm , V(XOP_M9,82,_,0,0,_,_,_ ), 0 , 81 , 0 , 308, 168), // #1125 - INST(Vgatherdpd , VexRmvRm_VM , V(660F38,92,_,x,1,_,_,_ ), E(660F38,92,_,x,_,1,3,T1S), 191, 80 , 309, 169), // #1126 - INST(Vgatherdps , VexRmvRm_VM , V(660F38,92,_,x,0,_,_,_ ), E(660F38,92,_,x,_,0,2,T1S), 30 , 81 , 310, 169), // #1127 - INST(Vgatherpf0dpd , VexM_VM , E(660F38,C6,1,2,_,1,3,T1S), 0 , 192, 0 , 311, 170), // #1128 - INST(Vgatherpf0dps , VexM_VM , E(660F38,C6,1,2,_,0,2,T1S), 0 , 193, 0 , 312, 170), // #1129 - INST(Vgatherpf0qpd , VexM_VM , E(660F38,C7,1,2,_,1,3,T1S), 0 , 192, 0 , 313, 170), // #1130 - INST(Vgatherpf0qps , VexM_VM , E(660F38,C7,1,2,_,0,2,T1S), 0 , 193, 0 , 313, 170), // #1131 - INST(Vgatherpf1dpd , VexM_VM , E(660F38,C6,2,2,_,1,3,T1S), 0 , 194, 0 , 311, 170), // #1132 - INST(Vgatherpf1dps , VexM_VM , E(660F38,C6,2,2,_,0,2,T1S), 0 , 195, 0 , 312, 170), // #1133 - INST(Vgatherpf1qpd , VexM_VM , E(660F38,C7,2,2,_,1,3,T1S), 0 , 194, 0 , 313, 170), // #1134 - INST(Vgatherpf1qps , VexM_VM , E(660F38,C7,2,2,_,0,2,T1S), 0 , 195, 0 , 313, 170), // #1135 - INST(Vgatherqpd , VexRmvRm_VM , V(660F38,93,_,x,1,_,_,_ ), E(660F38,93,_,x,_,1,3,T1S), 191, 82 , 314, 169), // #1136 - INST(Vgatherqps , VexRmvRm_VM , V(660F38,93,_,x,0,_,_,_ ), E(660F38,93,_,x,_,0,2,T1S), 30 , 83 , 315, 169), // #1137 - INST(Vgetexppd , VexRm_Lx , E(660F38,42,_,x,_,1,4,FV ), 0 , 114, 0 , 270, 152), // #1138 - INST(Vgetexpph , VexRm_Lx , E(66MAP6,42,_,_,_,0,4,FV ), 0 , 185, 0 , 272, 146), // #1139 - INST(Vgetexpps , VexRm_Lx , E(660F38,42,_,x,_,0,4,FV ), 0 , 115, 0 , 275, 152), // #1140 - INST(Vgetexpsd , VexRvm , E(660F38,43,_,I,_,1,3,T1S), 0 , 129, 0 , 316, 78 ), // #1141 - INST(Vgetexpsh , VexRvm , E(66MAP6,43,_,_,_,0,1,T1S), 0 , 187, 0 , 261, 148), // #1142 - INST(Vgetexpss , VexRvm , E(660F38,43,_,I,_,0,2,T1S), 0 , 130, 0 , 317, 78 ), // #1143 - INST(Vgetmantpd , VexRmi_Lx , E(660F3A,26,_,x,_,1,4,FV ), 0 , 113, 0 , 318, 152), // #1144 - INST(Vgetmantph , VexRmi_Lx , E(000F3A,26,_,_,_,0,4,FV ), 0 , 124, 0 , 319, 146), // #1145 - INST(Vgetmantps , VexRmi_Lx , E(660F3A,26,_,x,_,0,4,FV ), 0 , 112, 0 , 320, 152), // #1146 - INST(Vgetmantsd , VexRvmi , E(660F3A,27,_,I,_,1,3,T1S), 0 , 182, 0 , 295, 78 ), // #1147 - INST(Vgetmantsh , VexRvmi , E(000F3A,27,_,_,_,0,1,T1S), 0 , 190, 0 , 321, 148), // #1148 - INST(Vgetmantss , VexRvmi , E(660F3A,27,_,I,_,0,2,T1S), 0 , 183, 0 , 296, 78 ), // #1149 - INST(Vgf2p8affineinvqb, VexRvmi_Lx , V(660F3A,CF,_,x,1,1,4,FV ), 0 , 196, 0 , 322, 171), // #1150 - INST(Vgf2p8affineqb , VexRvmi_Lx , V(660F3A,CE,_,x,1,1,4,FV ), 0 , 196, 0 , 322, 171), // #1151 - INST(Vgf2p8mulb , VexRvm_Lx , V(660F38,CF,_,x,0,0,4,FV ), 0 , 111, 0 , 323, 171), // #1152 - INST(Vhaddpd , VexRvm_Lx , V(660F00,7C,_,x,I,_,_,_ ), 0 , 71 , 0 , 207, 149), // #1153 - INST(Vhaddps , VexRvm_Lx , V(F20F00,7C,_,x,I,_,_,_ ), 0 , 110, 0 , 207, 149), // #1154 - INST(Vhsubpd , VexRvm_Lx , V(660F00,7D,_,x,I,_,_,_ ), 0 , 71 , 0 , 207, 149), // #1155 - INST(Vhsubps , VexRvm_Lx , V(F20F00,7D,_,x,I,_,_,_ ), 0 , 110, 0 , 207, 149), // #1156 - INST(Vinsertf128 , VexRvmi , V(660F3A,18,_,1,0,_,_,_ ), 0 , 174, 0 , 324, 149), // #1157 - INST(Vinsertf32x4 , VexRvmi_Lx , E(660F3A,18,_,x,_,0,4,T4 ), 0 , 175, 0 , 325, 152), // #1158 - INST(Vinsertf32x8 , VexRvmi , E(660F3A,1A,_,2,_,0,5,T8 ), 0 , 176, 0 , 326, 76 ), // #1159 - INST(Vinsertf64x2 , VexRvmi_Lx , E(660F3A,18,_,x,_,1,4,T2 ), 0 , 177, 0 , 325, 155), // #1160 - INST(Vinsertf64x4 , VexRvmi , E(660F3A,1A,_,2,_,1,5,T4 ), 0 , 178, 0 , 326, 78 ), // #1161 - INST(Vinserti128 , VexRvmi , V(660F3A,38,_,1,0,_,_,_ ), 0 , 174, 0 , 324, 156), // #1162 - INST(Vinserti32x4 , VexRvmi_Lx , E(660F3A,38,_,x,_,0,4,T4 ), 0 , 175, 0 , 325, 152), // #1163 - INST(Vinserti32x8 , VexRvmi , E(660F3A,3A,_,2,_,0,5,T8 ), 0 , 176, 0 , 326, 76 ), // #1164 - INST(Vinserti64x2 , VexRvmi_Lx , E(660F3A,38,_,x,_,1,4,T2 ), 0 , 177, 0 , 325, 155), // #1165 - INST(Vinserti64x4 , VexRvmi , E(660F3A,3A,_,2,_,1,5,T4 ), 0 , 178, 0 , 326, 78 ), // #1166 - INST(Vinsertps , VexRvmi , V(660F3A,21,_,0,I,0,2,T1S), 0 , 179, 0 , 327, 147), // #1167 - INST(Vlddqu , VexRm_Lx , V(F20F00,F0,_,x,I,_,_,_ ), 0 , 110, 0 , 242, 149), // #1168 - INST(Vldmxcsr , VexM , V(000F00,AE,2,0,I,_,_,_ ), 0 , 197, 0 , 328, 149), // #1169 - INST(Vmaskmovdqu , VexRm_ZDI , V(660F00,F7,_,0,I,_,_,_ ), 0 , 71 , 0 , 329, 149), // #1170 - INST(Vmaskmovpd , VexRvmMvr_Lx , V(660F38,2D,_,x,0,_,_,_ ), V(660F38,2F,_,x,0,_,_,_ ), 30 , 84 , 330, 149), // #1171 - INST(Vmaskmovps , VexRvmMvr_Lx , V(660F38,2C,_,x,0,_,_,_ ), V(660F38,2E,_,x,0,_,_,_ ), 30 , 85 , 330, 149), // #1172 - INST(Vmaxpd , VexRvm_Lx , V(660F00,5F,_,x,I,1,4,FV ), 0 , 104, 0 , 331, 145), // #1173 - INST(Vmaxph , VexRvm_Lx , E(00MAP5,5F,_,_,_,0,4,FV ), 0 , 105, 0 , 332, 146), // #1174 - INST(Vmaxps , VexRvm_Lx , V(000F00,5F,_,x,I,0,4,FV ), 0 , 106, 0 , 333, 145), // #1175 - INST(Vmaxsd , VexRvm , V(F20F00,5F,_,I,I,1,3,T1S), 0 , 107, 0 , 334, 147), // #1176 - INST(Vmaxsh , VexRvm , E(F3MAP5,5F,_,_,_,0,1,T1S), 0 , 108, 0 , 261, 148), // #1177 - INST(Vmaxss , VexRvm , V(F30F00,5F,_,I,I,0,2,T1S), 0 , 109, 0 , 265, 147), // #1178 - INST(Vmcall , X86Op , O(000F01,C1,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 67 ), // #1179 - INST(Vmclear , X86M_Only , O(660F00,C7,6,_,_,_,_,_ ), 0 , 28 , 0 , 33 , 67 ), // #1180 - INST(Vmfunc , X86Op , O(000F01,D4,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 67 ), // #1181 - INST(Vmgexit , X86Op , O(F20F01,D9,_,_,_,_,_,_ ), 0 , 93 , 0 , 31 , 172), // #1182 - INST(Vminpd , VexRvm_Lx , V(660F00,5D,_,x,I,1,4,FV ), 0 , 104, 0 , 331, 145), // #1183 - INST(Vminph , VexRvm_Lx , E(00MAP5,5D,_,_,_,0,4,FV ), 0 , 105, 0 , 332, 146), // #1184 - INST(Vminps , VexRvm_Lx , V(000F00,5D,_,x,I,0,4,FV ), 0 , 106, 0 , 333, 145), // #1185 - INST(Vminsd , VexRvm , V(F20F00,5D,_,I,I,1,3,T1S), 0 , 107, 0 , 334, 147), // #1186 - INST(Vminsh , VexRvm , E(F3MAP5,5D,_,_,_,0,1,T1S), 0 , 108, 0 , 261, 148), // #1187 - INST(Vminss , VexRvm , V(F30F00,5D,_,I,I,0,2,T1S), 0 , 109, 0 , 265, 147), // #1188 - INST(Vmlaunch , X86Op , O(000F01,C2,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 67 ), // #1189 - INST(Vmload , X86Op_xAX , O(000F01,DA,_,_,_,_,_,_ ), 0 , 23 , 0 , 335, 23 ), // #1190 - INST(Vmmcall , X86Op , O(000F01,D9,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 23 ), // #1191 - INST(Vmovapd , VexRmMr_Lx , V(660F00,28,_,x,I,1,4,FVM), V(660F00,29,_,x,I,1,4,FVM), 104, 86 , 336, 173), // #1192 - INST(Vmovaps , VexRmMr_Lx , V(000F00,28,_,x,I,0,4,FVM), V(000F00,29,_,x,I,0,4,FVM), 106, 87 , 336, 173), // #1193 - INST(Vmovd , VexMovdMovq , V(660F00,6E,_,0,0,0,2,T1S), V(660F00,7E,_,0,0,0,2,T1S), 198, 88 , 337, 147), // #1194 - INST(Vmovddup , VexRm_Lx , V(F20F00,12,_,x,I,1,3,DUP), 0 , 199, 0 , 338, 145), // #1195 - INST(Vmovdqa , VexRmMr_Lx , V(660F00,6F,_,x,I,_,_,_ ), V(660F00,7F,_,x,I,_,_,_ ), 71 , 89 , 339, 174), // #1196 - INST(Vmovdqa32 , VexRmMr_Lx , E(660F00,6F,_,x,_,0,4,FVM), E(660F00,7F,_,x,_,0,4,FVM), 200, 90 , 340, 175), // #1197 - INST(Vmovdqa64 , VexRmMr_Lx , E(660F00,6F,_,x,_,1,4,FVM), E(660F00,7F,_,x,_,1,4,FVM), 136, 91 , 340, 175), // #1198 - INST(Vmovdqu , VexRmMr_Lx , V(F30F00,6F,_,x,I,_,_,_ ), V(F30F00,7F,_,x,I,_,_,_ ), 201, 92 , 339, 174), // #1199 - INST(Vmovdqu16 , VexRmMr_Lx , E(F20F00,6F,_,x,_,1,4,FVM), E(F20F00,7F,_,x,_,1,4,FVM), 167, 93 , 340, 176), // #1200 - INST(Vmovdqu32 , VexRmMr_Lx , E(F30F00,6F,_,x,_,0,4,FVM), E(F30F00,7F,_,x,_,0,4,FVM), 202, 94 , 340, 175), // #1201 - INST(Vmovdqu64 , VexRmMr_Lx , E(F30F00,6F,_,x,_,1,4,FVM), E(F30F00,7F,_,x,_,1,4,FVM), 150, 95 , 340, 175), // #1202 - INST(Vmovdqu8 , VexRmMr_Lx , E(F20F00,6F,_,x,_,0,4,FVM), E(F20F00,7F,_,x,_,0,4,FVM), 165, 96 , 340, 176), // #1203 - INST(Vmovhlps , VexRvm , V(000F00,12,_,0,I,0,_,_ ), 0 , 74 , 0 , 341, 147), // #1204 - INST(Vmovhpd , VexRvmMr , V(660F00,16,_,0,I,1,3,T1S), V(660F00,17,_,0,I,1,3,T1S), 126, 97 , 342, 147), // #1205 - INST(Vmovhps , VexRvmMr , V(000F00,16,_,0,I,0,3,T2 ), V(000F00,17,_,0,I,0,3,T2 ), 203, 98 , 342, 147), // #1206 - INST(Vmovlhps , VexRvm , V(000F00,16,_,0,I,0,_,_ ), 0 , 74 , 0 , 341, 147), // #1207 - INST(Vmovlpd , VexRvmMr , V(660F00,12,_,0,I,1,3,T1S), V(660F00,13,_,0,I,1,3,T1S), 126, 99 , 342, 147), // #1208 - INST(Vmovlps , VexRvmMr , V(000F00,12,_,0,I,0,3,T2 ), V(000F00,13,_,0,I,0,3,T2 ), 203, 100, 342, 147), // #1209 - INST(Vmovmskpd , VexRm_Lx , V(660F00,50,_,x,I,_,_,_ ), 0 , 71 , 0 , 343, 149), // #1210 - INST(Vmovmskps , VexRm_Lx , V(000F00,50,_,x,I,_,_,_ ), 0 , 74 , 0 , 343, 149), // #1211 - INST(Vmovntdq , VexMr_Lx , V(660F00,E7,_,x,I,0,4,FVM), 0 , 145, 0 , 344, 145), // #1212 - INST(Vmovntdqa , VexRm_Lx , V(660F38,2A,_,x,I,0,4,FVM), 0 , 111, 0 , 345, 157), // #1213 - INST(Vmovntpd , VexMr_Lx , V(660F00,2B,_,x,I,1,4,FVM), 0 , 104, 0 , 344, 145), // #1214 - INST(Vmovntps , VexMr_Lx , V(000F00,2B,_,x,I,0,4,FVM), 0 , 106, 0 , 344, 145), // #1215 - INST(Vmovq , VexMovdMovq , V(660F00,6E,_,0,I,1,3,T1S), V(660F00,7E,_,0,I,1,3,T1S), 126, 101, 346, 177), // #1216 - INST(Vmovsd , VexMovssMovsd , V(F20F00,10,_,I,I,1,3,T1S), V(F20F00,11,_,I,I,1,3,T1S), 107, 102, 347, 177), // #1217 - INST(Vmovsh , VexMovssMovsd , E(F3MAP5,10,_,I,_,0,1,T1S), E(F3MAP5,11,_,I,_,0,1,T1S), 108, 103, 348, 148), // #1218 - INST(Vmovshdup , VexRm_Lx , V(F30F00,16,_,x,I,0,4,FVM), 0 , 162, 0 , 349, 145), // #1219 - INST(Vmovsldup , VexRm_Lx , V(F30F00,12,_,x,I,0,4,FVM), 0 , 162, 0 , 349, 145), // #1220 - INST(Vmovss , VexMovssMovsd , V(F30F00,10,_,I,I,0,2,T1S), V(F30F00,11,_,I,I,0,2,T1S), 109, 104, 350, 177), // #1221 - INST(Vmovupd , VexRmMr_Lx , V(660F00,10,_,x,I,1,4,FVM), V(660F00,11,_,x,I,1,4,FVM), 104, 105, 336, 173), // #1222 - INST(Vmovups , VexRmMr_Lx , V(000F00,10,_,x,I,0,4,FVM), V(000F00,11,_,x,I,0,4,FVM), 106, 106, 336, 173), // #1223 - INST(Vmovw , VexMovdMovq , E(66MAP5,6E,_,0,_,I,1,T1S), E(66MAP5,7E,_,0,_,I,1,T1S), 204, 107, 351, 148), // #1224 - INST(Vmpsadbw , VexRvmi_Lx , V(660F3A,42,_,x,I,_,_,_ ), 0 , 75 , 0 , 220, 178), // #1225 - INST(Vmptrld , X86M_Only , O(000F00,C7,6,_,_,_,_,_ ), 0 , 82 , 0 , 33 , 67 ), // #1226 - INST(Vmptrst , X86M_Only , O(000F00,C7,7,_,_,_,_,_ ), 0 , 24 , 0 , 33 , 67 ), // #1227 - INST(Vmread , X86Mr_NoSize , O(000F00,78,_,_,_,_,_,_ ), 0 , 5 , 0 , 352, 67 ), // #1228 - INST(Vmresume , X86Op , O(000F01,C3,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 67 ), // #1229 - INST(Vmrun , X86Op_xAX , O(000F01,D8,_,_,_,_,_,_ ), 0 , 23 , 0 , 335, 23 ), // #1230 - INST(Vmsave , X86Op_xAX , O(000F01,DB,_,_,_,_,_,_ ), 0 , 23 , 0 , 335, 23 ), // #1231 - INST(Vmulpd , VexRvm_Lx , V(660F00,59,_,x,I,1,4,FV ), 0 , 104, 0 , 201, 145), // #1232 - INST(Vmulph , VexRvm_Lx , E(00MAP5,59,_,_,_,0,4,FV ), 0 , 105, 0 , 202, 146), // #1233 - INST(Vmulps , VexRvm_Lx , V(000F00,59,_,x,I,0,4,FV ), 0 , 106, 0 , 203, 145), // #1234 - INST(Vmulsd , VexRvm , V(F20F00,59,_,I,I,1,3,T1S), 0 , 107, 0 , 204, 147), // #1235 - INST(Vmulsh , VexRvm , E(F3MAP5,59,_,_,_,0,1,T1S), 0 , 108, 0 , 205, 148), // #1236 - INST(Vmulss , VexRvm , V(F30F00,59,_,I,I,0,2,T1S), 0 , 109, 0 , 206, 147), // #1237 - INST(Vmwrite , X86Rm_NoSize , O(000F00,79,_,_,_,_,_,_ ), 0 , 5 , 0 , 353, 67 ), // #1238 - INST(Vmxoff , X86Op , O(000F01,C4,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 67 ), // #1239 - INST(Vmxon , X86M_Only , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 26 , 0 , 33 , 67 ), // #1240 - INST(Vorpd , VexRvm_Lx , V(660F00,56,_,x,I,1,4,FV ), 0 , 104, 0 , 215, 153), // #1241 - INST(Vorps , VexRvm_Lx , V(000F00,56,_,x,I,0,4,FV ), 0 , 106, 0 , 216, 153), // #1242 - INST(Vp2intersectd , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,0,4,FV ), 0 , 132, 0 , 354, 179), // #1243 - INST(Vp2intersectq , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,1,4,FV ), 0 , 205, 0 , 355, 179), // #1244 - INST(Vp4dpwssd , VexRm_T1_4X , E(F20F38,52,_,2,_,0,4,T4X), 0 , 102, 0 , 199, 180), // #1245 - INST(Vp4dpwssds , VexRm_T1_4X , E(F20F38,53,_,2,_,0,4,T4X), 0 , 102, 0 , 199, 180), // #1246 - INST(Vpabsb , VexRm_Lx , V(660F38,1C,_,x,I,_,4,FVM), 0 , 111, 0 , 349, 181), // #1247 - INST(Vpabsd , VexRm_Lx , V(660F38,1E,_,x,I,0,4,FV ), 0 , 111, 0 , 356, 157), // #1248 - INST(Vpabsq , VexRm_Lx , E(660F38,1F,_,x,_,1,4,FV ), 0 , 114, 0 , 357, 152), // #1249 - INST(Vpabsw , VexRm_Lx , V(660F38,1D,_,x,I,_,4,FVM), 0 , 111, 0 , 349, 181), // #1250 - INST(Vpackssdw , VexRvm_Lx , V(660F00,6B,_,x,I,0,4,FV ), 0 , 145, 0 , 214, 181), // #1251 - INST(Vpacksswb , VexRvm_Lx , V(660F00,63,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1252 - INST(Vpackusdw , VexRvm_Lx , V(660F38,2B,_,x,I,0,4,FV ), 0 , 111, 0 , 214, 181), // #1253 - INST(Vpackuswb , VexRvm_Lx , V(660F00,67,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1254 - INST(Vpaddb , VexRvm_Lx , V(660F00,FC,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1255 - INST(Vpaddd , VexRvm_Lx , V(660F00,FE,_,x,I,0,4,FV ), 0 , 145, 0 , 214, 157), // #1256 - INST(Vpaddq , VexRvm_Lx , V(660F00,D4,_,x,I,1,4,FV ), 0 , 104, 0 , 213, 157), // #1257 - INST(Vpaddsb , VexRvm_Lx , V(660F00,EC,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1258 - INST(Vpaddsw , VexRvm_Lx , V(660F00,ED,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1259 - INST(Vpaddusb , VexRvm_Lx , V(660F00,DC,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1260 - INST(Vpaddusw , VexRvm_Lx , V(660F00,DD,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1261 - INST(Vpaddw , VexRvm_Lx , V(660F00,FD,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1262 - INST(Vpalignr , VexRvmi_Lx , V(660F3A,0F,_,x,I,I,4,FVM), 0 , 206, 0 , 322, 181), // #1263 - INST(Vpand , VexRvm_Lx , V(660F00,DB,_,x,I,_,_,_ ), 0 , 71 , 0 , 358, 178), // #1264 - INST(Vpandd , VexRvm_Lx , E(660F00,DB,_,x,_,0,4,FV ), 0 , 200, 0 , 359, 152), // #1265 - INST(Vpandn , VexRvm_Lx , V(660F00,DF,_,x,I,_,_,_ ), 0 , 71 , 0 , 360, 178), // #1266 - INST(Vpandnd , VexRvm_Lx , E(660F00,DF,_,x,_,0,4,FV ), 0 , 200, 0 , 361, 152), // #1267 - INST(Vpandnq , VexRvm_Lx , E(660F00,DF,_,x,_,1,4,FV ), 0 , 136, 0 , 362, 152), // #1268 - INST(Vpandq , VexRvm_Lx , E(660F00,DB,_,x,_,1,4,FV ), 0 , 136, 0 , 363, 152), // #1269 - INST(Vpavgb , VexRvm_Lx , V(660F00,E0,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1270 - INST(Vpavgw , VexRvm_Lx , V(660F00,E3,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1271 - INST(Vpblendd , VexRvmi_Lx , V(660F3A,02,_,x,0,_,_,_ ), 0 , 75 , 0 , 220, 156), // #1272 - INST(Vpblendmb , VexRvm_Lx , E(660F38,66,_,x,_,0,4,FVM), 0 , 115, 0 , 364, 163), // #1273 - INST(Vpblendmd , VexRvm_Lx , E(660F38,64,_,x,_,0,4,FV ), 0 , 115, 0 , 219, 152), // #1274 - INST(Vpblendmq , VexRvm_Lx , E(660F38,64,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1275 - INST(Vpblendmw , VexRvm_Lx , E(660F38,66,_,x,_,1,4,FVM), 0 , 114, 0 , 364, 163), // #1276 - INST(Vpblendvb , VexRvmr_Lx , V(660F3A,4C,_,x,0,_,_,_ ), 0 , 75 , 0 , 221, 178), // #1277 - INST(Vpblendw , VexRvmi_Lx , V(660F3A,0E,_,x,I,_,_,_ ), 0 , 75 , 0 , 220, 178), // #1278 - INST(Vpbroadcastb , VexRm_Lx_Bcst , V(660F38,78,_,x,0,0,0,T1S), E(660F38,7A,_,x,0,0,0,T1S), 30 , 108, 365, 182), // #1279 - INST(Vpbroadcastd , VexRm_Lx_Bcst , V(660F38,58,_,x,0,0,2,T1S), E(660F38,7C,_,x,0,0,0,T1S), 123, 109, 366, 169), // #1280 - INST(Vpbroadcastmb2q , VexRm_Lx , E(F30F38,2A,_,x,_,1,_,_ ), 0 , 207, 0 , 367, 183), // #1281 - INST(Vpbroadcastmw2d , VexRm_Lx , E(F30F38,3A,_,x,_,0,_,_ ), 0 , 208, 0 , 367, 183), // #1282 - INST(Vpbroadcastq , VexRm_Lx_Bcst , V(660F38,59,_,x,0,1,3,T1S), E(660F38,7C,_,x,0,1,0,T1S), 122, 110, 368, 169), // #1283 - INST(Vpbroadcastw , VexRm_Lx_Bcst , V(660F38,79,_,x,0,0,1,T1S), E(660F38,7B,_,x,0,0,0,T1S), 209, 111, 369, 182), // #1284 - INST(Vpclmulqdq , VexRvmi_Lx , V(660F3A,44,_,x,I,_,4,FVM), 0 , 206, 0 , 370, 184), // #1285 - INST(Vpcmov , VexRvrmRvmr_Lx , V(XOP_M8,A2,_,x,x,_,_,_ ), 0 , 210, 0 , 297, 168), // #1286 - INST(Vpcmpb , VexRvmi_Lx , E(660F3A,3F,_,x,_,0,4,FVM), 0 , 112, 0 , 371, 163), // #1287 - INST(Vpcmpd , VexRvmi_Lx , E(660F3A,1F,_,x,_,0,4,FV ), 0 , 112, 0 , 372, 152), // #1288 - INST(Vpcmpeqb , VexRvm_Lx_KEvex , V(660F00,74,_,x,I,I,4,FV ), 0 , 145, 0 , 373, 181), // #1289 - INST(Vpcmpeqd , VexRvm_Lx_KEvex , V(660F00,76,_,x,I,0,4,FVM), 0 , 145, 0 , 374, 157), // #1290 - INST(Vpcmpeqq , VexRvm_Lx_KEvex , V(660F38,29,_,x,I,1,4,FVM), 0 , 211, 0 , 375, 157), // #1291 - INST(Vpcmpeqw , VexRvm_Lx_KEvex , V(660F00,75,_,x,I,I,4,FV ), 0 , 145, 0 , 373, 181), // #1292 - INST(Vpcmpestri , VexRmi , V(660F3A,61,_,0,I,_,_,_ ), 0 , 75 , 0 , 376, 185), // #1293 - INST(Vpcmpestrm , VexRmi , V(660F3A,60,_,0,I,_,_,_ ), 0 , 75 , 0 , 377, 185), // #1294 - INST(Vpcmpgtb , VexRvm_Lx_KEvex , V(660F00,64,_,x,I,I,4,FV ), 0 , 145, 0 , 373, 181), // #1295 - INST(Vpcmpgtd , VexRvm_Lx_KEvex , V(660F00,66,_,x,I,0,4,FVM), 0 , 145, 0 , 374, 157), // #1296 - INST(Vpcmpgtq , VexRvm_Lx_KEvex , V(660F38,37,_,x,I,1,4,FVM), 0 , 211, 0 , 375, 157), // #1297 - INST(Vpcmpgtw , VexRvm_Lx_KEvex , V(660F00,65,_,x,I,I,4,FV ), 0 , 145, 0 , 373, 181), // #1298 - INST(Vpcmpistri , VexRmi , V(660F3A,63,_,0,I,_,_,_ ), 0 , 75 , 0 , 378, 185), // #1299 - INST(Vpcmpistrm , VexRmi , V(660F3A,62,_,0,I,_,_,_ ), 0 , 75 , 0 , 379, 185), // #1300 - INST(Vpcmpq , VexRvmi_Lx , E(660F3A,1F,_,x,_,1,4,FV ), 0 , 113, 0 , 380, 152), // #1301 - INST(Vpcmpub , VexRvmi_Lx , E(660F3A,3E,_,x,_,0,4,FVM), 0 , 112, 0 , 371, 163), // #1302 - INST(Vpcmpud , VexRvmi_Lx , E(660F3A,1E,_,x,_,0,4,FV ), 0 , 112, 0 , 372, 152), // #1303 - INST(Vpcmpuq , VexRvmi_Lx , E(660F3A,1E,_,x,_,1,4,FV ), 0 , 113, 0 , 380, 152), // #1304 - INST(Vpcmpuw , VexRvmi_Lx , E(660F3A,3E,_,x,_,1,4,FVM), 0 , 113, 0 , 380, 163), // #1305 - INST(Vpcmpw , VexRvmi_Lx , E(660F3A,3F,_,x,_,1,4,FVM), 0 , 113, 0 , 380, 163), // #1306 - INST(Vpcomb , VexRvmi , V(XOP_M8,CC,_,0,0,_,_,_ ), 0 , 210, 0 , 284, 168), // #1307 - INST(Vpcomd , VexRvmi , V(XOP_M8,CE,_,0,0,_,_,_ ), 0 , 210, 0 , 284, 168), // #1308 - INST(Vpcompressb , VexMr_Lx , E(660F38,63,_,x,_,0,0,T1S), 0 , 212, 0 , 238, 186), // #1309 - INST(Vpcompressd , VexMr_Lx , E(660F38,8B,_,x,_,0,2,T1S), 0 , 130, 0 , 238, 152), // #1310 - INST(Vpcompressq , VexMr_Lx , E(660F38,8B,_,x,_,1,3,T1S), 0 , 129, 0 , 238, 152), // #1311 - INST(Vpcompressw , VexMr_Lx , E(660F38,63,_,x,_,1,1,T1S), 0 , 213, 0 , 238, 186), // #1312 - INST(Vpcomq , VexRvmi , V(XOP_M8,CF,_,0,0,_,_,_ ), 0 , 210, 0 , 284, 168), // #1313 - INST(Vpcomub , VexRvmi , V(XOP_M8,EC,_,0,0,_,_,_ ), 0 , 210, 0 , 284, 168), // #1314 - INST(Vpcomud , VexRvmi , V(XOP_M8,EE,_,0,0,_,_,_ ), 0 , 210, 0 , 284, 168), // #1315 - INST(Vpcomuq , VexRvmi , V(XOP_M8,EF,_,0,0,_,_,_ ), 0 , 210, 0 , 284, 168), // #1316 - INST(Vpcomuw , VexRvmi , V(XOP_M8,ED,_,0,0,_,_,_ ), 0 , 210, 0 , 284, 168), // #1317 - INST(Vpcomw , VexRvmi , V(XOP_M8,CD,_,0,0,_,_,_ ), 0 , 210, 0 , 284, 168), // #1318 - INST(Vpconflictd , VexRm_Lx , E(660F38,C4,_,x,_,0,4,FV ), 0 , 115, 0 , 381, 183), // #1319 - INST(Vpconflictq , VexRm_Lx , E(660F38,C4,_,x,_,1,4,FV ), 0 , 114, 0 , 381, 183), // #1320 - INST(Vpdpbssd , VexRvm_Lx , V(F20F38,50,_,x,0,_,_,_ ), 0 , 85 , 0 , 207, 187), // #1321 - INST(Vpdpbssds , VexRvm_Lx , V(F20F38,51,_,x,0,_,_,_ ), 0 , 85 , 0 , 207, 187), // #1322 - INST(Vpdpbsud , VexRvm_Lx , V(F30F38,50,_,x,0,_,_,_ ), 0 , 89 , 0 , 207, 187), // #1323 - INST(Vpdpbsuds , VexRvm_Lx , V(F30F38,51,_,x,0,_,_,_ ), 0 , 89 , 0 , 207, 187), // #1324 - INST(Vpdpbusd , VexRvm_Lx , V(660F38,50,_,x,_,0,4,FV ), 0 , 111, 0 , 382, 188), // #1325 - INST(Vpdpbusds , VexRvm_Lx , V(660F38,51,_,x,_,0,4,FV ), 0 , 111, 0 , 382, 188), // #1326 - INST(Vpdpbuud , VexRvm_Lx , V(000F38,50,_,x,0,_,_,_ ), 0 , 11 , 0 , 207, 187), // #1327 - INST(Vpdpbuuds , VexRvm_Lx , V(000F38,51,_,x,0,_,_,_ ), 0 , 11 , 0 , 207, 187), // #1328 - INST(Vpdpwssd , VexRvm_Lx , V(660F38,52,_,x,_,0,4,FV ), 0 , 111, 0 , 382, 188), // #1329 - INST(Vpdpwssds , VexRvm_Lx , V(660F38,53,_,x,_,0,4,FV ), 0 , 111, 0 , 382, 188), // #1330 - INST(Vpdpwsud , VexRvm_Lx , V(F30F38,D2,_,x,0,_,_,_ ), 0 , 89 , 0 , 207, 189), // #1331 - INST(Vpdpwsuds , VexRvm_Lx , V(F30F38,D3,_,x,0,_,_,_ ), 0 , 89 , 0 , 207, 189), // #1332 - INST(Vpdpwusd , VexRvm_Lx , V(660F38,D2,_,x,0,_,_,_ ), 0 , 30 , 0 , 207, 189), // #1333 - INST(Vpdpwusds , VexRvm_Lx , V(660F38,D3,_,x,0,_,_,_ ), 0 , 30 , 0 , 207, 189), // #1334 - INST(Vpdpwuud , VexRvm_Lx , V(000F38,D2,_,x,0,_,_,_ ), 0 , 11 , 0 , 207, 189), // #1335 - INST(Vpdpwuuds , VexRvm_Lx , V(000F38,D3,_,x,0,_,_,_ ), 0 , 11 , 0 , 207, 189), // #1336 - INST(Vperm2f128 , VexRvmi , V(660F3A,06,_,1,0,_,_,_ ), 0 , 174, 0 , 383, 149), // #1337 - INST(Vperm2i128 , VexRvmi , V(660F3A,46,_,1,0,_,_,_ ), 0 , 174, 0 , 383, 156), // #1338 - INST(Vpermb , VexRvm_Lx , E(660F38,8D,_,x,_,0,4,FVM), 0 , 115, 0 , 364, 190), // #1339 - INST(Vpermd , VexRvm_Lx , V(660F38,36,_,x,0,0,4,FV ), 0 , 111, 0 , 384, 169), // #1340 - INST(Vpermi2b , VexRvm_Lx , E(660F38,75,_,x,_,0,4,FVM), 0 , 115, 0 , 364, 190), // #1341 - INST(Vpermi2d , VexRvm_Lx , E(660F38,76,_,x,_,0,4,FV ), 0 , 115, 0 , 219, 152), // #1342 - INST(Vpermi2pd , VexRvm_Lx , E(660F38,77,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1343 - INST(Vpermi2ps , VexRvm_Lx , E(660F38,77,_,x,_,0,4,FV ), 0 , 115, 0 , 219, 152), // #1344 - INST(Vpermi2q , VexRvm_Lx , E(660F38,76,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1345 - INST(Vpermi2w , VexRvm_Lx , E(660F38,75,_,x,_,1,4,FVM), 0 , 114, 0 , 364, 163), // #1346 - INST(Vpermil2pd , VexRvrmiRvmri_Lx , V(660F3A,49,_,x,x,_,_,_ ), 0 , 75 , 0 , 385, 168), // #1347 - INST(Vpermil2ps , VexRvrmiRvmri_Lx , V(660F3A,48,_,x,x,_,_,_ ), 0 , 75 , 0 , 385, 168), // #1348 - INST(Vpermilpd , VexRvmRmi_Lx , V(660F38,0D,_,x,0,1,4,FV ), V(660F3A,05,_,x,0,1,4,FV ), 211, 112, 386, 145), // #1349 - INST(Vpermilps , VexRvmRmi_Lx , V(660F38,0C,_,x,0,0,4,FV ), V(660F3A,04,_,x,0,0,4,FV ), 111, 113, 387, 145), // #1350 - INST(Vpermpd , VexRvmRmi_Lx , E(660F38,16,_,x,1,1,4,FV ), V(660F3A,01,_,x,1,1,4,FV ), 214, 114, 388, 169), // #1351 - INST(Vpermps , VexRvm_Lx , V(660F38,16,_,x,0,0,4,FV ), 0 , 111, 0 , 384, 169), // #1352 - INST(Vpermq , VexRvmRmi_Lx , E(660F38,36,_,x,_,1,4,FV ), V(660F3A,00,_,x,1,1,4,FV ), 114, 115, 388, 169), // #1353 - INST(Vpermt2b , VexRvm_Lx , E(660F38,7D,_,x,_,0,4,FVM), 0 , 115, 0 , 364, 190), // #1354 - INST(Vpermt2d , VexRvm_Lx , E(660F38,7E,_,x,_,0,4,FV ), 0 , 115, 0 , 219, 152), // #1355 - INST(Vpermt2pd , VexRvm_Lx , E(660F38,7F,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1356 - INST(Vpermt2ps , VexRvm_Lx , E(660F38,7F,_,x,_,0,4,FV ), 0 , 115, 0 , 219, 152), // #1357 - INST(Vpermt2q , VexRvm_Lx , E(660F38,7E,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1358 - INST(Vpermt2w , VexRvm_Lx , E(660F38,7D,_,x,_,1,4,FVM), 0 , 114, 0 , 364, 163), // #1359 - INST(Vpermw , VexRvm_Lx , E(660F38,8D,_,x,_,1,4,FVM), 0 , 114, 0 , 364, 163), // #1360 - INST(Vpexpandb , VexRm_Lx , E(660F38,62,_,x,_,0,0,T1S), 0 , 212, 0 , 287, 186), // #1361 - INST(Vpexpandd , VexRm_Lx , E(660F38,89,_,x,_,0,2,T1S), 0 , 130, 0 , 287, 152), // #1362 - INST(Vpexpandq , VexRm_Lx , E(660F38,89,_,x,_,1,3,T1S), 0 , 129, 0 , 287, 152), // #1363 - INST(Vpexpandw , VexRm_Lx , E(660F38,62,_,x,_,1,1,T1S), 0 , 213, 0 , 287, 186), // #1364 - INST(Vpextrb , VexMri , V(660F3A,14,_,0,0,I,0,T1S), 0 , 75 , 0 , 389, 191), // #1365 - INST(Vpextrd , VexMri , V(660F3A,16,_,0,0,0,2,T1S), 0 , 179, 0 , 291, 192), // #1366 - INST(Vpextrq , VexMri , V(660F3A,16,_,0,1,1,3,T1S), 0 , 215, 0 , 390, 192), // #1367 - INST(Vpextrw , VexMri_Vpextrw , V(660F3A,15,_,0,0,I,1,T1S), 0 , 216, 0 , 391, 191), // #1368 - INST(Vpgatherdd , VexRmvRm_VM , V(660F38,90,_,x,0,_,_,_ ), E(660F38,90,_,x,_,0,2,T1S), 30 , 116, 310, 169), // #1369 - INST(Vpgatherdq , VexRmvRm_VM , V(660F38,90,_,x,1,_,_,_ ), E(660F38,90,_,x,_,1,3,T1S), 191, 117, 309, 169), // #1370 - INST(Vpgatherqd , VexRmvRm_VM , V(660F38,91,_,x,0,_,_,_ ), E(660F38,91,_,x,_,0,2,T1S), 30 , 118, 315, 169), // #1371 - INST(Vpgatherqq , VexRmvRm_VM , V(660F38,91,_,x,1,_,_,_ ), E(660F38,91,_,x,_,1,3,T1S), 191, 119, 314, 169), // #1372 - INST(Vphaddbd , VexRm , V(XOP_M9,C2,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1373 - INST(Vphaddbq , VexRm , V(XOP_M9,C3,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1374 - INST(Vphaddbw , VexRm , V(XOP_M9,C1,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1375 - INST(Vphaddd , VexRvm_Lx , V(660F38,02,_,x,I,_,_,_ ), 0 , 30 , 0 , 207, 178), // #1376 - INST(Vphadddq , VexRm , V(XOP_M9,CB,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1377 - INST(Vphaddsw , VexRvm_Lx , V(660F38,03,_,x,I,_,_,_ ), 0 , 30 , 0 , 207, 178), // #1378 - INST(Vphaddubd , VexRm , V(XOP_M9,D2,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1379 - INST(Vphaddubq , VexRm , V(XOP_M9,D3,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1380 - INST(Vphaddubw , VexRm , V(XOP_M9,D1,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1381 - INST(Vphaddudq , VexRm , V(XOP_M9,DB,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1382 - INST(Vphadduwd , VexRm , V(XOP_M9,D6,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1383 - INST(Vphadduwq , VexRm , V(XOP_M9,D7,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1384 - INST(Vphaddw , VexRvm_Lx , V(660F38,01,_,x,I,_,_,_ ), 0 , 30 , 0 , 207, 178), // #1385 - INST(Vphaddwd , VexRm , V(XOP_M9,C6,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1386 - INST(Vphaddwq , VexRm , V(XOP_M9,C7,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1387 - INST(Vphminposuw , VexRm , V(660F38,41,_,0,I,_,_,_ ), 0 , 30 , 0 , 209, 149), // #1388 - INST(Vphsubbw , VexRm , V(XOP_M9,E1,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1389 - INST(Vphsubd , VexRvm_Lx , V(660F38,06,_,x,I,_,_,_ ), 0 , 30 , 0 , 207, 178), // #1390 - INST(Vphsubdq , VexRm , V(XOP_M9,E3,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1391 - INST(Vphsubsw , VexRvm_Lx , V(660F38,07,_,x,I,_,_,_ ), 0 , 30 , 0 , 207, 178), // #1392 - INST(Vphsubw , VexRvm_Lx , V(660F38,05,_,x,I,_,_,_ ), 0 , 30 , 0 , 207, 178), // #1393 - INST(Vphsubwd , VexRm , V(XOP_M9,E2,_,0,0,_,_,_ ), 0 , 81 , 0 , 209, 168), // #1394 - INST(Vpinsrb , VexRvmi , V(660F3A,20,_,0,0,I,0,T1S), 0 , 75 , 0 , 392, 191), // #1395 - INST(Vpinsrd , VexRvmi , V(660F3A,22,_,0,0,0,2,T1S), 0 , 179, 0 , 393, 192), // #1396 - INST(Vpinsrq , VexRvmi , V(660F3A,22,_,0,1,1,3,T1S), 0 , 215, 0 , 394, 192), // #1397 - INST(Vpinsrw , VexRvmi , V(660F00,C4,_,0,0,I,1,T1S), 0 , 217, 0 , 395, 191), // #1398 - INST(Vplzcntd , VexRm_Lx , E(660F38,44,_,x,_,0,4,FV ), 0 , 115, 0 , 381, 183), // #1399 - INST(Vplzcntq , VexRm_Lx , E(660F38,44,_,x,_,1,4,FV ), 0 , 114, 0 , 357, 183), // #1400 - INST(Vpmacsdd , VexRvmr , V(XOP_M8,9E,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1401 - INST(Vpmacsdqh , VexRvmr , V(XOP_M8,9F,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1402 - INST(Vpmacsdql , VexRvmr , V(XOP_M8,97,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1403 - INST(Vpmacssdd , VexRvmr , V(XOP_M8,8E,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1404 - INST(Vpmacssdqh , VexRvmr , V(XOP_M8,8F,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1405 - INST(Vpmacssdql , VexRvmr , V(XOP_M8,87,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1406 - INST(Vpmacsswd , VexRvmr , V(XOP_M8,86,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1407 - INST(Vpmacssww , VexRvmr , V(XOP_M8,85,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1408 - INST(Vpmacswd , VexRvmr , V(XOP_M8,96,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1409 - INST(Vpmacsww , VexRvmr , V(XOP_M8,95,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1410 - INST(Vpmadcsswd , VexRvmr , V(XOP_M8,A6,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1411 - INST(Vpmadcswd , VexRvmr , V(XOP_M8,B6,_,0,0,_,_,_ ), 0 , 210, 0 , 396, 168), // #1412 - INST(Vpmadd52huq , VexRvm_Lx , V(660F38,B5,_,x,1,1,4,FV ), 0 , 184, 0 , 397, 193), // #1413 - INST(Vpmadd52luq , VexRvm_Lx , V(660F38,B4,_,x,1,1,4,FV ), 0 , 184, 0 , 397, 193), // #1414 - INST(Vpmaddubsw , VexRvm_Lx , V(660F38,04,_,x,I,I,4,FVM), 0 , 111, 0 , 323, 181), // #1415 - INST(Vpmaddwd , VexRvm_Lx , V(660F00,F5,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1416 - INST(Vpmaskmovd , VexRvmMvr_Lx , V(660F38,8C,_,x,0,_,_,_ ), V(660F38,8E,_,x,0,_,_,_ ), 30 , 120, 330, 156), // #1417 - INST(Vpmaskmovq , VexRvmMvr_Lx , V(660F38,8C,_,x,1,_,_,_ ), V(660F38,8E,_,x,1,_,_,_ ), 191, 121, 330, 156), // #1418 - INST(Vpmaxsb , VexRvm_Lx , V(660F38,3C,_,x,I,I,4,FVM), 0 , 111, 0 , 398, 181), // #1419 - INST(Vpmaxsd , VexRvm_Lx , V(660F38,3D,_,x,I,0,4,FV ), 0 , 111, 0 , 216, 157), // #1420 - INST(Vpmaxsq , VexRvm_Lx , E(660F38,3D,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1421 - INST(Vpmaxsw , VexRvm_Lx , V(660F00,EE,_,x,I,I,4,FVM), 0 , 145, 0 , 398, 181), // #1422 - INST(Vpmaxub , VexRvm_Lx , V(660F00,DE,_,x,I,I,4,FVM), 0 , 145, 0 , 398, 181), // #1423 - INST(Vpmaxud , VexRvm_Lx , V(660F38,3F,_,x,I,0,4,FV ), 0 , 111, 0 , 216, 157), // #1424 - INST(Vpmaxuq , VexRvm_Lx , E(660F38,3F,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1425 - INST(Vpmaxuw , VexRvm_Lx , V(660F38,3E,_,x,I,I,4,FVM), 0 , 111, 0 , 398, 181), // #1426 - INST(Vpminsb , VexRvm_Lx , V(660F38,38,_,x,I,I,4,FVM), 0 , 111, 0 , 398, 181), // #1427 - INST(Vpminsd , VexRvm_Lx , V(660F38,39,_,x,I,0,4,FV ), 0 , 111, 0 , 216, 157), // #1428 - INST(Vpminsq , VexRvm_Lx , E(660F38,39,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1429 - INST(Vpminsw , VexRvm_Lx , V(660F00,EA,_,x,I,I,4,FVM), 0 , 145, 0 , 398, 181), // #1430 - INST(Vpminub , VexRvm_Lx , V(660F00,DA,_,x,I,_,4,FVM), 0 , 145, 0 , 398, 181), // #1431 - INST(Vpminud , VexRvm_Lx , V(660F38,3B,_,x,I,0,4,FV ), 0 , 111, 0 , 216, 157), // #1432 - INST(Vpminuq , VexRvm_Lx , E(660F38,3B,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1433 - INST(Vpminuw , VexRvm_Lx , V(660F38,3A,_,x,I,_,4,FVM), 0 , 111, 0 , 398, 181), // #1434 - INST(Vpmovb2m , VexRm_Lx , E(F30F38,29,_,x,_,0,_,_ ), 0 , 208, 0 , 399, 163), // #1435 - INST(Vpmovd2m , VexRm_Lx , E(F30F38,39,_,x,_,0,_,_ ), 0 , 208, 0 , 399, 155), // #1436 - INST(Vpmovdb , VexMr_Lx , E(F30F38,31,_,x,_,0,2,QVM), 0 , 218, 0 , 400, 152), // #1437 - INST(Vpmovdw , VexMr_Lx , E(F30F38,33,_,x,_,0,3,HVM), 0 , 219, 0 , 401, 152), // #1438 - INST(Vpmovm2b , VexRm_Lx , E(F30F38,28,_,x,_,0,_,_ ), 0 , 208, 0 , 367, 163), // #1439 - INST(Vpmovm2d , VexRm_Lx , E(F30F38,38,_,x,_,0,_,_ ), 0 , 208, 0 , 367, 155), // #1440 - INST(Vpmovm2q , VexRm_Lx , E(F30F38,38,_,x,_,1,_,_ ), 0 , 207, 0 , 367, 155), // #1441 - INST(Vpmovm2w , VexRm_Lx , E(F30F38,28,_,x,_,1,_,_ ), 0 , 207, 0 , 367, 163), // #1442 - INST(Vpmovmskb , VexRm_Lx , V(660F00,D7,_,x,I,_,_,_ ), 0 , 71 , 0 , 343, 178), // #1443 - INST(Vpmovq2m , VexRm_Lx , E(F30F38,39,_,x,_,1,_,_ ), 0 , 207, 0 , 399, 155), // #1444 - INST(Vpmovqb , VexMr_Lx , E(F30F38,32,_,x,_,0,1,OVM), 0 , 220, 0 , 402, 152), // #1445 - INST(Vpmovqd , VexMr_Lx , E(F30F38,35,_,x,_,0,3,HVM), 0 , 219, 0 , 401, 152), // #1446 - INST(Vpmovqw , VexMr_Lx , E(F30F38,34,_,x,_,0,2,QVM), 0 , 218, 0 , 400, 152), // #1447 - INST(Vpmovsdb , VexMr_Lx , E(F30F38,21,_,x,_,0,2,QVM), 0 , 218, 0 , 400, 152), // #1448 - INST(Vpmovsdw , VexMr_Lx , E(F30F38,23,_,x,_,0,3,HVM), 0 , 219, 0 , 401, 152), // #1449 - INST(Vpmovsqb , VexMr_Lx , E(F30F38,22,_,x,_,0,1,OVM), 0 , 220, 0 , 402, 152), // #1450 - INST(Vpmovsqd , VexMr_Lx , E(F30F38,25,_,x,_,0,3,HVM), 0 , 219, 0 , 401, 152), // #1451 - INST(Vpmovsqw , VexMr_Lx , E(F30F38,24,_,x,_,0,2,QVM), 0 , 218, 0 , 400, 152), // #1452 - INST(Vpmovswb , VexMr_Lx , E(F30F38,20,_,x,_,0,3,HVM), 0 , 219, 0 , 401, 163), // #1453 - INST(Vpmovsxbd , VexRm_Lx , V(660F38,21,_,x,I,I,2,QVM), 0 , 221, 0 , 403, 157), // #1454 - INST(Vpmovsxbq , VexRm_Lx , V(660F38,22,_,x,I,I,1,OVM), 0 , 222, 0 , 404, 157), // #1455 - INST(Vpmovsxbw , VexRm_Lx , V(660F38,20,_,x,I,I,3,HVM), 0 , 140, 0 , 405, 181), // #1456 - INST(Vpmovsxdq , VexRm_Lx , V(660F38,25,_,x,I,0,3,HVM), 0 , 140, 0 , 405, 157), // #1457 - INST(Vpmovsxwd , VexRm_Lx , V(660F38,23,_,x,I,I,3,HVM), 0 , 140, 0 , 405, 157), // #1458 - INST(Vpmovsxwq , VexRm_Lx , V(660F38,24,_,x,I,I,2,QVM), 0 , 221, 0 , 403, 157), // #1459 - INST(Vpmovusdb , VexMr_Lx , E(F30F38,11,_,x,_,0,2,QVM), 0 , 218, 0 , 400, 152), // #1460 - INST(Vpmovusdw , VexMr_Lx , E(F30F38,13,_,x,_,0,3,HVM), 0 , 219, 0 , 401, 152), // #1461 - INST(Vpmovusqb , VexMr_Lx , E(F30F38,12,_,x,_,0,1,OVM), 0 , 220, 0 , 402, 152), // #1462 - INST(Vpmovusqd , VexMr_Lx , E(F30F38,15,_,x,_,0,3,HVM), 0 , 219, 0 , 401, 152), // #1463 - INST(Vpmovusqw , VexMr_Lx , E(F30F38,14,_,x,_,0,2,QVM), 0 , 218, 0 , 400, 152), // #1464 - INST(Vpmovuswb , VexMr_Lx , E(F30F38,10,_,x,_,0,3,HVM), 0 , 219, 0 , 401, 163), // #1465 - INST(Vpmovw2m , VexRm_Lx , E(F30F38,29,_,x,_,1,_,_ ), 0 , 207, 0 , 399, 163), // #1466 - INST(Vpmovwb , VexMr_Lx , E(F30F38,30,_,x,_,0,3,HVM), 0 , 219, 0 , 401, 163), // #1467 - INST(Vpmovzxbd , VexRm_Lx , V(660F38,31,_,x,I,I,2,QVM), 0 , 221, 0 , 403, 157), // #1468 - INST(Vpmovzxbq , VexRm_Lx , V(660F38,32,_,x,I,I,1,OVM), 0 , 222, 0 , 404, 157), // #1469 - INST(Vpmovzxbw , VexRm_Lx , V(660F38,30,_,x,I,I,3,HVM), 0 , 140, 0 , 405, 181), // #1470 - INST(Vpmovzxdq , VexRm_Lx , V(660F38,35,_,x,I,0,3,HVM), 0 , 140, 0 , 405, 157), // #1471 - INST(Vpmovzxwd , VexRm_Lx , V(660F38,33,_,x,I,I,3,HVM), 0 , 140, 0 , 405, 157), // #1472 - INST(Vpmovzxwq , VexRm_Lx , V(660F38,34,_,x,I,I,2,QVM), 0 , 221, 0 , 403, 157), // #1473 - INST(Vpmuldq , VexRvm_Lx , V(660F38,28,_,x,I,1,4,FV ), 0 , 211, 0 , 213, 157), // #1474 - INST(Vpmulhrsw , VexRvm_Lx , V(660F38,0B,_,x,I,I,4,FVM), 0 , 111, 0 , 323, 181), // #1475 - INST(Vpmulhuw , VexRvm_Lx , V(660F00,E4,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1476 - INST(Vpmulhw , VexRvm_Lx , V(660F00,E5,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1477 - INST(Vpmulld , VexRvm_Lx , V(660F38,40,_,x,I,0,4,FV ), 0 , 111, 0 , 214, 157), // #1478 - INST(Vpmullq , VexRvm_Lx , E(660F38,40,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 155), // #1479 - INST(Vpmullw , VexRvm_Lx , V(660F00,D5,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1480 - INST(Vpmultishiftqb , VexRvm_Lx , E(660F38,83,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 190), // #1481 - INST(Vpmuludq , VexRvm_Lx , V(660F00,F4,_,x,I,1,4,FV ), 0 , 104, 0 , 213, 157), // #1482 - INST(Vpopcntb , VexRm_Lx , E(660F38,54,_,x,_,0,4,FV ), 0 , 115, 0 , 287, 194), // #1483 - INST(Vpopcntd , VexRm_Lx , E(660F38,55,_,x,_,0,4,FVM), 0 , 115, 0 , 381, 195), // #1484 - INST(Vpopcntq , VexRm_Lx , E(660F38,55,_,x,_,1,4,FVM), 0 , 114, 0 , 357, 195), // #1485 - INST(Vpopcntw , VexRm_Lx , E(660F38,54,_,x,_,1,4,FV ), 0 , 114, 0 , 287, 194), // #1486 - INST(Vpor , VexRvm_Lx , V(660F00,EB,_,x,I,_,_,_ ), 0 , 71 , 0 , 358, 178), // #1487 - INST(Vpord , VexRvm_Lx , E(660F00,EB,_,x,_,0,4,FV ), 0 , 200, 0 , 359, 152), // #1488 - INST(Vporq , VexRvm_Lx , E(660F00,EB,_,x,_,1,4,FV ), 0 , 136, 0 , 363, 152), // #1489 - INST(Vpperm , VexRvrmRvmr , V(XOP_M8,A3,_,0,x,_,_,_ ), 0 , 210, 0 , 406, 168), // #1490 - INST(Vprold , VexVmi_Lx , E(660F00,72,1,x,_,0,4,FV ), 0 , 223, 0 , 407, 152), // #1491 - INST(Vprolq , VexVmi_Lx , E(660F00,72,1,x,_,1,4,FV ), 0 , 224, 0 , 408, 152), // #1492 - INST(Vprolvd , VexRvm_Lx , E(660F38,15,_,x,_,0,4,FV ), 0 , 115, 0 , 219, 152), // #1493 - INST(Vprolvq , VexRvm_Lx , E(660F38,15,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1494 - INST(Vprord , VexVmi_Lx , E(660F00,72,0,x,_,0,4,FV ), 0 , 200, 0 , 407, 152), // #1495 - INST(Vprorq , VexVmi_Lx , E(660F00,72,0,x,_,1,4,FV ), 0 , 136, 0 , 408, 152), // #1496 - INST(Vprorvd , VexRvm_Lx , E(660F38,14,_,x,_,0,4,FV ), 0 , 115, 0 , 219, 152), // #1497 - INST(Vprorvq , VexRvm_Lx , E(660F38,14,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1498 - INST(Vprotb , VexRvmRmvRmi , V(XOP_M9,90,_,0,x,_,_,_ ), V(XOP_M8,C0,_,0,x,_,_,_ ), 81 , 122, 409, 168), // #1499 - INST(Vprotd , VexRvmRmvRmi , V(XOP_M9,92,_,0,x,_,_,_ ), V(XOP_M8,C2,_,0,x,_,_,_ ), 81 , 123, 409, 168), // #1500 - INST(Vprotq , VexRvmRmvRmi , V(XOP_M9,93,_,0,x,_,_,_ ), V(XOP_M8,C3,_,0,x,_,_,_ ), 81 , 124, 409, 168), // #1501 - INST(Vprotw , VexRvmRmvRmi , V(XOP_M9,91,_,0,x,_,_,_ ), V(XOP_M8,C1,_,0,x,_,_,_ ), 81 , 125, 409, 168), // #1502 - INST(Vpsadbw , VexRvm_Lx , V(660F00,F6,_,x,I,I,4,FVM), 0 , 145, 0 , 208, 181), // #1503 - INST(Vpscatterdd , VexMr_VM , E(660F38,A0,_,x,_,0,2,T1S), 0 , 130, 0 , 410, 152), // #1504 - INST(Vpscatterdq , VexMr_VM , E(660F38,A0,_,x,_,1,3,T1S), 0 , 129, 0 , 411, 152), // #1505 - INST(Vpscatterqd , VexMr_VM , E(660F38,A1,_,x,_,0,2,T1S), 0 , 130, 0 , 412, 152), // #1506 - INST(Vpscatterqq , VexMr_VM , E(660F38,A1,_,x,_,1,3,T1S), 0 , 129, 0 , 413, 152), // #1507 - INST(Vpshab , VexRvmRmv , V(XOP_M9,98,_,0,x,_,_,_ ), 0 , 81 , 0 , 414, 168), // #1508 - INST(Vpshad , VexRvmRmv , V(XOP_M9,9A,_,0,x,_,_,_ ), 0 , 81 , 0 , 414, 168), // #1509 - INST(Vpshaq , VexRvmRmv , V(XOP_M9,9B,_,0,x,_,_,_ ), 0 , 81 , 0 , 414, 168), // #1510 - INST(Vpshaw , VexRvmRmv , V(XOP_M9,99,_,0,x,_,_,_ ), 0 , 81 , 0 , 414, 168), // #1511 - INST(Vpshlb , VexRvmRmv , V(XOP_M9,94,_,0,x,_,_,_ ), 0 , 81 , 0 , 414, 168), // #1512 - INST(Vpshld , VexRvmRmv , V(XOP_M9,96,_,0,x,_,_,_ ), 0 , 81 , 0 , 414, 168), // #1513 - INST(Vpshldd , VexRvmi_Lx , E(660F3A,71,_,x,_,0,4,FV ), 0 , 112, 0 , 211, 186), // #1514 - INST(Vpshldq , VexRvmi_Lx , E(660F3A,71,_,x,_,1,4,FV ), 0 , 113, 0 , 212, 186), // #1515 - INST(Vpshldvd , VexRvm_Lx , E(660F38,71,_,x,_,0,4,FV ), 0 , 115, 0 , 219, 186), // #1516 - INST(Vpshldvq , VexRvm_Lx , E(660F38,71,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 186), // #1517 - INST(Vpshldvw , VexRvm_Lx , E(660F38,70,_,x,_,1,4,FVM), 0 , 114, 0 , 364, 186), // #1518 - INST(Vpshldw , VexRvmi_Lx , E(660F3A,70,_,x,_,1,4,FVM), 0 , 113, 0 , 283, 186), // #1519 - INST(Vpshlq , VexRvmRmv , V(XOP_M9,97,_,0,x,_,_,_ ), 0 , 81 , 0 , 414, 168), // #1520 - INST(Vpshlw , VexRvmRmv , V(XOP_M9,95,_,0,x,_,_,_ ), 0 , 81 , 0 , 414, 168), // #1521 - INST(Vpshrdd , VexRvmi_Lx , E(660F3A,73,_,x,_,0,4,FV ), 0 , 112, 0 , 211, 186), // #1522 - INST(Vpshrdq , VexRvmi_Lx , E(660F3A,73,_,x,_,1,4,FV ), 0 , 113, 0 , 212, 186), // #1523 - INST(Vpshrdvd , VexRvm_Lx , E(660F38,73,_,x,_,0,4,FV ), 0 , 115, 0 , 219, 186), // #1524 - INST(Vpshrdvq , VexRvm_Lx , E(660F38,73,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 186), // #1525 - INST(Vpshrdvw , VexRvm_Lx , E(660F38,72,_,x,_,1,4,FVM), 0 , 114, 0 , 364, 186), // #1526 - INST(Vpshrdw , VexRvmi_Lx , E(660F3A,72,_,x,_,1,4,FVM), 0 , 113, 0 , 283, 186), // #1527 - INST(Vpshufb , VexRvm_Lx , V(660F38,00,_,x,I,I,4,FVM), 0 , 111, 0 , 323, 181), // #1528 - INST(Vpshufbitqmb , VexRvm_Lx , E(660F38,8F,_,x,0,0,4,FVM), 0 , 115, 0 , 415, 194), // #1529 - INST(Vpshufd , VexRmi_Lx , V(660F00,70,_,x,I,0,4,FV ), 0 , 145, 0 , 416, 157), // #1530 - INST(Vpshufhw , VexRmi_Lx , V(F30F00,70,_,x,I,I,4,FVM), 0 , 162, 0 , 417, 181), // #1531 - INST(Vpshuflw , VexRmi_Lx , V(F20F00,70,_,x,I,I,4,FVM), 0 , 225, 0 , 417, 181), // #1532 - INST(Vpsignb , VexRvm_Lx , V(660F38,08,_,x,I,_,_,_ ), 0 , 30 , 0 , 207, 178), // #1533 - INST(Vpsignd , VexRvm_Lx , V(660F38,0A,_,x,I,_,_,_ ), 0 , 30 , 0 , 207, 178), // #1534 - INST(Vpsignw , VexRvm_Lx , V(660F38,09,_,x,I,_,_,_ ), 0 , 30 , 0 , 207, 178), // #1535 - INST(Vpslld , VexRvmVmi_Lx_MEvex , V(660F00,F2,_,x,I,0,4,128), V(660F00,72,6,x,I,0,4,FV ), 226, 126, 418, 157), // #1536 - INST(Vpslldq , VexVmi_Lx_MEvex , V(660F00,73,7,x,I,I,4,FVM), 0 , 227, 0 , 419, 181), // #1537 - INST(Vpsllq , VexRvmVmi_Lx_MEvex , V(660F00,F3,_,x,I,1,4,128), V(660F00,73,6,x,I,1,4,FV ), 228, 127, 420, 157), // #1538 - INST(Vpsllvd , VexRvm_Lx , V(660F38,47,_,x,0,0,4,FV ), 0 , 111, 0 , 214, 169), // #1539 - INST(Vpsllvq , VexRvm_Lx , V(660F38,47,_,x,1,1,4,FV ), 0 , 184, 0 , 213, 169), // #1540 - INST(Vpsllvw , VexRvm_Lx , E(660F38,12,_,x,_,1,4,FVM), 0 , 114, 0 , 364, 163), // #1541 - INST(Vpsllw , VexRvmVmi_Lx_MEvex , V(660F00,F1,_,x,I,I,4,128), V(660F00,71,6,x,I,I,4,FVM), 226, 128, 421, 181), // #1542 - INST(Vpsrad , VexRvmVmi_Lx_MEvex , V(660F00,E2,_,x,I,0,4,128), V(660F00,72,4,x,I,0,4,FV ), 226, 129, 418, 157), // #1543 - INST(Vpsraq , VexRvmVmi_Lx_MEvex , E(660F00,E2,_,x,_,1,4,128), E(660F00,72,4,x,_,1,4,FV ), 229, 130, 422, 152), // #1544 - INST(Vpsravd , VexRvm_Lx , V(660F38,46,_,x,0,0,4,FV ), 0 , 111, 0 , 214, 169), // #1545 - INST(Vpsravq , VexRvm_Lx , E(660F38,46,_,x,_,1,4,FV ), 0 , 114, 0 , 218, 152), // #1546 - INST(Vpsravw , VexRvm_Lx , E(660F38,11,_,x,_,1,4,FVM), 0 , 114, 0 , 364, 163), // #1547 - INST(Vpsraw , VexRvmVmi_Lx_MEvex , V(660F00,E1,_,x,I,I,4,128), V(660F00,71,4,x,I,I,4,FVM), 226, 131, 421, 181), // #1548 - INST(Vpsrld , VexRvmVmi_Lx_MEvex , V(660F00,D2,_,x,I,0,4,128), V(660F00,72,2,x,I,0,4,FV ), 226, 132, 418, 157), // #1549 - INST(Vpsrldq , VexVmi_Lx_MEvex , V(660F00,73,3,x,I,I,4,FVM), 0 , 230, 0 , 419, 181), // #1550 - INST(Vpsrlq , VexRvmVmi_Lx_MEvex , V(660F00,D3,_,x,I,1,4,128), V(660F00,73,2,x,I,1,4,FV ), 228, 133, 420, 157), // #1551 - INST(Vpsrlvd , VexRvm_Lx , V(660F38,45,_,x,0,0,4,FV ), 0 , 111, 0 , 214, 169), // #1552 - INST(Vpsrlvq , VexRvm_Lx , V(660F38,45,_,x,1,1,4,FV ), 0 , 184, 0 , 213, 169), // #1553 - INST(Vpsrlvw , VexRvm_Lx , E(660F38,10,_,x,_,1,4,FVM), 0 , 114, 0 , 364, 163), // #1554 - INST(Vpsrlw , VexRvmVmi_Lx_MEvex , V(660F00,D1,_,x,I,I,4,128), V(660F00,71,2,x,I,I,4,FVM), 226, 134, 421, 181), // #1555 - INST(Vpsubb , VexRvm_Lx , V(660F00,F8,_,x,I,I,4,FVM), 0 , 145, 0 , 423, 181), // #1556 - INST(Vpsubd , VexRvm_Lx , V(660F00,FA,_,x,I,0,4,FV ), 0 , 145, 0 , 424, 157), // #1557 - INST(Vpsubq , VexRvm_Lx , V(660F00,FB,_,x,I,1,4,FV ), 0 , 104, 0 , 425, 157), // #1558 - INST(Vpsubsb , VexRvm_Lx , V(660F00,E8,_,x,I,I,4,FVM), 0 , 145, 0 , 423, 181), // #1559 - INST(Vpsubsw , VexRvm_Lx , V(660F00,E9,_,x,I,I,4,FVM), 0 , 145, 0 , 423, 181), // #1560 - INST(Vpsubusb , VexRvm_Lx , V(660F00,D8,_,x,I,I,4,FVM), 0 , 145, 0 , 423, 181), // #1561 - INST(Vpsubusw , VexRvm_Lx , V(660F00,D9,_,x,I,I,4,FVM), 0 , 145, 0 , 423, 181), // #1562 - INST(Vpsubw , VexRvm_Lx , V(660F00,F9,_,x,I,I,4,FVM), 0 , 145, 0 , 423, 181), // #1563 - INST(Vpternlogd , VexRvmi_Lx , E(660F3A,25,_,x,_,0,4,FV ), 0 , 112, 0 , 211, 152), // #1564 - INST(Vpternlogq , VexRvmi_Lx , E(660F3A,25,_,x,_,1,4,FV ), 0 , 113, 0 , 212, 152), // #1565 - INST(Vptest , VexRm_Lx , V(660F38,17,_,x,I,_,_,_ ), 0 , 30 , 0 , 306, 185), // #1566 - INST(Vptestmb , VexRvm_Lx , E(660F38,26,_,x,_,0,4,FVM), 0 , 115, 0 , 415, 163), // #1567 - INST(Vptestmd , VexRvm_Lx , E(660F38,27,_,x,_,0,4,FV ), 0 , 115, 0 , 426, 152), // #1568 - INST(Vptestmq , VexRvm_Lx , E(660F38,27,_,x,_,1,4,FV ), 0 , 114, 0 , 427, 152), // #1569 - INST(Vptestmw , VexRvm_Lx , E(660F38,26,_,x,_,1,4,FVM), 0 , 114, 0 , 415, 163), // #1570 - INST(Vptestnmb , VexRvm_Lx , E(F30F38,26,_,x,_,0,4,FVM), 0 , 171, 0 , 415, 163), // #1571 - INST(Vptestnmd , VexRvm_Lx , E(F30F38,27,_,x,_,0,4,FV ), 0 , 171, 0 , 426, 152), // #1572 - INST(Vptestnmq , VexRvm_Lx , E(F30F38,27,_,x,_,1,4,FV ), 0 , 231, 0 , 427, 152), // #1573 - INST(Vptestnmw , VexRvm_Lx , E(F30F38,26,_,x,_,1,4,FVM), 0 , 231, 0 , 415, 163), // #1574 - INST(Vpunpckhbw , VexRvm_Lx , V(660F00,68,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1575 - INST(Vpunpckhdq , VexRvm_Lx , V(660F00,6A,_,x,I,0,4,FV ), 0 , 145, 0 , 214, 157), // #1576 - INST(Vpunpckhqdq , VexRvm_Lx , V(660F00,6D,_,x,I,1,4,FV ), 0 , 104, 0 , 213, 157), // #1577 - INST(Vpunpckhwd , VexRvm_Lx , V(660F00,69,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1578 - INST(Vpunpcklbw , VexRvm_Lx , V(660F00,60,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1579 - INST(Vpunpckldq , VexRvm_Lx , V(660F00,62,_,x,I,0,4,FV ), 0 , 145, 0 , 214, 157), // #1580 - INST(Vpunpcklqdq , VexRvm_Lx , V(660F00,6C,_,x,I,1,4,FV ), 0 , 104, 0 , 213, 157), // #1581 - INST(Vpunpcklwd , VexRvm_Lx , V(660F00,61,_,x,I,I,4,FVM), 0 , 145, 0 , 323, 181), // #1582 - INST(Vpxor , VexRvm_Lx , V(660F00,EF,_,x,I,_,_,_ ), 0 , 71 , 0 , 360, 178), // #1583 - INST(Vpxord , VexRvm_Lx , E(660F00,EF,_,x,_,0,4,FV ), 0 , 200, 0 , 361, 152), // #1584 - INST(Vpxorq , VexRvm_Lx , E(660F00,EF,_,x,_,1,4,FV ), 0 , 136, 0 , 362, 152), // #1585 - INST(Vrangepd , VexRvmi_Lx , E(660F3A,50,_,x,_,1,4,FV ), 0 , 113, 0 , 293, 155), // #1586 - INST(Vrangeps , VexRvmi_Lx , E(660F3A,50,_,x,_,0,4,FV ), 0 , 112, 0 , 294, 155), // #1587 - INST(Vrangesd , VexRvmi , E(660F3A,51,_,I,_,1,3,T1S), 0 , 182, 0 , 295, 76 ), // #1588 - INST(Vrangess , VexRvmi , E(660F3A,51,_,I,_,0,2,T1S), 0 , 183, 0 , 296, 76 ), // #1589 - INST(Vrcp14pd , VexRm_Lx , E(660F38,4C,_,x,_,1,4,FV ), 0 , 114, 0 , 357, 152), // #1590 - INST(Vrcp14ps , VexRm_Lx , E(660F38,4C,_,x,_,0,4,FV ), 0 , 115, 0 , 381, 152), // #1591 - INST(Vrcp14sd , VexRvm , E(660F38,4D,_,I,_,1,3,T1S), 0 , 129, 0 , 428, 78 ), // #1592 - INST(Vrcp14ss , VexRvm , E(660F38,4D,_,I,_,0,2,T1S), 0 , 130, 0 , 429, 78 ), // #1593 - INST(Vrcp28pd , VexRm , E(660F38,CA,_,2,_,1,4,FV ), 0 , 172, 0 , 285, 164), // #1594 - INST(Vrcp28ps , VexRm , E(660F38,CA,_,2,_,0,4,FV ), 0 , 173, 0 , 286, 164), // #1595 - INST(Vrcp28sd , VexRvm , E(660F38,CB,_,I,_,1,3,T1S), 0 , 129, 0 , 316, 164), // #1596 - INST(Vrcp28ss , VexRvm , E(660F38,CB,_,I,_,0,2,T1S), 0 , 130, 0 , 317, 164), // #1597 - INST(Vrcpph , VexRm_Lx , E(66MAP6,4C,_,_,_,0,4,FV ), 0 , 185, 0 , 430, 148), // #1598 - INST(Vrcpps , VexRm_Lx , V(000F00,53,_,x,I,_,_,_ ), 0 , 74 , 0 , 306, 149), // #1599 - INST(Vrcpsh , VexRvm , E(66MAP6,4D,_,_,_,0,1,T1S), 0 , 187, 0 , 431, 148), // #1600 - INST(Vrcpss , VexRvm , V(F30F00,53,_,I,I,_,_,_ ), 0 , 201, 0 , 432, 149), // #1601 - INST(Vreducepd , VexRmi_Lx , E(660F3A,56,_,x,_,1,4,FV ), 0 , 113, 0 , 408, 155), // #1602 - INST(Vreduceph , VexRmi_Lx , E(000F3A,56,_,_,_,0,4,FV ), 0 , 124, 0 , 319, 146), // #1603 - INST(Vreduceps , VexRmi_Lx , E(660F3A,56,_,x,_,0,4,FV ), 0 , 112, 0 , 407, 155), // #1604 - INST(Vreducesd , VexRvmi , E(660F3A,57,_,I,_,1,3,T1S), 0 , 182, 0 , 433, 76 ), // #1605 - INST(Vreducesh , VexRvmi , E(000F3A,57,_,_,_,0,1,T1S), 0 , 190, 0 , 321, 148), // #1606 - INST(Vreducess , VexRvmi , E(660F3A,57,_,I,_,0,2,T1S), 0 , 183, 0 , 434, 76 ), // #1607 - INST(Vrndscalepd , VexRmi_Lx , E(660F3A,09,_,x,_,1,4,FV ), 0 , 113, 0 , 318, 152), // #1608 - INST(Vrndscaleph , VexRmi_Lx , E(000F3A,08,_,_,_,0,4,FV ), 0 , 124, 0 , 319, 146), // #1609 - INST(Vrndscaleps , VexRmi_Lx , E(660F3A,08,_,x,_,0,4,FV ), 0 , 112, 0 , 320, 152), // #1610 - INST(Vrndscalesd , VexRvmi , E(660F3A,0B,_,I,_,1,3,T1S), 0 , 182, 0 , 295, 78 ), // #1611 - INST(Vrndscalesh , VexRvmi , E(000F3A,0A,_,_,_,0,1,T1S), 0 , 190, 0 , 321, 148), // #1612 - INST(Vrndscaless , VexRvmi , E(660F3A,0A,_,I,_,0,2,T1S), 0 , 183, 0 , 296, 78 ), // #1613 - INST(Vroundpd , VexRmi_Lx , V(660F3A,09,_,x,I,_,_,_ ), 0 , 75 , 0 , 435, 149), // #1614 - INST(Vroundps , VexRmi_Lx , V(660F3A,08,_,x,I,_,_,_ ), 0 , 75 , 0 , 435, 149), // #1615 - INST(Vroundsd , VexRvmi , V(660F3A,0B,_,I,I,_,_,_ ), 0 , 75 , 0 , 436, 149), // #1616 - INST(Vroundss , VexRvmi , V(660F3A,0A,_,I,I,_,_,_ ), 0 , 75 , 0 , 437, 149), // #1617 - INST(Vrsqrt14pd , VexRm_Lx , E(660F38,4E,_,x,_,1,4,FV ), 0 , 114, 0 , 357, 152), // #1618 - INST(Vrsqrt14ps , VexRm_Lx , E(660F38,4E,_,x,_,0,4,FV ), 0 , 115, 0 , 381, 152), // #1619 - INST(Vrsqrt14sd , VexRvm , E(660F38,4F,_,I,_,1,3,T1S), 0 , 129, 0 , 428, 78 ), // #1620 - INST(Vrsqrt14ss , VexRvm , E(660F38,4F,_,I,_,0,2,T1S), 0 , 130, 0 , 429, 78 ), // #1621 - INST(Vrsqrt28pd , VexRm , E(660F38,CC,_,2,_,1,4,FV ), 0 , 172, 0 , 285, 164), // #1622 - INST(Vrsqrt28ps , VexRm , E(660F38,CC,_,2,_,0,4,FV ), 0 , 173, 0 , 286, 164), // #1623 - INST(Vrsqrt28sd , VexRvm , E(660F38,CD,_,I,_,1,3,T1S), 0 , 129, 0 , 316, 164), // #1624 - INST(Vrsqrt28ss , VexRvm , E(660F38,CD,_,I,_,0,2,T1S), 0 , 130, 0 , 317, 164), // #1625 - INST(Vrsqrtph , VexRm_Lx , E(66MAP6,4E,_,_,_,0,4,FV ), 0 , 185, 0 , 430, 146), // #1626 - INST(Vrsqrtps , VexRm_Lx , V(000F00,52,_,x,I,_,_,_ ), 0 , 74 , 0 , 306, 149), // #1627 - INST(Vrsqrtsh , VexRvm , E(66MAP6,4F,_,_,_,0,1,T1S), 0 , 187, 0 , 431, 148), // #1628 - INST(Vrsqrtss , VexRvm , V(F30F00,52,_,I,I,_,_,_ ), 0 , 201, 0 , 432, 149), // #1629 - INST(Vscalefpd , VexRvm_Lx , E(660F38,2C,_,x,_,1,4,FV ), 0 , 114, 0 , 438, 152), // #1630 - INST(Vscalefph , VexRvm_Lx , E(66MAP6,2C,_,_,_,0,4,FV ), 0 , 185, 0 , 202, 146), // #1631 - INST(Vscalefps , VexRvm_Lx , E(660F38,2C,_,x,_,0,4,FV ), 0 , 115, 0 , 292, 152), // #1632 - INST(Vscalefsd , VexRvm , E(660F38,2D,_,I,_,1,3,T1S), 0 , 129, 0 , 258, 78 ), // #1633 - INST(Vscalefsh , VexRvm , E(66MAP6,2D,_,_,_,0,1,T1S), 0 , 187, 0 , 205, 148), // #1634 - INST(Vscalefss , VexRvm , E(660F38,2D,_,I,_,0,2,T1S), 0 , 130, 0 , 266, 78 ), // #1635 - INST(Vscatterdpd , VexMr_VM , E(660F38,A2,_,x,_,1,3,T1S), 0 , 129, 0 , 411, 152), // #1636 - INST(Vscatterdps , VexMr_VM , E(660F38,A2,_,x,_,0,2,T1S), 0 , 130, 0 , 410, 152), // #1637 - INST(Vscatterpf0dpd , VexM_VM , E(660F38,C6,5,2,_,1,3,T1S), 0 , 232, 0 , 311, 170), // #1638 - INST(Vscatterpf0dps , VexM_VM , E(660F38,C6,5,2,_,0,2,T1S), 0 , 233, 0 , 312, 170), // #1639 - INST(Vscatterpf0qpd , VexM_VM , E(660F38,C7,5,2,_,1,3,T1S), 0 , 232, 0 , 313, 170), // #1640 - INST(Vscatterpf0qps , VexM_VM , E(660F38,C7,5,2,_,0,2,T1S), 0 , 233, 0 , 313, 170), // #1641 - INST(Vscatterpf1dpd , VexM_VM , E(660F38,C6,6,2,_,1,3,T1S), 0 , 234, 0 , 311, 170), // #1642 - INST(Vscatterpf1dps , VexM_VM , E(660F38,C6,6,2,_,0,2,T1S), 0 , 235, 0 , 312, 170), // #1643 - INST(Vscatterpf1qpd , VexM_VM , E(660F38,C7,6,2,_,1,3,T1S), 0 , 234, 0 , 313, 170), // #1644 - INST(Vscatterpf1qps , VexM_VM , E(660F38,C7,6,2,_,0,2,T1S), 0 , 235, 0 , 313, 170), // #1645 - INST(Vscatterqpd , VexMr_VM , E(660F38,A3,_,x,_,1,3,T1S), 0 , 129, 0 , 413, 152), // #1646 - INST(Vscatterqps , VexMr_VM , E(660F38,A3,_,x,_,0,2,T1S), 0 , 130, 0 , 412, 152), // #1647 - INST(Vsha512msg1 , VexRm , V(F20F38,CC,_,1,0,_,_,_ ), 0 , 236, 0 , 439, 196), // #1648 - INST(Vsha512msg2 , VexRm , V(F20F38,CD,_,1,0,_,_,_ ), 0 , 236, 0 , 440, 196), // #1649 - INST(Vsha512rnds2 , VexRvm , V(F20F38,CB,_,1,0,_,_,_ ), 0 , 236, 0 , 441, 196), // #1650 - INST(Vshuff32x4 , VexRvmi_Lx , E(660F3A,23,_,x,_,0,4,FV ), 0 , 112, 0 , 442, 152), // #1651 - INST(Vshuff64x2 , VexRvmi_Lx , E(660F3A,23,_,x,_,1,4,FV ), 0 , 113, 0 , 443, 152), // #1652 - INST(Vshufi32x4 , VexRvmi_Lx , E(660F3A,43,_,x,_,0,4,FV ), 0 , 112, 0 , 442, 152), // #1653 - INST(Vshufi64x2 , VexRvmi_Lx , E(660F3A,43,_,x,_,1,4,FV ), 0 , 113, 0 , 443, 152), // #1654 - INST(Vshufpd , VexRvmi_Lx , V(660F00,C6,_,x,I,1,4,FV ), 0 , 104, 0 , 444, 145), // #1655 - INST(Vshufps , VexRvmi_Lx , V(000F00,C6,_,x,I,0,4,FV ), 0 , 106, 0 , 445, 145), // #1656 - INST(Vsm3msg1 , VexRvm , V(000F38,DA,_,0,0,_,_,_ ), 0 , 11 , 0 , 446, 197), // #1657 - INST(Vsm3msg2 , VexRvm , V(660F38,DA,_,0,0,_,_,_ ), 0 , 30 , 0 , 446, 197), // #1658 - INST(Vsm3rnds2 , VexRvmi , V(660F3A,DE,_,0,0,_,_,_ ), 0 , 75 , 0 , 284, 197), // #1659 - INST(Vsm4key4 , VexRvm_Lx , V(F30F38,DA,_,x,0,_,_,_ ), 0 , 89 , 0 , 207, 198), // #1660 - INST(Vsm4rnds4 , VexRvm_Lx , V(F20F38,DA,_,x,0,_,_,_ ), 0 , 85 , 0 , 207, 198), // #1661 - INST(Vsqrtpd , VexRm_Lx , V(660F00,51,_,x,I,1,4,FV ), 0 , 104, 0 , 447, 145), // #1662 - INST(Vsqrtph , VexRm_Lx , E(00MAP5,51,_,_,_,0,4,FV ), 0 , 105, 0 , 253, 146), // #1663 - INST(Vsqrtps , VexRm_Lx , V(000F00,51,_,x,I,0,4,FV ), 0 , 106, 0 , 241, 145), // #1664 - INST(Vsqrtsd , VexRvm , V(F20F00,51,_,I,I,1,3,T1S), 0 , 107, 0 , 204, 147), // #1665 - INST(Vsqrtsh , VexRvm , E(F3MAP5,51,_,_,_,0,1,T1S), 0 , 108, 0 , 205, 148), // #1666 - INST(Vsqrtss , VexRvm , V(F30F00,51,_,I,I,0,2,T1S), 0 , 109, 0 , 206, 147), // #1667 - INST(Vstmxcsr , VexM , V(000F00,AE,3,0,I,_,_,_ ), 0 , 237, 0 , 328, 149), // #1668 - INST(Vsubpd , VexRvm_Lx , V(660F00,5C,_,x,I,1,4,FV ), 0 , 104, 0 , 201, 145), // #1669 - INST(Vsubph , VexRvm_Lx , E(00MAP5,5C,_,_,_,0,4,FV ), 0 , 105, 0 , 202, 146), // #1670 - INST(Vsubps , VexRvm_Lx , V(000F00,5C,_,x,I,0,4,FV ), 0 , 106, 0 , 203, 145), // #1671 - INST(Vsubsd , VexRvm , V(F20F00,5C,_,I,I,1,3,T1S), 0 , 107, 0 , 204, 147), // #1672 - INST(Vsubsh , VexRvm , E(F3MAP5,5C,_,_,_,0,1,T1S), 0 , 108, 0 , 205, 148), // #1673 - INST(Vsubss , VexRvm , V(F30F00,5C,_,I,I,0,2,T1S), 0 , 109, 0 , 206, 147), // #1674 - INST(Vtestpd , VexRm_Lx , V(660F38,0F,_,x,0,_,_,_ ), 0 , 30 , 0 , 306, 185), // #1675 - INST(Vtestps , VexRm_Lx , V(660F38,0E,_,x,0,_,_,_ ), 0 , 30 , 0 , 306, 185), // #1676 - INST(Vucomisd , VexRm , V(660F00,2E,_,I,I,1,3,T1S), 0 , 126, 0 , 235, 158), // #1677 - INST(Vucomish , VexRm , E(00MAP5,2E,_,_,_,0,1,T1S), 0 , 127, 0 , 236, 159), // #1678 - INST(Vucomiss , VexRm , V(000F00,2E,_,I,I,0,2,T1S), 0 , 128, 0 , 237, 158), // #1679 - INST(Vunpckhpd , VexRvm_Lx , V(660F00,15,_,x,I,1,4,FV ), 0 , 104, 0 , 213, 145), // #1680 - INST(Vunpckhps , VexRvm_Lx , V(000F00,15,_,x,I,0,4,FV ), 0 , 106, 0 , 214, 145), // #1681 - INST(Vunpcklpd , VexRvm_Lx , V(660F00,14,_,x,I,1,4,FV ), 0 , 104, 0 , 213, 145), // #1682 - INST(Vunpcklps , VexRvm_Lx , V(000F00,14,_,x,I,0,4,FV ), 0 , 106, 0 , 214, 145), // #1683 - INST(Vxorpd , VexRvm_Lx , V(660F00,57,_,x,I,1,4,FV ), 0 , 104, 0 , 425, 153), // #1684 - INST(Vxorps , VexRvm_Lx , V(000F00,57,_,x,I,0,4,FV ), 0 , 106, 0 , 424, 153), // #1685 - INST(Vzeroall , VexOp , V(000F00,77,_,1,I,_,_,_ ), 0 , 70 , 0 , 448, 149), // #1686 - INST(Vzeroupper , VexOp , V(000F00,77,_,0,I,_,_,_ ), 0 , 74 , 0 , 448, 149), // #1687 - INST(Wbinvd , X86Op , O(000F00,09,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 45 ), // #1688 - INST(Wbnoinvd , X86Op , O(F30F00,09,_,_,_,_,_,_ ), 0 , 7 , 0 , 31 , 199), // #1689 - INST(Wrfsbase , X86M , O(F30F00,AE,2,_,x,_,_,_ ), 0 , 238, 0 , 178, 122), // #1690 - INST(Wrgsbase , X86M , O(F30F00,AE,3,_,x,_,_,_ ), 0 , 239, 0 , 178, 122), // #1691 - INST(Wrmsr , X86Op , O(000F00,30,_,_,_,_,_,_ ), 0 , 5 , 0 , 179, 123), // #1692 - INST(Wrssd , X86Mr , O(000F38,F6,_,_,_,_,_,_ ), 0 , 1 , 0 , 449, 65 ), // #1693 - INST(Wrssq , X86Mr , O(000F38,F6,_,_,1,_,_,_ ), 0 , 240, 0 , 450, 65 ), // #1694 - INST(Wrussd , X86Mr , O(660F38,F5,_,_,_,_,_,_ ), 0 , 2 , 0 , 449, 65 ), // #1695 - INST(Wrussq , X86Mr , O(660F38,F5,_,_,1,_,_,_ ), 0 , 241, 0 , 450, 65 ), // #1696 - INST(Xabort , X86Op_Mod11RM_I8 , O(000000,C6,7,_,_,_,_,_ ), 0 , 29 , 0 , 84 , 200), // #1697 - INST(Xadd , X86Xadd , O(000F00,C0,_,_,x,_,_,_ ), 0 , 5 , 0 , 451, 40 ), // #1698 - INST(Xbegin , X86JmpRel , O(000000,C7,7,_,_,_,_,_ ), 0 , 29 , 0 , 452, 200), // #1699 - INST(Xchg , X86Xchg , O(000000,86,_,_,x,_,_,_ ), 0 , 0 , 0 , 453, 0 ), // #1700 - INST(Xend , X86Op , O(000F01,D5,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 200), // #1701 - INST(Xgetbv , X86Op , O(000F01,D0,_,_,_,_,_,_ ), 0 , 23 , 0 , 179, 201), // #1702 - INST(Xlatb , X86Op , O(000000,D7,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 0 ), // #1703 - INST(Xor , X86Arith , O(000000,30,6,_,x,_,_,_ ), 0 , 34 , 0 , 184, 1 ), // #1704 - INST(Xorpd , ExtRm , O(660F00,57,_,_,_,_,_,_ ), 0 , 4 , 0 , 155, 5 ), // #1705 - INST(Xorps , ExtRm , O(000F00,57,_,_,_,_,_,_ ), 0 , 5 , 0 , 155, 6 ), // #1706 - INST(Xresldtrk , X86Op , O(F20F01,E9,_,_,_,_,_,_ ), 0 , 93 , 0 , 31 , 202), // #1707 - INST(Xrstor , X86M_Only_EDX_EAX , O(000F00,AE,5,_,_,_,_,_ ), 0 , 79 , 0 , 454, 201), // #1708 - INST(Xrstor64 , X86M_Only_EDX_EAX , O(000F00,AE,5,_,1,_,_,_ ), 0 , 242, 0 , 455, 201), // #1709 - INST(Xrstors , X86M_Only_EDX_EAX , O(000F00,C7,3,_,_,_,_,_ ), 0 , 80 , 0 , 454, 203), // #1710 - INST(Xrstors64 , X86M_Only_EDX_EAX , O(000F00,C7,3,_,1,_,_,_ ), 0 , 243, 0 , 455, 203), // #1711 - INST(Xsave , X86M_Only_EDX_EAX , O(000F00,AE,4,_,_,_,_,_ ), 0 , 98 , 0 , 454, 201), // #1712 - INST(Xsave64 , X86M_Only_EDX_EAX , O(000F00,AE,4,_,1,_,_,_ ), 0 , 244, 0 , 455, 201), // #1713 - INST(Xsavec , X86M_Only_EDX_EAX , O(000F00,C7,4,_,_,_,_,_ ), 0 , 98 , 0 , 454, 204), // #1714 - INST(Xsavec64 , X86M_Only_EDX_EAX , O(000F00,C7,4,_,1,_,_,_ ), 0 , 244, 0 , 455, 204), // #1715 - INST(Xsaveopt , X86M_Only_EDX_EAX , O(000F00,AE,6,_,_,_,_,_ ), 0 , 82 , 0 , 454, 205), // #1716 - INST(Xsaveopt64 , X86M_Only_EDX_EAX , O(000F00,AE,6,_,1,_,_,_ ), 0 , 245, 0 , 455, 205), // #1717 - INST(Xsaves , X86M_Only_EDX_EAX , O(000F00,C7,5,_,_,_,_,_ ), 0 , 79 , 0 , 454, 203), // #1718 - INST(Xsaves64 , X86M_Only_EDX_EAX , O(000F00,C7,5,_,1,_,_,_ ), 0 , 242, 0 , 455, 203), // #1719 - INST(Xsetbv , X86Op , O(000F01,D1,_,_,_,_,_,_ ), 0 , 23 , 0 , 179, 201), // #1720 - INST(Xsusldtrk , X86Op , O(F20F01,E8,_,_,_,_,_,_ ), 0 , 93 , 0 , 31 , 202), // #1721 - INST(Xtest , X86Op , O(000F01,D6,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 206) // #1722 + INST(Cmovb , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 30 ), // #81 + INST(Cmovbe , X86Rm , O(000F00,46,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 31 ), // #82 + INST(Cmovl , X86Rm , O(000F00,4C,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 32 ), // #83 + INST(Cmovle , X86Rm , O(000F00,4E,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 33 ), // #84 + INST(Cmovnb , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 30 ), // #85 + INST(Cmovnbe , X86Rm , O(000F00,47,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 31 ), // #86 + INST(Cmovnl , X86Rm , O(000F00,4D,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 32 ), // #87 + INST(Cmovnle , X86Rm , O(000F00,4F,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 33 ), // #88 + INST(Cmovno , X86Rm , O(000F00,41,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 34 ), // #89 + INST(Cmovnp , X86Rm , O(000F00,4B,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 35 ), // #90 + INST(Cmovns , X86Rm , O(000F00,49,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 36 ), // #91 + INST(Cmovnz , X86Rm , O(000F00,45,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 37 ), // #92 + INST(Cmovo , X86Rm , O(000F00,40,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 34 ), // #93 + INST(Cmovp , X86Rm , O(000F00,4A,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 35 ), // #94 + INST(Cmovs , X86Rm , O(000F00,48,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 36 ), // #95 + INST(Cmovz , X86Rm , O(000F00,44,_,_,x,_,_,_ ), 0 , 5 , 0 , 23 , 37 ), // #96 + INST(Cmp , X86Arith , O(000000,38,7,_,x,_,_,_ ), 0 , 29 , 0 , 36 , 1 ), // #97 + INST(Cmpbexadd , VexMvr_Wx , V(660F38,E6,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #98 + INST(Cmpbxadd , VexMvr_Wx , V(660F38,E2,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #99 + INST(Cmplexadd , VexMvr_Wx , V(660F38,EE,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #100 + INST(Cmplxadd , VexMvr_Wx , V(660F38,EC,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #101 + INST(Cmpnbexadd , VexMvr_Wx , V(660F38,E7,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #102 + INST(Cmpnbxadd , VexMvr_Wx , V(660F38,E3,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #103 + INST(Cmpnlexadd , VexMvr_Wx , V(660F38,EF,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #104 + INST(Cmpnlxadd , VexMvr_Wx , V(660F38,ED,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #105 + INST(Cmpnoxadd , VexMvr_Wx , V(660F38,E1,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #106 + INST(Cmpnpxadd , VexMvr_Wx , V(660F38,EB,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #107 + INST(Cmpnsxadd , VexMvr_Wx , V(660F38,E9,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #108 + INST(Cmpnzxadd , VexMvr_Wx , V(660F38,E5,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #109 + INST(Cmpoxadd , VexMvr_Wx , V(660F38,E0,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #110 + INST(Cmppd , ExtRmi , O(660F00,C2,_,_,_,_,_,_ ), 0 , 4 , 0 , 9 , 5 ), // #111 + INST(Cmpps , ExtRmi , O(000F00,C2,_,_,_,_,_,_ ), 0 , 5 , 0 , 9 , 6 ), // #112 + INST(Cmppxadd , VexMvr_Wx , V(660F38,EA,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #113 + INST(Cmps , X86StrMm , O(000000,A6,_,_,_,_,_,_ ), 0 , 0 , 0 , 38 , 39 ), // #114 + INST(Cmpsd , ExtRmi , O(F20F00,C2,_,_,_,_,_,_ ), 0 , 6 , 0 , 39 , 5 ), // #115 + INST(Cmpss , ExtRmi , O(F30F00,C2,_,_,_,_,_,_ ), 0 , 7 , 0 , 40 , 6 ), // #116 + INST(Cmpsxadd , VexMvr_Wx , V(660F38,E8,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #117 + INST(Cmpxchg , X86Cmpxchg , O(000F00,B0,_,_,x,_,_,_ ), 0 , 5 , 0 , 41 , 40 ), // #118 + INST(Cmpxchg16b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,1,_,_,_ ), 0 , 31 , 0 , 42 , 41 ), // #119 + INST(Cmpxchg8b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,_,_,_,_ ), 0 , 32 , 0 , 43 , 42 ), // #120 + INST(Cmpzxadd , VexMvr_Wx , V(660F38,E4,_,0,x,_,_,_ ), 0 , 30 , 0 , 37 , 38 ), // #121 + INST(Comisd , ExtRm , O(660F00,2F,_,_,_,_,_,_ ), 0 , 4 , 0 , 7 , 43 ), // #122 + INST(Comiss , ExtRm , O(000F00,2F,_,_,_,_,_,_ ), 0 , 5 , 0 , 8 , 44 ), // #123 + INST(Cpuid , X86Op , O(000F00,A2,_,_,_,_,_,_ ), 0 , 5 , 0 , 44 , 45 ), // #124 + INST(Cqo , X86Op_xDX_xAX , O(000000,99,_,_,1,_,_,_ ), 0 , 22 , 0 , 45 , 0 ), // #125 + INST(Crc32 , X86Crc , O(F20F38,F0,_,_,x,_,_,_ ), 0 , 12 , 0 , 46 , 46 ), // #126 + INST(Cvtdq2pd , ExtRm , O(F30F00,E6,_,_,_,_,_,_ ), 0 , 7 , 0 , 7 , 5 ), // #127 + INST(Cvtdq2ps , ExtRm , O(000F00,5B,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 5 ), // #128 + INST(Cvtpd2dq , ExtRm , O(F20F00,E6,_,_,_,_,_,_ ), 0 , 6 , 0 , 6 , 5 ), // #129 + INST(Cvtpd2pi , ExtRm , O(660F00,2D,_,_,_,_,_,_ ), 0 , 4 , 0 , 47 , 5 ), // #130 + INST(Cvtpd2ps , ExtRm , O(660F00,5A,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #131 + INST(Cvtpi2pd , ExtRm , O(660F00,2A,_,_,_,_,_,_ ), 0 , 4 , 0 , 48 , 5 ), // #132 + INST(Cvtpi2ps , ExtRm , O(000F00,2A,_,_,_,_,_,_ ), 0 , 5 , 0 , 48 , 6 ), // #133 + INST(Cvtps2dq , ExtRm , O(660F00,5B,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #134 + INST(Cvtps2pd , ExtRm , O(000F00,5A,_,_,_,_,_,_ ), 0 , 5 , 0 , 7 , 5 ), // #135 + INST(Cvtps2pi , ExtRm , O(000F00,2D,_,_,_,_,_,_ ), 0 , 5 , 0 , 49 , 6 ), // #136 + INST(Cvtsd2si , ExtRm_Wx_GpqOnly , O(F20F00,2D,_,_,x,_,_,_ ), 0 , 6 , 0 , 50 , 5 ), // #137 + INST(Cvtsd2ss , ExtRm , O(F20F00,5A,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #138 + INST(Cvtsi2sd , ExtRm_Wx , O(F20F00,2A,_,_,x,_,_,_ ), 0 , 6 , 0 , 51 , 5 ), // #139 + INST(Cvtsi2ss , ExtRm_Wx , O(F30F00,2A,_,_,x,_,_,_ ), 0 , 7 , 0 , 51 , 6 ), // #140 + INST(Cvtss2sd , ExtRm , O(F30F00,5A,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 5 ), // #141 + INST(Cvtss2si , ExtRm_Wx_GpqOnly , O(F30F00,2D,_,_,x,_,_,_ ), 0 , 7 , 0 , 52 , 6 ), // #142 + INST(Cvttpd2dq , ExtRm , O(660F00,E6,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #143 + INST(Cvttpd2pi , ExtRm , O(660F00,2C,_,_,_,_,_,_ ), 0 , 4 , 0 , 47 , 5 ), // #144 + INST(Cvttps2dq , ExtRm , O(F30F00,5B,_,_,_,_,_,_ ), 0 , 7 , 0 , 6 , 5 ), // #145 + INST(Cvttps2pi , ExtRm , O(000F00,2C,_,_,_,_,_,_ ), 0 , 5 , 0 , 49 , 6 ), // #146 + INST(Cvttsd2si , ExtRm_Wx_GpqOnly , O(F20F00,2C,_,_,x,_,_,_ ), 0 , 6 , 0 , 50 , 5 ), // #147 + INST(Cvttss2si , ExtRm_Wx_GpqOnly , O(F30F00,2C,_,_,x,_,_,_ ), 0 , 7 , 0 , 52 , 6 ), // #148 + INST(Cwd , X86Op_xDX_xAX , O(660000,99,_,_,_,_,_,_ ), 0 , 21 , 0 , 53 , 0 ), // #149 + INST(Cwde , X86Op_xAX , O(000000,98,_,_,_,_,_,_ ), 0 , 0 , 0 , 54 , 0 ), // #150 + INST(Daa , X86Op , O(000000,27,_,_,_,_,_,_ ), 0 , 0 , 0 , 1 , 1 ), // #151 + INST(Das , X86Op , O(000000,2F,_,_,_,_,_,_ ), 0 , 0 , 0 , 1 , 1 ), // #152 + INST(Dec , X86IncDec , O(000000,FE,1,_,x,_,_,_ ), O(000000,48,_,_,x,_,_,_ ), 33 , 6 , 55 , 47 ), // #153 + INST(Div , X86M_GPB_MulDiv , O(000000,F6,6,_,x,_,_,_ ), 0 , 34 , 0 , 56 , 1 ), // #154 + INST(Divpd , ExtRm , O(660F00,5E,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #155 + INST(Divps , ExtRm , O(000F00,5E,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #156 + INST(Divsd , ExtRm , O(F20F00,5E,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #157 + INST(Divss , ExtRm , O(F30F00,5E,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #158 + INST(Dppd , ExtRmi , O(660F3A,41,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #159 + INST(Dpps , ExtRmi , O(660F3A,40,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #160 + INST(Emms , X86Op , O(000F00,77,_,_,_,_,_,_ ), 0 , 5 , 0 , 57 , 48 ), // #161 + INST(Endbr32 , X86Op_Mod11RM , O(F30F00,1E,7,_,_,_,_,3 ), 0 , 35 , 0 , 31 , 49 ), // #162 + INST(Endbr64 , X86Op_Mod11RM , O(F30F00,1E,7,_,_,_,_,2 ), 0 , 36 , 0 , 31 , 49 ), // #163 + INST(Enqcmd , X86EnqcmdMovdir64b , O(F20F38,F8,_,_,_,_,_,_ ), 0 , 12 , 0 , 58 , 50 ), // #164 + INST(Enqcmds , X86EnqcmdMovdir64b , O(F30F38,F8,_,_,_,_,_,_ ), 0 , 8 , 0 , 58 , 50 ), // #165 + INST(Enter , X86Enter , O(000000,C8,_,_,_,_,_,_ ), 0 , 0 , 0 , 59 , 0 ), // #166 + INST(Extractps , ExtExtract , O(660F3A,17,_,_,_,_,_,_ ), 0 , 9 , 0 , 60 , 13 ), // #167 + INST(Extrq , ExtExtrq , O(660F00,79,_,_,_,_,_,_ ), O(660F00,78,0,_,_,_,_,_ ), 4 , 7 , 61 , 51 ), // #168 + INST(F2xm1 , FpuOp , O_FPU(00,D9F0,_) , 0 , 37 , 0 , 31 , 52 ), // #169 + INST(Fabs , FpuOp , O_FPU(00,D9E1,_) , 0 , 37 , 0 , 31 , 52 ), // #170 + INST(Fadd , FpuArith , O_FPU(00,C0C0,0) , 0 , 38 , 0 , 62 , 52 ), // #171 + INST(Faddp , FpuRDef , O_FPU(00,DEC0,_) , 0 , 39 , 0 , 63 , 52 ), // #172 + INST(Fbld , X86M_Only , O_FPU(00,00DF,4) , 0 , 40 , 0 , 64 , 52 ), // #173 + INST(Fbstp , X86M_Only , O_FPU(00,00DF,6) , 0 , 41 , 0 , 64 , 52 ), // #174 + INST(Fchs , FpuOp , O_FPU(00,D9E0,_) , 0 , 37 , 0 , 31 , 52 ), // #175 + INST(Fclex , FpuOp , O_FPU(9B,DBE2,_) , 0 , 42 , 0 , 31 , 52 ), // #176 + INST(Fcmovb , FpuR , O_FPU(00,DAC0,_) , 0 , 43 , 0 , 65 , 53 ), // #177 + INST(Fcmovbe , FpuR , O_FPU(00,DAD0,_) , 0 , 43 , 0 , 65 , 54 ), // #178 + INST(Fcmove , FpuR , O_FPU(00,DAC8,_) , 0 , 43 , 0 , 65 , 55 ), // #179 + INST(Fcmovnb , FpuR , O_FPU(00,DBC0,_) , 0 , 44 , 0 , 65 , 53 ), // #180 + INST(Fcmovnbe , FpuR , O_FPU(00,DBD0,_) , 0 , 44 , 0 , 65 , 54 ), // #181 + INST(Fcmovne , FpuR , O_FPU(00,DBC8,_) , 0 , 44 , 0 , 65 , 55 ), // #182 + INST(Fcmovnu , FpuR , O_FPU(00,DBD8,_) , 0 , 44 , 0 , 65 , 56 ), // #183 + INST(Fcmovu , FpuR , O_FPU(00,DAD8,_) , 0 , 43 , 0 , 65 , 56 ), // #184 + INST(Fcom , FpuCom , O_FPU(00,D0D0,2) , 0 , 45 , 0 , 66 , 52 ), // #185 + INST(Fcomi , FpuR , O_FPU(00,DBF0,_) , 0 , 44 , 0 , 65 , 57 ), // #186 + INST(Fcomip , FpuR , O_FPU(00,DFF0,_) , 0 , 46 , 0 , 65 , 57 ), // #187 + INST(Fcomp , FpuCom , O_FPU(00,D8D8,3) , 0 , 47 , 0 , 66 , 52 ), // #188 + INST(Fcompp , FpuOp , O_FPU(00,DED9,_) , 0 , 39 , 0 , 31 , 52 ), // #189 + INST(Fcos , FpuOp , O_FPU(00,D9FF,_) , 0 , 37 , 0 , 31 , 52 ), // #190 + INST(Fdecstp , FpuOp , O_FPU(00,D9F6,_) , 0 , 37 , 0 , 31 , 52 ), // #191 + INST(Fdiv , FpuArith , O_FPU(00,F0F8,6) , 0 , 48 , 0 , 62 , 52 ), // #192 + INST(Fdivp , FpuRDef , O_FPU(00,DEF8,_) , 0 , 39 , 0 , 63 , 52 ), // #193 + INST(Fdivr , FpuArith , O_FPU(00,F8F0,7) , 0 , 49 , 0 , 62 , 52 ), // #194 + INST(Fdivrp , FpuRDef , O_FPU(00,DEF0,_) , 0 , 39 , 0 , 63 , 52 ), // #195 + INST(Femms , X86Op , O(000F00,0E,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 58 ), // #196 + INST(Ffree , FpuR , O_FPU(00,DDC0,_) , 0 , 50 , 0 , 65 , 52 ), // #197 + INST(Fiadd , FpuM , O_FPU(00,00DA,0) , 0 , 51 , 0 , 67 , 52 ), // #198 + INST(Ficom , FpuM , O_FPU(00,00DA,2) , 0 , 52 , 0 , 67 , 52 ), // #199 + INST(Ficomp , FpuM , O_FPU(00,00DA,3) , 0 , 53 , 0 , 67 , 52 ), // #200 + INST(Fidiv , FpuM , O_FPU(00,00DA,6) , 0 , 41 , 0 , 67 , 52 ), // #201 + INST(Fidivr , FpuM , O_FPU(00,00DA,7) , 0 , 54 , 0 , 67 , 52 ), // #202 + INST(Fild , FpuM , O_FPU(00,00DB,0) , O_FPU(00,00DF,5) , 51 , 8 , 68 , 52 ), // #203 + INST(Fimul , FpuM , O_FPU(00,00DA,1) , 0 , 55 , 0 , 67 , 52 ), // #204 + INST(Fincstp , FpuOp , O_FPU(00,D9F7,_) , 0 , 37 , 0 , 31 , 52 ), // #205 + INST(Finit , FpuOp , O_FPU(9B,DBE3,_) , 0 , 42 , 0 , 31 , 52 ), // #206 + INST(Fist , FpuM , O_FPU(00,00DB,2) , 0 , 52 , 0 , 67 , 52 ), // #207 + INST(Fistp , FpuM , O_FPU(00,00DB,3) , O_FPU(00,00DF,7) , 53 , 9 , 68 , 52 ), // #208 + INST(Fisttp , FpuM , O_FPU(00,00DB,1) , O_FPU(00,00DD,1) , 55 , 10 , 68 , 59 ), // #209 + INST(Fisub , FpuM , O_FPU(00,00DA,4) , 0 , 40 , 0 , 67 , 52 ), // #210 + INST(Fisubr , FpuM , O_FPU(00,00DA,5) , 0 , 56 , 0 , 67 , 52 ), // #211 + INST(Fld , FpuFldFst , O_FPU(00,00D9,0) , O_FPU(00,00DB,5) , 51 , 11 , 69 , 52 ), // #212 + INST(Fld1 , FpuOp , O_FPU(00,D9E8,_) , 0 , 37 , 0 , 31 , 52 ), // #213 + INST(Fldcw , X86M_Only , O_FPU(00,00D9,5) , 0 , 56 , 0 , 70 , 52 ), // #214 + INST(Fldenv , X86M_Only , O_FPU(00,00D9,4) , 0 , 40 , 0 , 32 , 52 ), // #215 + INST(Fldl2e , FpuOp , O_FPU(00,D9EA,_) , 0 , 37 , 0 , 31 , 52 ), // #216 + INST(Fldl2t , FpuOp , O_FPU(00,D9E9,_) , 0 , 37 , 0 , 31 , 52 ), // #217 + INST(Fldlg2 , FpuOp , O_FPU(00,D9EC,_) , 0 , 37 , 0 , 31 , 52 ), // #218 + INST(Fldln2 , FpuOp , O_FPU(00,D9ED,_) , 0 , 37 , 0 , 31 , 52 ), // #219 + INST(Fldpi , FpuOp , O_FPU(00,D9EB,_) , 0 , 37 , 0 , 31 , 52 ), // #220 + INST(Fldz , FpuOp , O_FPU(00,D9EE,_) , 0 , 37 , 0 , 31 , 52 ), // #221 + INST(Fmul , FpuArith , O_FPU(00,C8C8,1) , 0 , 57 , 0 , 62 , 52 ), // #222 + INST(Fmulp , FpuRDef , O_FPU(00,DEC8,_) , 0 , 39 , 0 , 63 , 52 ), // #223 + INST(Fnclex , FpuOp , O_FPU(00,DBE2,_) , 0 , 44 , 0 , 31 , 52 ), // #224 + INST(Fninit , FpuOp , O_FPU(00,DBE3,_) , 0 , 44 , 0 , 31 , 52 ), // #225 + INST(Fnop , FpuOp , O_FPU(00,D9D0,_) , 0 , 37 , 0 , 31 , 52 ), // #226 + INST(Fnsave , X86M_Only , O_FPU(00,00DD,6) , 0 , 41 , 0 , 32 , 52 ), // #227 + INST(Fnstcw , X86M_Only , O_FPU(00,00D9,7) , 0 , 54 , 0 , 70 , 52 ), // #228 + INST(Fnstenv , X86M_Only , O_FPU(00,00D9,6) , 0 , 41 , 0 , 32 , 52 ), // #229 + INST(Fnstsw , FpuStsw , O_FPU(00,00DD,7) , O_FPU(00,DFE0,_) , 54 , 12 , 71 , 52 ), // #230 + INST(Fpatan , FpuOp , O_FPU(00,D9F3,_) , 0 , 37 , 0 , 31 , 52 ), // #231 + INST(Fprem , FpuOp , O_FPU(00,D9F8,_) , 0 , 37 , 0 , 31 , 52 ), // #232 + INST(Fprem1 , FpuOp , O_FPU(00,D9F5,_) , 0 , 37 , 0 , 31 , 52 ), // #233 + INST(Fptan , FpuOp , O_FPU(00,D9F2,_) , 0 , 37 , 0 , 31 , 52 ), // #234 + INST(Frndint , FpuOp , O_FPU(00,D9FC,_) , 0 , 37 , 0 , 31 , 52 ), // #235 + INST(Frstor , X86M_Only , O_FPU(00,00DD,4) , 0 , 40 , 0 , 32 , 52 ), // #236 + INST(Fsave , X86M_Only , O_FPU(9B,00DD,6) , 0 , 58 , 0 , 32 , 52 ), // #237 + INST(Fscale , FpuOp , O_FPU(00,D9FD,_) , 0 , 37 , 0 , 31 , 52 ), // #238 + INST(Fsin , FpuOp , O_FPU(00,D9FE,_) , 0 , 37 , 0 , 31 , 52 ), // #239 + INST(Fsincos , FpuOp , O_FPU(00,D9FB,_) , 0 , 37 , 0 , 31 , 52 ), // #240 + INST(Fsqrt , FpuOp , O_FPU(00,D9FA,_) , 0 , 37 , 0 , 31 , 52 ), // #241 + INST(Fst , FpuFldFst , O_FPU(00,00D9,2) , 0 , 52 , 0 , 72 , 52 ), // #242 + INST(Fstcw , X86M_Only , O_FPU(9B,00D9,7) , 0 , 59 , 0 , 70 , 52 ), // #243 + INST(Fstenv , X86M_Only , O_FPU(9B,00D9,6) , 0 , 58 , 0 , 32 , 52 ), // #244 + INST(Fstp , FpuFldFst , O_FPU(00,00D9,3) , O(000000,DB,7,_,_,_,_,_ ), 53 , 13 , 69 , 52 ), // #245 + INST(Fstsw , FpuStsw , O_FPU(9B,00DD,7) , O_FPU(9B,DFE0,_) , 59 , 14 , 71 , 52 ), // #246 + INST(Fsub , FpuArith , O_FPU(00,E0E8,4) , 0 , 60 , 0 , 62 , 52 ), // #247 + INST(Fsubp , FpuRDef , O_FPU(00,DEE8,_) , 0 , 39 , 0 , 63 , 52 ), // #248 + INST(Fsubr , FpuArith , O_FPU(00,E8E0,5) , 0 , 61 , 0 , 62 , 52 ), // #249 + INST(Fsubrp , FpuRDef , O_FPU(00,DEE0,_) , 0 , 39 , 0 , 63 , 52 ), // #250 + INST(Ftst , FpuOp , O_FPU(00,D9E4,_) , 0 , 37 , 0 , 31 , 52 ), // #251 + INST(Fucom , FpuRDef , O_FPU(00,DDE0,_) , 0 , 50 , 0 , 63 , 52 ), // #252 + INST(Fucomi , FpuR , O_FPU(00,DBE8,_) , 0 , 44 , 0 , 65 , 57 ), // #253 + INST(Fucomip , FpuR , O_FPU(00,DFE8,_) , 0 , 46 , 0 , 65 , 57 ), // #254 + INST(Fucomp , FpuRDef , O_FPU(00,DDE8,_) , 0 , 50 , 0 , 63 , 52 ), // #255 + INST(Fucompp , FpuOp , O_FPU(00,DAE9,_) , 0 , 43 , 0 , 31 , 52 ), // #256 + INST(Fwait , X86Op , O_FPU(00,009B,_) , 0 , 51 , 0 , 31 , 52 ), // #257 + INST(Fxam , FpuOp , O_FPU(00,D9E5,_) , 0 , 37 , 0 , 31 , 52 ), // #258 + INST(Fxch , FpuR , O_FPU(00,D9C8,_) , 0 , 37 , 0 , 63 , 52 ), // #259 + INST(Fxrstor , X86M_Only , O(000F00,AE,1,_,_,_,_,_ ), 0 , 32 , 0 , 32 , 60 ), // #260 + INST(Fxrstor64 , X86M_Only , O(000F00,AE,1,_,1,_,_,_ ), 0 , 31 , 0 , 73 , 60 ), // #261 + INST(Fxsave , X86M_Only , O(000F00,AE,0,_,_,_,_,_ ), 0 , 5 , 0 , 32 , 61 ), // #262 + INST(Fxsave64 , X86M_Only , O(000F00,AE,0,_,1,_,_,_ ), 0 , 62 , 0 , 73 , 61 ), // #263 + INST(Fxtract , FpuOp , O_FPU(00,D9F4,_) , 0 , 37 , 0 , 31 , 52 ), // #264 + INST(Fyl2x , FpuOp , O_FPU(00,D9F1,_) , 0 , 37 , 0 , 31 , 52 ), // #265 + INST(Fyl2xp1 , FpuOp , O_FPU(00,D9F9,_) , 0 , 37 , 0 , 31 , 52 ), // #266 + INST(Getsec , X86Op , O(000F00,37,_,_,_,_,_,_ ), 0 , 5 , 0 , 74 , 62 ), // #267 + INST(Gf2p8affineinvqb , ExtRmi , O(660F3A,CF,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 63 ), // #268 + INST(Gf2p8affineqb , ExtRmi , O(660F3A,CE,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 63 ), // #269 + INST(Gf2p8mulb , ExtRm , O(660F38,CF,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 63 ), // #270 + INST(Haddpd , ExtRm , O(660F00,7C,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 7 ), // #271 + INST(Haddps , ExtRm , O(F20F00,7C,_,_,_,_,_,_ ), 0 , 6 , 0 , 6 , 7 ), // #272 + INST(Hlt , X86Op , O(000000,F4,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 0 ), // #273 + INST(Hreset , X86Op_Mod11RM_I8 , O(F30F3A,F0,0,_,_,_,_,_ ), 0 , 63 , 0 , 75 , 64 ), // #274 + INST(Hsubpd , ExtRm , O(660F00,7D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 7 ), // #275 + INST(Hsubps , ExtRm , O(F20F00,7D,_,_,_,_,_,_ ), 0 , 6 , 0 , 6 , 7 ), // #276 + INST(Idiv , X86M_GPB_MulDiv , O(000000,F6,7,_,x,_,_,_ ), 0 , 29 , 0 , 56 , 1 ), // #277 + INST(Imul , X86Imul , O(000000,F6,5,_,x,_,_,_ ), 0 , 64 , 0 , 76 , 1 ), // #278 + INST(In , X86In , O(000000,EC,_,_,_,_,_,_ ), O(000000,E4,_,_,_,_,_,_ ), 0 , 15 , 77 , 0 ), // #279 + INST(Inc , X86IncDec , O(000000,FE,0,_,x,_,_,_ ), O(000000,40,_,_,x,_,_,_ ), 0 , 16 , 78 , 47 ), // #280 + INST(Incsspd , X86M , O(F30F00,AE,5,_,0,_,_,_ ), 0 , 65 , 0 , 79 , 65 ), // #281 + INST(Incsspq , X86M , O(F30F00,AE,5,_,1,_,_,_ ), 0 , 66 , 0 , 80 , 65 ), // #282 + INST(Ins , X86Ins , O(000000,6C,_,_,_,_,_,_ ), 0 , 0 , 0 , 81 , 0 ), // #283 + INST(Insertps , ExtRmi , O(660F3A,21,_,_,_,_,_,_ ), 0 , 9 , 0 , 40 , 13 ), // #284 + INST(Insertq , ExtInsertq , O(F20F00,79,_,_,_,_,_,_ ), O(F20F00,78,_,_,_,_,_,_ ), 6 , 17 , 82 , 51 ), // #285 + INST(Int , X86Int , O(000000,CD,_,_,_,_,_,_ ), 0 , 0 , 0 , 83 , 0 ), // #286 + INST(Int3 , X86Op , O(000000,CC,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 0 ), // #287 + INST(Into , X86Op , O(000000,CE,_,_,_,_,_,_ ), 0 , 0 , 0 , 84 , 66 ), // #288 + INST(Invd , X86Op , O(000F00,08,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 45 ), // #289 + INST(Invept , X86Rm_NoSize , O(660F38,80,_,_,_,_,_,_ ), 0 , 2 , 0 , 85 , 67 ), // #290 + INST(Invlpg , X86M_Only , O(000F00,01,7,_,_,_,_,_ ), 0 , 24 , 0 , 32 , 45 ), // #291 + INST(Invlpga , X86Op_xAddr , O(000F01,DF,_,_,_,_,_,_ ), 0 , 23 , 0 , 86 , 23 ), // #292 + INST(Invlpgb , X86Op , O(000F01,FE,_,_,_,_,_,_ ), 0 , 23 , 0 , 87 , 68 ), // #293 + INST(Invpcid , X86Rm_NoSize , O(660F38,82,_,_,_,_,_,_ ), 0 , 2 , 0 , 85 , 45 ), // #294 + INST(Invvpid , X86Rm_NoSize , O(660F38,81,_,_,_,_,_,_ ), 0 , 2 , 0 , 85 , 67 ), // #295 + INST(Iret , X86Op , O(660000,CF,_,_,_,_,_,_ ), 0 , 21 , 0 , 88 , 1 ), // #296 + INST(Iretd , X86Op , O(000000,CF,_,_,_,_,_,_ ), 0 , 0 , 0 , 88 , 1 ), // #297 + INST(Iretq , X86Op , O(000000,CF,_,_,1,_,_,_ ), 0 , 22 , 0 , 89 , 1 ), // #298 + INST(Jb , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 5 , 18 , 90 , 69 ), // #299 + INST(Jbe , X86Jcc , O(000F00,86,_,_,_,_,_,_ ), O(000000,76,_,_,_,_,_,_ ), 5 , 19 , 90 , 70 ), // #300 + INST(Jecxz , X86JecxzLoop , 0 , O(000000,E3,_,_,_,_,_,_ ), 0 , 20 , 91 , 0 ), // #301 + INST(Jl , X86Jcc , O(000F00,8C,_,_,_,_,_,_ ), O(000000,7C,_,_,_,_,_,_ ), 5 , 21 , 90 , 71 ), // #302 + INST(Jle , X86Jcc , O(000F00,8E,_,_,_,_,_,_ ), O(000000,7E,_,_,_,_,_,_ ), 5 , 22 , 90 , 72 ), // #303 + INST(Jmp , X86Jmp , O(000000,FF,4,_,_,_,_,_ ), O(000000,EB,_,_,_,_,_,_ ), 10 , 23 , 92 , 0 ), // #304 + INST(Jnb , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 5 , 24 , 90 , 69 ), // #305 + INST(Jnbe , X86Jcc , O(000F00,87,_,_,_,_,_,_ ), O(000000,77,_,_,_,_,_,_ ), 5 , 25 , 90 , 70 ), // #306 + INST(Jnl , X86Jcc , O(000F00,8D,_,_,_,_,_,_ ), O(000000,7D,_,_,_,_,_,_ ), 5 , 26 , 90 , 71 ), // #307 + INST(Jnle , X86Jcc , O(000F00,8F,_,_,_,_,_,_ ), O(000000,7F,_,_,_,_,_,_ ), 5 , 27 , 90 , 72 ), // #308 + INST(Jno , X86Jcc , O(000F00,81,_,_,_,_,_,_ ), O(000000,71,_,_,_,_,_,_ ), 5 , 28 , 93 , 66 ), // #309 + INST(Jnp , X86Jcc , O(000F00,8B,_,_,_,_,_,_ ), O(000000,7B,_,_,_,_,_,_ ), 5 , 29 , 90 , 73 ), // #310 + INST(Jns , X86Jcc , O(000F00,89,_,_,_,_,_,_ ), O(000000,79,_,_,_,_,_,_ ), 5 , 30 , 93 , 74 ), // #311 + INST(Jnz , X86Jcc , O(000F00,85,_,_,_,_,_,_ ), O(000000,75,_,_,_,_,_,_ ), 5 , 31 , 90 , 75 ), // #312 + INST(Jo , X86Jcc , O(000F00,80,_,_,_,_,_,_ ), O(000000,70,_,_,_,_,_,_ ), 5 , 32 , 93 , 66 ), // #313 + INST(Jp , X86Jcc , O(000F00,8A,_,_,_,_,_,_ ), O(000000,7A,_,_,_,_,_,_ ), 5 , 33 , 90 , 73 ), // #314 + INST(Js , X86Jcc , O(000F00,88,_,_,_,_,_,_ ), O(000000,78,_,_,_,_,_,_ ), 5 , 34 , 93 , 74 ), // #315 + INST(Jz , X86Jcc , O(000F00,84,_,_,_,_,_,_ ), O(000000,74,_,_,_,_,_,_ ), 5 , 35 , 90 , 75 ), // #316 + INST(Kaddb , VexRvm , V(660F00,4A,_,1,0,_,_,_ ), 0 , 67 , 0 , 94 , 76 ), // #317 + INST(Kaddd , VexRvm , V(660F00,4A,_,1,1,_,_,_ ), 0 , 68 , 0 , 94 , 77 ), // #318 + INST(Kaddq , VexRvm , V(000F00,4A,_,1,1,_,_,_ ), 0 , 69 , 0 , 94 , 77 ), // #319 + INST(Kaddw , VexRvm , V(000F00,4A,_,1,0,_,_,_ ), 0 , 70 , 0 , 94 , 76 ), // #320 + INST(Kandb , VexRvm , V(660F00,41,_,1,0,_,_,_ ), 0 , 67 , 0 , 94 , 76 ), // #321 + INST(Kandd , VexRvm , V(660F00,41,_,1,1,_,_,_ ), 0 , 68 , 0 , 94 , 77 ), // #322 + INST(Kandnb , VexRvm , V(660F00,42,_,1,0,_,_,_ ), 0 , 67 , 0 , 94 , 76 ), // #323 + INST(Kandnd , VexRvm , V(660F00,42,_,1,1,_,_,_ ), 0 , 68 , 0 , 94 , 77 ), // #324 + INST(Kandnq , VexRvm , V(000F00,42,_,1,1,_,_,_ ), 0 , 69 , 0 , 94 , 77 ), // #325 + INST(Kandnw , VexRvm , V(000F00,42,_,1,0,_,_,_ ), 0 , 70 , 0 , 94 , 78 ), // #326 + INST(Kandq , VexRvm , V(000F00,41,_,1,1,_,_,_ ), 0 , 69 , 0 , 94 , 77 ), // #327 + INST(Kandw , VexRvm , V(000F00,41,_,1,0,_,_,_ ), 0 , 70 , 0 , 94 , 78 ), // #328 + INST(Kmovb , VexKmov , V(660F00,90,_,0,0,_,_,_ ), V(660F00,92,_,0,0,_,_,_ ), 71 , 36 , 95 , 79 ), // #329 + INST(Kmovd , VexKmov , V(660F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,0,_,_,_ ), 72 , 37 , 96 , 80 ), // #330 + INST(Kmovq , VexKmov , V(000F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,1,_,_,_ ), 73 , 38 , 97 , 80 ), // #331 + INST(Kmovw , VexKmov , V(000F00,90,_,0,0,_,_,_ ), V(000F00,92,_,0,0,_,_,_ ), 74 , 39 , 98 , 81 ), // #332 + INST(Knotb , VexRm , V(660F00,44,_,0,0,_,_,_ ), 0 , 71 , 0 , 99 , 76 ), // #333 + INST(Knotd , VexRm , V(660F00,44,_,0,1,_,_,_ ), 0 , 72 , 0 , 99 , 77 ), // #334 + INST(Knotq , VexRm , V(000F00,44,_,0,1,_,_,_ ), 0 , 73 , 0 , 99 , 77 ), // #335 + INST(Knotw , VexRm , V(000F00,44,_,0,0,_,_,_ ), 0 , 74 , 0 , 99 , 78 ), // #336 + INST(Korb , VexRvm , V(660F00,45,_,1,0,_,_,_ ), 0 , 67 , 0 , 94 , 76 ), // #337 + INST(Kord , VexRvm , V(660F00,45,_,1,1,_,_,_ ), 0 , 68 , 0 , 94 , 77 ), // #338 + INST(Korq , VexRvm , V(000F00,45,_,1,1,_,_,_ ), 0 , 69 , 0 , 94 , 77 ), // #339 + INST(Kortestb , VexRm , V(660F00,98,_,0,0,_,_,_ ), 0 , 71 , 0 , 99 , 82 ), // #340 + INST(Kortestd , VexRm , V(660F00,98,_,0,1,_,_,_ ), 0 , 72 , 0 , 99 , 83 ), // #341 + INST(Kortestq , VexRm , V(000F00,98,_,0,1,_,_,_ ), 0 , 73 , 0 , 99 , 83 ), // #342 + INST(Kortestw , VexRm , V(000F00,98,_,0,0,_,_,_ ), 0 , 74 , 0 , 99 , 84 ), // #343 + INST(Korw , VexRvm , V(000F00,45,_,1,0,_,_,_ ), 0 , 70 , 0 , 94 , 78 ), // #344 + INST(Kshiftlb , VexRmi , V(660F3A,32,_,0,0,_,_,_ ), 0 , 75 , 0 , 100, 76 ), // #345 + INST(Kshiftld , VexRmi , V(660F3A,33,_,0,0,_,_,_ ), 0 , 75 , 0 , 100, 77 ), // #346 + INST(Kshiftlq , VexRmi , V(660F3A,33,_,0,1,_,_,_ ), 0 , 76 , 0 , 100, 77 ), // #347 + INST(Kshiftlw , VexRmi , V(660F3A,32,_,0,1,_,_,_ ), 0 , 76 , 0 , 100, 78 ), // #348 + INST(Kshiftrb , VexRmi , V(660F3A,30,_,0,0,_,_,_ ), 0 , 75 , 0 , 100, 76 ), // #349 + INST(Kshiftrd , VexRmi , V(660F3A,31,_,0,0,_,_,_ ), 0 , 75 , 0 , 100, 77 ), // #350 + INST(Kshiftrq , VexRmi , V(660F3A,31,_,0,1,_,_,_ ), 0 , 76 , 0 , 100, 77 ), // #351 + INST(Kshiftrw , VexRmi , V(660F3A,30,_,0,1,_,_,_ ), 0 , 76 , 0 , 100, 78 ), // #352 + INST(Ktestb , VexRm , V(660F00,99,_,0,0,_,_,_ ), 0 , 71 , 0 , 99 , 82 ), // #353 + INST(Ktestd , VexRm , V(660F00,99,_,0,1,_,_,_ ), 0 , 72 , 0 , 99 , 83 ), // #354 + INST(Ktestq , VexRm , V(000F00,99,_,0,1,_,_,_ ), 0 , 73 , 0 , 99 , 83 ), // #355 + INST(Ktestw , VexRm , V(000F00,99,_,0,0,_,_,_ ), 0 , 74 , 0 , 99 , 82 ), // #356 + INST(Kunpckbw , VexRvm , V(660F00,4B,_,1,0,_,_,_ ), 0 , 67 , 0 , 94 , 78 ), // #357 + INST(Kunpckdq , VexRvm , V(000F00,4B,_,1,1,_,_,_ ), 0 , 69 , 0 , 94 , 77 ), // #358 + INST(Kunpckwd , VexRvm , V(000F00,4B,_,1,0,_,_,_ ), 0 , 70 , 0 , 94 , 77 ), // #359 + INST(Kxnorb , VexRvm , V(660F00,46,_,1,0,_,_,_ ), 0 , 67 , 0 , 101, 76 ), // #360 + INST(Kxnord , VexRvm , V(660F00,46,_,1,1,_,_,_ ), 0 , 68 , 0 , 101, 77 ), // #361 + INST(Kxnorq , VexRvm , V(000F00,46,_,1,1,_,_,_ ), 0 , 69 , 0 , 101, 77 ), // #362 + INST(Kxnorw , VexRvm , V(000F00,46,_,1,0,_,_,_ ), 0 , 70 , 0 , 101, 78 ), // #363 + INST(Kxorb , VexRvm , V(660F00,47,_,1,0,_,_,_ ), 0 , 67 , 0 , 101, 76 ), // #364 + INST(Kxord , VexRvm , V(660F00,47,_,1,1,_,_,_ ), 0 , 68 , 0 , 101, 77 ), // #365 + INST(Kxorq , VexRvm , V(000F00,47,_,1,1,_,_,_ ), 0 , 69 , 0 , 101, 77 ), // #366 + INST(Kxorw , VexRvm , V(000F00,47,_,1,0,_,_,_ ), 0 , 70 , 0 , 101, 78 ), // #367 + INST(Lahf , X86Op , O(000000,9F,_,_,_,_,_,_ ), 0 , 0 , 0 , 102, 85 ), // #368 + INST(Lar , X86Rm , O(000F00,02,_,_,_,_,_,_ ), 0 , 5 , 0 , 103, 11 ), // #369 + INST(Lcall , X86LcallLjmp , O(000000,FF,3,_,_,_,_,_ ), O(000000,9A,_,_,_,_,_,_ ), 77 , 40 , 104, 1 ), // #370 + INST(Lddqu , ExtRm , O(F20F00,F0,_,_,_,_,_,_ ), 0 , 6 , 0 , 105, 7 ), // #371 + INST(Ldmxcsr , X86M_Only , O(000F00,AE,2,_,_,_,_,_ ), 0 , 78 , 0 , 106, 6 ), // #372 + INST(Lds , X86Rm , O(000000,C5,_,_,_,_,_,_ ), 0 , 0 , 0 , 107, 0 ), // #373 + INST(Ldtilecfg , AmxCfg , V(000F38,49,_,0,0,_,_,_ ), 0 , 11 , 0 , 108, 86 ), // #374 + INST(Lea , X86Lea , O(000000,8D,_,_,x,_,_,_ ), 0 , 0 , 0 , 109, 0 ), // #375 + INST(Leave , X86Op , O(000000,C9,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 0 ), // #376 + INST(Les , X86Rm , O(000000,C4,_,_,_,_,_,_ ), 0 , 0 , 0 , 107, 0 ), // #377 + INST(Lfence , X86Fence , O(000F00,AE,5,_,_,_,_,_ ), 0 , 79 , 0 , 31 , 5 ), // #378 + INST(Lfs , X86Rm , O(000F00,B4,_,_,_,_,_,_ ), 0 , 5 , 0 , 110, 0 ), // #379 + INST(Lgdt , X86M_Only , O(000F00,01,2,_,_,_,_,_ ), 0 , 78 , 0 , 32 , 0 ), // #380 + INST(Lgs , X86Rm , O(000F00,B5,_,_,_,_,_,_ ), 0 , 5 , 0 , 110, 0 ), // #381 + INST(Lidt , X86M_Only , O(000F00,01,3,_,_,_,_,_ ), 0 , 80 , 0 , 32 , 0 ), // #382 + INST(Ljmp , X86LcallLjmp , O(000000,FF,5,_,_,_,_,_ ), O(000000,EA,_,_,_,_,_,_ ), 64 , 41 , 111, 0 ), // #383 + INST(Lldt , X86M_NoSize , O(000F00,00,2,_,_,_,_,_ ), 0 , 78 , 0 , 112, 0 ), // #384 + INST(Llwpcb , VexR_Wx , V(XOP_M9,12,0,0,x,_,_,_ ), 0 , 81 , 0 , 113, 87 ), // #385 + INST(Lmsw , X86M_NoSize , O(000F00,01,6,_,_,_,_,_ ), 0 , 82 , 0 , 112, 0 ), // #386 + INST(Lods , X86StrRm , O(000000,AC,_,_,_,_,_,_ ), 0 , 0 , 0 , 114, 88 ), // #387 + INST(Loop , X86JecxzLoop , 0 , O(000000,E2,_,_,_,_,_,_ ), 0 , 42 , 115, 0 ), // #388 + INST(Loope , X86JecxzLoop , 0 , O(000000,E1,_,_,_,_,_,_ ), 0 , 43 , 115, 75 ), // #389 + INST(Loopne , X86JecxzLoop , 0 , O(000000,E0,_,_,_,_,_,_ ), 0 , 44 , 115, 75 ), // #390 + INST(Lsl , X86Rm , O(000F00,03,_,_,_,_,_,_ ), 0 , 5 , 0 , 116, 11 ), // #391 + INST(Lss , X86Rm , O(000F00,B2,_,_,_,_,_,_ ), 0 , 5 , 0 , 110, 0 ), // #392 + INST(Ltr , X86M_NoSize , O(000F00,00,3,_,_,_,_,_ ), 0 , 80 , 0 , 112, 0 ), // #393 + INST(Lwpins , VexVmi4_Wx , V(XOP_MA,12,0,0,x,_,_,_ ), 0 , 83 , 0 , 117, 87 ), // #394 + INST(Lwpval , VexVmi4_Wx , V(XOP_MA,12,1,0,x,_,_,_ ), 0 , 84 , 0 , 117, 87 ), // #395 + INST(Lzcnt , X86Rm_Raw66H , O(F30F00,BD,_,_,x,_,_,_ ), 0 , 7 , 0 , 23 , 89 ), // #396 + INST(Maskmovdqu , ExtRm_ZDI , O(660F00,F7,_,_,_,_,_,_ ), 0 , 4 , 0 , 118, 5 ), // #397 + INST(Maskmovq , ExtRm_ZDI , O(000F00,F7,_,_,_,_,_,_ ), 0 , 5 , 0 , 119, 90 ), // #398 + INST(Maxpd , ExtRm , O(660F00,5F,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #399 + INST(Maxps , ExtRm , O(000F00,5F,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #400 + INST(Maxsd , ExtRm , O(F20F00,5F,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #401 + INST(Maxss , ExtRm , O(F30F00,5F,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #402 + INST(Mcommit , X86Op , O(F30F01,FA,_,_,_,_,_,_ ), 0 , 27 , 0 , 31 , 91 ), // #403 + INST(Mfence , X86Fence , O(000F00,AE,6,_,_,_,_,_ ), 0 , 82 , 0 , 31 , 5 ), // #404 + INST(Minpd , ExtRm , O(660F00,5D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #405 + INST(Minps , ExtRm , O(000F00,5D,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #406 + INST(Minsd , ExtRm , O(F20F00,5D,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #407 + INST(Minss , ExtRm , O(F30F00,5D,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #408 + INST(Monitor , X86Op , O(000F01,C8,_,_,_,_,_,_ ), 0 , 23 , 0 , 120, 92 ), // #409 + INST(Monitorx , X86Op , O(000F01,FA,_,_,_,_,_,_ ), 0 , 23 , 0 , 120, 93 ), // #410 + INST(Mov , X86Mov , 0 , 0 , 0 , 0 , 121, 94 ), // #411 + INST(Movabs , X86Movabs , 0 , 0 , 0 , 0 , 122, 0 ), // #412 + INST(Movapd , ExtMov , O(660F00,28,_,_,_,_,_,_ ), O(660F00,29,_,_,_,_,_,_ ), 4 , 45 , 123, 95 ), // #413 + INST(Movaps , ExtMov , O(000F00,28,_,_,_,_,_,_ ), O(000F00,29,_,_,_,_,_,_ ), 5 , 46 , 123, 96 ), // #414 + INST(Movbe , ExtMovbe , O(000F38,F0,_,_,x,_,_,_ ), O(000F38,F1,_,_,x,_,_,_ ), 1 , 47 , 124, 97 ), // #415 + INST(Movd , ExtMovd , O(000F00,6E,_,_,_,_,_,_ ), O(000F00,7E,_,_,_,_,_,_ ), 5 , 48 , 125, 98 ), // #416 + INST(Movddup , ExtMov , O(F20F00,12,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 7 ), // #417 + INST(Movdir64b , X86EnqcmdMovdir64b , O(660F38,F8,_,_,_,_,_,_ ), 0 , 2 , 0 , 126, 99 ), // #418 + INST(Movdiri , X86MovntiMovdiri , O(000F38,F9,_,_,_,_,_,_ ), 0 , 1 , 0 , 3 , 100), // #419 + INST(Movdq2q , ExtMov , O(F20F00,D6,_,_,_,_,_,_ ), 0 , 6 , 0 , 127, 5 ), // #420 + INST(Movdqa , ExtMov , O(660F00,6F,_,_,_,_,_,_ ), O(660F00,7F,_,_,_,_,_,_ ), 4 , 49 , 123, 95 ), // #421 + INST(Movdqu , ExtMov , O(F30F00,6F,_,_,_,_,_,_ ), O(F30F00,7F,_,_,_,_,_,_ ), 7 , 50 , 123, 95 ), // #422 + INST(Movhlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), 0 , 5 , 0 , 128, 6 ), // #423 + INST(Movhpd , ExtMov , O(660F00,16,_,_,_,_,_,_ ), O(660F00,17,_,_,_,_,_,_ ), 4 , 51 , 129, 5 ), // #424 + INST(Movhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), O(000F00,17,_,_,_,_,_,_ ), 5 , 52 , 129, 6 ), // #425 + INST(Movlhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), 0 , 5 , 0 , 128, 6 ), // #426 + INST(Movlpd , ExtMov , O(660F00,12,_,_,_,_,_,_ ), O(660F00,13,_,_,_,_,_,_ ), 4 , 53 , 129, 5 ), // #427 + INST(Movlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), O(000F00,13,_,_,_,_,_,_ ), 5 , 54 , 129, 6 ), // #428 + INST(Movmskpd , ExtMov , O(660F00,50,_,_,_,_,_,_ ), 0 , 4 , 0 , 130, 5 ), // #429 + INST(Movmskps , ExtMov , O(000F00,50,_,_,_,_,_,_ ), 0 , 5 , 0 , 130, 6 ), // #430 + INST(Movntdq , ExtMov , 0 , O(660F00,E7,_,_,_,_,_,_ ), 0 , 55 , 131, 5 ), // #431 + INST(Movntdqa , ExtMov , O(660F38,2A,_,_,_,_,_,_ ), 0 , 2 , 0 , 105, 13 ), // #432 + INST(Movnti , X86MovntiMovdiri , O(000F00,C3,_,_,x,_,_,_ ), 0 , 5 , 0 , 3 , 5 ), // #433 + INST(Movntpd , ExtMov , 0 , O(660F00,2B,_,_,_,_,_,_ ), 0 , 56 , 131, 5 ), // #434 + INST(Movntps , ExtMov , 0 , O(000F00,2B,_,_,_,_,_,_ ), 0 , 57 , 131, 6 ), // #435 + INST(Movntq , ExtMov , 0 , O(000F00,E7,_,_,_,_,_,_ ), 0 , 58 , 132, 90 ), // #436 + INST(Movntsd , ExtMov , 0 , O(F20F00,2B,_,_,_,_,_,_ ), 0 , 59 , 133, 51 ), // #437 + INST(Movntss , ExtMov , 0 , O(F30F00,2B,_,_,_,_,_,_ ), 0 , 60 , 134, 51 ), // #438 + INST(Movq , ExtMovq , O(000F00,6E,_,_,x,_,_,_ ), O(000F00,7E,_,_,x,_,_,_ ), 5 , 48 , 135, 101), // #439 + INST(Movq2dq , ExtRm , O(F30F00,D6,_,_,_,_,_,_ ), 0 , 7 , 0 , 136, 5 ), // #440 + INST(Movs , X86StrMm , O(000000,A4,_,_,_,_,_,_ ), 0 , 0 , 0 , 137, 88 ), // #441 + INST(Movsd , ExtMov , O(F20F00,10,_,_,_,_,_,_ ), O(F20F00,11,_,_,_,_,_,_ ), 6 , 61 , 138, 95 ), // #442 + INST(Movshdup , ExtRm , O(F30F00,16,_,_,_,_,_,_ ), 0 , 7 , 0 , 6 , 7 ), // #443 + INST(Movsldup , ExtRm , O(F30F00,12,_,_,_,_,_,_ ), 0 , 7 , 0 , 6 , 7 ), // #444 + INST(Movss , ExtMov , O(F30F00,10,_,_,_,_,_,_ ), O(F30F00,11,_,_,_,_,_,_ ), 7 , 62 , 139, 96 ), // #445 + INST(Movsx , X86MovsxMovzx , O(000F00,BE,_,_,x,_,_,_ ), 0 , 5 , 0 , 140, 0 ), // #446 + INST(Movsxd , X86Rm , O(000000,63,_,_,x,_,_,_ ), 0 , 0 , 0 , 141, 0 ), // #447 + INST(Movupd , ExtMov , O(660F00,10,_,_,_,_,_,_ ), O(660F00,11,_,_,_,_,_,_ ), 4 , 63 , 123, 95 ), // #448 + INST(Movups , ExtMov , O(000F00,10,_,_,_,_,_,_ ), O(000F00,11,_,_,_,_,_,_ ), 5 , 64 , 123, 96 ), // #449 + INST(Movzx , X86MovsxMovzx , O(000F00,B6,_,_,x,_,_,_ ), 0 , 5 , 0 , 140, 0 ), // #450 + INST(Mpsadbw , ExtRmi , O(660F3A,42,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #451 + INST(Mul , X86M_GPB_MulDiv , O(000000,F6,4,_,x,_,_,_ ), 0 , 10 , 0 , 56 , 1 ), // #452 + INST(Mulpd , ExtRm , O(660F00,59,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #453 + INST(Mulps , ExtRm , O(000F00,59,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #454 + INST(Mulsd , ExtRm , O(F20F00,59,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #455 + INST(Mulss , ExtRm , O(F30F00,59,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #456 + INST(Mulx , VexRvm_ZDX_Wx , V(F20F38,F6,_,0,x,_,_,_ ), 0 , 85 , 0 , 142, 102), // #457 + INST(Mwait , X86Op , O(000F01,C9,_,_,_,_,_,_ ), 0 , 23 , 0 , 143, 92 ), // #458 + INST(Mwaitx , X86Op , O(000F01,FB,_,_,_,_,_,_ ), 0 , 23 , 0 , 144, 93 ), // #459 + INST(Neg , X86M_GPB , O(000000,F6,3,_,x,_,_,_ ), 0 , 77 , 0 , 145, 1 ), // #460 + INST(Nop , X86M_Nop , O(000000,90,_,_,_,_,_,_ ), 0 , 0 , 0 , 146, 0 ), // #461 + INST(Not , X86M_GPB , O(000000,F6,2,_,x,_,_,_ ), 0 , 3 , 0 , 145, 0 ), // #462 + INST(Or , X86Arith , O(000000,08,1,_,x,_,_,_ ), 0 , 33 , 0 , 147, 1 ), // #463 + INST(Orpd , ExtRm , O(660F00,56,_,_,_,_,_,_ ), 0 , 4 , 0 , 12 , 5 ), // #464 + INST(Orps , ExtRm , O(000F00,56,_,_,_,_,_,_ ), 0 , 5 , 0 , 12 , 6 ), // #465 + INST(Out , X86Out , O(000000,EE,_,_,_,_,_,_ ), O(000000,E6,_,_,_,_,_,_ ), 0 , 65 , 148, 0 ), // #466 + INST(Outs , X86Outs , O(000000,6E,_,_,_,_,_,_ ), 0 , 0 , 0 , 149, 0 ), // #467 + INST(Pabsb , ExtRm_P , O(000F38,1C,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #468 + INST(Pabsd , ExtRm_P , O(000F38,1E,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #469 + INST(Pabsw , ExtRm_P , O(000F38,1D,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #470 + INST(Packssdw , ExtRm_P , O(000F00,6B,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #471 + INST(Packsswb , ExtRm_P , O(000F00,63,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #472 + INST(Packusdw , ExtRm , O(660F38,2B,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 13 ), // #473 + INST(Packuswb , ExtRm_P , O(000F00,67,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #474 + INST(Paddb , ExtRm_P , O(000F00,FC,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #475 + INST(Paddd , ExtRm_P , O(000F00,FE,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #476 + INST(Paddq , ExtRm_P , O(000F00,D4,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 5 ), // #477 + INST(Paddsb , ExtRm_P , O(000F00,EC,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #478 + INST(Paddsw , ExtRm_P , O(000F00,ED,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #479 + INST(Paddusb , ExtRm_P , O(000F00,DC,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #480 + INST(Paddusw , ExtRm_P , O(000F00,DD,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #481 + INST(Paddw , ExtRm_P , O(000F00,FD,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #482 + INST(Palignr , ExtRmi_P , O(000F3A,0F,_,_,_,_,_,_ ), 0 , 86 , 0 , 151, 103), // #483 + INST(Pand , ExtRm_P , O(000F00,DB,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 98 ), // #484 + INST(Pandn , ExtRm_P , O(000F00,DF,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #485 + INST(Pause , X86Op , O(F30000,90,_,_,_,_,_,_ ), 0 , 87 , 0 , 31 , 0 ), // #486 + INST(Pavgb , ExtRm_P , O(000F00,E0,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 104), // #487 + INST(Pavgusb , Ext3dNow , O(000F0F,BF,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #488 + INST(Pavgw , ExtRm_P , O(000F00,E3,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 104), // #489 + INST(Pblendvb , ExtRm_XMM0 , O(660F38,10,_,_,_,_,_,_ ), 0 , 2 , 0 , 16 , 13 ), // #490 + INST(Pblendw , ExtRmi , O(660F3A,0E,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #491 + INST(Pclmulqdq , ExtRmi , O(660F3A,44,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 105), // #492 + INST(Pcmpeqb , ExtRm_P , O(000F00,74,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #493 + INST(Pcmpeqd , ExtRm_P , O(000F00,76,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #494 + INST(Pcmpeqq , ExtRm , O(660F38,29,_,_,_,_,_,_ ), 0 , 2 , 0 , 155, 13 ), // #495 + INST(Pcmpeqw , ExtRm_P , O(000F00,75,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #496 + INST(Pcmpestri , ExtRmi , O(660F3A,61,_,_,_,_,_,_ ), 0 , 9 , 0 , 156, 106), // #497 + INST(Pcmpestrm , ExtRmi , O(660F3A,60,_,_,_,_,_,_ ), 0 , 9 , 0 , 157, 106), // #498 + INST(Pcmpgtb , ExtRm_P , O(000F00,64,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #499 + INST(Pcmpgtd , ExtRm_P , O(000F00,66,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #500 + INST(Pcmpgtq , ExtRm , O(660F38,37,_,_,_,_,_,_ ), 0 , 2 , 0 , 155, 46 ), // #501 + INST(Pcmpgtw , ExtRm_P , O(000F00,65,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #502 + INST(Pcmpistri , ExtRmi , O(660F3A,63,_,_,_,_,_,_ ), 0 , 9 , 0 , 158, 106), // #503 + INST(Pcmpistrm , ExtRmi , O(660F3A,62,_,_,_,_,_,_ ), 0 , 9 , 0 , 159, 106), // #504 + INST(Pconfig , X86Op , O(000F01,C5,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 107), // #505 + INST(Pdep , VexRvm_Wx , V(F20F38,F5,_,0,x,_,_,_ ), 0 , 85 , 0 , 11 , 102), // #506 + INST(Pext , VexRvm_Wx , V(F30F38,F5,_,0,x,_,_,_ ), 0 , 89 , 0 , 11 , 102), // #507 + INST(Pextrb , ExtExtract , O(000F3A,14,_,_,_,_,_,_ ), 0 , 86 , 0 , 160, 13 ), // #508 + INST(Pextrd , ExtExtract , O(000F3A,16,_,_,_,_,_,_ ), 0 , 86 , 0 , 60 , 13 ), // #509 + INST(Pextrq , ExtExtract , O(000F3A,16,_,_,1,_,_,_ ), 0 , 90 , 0 , 161, 13 ), // #510 + INST(Pextrw , ExtPextrw , O(000F00,C5,_,_,_,_,_,_ ), O(000F3A,15,_,_,_,_,_,_ ), 5 , 66 , 162, 108), // #511 + INST(Pf2id , Ext3dNow , O(000F0F,1D,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #512 + INST(Pf2iw , Ext3dNow , O(000F0F,1C,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 109), // #513 + INST(Pfacc , Ext3dNow , O(000F0F,AE,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #514 + INST(Pfadd , Ext3dNow , O(000F0F,9E,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #515 + INST(Pfcmpeq , Ext3dNow , O(000F0F,B0,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #516 + INST(Pfcmpge , Ext3dNow , O(000F0F,90,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #517 + INST(Pfcmpgt , Ext3dNow , O(000F0F,A0,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #518 + INST(Pfmax , Ext3dNow , O(000F0F,A4,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #519 + INST(Pfmin , Ext3dNow , O(000F0F,94,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #520 + INST(Pfmul , Ext3dNow , O(000F0F,B4,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #521 + INST(Pfnacc , Ext3dNow , O(000F0F,8A,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 109), // #522 + INST(Pfpnacc , Ext3dNow , O(000F0F,8E,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 109), // #523 + INST(Pfrcp , Ext3dNow , O(000F0F,96,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #524 + INST(Pfrcpit1 , Ext3dNow , O(000F0F,A6,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #525 + INST(Pfrcpit2 , Ext3dNow , O(000F0F,B6,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #526 + INST(Pfrcpv , Ext3dNow , O(000F0F,86,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 110), // #527 + INST(Pfrsqit1 , Ext3dNow , O(000F0F,A7,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #528 + INST(Pfrsqrt , Ext3dNow , O(000F0F,97,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #529 + INST(Pfrsqrtv , Ext3dNow , O(000F0F,87,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 110), // #530 + INST(Pfsub , Ext3dNow , O(000F0F,9A,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #531 + INST(Pfsubr , Ext3dNow , O(000F0F,AA,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #532 + INST(Phaddd , ExtRm_P , O(000F38,02,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #533 + INST(Phaddsw , ExtRm_P , O(000F38,03,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #534 + INST(Phaddw , ExtRm_P , O(000F38,01,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #535 + INST(Phminposuw , ExtRm , O(660F38,41,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 13 ), // #536 + INST(Phsubd , ExtRm_P , O(000F38,06,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #537 + INST(Phsubsw , ExtRm_P , O(000F38,07,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #538 + INST(Phsubw , ExtRm_P , O(000F38,05,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #539 + INST(Pi2fd , Ext3dNow , O(000F0F,0D,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #540 + INST(Pi2fw , Ext3dNow , O(000F0F,0C,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 109), // #541 + INST(Pinsrb , ExtRmi , O(660F3A,20,_,_,_,_,_,_ ), 0 , 9 , 0 , 163, 13 ), // #542 + INST(Pinsrd , ExtRmi , O(660F3A,22,_,_,_,_,_,_ ), 0 , 9 , 0 , 164, 13 ), // #543 + INST(Pinsrq , ExtRmi , O(660F3A,22,_,_,1,_,_,_ ), 0 , 91 , 0 , 165, 13 ), // #544 + INST(Pinsrw , ExtRmi_P , O(000F00,C4,_,_,_,_,_,_ ), 0 , 5 , 0 , 166, 104), // #545 + INST(Pmaddubsw , ExtRm_P , O(000F38,04,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #546 + INST(Pmaddwd , ExtRm_P , O(000F00,F5,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #547 + INST(Pmaxsb , ExtRm , O(660F38,3C,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #548 + INST(Pmaxsd , ExtRm , O(660F38,3D,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #549 + INST(Pmaxsw , ExtRm_P , O(000F00,EE,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 104), // #550 + INST(Pmaxub , ExtRm_P , O(000F00,DE,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 104), // #551 + INST(Pmaxud , ExtRm , O(660F38,3F,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #552 + INST(Pmaxuw , ExtRm , O(660F38,3E,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #553 + INST(Pminsb , ExtRm , O(660F38,38,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #554 + INST(Pminsd , ExtRm , O(660F38,39,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #555 + INST(Pminsw , ExtRm_P , O(000F00,EA,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 104), // #556 + INST(Pminub , ExtRm_P , O(000F00,DA,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 104), // #557 + INST(Pminud , ExtRm , O(660F38,3B,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #558 + INST(Pminuw , ExtRm , O(660F38,3A,_,_,_,_,_,_ ), 0 , 2 , 0 , 12 , 13 ), // #559 + INST(Pmovmskb , ExtRm_P , O(000F00,D7,_,_,_,_,_,_ ), 0 , 5 , 0 , 167, 104), // #560 + INST(Pmovsxbd , ExtRm , O(660F38,21,_,_,_,_,_,_ ), 0 , 2 , 0 , 8 , 13 ), // #561 + INST(Pmovsxbq , ExtRm , O(660F38,22,_,_,_,_,_,_ ), 0 , 2 , 0 , 168, 13 ), // #562 + INST(Pmovsxbw , ExtRm , O(660F38,20,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #563 + INST(Pmovsxdq , ExtRm , O(660F38,25,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #564 + INST(Pmovsxwd , ExtRm , O(660F38,23,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #565 + INST(Pmovsxwq , ExtRm , O(660F38,24,_,_,_,_,_,_ ), 0 , 2 , 0 , 8 , 13 ), // #566 + INST(Pmovzxbd , ExtRm , O(660F38,31,_,_,_,_,_,_ ), 0 , 2 , 0 , 8 , 13 ), // #567 + INST(Pmovzxbq , ExtRm , O(660F38,32,_,_,_,_,_,_ ), 0 , 2 , 0 , 168, 13 ), // #568 + INST(Pmovzxbw , ExtRm , O(660F38,30,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #569 + INST(Pmovzxdq , ExtRm , O(660F38,35,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #570 + INST(Pmovzxwd , ExtRm , O(660F38,33,_,_,_,_,_,_ ), 0 , 2 , 0 , 7 , 13 ), // #571 + INST(Pmovzxwq , ExtRm , O(660F38,34,_,_,_,_,_,_ ), 0 , 2 , 0 , 8 , 13 ), // #572 + INST(Pmuldq , ExtRm , O(660F38,28,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 13 ), // #573 + INST(Pmulhrsw , ExtRm_P , O(000F38,0B,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #574 + INST(Pmulhrw , Ext3dNow , O(000F0F,B7,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 58 ), // #575 + INST(Pmulhuw , ExtRm_P , O(000F00,E4,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 104), // #576 + INST(Pmulhw , ExtRm_P , O(000F00,E5,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #577 + INST(Pmulld , ExtRm , O(660F38,40,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 13 ), // #578 + INST(Pmullw , ExtRm_P , O(000F00,D5,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #579 + INST(Pmuludq , ExtRm_P , O(000F00,F4,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 5 ), // #580 + INST(Pop , X86Pop , O(000000,8F,0,_,_,_,_,_ ), O(000000,58,_,_,_,_,_,_ ), 0 , 67 , 169, 0 ), // #581 + INST(Popa , X86Op , O(660000,61,_,_,_,_,_,_ ), 0 , 21 , 0 , 84 , 0 ), // #582 + INST(Popad , X86Op , O(000000,61,_,_,_,_,_,_ ), 0 , 0 , 0 , 84 , 0 ), // #583 + INST(Popcnt , X86Rm_Raw66H , O(F30F00,B8,_,_,x,_,_,_ ), 0 , 7 , 0 , 23 , 111), // #584 + INST(Popf , X86Op , O(660000,9D,_,_,_,_,_,_ ), 0 , 21 , 0 , 31 , 112), // #585 + INST(Popfd , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 84 , 112), // #586 + INST(Popfq , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 34 , 112), // #587 + INST(Por , ExtRm_P , O(000F00,EB,_,_,_,_,_,_ ), 0 , 5 , 0 , 152, 98 ), // #588 + INST(Prefetch , X86M_Only , O(000F00,0D,0,_,_,_,_,_ ), 0 , 5 , 0 , 32 , 58 ), // #589 + INST(Prefetchit0 , X86M_Only , O(000F00,18,7,_,_,_,_,_ ), 0 , 24 , 0 , 73 , 113), // #590 + INST(Prefetchit1 , X86M_Only , O(000F00,18,6,_,_,_,_,_ ), 0 , 82 , 0 , 73 , 113), // #591 + INST(Prefetchnta , X86M_Only , O(000F00,18,0,_,_,_,_,_ ), 0 , 5 , 0 , 32 , 6 ), // #592 + INST(Prefetcht0 , X86M_Only , O(000F00,18,1,_,_,_,_,_ ), 0 , 32 , 0 , 32 , 6 ), // #593 + INST(Prefetcht1 , X86M_Only , O(000F00,18,2,_,_,_,_,_ ), 0 , 78 , 0 , 32 , 6 ), // #594 + INST(Prefetcht2 , X86M_Only , O(000F00,18,3,_,_,_,_,_ ), 0 , 80 , 0 , 32 , 6 ), // #595 + INST(Prefetchw , X86M_Only , O(000F00,0D,1,_,_,_,_,_ ), 0 , 32 , 0 , 32 , 114), // #596 + INST(Prefetchwt1 , X86M_Only , O(000F00,0D,2,_,_,_,_,_ ), 0 , 78 , 0 , 32 , 115), // #597 + INST(Psadbw , ExtRm_P , O(000F00,F6,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 104), // #598 + INST(Pshufb , ExtRm_P , O(000F38,00,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #599 + INST(Pshufd , ExtRmi , O(660F00,70,_,_,_,_,_,_ ), 0 , 4 , 0 , 9 , 5 ), // #600 + INST(Pshufhw , ExtRmi , O(F30F00,70,_,_,_,_,_,_ ), 0 , 7 , 0 , 9 , 5 ), // #601 + INST(Pshuflw , ExtRmi , O(F20F00,70,_,_,_,_,_,_ ), 0 , 6 , 0 , 9 , 5 ), // #602 + INST(Pshufw , ExtRmi_P , O(000F00,70,_,_,_,_,_,_ ), 0 , 5 , 0 , 170, 90 ), // #603 + INST(Psignb , ExtRm_P , O(000F38,08,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #604 + INST(Psignd , ExtRm_P , O(000F38,0A,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #605 + INST(Psignw , ExtRm_P , O(000F38,09,_,_,_,_,_,_ ), 0 , 1 , 0 , 150, 103), // #606 + INST(Pslld , ExtRmRi_P , O(000F00,F2,_,_,_,_,_,_ ), O(000F00,72,6,_,_,_,_,_ ), 5 , 68 , 171, 98 ), // #607 + INST(Pslldq , ExtRmRi , 0 , O(660F00,73,7,_,_,_,_,_ ), 0 , 69 , 172, 5 ), // #608 + INST(Psllq , ExtRmRi_P , O(000F00,F3,_,_,_,_,_,_ ), O(000F00,73,6,_,_,_,_,_ ), 5 , 70 , 171, 98 ), // #609 + INST(Psllw , ExtRmRi_P , O(000F00,F1,_,_,_,_,_,_ ), O(000F00,71,6,_,_,_,_,_ ), 5 , 71 , 171, 98 ), // #610 + INST(Psmash , X86Op , O(F30F01,FF,_,_,_,_,_,_ ), 0 , 27 , 0 , 34 , 116), // #611 + INST(Psrad , ExtRmRi_P , O(000F00,E2,_,_,_,_,_,_ ), O(000F00,72,4,_,_,_,_,_ ), 5 , 72 , 171, 98 ), // #612 + INST(Psraw , ExtRmRi_P , O(000F00,E1,_,_,_,_,_,_ ), O(000F00,71,4,_,_,_,_,_ ), 5 , 73 , 171, 98 ), // #613 + INST(Psrld , ExtRmRi_P , O(000F00,D2,_,_,_,_,_,_ ), O(000F00,72,2,_,_,_,_,_ ), 5 , 74 , 171, 98 ), // #614 + INST(Psrldq , ExtRmRi , 0 , O(660F00,73,3,_,_,_,_,_ ), 0 , 75 , 172, 5 ), // #615 + INST(Psrlq , ExtRmRi_P , O(000F00,D3,_,_,_,_,_,_ ), O(000F00,73,2,_,_,_,_,_ ), 5 , 76 , 171, 98 ), // #616 + INST(Psrlw , ExtRmRi_P , O(000F00,D1,_,_,_,_,_,_ ), O(000F00,71,2,_,_,_,_,_ ), 5 , 77 , 171, 98 ), // #617 + INST(Psubb , ExtRm_P , O(000F00,F8,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #618 + INST(Psubd , ExtRm_P , O(000F00,FA,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #619 + INST(Psubq , ExtRm_P , O(000F00,FB,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 5 ), // #620 + INST(Psubsb , ExtRm_P , O(000F00,E8,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #621 + INST(Psubsw , ExtRm_P , O(000F00,E9,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #622 + INST(Psubusb , ExtRm_P , O(000F00,D8,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #623 + INST(Psubusw , ExtRm_P , O(000F00,D9,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #624 + INST(Psubw , ExtRm_P , O(000F00,F9,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #625 + INST(Pswapd , Ext3dNow , O(000F0F,BB,_,_,_,_,_,_ ), 0 , 88 , 0 , 154, 109), // #626 + INST(Ptest , ExtRm , O(660F38,17,_,_,_,_,_,_ ), 0 , 2 , 0 , 6 , 117), // #627 + INST(Ptwrite , X86M , O(F30F00,AE,4,_,_,_,_,_ ), 0 , 92 , 0 , 173, 118), // #628 + INST(Punpckhbw , ExtRm_P , O(000F00,68,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #629 + INST(Punpckhdq , ExtRm_P , O(000F00,6A,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #630 + INST(Punpckhqdq , ExtRm , O(660F00,6D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #631 + INST(Punpckhwd , ExtRm_P , O(000F00,69,_,_,_,_,_,_ ), 0 , 5 , 0 , 150, 98 ), // #632 + INST(Punpcklbw , ExtRm_P , O(000F00,60,_,_,_,_,_,_ ), 0 , 5 , 0 , 174, 98 ), // #633 + INST(Punpckldq , ExtRm_P , O(000F00,62,_,_,_,_,_,_ ), 0 , 5 , 0 , 174, 98 ), // #634 + INST(Punpcklqdq , ExtRm , O(660F00,6C,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #635 + INST(Punpcklwd , ExtRm_P , O(000F00,61,_,_,_,_,_,_ ), 0 , 5 , 0 , 174, 98 ), // #636 + INST(Push , X86Push , O(000000,FF,6,_,_,_,_,_ ), O(000000,50,_,_,_,_,_,_ ), 34 , 78 , 175, 0 ), // #637 + INST(Pusha , X86Op , O(660000,60,_,_,_,_,_,_ ), 0 , 21 , 0 , 84 , 0 ), // #638 + INST(Pushad , X86Op , O(000000,60,_,_,_,_,_,_ ), 0 , 0 , 0 , 84 , 0 ), // #639 + INST(Pushf , X86Op , O(660000,9C,_,_,_,_,_,_ ), 0 , 21 , 0 , 31 , 119), // #640 + INST(Pushfd , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 84 , 119), // #641 + INST(Pushfq , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 34 , 119), // #642 + INST(Pushw , X86Pushw , O(000000,FF,6,_,_,_,_,_ ), O(000000,50,_,_,_,_,_,_ ), 34 , 78 , 176, 0 ), // #643 + INST(Pvalidate , X86Op , O(F20F01,FF,_,_,_,_,_,_ ), 0 , 93 , 0 , 31 , 120), // #644 + INST(Pxor , ExtRm_P , O(000F00,EF,_,_,_,_,_,_ ), 0 , 5 , 0 , 153, 98 ), // #645 + INST(Rcl , X86Rot , O(000000,D0,2,_,x,_,_,_ ), 0 , 3 , 0 , 177, 121), // #646 + INST(Rcpps , ExtRm , O(000F00,53,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #647 + INST(Rcpss , ExtRm , O(F30F00,53,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #648 + INST(Rcr , X86Rot , O(000000,D0,3,_,x,_,_,_ ), 0 , 77 , 0 , 177, 121), // #649 + INST(Rdfsbase , X86M , O(F30F00,AE,0,_,x,_,_,_ ), 0 , 7 , 0 , 178, 122), // #650 + INST(Rdgsbase , X86M , O(F30F00,AE,1,_,x,_,_,_ ), 0 , 94 , 0 , 178, 122), // #651 + INST(Rdmsr , X86Op , O(000F00,32,_,_,_,_,_,_ ), 0 , 5 , 0 , 179, 123), // #652 + INST(Rdpid , X86R_Native , O(F30F00,C7,7,_,_,_,_,_ ), 0 , 95 , 0 , 180, 124), // #653 + INST(Rdpkru , X86Op , O(000F01,EE,_,_,_,_,_,_ ), 0 , 23 , 0 , 181, 125), // #654 + INST(Rdpmc , X86Op , O(000F00,33,_,_,_,_,_,_ ), 0 , 5 , 0 , 181, 0 ), // #655 + INST(Rdpru , X86Op , O(000F01,FD,_,_,_,_,_,_ ), 0 , 23 , 0 , 181, 126), // #656 + INST(Rdrand , X86M , O(000F00,C7,6,_,x,_,_,_ ), 0 , 82 , 0 , 24 , 127), // #657 + INST(Rdseed , X86M , O(000F00,C7,7,_,x,_,_,_ ), 0 , 24 , 0 , 24 , 128), // #658 + INST(Rdsspd , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 94 , 0 , 79 , 65 ), // #659 + INST(Rdsspq , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 94 , 0 , 80 , 65 ), // #660 + INST(Rdtsc , X86Op , O(000F00,31,_,_,_,_,_,_ ), 0 , 5 , 0 , 29 , 129), // #661 + INST(Rdtscp , X86Op , O(000F01,F9,_,_,_,_,_,_ ), 0 , 23 , 0 , 181, 130), // #662 + INST(Ret , X86Ret , O(000000,C2,_,_,_,_,_,_ ), 0 , 0 , 0 , 182, 0 ), // #663 + INST(Retf , X86Ret , O(000000,CA,_,_,x,_,_,_ ), 0 , 0 , 0 , 183, 0 ), // #664 + INST(Rmpadjust , X86Op , O(F30F01,FE,_,_,_,_,_,_ ), 0 , 27 , 0 , 34 , 116), // #665 + INST(Rmpupdate , X86Op , O(F20F01,FE,_,_,_,_,_,_ ), 0 , 93 , 0 , 34 , 116), // #666 + INST(Rol , X86Rot , O(000000,D0,0,_,x,_,_,_ ), 0 , 0 , 0 , 177, 131), // #667 + INST(Ror , X86Rot , O(000000,D0,1,_,x,_,_,_ ), 0 , 33 , 0 , 177, 131), // #668 + INST(Rorx , VexRmi_Wx , V(F20F3A,F0,_,0,x,_,_,_ ), 0 , 96 , 0 , 184, 102), // #669 + INST(Roundpd , ExtRmi , O(660F3A,09,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #670 + INST(Roundps , ExtRmi , O(660F3A,08,_,_,_,_,_,_ ), 0 , 9 , 0 , 9 , 13 ), // #671 + INST(Roundsd , ExtRmi , O(660F3A,0B,_,_,_,_,_,_ ), 0 , 9 , 0 , 39 , 13 ), // #672 + INST(Roundss , ExtRmi , O(660F3A,0A,_,_,_,_,_,_ ), 0 , 9 , 0 , 40 , 13 ), // #673 + INST(Rsm , X86Op , O(000F00,AA,_,_,_,_,_,_ ), 0 , 5 , 0 , 84 , 1 ), // #674 + INST(Rsqrtps , ExtRm , O(000F00,52,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #675 + INST(Rsqrtss , ExtRm , O(F30F00,52,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #676 + INST(Rstorssp , X86M_Only , O(F30F00,01,5,_,_,_,_,_ ), 0 , 65 , 0 , 33 , 25 ), // #677 + INST(Sahf , X86Op , O(000000,9E,_,_,_,_,_,_ ), 0 , 0 , 0 , 102, 132), // #678 + INST(Sar , X86Rot , O(000000,D0,7,_,x,_,_,_ ), 0 , 29 , 0 , 177, 1 ), // #679 + INST(Sarx , VexRmv_Wx , V(F30F38,F7,_,0,x,_,_,_ ), 0 , 89 , 0 , 14 , 102), // #680 + INST(Saveprevssp , X86Op , O(F30F01,EA,_,_,_,_,_,_ ), 0 , 27 , 0 , 31 , 25 ), // #681 + INST(Sbb , X86Arith , O(000000,18,3,_,x,_,_,_ ), 0 , 77 , 0 , 185, 3 ), // #682 + INST(Scas , X86StrRm , O(000000,AE,_,_,_,_,_,_ ), 0 , 0 , 0 , 186, 39 ), // #683 + INST(Seamcall , X86Op , O(660F01,CF,_,_,_,_,_,_ ), 0 , 97 , 0 , 31 , 133), // #684 + INST(Seamops , X86Op , O(660F01,CE,_,_,_,_,_,_ ), 0 , 97 , 0 , 31 , 133), // #685 + INST(Seamret , X86Op , O(660F01,CD,_,_,_,_,_,_ ), 0 , 97 , 0 , 31 , 133), // #686 + INST(Senduipi , X86M_NoSize , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 26 , 0 , 80 , 26 ), // #687 + INST(Serialize , X86Op , O(000F01,E8,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 134), // #688 + INST(Setb , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 69 ), // #689 + INST(Setbe , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 70 ), // #690 + INST(Setl , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 71 ), // #691 + INST(Setle , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 72 ), // #692 + INST(Setnb , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 69 ), // #693 + INST(Setnbe , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 70 ), // #694 + INST(Setnl , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 71 ), // #695 + INST(Setnle , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 72 ), // #696 + INST(Setno , X86Set , O(000F00,91,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 66 ), // #697 + INST(Setnp , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 73 ), // #698 + INST(Setns , X86Set , O(000F00,99,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 74 ), // #699 + INST(Setnz , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 75 ), // #700 + INST(Seto , X86Set , O(000F00,90,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 66 ), // #701 + INST(Setp , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 73 ), // #702 + INST(Sets , X86Set , O(000F00,98,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 74 ), // #703 + INST(Setssbsy , X86Op , O(F30F01,E8,_,_,_,_,_,_ ), 0 , 27 , 0 , 31 , 65 ), // #704 + INST(Setz , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 5 , 0 , 187, 75 ), // #705 + INST(Sfence , X86Fence , O(000F00,AE,7,_,_,_,_,_ ), 0 , 24 , 0 , 31 , 6 ), // #706 + INST(Sgdt , X86M_Only , O(000F00,01,0,_,_,_,_,_ ), 0 , 5 , 0 , 32 , 0 ), // #707 + INST(Sha1msg1 , ExtRm , O(000F38,C9,_,_,_,_,_,_ ), 0 , 1 , 0 , 6 , 135), // #708 + INST(Sha1msg2 , ExtRm , O(000F38,CA,_,_,_,_,_,_ ), 0 , 1 , 0 , 6 , 135), // #709 + INST(Sha1nexte , ExtRm , O(000F38,C8,_,_,_,_,_,_ ), 0 , 1 , 0 , 6 , 135), // #710 + INST(Sha1rnds4 , ExtRmi , O(000F3A,CC,_,_,_,_,_,_ ), 0 , 86 , 0 , 9 , 135), // #711 + INST(Sha256msg1 , ExtRm , O(000F38,CC,_,_,_,_,_,_ ), 0 , 1 , 0 , 6 , 135), // #712 + INST(Sha256msg2 , ExtRm , O(000F38,CD,_,_,_,_,_,_ ), 0 , 1 , 0 , 6 , 135), // #713 + INST(Sha256rnds2 , ExtRm_XMM0 , O(000F38,CB,_,_,_,_,_,_ ), 0 , 1 , 0 , 16 , 135), // #714 + INST(Shl , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 10 , 0 , 177, 1 ), // #715 + INST(Shld , X86ShldShrd , O(000F00,A4,_,_,x,_,_,_ ), 0 , 5 , 0 , 188, 1 ), // #716 + INST(Shlx , VexRmv_Wx , V(660F38,F7,_,0,x,_,_,_ ), 0 , 30 , 0 , 14 , 102), // #717 + INST(Shr , X86Rot , O(000000,D0,5,_,x,_,_,_ ), 0 , 64 , 0 , 177, 1 ), // #718 + INST(Shrd , X86ShldShrd , O(000F00,AC,_,_,x,_,_,_ ), 0 , 5 , 0 , 188, 1 ), // #719 + INST(Shrx , VexRmv_Wx , V(F20F38,F7,_,0,x,_,_,_ ), 0 , 85 , 0 , 14 , 102), // #720 + INST(Shufpd , ExtRmi , O(660F00,C6,_,_,_,_,_,_ ), 0 , 4 , 0 , 9 , 5 ), // #721 + INST(Shufps , ExtRmi , O(000F00,C6,_,_,_,_,_,_ ), 0 , 5 , 0 , 9 , 6 ), // #722 + INST(Sidt , X86M_Only , O(000F00,01,1,_,_,_,_,_ ), 0 , 32 , 0 , 32 , 0 ), // #723 + INST(Skinit , X86Op_xAX , O(000F01,DE,_,_,_,_,_,_ ), 0 , 23 , 0 , 54 , 136), // #724 + INST(Sldt , X86M_NoMemSize , O(000F00,00,0,_,_,_,_,_ ), 0 , 5 , 0 , 189, 0 ), // #725 + INST(Slwpcb , VexR_Wx , V(XOP_M9,12,1,0,x,_,_,_ ), 0 , 13 , 0 , 113, 87 ), // #726 + INST(Smsw , X86M_NoMemSize , O(000F00,01,4,_,_,_,_,_ ), 0 , 98 , 0 , 189, 0 ), // #727 + INST(Sqrtpd , ExtRm , O(660F00,51,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #728 + INST(Sqrtps , ExtRm , O(000F00,51,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #729 + INST(Sqrtsd , ExtRm , O(F20F00,51,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #730 + INST(Sqrtss , ExtRm , O(F30F00,51,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #731 + INST(Stac , X86Op , O(000F01,CB,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 17 ), // #732 + INST(Stc , X86Op , O(000000,F9,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 18 ), // #733 + INST(Std , X86Op , O(000000,FD,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 19 ), // #734 + INST(Stgi , X86Op , O(000F01,DC,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 136), // #735 + INST(Sti , X86Op , O(000000,FB,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 24 ), // #736 + INST(Stmxcsr , X86M_Only , O(000F00,AE,3,_,_,_,_,_ ), 0 , 80 , 0 , 106, 6 ), // #737 + INST(Stos , X86StrMr , O(000000,AA,_,_,_,_,_,_ ), 0 , 0 , 0 , 190, 88 ), // #738 + INST(Str , X86M_NoMemSize , O(000F00,00,1,_,_,_,_,_ ), 0 , 32 , 0 , 189, 0 ), // #739 + INST(Sttilecfg , AmxCfg , V(660F38,49,_,0,0,_,_,_ ), 0 , 30 , 0 , 108, 86 ), // #740 + INST(Stui , X86Op , O(F30F01,EF,_,_,_,_,_,_ ), 0 , 27 , 0 , 34 , 26 ), // #741 + INST(Sub , X86Arith , O(000000,28,5,_,x,_,_,_ ), 0 , 64 , 0 , 185, 1 ), // #742 + INST(Subpd , ExtRm , O(660F00,5C,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #743 + INST(Subps , ExtRm , O(000F00,5C,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #744 + INST(Subsd , ExtRm , O(F20F00,5C,_,_,_,_,_,_ ), 0 , 6 , 0 , 7 , 5 ), // #745 + INST(Subss , ExtRm , O(F30F00,5C,_,_,_,_,_,_ ), 0 , 7 , 0 , 8 , 6 ), // #746 + INST(Swapgs , X86Op , O(000F01,F8,_,_,_,_,_,_ ), 0 , 23 , 0 , 34 , 0 ), // #747 + INST(Syscall , X86Op , O(000F00,05,_,_,_,_,_,_ ), 0 , 5 , 0 , 34 , 0 ), // #748 + INST(Sysenter , X86Op , O(000F00,34,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 0 ), // #749 + INST(Sysexit , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 0 ), // #750 + INST(Sysexitq , X86Op , O(000F00,35,_,_,1,_,_,_ ), 0 , 62 , 0 , 34 , 0 ), // #751 + INST(Sysret , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 5 , 0 , 34 , 0 ), // #752 + INST(Sysretq , X86Op , O(000F00,07,_,_,1,_,_,_ ), 0 , 62 , 0 , 34 , 0 ), // #753 + INST(T1mskc , VexVm_Wx , V(XOP_M9,01,7,0,x,_,_,_ ), 0 , 99 , 0 , 15 , 12 ), // #754 + INST(Tcmmimfp16ps , AmxRmv , V(660F38,6C,_,0,0,_,_,_ ), 0 , 30 , 0 , 191, 137), // #755 + INST(Tcmmrlfp16ps , AmxRmv , V(000F38,6C,_,0,0,_,_,_ ), 0 , 11 , 0 , 191, 137), // #756 + INST(Tdcall , X86Op , O(660F01,CC,_,_,_,_,_,_ ), 0 , 97 , 0 , 31 , 133), // #757 + INST(Tdpbf16ps , AmxRmv , V(F30F38,5C,_,0,0,_,_,_ ), 0 , 89 , 0 , 191, 138), // #758 + INST(Tdpbssd , AmxRmv , V(F20F38,5E,_,0,0,_,_,_ ), 0 , 85 , 0 , 191, 139), // #759 + INST(Tdpbsud , AmxRmv , V(F30F38,5E,_,0,0,_,_,_ ), 0 , 89 , 0 , 191, 139), // #760 + INST(Tdpbusd , AmxRmv , V(660F38,5E,_,0,0,_,_,_ ), 0 , 30 , 0 , 191, 139), // #761 + INST(Tdpbuud , AmxRmv , V(000F38,5E,_,0,0,_,_,_ ), 0 , 11 , 0 , 191, 139), // #762 + INST(Tdpfp16ps , AmxRmv , V(F20F38,5C,_,0,0,_,_,_ ), 0 , 85 , 0 , 191, 140), // #763 + INST(Test , X86Test , O(000000,84,_,_,x,_,_,_ ), O(000000,F6,_,_,x,_,_,_ ), 0 , 79 , 192, 1 ), // #764 + INST(Testui , X86Op , O(F30F01,ED,_,_,_,_,_,_ ), 0 , 27 , 0 , 34 , 141), // #765 + INST(Tileloadd , AmxRm , V(F20F38,4B,_,0,0,_,_,_ ), 0 , 85 , 0 , 193, 86 ), // #766 + INST(Tileloaddt1 , AmxRm , V(660F38,4B,_,0,0,_,_,_ ), 0 , 30 , 0 , 193, 86 ), // #767 + INST(Tilerelease , VexOpMod , V(000F38,49,0,0,0,_,_,_ ), 0 , 11 , 0 , 194, 86 ), // #768 + INST(Tilestored , AmxMr , V(F30F38,4B,_,0,0,_,_,_ ), 0 , 89 , 0 , 195, 86 ), // #769 + INST(Tilezero , AmxR , V(F20F38,49,_,0,0,_,_,_ ), 0 , 85 , 0 , 196, 86 ), // #770 + INST(Tlbsync , X86Op , O(000F01,FF,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 68 ), // #771 + INST(Tpause , X86R32_EDX_EAX , O(660F00,AE,6,_,_,_,_,_ ), 0 , 28 , 0 , 197, 142), // #772 + INST(Tzcnt , X86Rm_Raw66H , O(F30F00,BC,_,_,x,_,_,_ ), 0 , 7 , 0 , 23 , 10 ), // #773 + INST(Tzmsk , VexVm_Wx , V(XOP_M9,01,4,0,x,_,_,_ ), 0 , 100, 0 , 15 , 12 ), // #774 + INST(Ucomisd , ExtRm , O(660F00,2E,_,_,_,_,_,_ ), 0 , 4 , 0 , 7 , 43 ), // #775 + INST(Ucomiss , ExtRm , O(000F00,2E,_,_,_,_,_,_ ), 0 , 5 , 0 , 8 , 44 ), // #776 + INST(Ud0 , X86Rm , O(000F00,FF,_,_,_,_,_,_ ), 0 , 5 , 0 , 198, 0 ), // #777 + INST(Ud1 , X86Rm , O(000F00,B9,_,_,_,_,_,_ ), 0 , 5 , 0 , 198, 0 ), // #778 + INST(Ud2 , X86Op , O(000F00,0B,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 0 ), // #779 + INST(Uiret , X86Op , O(F30F01,EC,_,_,_,_,_,_ ), 0 , 27 , 0 , 34 , 26 ), // #780 + INST(Umonitor , X86R_FromM , O(F30F00,AE,6,_,_,_,_,_ ), 0 , 26 , 0 , 199, 143), // #781 + INST(Umwait , X86R32_EDX_EAX , O(F20F00,AE,6,_,_,_,_,_ ), 0 , 101, 0 , 197, 142), // #782 + INST(Unpckhpd , ExtRm , O(660F00,15,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #783 + INST(Unpckhps , ExtRm , O(000F00,15,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #784 + INST(Unpcklpd , ExtRm , O(660F00,14,_,_,_,_,_,_ ), 0 , 4 , 0 , 6 , 5 ), // #785 + INST(Unpcklps , ExtRm , O(000F00,14,_,_,_,_,_,_ ), 0 , 5 , 0 , 6 , 6 ), // #786 + INST(Vaddpd , VexRvm_Lx , V(660F00,58,_,x,I,1,4,FV ), 0 , 102, 0 , 200, 144), // #787 + INST(Vaddph , VexRvm_Lx , E(00MAP5,58,_,_,_,0,4,FV ), 0 , 103, 0 , 201, 145), // #788 + INST(Vaddps , VexRvm_Lx , V(000F00,58,_,x,I,0,4,FV ), 0 , 104, 0 , 202, 144), // #789 + INST(Vaddsd , VexRvm , V(F20F00,58,_,I,I,1,3,T1S), 0 , 105, 0 , 203, 144), // #790 + INST(Vaddsh , VexRvm , E(F3MAP5,58,_,_,_,0,1,T1S), 0 , 106, 0 , 204, 145), // #791 + INST(Vaddss , VexRvm , V(F30F00,58,_,I,I,0,2,T1S), 0 , 107, 0 , 205, 144), // #792 + INST(Vaddsubpd , VexRvm_Lx , V(660F00,D0,_,x,I,_,_,_ ), 0 , 71 , 0 , 206, 146), // #793 + INST(Vaddsubps , VexRvm_Lx , V(F20F00,D0,_,x,I,_,_,_ ), 0 , 108, 0 , 206, 146), // #794 + INST(Vaesdec , VexRvm_Lx , V(660F38,DE,_,x,I,_,4,FVM), 0 , 109, 0 , 207, 147), // #795 + INST(Vaesdeclast , VexRvm_Lx , V(660F38,DF,_,x,I,_,4,FVM), 0 , 109, 0 , 207, 147), // #796 + INST(Vaesenc , VexRvm_Lx , V(660F38,DC,_,x,I,_,4,FVM), 0 , 109, 0 , 207, 147), // #797 + INST(Vaesenclast , VexRvm_Lx , V(660F38,DD,_,x,I,_,4,FVM), 0 , 109, 0 , 207, 147), // #798 + INST(Vaesimc , VexRm , V(660F38,DB,_,0,I,_,_,_ ), 0 , 30 , 0 , 208, 148), // #799 + INST(Vaeskeygenassist , VexRmi , V(660F3A,DF,_,0,I,_,_,_ ), 0 , 75 , 0 , 209, 148), // #800 + INST(Valignd , VexRvmi_Lx , E(660F3A,03,_,x,_,0,4,FV ), 0 , 110, 0 , 210, 149), // #801 + INST(Valignq , VexRvmi_Lx , E(660F3A,03,_,x,_,1,4,FV ), 0 , 111, 0 , 211, 149), // #802 + INST(Vandnpd , VexRvm_Lx , V(660F00,55,_,x,I,1,4,FV ), 0 , 102, 0 , 212, 150), // #803 + INST(Vandnps , VexRvm_Lx , V(000F00,55,_,x,I,0,4,FV ), 0 , 104, 0 , 213, 150), // #804 + INST(Vandpd , VexRvm_Lx , V(660F00,54,_,x,I,1,4,FV ), 0 , 102, 0 , 214, 150), // #805 + INST(Vandps , VexRvm_Lx , V(000F00,54,_,x,I,0,4,FV ), 0 , 104, 0 , 215, 150), // #806 + INST(Vbcstnebf162ps , VexRm_Lx , V(F30F38,B1,_,x,0,_,_,_ ), 0 , 89 , 0 , 216, 151), // #807 + INST(Vbcstnesh2ps , VexRm_Lx , V(660F38,B1,_,x,0,_,_,_ ), 0 , 30 , 0 , 216, 151), // #808 + INST(Vblendmpd , VexRvm_Lx , E(660F38,65,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #809 + INST(Vblendmps , VexRvm_Lx , E(660F38,65,_,x,_,0,4,FV ), 0 , 113, 0 , 218, 149), // #810 + INST(Vblendpd , VexRvmi_Lx , V(660F3A,0D,_,x,I,_,_,_ ), 0 , 75 , 0 , 219, 146), // #811 + INST(Vblendps , VexRvmi_Lx , V(660F3A,0C,_,x,I,_,_,_ ), 0 , 75 , 0 , 219, 146), // #812 + INST(Vblendvpd , VexRvmr_Lx , V(660F3A,4B,_,x,0,_,_,_ ), 0 , 75 , 0 , 220, 146), // #813 + INST(Vblendvps , VexRvmr_Lx , V(660F3A,4A,_,x,0,_,_,_ ), 0 , 75 , 0 , 220, 146), // #814 + INST(Vbroadcastf128 , VexRm , V(660F38,1A,_,1,0,_,_,_ ), 0 , 114, 0 , 221, 146), // #815 + INST(Vbroadcastf32x2 , VexRm_Lx , E(660F38,19,_,x,_,0,3,T2 ), 0 , 115, 0 , 222, 152), // #816 + INST(Vbroadcastf32x4 , VexRm_Lx , E(660F38,1A,_,x,_,0,4,T4 ), 0 , 116, 0 , 223, 149), // #817 + INST(Vbroadcastf32x8 , VexRm , E(660F38,1B,_,2,_,0,5,T8 ), 0 , 117, 0 , 224, 152), // #818 + INST(Vbroadcastf64x2 , VexRm_Lx , E(660F38,1A,_,x,_,1,4,T2 ), 0 , 118, 0 , 223, 152), // #819 + INST(Vbroadcastf64x4 , VexRm , E(660F38,1B,_,2,_,1,5,T4 ), 0 , 119, 0 , 224, 149), // #820 + INST(Vbroadcasti128 , VexRm , V(660F38,5A,_,1,0,_,_,_ ), 0 , 114, 0 , 221, 153), // #821 + INST(Vbroadcasti32x2 , VexRm_Lx , E(660F38,59,_,x,_,0,3,T2 ), 0 , 115, 0 , 225, 152), // #822 + INST(Vbroadcasti32x4 , VexRm_Lx , E(660F38,5A,_,x,_,0,4,T4 ), 0 , 116, 0 , 223, 149), // #823 + INST(Vbroadcasti32x8 , VexRm , E(660F38,5B,_,2,_,0,5,T8 ), 0 , 117, 0 , 224, 152), // #824 + INST(Vbroadcasti64x2 , VexRm_Lx , E(660F38,5A,_,x,_,1,4,T2 ), 0 , 118, 0 , 223, 152), // #825 + INST(Vbroadcasti64x4 , VexRm , E(660F38,5B,_,2,_,1,5,T4 ), 0 , 119, 0 , 224, 149), // #826 + INST(Vbroadcastsd , VexRm_Lx , V(660F38,19,_,x,0,1,3,T1S), 0 , 120, 0 , 226, 154), // #827 + INST(Vbroadcastss , VexRm_Lx , V(660F38,18,_,x,0,0,2,T1S), 0 , 121, 0 , 227, 154), // #828 + INST(Vcmppd , VexRvmi_Lx_KEvex , V(660F00,C2,_,x,I,1,4,FV ), 0 , 102, 0 , 228, 144), // #829 + INST(Vcmpph , VexRvmi_Lx_KEvex , E(000F3A,C2,_,_,_,0,4,FV ), 0 , 122, 0 , 229, 145), // #830 + INST(Vcmpps , VexRvmi_Lx_KEvex , V(000F00,C2,_,x,I,0,4,FV ), 0 , 104, 0 , 230, 144), // #831 + INST(Vcmpsd , VexRvmi_KEvex , V(F20F00,C2,_,I,I,1,3,T1S), 0 , 105, 0 , 231, 144), // #832 + INST(Vcmpsh , VexRvmi_KEvex , E(F30F3A,C2,_,_,_,0,1,T1S), 0 , 123, 0 , 232, 145), // #833 + INST(Vcmpss , VexRvmi_KEvex , V(F30F00,C2,_,I,I,0,2,T1S), 0 , 107, 0 , 233, 144), // #834 + INST(Vcomisd , VexRm , V(660F00,2F,_,I,I,1,3,T1S), 0 , 124, 0 , 234, 155), // #835 + INST(Vcomish , VexRm , E(00MAP5,2F,_,_,_,0,1,T1S), 0 , 125, 0 , 235, 156), // #836 + INST(Vcomiss , VexRm , V(000F00,2F,_,I,I,0,2,T1S), 0 , 126, 0 , 236, 155), // #837 + INST(Vcompresspd , VexMr_Lx , E(660F38,8A,_,x,_,1,3,T1S), 0 , 127, 0 , 237, 149), // #838 + INST(Vcompressps , VexMr_Lx , E(660F38,8A,_,x,_,0,2,T1S), 0 , 128, 0 , 237, 149), // #839 + INST(Vcvtdq2pd , VexRm_Lx , V(F30F00,E6,_,x,I,0,3,HV ), 0 , 129, 0 , 238, 144), // #840 + INST(Vcvtdq2ph , VexRm_Lx_Narrow , E(00MAP5,5B,_,x,0,0,4,FV ), 0 , 103, 0 , 239, 145), // #841 + INST(Vcvtdq2ps , VexRm_Lx , V(000F00,5B,_,x,I,0,4,FV ), 0 , 104, 0 , 240, 144), // #842 + INST(Vcvtne2ps2bf16 , VexRvm_Lx , E(F20F38,72,_,_,_,0,4,FV ), 0 , 130, 0 , 218, 157), // #843 + INST(Vcvtneebf162ps , VexRm_Lx , V(F30F38,B0,_,x,0,_,_,_ ), 0 , 89 , 0 , 241, 151), // #844 + INST(Vcvtneeph2ps , VexRm_Lx , V(660F38,B0,_,x,0,_,_,_ ), 0 , 30 , 0 , 241, 151), // #845 + INST(Vcvtneobf162ps , VexRm_Lx , V(F20F38,B0,_,x,0,_,_,_ ), 0 , 85 , 0 , 241, 151), // #846 + INST(Vcvtneoph2ps , VexRm_Lx , V(000F38,B0,_,x,0,_,_,_ ), 0 , 11 , 0 , 241, 151), // #847 + INST(Vcvtneps2bf16 , VexRm_Lx_Narrow , V(F30F38,72,_,_,_,0,4,FV ), 0 , 131, 0 , 242, 158), // #848 + INST(Vcvtpd2dq , VexRm_Lx_Narrow , V(F20F00,E6,_,x,I,1,4,FV ), 0 , 132, 0 , 243, 144), // #849 + INST(Vcvtpd2ph , VexRm_Lx , E(66MAP5,5A,_,_,_,1,4,FV ), 0 , 133, 0 , 244, 145), // #850 + INST(Vcvtpd2ps , VexRm_Lx_Narrow , V(660F00,5A,_,x,I,1,4,FV ), 0 , 102, 0 , 243, 144), // #851 + INST(Vcvtpd2qq , VexRm_Lx , E(660F00,7B,_,x,_,1,4,FV ), 0 , 134, 0 , 245, 152), // #852 + INST(Vcvtpd2udq , VexRm_Lx_Narrow , E(000F00,79,_,x,_,1,4,FV ), 0 , 135, 0 , 246, 149), // #853 + INST(Vcvtpd2uqq , VexRm_Lx , E(660F00,79,_,x,_,1,4,FV ), 0 , 134, 0 , 245, 152), // #854 + INST(Vcvtph2dq , VexRm_Lx , E(66MAP5,5B,_,_,_,0,3,HV ), 0 , 136, 0 , 247, 145), // #855 + INST(Vcvtph2pd , VexRm_Lx , E(00MAP5,5A,_,_,_,0,2,QV ), 0 , 137, 0 , 248, 145), // #856 + INST(Vcvtph2ps , VexRm_Lx , V(660F38,13,_,x,0,0,3,HVM), 0 , 138, 0 , 249, 159), // #857 + INST(Vcvtph2psx , VexRm_Lx , E(66MAP6,13,_,_,_,0,3,HV ), 0 , 139, 0 , 250, 145), // #858 + INST(Vcvtph2qq , VexRm_Lx , E(66MAP5,7B,_,_,_,0,2,QV ), 0 , 140, 0 , 251, 145), // #859 + INST(Vcvtph2udq , VexRm_Lx , E(00MAP5,79,_,_,_,0,3,HV ), 0 , 141, 0 , 247, 145), // #860 + INST(Vcvtph2uqq , VexRm_Lx , E(66MAP5,79,_,_,_,0,2,QV ), 0 , 140, 0 , 251, 145), // #861 + INST(Vcvtph2uw , VexRm_Lx , E(00MAP5,7D,_,_,_,0,4,FV ), 0 , 103, 0 , 252, 145), // #862 + INST(Vcvtph2w , VexRm_Lx , E(66MAP5,7D,_,_,_,0,4,FV ), 0 , 142, 0 , 252, 145), // #863 + INST(Vcvtps2dq , VexRm_Lx , V(660F00,5B,_,x,I,0,4,FV ), 0 , 143, 0 , 240, 144), // #864 + INST(Vcvtps2pd , VexRm_Lx , V(000F00,5A,_,x,I,0,3,HV ), 0 , 144, 0 , 253, 144), // #865 + INST(Vcvtps2ph , VexMri_Lx , V(660F3A,1D,_,x,0,0,3,HVM), 0 , 145, 0 , 254, 159), // #866 + INST(Vcvtps2phx , VexRm_Lx_Narrow , E(66MAP5,1D,_,_,_,0,4,FV ), 0 , 142, 0 , 239, 145), // #867 + INST(Vcvtps2qq , VexRm_Lx , E(660F00,7B,_,x,_,0,3,HV ), 0 , 146, 0 , 255, 152), // #868 + INST(Vcvtps2udq , VexRm_Lx , E(000F00,79,_,x,_,0,4,FV ), 0 , 147, 0 , 256, 149), // #869 + INST(Vcvtps2uqq , VexRm_Lx , E(660F00,79,_,x,_,0,3,HV ), 0 , 146, 0 , 255, 152), // #870 + INST(Vcvtqq2pd , VexRm_Lx , E(F30F00,E6,_,x,_,1,4,FV ), 0 , 148, 0 , 245, 152), // #871 + INST(Vcvtqq2ph , VexRm_Lx , E(00MAP5,5B,_,_,_,1,4,FV ), 0 , 149, 0 , 244, 145), // #872 + INST(Vcvtqq2ps , VexRm_Lx_Narrow , E(000F00,5B,_,x,_,1,4,FV ), 0 , 135, 0 , 246, 152), // #873 + INST(Vcvtsd2sh , VexRvm , E(F2MAP5,5A,_,_,_,1,3,T1S), 0 , 150, 0 , 257, 145), // #874 + INST(Vcvtsd2si , VexRm_Wx , V(F20F00,2D,_,I,x,x,3,T1F), 0 , 151, 0 , 258, 144), // #875 + INST(Vcvtsd2ss , VexRvm , V(F20F00,5A,_,I,I,1,3,T1S), 0 , 105, 0 , 203, 144), // #876 + INST(Vcvtsd2usi , VexRm_Wx , E(F20F00,79,_,I,_,x,3,T1F), 0 , 152, 0 , 259, 149), // #877 + INST(Vcvtsh2sd , VexRvm , E(F3MAP5,5A,_,_,_,0,1,T1S), 0 , 106, 0 , 260, 145), // #878 + INST(Vcvtsh2si , VexRm_Wx , E(F3MAP5,2D,_,_,_,x,1,T1S), 0 , 106, 0 , 261, 145), // #879 + INST(Vcvtsh2ss , VexRvm , E(00MAP6,13,_,_,_,0,1,T1S), 0 , 153, 0 , 260, 145), // #880 + INST(Vcvtsh2usi , VexRm_Wx , E(F3MAP5,79,_,_,_,x,1,T1S), 0 , 106, 0 , 261, 145), // #881 + INST(Vcvtsi2sd , VexRvm_Wx , V(F20F00,2A,_,I,x,x,2,T1W), 0 , 154, 0 , 262, 144), // #882 + INST(Vcvtsi2sh , VexRvm_Wx , E(F3MAP5,2A,_,_,_,x,2,T1W), 0 , 155, 0 , 263, 145), // #883 + INST(Vcvtsi2ss , VexRvm_Wx , V(F30F00,2A,_,I,x,x,2,T1W), 0 , 156, 0 , 262, 144), // #884 + INST(Vcvtss2sd , VexRvm , V(F30F00,5A,_,I,I,0,2,T1S), 0 , 107, 0 , 264, 144), // #885 + INST(Vcvtss2sh , VexRvm , E(00MAP5,1D,_,_,_,0,2,T1S), 0 , 157, 0 , 265, 145), // #886 + INST(Vcvtss2si , VexRm_Wx , V(F30F00,2D,_,I,x,x,2,T1F), 0 , 107, 0 , 266, 144), // #887 + INST(Vcvtss2usi , VexRm_Wx , E(F30F00,79,_,I,_,x,2,T1F), 0 , 158, 0 , 267, 149), // #888 + INST(Vcvttpd2dq , VexRm_Lx_Narrow , V(660F00,E6,_,x,I,1,4,FV ), 0 , 102, 0 , 268, 144), // #889 + INST(Vcvttpd2qq , VexRm_Lx , E(660F00,7A,_,x,_,1,4,FV ), 0 , 134, 0 , 269, 149), // #890 + INST(Vcvttpd2udq , VexRm_Lx_Narrow , E(000F00,78,_,x,_,1,4,FV ), 0 , 135, 0 , 270, 149), // #891 + INST(Vcvttpd2uqq , VexRm_Lx , E(660F00,78,_,x,_,1,4,FV ), 0 , 134, 0 , 269, 152), // #892 + INST(Vcvttph2dq , VexRm_Lx , E(F3MAP5,5B,_,_,_,0,3,HV ), 0 , 159, 0 , 250, 145), // #893 + INST(Vcvttph2qq , VexRm_Lx , E(66MAP5,7A,_,_,_,0,2,QV ), 0 , 140, 0 , 248, 145), // #894 + INST(Vcvttph2udq , VexRm_Lx , E(00MAP5,78,_,_,_,0,3,HV ), 0 , 141, 0 , 250, 145), // #895 + INST(Vcvttph2uqq , VexRm_Lx , E(66MAP5,78,_,_,_,0,2,QV ), 0 , 140, 0 , 248, 145), // #896 + INST(Vcvttph2uw , VexRm_Lx , E(00MAP5,7C,_,_,_,0,4,FV ), 0 , 103, 0 , 271, 145), // #897 + INST(Vcvttph2w , VexRm_Lx , E(66MAP5,7C,_,_,_,0,4,FV ), 0 , 142, 0 , 271, 145), // #898 + INST(Vcvttps2dq , VexRm_Lx , V(F30F00,5B,_,x,I,0,4,FV ), 0 , 160, 0 , 272, 144), // #899 + INST(Vcvttps2qq , VexRm_Lx , E(660F00,7A,_,x,_,0,3,HV ), 0 , 146, 0 , 273, 152), // #900 + INST(Vcvttps2udq , VexRm_Lx , E(000F00,78,_,x,_,0,4,FV ), 0 , 147, 0 , 274, 149), // #901 + INST(Vcvttps2uqq , VexRm_Lx , E(660F00,78,_,x,_,0,3,HV ), 0 , 146, 0 , 273, 152), // #902 + INST(Vcvttsd2si , VexRm_Wx , V(F20F00,2C,_,I,x,x,3,T1F), 0 , 151, 0 , 275, 144), // #903 + INST(Vcvttsd2usi , VexRm_Wx , E(F20F00,78,_,I,_,x,3,T1F), 0 , 152, 0 , 276, 149), // #904 + INST(Vcvttsh2si , VexRm_Wx , E(F3MAP5,2C,_,_,_,x,1,T1S), 0 , 106, 0 , 277, 145), // #905 + INST(Vcvttsh2usi , VexRm_Wx , E(F3MAP5,78,_,_,_,x,1,T1S), 0 , 106, 0 , 277, 145), // #906 + INST(Vcvttss2si , VexRm_Wx , V(F30F00,2C,_,I,x,x,2,T1F), 0 , 107, 0 , 278, 144), // #907 + INST(Vcvttss2usi , VexRm_Wx , E(F30F00,78,_,I,_,x,2,T1F), 0 , 158, 0 , 279, 149), // #908 + INST(Vcvtudq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,0,3,HV ), 0 , 161, 0 , 255, 149), // #909 + INST(Vcvtudq2ph , VexRm_Lx_Narrow , E(F2MAP5,7A,_,_,_,0,4,FV ), 0 , 162, 0 , 239, 145), // #910 + INST(Vcvtudq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,0,4,FV ), 0 , 163, 0 , 256, 149), // #911 + INST(Vcvtuqq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,1,4,FV ), 0 , 148, 0 , 245, 152), // #912 + INST(Vcvtuqq2ph , VexRm_Lx , E(F2MAP5,7A,_,_,_,1,4,FV ), 0 , 164, 0 , 244, 145), // #913 + INST(Vcvtuqq2ps , VexRm_Lx_Narrow , E(F20F00,7A,_,x,_,1,4,FV ), 0 , 165, 0 , 246, 152), // #914 + INST(Vcvtusi2sd , VexRvm_Wx , E(F20F00,7B,_,I,_,x,2,T1W), 0 , 166, 0 , 280, 149), // #915 + INST(Vcvtusi2sh , VexRvm_Wx , E(F3MAP5,7B,_,_,_,x,2,T1W), 0 , 155, 0 , 263, 145), // #916 + INST(Vcvtusi2ss , VexRvm_Wx , E(F30F00,7B,_,I,_,x,2,T1W), 0 , 167, 0 , 280, 149), // #917 + INST(Vcvtuw2ph , VexRm_Lx , E(F2MAP5,7D,_,_,_,0,4,FV ), 0 , 162, 0 , 252, 145), // #918 + INST(Vcvtw2ph , VexRm_Lx , E(F3MAP5,7D,_,_,_,0,4,FV ), 0 , 168, 0 , 252, 145), // #919 + INST(Vdbpsadbw , VexRvmi_Lx , E(660F3A,42,_,x,_,0,4,FVM), 0 , 110, 0 , 281, 160), // #920 + INST(Vdivpd , VexRvm_Lx , V(660F00,5E,_,x,I,1,4,FV ), 0 , 102, 0 , 200, 144), // #921 + INST(Vdivph , VexRvm_Lx , E(00MAP5,5E,_,_,_,0,4,FV ), 0 , 103, 0 , 201, 145), // #922 + INST(Vdivps , VexRvm_Lx , V(000F00,5E,_,x,I,0,4,FV ), 0 , 104, 0 , 202, 144), // #923 + INST(Vdivsd , VexRvm , V(F20F00,5E,_,I,I,1,3,T1S), 0 , 105, 0 , 203, 144), // #924 + INST(Vdivsh , VexRvm , E(F3MAP5,5E,_,_,_,0,1,T1S), 0 , 106, 0 , 204, 145), // #925 + INST(Vdivss , VexRvm , V(F30F00,5E,_,I,I,0,2,T1S), 0 , 107, 0 , 205, 144), // #926 + INST(Vdpbf16ps , VexRvm_Lx , E(F30F38,52,_,_,_,0,4,FV ), 0 , 169, 0 , 218, 157), // #927 + INST(Vdppd , VexRvmi_Lx , V(660F3A,41,_,x,I,_,_,_ ), 0 , 75 , 0 , 282, 146), // #928 + INST(Vdpps , VexRvmi_Lx , V(660F3A,40,_,x,I,_,_,_ ), 0 , 75 , 0 , 219, 146), // #929 + INST(Verr , X86M_NoSize , O(000F00,00,4,_,_,_,_,_ ), 0 , 98 , 0 , 112, 11 ), // #930 + INST(Verw , X86M_NoSize , O(000F00,00,5,_,_,_,_,_ ), 0 , 79 , 0 , 112, 11 ), // #931 + INST(Vexpandpd , VexRm_Lx , E(660F38,88,_,x,_,1,3,T1S), 0 , 127, 0 , 283, 149), // #932 + INST(Vexpandps , VexRm_Lx , E(660F38,88,_,x,_,0,2,T1S), 0 , 128, 0 , 283, 149), // #933 + INST(Vextractf128 , VexMri , V(660F3A,19,_,1,0,_,_,_ ), 0 , 170, 0 , 284, 146), // #934 + INST(Vextractf32x4 , VexMri_Lx , E(660F3A,19,_,x,_,0,4,T4 ), 0 , 171, 0 , 285, 149), // #935 + INST(Vextractf32x8 , VexMri , E(660F3A,1B,_,2,_,0,5,T8 ), 0 , 172, 0 , 286, 152), // #936 + INST(Vextractf64x2 , VexMri_Lx , E(660F3A,19,_,x,_,1,4,T2 ), 0 , 173, 0 , 285, 152), // #937 + INST(Vextractf64x4 , VexMri , E(660F3A,1B,_,2,_,1,5,T4 ), 0 , 174, 0 , 286, 149), // #938 + INST(Vextracti128 , VexMri , V(660F3A,39,_,1,0,_,_,_ ), 0 , 170, 0 , 284, 153), // #939 + INST(Vextracti32x4 , VexMri_Lx , E(660F3A,39,_,x,_,0,4,T4 ), 0 , 171, 0 , 285, 149), // #940 + INST(Vextracti32x8 , VexMri , E(660F3A,3B,_,2,_,0,5,T8 ), 0 , 172, 0 , 286, 152), // #941 + INST(Vextracti64x2 , VexMri_Lx , E(660F3A,39,_,x,_,1,4,T2 ), 0 , 173, 0 , 285, 152), // #942 + INST(Vextracti64x4 , VexMri , E(660F3A,3B,_,2,_,1,5,T4 ), 0 , 174, 0 , 286, 149), // #943 + INST(Vextractps , VexMri , V(660F3A,17,_,0,I,I,2,T1S), 0 , 175, 0 , 287, 144), // #944 + INST(Vfcmaddcph , VexRvm_Lx , E(F2MAP6,56,_,_,_,0,4,FV ), 0 , 176, 0 , 288, 145), // #945 + INST(Vfcmaddcsh , VexRvm , E(F2MAP6,57,_,_,_,0,2,T1S), 0 , 177, 0 , 265, 145), // #946 + INST(Vfcmulcph , VexRvm_Lx , E(F2MAP6,D6,_,_,_,0,4,FV ), 0 , 176, 0 , 288, 145), // #947 + INST(Vfcmulcsh , VexRvm , E(F2MAP6,D7,_,_,_,0,2,T1S), 0 , 177, 0 , 265, 145), // #948 + INST(Vfixupimmpd , VexRvmi_Lx , E(660F3A,54,_,x,_,1,4,FV ), 0 , 111, 0 , 289, 149), // #949 + INST(Vfixupimmps , VexRvmi_Lx , E(660F3A,54,_,x,_,0,4,FV ), 0 , 110, 0 , 290, 149), // #950 + INST(Vfixupimmsd , VexRvmi , E(660F3A,55,_,I,_,1,3,T1S), 0 , 178, 0 , 291, 149), // #951 + INST(Vfixupimmss , VexRvmi , E(660F3A,55,_,I,_,0,2,T1S), 0 , 179, 0 , 292, 149), // #952 + INST(Vfmadd132pd , VexRvm_Lx , V(660F38,98,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #953 + INST(Vfmadd132ph , VexRvm_Lx , E(66MAP6,98,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #954 + INST(Vfmadd132ps , VexRvm_Lx , V(660F38,98,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #955 + INST(Vfmadd132sd , VexRvm , V(660F38,99,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #956 + INST(Vfmadd132sh , VexRvm , E(66MAP6,99,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #957 + INST(Vfmadd132ss , VexRvm , V(660F38,99,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #958 + INST(Vfmadd213pd , VexRvm_Lx , V(660F38,A8,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #959 + INST(Vfmadd213ph , VexRvm_Lx , E(66MAP6,A8,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #960 + INST(Vfmadd213ps , VexRvm_Lx , V(660F38,A8,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #961 + INST(Vfmadd213sd , VexRvm , V(660F38,A9,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #962 + INST(Vfmadd213sh , VexRvm , E(66MAP6,A9,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #963 + INST(Vfmadd213ss , VexRvm , V(660F38,A9,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #964 + INST(Vfmadd231pd , VexRvm_Lx , V(660F38,B8,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #965 + INST(Vfmadd231ph , VexRvm_Lx , E(66MAP6,B8,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #966 + INST(Vfmadd231ps , VexRvm_Lx , V(660F38,B8,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #967 + INST(Vfmadd231sd , VexRvm , V(660F38,B9,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #968 + INST(Vfmadd231sh , VexRvm , E(66MAP6,B9,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #969 + INST(Vfmadd231ss , VexRvm , V(660F38,B9,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #970 + INST(Vfmaddcph , VexRvm_Lx , E(F3MAP6,56,_,_,_,0,4,FV ), 0 , 184, 0 , 288, 145), // #971 + INST(Vfmaddcsh , VexRvm , E(F3MAP6,57,_,_,_,0,2,T1S), 0 , 185, 0 , 265, 145), // #972 + INST(Vfmaddpd , Fma4_Lx , V(660F3A,69,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #973 + INST(Vfmaddps , Fma4_Lx , V(660F3A,68,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #974 + INST(Vfmaddsd , Fma4 , V(660F3A,6B,_,0,x,_,_,_ ), 0 , 75 , 0 , 294, 162), // #975 + INST(Vfmaddss , Fma4 , V(660F3A,6A,_,0,x,_,_,_ ), 0 , 75 , 0 , 295, 162), // #976 + INST(Vfmaddsub132pd , VexRvm_Lx , V(660F38,96,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #977 + INST(Vfmaddsub132ph , VexRvm_Lx , E(66MAP6,96,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #978 + INST(Vfmaddsub132ps , VexRvm_Lx , V(660F38,96,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #979 + INST(Vfmaddsub213pd , VexRvm_Lx , V(660F38,A6,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #980 + INST(Vfmaddsub213ph , VexRvm_Lx , E(66MAP6,A6,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #981 + INST(Vfmaddsub213ps , VexRvm_Lx , V(660F38,A6,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #982 + INST(Vfmaddsub231pd , VexRvm_Lx , V(660F38,B6,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #983 + INST(Vfmaddsub231ph , VexRvm_Lx , E(66MAP6,B6,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #984 + INST(Vfmaddsub231ps , VexRvm_Lx , V(660F38,B6,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #985 + INST(Vfmaddsubpd , Fma4_Lx , V(660F3A,5D,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #986 + INST(Vfmaddsubps , Fma4_Lx , V(660F3A,5C,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #987 + INST(Vfmsub132pd , VexRvm_Lx , V(660F38,9A,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #988 + INST(Vfmsub132ph , VexRvm_Lx , E(66MAP6,9A,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #989 + INST(Vfmsub132ps , VexRvm_Lx , V(660F38,9A,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #990 + INST(Vfmsub132sd , VexRvm , V(660F38,9B,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #991 + INST(Vfmsub132sh , VexRvm , E(66MAP6,9B,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #992 + INST(Vfmsub132ss , VexRvm , V(660F38,9B,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #993 + INST(Vfmsub213pd , VexRvm_Lx , V(660F38,AA,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #994 + INST(Vfmsub213ph , VexRvm_Lx , E(66MAP6,AA,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #995 + INST(Vfmsub213ps , VexRvm_Lx , V(660F38,AA,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #996 + INST(Vfmsub213sd , VexRvm , V(660F38,AB,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #997 + INST(Vfmsub213sh , VexRvm , E(66MAP6,AB,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #998 + INST(Vfmsub213ss , VexRvm , V(660F38,AB,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #999 + INST(Vfmsub231pd , VexRvm_Lx , V(660F38,BA,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #1000 + INST(Vfmsub231ph , VexRvm_Lx , E(66MAP6,BA,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #1001 + INST(Vfmsub231ps , VexRvm_Lx , V(660F38,BA,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #1002 + INST(Vfmsub231sd , VexRvm , V(660F38,BB,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #1003 + INST(Vfmsub231sh , VexRvm , E(66MAP6,BB,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #1004 + INST(Vfmsub231ss , VexRvm , V(660F38,BB,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #1005 + INST(Vfmsubadd132pd , VexRvm_Lx , V(660F38,97,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #1006 + INST(Vfmsubadd132ph , VexRvm_Lx , E(66MAP6,97,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #1007 + INST(Vfmsubadd132ps , VexRvm_Lx , V(660F38,97,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #1008 + INST(Vfmsubadd213pd , VexRvm_Lx , V(660F38,A7,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #1009 + INST(Vfmsubadd213ph , VexRvm_Lx , E(66MAP6,A7,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #1010 + INST(Vfmsubadd213ps , VexRvm_Lx , V(660F38,A7,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #1011 + INST(Vfmsubadd231pd , VexRvm_Lx , V(660F38,B7,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #1012 + INST(Vfmsubadd231ph , VexRvm_Lx , E(66MAP6,B7,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #1013 + INST(Vfmsubadd231ps , VexRvm_Lx , V(660F38,B7,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #1014 + INST(Vfmsubaddpd , Fma4_Lx , V(660F3A,5F,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #1015 + INST(Vfmsubaddps , Fma4_Lx , V(660F3A,5E,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #1016 + INST(Vfmsubpd , Fma4_Lx , V(660F3A,6D,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #1017 + INST(Vfmsubps , Fma4_Lx , V(660F3A,6C,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #1018 + INST(Vfmsubsd , Fma4 , V(660F3A,6F,_,0,x,_,_,_ ), 0 , 75 , 0 , 294, 162), // #1019 + INST(Vfmsubss , Fma4 , V(660F3A,6E,_,0,x,_,_,_ ), 0 , 75 , 0 , 295, 162), // #1020 + INST(Vfmulcph , VexRvm_Lx , E(F3MAP6,D6,_,_,_,0,4,FV ), 0 , 184, 0 , 288, 145), // #1021 + INST(Vfmulcsh , VexRvm , E(F3MAP6,D7,_,_,_,0,2,T1S), 0 , 185, 0 , 265, 145), // #1022 + INST(Vfnmadd132pd , VexRvm_Lx , V(660F38,9C,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #1023 + INST(Vfnmadd132ph , VexRvm_Lx , E(66MAP6,9C,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #1024 + INST(Vfnmadd132ps , VexRvm_Lx , V(660F38,9C,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #1025 + INST(Vfnmadd132sd , VexRvm , V(660F38,9D,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #1026 + INST(Vfnmadd132sh , VexRvm , E(66MAP6,9D,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #1027 + INST(Vfnmadd132ss , VexRvm , V(660F38,9D,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #1028 + INST(Vfnmadd213pd , VexRvm_Lx , V(660F38,AC,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #1029 + INST(Vfnmadd213ph , VexRvm_Lx , E(66MAP6,AC,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #1030 + INST(Vfnmadd213ps , VexRvm_Lx , V(660F38,AC,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #1031 + INST(Vfnmadd213sd , VexRvm , V(660F38,AD,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #1032 + INST(Vfnmadd213sh , VexRvm , E(66MAP6,AD,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #1033 + INST(Vfnmadd213ss , VexRvm , V(660F38,AD,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #1034 + INST(Vfnmadd231pd , VexRvm_Lx , V(660F38,BC,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #1035 + INST(Vfnmadd231ph , VexRvm_Lx , E(66MAP6,BC,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #1036 + INST(Vfnmadd231ps , VexRvm_Lx , V(660F38,BC,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #1037 + INST(Vfnmadd231sd , VexRvm , V(660F38,BD,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #1038 + INST(Vfnmadd231sh , VexRvm , E(66MAP6,BD,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #1039 + INST(Vfnmadd231ss , VexRvm , V(660F38,BD,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #1040 + INST(Vfnmaddpd , Fma4_Lx , V(660F3A,79,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #1041 + INST(Vfnmaddps , Fma4_Lx , V(660F3A,78,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #1042 + INST(Vfnmaddsd , Fma4 , V(660F3A,7B,_,0,x,_,_,_ ), 0 , 75 , 0 , 294, 162), // #1043 + INST(Vfnmaddss , Fma4 , V(660F3A,7A,_,0,x,_,_,_ ), 0 , 75 , 0 , 295, 162), // #1044 + INST(Vfnmsub132pd , VexRvm_Lx , V(660F38,9E,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #1045 + INST(Vfnmsub132ph , VexRvm_Lx , E(66MAP6,9E,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #1046 + INST(Vfnmsub132ps , VexRvm_Lx , V(660F38,9E,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #1047 + INST(Vfnmsub132sd , VexRvm , V(660F38,9F,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #1048 + INST(Vfnmsub132sh , VexRvm , E(66MAP6,9F,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #1049 + INST(Vfnmsub132ss , VexRvm , V(660F38,9F,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #1050 + INST(Vfnmsub213pd , VexRvm_Lx , V(660F38,AE,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #1051 + INST(Vfnmsub213ph , VexRvm_Lx , E(66MAP6,AE,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #1052 + INST(Vfnmsub213ps , VexRvm_Lx , V(660F38,AE,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #1053 + INST(Vfnmsub213sd , VexRvm , V(660F38,AF,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #1054 + INST(Vfnmsub213sh , VexRvm , E(66MAP6,AF,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #1055 + INST(Vfnmsub213ss , VexRvm , V(660F38,AF,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #1056 + INST(Vfnmsub231pd , VexRvm_Lx , V(660F38,BE,_,x,1,1,4,FV ), 0 , 180, 0 , 200, 161), // #1057 + INST(Vfnmsub231ph , VexRvm_Lx , E(66MAP6,BE,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #1058 + INST(Vfnmsub231ps , VexRvm_Lx , V(660F38,BE,_,x,0,0,4,FV ), 0 , 109, 0 , 202, 161), // #1059 + INST(Vfnmsub231sd , VexRvm , V(660F38,BF,_,I,1,1,3,T1S), 0 , 182, 0 , 203, 161), // #1060 + INST(Vfnmsub231sh , VexRvm , E(66MAP6,BF,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #1061 + INST(Vfnmsub231ss , VexRvm , V(660F38,BF,_,I,0,0,2,T1S), 0 , 121, 0 , 205, 161), // #1062 + INST(Vfnmsubpd , Fma4_Lx , V(660F3A,7D,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #1063 + INST(Vfnmsubps , Fma4_Lx , V(660F3A,7C,_,x,x,_,_,_ ), 0 , 75 , 0 , 293, 162), // #1064 + INST(Vfnmsubsd , Fma4 , V(660F3A,7F,_,0,x,_,_,_ ), 0 , 75 , 0 , 294, 162), // #1065 + INST(Vfnmsubss , Fma4 , V(660F3A,7E,_,0,x,_,_,_ ), 0 , 75 , 0 , 295, 162), // #1066 + INST(Vfpclasspd , VexRmi_Lx , E(660F3A,66,_,x,_,1,4,FV ), 0 , 111, 0 , 296, 152), // #1067 + INST(Vfpclassph , VexRmi_Lx , E(000F3A,66,_,_,_,0,4,FV ), 0 , 122, 0 , 297, 145), // #1068 + INST(Vfpclassps , VexRmi_Lx , E(660F3A,66,_,x,_,0,4,FV ), 0 , 110, 0 , 298, 152), // #1069 + INST(Vfpclasssd , VexRmi , E(660F3A,67,_,I,_,1,3,T1S), 0 , 178, 0 , 299, 152), // #1070 + INST(Vfpclasssh , VexRmi , E(000F3A,67,_,_,_,0,1,T1S), 0 , 186, 0 , 300, 145), // #1071 + INST(Vfpclassss , VexRmi , E(660F3A,67,_,I,_,0,2,T1S), 0 , 179, 0 , 301, 152), // #1072 + INST(Vfrczpd , VexRm_Lx , V(XOP_M9,81,_,x,0,_,_,_ ), 0 , 81 , 0 , 302, 163), // #1073 + INST(Vfrczps , VexRm_Lx , V(XOP_M9,80,_,x,0,_,_,_ ), 0 , 81 , 0 , 302, 163), // #1074 + INST(Vfrczsd , VexRm , V(XOP_M9,83,_,0,0,_,_,_ ), 0 , 81 , 0 , 303, 163), // #1075 + INST(Vfrczss , VexRm , V(XOP_M9,82,_,0,0,_,_,_ ), 0 , 81 , 0 , 304, 163), // #1076 + INST(Vgatherdpd , VexRmvRm_VM , V(660F38,92,_,x,1,_,_,_ ), E(660F38,92,_,x,_,1,3,T1S), 187, 80 , 305, 164), // #1077 + INST(Vgatherdps , VexRmvRm_VM , V(660F38,92,_,x,0,_,_,_ ), E(660F38,92,_,x,_,0,2,T1S), 30 , 81 , 306, 164), // #1078 + INST(Vgatherqpd , VexRmvRm_VM , V(660F38,93,_,x,1,_,_,_ ), E(660F38,93,_,x,_,1,3,T1S), 187, 82 , 307, 164), // #1079 + INST(Vgatherqps , VexRmvRm_VM , V(660F38,93,_,x,0,_,_,_ ), E(660F38,93,_,x,_,0,2,T1S), 30 , 83 , 308, 164), // #1080 + INST(Vgetexppd , VexRm_Lx , E(660F38,42,_,x,_,1,4,FV ), 0 , 112, 0 , 269, 149), // #1081 + INST(Vgetexpph , VexRm_Lx , E(66MAP6,42,_,_,_,0,4,FV ), 0 , 181, 0 , 271, 145), // #1082 + INST(Vgetexpps , VexRm_Lx , E(660F38,42,_,x,_,0,4,FV ), 0 , 113, 0 , 274, 149), // #1083 + INST(Vgetexpsd , VexRvm , E(660F38,43,_,I,_,1,3,T1S), 0 , 127, 0 , 309, 149), // #1084 + INST(Vgetexpsh , VexRvm , E(66MAP6,43,_,_,_,0,1,T1S), 0 , 183, 0 , 260, 145), // #1085 + INST(Vgetexpss , VexRvm , E(660F38,43,_,I,_,0,2,T1S), 0 , 128, 0 , 310, 149), // #1086 + INST(Vgetmantpd , VexRmi_Lx , E(660F3A,26,_,x,_,1,4,FV ), 0 , 111, 0 , 311, 149), // #1087 + INST(Vgetmantph , VexRmi_Lx , E(000F3A,26,_,_,_,0,4,FV ), 0 , 122, 0 , 312, 145), // #1088 + INST(Vgetmantps , VexRmi_Lx , E(660F3A,26,_,x,_,0,4,FV ), 0 , 110, 0 , 313, 149), // #1089 + INST(Vgetmantsd , VexRvmi , E(660F3A,27,_,I,_,1,3,T1S), 0 , 178, 0 , 291, 149), // #1090 + INST(Vgetmantsh , VexRvmi , E(000F3A,27,_,_,_,0,1,T1S), 0 , 186, 0 , 314, 145), // #1091 + INST(Vgetmantss , VexRvmi , E(660F3A,27,_,I,_,0,2,T1S), 0 , 179, 0 , 292, 149), // #1092 + INST(Vgf2p8affineinvqb, VexRvmi_Lx , V(660F3A,CF,_,x,1,1,4,FV ), 0 , 188, 0 , 315, 165), // #1093 + INST(Vgf2p8affineqb , VexRvmi_Lx , V(660F3A,CE,_,x,1,1,4,FV ), 0 , 188, 0 , 315, 165), // #1094 + INST(Vgf2p8mulb , VexRvm_Lx , V(660F38,CF,_,x,0,0,4,FV ), 0 , 109, 0 , 316, 165), // #1095 + INST(Vhaddpd , VexRvm_Lx , V(660F00,7C,_,x,I,_,_,_ ), 0 , 71 , 0 , 206, 146), // #1096 + INST(Vhaddps , VexRvm_Lx , V(F20F00,7C,_,x,I,_,_,_ ), 0 , 108, 0 , 206, 146), // #1097 + INST(Vhsubpd , VexRvm_Lx , V(660F00,7D,_,x,I,_,_,_ ), 0 , 71 , 0 , 206, 146), // #1098 + INST(Vhsubps , VexRvm_Lx , V(F20F00,7D,_,x,I,_,_,_ ), 0 , 108, 0 , 206, 146), // #1099 + INST(Vinsertf128 , VexRvmi , V(660F3A,18,_,1,0,_,_,_ ), 0 , 170, 0 , 317, 146), // #1100 + INST(Vinsertf32x4 , VexRvmi_Lx , E(660F3A,18,_,x,_,0,4,T4 ), 0 , 171, 0 , 318, 149), // #1101 + INST(Vinsertf32x8 , VexRvmi , E(660F3A,1A,_,2,_,0,5,T8 ), 0 , 172, 0 , 319, 152), // #1102 + INST(Vinsertf64x2 , VexRvmi_Lx , E(660F3A,18,_,x,_,1,4,T2 ), 0 , 173, 0 , 318, 152), // #1103 + INST(Vinsertf64x4 , VexRvmi , E(660F3A,1A,_,2,_,1,5,T4 ), 0 , 174, 0 , 319, 149), // #1104 + INST(Vinserti128 , VexRvmi , V(660F3A,38,_,1,0,_,_,_ ), 0 , 170, 0 , 317, 153), // #1105 + INST(Vinserti32x4 , VexRvmi_Lx , E(660F3A,38,_,x,_,0,4,T4 ), 0 , 171, 0 , 318, 149), // #1106 + INST(Vinserti32x8 , VexRvmi , E(660F3A,3A,_,2,_,0,5,T8 ), 0 , 172, 0 , 319, 152), // #1107 + INST(Vinserti64x2 , VexRvmi_Lx , E(660F3A,38,_,x,_,1,4,T2 ), 0 , 173, 0 , 318, 152), // #1108 + INST(Vinserti64x4 , VexRvmi , E(660F3A,3A,_,2,_,1,5,T4 ), 0 , 174, 0 , 319, 149), // #1109 + INST(Vinsertps , VexRvmi , V(660F3A,21,_,0,I,0,2,T1S), 0 , 175, 0 , 320, 144), // #1110 + INST(Vlddqu , VexRm_Lx , V(F20F00,F0,_,x,I,_,_,_ ), 0 , 108, 0 , 241, 146), // #1111 + INST(Vldmxcsr , VexM , V(000F00,AE,2,0,I,_,_,_ ), 0 , 189, 0 , 321, 146), // #1112 + INST(Vmaskmovdqu , VexRm_ZDI , V(660F00,F7,_,0,I,_,_,_ ), 0 , 71 , 0 , 322, 146), // #1113 + INST(Vmaskmovpd , VexRvmMvr_Lx , V(660F38,2D,_,x,0,_,_,_ ), V(660F38,2F,_,x,0,_,_,_ ), 30 , 84 , 323, 146), // #1114 + INST(Vmaskmovps , VexRvmMvr_Lx , V(660F38,2C,_,x,0,_,_,_ ), V(660F38,2E,_,x,0,_,_,_ ), 30 , 85 , 323, 146), // #1115 + INST(Vmaxpd , VexRvm_Lx , V(660F00,5F,_,x,I,1,4,FV ), 0 , 102, 0 , 324, 144), // #1116 + INST(Vmaxph , VexRvm_Lx , E(00MAP5,5F,_,_,_,0,4,FV ), 0 , 103, 0 , 325, 145), // #1117 + INST(Vmaxps , VexRvm_Lx , V(000F00,5F,_,x,I,0,4,FV ), 0 , 104, 0 , 326, 144), // #1118 + INST(Vmaxsd , VexRvm , V(F20F00,5F,_,I,I,1,3,T1S), 0 , 105, 0 , 327, 144), // #1119 + INST(Vmaxsh , VexRvm , E(F3MAP5,5F,_,_,_,0,1,T1S), 0 , 106, 0 , 260, 145), // #1120 + INST(Vmaxss , VexRvm , V(F30F00,5F,_,I,I,0,2,T1S), 0 , 107, 0 , 264, 144), // #1121 + INST(Vmcall , X86Op , O(000F01,C1,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 67 ), // #1122 + INST(Vmclear , X86M_Only , O(660F00,C7,6,_,_,_,_,_ ), 0 , 28 , 0 , 33 , 67 ), // #1123 + INST(Vmfunc , X86Op , O(000F01,D4,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 67 ), // #1124 + INST(Vmgexit , X86Op , O(F20F01,D9,_,_,_,_,_,_ ), 0 , 93 , 0 , 31 , 166), // #1125 + INST(Vminpd , VexRvm_Lx , V(660F00,5D,_,x,I,1,4,FV ), 0 , 102, 0 , 324, 144), // #1126 + INST(Vminph , VexRvm_Lx , E(00MAP5,5D,_,_,_,0,4,FV ), 0 , 103, 0 , 325, 145), // #1127 + INST(Vminps , VexRvm_Lx , V(000F00,5D,_,x,I,0,4,FV ), 0 , 104, 0 , 326, 144), // #1128 + INST(Vminsd , VexRvm , V(F20F00,5D,_,I,I,1,3,T1S), 0 , 105, 0 , 327, 144), // #1129 + INST(Vminsh , VexRvm , E(F3MAP5,5D,_,_,_,0,1,T1S), 0 , 106, 0 , 260, 145), // #1130 + INST(Vminss , VexRvm , V(F30F00,5D,_,I,I,0,2,T1S), 0 , 107, 0 , 264, 144), // #1131 + INST(Vmlaunch , X86Op , O(000F01,C2,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 67 ), // #1132 + INST(Vmload , X86Op_xAX , O(000F01,DA,_,_,_,_,_,_ ), 0 , 23 , 0 , 328, 23 ), // #1133 + INST(Vmmcall , X86Op , O(000F01,D9,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 23 ), // #1134 + INST(Vmovapd , VexRmMr_Lx , V(660F00,28,_,x,I,1,4,FVM), V(660F00,29,_,x,I,1,4,FVM), 102, 86 , 329, 167), // #1135 + INST(Vmovaps , VexRmMr_Lx , V(000F00,28,_,x,I,0,4,FVM), V(000F00,29,_,x,I,0,4,FVM), 104, 87 , 329, 167), // #1136 + INST(Vmovd , VexMovdMovq , V(660F00,6E,_,0,0,0,2,T1S), V(660F00,7E,_,0,0,0,2,T1S), 190, 88 , 330, 144), // #1137 + INST(Vmovddup , VexRm_Lx , V(F20F00,12,_,x,I,1,3,DUP), 0 , 191, 0 , 331, 144), // #1138 + INST(Vmovdqa , VexRmMr_Lx , V(660F00,6F,_,x,I,_,_,_ ), V(660F00,7F,_,x,I,_,_,_ ), 71 , 89 , 332, 168), // #1139 + INST(Vmovdqa32 , VexRmMr_Lx , E(660F00,6F,_,x,_,0,4,FVM), E(660F00,7F,_,x,_,0,4,FVM), 192, 90 , 333, 169), // #1140 + INST(Vmovdqa64 , VexRmMr_Lx , E(660F00,6F,_,x,_,1,4,FVM), E(660F00,7F,_,x,_,1,4,FVM), 134, 91 , 333, 169), // #1141 + INST(Vmovdqu , VexRmMr_Lx , V(F30F00,6F,_,x,I,_,_,_ ), V(F30F00,7F,_,x,I,_,_,_ ), 193, 92 , 332, 168), // #1142 + INST(Vmovdqu16 , VexRmMr_Lx , E(F20F00,6F,_,x,_,1,4,FVM), E(F20F00,7F,_,x,_,1,4,FVM), 165, 93 , 333, 170), // #1143 + INST(Vmovdqu32 , VexRmMr_Lx , E(F30F00,6F,_,x,_,0,4,FVM), E(F30F00,7F,_,x,_,0,4,FVM), 194, 94 , 333, 169), // #1144 + INST(Vmovdqu64 , VexRmMr_Lx , E(F30F00,6F,_,x,_,1,4,FVM), E(F30F00,7F,_,x,_,1,4,FVM), 148, 95 , 333, 169), // #1145 + INST(Vmovdqu8 , VexRmMr_Lx , E(F20F00,6F,_,x,_,0,4,FVM), E(F20F00,7F,_,x,_,0,4,FVM), 163, 96 , 333, 170), // #1146 + INST(Vmovhlps , VexRvm , V(000F00,12,_,0,I,0,_,_ ), 0 , 74 , 0 , 334, 144), // #1147 + INST(Vmovhpd , VexRvmMr , V(660F00,16,_,0,I,1,3,T1S), V(660F00,17,_,0,I,1,3,T1S), 124, 97 , 335, 144), // #1148 + INST(Vmovhps , VexRvmMr , V(000F00,16,_,0,I,0,3,T2 ), V(000F00,17,_,0,I,0,3,T2 ), 195, 98 , 335, 144), // #1149 + INST(Vmovlhps , VexRvm , V(000F00,16,_,0,I,0,_,_ ), 0 , 74 , 0 , 334, 144), // #1150 + INST(Vmovlpd , VexRvmMr , V(660F00,12,_,0,I,1,3,T1S), V(660F00,13,_,0,I,1,3,T1S), 124, 99 , 335, 144), // #1151 + INST(Vmovlps , VexRvmMr , V(000F00,12,_,0,I,0,3,T2 ), V(000F00,13,_,0,I,0,3,T2 ), 195, 100, 335, 144), // #1152 + INST(Vmovmskpd , VexRm_Lx , V(660F00,50,_,x,I,_,_,_ ), 0 , 71 , 0 , 336, 146), // #1153 + INST(Vmovmskps , VexRm_Lx , V(000F00,50,_,x,I,_,_,_ ), 0 , 74 , 0 , 336, 146), // #1154 + INST(Vmovntdq , VexMr_Lx , V(660F00,E7,_,x,I,0,4,FVM), 0 , 143, 0 , 337, 144), // #1155 + INST(Vmovntdqa , VexRm_Lx , V(660F38,2A,_,x,I,0,4,FVM), 0 , 109, 0 , 338, 154), // #1156 + INST(Vmovntpd , VexMr_Lx , V(660F00,2B,_,x,I,1,4,FVM), 0 , 102, 0 , 337, 144), // #1157 + INST(Vmovntps , VexMr_Lx , V(000F00,2B,_,x,I,0,4,FVM), 0 , 104, 0 , 337, 144), // #1158 + INST(Vmovq , VexMovdMovq , V(660F00,6E,_,0,I,1,3,T1S), V(660F00,7E,_,0,I,1,3,T1S), 124, 101, 339, 167), // #1159 + INST(Vmovsd , VexMovssMovsd , V(F20F00,10,_,I,I,1,3,T1S), V(F20F00,11,_,I,I,1,3,T1S), 105, 102, 340, 167), // #1160 + INST(Vmovsh , VexMovssMovsd , E(F3MAP5,10,_,I,_,0,1,T1S), E(F3MAP5,11,_,I,_,0,1,T1S), 106, 103, 341, 145), // #1161 + INST(Vmovshdup , VexRm_Lx , V(F30F00,16,_,x,I,0,4,FVM), 0 , 160, 0 , 342, 144), // #1162 + INST(Vmovsldup , VexRm_Lx , V(F30F00,12,_,x,I,0,4,FVM), 0 , 160, 0 , 342, 144), // #1163 + INST(Vmovss , VexMovssMovsd , V(F30F00,10,_,I,I,0,2,T1S), V(F30F00,11,_,I,I,0,2,T1S), 107, 104, 343, 167), // #1164 + INST(Vmovupd , VexRmMr_Lx , V(660F00,10,_,x,I,1,4,FVM), V(660F00,11,_,x,I,1,4,FVM), 102, 105, 329, 167), // #1165 + INST(Vmovups , VexRmMr_Lx , V(000F00,10,_,x,I,0,4,FVM), V(000F00,11,_,x,I,0,4,FVM), 104, 106, 329, 167), // #1166 + INST(Vmovw , VexMovdMovq , E(66MAP5,6E,_,0,_,I,1,T1S), E(66MAP5,7E,_,0,_,I,1,T1S), 196, 107, 344, 145), // #1167 + INST(Vmpsadbw , VexRvmi_Lx , V(660F3A,42,_,x,I,_,_,_ ), 0 , 75 , 0 , 219, 171), // #1168 + INST(Vmptrld , X86M_Only , O(000F00,C7,6,_,_,_,_,_ ), 0 , 82 , 0 , 33 , 67 ), // #1169 + INST(Vmptrst , X86M_Only , O(000F00,C7,7,_,_,_,_,_ ), 0 , 24 , 0 , 33 , 67 ), // #1170 + INST(Vmread , X86Mr_NoSize , O(000F00,78,_,_,_,_,_,_ ), 0 , 5 , 0 , 345, 67 ), // #1171 + INST(Vmresume , X86Op , O(000F01,C3,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 67 ), // #1172 + INST(Vmrun , X86Op_xAX , O(000F01,D8,_,_,_,_,_,_ ), 0 , 23 , 0 , 328, 23 ), // #1173 + INST(Vmsave , X86Op_xAX , O(000F01,DB,_,_,_,_,_,_ ), 0 , 23 , 0 , 328, 23 ), // #1174 + INST(Vmulpd , VexRvm_Lx , V(660F00,59,_,x,I,1,4,FV ), 0 , 102, 0 , 200, 144), // #1175 + INST(Vmulph , VexRvm_Lx , E(00MAP5,59,_,_,_,0,4,FV ), 0 , 103, 0 , 201, 145), // #1176 + INST(Vmulps , VexRvm_Lx , V(000F00,59,_,x,I,0,4,FV ), 0 , 104, 0 , 202, 144), // #1177 + INST(Vmulsd , VexRvm , V(F20F00,59,_,I,I,1,3,T1S), 0 , 105, 0 , 203, 144), // #1178 + INST(Vmulsh , VexRvm , E(F3MAP5,59,_,_,_,0,1,T1S), 0 , 106, 0 , 204, 145), // #1179 + INST(Vmulss , VexRvm , V(F30F00,59,_,I,I,0,2,T1S), 0 , 107, 0 , 205, 144), // #1180 + INST(Vmwrite , X86Rm_NoSize , O(000F00,79,_,_,_,_,_,_ ), 0 , 5 , 0 , 346, 67 ), // #1181 + INST(Vmxoff , X86Op , O(000F01,C4,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 67 ), // #1182 + INST(Vmxon , X86M_Only , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 26 , 0 , 33 , 67 ), // #1183 + INST(Vorpd , VexRvm_Lx , V(660F00,56,_,x,I,1,4,FV ), 0 , 102, 0 , 214, 150), // #1184 + INST(Vorps , VexRvm_Lx , V(000F00,56,_,x,I,0,4,FV ), 0 , 104, 0 , 215, 150), // #1185 + INST(Vp2intersectd , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,0,4,FV ), 0 , 130, 0 , 347, 172), // #1186 + INST(Vp2intersectq , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,1,4,FV ), 0 , 197, 0 , 348, 172), // #1187 + INST(Vpabsb , VexRm_Lx , V(660F38,1C,_,x,I,_,4,FVM), 0 , 109, 0 , 342, 173), // #1188 + INST(Vpabsd , VexRm_Lx , V(660F38,1E,_,x,I,0,4,FV ), 0 , 109, 0 , 349, 154), // #1189 + INST(Vpabsq , VexRm_Lx , E(660F38,1F,_,x,_,1,4,FV ), 0 , 112, 0 , 350, 149), // #1190 + INST(Vpabsw , VexRm_Lx , V(660F38,1D,_,x,I,_,4,FVM), 0 , 109, 0 , 342, 173), // #1191 + INST(Vpackssdw , VexRvm_Lx , V(660F00,6B,_,x,I,0,4,FV ), 0 , 143, 0 , 213, 173), // #1192 + INST(Vpacksswb , VexRvm_Lx , V(660F00,63,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1193 + INST(Vpackusdw , VexRvm_Lx , V(660F38,2B,_,x,I,0,4,FV ), 0 , 109, 0 , 213, 173), // #1194 + INST(Vpackuswb , VexRvm_Lx , V(660F00,67,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1195 + INST(Vpaddb , VexRvm_Lx , V(660F00,FC,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1196 + INST(Vpaddd , VexRvm_Lx , V(660F00,FE,_,x,I,0,4,FV ), 0 , 143, 0 , 213, 154), // #1197 + INST(Vpaddq , VexRvm_Lx , V(660F00,D4,_,x,I,1,4,FV ), 0 , 102, 0 , 212, 154), // #1198 + INST(Vpaddsb , VexRvm_Lx , V(660F00,EC,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1199 + INST(Vpaddsw , VexRvm_Lx , V(660F00,ED,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1200 + INST(Vpaddusb , VexRvm_Lx , V(660F00,DC,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1201 + INST(Vpaddusw , VexRvm_Lx , V(660F00,DD,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1202 + INST(Vpaddw , VexRvm_Lx , V(660F00,FD,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1203 + INST(Vpalignr , VexRvmi_Lx , V(660F3A,0F,_,x,I,I,4,FVM), 0 , 198, 0 , 315, 173), // #1204 + INST(Vpand , VexRvm_Lx , V(660F00,DB,_,x,I,_,_,_ ), 0 , 71 , 0 , 351, 171), // #1205 + INST(Vpandd , VexRvm_Lx , E(660F00,DB,_,x,_,0,4,FV ), 0 , 192, 0 , 352, 149), // #1206 + INST(Vpandn , VexRvm_Lx , V(660F00,DF,_,x,I,_,_,_ ), 0 , 71 , 0 , 353, 171), // #1207 + INST(Vpandnd , VexRvm_Lx , E(660F00,DF,_,x,_,0,4,FV ), 0 , 192, 0 , 354, 149), // #1208 + INST(Vpandnq , VexRvm_Lx , E(660F00,DF,_,x,_,1,4,FV ), 0 , 134, 0 , 355, 149), // #1209 + INST(Vpandq , VexRvm_Lx , E(660F00,DB,_,x,_,1,4,FV ), 0 , 134, 0 , 356, 149), // #1210 + INST(Vpavgb , VexRvm_Lx , V(660F00,E0,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1211 + INST(Vpavgw , VexRvm_Lx , V(660F00,E3,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1212 + INST(Vpblendd , VexRvmi_Lx , V(660F3A,02,_,x,0,_,_,_ ), 0 , 75 , 0 , 219, 153), // #1213 + INST(Vpblendmb , VexRvm_Lx , E(660F38,66,_,x,_,0,4,FVM), 0 , 113, 0 , 357, 160), // #1214 + INST(Vpblendmd , VexRvm_Lx , E(660F38,64,_,x,_,0,4,FV ), 0 , 113, 0 , 218, 149), // #1215 + INST(Vpblendmq , VexRvm_Lx , E(660F38,64,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1216 + INST(Vpblendmw , VexRvm_Lx , E(660F38,66,_,x,_,1,4,FVM), 0 , 112, 0 , 357, 160), // #1217 + INST(Vpblendvb , VexRvmr_Lx , V(660F3A,4C,_,x,0,_,_,_ ), 0 , 75 , 0 , 220, 171), // #1218 + INST(Vpblendw , VexRvmi_Lx , V(660F3A,0E,_,x,I,_,_,_ ), 0 , 75 , 0 , 219, 171), // #1219 + INST(Vpbroadcastb , VexRm_Lx_Bcst , V(660F38,78,_,x,0,0,0,T1S), E(660F38,7A,_,x,0,0,0,T1S), 30 , 108, 358, 174), // #1220 + INST(Vpbroadcastd , VexRm_Lx_Bcst , V(660F38,58,_,x,0,0,2,T1S), E(660F38,7C,_,x,0,0,0,T1S), 121, 109, 359, 164), // #1221 + INST(Vpbroadcastmb2q , VexRm_Lx , E(F30F38,2A,_,x,_,1,_,_ ), 0 , 199, 0 , 360, 175), // #1222 + INST(Vpbroadcastmw2d , VexRm_Lx , E(F30F38,3A,_,x,_,0,_,_ ), 0 , 200, 0 , 360, 175), // #1223 + INST(Vpbroadcastq , VexRm_Lx_Bcst , V(660F38,59,_,x,0,1,3,T1S), E(660F38,7C,_,x,0,1,0,T1S), 120, 110, 361, 164), // #1224 + INST(Vpbroadcastw , VexRm_Lx_Bcst , V(660F38,79,_,x,0,0,1,T1S), E(660F38,7B,_,x,0,0,0,T1S), 201, 111, 362, 174), // #1225 + INST(Vpclmulqdq , VexRvmi_Lx , V(660F3A,44,_,x,I,_,4,FVM), 0 , 198, 0 , 363, 176), // #1226 + INST(Vpcmov , VexRvrmRvmr_Lx , V(XOP_M8,A2,_,x,x,_,_,_ ), 0 , 202, 0 , 364, 163), // #1227 + INST(Vpcmpb , VexRvmi_Lx , E(660F3A,3F,_,x,_,0,4,FVM), 0 , 110, 0 , 365, 160), // #1228 + INST(Vpcmpd , VexRvmi_Lx , E(660F3A,1F,_,x,_,0,4,FV ), 0 , 110, 0 , 366, 149), // #1229 + INST(Vpcmpeqb , VexRvm_Lx_KEvex , V(660F00,74,_,x,I,I,4,FV ), 0 , 143, 0 , 367, 173), // #1230 + INST(Vpcmpeqd , VexRvm_Lx_KEvex , V(660F00,76,_,x,I,0,4,FVM), 0 , 143, 0 , 368, 154), // #1231 + INST(Vpcmpeqq , VexRvm_Lx_KEvex , V(660F38,29,_,x,I,1,4,FVM), 0 , 203, 0 , 369, 154), // #1232 + INST(Vpcmpeqw , VexRvm_Lx_KEvex , V(660F00,75,_,x,I,I,4,FV ), 0 , 143, 0 , 367, 173), // #1233 + INST(Vpcmpestri , VexRmi , V(660F3A,61,_,0,I,_,_,_ ), 0 , 75 , 0 , 370, 177), // #1234 + INST(Vpcmpestrm , VexRmi , V(660F3A,60,_,0,I,_,_,_ ), 0 , 75 , 0 , 371, 177), // #1235 + INST(Vpcmpgtb , VexRvm_Lx_KEvex , V(660F00,64,_,x,I,I,4,FV ), 0 , 143, 0 , 367, 173), // #1236 + INST(Vpcmpgtd , VexRvm_Lx_KEvex , V(660F00,66,_,x,I,0,4,FVM), 0 , 143, 0 , 368, 154), // #1237 + INST(Vpcmpgtq , VexRvm_Lx_KEvex , V(660F38,37,_,x,I,1,4,FVM), 0 , 203, 0 , 369, 154), // #1238 + INST(Vpcmpgtw , VexRvm_Lx_KEvex , V(660F00,65,_,x,I,I,4,FV ), 0 , 143, 0 , 367, 173), // #1239 + INST(Vpcmpistri , VexRmi , V(660F3A,63,_,0,I,_,_,_ ), 0 , 75 , 0 , 372, 177), // #1240 + INST(Vpcmpistrm , VexRmi , V(660F3A,62,_,0,I,_,_,_ ), 0 , 75 , 0 , 373, 177), // #1241 + INST(Vpcmpq , VexRvmi_Lx , E(660F3A,1F,_,x,_,1,4,FV ), 0 , 111, 0 , 374, 149), // #1242 + INST(Vpcmpub , VexRvmi_Lx , E(660F3A,3E,_,x,_,0,4,FVM), 0 , 110, 0 , 365, 160), // #1243 + INST(Vpcmpud , VexRvmi_Lx , E(660F3A,1E,_,x,_,0,4,FV ), 0 , 110, 0 , 366, 149), // #1244 + INST(Vpcmpuq , VexRvmi_Lx , E(660F3A,1E,_,x,_,1,4,FV ), 0 , 111, 0 , 374, 149), // #1245 + INST(Vpcmpuw , VexRvmi_Lx , E(660F3A,3E,_,x,_,1,4,FVM), 0 , 111, 0 , 365, 160), // #1246 + INST(Vpcmpw , VexRvmi_Lx , E(660F3A,3F,_,x,_,1,4,FVM), 0 , 111, 0 , 365, 160), // #1247 + INST(Vpcomb , VexRvmi , V(XOP_M8,CC,_,0,0,_,_,_ ), 0 , 202, 0 , 282, 163), // #1248 + INST(Vpcomd , VexRvmi , V(XOP_M8,CE,_,0,0,_,_,_ ), 0 , 202, 0 , 282, 163), // #1249 + INST(Vpcompressb , VexMr_Lx , E(660F38,63,_,x,_,0,0,T1S), 0 , 204, 0 , 237, 178), // #1250 + INST(Vpcompressd , VexMr_Lx , E(660F38,8B,_,x,_,0,2,T1S), 0 , 128, 0 , 237, 149), // #1251 + INST(Vpcompressq , VexMr_Lx , E(660F38,8B,_,x,_,1,3,T1S), 0 , 127, 0 , 237, 149), // #1252 + INST(Vpcompressw , VexMr_Lx , E(660F38,63,_,x,_,1,1,T1S), 0 , 205, 0 , 237, 178), // #1253 + INST(Vpcomq , VexRvmi , V(XOP_M8,CF,_,0,0,_,_,_ ), 0 , 202, 0 , 282, 163), // #1254 + INST(Vpcomub , VexRvmi , V(XOP_M8,EC,_,0,0,_,_,_ ), 0 , 202, 0 , 282, 163), // #1255 + INST(Vpcomud , VexRvmi , V(XOP_M8,EE,_,0,0,_,_,_ ), 0 , 202, 0 , 282, 163), // #1256 + INST(Vpcomuq , VexRvmi , V(XOP_M8,EF,_,0,0,_,_,_ ), 0 , 202, 0 , 282, 163), // #1257 + INST(Vpcomuw , VexRvmi , V(XOP_M8,ED,_,0,0,_,_,_ ), 0 , 202, 0 , 282, 163), // #1258 + INST(Vpcomw , VexRvmi , V(XOP_M8,CD,_,0,0,_,_,_ ), 0 , 202, 0 , 282, 163), // #1259 + INST(Vpconflictd , VexRm_Lx , E(660F38,C4,_,x,_,0,4,FV ), 0 , 113, 0 , 375, 175), // #1260 + INST(Vpconflictq , VexRm_Lx , E(660F38,C4,_,x,_,1,4,FV ), 0 , 112, 0 , 375, 175), // #1261 + INST(Vpdpbssd , VexRvm_Lx , V(F20F38,50,_,x,0,_,_,_ ), 0 , 85 , 0 , 206, 179), // #1262 + INST(Vpdpbssds , VexRvm_Lx , V(F20F38,51,_,x,0,_,_,_ ), 0 , 85 , 0 , 206, 179), // #1263 + INST(Vpdpbsud , VexRvm_Lx , V(F30F38,50,_,x,0,_,_,_ ), 0 , 89 , 0 , 206, 179), // #1264 + INST(Vpdpbsuds , VexRvm_Lx , V(F30F38,51,_,x,0,_,_,_ ), 0 , 89 , 0 , 206, 179), // #1265 + INST(Vpdpbusd , VexRvm_Lx , V(660F38,50,_,x,_,0,4,FV ), 0 , 109, 0 , 376, 180), // #1266 + INST(Vpdpbusds , VexRvm_Lx , V(660F38,51,_,x,_,0,4,FV ), 0 , 109, 0 , 376, 180), // #1267 + INST(Vpdpbuud , VexRvm_Lx , V(000F38,50,_,x,0,_,_,_ ), 0 , 11 , 0 , 206, 179), // #1268 + INST(Vpdpbuuds , VexRvm_Lx , V(000F38,51,_,x,0,_,_,_ ), 0 , 11 , 0 , 206, 179), // #1269 + INST(Vpdpwssd , VexRvm_Lx , V(660F38,52,_,x,_,0,4,FV ), 0 , 109, 0 , 376, 180), // #1270 + INST(Vpdpwssds , VexRvm_Lx , V(660F38,53,_,x,_,0,4,FV ), 0 , 109, 0 , 376, 180), // #1271 + INST(Vpdpwsud , VexRvm_Lx , V(F30F38,D2,_,x,0,_,_,_ ), 0 , 89 , 0 , 206, 181), // #1272 + INST(Vpdpwsuds , VexRvm_Lx , V(F30F38,D3,_,x,0,_,_,_ ), 0 , 89 , 0 , 206, 181), // #1273 + INST(Vpdpwusd , VexRvm_Lx , V(660F38,D2,_,x,0,_,_,_ ), 0 , 30 , 0 , 206, 181), // #1274 + INST(Vpdpwusds , VexRvm_Lx , V(660F38,D3,_,x,0,_,_,_ ), 0 , 30 , 0 , 206, 181), // #1275 + INST(Vpdpwuud , VexRvm_Lx , V(000F38,D2,_,x,0,_,_,_ ), 0 , 11 , 0 , 206, 181), // #1276 + INST(Vpdpwuuds , VexRvm_Lx , V(000F38,D3,_,x,0,_,_,_ ), 0 , 11 , 0 , 206, 181), // #1277 + INST(Vperm2f128 , VexRvmi , V(660F3A,06,_,1,0,_,_,_ ), 0 , 170, 0 , 377, 146), // #1278 + INST(Vperm2i128 , VexRvmi , V(660F3A,46,_,1,0,_,_,_ ), 0 , 170, 0 , 377, 153), // #1279 + INST(Vpermb , VexRvm_Lx , E(660F38,8D,_,x,_,0,4,FVM), 0 , 113, 0 , 357, 182), // #1280 + INST(Vpermd , VexRvm_Lx , V(660F38,36,_,x,0,0,4,FV ), 0 , 109, 0 , 378, 164), // #1281 + INST(Vpermi2b , VexRvm_Lx , E(660F38,75,_,x,_,0,4,FVM), 0 , 113, 0 , 357, 182), // #1282 + INST(Vpermi2d , VexRvm_Lx , E(660F38,76,_,x,_,0,4,FV ), 0 , 113, 0 , 218, 149), // #1283 + INST(Vpermi2pd , VexRvm_Lx , E(660F38,77,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1284 + INST(Vpermi2ps , VexRvm_Lx , E(660F38,77,_,x,_,0,4,FV ), 0 , 113, 0 , 218, 149), // #1285 + INST(Vpermi2q , VexRvm_Lx , E(660F38,76,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1286 + INST(Vpermi2w , VexRvm_Lx , E(660F38,75,_,x,_,1,4,FVM), 0 , 112, 0 , 357, 160), // #1287 + INST(Vpermil2pd , VexRvrmiRvmri_Lx , V(660F3A,49,_,x,x,_,_,_ ), 0 , 75 , 0 , 379, 163), // #1288 + INST(Vpermil2ps , VexRvrmiRvmri_Lx , V(660F3A,48,_,x,x,_,_,_ ), 0 , 75 , 0 , 379, 163), // #1289 + INST(Vpermilpd , VexRvmRmi_Lx , V(660F38,0D,_,x,0,1,4,FV ), V(660F3A,05,_,x,0,1,4,FV ), 203, 112, 380, 144), // #1290 + INST(Vpermilps , VexRvmRmi_Lx , V(660F38,0C,_,x,0,0,4,FV ), V(660F3A,04,_,x,0,0,4,FV ), 109, 113, 381, 144), // #1291 + INST(Vpermpd , VexRvmRmi_Lx , E(660F38,16,_,x,1,1,4,FV ), V(660F3A,01,_,x,1,1,4,FV ), 206, 114, 382, 164), // #1292 + INST(Vpermps , VexRvm_Lx , V(660F38,16,_,x,0,0,4,FV ), 0 , 109, 0 , 378, 164), // #1293 + INST(Vpermq , VexRvmRmi_Lx , E(660F38,36,_,x,_,1,4,FV ), V(660F3A,00,_,x,1,1,4,FV ), 112, 115, 382, 164), // #1294 + INST(Vpermt2b , VexRvm_Lx , E(660F38,7D,_,x,_,0,4,FVM), 0 , 113, 0 , 357, 182), // #1295 + INST(Vpermt2d , VexRvm_Lx , E(660F38,7E,_,x,_,0,4,FV ), 0 , 113, 0 , 218, 149), // #1296 + INST(Vpermt2pd , VexRvm_Lx , E(660F38,7F,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1297 + INST(Vpermt2ps , VexRvm_Lx , E(660F38,7F,_,x,_,0,4,FV ), 0 , 113, 0 , 218, 149), // #1298 + INST(Vpermt2q , VexRvm_Lx , E(660F38,7E,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1299 + INST(Vpermt2w , VexRvm_Lx , E(660F38,7D,_,x,_,1,4,FVM), 0 , 112, 0 , 357, 160), // #1300 + INST(Vpermw , VexRvm_Lx , E(660F38,8D,_,x,_,1,4,FVM), 0 , 112, 0 , 357, 160), // #1301 + INST(Vpexpandb , VexRm_Lx , E(660F38,62,_,x,_,0,0,T1S), 0 , 204, 0 , 283, 178), // #1302 + INST(Vpexpandd , VexRm_Lx , E(660F38,89,_,x,_,0,2,T1S), 0 , 128, 0 , 283, 149), // #1303 + INST(Vpexpandq , VexRm_Lx , E(660F38,89,_,x,_,1,3,T1S), 0 , 127, 0 , 283, 149), // #1304 + INST(Vpexpandw , VexRm_Lx , E(660F38,62,_,x,_,1,1,T1S), 0 , 205, 0 , 283, 178), // #1305 + INST(Vpextrb , VexMri , V(660F3A,14,_,0,0,I,0,T1S), 0 , 75 , 0 , 383, 183), // #1306 + INST(Vpextrd , VexMri , V(660F3A,16,_,0,0,0,2,T1S), 0 , 175, 0 , 287, 150), // #1307 + INST(Vpextrq , VexMri , V(660F3A,16,_,0,1,1,3,T1S), 0 , 207, 0 , 384, 150), // #1308 + INST(Vpextrw , VexMri_Vpextrw , V(660F3A,15,_,0,0,I,1,T1S), 0 , 208, 0 , 385, 183), // #1309 + INST(Vpgatherdd , VexRmvRm_VM , V(660F38,90,_,x,0,_,_,_ ), E(660F38,90,_,x,_,0,2,T1S), 30 , 116, 306, 164), // #1310 + INST(Vpgatherdq , VexRmvRm_VM , V(660F38,90,_,x,1,_,_,_ ), E(660F38,90,_,x,_,1,3,T1S), 187, 117, 305, 164), // #1311 + INST(Vpgatherqd , VexRmvRm_VM , V(660F38,91,_,x,0,_,_,_ ), E(660F38,91,_,x,_,0,2,T1S), 30 , 118, 308, 164), // #1312 + INST(Vpgatherqq , VexRmvRm_VM , V(660F38,91,_,x,1,_,_,_ ), E(660F38,91,_,x,_,1,3,T1S), 187, 119, 307, 164), // #1313 + INST(Vphaddbd , VexRm , V(XOP_M9,C2,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1314 + INST(Vphaddbq , VexRm , V(XOP_M9,C3,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1315 + INST(Vphaddbw , VexRm , V(XOP_M9,C1,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1316 + INST(Vphaddd , VexRvm_Lx , V(660F38,02,_,x,I,_,_,_ ), 0 , 30 , 0 , 206, 171), // #1317 + INST(Vphadddq , VexRm , V(XOP_M9,CB,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1318 + INST(Vphaddsw , VexRvm_Lx , V(660F38,03,_,x,I,_,_,_ ), 0 , 30 , 0 , 206, 171), // #1319 + INST(Vphaddubd , VexRm , V(XOP_M9,D2,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1320 + INST(Vphaddubq , VexRm , V(XOP_M9,D3,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1321 + INST(Vphaddubw , VexRm , V(XOP_M9,D1,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1322 + INST(Vphaddudq , VexRm , V(XOP_M9,DB,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1323 + INST(Vphadduwd , VexRm , V(XOP_M9,D6,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1324 + INST(Vphadduwq , VexRm , V(XOP_M9,D7,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1325 + INST(Vphaddw , VexRvm_Lx , V(660F38,01,_,x,I,_,_,_ ), 0 , 30 , 0 , 206, 171), // #1326 + INST(Vphaddwd , VexRm , V(XOP_M9,C6,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1327 + INST(Vphaddwq , VexRm , V(XOP_M9,C7,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1328 + INST(Vphminposuw , VexRm , V(660F38,41,_,0,I,_,_,_ ), 0 , 30 , 0 , 208, 146), // #1329 + INST(Vphsubbw , VexRm , V(XOP_M9,E1,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1330 + INST(Vphsubd , VexRvm_Lx , V(660F38,06,_,x,I,_,_,_ ), 0 , 30 , 0 , 206, 171), // #1331 + INST(Vphsubdq , VexRm , V(XOP_M9,E3,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1332 + INST(Vphsubsw , VexRvm_Lx , V(660F38,07,_,x,I,_,_,_ ), 0 , 30 , 0 , 206, 171), // #1333 + INST(Vphsubw , VexRvm_Lx , V(660F38,05,_,x,I,_,_,_ ), 0 , 30 , 0 , 206, 171), // #1334 + INST(Vphsubwd , VexRm , V(XOP_M9,E2,_,0,0,_,_,_ ), 0 , 81 , 0 , 208, 163), // #1335 + INST(Vpinsrb , VexRvmi , V(660F3A,20,_,0,0,I,0,T1S), 0 , 75 , 0 , 386, 183), // #1336 + INST(Vpinsrd , VexRvmi , V(660F3A,22,_,0,0,0,2,T1S), 0 , 175, 0 , 387, 150), // #1337 + INST(Vpinsrq , VexRvmi , V(660F3A,22,_,0,1,1,3,T1S), 0 , 207, 0 , 388, 150), // #1338 + INST(Vpinsrw , VexRvmi , V(660F00,C4,_,0,0,I,1,T1S), 0 , 209, 0 , 389, 183), // #1339 + INST(Vplzcntd , VexRm_Lx , E(660F38,44,_,x,_,0,4,FV ), 0 , 113, 0 , 375, 175), // #1340 + INST(Vplzcntq , VexRm_Lx , E(660F38,44,_,x,_,1,4,FV ), 0 , 112, 0 , 350, 175), // #1341 + INST(Vpmacsdd , VexRvmr , V(XOP_M8,9E,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1342 + INST(Vpmacsdqh , VexRvmr , V(XOP_M8,9F,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1343 + INST(Vpmacsdql , VexRvmr , V(XOP_M8,97,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1344 + INST(Vpmacssdd , VexRvmr , V(XOP_M8,8E,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1345 + INST(Vpmacssdqh , VexRvmr , V(XOP_M8,8F,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1346 + INST(Vpmacssdql , VexRvmr , V(XOP_M8,87,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1347 + INST(Vpmacsswd , VexRvmr , V(XOP_M8,86,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1348 + INST(Vpmacssww , VexRvmr , V(XOP_M8,85,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1349 + INST(Vpmacswd , VexRvmr , V(XOP_M8,96,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1350 + INST(Vpmacsww , VexRvmr , V(XOP_M8,95,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1351 + INST(Vpmadcsswd , VexRvmr , V(XOP_M8,A6,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1352 + INST(Vpmadcswd , VexRvmr , V(XOP_M8,B6,_,0,0,_,_,_ ), 0 , 202, 0 , 390, 163), // #1353 + INST(Vpmadd52huq , VexRvm_Lx , V(660F38,B5,_,x,1,1,4,FV ), 0 , 180, 0 , 391, 184), // #1354 + INST(Vpmadd52luq , VexRvm_Lx , V(660F38,B4,_,x,1,1,4,FV ), 0 , 180, 0 , 391, 184), // #1355 + INST(Vpmaddubsw , VexRvm_Lx , V(660F38,04,_,x,I,I,4,FVM), 0 , 109, 0 , 316, 173), // #1356 + INST(Vpmaddwd , VexRvm_Lx , V(660F00,F5,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1357 + INST(Vpmaskmovd , VexRvmMvr_Lx , V(660F38,8C,_,x,0,_,_,_ ), V(660F38,8E,_,x,0,_,_,_ ), 30 , 120, 323, 153), // #1358 + INST(Vpmaskmovq , VexRvmMvr_Lx , V(660F38,8C,_,x,1,_,_,_ ), V(660F38,8E,_,x,1,_,_,_ ), 187, 121, 323, 153), // #1359 + INST(Vpmaxsb , VexRvm_Lx , V(660F38,3C,_,x,I,I,4,FVM), 0 , 109, 0 , 392, 173), // #1360 + INST(Vpmaxsd , VexRvm_Lx , V(660F38,3D,_,x,I,0,4,FV ), 0 , 109, 0 , 215, 154), // #1361 + INST(Vpmaxsq , VexRvm_Lx , E(660F38,3D,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1362 + INST(Vpmaxsw , VexRvm_Lx , V(660F00,EE,_,x,I,I,4,FVM), 0 , 143, 0 , 392, 173), // #1363 + INST(Vpmaxub , VexRvm_Lx , V(660F00,DE,_,x,I,I,4,FVM), 0 , 143, 0 , 392, 173), // #1364 + INST(Vpmaxud , VexRvm_Lx , V(660F38,3F,_,x,I,0,4,FV ), 0 , 109, 0 , 215, 154), // #1365 + INST(Vpmaxuq , VexRvm_Lx , E(660F38,3F,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1366 + INST(Vpmaxuw , VexRvm_Lx , V(660F38,3E,_,x,I,I,4,FVM), 0 , 109, 0 , 392, 173), // #1367 + INST(Vpminsb , VexRvm_Lx , V(660F38,38,_,x,I,I,4,FVM), 0 , 109, 0 , 392, 173), // #1368 + INST(Vpminsd , VexRvm_Lx , V(660F38,39,_,x,I,0,4,FV ), 0 , 109, 0 , 215, 154), // #1369 + INST(Vpminsq , VexRvm_Lx , E(660F38,39,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1370 + INST(Vpminsw , VexRvm_Lx , V(660F00,EA,_,x,I,I,4,FVM), 0 , 143, 0 , 392, 173), // #1371 + INST(Vpminub , VexRvm_Lx , V(660F00,DA,_,x,I,_,4,FVM), 0 , 143, 0 , 392, 173), // #1372 + INST(Vpminud , VexRvm_Lx , V(660F38,3B,_,x,I,0,4,FV ), 0 , 109, 0 , 215, 154), // #1373 + INST(Vpminuq , VexRvm_Lx , E(660F38,3B,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1374 + INST(Vpminuw , VexRvm_Lx , V(660F38,3A,_,x,I,_,4,FVM), 0 , 109, 0 , 392, 173), // #1375 + INST(Vpmovb2m , VexRm_Lx , E(F30F38,29,_,x,_,0,_,_ ), 0 , 200, 0 , 393, 160), // #1376 + INST(Vpmovd2m , VexRm_Lx , E(F30F38,39,_,x,_,0,_,_ ), 0 , 200, 0 , 393, 152), // #1377 + INST(Vpmovdb , VexMr_Lx , E(F30F38,31,_,x,_,0,2,QVM), 0 , 210, 0 , 394, 149), // #1378 + INST(Vpmovdw , VexMr_Lx , E(F30F38,33,_,x,_,0,3,HVM), 0 , 211, 0 , 395, 149), // #1379 + INST(Vpmovm2b , VexRm_Lx , E(F30F38,28,_,x,_,0,_,_ ), 0 , 200, 0 , 360, 160), // #1380 + INST(Vpmovm2d , VexRm_Lx , E(F30F38,38,_,x,_,0,_,_ ), 0 , 200, 0 , 360, 152), // #1381 + INST(Vpmovm2q , VexRm_Lx , E(F30F38,38,_,x,_,1,_,_ ), 0 , 199, 0 , 360, 152), // #1382 + INST(Vpmovm2w , VexRm_Lx , E(F30F38,28,_,x,_,1,_,_ ), 0 , 199, 0 , 360, 160), // #1383 + INST(Vpmovmskb , VexRm_Lx , V(660F00,D7,_,x,I,_,_,_ ), 0 , 71 , 0 , 336, 171), // #1384 + INST(Vpmovq2m , VexRm_Lx , E(F30F38,39,_,x,_,1,_,_ ), 0 , 199, 0 , 393, 152), // #1385 + INST(Vpmovqb , VexMr_Lx , E(F30F38,32,_,x,_,0,1,OVM), 0 , 212, 0 , 396, 149), // #1386 + INST(Vpmovqd , VexMr_Lx , E(F30F38,35,_,x,_,0,3,HVM), 0 , 211, 0 , 395, 149), // #1387 + INST(Vpmovqw , VexMr_Lx , E(F30F38,34,_,x,_,0,2,QVM), 0 , 210, 0 , 394, 149), // #1388 + INST(Vpmovsdb , VexMr_Lx , E(F30F38,21,_,x,_,0,2,QVM), 0 , 210, 0 , 394, 149), // #1389 + INST(Vpmovsdw , VexMr_Lx , E(F30F38,23,_,x,_,0,3,HVM), 0 , 211, 0 , 395, 149), // #1390 + INST(Vpmovsqb , VexMr_Lx , E(F30F38,22,_,x,_,0,1,OVM), 0 , 212, 0 , 396, 149), // #1391 + INST(Vpmovsqd , VexMr_Lx , E(F30F38,25,_,x,_,0,3,HVM), 0 , 211, 0 , 395, 149), // #1392 + INST(Vpmovsqw , VexMr_Lx , E(F30F38,24,_,x,_,0,2,QVM), 0 , 210, 0 , 394, 149), // #1393 + INST(Vpmovswb , VexMr_Lx , E(F30F38,20,_,x,_,0,3,HVM), 0 , 211, 0 , 395, 160), // #1394 + INST(Vpmovsxbd , VexRm_Lx , V(660F38,21,_,x,I,I,2,QVM), 0 , 213, 0 , 397, 154), // #1395 + INST(Vpmovsxbq , VexRm_Lx , V(660F38,22,_,x,I,I,1,OVM), 0 , 214, 0 , 398, 154), // #1396 + INST(Vpmovsxbw , VexRm_Lx , V(660F38,20,_,x,I,I,3,HVM), 0 , 138, 0 , 399, 173), // #1397 + INST(Vpmovsxdq , VexRm_Lx , V(660F38,25,_,x,I,0,3,HVM), 0 , 138, 0 , 399, 154), // #1398 + INST(Vpmovsxwd , VexRm_Lx , V(660F38,23,_,x,I,I,3,HVM), 0 , 138, 0 , 399, 154), // #1399 + INST(Vpmovsxwq , VexRm_Lx , V(660F38,24,_,x,I,I,2,QVM), 0 , 213, 0 , 397, 154), // #1400 + INST(Vpmovusdb , VexMr_Lx , E(F30F38,11,_,x,_,0,2,QVM), 0 , 210, 0 , 394, 149), // #1401 + INST(Vpmovusdw , VexMr_Lx , E(F30F38,13,_,x,_,0,3,HVM), 0 , 211, 0 , 395, 149), // #1402 + INST(Vpmovusqb , VexMr_Lx , E(F30F38,12,_,x,_,0,1,OVM), 0 , 212, 0 , 396, 149), // #1403 + INST(Vpmovusqd , VexMr_Lx , E(F30F38,15,_,x,_,0,3,HVM), 0 , 211, 0 , 395, 149), // #1404 + INST(Vpmovusqw , VexMr_Lx , E(F30F38,14,_,x,_,0,2,QVM), 0 , 210, 0 , 394, 149), // #1405 + INST(Vpmovuswb , VexMr_Lx , E(F30F38,10,_,x,_,0,3,HVM), 0 , 211, 0 , 395, 160), // #1406 + INST(Vpmovw2m , VexRm_Lx , E(F30F38,29,_,x,_,1,_,_ ), 0 , 199, 0 , 393, 160), // #1407 + INST(Vpmovwb , VexMr_Lx , E(F30F38,30,_,x,_,0,3,HVM), 0 , 211, 0 , 395, 160), // #1408 + INST(Vpmovzxbd , VexRm_Lx , V(660F38,31,_,x,I,I,2,QVM), 0 , 213, 0 , 397, 154), // #1409 + INST(Vpmovzxbq , VexRm_Lx , V(660F38,32,_,x,I,I,1,OVM), 0 , 214, 0 , 398, 154), // #1410 + INST(Vpmovzxbw , VexRm_Lx , V(660F38,30,_,x,I,I,3,HVM), 0 , 138, 0 , 399, 173), // #1411 + INST(Vpmovzxdq , VexRm_Lx , V(660F38,35,_,x,I,0,3,HVM), 0 , 138, 0 , 399, 154), // #1412 + INST(Vpmovzxwd , VexRm_Lx , V(660F38,33,_,x,I,I,3,HVM), 0 , 138, 0 , 399, 154), // #1413 + INST(Vpmovzxwq , VexRm_Lx , V(660F38,34,_,x,I,I,2,QVM), 0 , 213, 0 , 397, 154), // #1414 + INST(Vpmuldq , VexRvm_Lx , V(660F38,28,_,x,I,1,4,FV ), 0 , 203, 0 , 212, 154), // #1415 + INST(Vpmulhrsw , VexRvm_Lx , V(660F38,0B,_,x,I,I,4,FVM), 0 , 109, 0 , 316, 173), // #1416 + INST(Vpmulhuw , VexRvm_Lx , V(660F00,E4,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1417 + INST(Vpmulhw , VexRvm_Lx , V(660F00,E5,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1418 + INST(Vpmulld , VexRvm_Lx , V(660F38,40,_,x,I,0,4,FV ), 0 , 109, 0 , 213, 154), // #1419 + INST(Vpmullq , VexRvm_Lx , E(660F38,40,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 152), // #1420 + INST(Vpmullw , VexRvm_Lx , V(660F00,D5,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1421 + INST(Vpmultishiftqb , VexRvm_Lx , E(660F38,83,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 182), // #1422 + INST(Vpmuludq , VexRvm_Lx , V(660F00,F4,_,x,I,1,4,FV ), 0 , 102, 0 , 212, 154), // #1423 + INST(Vpopcntb , VexRm_Lx , E(660F38,54,_,x,_,0,4,FV ), 0 , 113, 0 , 283, 185), // #1424 + INST(Vpopcntd , VexRm_Lx , E(660F38,55,_,x,_,0,4,FVM), 0 , 113, 0 , 375, 186), // #1425 + INST(Vpopcntq , VexRm_Lx , E(660F38,55,_,x,_,1,4,FVM), 0 , 112, 0 , 350, 186), // #1426 + INST(Vpopcntw , VexRm_Lx , E(660F38,54,_,x,_,1,4,FV ), 0 , 112, 0 , 283, 185), // #1427 + INST(Vpor , VexRvm_Lx , V(660F00,EB,_,x,I,_,_,_ ), 0 , 71 , 0 , 351, 171), // #1428 + INST(Vpord , VexRvm_Lx , E(660F00,EB,_,x,_,0,4,FV ), 0 , 192, 0 , 352, 149), // #1429 + INST(Vporq , VexRvm_Lx , E(660F00,EB,_,x,_,1,4,FV ), 0 , 134, 0 , 356, 149), // #1430 + INST(Vpperm , VexRvrmRvmr , V(XOP_M8,A3,_,0,x,_,_,_ ), 0 , 202, 0 , 400, 163), // #1431 + INST(Vprold , VexVmi_Lx , E(660F00,72,1,x,_,0,4,FV ), 0 , 215, 0 , 401, 149), // #1432 + INST(Vprolq , VexVmi_Lx , E(660F00,72,1,x,_,1,4,FV ), 0 , 216, 0 , 402, 149), // #1433 + INST(Vprolvd , VexRvm_Lx , E(660F38,15,_,x,_,0,4,FV ), 0 , 113, 0 , 218, 149), // #1434 + INST(Vprolvq , VexRvm_Lx , E(660F38,15,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1435 + INST(Vprord , VexVmi_Lx , E(660F00,72,0,x,_,0,4,FV ), 0 , 192, 0 , 401, 149), // #1436 + INST(Vprorq , VexVmi_Lx , E(660F00,72,0,x,_,1,4,FV ), 0 , 134, 0 , 402, 149), // #1437 + INST(Vprorvd , VexRvm_Lx , E(660F38,14,_,x,_,0,4,FV ), 0 , 113, 0 , 218, 149), // #1438 + INST(Vprorvq , VexRvm_Lx , E(660F38,14,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1439 + INST(Vprotb , VexRvmRmvRmi , V(XOP_M9,90,_,0,x,_,_,_ ), V(XOP_M8,C0,_,0,x,_,_,_ ), 81 , 122, 403, 163), // #1440 + INST(Vprotd , VexRvmRmvRmi , V(XOP_M9,92,_,0,x,_,_,_ ), V(XOP_M8,C2,_,0,x,_,_,_ ), 81 , 123, 403, 163), // #1441 + INST(Vprotq , VexRvmRmvRmi , V(XOP_M9,93,_,0,x,_,_,_ ), V(XOP_M8,C3,_,0,x,_,_,_ ), 81 , 124, 403, 163), // #1442 + INST(Vprotw , VexRvmRmvRmi , V(XOP_M9,91,_,0,x,_,_,_ ), V(XOP_M8,C1,_,0,x,_,_,_ ), 81 , 125, 403, 163), // #1443 + INST(Vpsadbw , VexRvm_Lx , V(660F00,F6,_,x,I,I,4,FVM), 0 , 143, 0 , 207, 173), // #1444 + INST(Vpscatterdd , VexMr_VM , E(660F38,A0,_,x,_,0,2,T1S), 0 , 128, 0 , 404, 149), // #1445 + INST(Vpscatterdq , VexMr_VM , E(660F38,A0,_,x,_,1,3,T1S), 0 , 127, 0 , 405, 149), // #1446 + INST(Vpscatterqd , VexMr_VM , E(660F38,A1,_,x,_,0,2,T1S), 0 , 128, 0 , 406, 149), // #1447 + INST(Vpscatterqq , VexMr_VM , E(660F38,A1,_,x,_,1,3,T1S), 0 , 127, 0 , 407, 149), // #1448 + INST(Vpshab , VexRvmRmv , V(XOP_M9,98,_,0,x,_,_,_ ), 0 , 81 , 0 , 408, 163), // #1449 + INST(Vpshad , VexRvmRmv , V(XOP_M9,9A,_,0,x,_,_,_ ), 0 , 81 , 0 , 408, 163), // #1450 + INST(Vpshaq , VexRvmRmv , V(XOP_M9,9B,_,0,x,_,_,_ ), 0 , 81 , 0 , 408, 163), // #1451 + INST(Vpshaw , VexRvmRmv , V(XOP_M9,99,_,0,x,_,_,_ ), 0 , 81 , 0 , 408, 163), // #1452 + INST(Vpshlb , VexRvmRmv , V(XOP_M9,94,_,0,x,_,_,_ ), 0 , 81 , 0 , 408, 163), // #1453 + INST(Vpshld , VexRvmRmv , V(XOP_M9,96,_,0,x,_,_,_ ), 0 , 81 , 0 , 408, 163), // #1454 + INST(Vpshldd , VexRvmi_Lx , E(660F3A,71,_,x,_,0,4,FV ), 0 , 110, 0 , 210, 178), // #1455 + INST(Vpshldq , VexRvmi_Lx , E(660F3A,71,_,x,_,1,4,FV ), 0 , 111, 0 , 211, 178), // #1456 + INST(Vpshldvd , VexRvm_Lx , E(660F38,71,_,x,_,0,4,FV ), 0 , 113, 0 , 218, 178), // #1457 + INST(Vpshldvq , VexRvm_Lx , E(660F38,71,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 178), // #1458 + INST(Vpshldvw , VexRvm_Lx , E(660F38,70,_,x,_,1,4,FVM), 0 , 112, 0 , 357, 178), // #1459 + INST(Vpshldw , VexRvmi_Lx , E(660F3A,70,_,x,_,1,4,FVM), 0 , 111, 0 , 281, 178), // #1460 + INST(Vpshlq , VexRvmRmv , V(XOP_M9,97,_,0,x,_,_,_ ), 0 , 81 , 0 , 408, 163), // #1461 + INST(Vpshlw , VexRvmRmv , V(XOP_M9,95,_,0,x,_,_,_ ), 0 , 81 , 0 , 408, 163), // #1462 + INST(Vpshrdd , VexRvmi_Lx , E(660F3A,73,_,x,_,0,4,FV ), 0 , 110, 0 , 210, 178), // #1463 + INST(Vpshrdq , VexRvmi_Lx , E(660F3A,73,_,x,_,1,4,FV ), 0 , 111, 0 , 211, 178), // #1464 + INST(Vpshrdvd , VexRvm_Lx , E(660F38,73,_,x,_,0,4,FV ), 0 , 113, 0 , 218, 178), // #1465 + INST(Vpshrdvq , VexRvm_Lx , E(660F38,73,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 178), // #1466 + INST(Vpshrdvw , VexRvm_Lx , E(660F38,72,_,x,_,1,4,FVM), 0 , 112, 0 , 357, 178), // #1467 + INST(Vpshrdw , VexRvmi_Lx , E(660F3A,72,_,x,_,1,4,FVM), 0 , 111, 0 , 281, 178), // #1468 + INST(Vpshufb , VexRvm_Lx , V(660F38,00,_,x,I,I,4,FVM), 0 , 109, 0 , 316, 173), // #1469 + INST(Vpshufbitqmb , VexRvm_Lx , E(660F38,8F,_,x,0,0,4,FVM), 0 , 113, 0 , 409, 185), // #1470 + INST(Vpshufd , VexRmi_Lx , V(660F00,70,_,x,I,0,4,FV ), 0 , 143, 0 , 410, 154), // #1471 + INST(Vpshufhw , VexRmi_Lx , V(F30F00,70,_,x,I,I,4,FVM), 0 , 160, 0 , 411, 173), // #1472 + INST(Vpshuflw , VexRmi_Lx , V(F20F00,70,_,x,I,I,4,FVM), 0 , 217, 0 , 411, 173), // #1473 + INST(Vpsignb , VexRvm_Lx , V(660F38,08,_,x,I,_,_,_ ), 0 , 30 , 0 , 206, 171), // #1474 + INST(Vpsignd , VexRvm_Lx , V(660F38,0A,_,x,I,_,_,_ ), 0 , 30 , 0 , 206, 171), // #1475 + INST(Vpsignw , VexRvm_Lx , V(660F38,09,_,x,I,_,_,_ ), 0 , 30 , 0 , 206, 171), // #1476 + INST(Vpslld , VexRvmVmi_Lx_MEvex , V(660F00,F2,_,x,I,0,4,128), V(660F00,72,6,x,I,0,4,FV ), 218, 126, 412, 154), // #1477 + INST(Vpslldq , VexVmi_Lx_MEvex , V(660F00,73,7,x,I,I,4,FVM), 0 , 219, 0 , 413, 173), // #1478 + INST(Vpsllq , VexRvmVmi_Lx_MEvex , V(660F00,F3,_,x,I,1,4,128), V(660F00,73,6,x,I,1,4,FV ), 220, 127, 414, 154), // #1479 + INST(Vpsllvd , VexRvm_Lx , V(660F38,47,_,x,0,0,4,FV ), 0 , 109, 0 , 213, 164), // #1480 + INST(Vpsllvq , VexRvm_Lx , V(660F38,47,_,x,1,1,4,FV ), 0 , 180, 0 , 212, 164), // #1481 + INST(Vpsllvw , VexRvm_Lx , E(660F38,12,_,x,_,1,4,FVM), 0 , 112, 0 , 357, 160), // #1482 + INST(Vpsllw , VexRvmVmi_Lx_MEvex , V(660F00,F1,_,x,I,I,4,128), V(660F00,71,6,x,I,I,4,FVM), 218, 128, 415, 173), // #1483 + INST(Vpsrad , VexRvmVmi_Lx_MEvex , V(660F00,E2,_,x,I,0,4,128), V(660F00,72,4,x,I,0,4,FV ), 218, 129, 412, 154), // #1484 + INST(Vpsraq , VexRvmVmi_Lx_MEvex , E(660F00,E2,_,x,_,1,4,128), E(660F00,72,4,x,_,1,4,FV ), 221, 130, 416, 149), // #1485 + INST(Vpsravd , VexRvm_Lx , V(660F38,46,_,x,0,0,4,FV ), 0 , 109, 0 , 213, 164), // #1486 + INST(Vpsravq , VexRvm_Lx , E(660F38,46,_,x,_,1,4,FV ), 0 , 112, 0 , 217, 149), // #1487 + INST(Vpsravw , VexRvm_Lx , E(660F38,11,_,x,_,1,4,FVM), 0 , 112, 0 , 357, 160), // #1488 + INST(Vpsraw , VexRvmVmi_Lx_MEvex , V(660F00,E1,_,x,I,I,4,128), V(660F00,71,4,x,I,I,4,FVM), 218, 131, 415, 173), // #1489 + INST(Vpsrld , VexRvmVmi_Lx_MEvex , V(660F00,D2,_,x,I,0,4,128), V(660F00,72,2,x,I,0,4,FV ), 218, 132, 412, 154), // #1490 + INST(Vpsrldq , VexVmi_Lx_MEvex , V(660F00,73,3,x,I,I,4,FVM), 0 , 222, 0 , 413, 173), // #1491 + INST(Vpsrlq , VexRvmVmi_Lx_MEvex , V(660F00,D3,_,x,I,1,4,128), V(660F00,73,2,x,I,1,4,FV ), 220, 133, 414, 154), // #1492 + INST(Vpsrlvd , VexRvm_Lx , V(660F38,45,_,x,0,0,4,FV ), 0 , 109, 0 , 213, 164), // #1493 + INST(Vpsrlvq , VexRvm_Lx , V(660F38,45,_,x,1,1,4,FV ), 0 , 180, 0 , 212, 164), // #1494 + INST(Vpsrlvw , VexRvm_Lx , E(660F38,10,_,x,_,1,4,FVM), 0 , 112, 0 , 357, 160), // #1495 + INST(Vpsrlw , VexRvmVmi_Lx_MEvex , V(660F00,D1,_,x,I,I,4,128), V(660F00,71,2,x,I,I,4,FVM), 218, 134, 415, 173), // #1496 + INST(Vpsubb , VexRvm_Lx , V(660F00,F8,_,x,I,I,4,FVM), 0 , 143, 0 , 417, 173), // #1497 + INST(Vpsubd , VexRvm_Lx , V(660F00,FA,_,x,I,0,4,FV ), 0 , 143, 0 , 418, 154), // #1498 + INST(Vpsubq , VexRvm_Lx , V(660F00,FB,_,x,I,1,4,FV ), 0 , 102, 0 , 419, 154), // #1499 + INST(Vpsubsb , VexRvm_Lx , V(660F00,E8,_,x,I,I,4,FVM), 0 , 143, 0 , 417, 173), // #1500 + INST(Vpsubsw , VexRvm_Lx , V(660F00,E9,_,x,I,I,4,FVM), 0 , 143, 0 , 417, 173), // #1501 + INST(Vpsubusb , VexRvm_Lx , V(660F00,D8,_,x,I,I,4,FVM), 0 , 143, 0 , 417, 173), // #1502 + INST(Vpsubusw , VexRvm_Lx , V(660F00,D9,_,x,I,I,4,FVM), 0 , 143, 0 , 417, 173), // #1503 + INST(Vpsubw , VexRvm_Lx , V(660F00,F9,_,x,I,I,4,FVM), 0 , 143, 0 , 417, 173), // #1504 + INST(Vpternlogd , VexRvmi_Lx , E(660F3A,25,_,x,_,0,4,FV ), 0 , 110, 0 , 210, 149), // #1505 + INST(Vpternlogq , VexRvmi_Lx , E(660F3A,25,_,x,_,1,4,FV ), 0 , 111, 0 , 211, 149), // #1506 + INST(Vptest , VexRm_Lx , V(660F38,17,_,x,I,_,_,_ ), 0 , 30 , 0 , 302, 177), // #1507 + INST(Vptestmb , VexRvm_Lx , E(660F38,26,_,x,_,0,4,FVM), 0 , 113, 0 , 409, 160), // #1508 + INST(Vptestmd , VexRvm_Lx , E(660F38,27,_,x,_,0,4,FV ), 0 , 113, 0 , 420, 149), // #1509 + INST(Vptestmq , VexRvm_Lx , E(660F38,27,_,x,_,1,4,FV ), 0 , 112, 0 , 421, 149), // #1510 + INST(Vptestmw , VexRvm_Lx , E(660F38,26,_,x,_,1,4,FVM), 0 , 112, 0 , 409, 160), // #1511 + INST(Vptestnmb , VexRvm_Lx , E(F30F38,26,_,x,_,0,4,FVM), 0 , 169, 0 , 409, 160), // #1512 + INST(Vptestnmd , VexRvm_Lx , E(F30F38,27,_,x,_,0,4,FV ), 0 , 169, 0 , 420, 149), // #1513 + INST(Vptestnmq , VexRvm_Lx , E(F30F38,27,_,x,_,1,4,FV ), 0 , 223, 0 , 421, 149), // #1514 + INST(Vptestnmw , VexRvm_Lx , E(F30F38,26,_,x,_,1,4,FVM), 0 , 223, 0 , 409, 160), // #1515 + INST(Vpunpckhbw , VexRvm_Lx , V(660F00,68,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1516 + INST(Vpunpckhdq , VexRvm_Lx , V(660F00,6A,_,x,I,0,4,FV ), 0 , 143, 0 , 213, 154), // #1517 + INST(Vpunpckhqdq , VexRvm_Lx , V(660F00,6D,_,x,I,1,4,FV ), 0 , 102, 0 , 212, 154), // #1518 + INST(Vpunpckhwd , VexRvm_Lx , V(660F00,69,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1519 + INST(Vpunpcklbw , VexRvm_Lx , V(660F00,60,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1520 + INST(Vpunpckldq , VexRvm_Lx , V(660F00,62,_,x,I,0,4,FV ), 0 , 143, 0 , 213, 154), // #1521 + INST(Vpunpcklqdq , VexRvm_Lx , V(660F00,6C,_,x,I,1,4,FV ), 0 , 102, 0 , 212, 154), // #1522 + INST(Vpunpcklwd , VexRvm_Lx , V(660F00,61,_,x,I,I,4,FVM), 0 , 143, 0 , 316, 173), // #1523 + INST(Vpxor , VexRvm_Lx , V(660F00,EF,_,x,I,_,_,_ ), 0 , 71 , 0 , 353, 171), // #1524 + INST(Vpxord , VexRvm_Lx , E(660F00,EF,_,x,_,0,4,FV ), 0 , 192, 0 , 354, 149), // #1525 + INST(Vpxorq , VexRvm_Lx , E(660F00,EF,_,x,_,1,4,FV ), 0 , 134, 0 , 355, 149), // #1526 + INST(Vrangepd , VexRvmi_Lx , E(660F3A,50,_,x,_,1,4,FV ), 0 , 111, 0 , 289, 152), // #1527 + INST(Vrangeps , VexRvmi_Lx , E(660F3A,50,_,x,_,0,4,FV ), 0 , 110, 0 , 290, 152), // #1528 + INST(Vrangesd , VexRvmi , E(660F3A,51,_,I,_,1,3,T1S), 0 , 178, 0 , 291, 152), // #1529 + INST(Vrangess , VexRvmi , E(660F3A,51,_,I,_,0,2,T1S), 0 , 179, 0 , 292, 152), // #1530 + INST(Vrcp14pd , VexRm_Lx , E(660F38,4C,_,x,_,1,4,FV ), 0 , 112, 0 , 350, 149), // #1531 + INST(Vrcp14ps , VexRm_Lx , E(660F38,4C,_,x,_,0,4,FV ), 0 , 113, 0 , 375, 149), // #1532 + INST(Vrcp14sd , VexRvm , E(660F38,4D,_,I,_,1,3,T1S), 0 , 127, 0 , 422, 149), // #1533 + INST(Vrcp14ss , VexRvm , E(660F38,4D,_,I,_,0,2,T1S), 0 , 128, 0 , 423, 149), // #1534 + INST(Vrcpph , VexRm_Lx , E(66MAP6,4C,_,_,_,0,4,FV ), 0 , 181, 0 , 424, 145), // #1535 + INST(Vrcpps , VexRm_Lx , V(000F00,53,_,x,I,_,_,_ ), 0 , 74 , 0 , 302, 146), // #1536 + INST(Vrcpsh , VexRvm , E(66MAP6,4D,_,_,_,0,1,T1S), 0 , 183, 0 , 425, 145), // #1537 + INST(Vrcpss , VexRvm , V(F30F00,53,_,I,I,_,_,_ ), 0 , 193, 0 , 426, 146), // #1538 + INST(Vreducepd , VexRmi_Lx , E(660F3A,56,_,x,_,1,4,FV ), 0 , 111, 0 , 402, 152), // #1539 + INST(Vreduceph , VexRmi_Lx , E(000F3A,56,_,_,_,0,4,FV ), 0 , 122, 0 , 312, 145), // #1540 + INST(Vreduceps , VexRmi_Lx , E(660F3A,56,_,x,_,0,4,FV ), 0 , 110, 0 , 401, 152), // #1541 + INST(Vreducesd , VexRvmi , E(660F3A,57,_,I,_,1,3,T1S), 0 , 178, 0 , 427, 152), // #1542 + INST(Vreducesh , VexRvmi , E(000F3A,57,_,_,_,0,1,T1S), 0 , 186, 0 , 314, 145), // #1543 + INST(Vreducess , VexRvmi , E(660F3A,57,_,I,_,0,2,T1S), 0 , 179, 0 , 428, 152), // #1544 + INST(Vrndscalepd , VexRmi_Lx , E(660F3A,09,_,x,_,1,4,FV ), 0 , 111, 0 , 311, 149), // #1545 + INST(Vrndscaleph , VexRmi_Lx , E(000F3A,08,_,_,_,0,4,FV ), 0 , 122, 0 , 312, 145), // #1546 + INST(Vrndscaleps , VexRmi_Lx , E(660F3A,08,_,x,_,0,4,FV ), 0 , 110, 0 , 313, 149), // #1547 + INST(Vrndscalesd , VexRvmi , E(660F3A,0B,_,I,_,1,3,T1S), 0 , 178, 0 , 291, 149), // #1548 + INST(Vrndscalesh , VexRvmi , E(000F3A,0A,_,_,_,0,1,T1S), 0 , 186, 0 , 314, 145), // #1549 + INST(Vrndscaless , VexRvmi , E(660F3A,0A,_,I,_,0,2,T1S), 0 , 179, 0 , 292, 149), // #1550 + INST(Vroundpd , VexRmi_Lx , V(660F3A,09,_,x,I,_,_,_ ), 0 , 75 , 0 , 429, 146), // #1551 + INST(Vroundps , VexRmi_Lx , V(660F3A,08,_,x,I,_,_,_ ), 0 , 75 , 0 , 429, 146), // #1552 + INST(Vroundsd , VexRvmi , V(660F3A,0B,_,I,I,_,_,_ ), 0 , 75 , 0 , 430, 146), // #1553 + INST(Vroundss , VexRvmi , V(660F3A,0A,_,I,I,_,_,_ ), 0 , 75 , 0 , 431, 146), // #1554 + INST(Vrsqrt14pd , VexRm_Lx , E(660F38,4E,_,x,_,1,4,FV ), 0 , 112, 0 , 350, 149), // #1555 + INST(Vrsqrt14ps , VexRm_Lx , E(660F38,4E,_,x,_,0,4,FV ), 0 , 113, 0 , 375, 149), // #1556 + INST(Vrsqrt14sd , VexRvm , E(660F38,4F,_,I,_,1,3,T1S), 0 , 127, 0 , 422, 149), // #1557 + INST(Vrsqrt14ss , VexRvm , E(660F38,4F,_,I,_,0,2,T1S), 0 , 128, 0 , 423, 149), // #1558 + INST(Vrsqrtph , VexRm_Lx , E(66MAP6,4E,_,_,_,0,4,FV ), 0 , 181, 0 , 424, 145), // #1559 + INST(Vrsqrtps , VexRm_Lx , V(000F00,52,_,x,I,_,_,_ ), 0 , 74 , 0 , 302, 146), // #1560 + INST(Vrsqrtsh , VexRvm , E(66MAP6,4F,_,_,_,0,1,T1S), 0 , 183, 0 , 425, 145), // #1561 + INST(Vrsqrtss , VexRvm , V(F30F00,52,_,I,I,_,_,_ ), 0 , 193, 0 , 426, 146), // #1562 + INST(Vscalefpd , VexRvm_Lx , E(660F38,2C,_,x,_,1,4,FV ), 0 , 112, 0 , 432, 149), // #1563 + INST(Vscalefph , VexRvm_Lx , E(66MAP6,2C,_,_,_,0,4,FV ), 0 , 181, 0 , 201, 145), // #1564 + INST(Vscalefps , VexRvm_Lx , E(660F38,2C,_,x,_,0,4,FV ), 0 , 113, 0 , 288, 149), // #1565 + INST(Vscalefsd , VexRvm , E(660F38,2D,_,I,_,1,3,T1S), 0 , 127, 0 , 257, 149), // #1566 + INST(Vscalefsh , VexRvm , E(66MAP6,2D,_,_,_,0,1,T1S), 0 , 183, 0 , 204, 145), // #1567 + INST(Vscalefss , VexRvm , E(660F38,2D,_,I,_,0,2,T1S), 0 , 128, 0 , 265, 149), // #1568 + INST(Vscatterdpd , VexMr_VM , E(660F38,A2,_,x,_,1,3,T1S), 0 , 127, 0 , 405, 149), // #1569 + INST(Vscatterdps , VexMr_VM , E(660F38,A2,_,x,_,0,2,T1S), 0 , 128, 0 , 404, 149), // #1570 + INST(Vscatterqpd , VexMr_VM , E(660F38,A3,_,x,_,1,3,T1S), 0 , 127, 0 , 407, 149), // #1571 + INST(Vscatterqps , VexMr_VM , E(660F38,A3,_,x,_,0,2,T1S), 0 , 128, 0 , 406, 149), // #1572 + INST(Vsha512msg1 , VexRm , V(F20F38,CC,_,1,0,_,_,_ ), 0 , 224, 0 , 433, 187), // #1573 + INST(Vsha512msg2 , VexRm , V(F20F38,CD,_,1,0,_,_,_ ), 0 , 224, 0 , 434, 187), // #1574 + INST(Vsha512rnds2 , VexRvm , V(F20F38,CB,_,1,0,_,_,_ ), 0 , 224, 0 , 435, 187), // #1575 + INST(Vshuff32x4 , VexRvmi_Lx , E(660F3A,23,_,x,_,0,4,FV ), 0 , 110, 0 , 436, 149), // #1576 + INST(Vshuff64x2 , VexRvmi_Lx , E(660F3A,23,_,x,_,1,4,FV ), 0 , 111, 0 , 437, 149), // #1577 + INST(Vshufi32x4 , VexRvmi_Lx , E(660F3A,43,_,x,_,0,4,FV ), 0 , 110, 0 , 436, 149), // #1578 + INST(Vshufi64x2 , VexRvmi_Lx , E(660F3A,43,_,x,_,1,4,FV ), 0 , 111, 0 , 437, 149), // #1579 + INST(Vshufpd , VexRvmi_Lx , V(660F00,C6,_,x,I,1,4,FV ), 0 , 102, 0 , 438, 144), // #1580 + INST(Vshufps , VexRvmi_Lx , V(000F00,C6,_,x,I,0,4,FV ), 0 , 104, 0 , 439, 144), // #1581 + INST(Vsm3msg1 , VexRvm , V(000F38,DA,_,0,0,_,_,_ ), 0 , 11 , 0 , 440, 188), // #1582 + INST(Vsm3msg2 , VexRvm , V(660F38,DA,_,0,0,_,_,_ ), 0 , 30 , 0 , 440, 188), // #1583 + INST(Vsm3rnds2 , VexRvmi , V(660F3A,DE,_,0,0,_,_,_ ), 0 , 75 , 0 , 282, 188), // #1584 + INST(Vsm4key4 , VexRvm_Lx , V(F30F38,DA,_,x,0,_,_,_ ), 0 , 89 , 0 , 206, 189), // #1585 + INST(Vsm4rnds4 , VexRvm_Lx , V(F20F38,DA,_,x,0,_,_,_ ), 0 , 85 , 0 , 206, 189), // #1586 + INST(Vsqrtpd , VexRm_Lx , V(660F00,51,_,x,I,1,4,FV ), 0 , 102, 0 , 441, 144), // #1587 + INST(Vsqrtph , VexRm_Lx , E(00MAP5,51,_,_,_,0,4,FV ), 0 , 103, 0 , 252, 145), // #1588 + INST(Vsqrtps , VexRm_Lx , V(000F00,51,_,x,I,0,4,FV ), 0 , 104, 0 , 240, 144), // #1589 + INST(Vsqrtsd , VexRvm , V(F20F00,51,_,I,I,1,3,T1S), 0 , 105, 0 , 203, 144), // #1590 + INST(Vsqrtsh , VexRvm , E(F3MAP5,51,_,_,_,0,1,T1S), 0 , 106, 0 , 204, 145), // #1591 + INST(Vsqrtss , VexRvm , V(F30F00,51,_,I,I,0,2,T1S), 0 , 107, 0 , 205, 144), // #1592 + INST(Vstmxcsr , VexM , V(000F00,AE,3,0,I,_,_,_ ), 0 , 225, 0 , 321, 146), // #1593 + INST(Vsubpd , VexRvm_Lx , V(660F00,5C,_,x,I,1,4,FV ), 0 , 102, 0 , 200, 144), // #1594 + INST(Vsubph , VexRvm_Lx , E(00MAP5,5C,_,_,_,0,4,FV ), 0 , 103, 0 , 201, 145), // #1595 + INST(Vsubps , VexRvm_Lx , V(000F00,5C,_,x,I,0,4,FV ), 0 , 104, 0 , 202, 144), // #1596 + INST(Vsubsd , VexRvm , V(F20F00,5C,_,I,I,1,3,T1S), 0 , 105, 0 , 203, 144), // #1597 + INST(Vsubsh , VexRvm , E(F3MAP5,5C,_,_,_,0,1,T1S), 0 , 106, 0 , 204, 145), // #1598 + INST(Vsubss , VexRvm , V(F30F00,5C,_,I,I,0,2,T1S), 0 , 107, 0 , 205, 144), // #1599 + INST(Vtestpd , VexRm_Lx , V(660F38,0F,_,x,0,_,_,_ ), 0 , 30 , 0 , 302, 177), // #1600 + INST(Vtestps , VexRm_Lx , V(660F38,0E,_,x,0,_,_,_ ), 0 , 30 , 0 , 302, 177), // #1601 + INST(Vucomisd , VexRm , V(660F00,2E,_,I,I,1,3,T1S), 0 , 124, 0 , 234, 155), // #1602 + INST(Vucomish , VexRm , E(00MAP5,2E,_,_,_,0,1,T1S), 0 , 125, 0 , 235, 156), // #1603 + INST(Vucomiss , VexRm , V(000F00,2E,_,I,I,0,2,T1S), 0 , 126, 0 , 236, 155), // #1604 + INST(Vunpckhpd , VexRvm_Lx , V(660F00,15,_,x,I,1,4,FV ), 0 , 102, 0 , 212, 144), // #1605 + INST(Vunpckhps , VexRvm_Lx , V(000F00,15,_,x,I,0,4,FV ), 0 , 104, 0 , 213, 144), // #1606 + INST(Vunpcklpd , VexRvm_Lx , V(660F00,14,_,x,I,1,4,FV ), 0 , 102, 0 , 212, 144), // #1607 + INST(Vunpcklps , VexRvm_Lx , V(000F00,14,_,x,I,0,4,FV ), 0 , 104, 0 , 213, 144), // #1608 + INST(Vxorpd , VexRvm_Lx , V(660F00,57,_,x,I,1,4,FV ), 0 , 102, 0 , 419, 150), // #1609 + INST(Vxorps , VexRvm_Lx , V(000F00,57,_,x,I,0,4,FV ), 0 , 104, 0 , 418, 150), // #1610 + INST(Vzeroall , VexOp , V(000F00,77,_,1,I,_,_,_ ), 0 , 70 , 0 , 442, 146), // #1611 + INST(Vzeroupper , VexOp , V(000F00,77,_,0,I,_,_,_ ), 0 , 74 , 0 , 442, 146), // #1612 + INST(Wbinvd , X86Op , O(000F00,09,_,_,_,_,_,_ ), 0 , 5 , 0 , 31 , 45 ), // #1613 + INST(Wbnoinvd , X86Op , O(F30F00,09,_,_,_,_,_,_ ), 0 , 7 , 0 , 31 , 190), // #1614 + INST(Wrfsbase , X86M , O(F30F00,AE,2,_,x,_,_,_ ), 0 , 226, 0 , 178, 122), // #1615 + INST(Wrgsbase , X86M , O(F30F00,AE,3,_,x,_,_,_ ), 0 , 227, 0 , 178, 122), // #1616 + INST(Wrmsr , X86Op , O(000F00,30,_,_,_,_,_,_ ), 0 , 5 , 0 , 181, 191), // #1617 + INST(Wrssd , X86Mr , O(000F38,F6,_,_,_,_,_,_ ), 0 , 1 , 0 , 443, 65 ), // #1618 + INST(Wrssq , X86Mr , O(000F38,F6,_,_,1,_,_,_ ), 0 , 228, 0 , 444, 65 ), // #1619 + INST(Wrussd , X86Mr , O(660F38,F5,_,_,_,_,_,_ ), 0 , 2 , 0 , 443, 65 ), // #1620 + INST(Wrussq , X86Mr , O(660F38,F5,_,_,1,_,_,_ ), 0 , 229, 0 , 444, 65 ), // #1621 + INST(Xabort , X86Op_Mod11RM_I8 , O(000000,C6,7,_,_,_,_,_ ), 0 , 29 , 0 , 83 , 192), // #1622 + INST(Xadd , X86Xadd , O(000F00,C0,_,_,x,_,_,_ ), 0 , 5 , 0 , 445, 40 ), // #1623 + INST(Xbegin , X86JmpRel , O(000000,C7,7,_,_,_,_,_ ), 0 , 29 , 0 , 446, 192), // #1624 + INST(Xchg , X86Xchg , O(000000,86,_,_,x,_,_,_ ), 0 , 0 , 0 , 447, 0 ), // #1625 + INST(Xend , X86Op , O(000F01,D5,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 192), // #1626 + INST(Xgetbv , X86Op , O(000F01,D0,_,_,_,_,_,_ ), 0 , 23 , 0 , 181, 193), // #1627 + INST(Xlatb , X86Op , O(000000,D7,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 0 ), // #1628 + INST(Xor , X86Arith , O(000000,30,6,_,x,_,_,_ ), 0 , 34 , 0 , 185, 1 ), // #1629 + INST(Xorpd , ExtRm , O(660F00,57,_,_,_,_,_,_ ), 0 , 4 , 0 , 155, 5 ), // #1630 + INST(Xorps , ExtRm , O(000F00,57,_,_,_,_,_,_ ), 0 , 5 , 0 , 155, 6 ), // #1631 + INST(Xresldtrk , X86Op , O(F20F01,E9,_,_,_,_,_,_ ), 0 , 93 , 0 , 31 , 194), // #1632 + INST(Xrstor , X86M_Only_EDX_EAX , O(000F00,AE,5,_,_,_,_,_ ), 0 , 79 , 0 , 448, 193), // #1633 + INST(Xrstor64 , X86M_Only_EDX_EAX , O(000F00,AE,5,_,1,_,_,_ ), 0 , 230, 0 , 449, 193), // #1634 + INST(Xrstors , X86M_Only_EDX_EAX , O(000F00,C7,3,_,_,_,_,_ ), 0 , 80 , 0 , 448, 195), // #1635 + INST(Xrstors64 , X86M_Only_EDX_EAX , O(000F00,C7,3,_,1,_,_,_ ), 0 , 231, 0 , 449, 195), // #1636 + INST(Xsave , X86M_Only_EDX_EAX , O(000F00,AE,4,_,_,_,_,_ ), 0 , 98 , 0 , 448, 193), // #1637 + INST(Xsave64 , X86M_Only_EDX_EAX , O(000F00,AE,4,_,1,_,_,_ ), 0 , 232, 0 , 449, 193), // #1638 + INST(Xsavec , X86M_Only_EDX_EAX , O(000F00,C7,4,_,_,_,_,_ ), 0 , 98 , 0 , 448, 196), // #1639 + INST(Xsavec64 , X86M_Only_EDX_EAX , O(000F00,C7,4,_,1,_,_,_ ), 0 , 232, 0 , 449, 196), // #1640 + INST(Xsaveopt , X86M_Only_EDX_EAX , O(000F00,AE,6,_,_,_,_,_ ), 0 , 82 , 0 , 448, 197), // #1641 + INST(Xsaveopt64 , X86M_Only_EDX_EAX , O(000F00,AE,6,_,1,_,_,_ ), 0 , 233, 0 , 449, 197), // #1642 + INST(Xsaves , X86M_Only_EDX_EAX , O(000F00,C7,5,_,_,_,_,_ ), 0 , 79 , 0 , 448, 195), // #1643 + INST(Xsaves64 , X86M_Only_EDX_EAX , O(000F00,C7,5,_,1,_,_,_ ), 0 , 230, 0 , 449, 195), // #1644 + INST(Xsetbv , X86Op , O(000F01,D1,_,_,_,_,_,_ ), 0 , 23 , 0 , 181, 193), // #1645 + INST(Xsusldtrk , X86Op , O(F20F01,E8,_,_,_,_,_,_ ), 0 , 93 , 0 , 31 , 194), // #1646 + INST(Xtest , X86Op , O(000F01,D6,_,_,_,_,_,_ ), 0 , 23 , 0 , 31 , 198) // #1647 // ${InstInfo:End} }; #undef NAME_DATA_INDEX @@ -1785,12 +1710,12 @@ const uint32_t InstDB::_mainOpcodeTable[] = { O(660F38,00,0,0,0,0,0,0 ), // #2 [ref=44x] O(000000,00,2,0,0,0,0,0 ), // #3 [ref=4x] O(660F00,00,0,0,0,0,0,0 ), // #4 [ref=38x] - O(000F00,00,0,0,0,0,0,0 ), // #5 [ref=231x] + O(000F00,00,0,0,0,0,0,0 ), // #5 [ref=189x] O(F20F00,00,0,0,0,0,0,0 ), // #6 [ref=24x] O(F30F00,00,0,0,0,0,0,0 ), // #7 [ref=29x] O(F30F38,00,0,0,0,0,0,0 ), // #8 [ref=3x] O(660F3A,00,0,0,0,0,0,0 ), // #9 [ref=22x] - O(000000,00,4,0,0,0,0,0 ), // #10 [ref=5x] + O(000000,00,4,0,0,0,0,0 ), // #10 [ref=4x] V(000F38,00,0,0,0,0,0,None), // #11 [ref=13x] O(F20F38,00,0,0,0,0,0,0 ), // #12 [ref=3x] V(XOP_M9,00,1,0,0,0,0,None), // #13 [ref=3x] @@ -1882,150 +1807,138 @@ const uint32_t InstDB::_mainOpcodeTable[] = { V(XOP_M9,00,7,0,0,0,0,None), // #99 [ref=1x] V(XOP_M9,00,4,0,0,0,0,None), // #100 [ref=1x] O(F20F00,00,6,0,0,0,0,0 ), // #101 [ref=1x] - E(F20F38,00,0,2,0,0,4,None), // #102 [ref=4x] - E(F20F38,00,0,0,0,0,4,None), // #103 [ref=2x] - V(660F00,00,0,0,0,1,4,ByLL), // #104 [ref=25x] - E(00MAP5,00,0,0,0,0,4,ByLL), // #105 [ref=10x] - V(000F00,00,0,0,0,0,4,ByLL), // #106 [ref=19x] - V(F20F00,00,0,0,0,1,3,None), // #107 [ref=10x] - E(F3MAP5,00,0,0,0,0,1,None), // #108 [ref=13x] - V(F30F00,00,0,0,0,0,2,None), // #109 [ref=12x] - V(F20F00,00,0,0,0,0,0,None), // #110 [ref=4x] - V(660F38,00,0,0,0,0,4,ByLL), // #111 [ref=50x] - E(660F3A,00,0,0,0,0,4,ByLL), // #112 [ref=17x] - E(660F3A,00,0,0,0,1,4,ByLL), // #113 [ref=18x] - E(660F38,00,0,0,0,1,4,ByLL), // #114 [ref=38x] - E(660F38,00,0,0,0,0,4,ByLL), // #115 [ref=25x] - V(660F38,00,0,1,0,0,0,None), // #116 [ref=2x] - E(660F38,00,0,0,0,0,3,None), // #117 [ref=2x] - E(660F38,00,0,0,0,0,4,None), // #118 [ref=2x] - E(660F38,00,0,2,0,0,5,None), // #119 [ref=2x] - E(660F38,00,0,0,0,1,4,None), // #120 [ref=2x] - E(660F38,00,0,2,0,1,5,None), // #121 [ref=2x] - V(660F38,00,0,0,0,1,3,None), // #122 [ref=2x] - V(660F38,00,0,0,0,0,2,None), // #123 [ref=14x] - E(000F3A,00,0,0,0,0,4,ByLL), // #124 [ref=5x] - E(F30F3A,00,0,0,0,0,1,None), // #125 [ref=1x] - V(660F00,00,0,0,0,1,3,None), // #126 [ref=5x] - E(00MAP5,00,0,0,0,0,1,None), // #127 [ref=2x] - V(000F00,00,0,0,0,0,2,None), // #128 [ref=2x] - E(660F38,00,0,0,0,1,3,None), // #129 [ref=14x] - E(660F38,00,0,0,0,0,2,None), // #130 [ref=14x] - V(F30F00,00,0,0,0,0,3,ByLL), // #131 [ref=1x] - E(F20F38,00,0,0,0,0,4,ByLL), // #132 [ref=2x] - V(F30F38,00,0,0,0,0,4,ByLL), // #133 [ref=1x] - V(F20F00,00,0,0,0,1,4,ByLL), // #134 [ref=1x] - E(66MAP5,00,0,0,0,1,4,ByLL), // #135 [ref=1x] - E(660F00,00,0,0,0,1,4,ByLL), // #136 [ref=10x] - E(000F00,00,0,0,0,1,4,ByLL), // #137 [ref=3x] - E(66MAP5,00,0,0,0,0,3,ByLL), // #138 [ref=1x] - E(00MAP5,00,0,0,0,0,2,ByLL), // #139 [ref=1x] - V(660F38,00,0,0,0,0,3,ByLL), // #140 [ref=7x] - E(66MAP6,00,0,0,0,0,3,ByLL), // #141 [ref=1x] - E(66MAP5,00,0,0,0,0,2,ByLL), // #142 [ref=4x] - E(00MAP5,00,0,0,0,0,3,ByLL), // #143 [ref=2x] - E(66MAP5,00,0,0,0,0,4,ByLL), // #144 [ref=3x] - V(660F00,00,0,0,0,0,4,ByLL), // #145 [ref=43x] - V(000F00,00,0,0,0,0,3,ByLL), // #146 [ref=1x] - V(660F3A,00,0,0,0,0,3,ByLL), // #147 [ref=1x] - E(660F00,00,0,0,0,0,3,ByLL), // #148 [ref=4x] - E(000F00,00,0,0,0,0,4,ByLL), // #149 [ref=2x] - E(F30F00,00,0,0,0,1,4,ByLL), // #150 [ref=3x] - E(00MAP5,00,0,0,0,1,4,ByLL), // #151 [ref=1x] - E(F2MAP5,00,0,0,0,1,3,None), // #152 [ref=1x] - V(F20F00,00,0,0,0,0,3,None), // #153 [ref=2x] - E(F20F00,00,0,0,0,0,3,None), // #154 [ref=2x] - E(00MAP6,00,0,0,0,0,1,None), // #155 [ref=1x] - V(F20F00,00,0,0,0,0,2,T1W ), // #156 [ref=1x] - E(F3MAP5,00,0,0,0,0,2,T1W ), // #157 [ref=2x] - V(F30F00,00,0,0,0,0,2,T1W ), // #158 [ref=1x] - E(00MAP5,00,0,0,0,0,2,None), // #159 [ref=1x] - E(F30F00,00,0,0,0,0,2,None), // #160 [ref=2x] - E(F3MAP5,00,0,0,0,0,3,ByLL), // #161 [ref=1x] - V(F30F00,00,0,0,0,0,4,ByLL), // #162 [ref=4x] - E(F30F00,00,0,0,0,0,3,ByLL), // #163 [ref=1x] - E(F2MAP5,00,0,0,0,0,4,ByLL), // #164 [ref=2x] - E(F20F00,00,0,0,0,0,4,ByLL), // #165 [ref=2x] - E(F2MAP5,00,0,0,0,1,4,ByLL), // #166 [ref=1x] - E(F20F00,00,0,0,0,1,4,ByLL), // #167 [ref=2x] - E(F20F00,00,0,0,0,0,2,T1W ), // #168 [ref=1x] - E(F30F00,00,0,0,0,0,2,T1W ), // #169 [ref=1x] - E(F3MAP5,00,0,0,0,0,4,ByLL), // #170 [ref=1x] - E(F30F38,00,0,0,0,0,4,ByLL), // #171 [ref=3x] - E(660F38,00,0,2,0,1,4,ByLL), // #172 [ref=3x] - E(660F38,00,0,2,0,0,4,ByLL), // #173 [ref=3x] - V(660F3A,00,0,1,0,0,0,None), // #174 [ref=6x] - E(660F3A,00,0,0,0,0,4,None), // #175 [ref=4x] - E(660F3A,00,0,2,0,0,5,None), // #176 [ref=4x] - E(660F3A,00,0,0,0,1,4,None), // #177 [ref=4x] - E(660F3A,00,0,2,0,1,5,None), // #178 [ref=4x] - V(660F3A,00,0,0,0,0,2,None), // #179 [ref=4x] - E(F2MAP6,00,0,0,0,0,4,ByLL), // #180 [ref=2x] - E(F2MAP6,00,0,0,0,0,2,None), // #181 [ref=2x] - E(660F3A,00,0,0,0,1,3,None), // #182 [ref=6x] - E(660F3A,00,0,0,0,0,2,None), // #183 [ref=6x] - V(660F38,00,0,0,1,1,4,ByLL), // #184 [ref=22x] - E(66MAP6,00,0,0,0,0,4,ByLL), // #185 [ref=22x] - V(660F38,00,0,0,1,1,3,None), // #186 [ref=12x] - E(66MAP6,00,0,0,0,0,1,None), // #187 [ref=16x] - E(F3MAP6,00,0,0,0,0,4,ByLL), // #188 [ref=2x] - E(F3MAP6,00,0,0,0,0,2,None), // #189 [ref=2x] - E(000F3A,00,0,0,0,0,1,None), // #190 [ref=4x] - V(660F38,00,0,0,1,0,0,None), // #191 [ref=5x] - E(660F38,00,1,2,0,1,3,None), // #192 [ref=2x] - E(660F38,00,1,2,0,0,2,None), // #193 [ref=2x] - E(660F38,00,2,2,0,1,3,None), // #194 [ref=2x] - E(660F38,00,2,2,0,0,2,None), // #195 [ref=2x] - V(660F3A,00,0,0,1,1,4,ByLL), // #196 [ref=2x] - V(000F00,00,2,0,0,0,0,None), // #197 [ref=1x] - V(660F00,00,0,0,0,0,2,None), // #198 [ref=1x] - V(F20F00,00,0,0,0,1,3,DUP ), // #199 [ref=1x] - E(660F00,00,0,0,0,0,4,ByLL), // #200 [ref=6x] - V(F30F00,00,0,0,0,0,0,None), // #201 [ref=3x] - E(F30F00,00,0,0,0,0,4,ByLL), // #202 [ref=1x] - V(000F00,00,0,0,0,0,3,None), // #203 [ref=2x] - E(66MAP5,00,0,0,0,0,1,None), // #204 [ref=1x] - E(F20F38,00,0,0,0,1,4,ByLL), // #205 [ref=1x] - V(660F3A,00,0,0,0,0,4,ByLL), // #206 [ref=2x] - E(F30F38,00,0,0,0,1,0,None), // #207 [ref=5x] - E(F30F38,00,0,0,0,0,0,None), // #208 [ref=5x] - V(660F38,00,0,0,0,0,1,None), // #209 [ref=1x] - V(XOP_M8,00,0,0,0,0,0,None), // #210 [ref=22x] - V(660F38,00,0,0,0,1,4,ByLL), // #211 [ref=4x] - E(660F38,00,0,0,0,0,0,None), // #212 [ref=2x] - E(660F38,00,0,0,0,1,1,None), // #213 [ref=2x] - E(660F38,00,0,0,1,1,4,ByLL), // #214 [ref=1x] - V(660F3A,00,0,0,1,1,3,None), // #215 [ref=2x] - V(660F3A,00,0,0,0,0,1,None), // #216 [ref=1x] - V(660F00,00,0,0,0,0,1,None), // #217 [ref=1x] - E(F30F38,00,0,0,0,0,2,ByLL), // #218 [ref=6x] - E(F30F38,00,0,0,0,0,3,ByLL), // #219 [ref=9x] - E(F30F38,00,0,0,0,0,1,ByLL), // #220 [ref=3x] - V(660F38,00,0,0,0,0,2,ByLL), // #221 [ref=4x] - V(660F38,00,0,0,0,0,1,ByLL), // #222 [ref=2x] - E(660F00,00,1,0,0,0,4,ByLL), // #223 [ref=1x] - E(660F00,00,1,0,0,1,4,ByLL), // #224 [ref=1x] - V(F20F00,00,0,0,0,0,4,ByLL), // #225 [ref=1x] - V(660F00,00,0,0,0,0,4,None), // #226 [ref=6x] - V(660F00,00,7,0,0,0,4,ByLL), // #227 [ref=1x] - V(660F00,00,0,0,0,1,4,None), // #228 [ref=2x] - E(660F00,00,0,0,0,1,4,None), // #229 [ref=1x] - V(660F00,00,3,0,0,0,4,ByLL), // #230 [ref=1x] - E(F30F38,00,0,0,0,1,4,ByLL), // #231 [ref=2x] - E(660F38,00,5,2,0,1,3,None), // #232 [ref=2x] - E(660F38,00,5,2,0,0,2,None), // #233 [ref=2x] - E(660F38,00,6,2,0,1,3,None), // #234 [ref=2x] - E(660F38,00,6,2,0,0,2,None), // #235 [ref=2x] - V(F20F38,00,0,1,0,0,0,None), // #236 [ref=3x] - V(000F00,00,3,0,0,0,0,None), // #237 [ref=1x] - O(F30F00,00,2,0,0,0,0,0 ), // #238 [ref=1x] - O(F30F00,00,3,0,0,0,0,0 ), // #239 [ref=1x] - O(000F38,00,0,0,1,0,0,0 ), // #240 [ref=1x] - O(660F38,00,0,0,1,0,0,0 ), // #241 [ref=1x] - O(000F00,00,5,0,1,0,0,0 ), // #242 [ref=2x] - O(000F00,00,3,0,1,0,0,0 ), // #243 [ref=1x] - O(000F00,00,4,0,1,0,0,0 ), // #244 [ref=2x] - O(000F00,00,6,0,1,0,0,0 ) // #245 [ref=1x] + V(660F00,00,0,0,0,1,4,ByLL), // #102 [ref=25x] + E(00MAP5,00,0,0,0,0,4,ByLL), // #103 [ref=10x] + V(000F00,00,0,0,0,0,4,ByLL), // #104 [ref=19x] + V(F20F00,00,0,0,0,1,3,None), // #105 [ref=10x] + E(F3MAP5,00,0,0,0,0,1,None), // #106 [ref=13x] + V(F30F00,00,0,0,0,0,2,None), // #107 [ref=12x] + V(F20F00,00,0,0,0,0,0,None), // #108 [ref=4x] + V(660F38,00,0,0,0,0,4,ByLL), // #109 [ref=50x] + E(660F3A,00,0,0,0,0,4,ByLL), // #110 [ref=17x] + E(660F3A,00,0,0,0,1,4,ByLL), // #111 [ref=18x] + E(660F38,00,0,0,0,1,4,ByLL), // #112 [ref=38x] + E(660F38,00,0,0,0,0,4,ByLL), // #113 [ref=25x] + V(660F38,00,0,1,0,0,0,None), // #114 [ref=2x] + E(660F38,00,0,0,0,0,3,None), // #115 [ref=2x] + E(660F38,00,0,0,0,0,4,None), // #116 [ref=2x] + E(660F38,00,0,2,0,0,5,None), // #117 [ref=2x] + E(660F38,00,0,0,0,1,4,None), // #118 [ref=2x] + E(660F38,00,0,2,0,1,5,None), // #119 [ref=2x] + V(660F38,00,0,0,0,1,3,None), // #120 [ref=2x] + V(660F38,00,0,0,0,0,2,None), // #121 [ref=14x] + E(000F3A,00,0,0,0,0,4,ByLL), // #122 [ref=5x] + E(F30F3A,00,0,0,0,0,1,None), // #123 [ref=1x] + V(660F00,00,0,0,0,1,3,None), // #124 [ref=5x] + E(00MAP5,00,0,0,0,0,1,None), // #125 [ref=2x] + V(000F00,00,0,0,0,0,2,None), // #126 [ref=2x] + E(660F38,00,0,0,0,1,3,None), // #127 [ref=12x] + E(660F38,00,0,0,0,0,2,None), // #128 [ref=12x] + V(F30F00,00,0,0,0,0,3,ByLL), // #129 [ref=1x] + E(F20F38,00,0,0,0,0,4,ByLL), // #130 [ref=2x] + V(F30F38,00,0,0,0,0,4,ByLL), // #131 [ref=1x] + V(F20F00,00,0,0,0,1,4,ByLL), // #132 [ref=1x] + E(66MAP5,00,0,0,0,1,4,ByLL), // #133 [ref=1x] + E(660F00,00,0,0,0,1,4,ByLL), // #134 [ref=10x] + E(000F00,00,0,0,0,1,4,ByLL), // #135 [ref=3x] + E(66MAP5,00,0,0,0,0,3,ByLL), // #136 [ref=1x] + E(00MAP5,00,0,0,0,0,2,ByLL), // #137 [ref=1x] + V(660F38,00,0,0,0,0,3,ByLL), // #138 [ref=7x] + E(66MAP6,00,0,0,0,0,3,ByLL), // #139 [ref=1x] + E(66MAP5,00,0,0,0,0,2,ByLL), // #140 [ref=4x] + E(00MAP5,00,0,0,0,0,3,ByLL), // #141 [ref=2x] + E(66MAP5,00,0,0,0,0,4,ByLL), // #142 [ref=3x] + V(660F00,00,0,0,0,0,4,ByLL), // #143 [ref=43x] + V(000F00,00,0,0,0,0,3,ByLL), // #144 [ref=1x] + V(660F3A,00,0,0,0,0,3,ByLL), // #145 [ref=1x] + E(660F00,00,0,0,0,0,3,ByLL), // #146 [ref=4x] + E(000F00,00,0,0,0,0,4,ByLL), // #147 [ref=2x] + E(F30F00,00,0,0,0,1,4,ByLL), // #148 [ref=3x] + E(00MAP5,00,0,0,0,1,4,ByLL), // #149 [ref=1x] + E(F2MAP5,00,0,0,0,1,3,None), // #150 [ref=1x] + V(F20F00,00,0,0,0,0,3,None), // #151 [ref=2x] + E(F20F00,00,0,0,0,0,3,None), // #152 [ref=2x] + E(00MAP6,00,0,0,0,0,1,None), // #153 [ref=1x] + V(F20F00,00,0,0,0,0,2,T1W ), // #154 [ref=1x] + E(F3MAP5,00,0,0,0,0,2,T1W ), // #155 [ref=2x] + V(F30F00,00,0,0,0,0,2,T1W ), // #156 [ref=1x] + E(00MAP5,00,0,0,0,0,2,None), // #157 [ref=1x] + E(F30F00,00,0,0,0,0,2,None), // #158 [ref=2x] + E(F3MAP5,00,0,0,0,0,3,ByLL), // #159 [ref=1x] + V(F30F00,00,0,0,0,0,4,ByLL), // #160 [ref=4x] + E(F30F00,00,0,0,0,0,3,ByLL), // #161 [ref=1x] + E(F2MAP5,00,0,0,0,0,4,ByLL), // #162 [ref=2x] + E(F20F00,00,0,0,0,0,4,ByLL), // #163 [ref=2x] + E(F2MAP5,00,0,0,0,1,4,ByLL), // #164 [ref=1x] + E(F20F00,00,0,0,0,1,4,ByLL), // #165 [ref=2x] + E(F20F00,00,0,0,0,0,2,T1W ), // #166 [ref=1x] + E(F30F00,00,0,0,0,0,2,T1W ), // #167 [ref=1x] + E(F3MAP5,00,0,0,0,0,4,ByLL), // #168 [ref=1x] + E(F30F38,00,0,0,0,0,4,ByLL), // #169 [ref=3x] + V(660F3A,00,0,1,0,0,0,None), // #170 [ref=6x] + E(660F3A,00,0,0,0,0,4,None), // #171 [ref=4x] + E(660F3A,00,0,2,0,0,5,None), // #172 [ref=4x] + E(660F3A,00,0,0,0,1,4,None), // #173 [ref=4x] + E(660F3A,00,0,2,0,1,5,None), // #174 [ref=4x] + V(660F3A,00,0,0,0,0,2,None), // #175 [ref=4x] + E(F2MAP6,00,0,0,0,0,4,ByLL), // #176 [ref=2x] + E(F2MAP6,00,0,0,0,0,2,None), // #177 [ref=2x] + E(660F3A,00,0,0,0,1,3,None), // #178 [ref=6x] + E(660F3A,00,0,0,0,0,2,None), // #179 [ref=6x] + V(660F38,00,0,0,1,1,4,ByLL), // #180 [ref=22x] + E(66MAP6,00,0,0,0,0,4,ByLL), // #181 [ref=22x] + V(660F38,00,0,0,1,1,3,None), // #182 [ref=12x] + E(66MAP6,00,0,0,0,0,1,None), // #183 [ref=16x] + E(F3MAP6,00,0,0,0,0,4,ByLL), // #184 [ref=2x] + E(F3MAP6,00,0,0,0,0,2,None), // #185 [ref=2x] + E(000F3A,00,0,0,0,0,1,None), // #186 [ref=4x] + V(660F38,00,0,0,1,0,0,None), // #187 [ref=5x] + V(660F3A,00,0,0,1,1,4,ByLL), // #188 [ref=2x] + V(000F00,00,2,0,0,0,0,None), // #189 [ref=1x] + V(660F00,00,0,0,0,0,2,None), // #190 [ref=1x] + V(F20F00,00,0,0,0,1,3,DUP ), // #191 [ref=1x] + E(660F00,00,0,0,0,0,4,ByLL), // #192 [ref=6x] + V(F30F00,00,0,0,0,0,0,None), // #193 [ref=3x] + E(F30F00,00,0,0,0,0,4,ByLL), // #194 [ref=1x] + V(000F00,00,0,0,0,0,3,None), // #195 [ref=2x] + E(66MAP5,00,0,0,0,0,1,None), // #196 [ref=1x] + E(F20F38,00,0,0,0,1,4,ByLL), // #197 [ref=1x] + V(660F3A,00,0,0,0,0,4,ByLL), // #198 [ref=2x] + E(F30F38,00,0,0,0,1,0,None), // #199 [ref=5x] + E(F30F38,00,0,0,0,0,0,None), // #200 [ref=5x] + V(660F38,00,0,0,0,0,1,None), // #201 [ref=1x] + V(XOP_M8,00,0,0,0,0,0,None), // #202 [ref=22x] + V(660F38,00,0,0,0,1,4,ByLL), // #203 [ref=4x] + E(660F38,00,0,0,0,0,0,None), // #204 [ref=2x] + E(660F38,00,0,0,0,1,1,None), // #205 [ref=2x] + E(660F38,00,0,0,1,1,4,ByLL), // #206 [ref=1x] + V(660F3A,00,0,0,1,1,3,None), // #207 [ref=2x] + V(660F3A,00,0,0,0,0,1,None), // #208 [ref=1x] + V(660F00,00,0,0,0,0,1,None), // #209 [ref=1x] + E(F30F38,00,0,0,0,0,2,ByLL), // #210 [ref=6x] + E(F30F38,00,0,0,0,0,3,ByLL), // #211 [ref=9x] + E(F30F38,00,0,0,0,0,1,ByLL), // #212 [ref=3x] + V(660F38,00,0,0,0,0,2,ByLL), // #213 [ref=4x] + V(660F38,00,0,0,0,0,1,ByLL), // #214 [ref=2x] + E(660F00,00,1,0,0,0,4,ByLL), // #215 [ref=1x] + E(660F00,00,1,0,0,1,4,ByLL), // #216 [ref=1x] + V(F20F00,00,0,0,0,0,4,ByLL), // #217 [ref=1x] + V(660F00,00,0,0,0,0,4,None), // #218 [ref=6x] + V(660F00,00,7,0,0,0,4,ByLL), // #219 [ref=1x] + V(660F00,00,0,0,0,1,4,None), // #220 [ref=2x] + E(660F00,00,0,0,0,1,4,None), // #221 [ref=1x] + V(660F00,00,3,0,0,0,4,ByLL), // #222 [ref=1x] + E(F30F38,00,0,0,0,1,4,ByLL), // #223 [ref=2x] + V(F20F38,00,0,1,0,0,0,None), // #224 [ref=3x] + V(000F00,00,3,0,0,0,0,None), // #225 [ref=1x] + O(F30F00,00,2,0,0,0,0,0 ), // #226 [ref=1x] + O(F30F00,00,3,0,0,0,0,0 ), // #227 [ref=1x] + O(000F38,00,0,0,1,0,0,0 ), // #228 [ref=1x] + O(660F38,00,0,0,1,0,0,0 ), // #229 [ref=1x] + O(000F00,00,5,0,1,0,0,0 ), // #230 [ref=2x] + O(000F00,00,3,0,1,0,0,0 ), // #231 [ref=1x] + O(000F00,00,4,0,1,0,0,0 ), // #232 [ref=2x] + O(000F00,00,6,0,1,0,0,0 ) // #233 [ref=1x] }; // ---------------------------------------------------------------------------- // ${MainOpcodeTable:End} @@ -2033,7 +1946,7 @@ const uint32_t InstDB::_mainOpcodeTable[] = { // ${AltOpcodeTable:Begin} // ------------------- Automatically generated, do not edit ------------------- const uint32_t InstDB::_altOpcodeTable[] = { - O(000000,00,0,0,0,0,0,0 ), // #0 [ref=1573x] + O(000000,00,0,0,0,0,0,0 ), // #0 [ref=1512x] O(660F00,1B,0,0,0,0,0,0 ), // #1 [ref=1x] O(000F00,BA,4,0,0,0,0,0 ), // #2 [ref=1x] O(000F00,BA,7,0,0,0,0,0 ), // #3 [ref=1x] @@ -2051,24 +1964,24 @@ const uint32_t InstDB::_altOpcodeTable[] = { O(000000,E4,0,0,0,0,0,0 ), // #15 [ref=1x] O(000000,40,0,0,0,0,0,0 ), // #16 [ref=1x] O(F20F00,78,0,0,0,0,0,0 ), // #17 [ref=1x] - O(000000,77,0,0,0,0,0,0 ), // #18 [ref=2x] - O(000000,73,0,0,0,0,0,0 ), // #19 [ref=3x] - O(000000,72,0,0,0,0,0,0 ), // #20 [ref=3x] - O(000000,76,0,0,0,0,0,0 ), // #21 [ref=2x] - O(000000,74,0,0,0,0,0,0 ), // #22 [ref=2x] - O(000000,E3,0,0,0,0,0,0 ), // #23 [ref=1x] - O(000000,7F,0,0,0,0,0,0 ), // #24 [ref=2x] - O(000000,7D,0,0,0,0,0,0 ), // #25 [ref=2x] - O(000000,7C,0,0,0,0,0,0 ), // #26 [ref=2x] - O(000000,7E,0,0,0,0,0,0 ), // #27 [ref=2x] - O(000000,EB,0,0,0,0,0,0 ), // #28 [ref=1x] - O(000000,75,0,0,0,0,0,0 ), // #29 [ref=2x] - O(000000,71,0,0,0,0,0,0 ), // #30 [ref=1x] - O(000000,7B,0,0,0,0,0,0 ), // #31 [ref=2x] - O(000000,79,0,0,0,0,0,0 ), // #32 [ref=1x] - O(000000,70,0,0,0,0,0,0 ), // #33 [ref=1x] - O(000000,7A,0,0,0,0,0,0 ), // #34 [ref=2x] - O(000000,78,0,0,0,0,0,0 ), // #35 [ref=1x] + O(000000,72,0,0,0,0,0,0 ), // #18 [ref=1x] + O(000000,76,0,0,0,0,0,0 ), // #19 [ref=1x] + O(000000,E3,0,0,0,0,0,0 ), // #20 [ref=1x] + O(000000,7C,0,0,0,0,0,0 ), // #21 [ref=1x] + O(000000,7E,0,0,0,0,0,0 ), // #22 [ref=1x] + O(000000,EB,0,0,0,0,0,0 ), // #23 [ref=1x] + O(000000,73,0,0,0,0,0,0 ), // #24 [ref=1x] + O(000000,77,0,0,0,0,0,0 ), // #25 [ref=1x] + O(000000,7D,0,0,0,0,0,0 ), // #26 [ref=1x] + O(000000,7F,0,0,0,0,0,0 ), // #27 [ref=1x] + O(000000,71,0,0,0,0,0,0 ), // #28 [ref=1x] + O(000000,7B,0,0,0,0,0,0 ), // #29 [ref=1x] + O(000000,79,0,0,0,0,0,0 ), // #30 [ref=1x] + O(000000,75,0,0,0,0,0,0 ), // #31 [ref=1x] + O(000000,70,0,0,0,0,0,0 ), // #32 [ref=1x] + O(000000,7A,0,0,0,0,0,0 ), // #33 [ref=1x] + O(000000,78,0,0,0,0,0,0 ), // #34 [ref=1x] + O(000000,74,0,0,0,0,0,0 ), // #35 [ref=1x] V(660F00,92,0,0,0,0,0,None), // #36 [ref=1x] V(F20F00,92,0,0,0,0,0,None), // #37 [ref=1x] V(F20F00,92,0,0,1,0,0,None), // #38 [ref=1x] @@ -2188,461 +2101,455 @@ const uint32_t InstDB::_altOpcodeTable[] = { #define SAME_REG_HINT(VAL) uint8_t(InstSameRegHint::k##VAL) const InstDB::CommonInfo InstDB::_commonInfoTable[] = { { 0 , 0 , 0 , 0 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #0 [ref=1x] - { 0 , 0 , 455, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #1 [ref=4x] - { 0 , 0 , 456, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #2 [ref=2x] - { 0 , 0 , 108, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #3 [ref=6x] + { 0 , 0 , 488, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #1 [ref=4x] + { 0 , 0 , 489, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #2 [ref=2x] + { 0 , 0 , 143, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #3 [ref=6x] { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 20 , 13, CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #4 [ref=2x] - { 0 , 0 , 50 , 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #5 [ref=2x] - { F(Vec) , 0 , 72 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #6 [ref=54x] - { F(Vec) , 0 , 143, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #7 [ref=19x] - { F(Vec) , 0 , 283, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #8 [ref=16x] - { F(Vec) , 0 , 292, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #9 [ref=20x] - { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 33 , 12, CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #10 [ref=1x] - { F(Vex) , 0 , 325, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #11 [ref=3x] - { F(Vec) , 0 , 72 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #12 [ref=12x] - { 0 , 0 , 457, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #13 [ref=1x] - { F(Vex) , 0 , 327, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #14 [ref=5x] - { F(Vex) , 0 , 50 , 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #15 [ref=12x] - { F(Vec) , 0 , 458, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #16 [ref=4x] - { 0 , 0 , 329, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #17 [ref=3x] - { F(Mib) , 0 , 459, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #18 [ref=1x] - { 0 , 0 , 460, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #19 [ref=1x] - { 0 , 0 , 331, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #20 [ref=1x] - { F(Mib) , 0 , 461, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #21 [ref=1x] - { 0 , 0 , 333, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #22 [ref=1x] - { 0 , 0 , 49 , 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #23 [ref=35x] - { 0 , 0 , 335, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #24 [ref=3x] - { 0 , 0 , 134, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #25 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 134, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #26 [ref=3x] - { F(Rep)|F(RepIgnored) , 0 , 235, 3 , CONTROL_FLOW(Call), SAME_REG_HINT(None)}, // #27 [ref=1x] - { 0 , 0 , 462, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #28 [ref=1x] - { 0 , 0 , 463, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #29 [ref=2x] - { 0 , 0 , 436, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #30 [ref=1x] - { 0 , 0 , 110, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #31 [ref=88x] - { 0 , 0 , 464, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #32 [ref=24x] - { 0 , 0 , 465, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #33 [ref=6x] - { 0 , 0 , 466, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #34 [ref=14x] - { 0 , 0 , 467, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #35 [ref=1x] - { 0 , 0 , 20 , 13, CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #36 [ref=1x] - { F(Vex) , 0 , 337, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #37 [ref=16x] - { F(Rep) , 0 , 179, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #38 [ref=1x] - { F(Vec) , 0 , 468, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #39 [ref=2x] - { F(Vec) , 0 , 469, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #40 [ref=3x] - { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 183, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #41 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 470, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #42 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 471, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #43 [ref=1x] - { 0 , 0 , 472, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #44 [ref=1x] - { 0 , 0 , 473, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #45 [ref=1x] - { 0 , 0 , 339, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #46 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 474, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #47 [ref=2x] - { F(Mmx)|F(Vec) , 0 , 475, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #48 [ref=2x] - { F(Mmx)|F(Vec) , 0 , 476, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #49 [ref=2x] - { F(Vec) , 0 , 341, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #50 [ref=2x] - { F(Vec) , 0 , 343, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #51 [ref=1x] - { F(Vec) , 0 , 345, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #52 [ref=1x] - { F(Vec) , 0 , 347, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #53 [ref=1x] - { F(Vec) , 0 , 349, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #54 [ref=1x] - { 0 , 0 , 477, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #55 [ref=1x] - { 0 , 0 , 478, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #56 [ref=3x] - { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 238, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #57 [ref=1x] - { 0 , 0 , 45 , 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #58 [ref=3x] - { F(Mmx) , 0 , 110, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #59 [ref=1x] - { 0 , 0 , 351, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #60 [ref=2x] - { 0 , 0 , 479, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #61 [ref=1x] - { F(Vec) , 0 , 480, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #62 [ref=2x] - { F(Vec) , 0 , 353, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #63 [ref=1x] - { F(FpuM32)|F(FpuM64) , 0 , 241, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #64 [ref=6x] - { 0 , 0 , 355, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #65 [ref=9x] - { F(FpuM80) , 0 , 481, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #66 [ref=2x] - { 0 , 0 , 356, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #67 [ref=13x] - { F(FpuM32)|F(FpuM64) , 0 , 357, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #68 [ref=2x] - { F(FpuM16)|F(FpuM32) , 0 , 482, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #69 [ref=9x] - { F(FpuM16)|F(FpuM32)|F(FpuM64) , 0 , 483, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #70 [ref=3x] - { F(FpuM32)|F(FpuM64)|F(FpuM80) , 0 , 484, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #71 [ref=2x] - { F(FpuM16) , 0 , 485, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #72 [ref=3x] - { F(FpuM16) , 0 , 486, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #73 [ref=2x] - { F(FpuM32)|F(FpuM64) , 0 , 358, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #74 [ref=1x] - { 0 , 0 , 487, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #75 [ref=4x] - { 0 , 0 , 488, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #76 [ref=1x] - { 0 , 0 , 45 , 10, CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #77 [ref=1x] - { 0 , 0 , 489, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #78 [ref=1x] - { F(Lock) , 0 , 238, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #79 [ref=1x] - { 0 , 0 , 379, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #80 [ref=2x] - { 0 , 0 , 336, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #81 [ref=3x] - { F(Rep) , 0 , 490, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #82 [ref=1x] - { F(Vec) , 0 , 359, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #83 [ref=1x] - { 0 , 0 , 491, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #84 [ref=2x] - { 0 , 0 , 492, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #85 [ref=8x] - { 0 , 0 , 361, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #86 [ref=3x] - { 0 , 0 , 363, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #87 [ref=1x] - { 0 , 0 , 365, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #88 [ref=1x] - { 0 , 0 , 110, 1 , CONTROL_FLOW(Return), SAME_REG_HINT(None)}, // #89 [ref=2x] - { 0 , 0 , 466, 1 , CONTROL_FLOW(Return), SAME_REG_HINT(None)}, // #90 [ref=1x] - { F(Rep) , 0 , 244, 1 , CONTROL_FLOW(Branch), SAME_REG_HINT(None)}, // #91 [ref=30x] - { F(Rep) , 0 , 367, 2 , CONTROL_FLOW(Branch), SAME_REG_HINT(None)}, // #92 [ref=1x] - { F(Rep) , 0 , 244, 3 , CONTROL_FLOW(Jump), SAME_REG_HINT(None)}, // #93 [ref=1x] - { F(Vex) , 0 , 493, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #94 [ref=19x] - { F(Vex) , 0 , 369, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #95 [ref=1x] - { F(Vex) , 0 , 371, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #96 [ref=1x] - { F(Vex) , 0 , 187, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #97 [ref=1x] - { F(Vex) , 0 , 373, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #98 [ref=1x] - { F(Vex) , 0 , 494, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #99 [ref=12x] - { F(Vex) , 0 , 495, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #100 [ref=8x] - { F(Vex) , 0 , 493, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #101 [ref=8x] - { 0 , 0 , 496, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #102 [ref=2x] - { 0 , 0 , 253, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #103 [ref=1x] - { 0 , 0 , 247, 3 , CONTROL_FLOW(Call), SAME_REG_HINT(None)}, // #104 [ref=1x] - { F(Vec) , 0 , 169, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #105 [ref=2x] - { 0 , 0 , 497, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #106 [ref=2x] - { 0 , 0 , 375, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #107 [ref=2x] - { F(Vex) , 0 , 498, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #108 [ref=2x] - { 0 , 0 , 377, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #109 [ref=1x] - { 0 , 0 , 250, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #110 [ref=3x] - { 0 , 0 , 247, 3 , CONTROL_FLOW(Jump), SAME_REG_HINT(None)}, // #111 [ref=1x] - { 0 , 0 , 499, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #112 [ref=5x] - { F(Vex) , 0 , 379, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #113 [ref=2x] - { F(Rep) , 0 , 191, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #114 [ref=1x] - { 0 , 0 , 367, 2 , CONTROL_FLOW(Branch), SAME_REG_HINT(None)}, // #115 [ref=3x] - { 0 , 0 , 253, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #116 [ref=1x] - { F(Vex) , 0 , 381, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #117 [ref=2x] - { F(Vec) , 0 , 500, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #118 [ref=1x] - { F(Mmx) , 0 , 501, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #119 [ref=1x] - { 0 , 0 , 502, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #120 [ref=2x] + { 0 , 0 , 77 , 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #5 [ref=2x] + { F(Vec) , 0 , 99 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #6 [ref=54x] + { F(Vec) , 0 , 172, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #7 [ref=19x] + { F(Vec) , 0 , 316, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #8 [ref=16x] + { F(Vec) , 0 , 325, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #9 [ref=20x] + { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 33 , 13, CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #10 [ref=1x] + { F(Vex) , 0 , 358, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #11 [ref=3x] + { F(Vec) , 0 , 99 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #12 [ref=12x] + { 0 , 0 , 490, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #13 [ref=1x] + { F(Vex) , 0 , 360, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #14 [ref=5x] + { F(Vex) , 0 , 77 , 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #15 [ref=12x] + { F(Vec) , 0 , 491, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #16 [ref=4x] + { 0 , 0 , 362, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #17 [ref=3x] + { F(Mib) , 0 , 492, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #18 [ref=1x] + { 0 , 0 , 493, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #19 [ref=1x] + { 0 , 0 , 364, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #20 [ref=1x] + { F(Mib) , 0 , 494, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #21 [ref=1x] + { 0 , 0 , 366, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #22 [ref=1x] + { 0 , 0 , 76 , 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #23 [ref=21x] + { 0 , 0 , 368, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #24 [ref=3x] + { 0 , 0 , 163, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #25 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 163, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #26 [ref=3x] + { F(Rep)|F(RepIgnored) , 0 , 268, 3 , CONTROL_FLOW(Call), SAME_REG_HINT(None)}, // #27 [ref=1x] + { 0 , 0 , 495, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #28 [ref=1x] + { 0 , 0 , 496, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #29 [ref=2x] + { 0 , 0 , 469, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #30 [ref=1x] + { 0 , 0 , 145, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #31 [ref=88x] + { 0 , 0 , 497, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #32 [ref=24x] + { 0 , 0 , 498, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #33 [ref=6x] + { 0 , 0 , 499, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #34 [ref=14x] + { 0 , 0 , 500, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #35 [ref=1x] + { 0 , 0 , 46 , 13, CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #36 [ref=1x] + { F(Vex) , 0 , 370, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #37 [ref=16x] + { F(Rep) , 0 , 208, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #38 [ref=1x] + { F(Vec) , 0 , 501, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #39 [ref=2x] + { F(Vec) , 0 , 502, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #40 [ref=3x] + { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 212, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #41 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 503, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #42 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 504, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #43 [ref=1x] + { 0 , 0 , 505, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #44 [ref=1x] + { 0 , 0 , 506, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #45 [ref=1x] + { 0 , 0 , 372, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #46 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 507, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #47 [ref=2x] + { F(Mmx)|F(Vec) , 0 , 508, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #48 [ref=2x] + { F(Mmx)|F(Vec) , 0 , 509, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #49 [ref=2x] + { F(Vec) , 0 , 374, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #50 [ref=2x] + { F(Vec) , 0 , 376, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #51 [ref=2x] + { F(Vec) , 0 , 378, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #52 [ref=2x] + { 0 , 0 , 510, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #53 [ref=1x] + { 0 , 0 , 511, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #54 [ref=2x] + { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 271, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #55 [ref=1x] + { 0 , 0 , 72 , 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #56 [ref=3x] + { F(Mmx) , 0 , 145, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #57 [ref=1x] + { 0 , 0 , 380, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #58 [ref=2x] + { 0 , 0 , 512, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #59 [ref=1x] + { F(Vec) , 0 , 513, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #60 [ref=2x] + { F(Vec) , 0 , 382, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #61 [ref=1x] + { F(FpuM32)|F(FpuM64) , 0 , 274, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #62 [ref=6x] + { 0 , 0 , 384, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #63 [ref=9x] + { F(FpuM80) , 0 , 514, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #64 [ref=2x] + { 0 , 0 , 385, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #65 [ref=13x] + { F(FpuM32)|F(FpuM64) , 0 , 386, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #66 [ref=2x] + { F(FpuM16)|F(FpuM32) , 0 , 515, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #67 [ref=9x] + { F(FpuM16)|F(FpuM32)|F(FpuM64) , 0 , 516, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #68 [ref=3x] + { F(FpuM32)|F(FpuM64)|F(FpuM80) , 0 , 517, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #69 [ref=2x] + { F(FpuM16) , 0 , 518, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #70 [ref=3x] + { F(FpuM16) , 0 , 519, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #71 [ref=2x] + { F(FpuM32)|F(FpuM64) , 0 , 387, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #72 [ref=1x] + { 0 , 0 , 520, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #73 [ref=4x] + { 0 , 0 , 521, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #74 [ref=1x] + { 0 , 0 , 522, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #75 [ref=1x] + { 0 , 0 , 72 , 10, CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #76 [ref=1x] + { 0 , 0 , 523, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #77 [ref=1x] + { F(Lock) , 0 , 271, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #78 [ref=1x] + { 0 , 0 , 410, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #79 [ref=2x] + { 0 , 0 , 369, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #80 [ref=3x] + { F(Rep) , 0 , 524, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #81 [ref=1x] + { F(Vec) , 0 , 388, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #82 [ref=1x] + { 0 , 0 , 525, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #83 [ref=2x] + { 0 , 0 , 526, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #84 [ref=8x] + { 0 , 0 , 390, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #85 [ref=3x] + { 0 , 0 , 392, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #86 [ref=1x] + { 0 , 0 , 394, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #87 [ref=1x] + { 0 , 0 , 145, 1 , CONTROL_FLOW(Return), SAME_REG_HINT(None)}, // #88 [ref=2x] + { 0 , 0 , 499, 1 , CONTROL_FLOW(Return), SAME_REG_HINT(None)}, // #89 [ref=1x] + { F(Rep) , 0 , 396, 2 , CONTROL_FLOW(Branch), SAME_REG_HINT(None)}, // #90 [ref=12x] + { F(Rep) , 0 , 398, 2 , CONTROL_FLOW(Branch), SAME_REG_HINT(None)}, // #91 [ref=1x] + { F(Rep) , 0 , 277, 3 , CONTROL_FLOW(Jump), SAME_REG_HINT(None)}, // #92 [ref=1x] + { F(Rep) , 0 , 396, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #93 [ref=4x] + { F(Vex) , 0 , 527, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #94 [ref=19x] + { F(Vex) , 0 , 400, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #95 [ref=1x] + { F(Vex) , 0 , 402, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #96 [ref=1x] + { F(Vex) , 0 , 216, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #97 [ref=1x] + { F(Vex) , 0 , 404, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #98 [ref=1x] + { F(Vex) , 0 , 528, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #99 [ref=12x] + { F(Vex) , 0 , 529, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #100 [ref=8x] + { F(Vex) , 0 , 527, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #101 [ref=8x] + { 0 , 0 , 530, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #102 [ref=2x] + { 0 , 0 , 286, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #103 [ref=1x] + { 0 , 0 , 280, 3 , CONTROL_FLOW(Call), SAME_REG_HINT(None)}, // #104 [ref=1x] + { F(Vec) , 0 , 198, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #105 [ref=2x] + { 0 , 0 , 531, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #106 [ref=2x] + { 0 , 0 , 406, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #107 [ref=2x] + { F(Vex) , 0 , 532, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #108 [ref=2x] + { 0 , 0 , 408, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #109 [ref=1x] + { 0 , 0 , 283, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #110 [ref=3x] + { 0 , 0 , 280, 3 , CONTROL_FLOW(Jump), SAME_REG_HINT(None)}, // #111 [ref=1x] + { 0 , 0 , 533, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #112 [ref=5x] + { F(Vex) , 0 , 410, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #113 [ref=2x] + { F(Rep) , 0 , 220, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #114 [ref=1x] + { 0 , 0 , 398, 2 , CONTROL_FLOW(Branch), SAME_REG_HINT(None)}, // #115 [ref=3x] + { 0 , 0 , 286, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #116 [ref=1x] + { F(Vex) , 0 , 412, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #117 [ref=2x] + { F(Vec) , 0 , 534, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #118 [ref=1x] + { F(Mmx) , 0 , 535, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #119 [ref=1x] + { 0 , 0 , 536, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #120 [ref=2x] { F(XRelease) , 0 , 0 , 20, CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #121 [ref=1x] - { 0 , 0 , 55 , 9 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #122 [ref=1x] - { F(Vec) , 0 , 72 , 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #123 [ref=6x] - { 0 , 0 , 104, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #124 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 383, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #125 [ref=1x] - { 0 , 0 , 385, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #126 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 503, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #127 [ref=1x] - { F(Vec) , 0 , 354, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #128 [ref=2x] - { F(Vec) , 0 , 80 , 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #129 [ref=4x] - { F(Vec) , 0 , 504, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #130 [ref=2x] - { F(Vec) , 0 , 73 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #131 [ref=3x] - { F(Mmx) , 0 , 505, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #132 [ref=1x] - { F(Vec) , 0 , 80 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #133 [ref=1x] - { F(Vec) , 0 , 88 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #134 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 139, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #135 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 506, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #136 [ref=1x] - { F(Rep) , 0 , 195, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #137 [ref=1x] - { F(Vec) , 0 , 387, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #138 [ref=1x] - { F(Vec) , 0 , 389, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #139 [ref=1x] - { 0 , 0 , 256, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #140 [ref=2x] - { 0 , 0 , 391, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #141 [ref=1x] - { F(Vex) , 0 , 393, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #142 [ref=1x] - { 0 , 0 , 507, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #143 [ref=1x] - { 0 , 0 , 508, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #144 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 239, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #145 [ref=2x] - { 0 , 0 , 110, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #146 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 20 , 13, CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #147 [ref=1x] - { 0 , 0 , 509, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #148 [ref=1x] - { F(Rep) , 0 , 510, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #149 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 395, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #150 [ref=37x] - { F(Mmx)|F(Vec) , 0 , 397, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #151 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 395, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #152 [ref=6x] - { F(Mmx)|F(Vec) , 0 , 395, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #153 [ref=16x] - { F(Mmx) , 0 , 139, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #154 [ref=26x] - { F(Vec) , 0 , 72 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #155 [ref=4x] - { F(Vec) , 0 , 511, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #156 [ref=1x] - { F(Vec) , 0 , 512, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #157 [ref=1x] - { F(Vec) , 0 , 513, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #158 [ref=1x] - { F(Vec) , 0 , 514, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #159 [ref=1x] - { F(Vec) , 0 , 515, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #160 [ref=1x] - { F(Vec) , 0 , 516, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #161 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 399, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #162 [ref=1x] - { F(Vec) , 0 , 517, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #163 [ref=1x] - { F(Vec) , 0 , 518, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #164 [ref=1x] - { F(Vec) , 0 , 519, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #165 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 520, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #166 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 521, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #167 [ref=1x] - { F(Vec) , 0 , 313, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #168 [ref=2x] - { 0 , 0 , 144, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #169 [ref=1x] - { F(Mmx) , 0 , 397, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #170 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 401, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #171 [ref=8x] - { F(Vec) , 0 , 522, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #172 [ref=2x] - { 0 , 0 , 403, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #173 [ref=1x] - { F(Mmx)|F(Vec) , 0 , 405, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #174 [ref=3x] - { 0 , 0 , 149, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #175 [ref=1x] - { 0 , 0 , 523, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #176 [ref=1x] - { 0 , 0 , 407, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #177 [ref=8x] - { 0 , 0 , 524, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #178 [ref=4x] - { 0 , 0 , 525, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #179 [ref=8x] - { 0 , 0 , 409, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #180 [ref=1x] - { F(Rep)|F(RepIgnored) , 0 , 411, 2 , CONTROL_FLOW(Return), SAME_REG_HINT(None)}, // #181 [ref=1x] - { 0 , 0 , 411, 2 , CONTROL_FLOW(Return), SAME_REG_HINT(None)}, // #182 [ref=1x] - { F(Vex) , 0 , 413, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #183 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 20 , 13, CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #184 [ref=3x] - { F(Rep) , 0 , 199, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #185 [ref=1x] - { 0 , 0 , 526, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #186 [ref=30x] - { 0 , 0 , 259, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #187 [ref=2x] - { 0 , 0 , 415, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #188 [ref=3x] - { F(Rep) , 0 , 203, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #189 [ref=1x] - { F(Vex) , 0 , 527, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #190 [ref=8x] - { 0 , 0 , 64 , 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #191 [ref=1x] - { F(Tsib)|F(Vex) , 0 , 528, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #192 [ref=2x] - { F(Vex) , 0 , 466, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #193 [ref=1x] - { F(Tsib)|F(Vex) , 0 , 529, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #194 [ref=1x] - { F(Vex) , 0 , 530, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #195 [ref=1x] - { 0 , 0 , 531, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #196 [ref=2x] - { 0 , 0 , 50 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #197 [ref=2x] - { 0 , 0 , 417, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #198 [ref=1x] - { F(Evex)|F(Vec) , X(K)|X(T4X)|X(Z) , 532, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #199 [ref=4x] - { F(Evex)|F(Vec) , X(K)|X(T4X)|X(Z) , 533, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #200 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #201 [ref=22x] - { F(Evex)|F(Vec) , X(B16)|X(ER)|X(K)|X(SAE)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #202 [ref=23x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #203 [ref=22x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(ER)|X(K)|X(SAE)|X(Z) , 534, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #204 [ref=18x] - { F(Evex)|F(Vec) , X(ER)|X(K)|X(SAE)|X(Z) , 535, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #205 [ref=18x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(ER)|X(K)|X(SAE)|X(Z) , 536, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #206 [ref=17x] - { F(Vec)|F(Vex) , 0 , 262, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #207 [ref=29x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #208 [ref=5x] - { F(Vec)|F(Vex) , 0 , 72 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #209 [ref=17x] - { F(Vec)|F(Vex) , 0 , 292, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #210 [ref=1x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 265, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #211 [ref=4x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 265, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #212 [ref=4x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #213 [ref=10x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #214 [ref=12x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #215 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #216 [ref=6x] - { F(Vec)|F(Vex) , 0 , 537, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #217 [ref=2x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #218 [ref=17x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #219 [ref=12x] - { F(Vec)|F(Vex) , 0 , 265, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #220 [ref=6x] - { F(Vec)|F(Vex) , 0 , 419, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #221 [ref=3x] - { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 538, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #222 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 539, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #223 [ref=1x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 540, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #224 [ref=4x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 541, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #225 [ref=4x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 445, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #226 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 539, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #227 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 542, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #228 [ref=1x] - { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(B64)|X(ImplicitZ)|X(K)|X(SAE), 268, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #229 [ref=1x] - { F(Evex)|F(Vec) , X(B16)|X(ImplicitZ)|X(K)|X(SAE), 271, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #230 [ref=1x] - { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(B32)|X(ImplicitZ)|X(K)|X(SAE), 268, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #231 [ref=1x] - { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(ImplicitZ)|X(K)|X(SAE) , 543, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #232 [ref=1x] - { F(Evex)|F(Vec) , X(ImplicitZ)|X(K)|X(SAE) , 544, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #233 [ref=1x] - { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(ImplicitZ)|X(K)|X(SAE) , 545, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #234 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(SAE) , 143, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #235 [ref=2x] - { F(Evex)|F(Vec) , X(SAE) , 313, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #236 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(SAE) , 283, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #237 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 274, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #238 [ref=6x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 277, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #239 [ref=1x] - { F(Evex)|F(Vec) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 421, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #240 [ref=3x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #241 [ref=3x] - { F(Vec)|F(Vex) , 0 , 169, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #242 [ref=5x] - { F(Evex)|F(EvexCompat)|F(PreferEvex)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 421, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #243 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 421, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #244 [ref=2x] - { F(Evex)|F(Vec) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 546, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #245 [ref=3x] - { F(Evex)|F(Vec) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #246 [ref=4x] - { F(Evex)|F(Vec) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 421, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #247 [ref=3x] - { F(Evex)|F(Vec) , X(B16)|X(ER)|X(K)|X(SAE)|X(Z) , 277, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #248 [ref=2x] - { F(Evex)|F(Vec) , X(B16)|X(K)|X(SAE)|X(Z) , 283, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #249 [ref=3x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(SAE)|X(Z) , 277, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #250 [ref=1x] - { F(Evex)|F(Vec) , X(B16)|X(K)|X(SAE)|X(Z) , 277, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #251 [ref=3x] - { F(Evex)|F(Vec) , X(B16)|X(ER)|X(K)|X(SAE)|X(Z) , 283, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #252 [ref=2x] - { F(Evex)|F(Vec) , X(B16)|X(ER)|X(K)|X(SAE)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #253 [ref=5x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 277, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #254 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(SAE)|X(Z) , 286, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #255 [ref=1x] - { F(Evex)|F(Vec) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 277, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #256 [ref=2x] - { F(Evex)|F(Vec) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #257 [ref=2x] - { F(Evex)|F(Vec) , X(ER)|X(K)|X(SAE)|X(Z) , 534, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #258 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(ER)|X(SAE) , 341, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #259 [ref=1x] - { F(Evex)|F(Vec) , X(ER)|X(SAE) , 341, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #260 [ref=1x] - { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 535, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #261 [ref=5x] - { F(Evex)|F(Vec) , X(ER)|X(SAE) , 423, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #262 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(ER)|X(SAE) , 425, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #263 [ref=2x] - { F(Evex)|F(Vec) , X(ER)|X(SAE) , 427, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #264 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(SAE)|X(Z) , 536, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #265 [ref=3x] - { F(Evex)|F(Vec) , X(ER)|X(K)|X(SAE)|X(Z) , 536, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #266 [ref=6x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(ER)|X(SAE) , 347, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #267 [ref=1x] - { F(Evex)|F(Vec) , X(ER)|X(SAE) , 347, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #268 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(SAE)|X(Z) , 421, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #269 [ref=1x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(SAE)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #270 [ref=3x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(SAE)|X(Z) , 421, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #271 [ref=1x] - { F(Evex)|F(Vec) , X(B16)|X(K)|X(SAE)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #272 [ref=3x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(SAE)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #273 [ref=1x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(SAE)|X(Z) , 277, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #274 [ref=2x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(SAE)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #275 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(SAE) , 341, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #276 [ref=1x] - { F(Evex)|F(Vec) , X(SAE) , 341, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #277 [ref=1x] - { F(Evex)|F(Vec) , X(SAE) , 423, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #278 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(SAE) , 347, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #279 [ref=1x] - { F(Evex)|F(Vec) , X(SAE) , 347, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #280 [ref=1x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 277, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #281 [ref=1x] - { F(Evex)|F(Vec) , X(ER)|X(SAE) , 425, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #282 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 265, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #283 [ref=3x] - { F(Vec)|F(Vex) , 0 , 265, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #284 [ref=10x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(SAE)|X(Z) , 78 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #285 [ref=3x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(SAE)|X(Z) , 78 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #286 [ref=3x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #287 [ref=8x] - { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 287, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #288 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 547, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #289 [ref=4x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 288, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #290 [ref=4x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 480, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #291 [ref=2x] - { F(Evex)|F(Vec) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #292 [ref=5x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(SAE)|X(Z) , 265, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #293 [ref=2x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(SAE)|X(Z) , 265, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #294 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 548, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #295 [ref=4x] - { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 549, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #296 [ref=4x] - { F(Vec)|F(Vex) , 0 , 207, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #297 [ref=13x] - { F(Vec)|F(Vex) , 0 , 429, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #298 [ref=4x] - { F(Vec)|F(Vex) , 0 , 431, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #299 [ref=4x] - { F(Evex)|F(Vec) , X(B64)|X(ImplicitZ)|X(K) , 550, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #300 [ref=1x] - { F(Evex)|F(Vec) , X(B16)|X(K) , 550, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #301 [ref=1x] - { F(Evex)|F(Vec) , X(B32)|X(ImplicitZ)|X(K) , 550, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #302 [ref=1x] - { F(Evex)|F(Vec) , X(ImplicitZ)|X(K) , 551, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #303 [ref=1x] - { F(Evex)|F(Vec) , X(K) , 552, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #304 [ref=1x] - { F(Evex)|F(Vec) , X(ImplicitZ)|X(K) , 553, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #305 [ref=1x] - { F(Vec)|F(Vex) , 0 , 280, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #306 [ref=7x] - { F(Vec)|F(Vex) , 0 , 143, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #307 [ref=1x] - { F(Vec)|F(Vex) , 0 , 283, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #308 [ref=1x] - { F(Evex)|F(EvexTwoOp)|F(Vec)|F(Vex)|F(Vsib) , X(K) , 211, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #309 [ref=2x] - { F(Evex)|F(EvexTwoOp)|F(Vec)|F(Vex)|F(Vsib) , X(K) , 154, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #310 [ref=2x] - { F(Evex)|F(Vsib) , X(K) , 554, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #311 [ref=4x] - { F(Evex)|F(Vsib) , X(K) , 555, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #312 [ref=4x] - { F(Evex)|F(Vsib) , X(K) , 556, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #313 [ref=8x] - { F(Evex)|F(EvexTwoOp)|F(Vec)|F(Vex)|F(Vsib) , X(K) , 159, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #314 [ref=2x] - { F(Evex)|F(EvexTwoOp)|F(Vec)|F(Vex)|F(Vsib) , X(K) , 289, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #315 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 534, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #316 [ref=3x] - { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 536, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #317 [ref=3x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(SAE)|X(Z) , 292, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #318 [ref=2x] - { F(Evex)|F(Vec) , X(B16)|X(K)|X(SAE)|X(Z) , 292, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #319 [ref=3x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(SAE)|X(Z) , 292, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #320 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 557, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #321 [ref=3x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 265, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #322 [ref=3x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #323 [ref=22x] - { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 433, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #324 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 433, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #325 [ref=4x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 558, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #326 [ref=4x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 549, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #327 [ref=1x] - { F(Vex) , 0 , 497, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #328 [ref=2x] - { F(Vec)|F(Vex) , 0 , 500, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #329 [ref=1x] - { F(Vec)|F(Vex) , 0 , 215, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #330 [ref=4x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(SAE)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #331 [ref=2x] - { F(Evex)|F(Vec) , X(B16)|X(K)|X(SAE)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #332 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(SAE)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #333 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(SAE)|X(Z) , 534, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #334 [ref=2x] - { 0 , 0 , 435, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #335 [ref=3x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 72 , 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #336 [ref=4x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 437, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #337 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 295, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #338 [ref=1x] - { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 72 , 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #339 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 116, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #340 [ref=6x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 82 , 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #341 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 219, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #342 [ref=4x] - { F(Vec)|F(Vex) , 0 , 559, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #343 [ref=3x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 164, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #344 [ref=3x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 169, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #345 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 174, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #346 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 80 , 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #347 [ref=1x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 223, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #348 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #349 [ref=4x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 88 , 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #350 [ref=1x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 439, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #351 [ref=1x] - { 0 , 0 , 441, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #352 [ref=1x] - { 0 , 0 , 443, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #353 [ref=1x] - { F(Evex)|F(Vec) , X(B32) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #354 [ref=1x] - { F(Evex)|F(Vec) , X(B64) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #355 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #356 [ref=1x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #357 [ref=5x] - { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 262, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #358 [ref=2x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #359 [ref=2x] - { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 262, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #360 [ref=2x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #361 [ref=2x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #362 [ref=2x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #363 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #364 [ref=13x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 560, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #365 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 561, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #366 [ref=1x] - { F(Evex)|F(Vec) , 0 , 562, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #367 [ref=6x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 445, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #368 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 563, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #369 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 265, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #370 [ref=1x] - { F(Evex)|F(Vec) , X(ImplicitZ)|X(K) , 271, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #371 [ref=2x] - { F(Evex)|F(Vec) , X(B32)|X(ImplicitZ)|X(K) , 271, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #372 [ref=2x] - { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(ImplicitZ)|X(K) , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #373 [ref=4x] - { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(B32)|X(ImplicitZ)|X(K) , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #374 [ref=2x] - { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(B64)|X(ImplicitZ)|X(K) , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #375 [ref=2x] - { F(Vec)|F(Vex) , 0 , 511, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #376 [ref=1x] - { F(Vec)|F(Vex) , 0 , 512, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #377 [ref=1x] - { F(Vec)|F(Vex) , 0 , 513, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #378 [ref=1x] - { F(Vec)|F(Vex) , 0 , 514, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #379 [ref=1x] - { F(Evex)|F(Vec) , X(B64)|X(ImplicitZ)|X(K) , 271, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #380 [ref=4x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #381 [ref=6x] - { F(Evex)|F(EvexCompat)|F(PreferEvex)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #382 [ref=4x] - { F(Vec)|F(Vex) , 0 , 266, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #383 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 263, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #384 [ref=2x] - { F(Vec)|F(Vex) , 0 , 227, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #385 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 96 , 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #386 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 96 , 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #387 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 231, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #388 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 515, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #389 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 516, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #390 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 564, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #391 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 565, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #392 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 566, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #393 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 567, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #394 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 568, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #395 [ref=1x] - { F(Vec)|F(Vex) , 0 , 419, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #396 [ref=12x] - { F(Evex)|F(EvexCompat)|F(PreferEvex)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #397 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #398 [ref=8x] - { F(Evex)|F(Vec) , 0 , 569, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #399 [ref=4x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 304, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #400 [ref=6x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 307, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #401 [ref=9x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 310, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #402 [ref=3x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 283, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #403 [ref=4x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 313, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #404 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 277, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #405 [ref=6x] - { F(Vec)|F(Vex) , 0 , 207, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #406 [ref=1x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 292, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #407 [ref=3x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 292, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #408 [ref=3x] - { F(Vec)|F(Vex) , 0 , 447, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #409 [ref=4x] - { F(Evex)|F(Vec)|F(Vsib) , X(K) , 316, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #410 [ref=2x] - { F(Evex)|F(Vec)|F(Vsib) , X(K) , 449, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #411 [ref=2x] - { F(Evex)|F(Vec)|F(Vsib) , X(K) , 451, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #412 [ref=2x] - { F(Evex)|F(Vec)|F(Vsib) , X(K) , 319, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #413 [ref=2x] - { F(Vec)|F(Vex) , 0 , 453, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #414 [ref=8x] - { F(Evex)|F(Vec) , X(ImplicitZ)|X(K) , 322, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #415 [ref=5x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 292, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #416 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 292, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #417 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 122, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #418 [ref=3x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 292, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #419 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 122, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #420 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 122, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #421 [ref=3x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 128, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #422 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #423 [ref=6x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #424 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #425 [ref=2x] - { F(Evex)|F(Vec) , X(B32)|X(ImplicitZ)|X(K) , 322, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #426 [ref=2x] - { F(Evex)|F(Vec) , X(B64)|X(ImplicitZ)|X(K) , 322, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #427 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 534, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #428 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 536, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #429 [ref=2x] - { F(Evex)|F(Vec) , X(B16)|X(K)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #430 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 535, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #431 [ref=2x] - { F(Vec)|F(Vex) , 0 , 536, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #432 [ref=2x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 548, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #433 [ref=1x] - { F(Evex)|F(Vec) , X(K)|X(Z) , 549, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #434 [ref=1x] - { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 292, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #435 [ref=2x] - { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 548, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #436 [ref=1x] - { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 549, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #437 [ref=1x] - { F(Evex)|F(Vec) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 262, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #438 [ref=1x] - { F(Vec)|F(Vex) , 0 , 570, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #439 [ref=1x] - { F(Vec)|F(Vex) , 0 , 571, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #440 [ref=1x] - { F(Vec)|F(Vex) , 0 , 572, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #441 [ref=1x] - { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 266, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #442 [ref=2x] - { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 266, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #443 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 265, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #444 [ref=1x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 265, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #445 [ref=1x] - { F(Vec)|F(Vex) , 0 , 262, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #446 [ref=2x] - { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 280, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #447 [ref=1x] - { F(Vec)|F(Vex) , 0 , 110, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #448 [ref=2x] - { 0 , 0 , 27 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #449 [ref=2x] - { 0 , 0 , 28 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #450 [ref=2x] - { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 25 , 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #451 [ref=1x] - { 0 , 0 , 236, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #452 [ref=1x] - { F(XAcquire) , 0 , 25 , 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #453 [ref=1x] - { 0 , 0 , 573, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #454 [ref=6x] - { 0 , 0 , 574, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)} // #455 [ref=6x] + { 0 , 0 , 82 , 9 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #122 [ref=1x] + { F(Vec) , 0 , 414, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #123 [ref=6x] + { 0 , 0 , 139, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #124 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 416, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #125 [ref=1x] + { 0 , 0 , 418, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #126 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 537, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #127 [ref=1x] + { F(Vec) , 0 , 383, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #128 [ref=2x] + { F(Vec) , 0 , 107, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #129 [ref=4x] + { F(Vec) , 0 , 538, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #130 [ref=2x] + { F(Vec) , 0 , 101, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #131 [ref=3x] + { F(Mmx) , 0 , 539, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #132 [ref=1x] + { F(Vec) , 0 , 107, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #133 [ref=1x] + { F(Vec) , 0 , 115, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #134 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 168, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #135 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 540, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #136 [ref=1x] + { F(Rep) , 0 , 224, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #137 [ref=1x] + { F(Vec) , 0 , 420, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #138 [ref=1x] + { F(Vec) , 0 , 422, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #139 [ref=1x] + { 0 , 0 , 289, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #140 [ref=2x] + { 0 , 0 , 424, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #141 [ref=1x] + { F(Vex) , 0 , 426, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #142 [ref=1x] + { 0 , 0 , 541, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #143 [ref=1x] + { 0 , 0 , 542, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #144 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 272, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #145 [ref=2x] + { 0 , 0 , 145, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #146 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 59 , 13, CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #147 [ref=1x] + { 0 , 0 , 543, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #148 [ref=1x] + { F(Rep) , 0 , 544, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #149 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 428, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #150 [ref=37x] + { F(Mmx)|F(Vec) , 0 , 430, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #151 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 428, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #152 [ref=6x] + { F(Mmx)|F(Vec) , 0 , 428, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #153 [ref=16x] + { F(Mmx) , 0 , 168, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #154 [ref=26x] + { F(Vec) , 0 , 99 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #155 [ref=4x] + { F(Vec) , 0 , 545, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #156 [ref=1x] + { F(Vec) , 0 , 546, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #157 [ref=1x] + { F(Vec) , 0 , 547, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #158 [ref=1x] + { F(Vec) , 0 , 548, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #159 [ref=1x] + { F(Vec) , 0 , 549, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #160 [ref=1x] + { F(Vec) , 0 , 550, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #161 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 432, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #162 [ref=1x] + { F(Vec) , 0 , 551, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #163 [ref=1x] + { F(Vec) , 0 , 552, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #164 [ref=1x] + { F(Vec) , 0 , 553, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #165 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 554, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #166 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 555, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #167 [ref=1x] + { F(Vec) , 0 , 346, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #168 [ref=2x] + { 0 , 0 , 173, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #169 [ref=1x] + { F(Mmx) , 0 , 430, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #170 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 434, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #171 [ref=8x] + { F(Vec) , 0 , 556, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #172 [ref=2x] + { 0 , 0 , 436, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #173 [ref=1x] + { F(Mmx)|F(Vec) , 0 , 438, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #174 [ref=3x] + { 0 , 0 , 178, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #175 [ref=1x] + { 0 , 0 , 557, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #176 [ref=1x] + { 0 , 0 , 440, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #177 [ref=7x] + { 0 , 0 , 558, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #178 [ref=4x] + { F(Evex)|F(EvexCompat)|F(Vex) , 0 , 292, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #179 [ref=1x] + { 0 , 0 , 442, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #180 [ref=1x] + { 0 , 0 , 292, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #181 [ref=7x] + { F(Rep)|F(RepIgnored) , 0 , 444, 2 , CONTROL_FLOW(Return), SAME_REG_HINT(None)}, // #182 [ref=1x] + { 0 , 0 , 444, 2 , CONTROL_FLOW(Return), SAME_REG_HINT(None)}, // #183 [ref=1x] + { F(Vex) , 0 , 446, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #184 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 20 , 13, CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #185 [ref=3x] + { F(Rep) , 0 , 228, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #186 [ref=1x] + { 0 , 0 , 559, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #187 [ref=16x] + { 0 , 0 , 295, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #188 [ref=2x] + { 0 , 0 , 448, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #189 [ref=3x] + { F(Rep) , 0 , 232, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #190 [ref=1x] + { F(Vex) , 0 , 560, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #191 [ref=8x] + { 0 , 0 , 91 , 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #192 [ref=1x] + { F(Tsib)|F(Vex) , 0 , 561, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #193 [ref=2x] + { F(Vex) , 0 , 499, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #194 [ref=1x] + { F(Tsib)|F(Vex) , 0 , 562, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #195 [ref=1x] + { F(Vex) , 0 , 563, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #196 [ref=1x] + { 0 , 0 , 564, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #197 [ref=2x] + { 0 , 0 , 77 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #198 [ref=2x] + { 0 , 0 , 450, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #199 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #200 [ref=22x] + { F(Evex)|F(Vec) , X(B16)|X(ER)|X(K)|X(SAE)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #201 [ref=23x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #202 [ref=22x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(ER)|X(K)|X(SAE)|X(Z) , 565, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #203 [ref=18x] + { F(Evex)|F(Vec) , X(ER)|X(K)|X(SAE)|X(Z) , 566, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #204 [ref=18x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(ER)|X(K)|X(SAE)|X(Z) , 567, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #205 [ref=17x] + { F(Vec)|F(Vex) , 0 , 298, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #206 [ref=29x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #207 [ref=5x] + { F(Vec)|F(Vex) , 0 , 99 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #208 [ref=17x] + { F(Vec)|F(Vex) , 0 , 325, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #209 [ref=1x] + { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #210 [ref=4x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #211 [ref=4x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #212 [ref=10x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #213 [ref=12x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #214 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #215 [ref=6x] + { F(Vec)|F(Vex) , 0 , 568, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #216 [ref=2x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #217 [ref=17x] + { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #218 [ref=12x] + { F(Vec)|F(Vex) , 0 , 301, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #219 [ref=6x] + { F(Vec)|F(Vex) , 0 , 452, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #220 [ref=3x] + { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 569, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #221 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 570, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #222 [ref=1x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 571, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #223 [ref=4x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 572, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #224 [ref=4x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 478, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #225 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 570, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #226 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 573, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #227 [ref=1x] + { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(B64)|X(ImplicitZ)|X(K)|X(SAE), 304, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #228 [ref=1x] + { F(Evex)|F(Vec) , X(B16)|X(ImplicitZ)|X(K)|X(SAE), 307, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #229 [ref=1x] + { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(B32)|X(ImplicitZ)|X(K)|X(SAE), 304, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #230 [ref=1x] + { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(ImplicitZ)|X(K)|X(SAE) , 574, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #231 [ref=1x] + { F(Evex)|F(Vec) , X(ImplicitZ)|X(K)|X(SAE) , 575, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #232 [ref=1x] + { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(ImplicitZ)|X(K)|X(SAE) , 576, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #233 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(SAE) , 172, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #234 [ref=2x] + { F(Evex)|F(Vec) , X(SAE) , 346, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #235 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(SAE) , 316, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #236 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 310, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #237 [ref=6x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 313, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #238 [ref=1x] + { F(Evex)|F(Vec) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 454, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #239 [ref=3x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #240 [ref=3x] + { F(Vec)|F(Vex) , 0 , 198, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #241 [ref=5x] + { F(Evex)|F(EvexCompat)|F(PreferEvex)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 454, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #242 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 454, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #243 [ref=2x] + { F(Evex)|F(Vec) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 577, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #244 [ref=3x] + { F(Evex)|F(Vec) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #245 [ref=4x] + { F(Evex)|F(Vec) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 454, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #246 [ref=3x] + { F(Evex)|F(Vec) , X(B16)|X(ER)|X(K)|X(SAE)|X(Z) , 313, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #247 [ref=2x] + { F(Evex)|F(Vec) , X(B16)|X(K)|X(SAE)|X(Z) , 316, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #248 [ref=3x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(SAE)|X(Z) , 313, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #249 [ref=1x] + { F(Evex)|F(Vec) , X(B16)|X(K)|X(SAE)|X(Z) , 313, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #250 [ref=3x] + { F(Evex)|F(Vec) , X(B16)|X(ER)|X(K)|X(SAE)|X(Z) , 316, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #251 [ref=2x] + { F(Evex)|F(Vec) , X(B16)|X(ER)|X(K)|X(SAE)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #252 [ref=5x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 313, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #253 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(SAE)|X(Z) , 319, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #254 [ref=1x] + { F(Evex)|F(Vec) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 313, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #255 [ref=3x] + { F(Evex)|F(Vec) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #256 [ref=2x] + { F(Evex)|F(Vec) , X(ER)|X(K)|X(SAE)|X(Z) , 565, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #257 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(ER)|X(SAE) , 374, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #258 [ref=1x] + { F(Evex)|F(Vec) , X(ER)|X(SAE) , 374, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #259 [ref=1x] + { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 566, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #260 [ref=5x] + { F(Evex)|F(Vec) , X(ER)|X(SAE) , 456, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #261 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(ER)|X(SAE) , 458, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #262 [ref=2x] + { F(Evex)|F(Vec) , X(ER)|X(SAE) , 460, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #263 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(SAE)|X(Z) , 567, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #264 [ref=3x] + { F(Evex)|F(Vec) , X(ER)|X(K)|X(SAE)|X(Z) , 567, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #265 [ref=6x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(ER)|X(SAE) , 378, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #266 [ref=1x] + { F(Evex)|F(Vec) , X(ER)|X(SAE) , 378, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #267 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(SAE)|X(Z) , 454, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #268 [ref=1x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(SAE)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #269 [ref=3x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(SAE)|X(Z) , 454, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #270 [ref=1x] + { F(Evex)|F(Vec) , X(B16)|X(K)|X(SAE)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #271 [ref=3x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(SAE)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #272 [ref=1x] + { F(Evex)|F(Vec) , X(B32)|X(K)|X(SAE)|X(Z) , 313, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #273 [ref=2x] + { F(Evex)|F(Vec) , X(B32)|X(K)|X(SAE)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #274 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(SAE) , 374, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #275 [ref=1x] + { F(Evex)|F(Vec) , X(SAE) , 374, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #276 [ref=1x] + { F(Evex)|F(Vec) , X(SAE) , 456, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #277 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(SAE) , 378, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #278 [ref=1x] + { F(Evex)|F(Vec) , X(SAE) , 378, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #279 [ref=1x] + { F(Evex)|F(Vec) , X(ER)|X(SAE) , 458, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #280 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #281 [ref=3x] + { F(Vec)|F(Vex) , 0 , 301, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #282 [ref=10x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #283 [ref=8x] + { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 320, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #284 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 578, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #285 [ref=4x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 321, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #286 [ref=4x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 513, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #287 [ref=2x] + { F(Evex)|F(Vec) , X(B32)|X(ER)|X(K)|X(SAE)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #288 [ref=5x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(SAE)|X(Z) , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #289 [ref=2x] + { F(Evex)|F(Vec) , X(B32)|X(K)|X(SAE)|X(Z) , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #290 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 579, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #291 [ref=4x] + { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 580, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #292 [ref=4x] + { F(Vec)|F(Vex) , 0 , 236, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #293 [ref=12x] + { F(Vec)|F(Vex) , 0 , 462, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #294 [ref=4x] + { F(Vec)|F(Vex) , 0 , 464, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #295 [ref=4x] + { F(Evex)|F(Vec) , X(B64)|X(ImplicitZ)|X(K) , 581, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #296 [ref=1x] + { F(Evex)|F(Vec) , X(B16)|X(ImplicitZ)|X(K) , 581, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #297 [ref=1x] + { F(Evex)|F(Vec) , X(B32)|X(ImplicitZ)|X(K) , 581, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #298 [ref=1x] + { F(Evex)|F(Vec) , X(ImplicitZ)|X(K) , 582, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #299 [ref=1x] + { F(Evex)|F(Vec) , X(ImplicitZ)|X(K) , 583, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #300 [ref=1x] + { F(Evex)|F(Vec) , X(ImplicitZ)|X(K) , 584, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #301 [ref=1x] + { F(Vec)|F(Vex) , 0 , 99 , 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #302 [ref=7x] + { F(Vec)|F(Vex) , 0 , 172, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #303 [ref=1x] + { F(Vec)|F(Vex) , 0 , 316, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #304 [ref=1x] + { F(Evex)|F(EvexTwoOp)|F(Vec)|F(Vex)|F(Vsib) , X(K) , 240, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #305 [ref=2x] + { F(Evex)|F(EvexTwoOp)|F(Vec)|F(Vex)|F(Vsib) , X(K) , 183, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #306 [ref=2x] + { F(Evex)|F(EvexTwoOp)|F(Vec)|F(Vex)|F(Vsib) , X(K) , 188, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #307 [ref=2x] + { F(Evex)|F(EvexTwoOp)|F(Vec)|F(Vex)|F(Vsib) , X(K) , 322, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #308 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 565, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #309 [ref=1x] + { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 567, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #310 [ref=1x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(SAE)|X(Z) , 325, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #311 [ref=2x] + { F(Evex)|F(Vec) , X(B16)|X(K)|X(SAE)|X(Z) , 325, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #312 [ref=3x] + { F(Evex)|F(Vec) , X(B32)|X(K)|X(SAE)|X(Z) , 325, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #313 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(SAE)|X(Z) , 585, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #314 [ref=3x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #315 [ref=3x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #316 [ref=22x] + { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 466, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #317 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 466, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #318 [ref=4x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 586, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #319 [ref=4x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 580, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #320 [ref=1x] + { F(Vex) , 0 , 531, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #321 [ref=2x] + { F(Vec)|F(Vex) , 0 , 534, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #322 [ref=1x] + { F(Vec)|F(Vex) , 0 , 244, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #323 [ref=4x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(SAE)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #324 [ref=2x] + { F(Evex)|F(Vec) , X(B16)|X(K)|X(SAE)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #325 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(SAE)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #326 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(SAE)|X(Z) , 565, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #327 [ref=2x] + { 0 , 0 , 468, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #328 [ref=3x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 99 , 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #329 [ref=4x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 470, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #330 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 328, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #331 [ref=1x] + { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 99 , 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #332 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 151, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #333 [ref=6x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 109, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #334 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 248, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #335 [ref=4x] + { F(Vec)|F(Vex) , 0 , 587, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #336 [ref=3x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 193, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #337 [ref=3x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 198, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #338 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 203, 5 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #339 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 107, 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #340 [ref=1x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 252, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #341 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #342 [ref=4x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 115, 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #343 [ref=1x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 472, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #344 [ref=1x] + { 0 , 0 , 474, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #345 [ref=1x] + { 0 , 0 , 476, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #346 [ref=1x] + { F(Evex)|F(Vec) , X(B32) , 331, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #347 [ref=1x] + { F(Evex)|F(Vec) , X(B64) , 331, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #348 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #349 [ref=1x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #350 [ref=5x] + { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 298, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #351 [ref=2x] + { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #352 [ref=2x] + { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 298, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #353 [ref=2x] + { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #354 [ref=2x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #355 [ref=2x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #356 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #357 [ref=13x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 588, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #358 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 589, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #359 [ref=1x] + { F(Evex)|F(Vec) , 0 , 590, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #360 [ref=6x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 478, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #361 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 591, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #362 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #363 [ref=1x] + { F(Vec)|F(Vex) , 0 , 256, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #364 [ref=1x] + { F(Evex)|F(Vec) , X(ImplicitZ)|X(K) , 307, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #365 [ref=4x] + { F(Evex)|F(Vec) , X(B32)|X(ImplicitZ)|X(K) , 307, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #366 [ref=2x] + { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(ImplicitZ)|X(K) , 334, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #367 [ref=4x] + { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(B32)|X(ImplicitZ)|X(K) , 334, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #368 [ref=2x] + { F(Evex)|F(EvexKReg)|F(Vec)|F(Vex) , X(B64)|X(ImplicitZ)|X(K) , 334, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #369 [ref=2x] + { F(Vec)|F(Vex) , 0 , 545, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #370 [ref=1x] + { F(Vec)|F(Vex) , 0 , 546, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #371 [ref=1x] + { F(Vec)|F(Vex) , 0 , 547, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #372 [ref=1x] + { F(Vec)|F(Vex) , 0 , 548, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #373 [ref=1x] + { F(Evex)|F(Vec) , X(B64)|X(ImplicitZ)|X(K) , 307, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #374 [ref=2x] + { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #375 [ref=6x] + { F(Evex)|F(EvexCompat)|F(PreferEvex)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #376 [ref=4x] + { F(Vec)|F(Vex) , 0 , 302, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #377 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 299, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #378 [ref=2x] + { F(Vec)|F(Vex) , 0 , 260, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #379 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 123, 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #380 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 123, 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #381 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 264, 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #382 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 549, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #383 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 550, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #384 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 592, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #385 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 593, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #386 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 594, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #387 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 595, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #388 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 596, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #389 [ref=1x] + { F(Vec)|F(Vex) , 0 , 452, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #390 [ref=12x] + { F(Evex)|F(EvexCompat)|F(PreferEvex)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #391 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #392 [ref=8x] + { F(Evex)|F(Vec) , 0 , 597, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #393 [ref=4x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 337, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #394 [ref=6x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 340, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #395 [ref=9x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 343, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #396 [ref=3x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 316, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #397 [ref=4x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 346, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #398 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 313, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #399 [ref=6x] + { F(Vec)|F(Vex) , 0 , 256, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #400 [ref=1x] + { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 325, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #401 [ref=3x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 325, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #402 [ref=3x] + { F(Vec)|F(Vex) , 0 , 480, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #403 [ref=4x] + { F(Evex)|F(Vec)|F(Vsib) , X(K) , 349, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #404 [ref=2x] + { F(Evex)|F(Vec)|F(Vsib) , X(K) , 482, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #405 [ref=2x] + { F(Evex)|F(Vec)|F(Vsib) , X(K) , 484, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #406 [ref=2x] + { F(Evex)|F(Vec)|F(Vsib) , X(K) , 352, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #407 [ref=2x] + { F(Vec)|F(Vex) , 0 , 486, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #408 [ref=8x] + { F(Evex)|F(Vec) , X(ImplicitZ)|X(K) , 355, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #409 [ref=5x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 325, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #410 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 325, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #411 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 157, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #412 [ref=3x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , 0 , 325, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #413 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 157, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #414 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 157, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #415 [ref=3x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 157, 6 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #416 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #417 [ref=6x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #418 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(WO)}, // #419 [ref=2x] + { F(Evex)|F(Vec) , X(B32)|X(ImplicitZ)|X(K) , 355, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #420 [ref=2x] + { F(Evex)|F(Vec) , X(B64)|X(ImplicitZ)|X(K) , 355, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #421 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 565, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #422 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 567, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #423 [ref=2x] + { F(Evex)|F(Vec) , X(B16)|X(K)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #424 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 566, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #425 [ref=2x] + { F(Vec)|F(Vex) , 0 , 567, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #426 [ref=2x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 579, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #427 [ref=1x] + { F(Evex)|F(Vec) , X(K)|X(Z) , 580, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #428 [ref=1x] + { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 325, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #429 [ref=2x] + { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 579, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #430 [ref=1x] + { F(EvexTransformable)|F(Vec)|F(Vex) , 0 , 580, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #431 [ref=1x] + { F(Evex)|F(Vec) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 298, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #432 [ref=1x] + { F(Vec)|F(Vex) , 0 , 598, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #433 [ref=1x] + { F(Vec)|F(Vex) , 0 , 599, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #434 [ref=1x] + { F(Vec)|F(Vex) , 0 , 600, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #435 [ref=1x] + { F(Evex)|F(Vec) , X(B32)|X(K)|X(Z) , 302, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #436 [ref=2x] + { F(Evex)|F(Vec) , X(B64)|X(K)|X(Z) , 302, 2 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #437 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(K)|X(Z) , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #438 [ref=1x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B32)|X(K)|X(Z) , 301, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #439 [ref=1x] + { F(Vec)|F(Vex) , 0 , 298, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #440 [ref=2x] + { F(Evex)|F(EvexCompat)|F(Vec)|F(Vex) , X(B64)|X(ER)|X(K)|X(SAE)|X(Z) , 151, 3 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #441 [ref=1x] + { F(Vec)|F(Vex) , 0 , 145, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #442 [ref=2x] + { 0 , 0 , 22 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #443 [ref=2x] + { 0 , 0 , 23 , 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #444 [ref=2x] + { F(Lock)|F(XAcquire)|F(XRelease) , 0 , 20 , 4 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #445 [ref=1x] + { 0 , 0 , 269, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #446 [ref=1x] + { F(XAcquire) , 0 , 131, 8 , CONTROL_FLOW(Regular), SAME_REG_HINT(RO)}, // #447 [ref=1x] + { 0 , 0 , 601, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)}, // #448 [ref=6x] + { 0 , 0 , 602, 1 , CONTROL_FLOW(Regular), SAME_REG_HINT(None)} // #449 [ref=6x] }; #undef SAME_REG_HINT #undef CONTROL_FLOW @@ -2659,7 +2566,7 @@ const InstDB::CommonInfo InstDB::_commonInfoTable[] = { #define EXT(VAL) uint32_t(CpuFeatures::X86::k##VAL) const InstDB::AdditionalInfo InstDB::_additionalInfoTable[] = { { 0, 0, { 0 } }, // #0 [ref=68x] - { 0, 1, { 0 } }, // #1 [ref=32x] + { 0, 1, { 0 } }, // #1 [ref=31x] { 0, 0, { EXT(RAO_INT) } }, // #2 [ref=4x] { 0, 2, { 0 } }, // #3 [ref=2x] { 0, 3, { EXT(ADX) } }, // #4 [ref=1x] @@ -2688,13 +2595,13 @@ const InstDB::AdditionalInfo InstDB::_additionalInfoTable[] = { { 0, 0, { EXT(CLWB) } }, // #27 [ref=1x] { 0, 0, { EXT(CLZERO) } }, // #28 [ref=1x] { 0, 3, { 0 } }, // #29 [ref=1x] - { 0, 11, { EXT(CMOV) } }, // #30 [ref=4x] - { 0, 12, { EXT(CMOV) } }, // #31 [ref=6x] - { 0, 13, { EXT(CMOV) } }, // #32 [ref=4x] - { 0, 14, { EXT(CMOV) } }, // #33 [ref=4x] - { 0, 15, { EXT(CMOV) } }, // #34 [ref=4x] + { 0, 11, { EXT(CMOV) } }, // #30 [ref=2x] + { 0, 12, { EXT(CMOV) } }, // #31 [ref=2x] + { 0, 13, { EXT(CMOV) } }, // #32 [ref=2x] + { 0, 14, { EXT(CMOV) } }, // #33 [ref=2x] + { 0, 15, { EXT(CMOV) } }, // #34 [ref=2x] { 0, 16, { EXT(CMOV) } }, // #35 [ref=2x] - { 0, 17, { EXT(CMOV) } }, // #36 [ref=4x] + { 0, 17, { EXT(CMOV) } }, // #36 [ref=2x] { 0, 18, { EXT(CMOV) } }, // #37 [ref=2x] { 0, 1, { EXT(CMPCCXADD) } }, // #38 [ref=16x] { 0, 19, { 0 } }, // #39 [ref=2x] @@ -2724,19 +2631,19 @@ const InstDB::AdditionalInfo InstDB::_additionalInfoTable[] = { { 0, 0, { EXT(GFNI) } }, // #63 [ref=3x] { 0, 0, { EXT(HRESET) } }, // #64 [ref=1x] { 0, 0, { EXT(CET_SS) } }, // #65 [ref=9x] - { 0, 16, { 0 } }, // #66 [ref=5x] + { 0, 15, { 0 } }, // #66 [ref=5x] { 0, 0, { EXT(VMX) } }, // #67 [ref=13x] { 0, 0, { EXT(INVLPGB) } }, // #68 [ref=2x] - { 0, 11, { 0 } }, // #69 [ref=8x] - { 0, 12, { 0 } }, // #70 [ref=12x] - { 0, 13, { 0 } }, // #71 [ref=10x] - { 0, 14, { 0 } }, // #72 [ref=8x] - { 0, 15, { 0 } }, // #73 [ref=8x] - { 0, 17, { 0 } }, // #74 [ref=8x] - { 0, 18, { 0 } }, // #75 [ref=4x] - { 0, 0, { EXT(AVX512_DQ) } }, // #76 [ref=22x] + { 0, 11, { 0 } }, // #69 [ref=4x] + { 0, 12, { 0 } }, // #70 [ref=4x] + { 0, 13, { 0 } }, // #71 [ref=4x] + { 0, 14, { 0 } }, // #72 [ref=4x] + { 0, 16, { 0 } }, // #73 [ref=4x] + { 0, 17, { 0 } }, // #74 [ref=4x] + { 0, 18, { 0 } }, // #75 [ref=6x] + { 0, 0, { EXT(AVX512_DQ) } }, // #76 [ref=10x] { 0, 0, { EXT(AVX512_BW) } }, // #77 [ref=20x] - { 0, 0, { EXT(AVX512_F) } }, // #78 [ref=36x] + { 0, 0, { EXT(AVX512_F) } }, // #78 [ref=9x] { 1, 0, { EXT(AVX512_DQ) } }, // #79 [ref=1x] { 1, 0, { EXT(AVX512_BW) } }, // #80 [ref=2x] { 1, 0, { EXT(AVX512_F) } }, // #81 [ref=1x] @@ -2781,7 +2688,7 @@ const InstDB::AdditionalInfo InstDB::_additionalInfoTable[] = { { 0, 1, { EXT(SEV_SNP) } }, // #120 [ref=1x] { 0, 32, { 0 } }, // #121 [ref=2x] { 0, 0, { EXT(FSGSBASE) } }, // #122 [ref=4x] - { 0, 0, { EXT(MSR) } }, // #123 [ref=2x] + { 0, 0, { EXT(MSR), EXT(MSR_IMM) } }, // #123 [ref=1x] { 0, 0, { EXT(RDPID) } }, // #124 [ref=1x] { 0, 0, { EXT(OSPKE) } }, // #125 [ref=1x] { 0, 0, { EXT(RDPRU) } }, // #126 [ref=1x] @@ -2802,76 +2709,68 @@ const InstDB::AdditionalInfo InstDB::_additionalInfoTable[] = { { 0, 1, { EXT(UINTR) } }, // #141 [ref=1x] { 0, 1, { EXT(WAITPKG) } }, // #142 [ref=2x] { 0, 0, { EXT(WAITPKG) } }, // #143 [ref=1x] - { 0, 0, { EXT(AVX512_4FMAPS) } }, // #144 [ref=4x] - { 0, 0, { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) } }, // #145 [ref=38x] - { 0, 0, { EXT(AVX512_FP16), EXT(AVX512_VL) } }, // #146 [ref=60x] - { 0, 0, { EXT(AVX), EXT(AVX512_F) } }, // #147 [ref=33x] - { 0, 0, { EXT(AVX512_FP16) } }, // #148 [ref=44x] - { 0, 0, { EXT(AVX) } }, // #149 [ref=35x] - { 0, 0, { EXT(AESNI), EXT(VAES), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) } }, // #150 [ref=4x] - { 0, 0, { EXT(AESNI), EXT(AVX) } }, // #151 [ref=2x] - { 0, 0, { EXT(AVX512_F), EXT(AVX512_VL) } }, // #152 [ref=108x] - { 0, 0, { EXT(AVX), EXT(AVX512_DQ), EXT(AVX512_VL) } }, // #153 [ref=8x] - { 0, 0, { EXT(AVX_NE_CONVERT) } }, // #154 [ref=6x] - { 0, 0, { EXT(AVX512_DQ), EXT(AVX512_VL) } }, // #155 [ref=30x] - { 0, 0, { EXT(AVX2) } }, // #156 [ref=7x] - { 0, 0, { EXT(AVX), EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) } }, // #157 [ref=39x] - { 0, 1, { EXT(AVX), EXT(AVX512_F) } }, // #158 [ref=4x] - { 0, 1, { EXT(AVX512_FP16) } }, // #159 [ref=2x] - { 0, 0, { EXT(AVX512_BF16), EXT(AVX512_VL) } }, // #160 [ref=2x] - { 0, 0, { EXT(AVX_NE_CONVERT), EXT(AVX512_BF16), EXT(AVX512_VL) } }, // #161 [ref=1x] - { 0, 0, { EXT(F16C), EXT(AVX512_F), EXT(AVX512_VL) } }, // #162 [ref=2x] - { 0, 0, { EXT(AVX512_BW), EXT(AVX512_VL) } }, // #163 [ref=24x] - { 0, 0, { EXT(AVX512_ER) } }, // #164 [ref=10x] - { 0, 0, { EXT(FMA), EXT(AVX512_F), EXT(AVX512_VL) } }, // #165 [ref=36x] - { 0, 0, { EXT(FMA), EXT(AVX512_F) } }, // #166 [ref=24x] - { 0, 0, { EXT(FMA4) } }, // #167 [ref=20x] - { 0, 0, { EXT(XOP) } }, // #168 [ref=55x] - { 0, 0, { EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) } }, // #169 [ref=19x] - { 0, 0, { EXT(AVX512_PF) } }, // #170 [ref=16x] - { 0, 0, { EXT(GFNI), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) } }, // #171 [ref=3x] - { 0, 0, { EXT(SEV_ES) } }, // #172 [ref=1x] - { 1, 0, { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) } }, // #173 [ref=4x] - { 1, 0, { EXT(AVX) } }, // #174 [ref=2x] - { 1, 0, { EXT(AVX512_F), EXT(AVX512_VL) } }, // #175 [ref=4x] - { 1, 0, { EXT(AVX512_BW), EXT(AVX512_VL) } }, // #176 [ref=2x] - { 1, 0, { EXT(AVX), EXT(AVX512_F) } }, // #177 [ref=3x] - { 0, 0, { EXT(AVX), EXT(AVX2) } }, // #178 [ref=17x] - { 0, 0, { EXT(AVX512_VL), EXT(AVX512_VP2INTERSECT) } }, // #179 [ref=2x] - { 0, 0, { EXT(AVX512_4VNNIW) } }, // #180 [ref=2x] - { 0, 0, { EXT(AVX), EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) } }, // #181 [ref=54x] - { 0, 0, { EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) } }, // #182 [ref=2x] - { 0, 0, { EXT(AVX512_CD), EXT(AVX512_VL) } }, // #183 [ref=6x] - { 0, 0, { EXT(PCLMULQDQ), EXT(VPCLMULQDQ), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) } }, // #184 [ref=1x] - { 0, 1, { EXT(AVX) } }, // #185 [ref=7x] - { 0, 0, { EXT(AVX512_VBMI2), EXT(AVX512_VL) } }, // #186 [ref=16x] - { 0, 0, { EXT(AVX_VNNI_INT8) } }, // #187 [ref=6x] - { 0, 0, { EXT(AVX_VNNI), EXT(AVX512_VL), EXT(AVX512_VNNI) } }, // #188 [ref=4x] - { 0, 0, { EXT(AVX_VNNI_INT16) } }, // #189 [ref=6x] - { 0, 0, { EXT(AVX512_VBMI), EXT(AVX512_VL) } }, // #190 [ref=4x] - { 0, 0, { EXT(AVX), EXT(AVX512_BW) } }, // #191 [ref=4x] - { 0, 0, { EXT(AVX), EXT(AVX512_DQ) } }, // #192 [ref=4x] - { 0, 0, { EXT(AVX_IFMA), EXT(AVX512_IFMA), EXT(AVX512_VL) } }, // #193 [ref=2x] - { 0, 0, { EXT(AVX512_BITALG), EXT(AVX512_VL) } }, // #194 [ref=3x] - { 0, 0, { EXT(AVX512_VL), EXT(AVX512_VPOPCNTDQ) } }, // #195 [ref=2x] - { 0, 0, { EXT(SHA512), EXT(AVX) } }, // #196 [ref=3x] - { 0, 0, { EXT(SM3), EXT(AVX) } }, // #197 [ref=3x] - { 0, 0, { EXT(SM4), EXT(AVX) } }, // #198 [ref=2x] - { 0, 0, { EXT(WBNOINVD) } }, // #199 [ref=1x] - { 0, 0, { EXT(RTM) } }, // #200 [ref=3x] - { 0, 0, { EXT(XSAVE) } }, // #201 [ref=6x] - { 0, 0, { EXT(TSXLDTRK) } }, // #202 [ref=2x] - { 0, 0, { EXT(XSAVES) } }, // #203 [ref=4x] - { 0, 0, { EXT(XSAVEC) } }, // #204 [ref=2x] - { 0, 0, { EXT(XSAVEOPT) } }, // #205 [ref=2x] - { 0, 1, { EXT(TSX) } } // #206 [ref=1x] + { 0, 0, { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) } }, // #144 [ref=71x] + { 0, 0, { EXT(AVX512_FP16), EXT(AVX512_VL) } }, // #145 [ref=104x] + { 0, 0, { EXT(AVX) } }, // #146 [ref=35x] + { 0, 0, { EXT(AESNI), EXT(VAES), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) } }, // #147 [ref=4x] + { 0, 0, { EXT(AESNI), EXT(AVX) } }, // #148 [ref=2x] + { 0, 0, { EXT(AVX512_F), EXT(AVX512_VL) } }, // #149 [ref=135x] + { 0, 0, { EXT(AVX), EXT(AVX512_DQ), EXT(AVX512_VL) } }, // #150 [ref=12x] + { 0, 0, { EXT(AVX_NE_CONVERT) } }, // #151 [ref=6x] + { 0, 0, { EXT(AVX512_DQ), EXT(AVX512_VL) } }, // #152 [ref=42x] + { 0, 0, { EXT(AVX2) } }, // #153 [ref=7x] + { 0, 0, { EXT(AVX), EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) } }, // #154 [ref=39x] + { 0, 1, { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) } }, // #155 [ref=4x] + { 0, 1, { EXT(AVX512_FP16), EXT(AVX512_VL) } }, // #156 [ref=2x] + { 0, 0, { EXT(AVX512_BF16), EXT(AVX512_VL) } }, // #157 [ref=2x] + { 0, 0, { EXT(AVX_NE_CONVERT), EXT(AVX512_BF16), EXT(AVX512_VL) } }, // #158 [ref=1x] + { 0, 0, { EXT(F16C), EXT(AVX512_F), EXT(AVX512_VL) } }, // #159 [ref=2x] + { 0, 0, { EXT(AVX512_BW), EXT(AVX512_VL) } }, // #160 [ref=24x] + { 0, 0, { EXT(FMA), EXT(AVX512_F), EXT(AVX512_VL) } }, // #161 [ref=60x] + { 0, 0, { EXT(FMA4) } }, // #162 [ref=20x] + { 0, 0, { EXT(XOP) } }, // #163 [ref=55x] + { 0, 0, { EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) } }, // #164 [ref=19x] + { 0, 0, { EXT(GFNI), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) } }, // #165 [ref=3x] + { 0, 0, { EXT(SEV_ES) } }, // #166 [ref=1x] + { 1, 0, { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) } }, // #167 [ref=7x] + { 1, 0, { EXT(AVX) } }, // #168 [ref=2x] + { 1, 0, { EXT(AVX512_F), EXT(AVX512_VL) } }, // #169 [ref=4x] + { 1, 0, { EXT(AVX512_BW), EXT(AVX512_VL) } }, // #170 [ref=2x] + { 0, 0, { EXT(AVX), EXT(AVX2) } }, // #171 [ref=17x] + { 0, 0, { EXT(AVX512_VL), EXT(AVX512_VP2INTERSECT) } }, // #172 [ref=2x] + { 0, 0, { EXT(AVX), EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) } }, // #173 [ref=54x] + { 0, 0, { EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) } }, // #174 [ref=2x] + { 0, 0, { EXT(AVX512_CD), EXT(AVX512_VL) } }, // #175 [ref=6x] + { 0, 0, { EXT(PCLMULQDQ), EXT(VPCLMULQDQ), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) } }, // #176 [ref=1x] + { 0, 1, { EXT(AVX) } }, // #177 [ref=7x] + { 0, 0, { EXT(AVX512_VBMI2), EXT(AVX512_VL) } }, // #178 [ref=16x] + { 0, 0, { EXT(AVX_VNNI_INT8) } }, // #179 [ref=6x] + { 0, 0, { EXT(AVX_VNNI), EXT(AVX512_VL), EXT(AVX512_VNNI) } }, // #180 [ref=4x] + { 0, 0, { EXT(AVX_VNNI_INT16) } }, // #181 [ref=6x] + { 0, 0, { EXT(AVX512_VBMI), EXT(AVX512_VL) } }, // #182 [ref=4x] + { 0, 0, { EXT(AVX), EXT(AVX512_BW), EXT(AVX512_VL) } }, // #183 [ref=4x] + { 0, 0, { EXT(AVX_IFMA), EXT(AVX512_IFMA), EXT(AVX512_VL) } }, // #184 [ref=2x] + { 0, 0, { EXT(AVX512_BITALG), EXT(AVX512_VL) } }, // #185 [ref=3x] + { 0, 0, { EXT(AVX512_VL), EXT(AVX512_VPOPCNTDQ) } }, // #186 [ref=2x] + { 0, 0, { EXT(SHA512), EXT(AVX) } }, // #187 [ref=3x] + { 0, 0, { EXT(SM3), EXT(AVX) } }, // #188 [ref=3x] + { 0, 0, { EXT(SM4), EXT(AVX) } }, // #189 [ref=2x] + { 0, 0, { EXT(WBNOINVD) } }, // #190 [ref=1x] + { 0, 0, { EXT(MSR) } }, // #191 [ref=1x] + { 0, 0, { EXT(RTM) } }, // #192 [ref=3x] + { 0, 0, { EXT(XSAVE) } }, // #193 [ref=6x] + { 0, 0, { EXT(TSXLDTRK) } }, // #194 [ref=2x] + { 0, 0, { EXT(XSAVES) } }, // #195 [ref=4x] + { 0, 0, { EXT(XSAVEC) } }, // #196 [ref=2x] + { 0, 0, { EXT(XSAVEOPT) } }, // #197 [ref=2x] + { 0, 1, { EXT(RTM) } } // #198 [ref=1x] }; #undef EXT #define FLAG(VAL) uint32_t(CpuRWFlags::kX86_##VAL) const InstDB::RWFlagsInfoTable InstDB::_rwFlagsInfoTable[] = { - { 0, 0 }, // #0 [ref=1384x] - { 0, FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #1 [ref=104x] + { 0, 0 }, // #0 [ref=1352x] + { 0, FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #1 [ref=103x] { FLAG(CF), FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #2 [ref=2x] { FLAG(CF), FLAG(CF) }, // #3 [ref=2x] { FLAG(OF), FLAG(OF) }, // #4 [ref=1x] @@ -2881,14 +2780,14 @@ const InstDB::RWFlagsInfoTable InstDB::_rwFlagsInfoTable[] = { { 0, FLAG(CF) }, // #8 [ref=2x] { 0, FLAG(DF) }, // #9 [ref=2x] { 0, FLAG(IF) }, // #10 [ref=2x] - { FLAG(CF) | FLAG(ZF), 0 }, // #11 [ref=12x] - { FLAG(CF), 0 }, // #12 [ref=18x] - { FLAG(ZF), 0 }, // #13 [ref=14x] - { FLAG(OF) | FLAG(SF) | FLAG(ZF), 0 }, // #14 [ref=12x] - { FLAG(OF) | FLAG(SF), 0 }, // #15 [ref=12x] - { FLAG(OF), 0 }, // #16 [ref=7x] - { FLAG(PF), 0 }, // #17 [ref=12x] - { FLAG(SF), 0 }, // #18 [ref=6x] + { FLAG(CF), 0 }, // #11 [ref=6x] + { FLAG(CF) | FLAG(ZF), 0 }, // #12 [ref=6x] + { FLAG(OF) | FLAG(SF), 0 }, // #13 [ref=6x] + { FLAG(OF) | FLAG(SF) | FLAG(ZF), 0 }, // #14 [ref=6x] + { FLAG(OF), 0 }, // #15 [ref=7x] + { FLAG(PF), 0 }, // #16 [ref=6x] + { FLAG(SF), 0 }, // #17 [ref=6x] + { FLAG(ZF), 0 }, // #18 [ref=8x] { FLAG(DF), FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #19 [ref=2x] { 0, FLAG(AF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #20 [ref=5x] { 0, FLAG(C0) | FLAG(C1) | FLAG(C2) | FLAG(C3) }, // #21 [ref=83x] @@ -2910,7 +2809,7 @@ const InstDB::RWFlagsInfoTable InstDB::_rwFlagsInfoTable[] = { #define FLAG(VAL) uint32_t(InstRWFlags::k##VAL) const InstRWFlags InstDB::_instFlagsTable[] = { - InstRWFlags(FLAG(None)), // #0 [ref=1694x] + InstRWFlags(FLAG(None)), // #0 [ref=1619x] InstRWFlags(FLAG(MovOp)) // #1 [ref=29x] }; #undef FLAG @@ -2933,7 +2832,7 @@ const InstNameIndex InstDB::instNameIndex = {{ { Inst::kIdGetsec , Inst::kIdGf2p8mulb + 1 }, { Inst::kIdHaddpd , Inst::kIdHsubps + 1 }, { Inst::kIdIdiv , Inst::kIdIretq + 1 }, - { Inst::kIdJa , Inst::kIdJz + 1 }, + { Inst::kIdJb , Inst::kIdJz + 1 }, { Inst::kIdKaddb , Inst::kIdKxorw + 1 }, { Inst::kIdLahf , Inst::kIdLzcnt + 1 }, { Inst::kIdMaskmovdqu , Inst::kIdMwaitx + 1 }, @@ -2945,7 +2844,7 @@ const InstNameIndex InstDB::instNameIndex = {{ { Inst::kIdSahf , Inst::kIdSysretq + 1 }, { Inst::kIdT1mskc , Inst::kIdTzmsk + 1 }, { Inst::kIdUcomisd , Inst::kIdUnpcklps + 1 }, - { Inst::kIdV4fmaddps , Inst::kIdVzeroupper + 1 }, + { Inst::kIdVaddpd , Inst::kIdVzeroupper + 1 }, { Inst::kIdWbinvd , Inst::kIdWrussq + 1 }, { Inst::kIdXabort , Inst::kIdXtest + 1 }, { Inst::kIdNone , Inst::kIdNone + 1 }, @@ -2953,33 +2852,94 @@ const InstNameIndex InstDB::instNameIndex = {{ }, uint16_t(17)}; const char InstDB::_instNameStringTable[] = - "vgf2p8affineinvqbvaeskeygenassistvbroadcastf32x464x264x4i32x2i32x4i32x8i64x2i64x" - "4vpbroadcastmb2w2dvbcstnebf162p128i128vcvtne2ps2vcvtneebf16vcvtneobf16vfmaddsub1" - "32ph213pd213ph213ps231pd231ph231psvfmsubadd132vpmultishiftvscatterpf0dqpdqps1dpd" - "1dps1qpd1qpsvcvtneps2vextracvextractfvgatherpf0vp2intersecttcmmimfp16tcmmrlfp16s" - "h2pssdph2psvfnmadd132213sd213sh213ss231sd231sh231ssvfnmsub132vinservinsertfvpshu" - "fbitqvsha512rndprefetchitntawt1saveprevsssha256rndtileloaddtilereleavaesdeclvaes" - "enclvcompressvcvttpd2uqqvcvttph2uvcvttps2uvcvttsd2uvcvttsh2uvcvttss2uvfixupimmvf" - "madd132vfmsub132vmaskmovdqvpcompressvpconflictvphminposuvpmadd52hluqvpscatterqdv" - "punpckhqlqdqvrndscalemsg1msg2clflushopcmpnbexcmpnlexcmpxchg16t0t2tilestorev4fnma" - "ddssvcvtpd2uvcvtph2psudqvcvtps2phvcvtsd2uvcvtsh2uvcvtss2uvcvtudq2vcvtuqq2vcvtusi" - "2vfcmaddcvfpclassvgetmanmulbvp4dpwssvpclmuvpcmpestrvpcmpistrvperm2fvpermil2vpgat" - "hervpmacssdqvpmadcsswubswvpmaskmovpternlogbwwdlbwldqlwdvrsqrt1428pd28ps28sd28ssv" - "shufvshuffvzeroupxsaveoptcmpbexcmplexcmpnbxcmpnlxcmpnoxcmpnpxcmpnsxcmpnzx8bfxrst" - "orldtilecfmovdir64pvalidarmpadjurmpupdaserialisha1nexsha1rndssttilecftdpbf16tdpf" - "p16v4fmadvaddsubvblendmvpdvcvtdq2uwvcvtqq2vcvtsi2vcvtuwvdbpsadvdpbf16vexpanvfcmu" - "lccphcshvgetexpvmovdqau16u32u64vmovmskvmovntvmovshdvmovsldvpackssdwbvpackuswbvpb" - "lendmdvpdpbssudsvpdpbusvpdpwssvpdpwus2pdvpermtvpexpanvphaddubwqdqhvpmovmskvpmovs" - "xbvpmovusqwvpmovzxbvpmulhrvptestnmqvreducevscalefvsm3rndvsm4rndsvunpckhlpdlpsxre" - "sldtrs64xsusldtrcldemoclrssbscmpbxcmplxcmpoxcmppxcmpsxcmpzxcvtpifcmovfxsavekorte" - "stkshiftrbkunpckmonitorpfrcpipfrsqirtvrdfsbrdgsbsspseamcalsenduisetssbssysesysex" - "vcvtwvfmulvldmxcsvmlaundupu8vmovhvmovlhvmpsadvmresumvpadduvpaligngtbgtdgtqgtw2b2" - "qbdbqvphsubvplzcnb2md2mq2mw2mvpopcnvpshldvqvpshrdvwhwvpsubuvrangevrcp14vroundsdv" - "sm4keyvstmxcsvucomiallwbnoinwrfsbwrgsbc64blcfiblsficmovnendbrenqcmnufdecsfincsfn" - "stefrndfsincfucomfyl2xincsspqinvlinvlpinvpcinvvpmcommmovq2pavgupfcmpepfpnaptwris" - "eamoseamrsyscsysretdpbutlbsyvaesivaligvandnvcomivfrczvhadvhsubvmclevmgexvmmcvmov" - "avmovuvmptvmwrivpandvpextrwvpinsvpmaxvpminvprolvprorvpsadvpsigvpslvpsllvpsravpsr" - "lvsqrvtes"; + "\x63\x6D\x6F\x76\x62\x0C\x63\x6D\x6F\x76\x2E\x62\x7C\x6E\x61\x65\x7C\x63\x63\x6D\x6F\x76\x62\x65\x0A\x63\x6D\x6F\x76" + "\x2E\x62\x65\x7C\x6E\x61\x63\x6D\x6F\x76\x6C\x0A\x63\x6D\x6F\x76\x2E\x6C\x7C\x6E\x67\x65\x63\x6D\x6F\x76\x6C\x65\x0A" + "\x63\x6D\x6F\x76\x2E\x6C\x65\x7C\x6E\x67\x63\x6D\x6F\x76\x6E\x62\x0D\x63\x6D\x6F\x76\x2E\x6E\x62\x7C\x61\x65\x7C\x6E" + "\x63\x63\x6D\x6F\x76\x6E\x62\x65\x0A\x63\x6D\x6F\x76\x2E\x6E\x62\x65\x7C\x61\x63\x6D\x6F\x76\x6E\x6C\x0A\x63\x6D\x6F" + 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"\x76\x6D\x63\x6C\x65\x76\x6D\x67\x65\x78\x76\x6D\x6D\x63\x76\x6D\x6F\x76\x61\x76\x6D\x6F\x76\x75\x76\x6D\x70\x74\x76" + "\x6D\x77\x72\x69\x76\x70\x61\x6E\x64\x76\x70\x65\x78\x74\x72\x77\x76\x70\x69\x6E\x73\x76\x70\x6D\x61\x78\x76\x70\x6D" + "\x69\x6E\x76\x70\x72\x6F\x6C\x76\x70\x72\x6F\x72\x76\x70\x73\x61\x64\x76\x70\x73\x69\x67\x76\x70\x73\x6C\x76\x70\x73" + "\x6C\x6C\x76\x70\x73\x72\x61\x76\x70\x73\x72\x6C\x76\x73\x71\x72\x76\x74\x65\x73"; const uint32_t InstDB::_instNameIndexTable[] = { @@ -2997,15 +2957,15 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x81381081, // Small 'addps'. 0x80499081, // Small 'addsd'. 0x81399081, // Small 'addss'. - 0x20A76099, // Large 'addsub|pd'. - 0x207D6099, // Large 'addsub|ps'. + 0x22AC629E, // Large 'addsub|pd'. + 0x2282629E, // Large 'addsub|ps'. 0x800C3C81, // Small 'adox'. 0x86524CA1, // Small 'aesdec'. - 0x302871D5, // Large 'aesdecl|ast'. + 0x322D73AE, // Large 'aesdecl|ast'. 0x86E2CCA1, // Small 'aesenc'. - 0x302871DD, // Large 'aesencl|ast'. + 0x322D73B6, // Large 'aesencl|ast'. 0x86D4CCA1, // Small 'aesimc'. - 0x0000F012, // Large 'aeskeygenassist'. + 0x1154E218, // Large 'aeskeygenassis|t'. 0x800011C1, // Small 'and'. 0x800711C1, // Small 'andn'. 0x890711C1, // Small 'andnpd'. @@ -3016,16 +2976,16 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x80064241, // Small 'arpl'. 0x80093F01, // Small 'axor'. 0x812A60A2, // Small 'bextr'. - 0x26F45709, // Large 'blcfi|ll'. + 0x28BA58CF, // Large 'blcfi|ll'. 0x80048D82, // Small 'blci'. 0x80348D82, // Small 'blcic'. 0x97368D82, // Small 'blcmsk'. 0x80098D82, // Small 'blcs'. - 0x20A75471, // Large 'blend|pd'. - 0x207D5471, // Large 'blend|ps'. - 0x34775471, // Large 'blend|vpd'. - 0x318B5471, // Large 'blend|vps'. - 0x26F4570E, // Large 'blsfi|ll'. + 0x22AC563C, // Large 'blend|pd'. + 0x2282563C, // Large 'blend|ps'. + 0x3642563C, // Large 'blend|vpd'. + 0x3364563C, // Large 'blend|vps'. + 0x28BA58D4, // Large 'blsfi|ll'. 0x8004CD82, // Small 'blsi'. 0x8034CD82, // Small 'blsic'. 0x9736CD82, // Small 'blsmsk'. @@ -3053,99 +3013,85 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x80018583, // Small 'clac'. 0x80000D83, // Small 'clc'. 0x80001183, // Small 'cld'. - 0x20DF65B0, // Large 'cldemo|te'. - 0x0000729D, // Large 'clflush'. - 0x1020929D, // Large 'clflushop|t'. + 0x22FD677C, // Large 'cldemo|te'. + 0x00007486, // Large 'clflush'. + 0x11549486, // Large 'clflushop|t'. 0x80049D83, // Small 'clgi'. 0x80002583, // Small 'cli'. - 0x101775B6, // Large 'clrssbs|y'. + 0x121D7782, // Large 'clrssbs|y'. 0x8009D183, // Small 'clts'. 0x8004D583, // Small 'clui'. 0x80015D83, // Small 'clwb'. 0x9F22E983, // Small 'clzero'. 0x80000DA3, // Small 'cmc'. - 0x801B3DA3, // Small 'cmova'. - 0x8A1B3DA3, // Small 'cmovae'. - 0x802B3DA3, // Small 'cmovb'. - 0x8A2B3DA3, // Small 'cmovbe'. - 0x803B3DA3, // Small 'cmovc'. - 0x805B3DA3, // Small 'cmove'. - 0x807B3DA3, // Small 'cmovg'. - 0x8A7B3DA3, // Small 'cmovge'. - 0x80CB3DA3, // Small 'cmovl'. - 0x8ACB3DA3, // Small 'cmovle'. - 0x82EB3DA3, // Small 'cmovna'. - 0x20125713, // Large 'cmovn|ae'. - 0x84EB3DA3, // Small 'cmovnb'. - 0x22AA5713, // Large 'cmovn|be'. - 0x86EB3DA3, // Small 'cmovnc'. - 0x8AEB3DA3, // Small 'cmovne'. - 0x8EEB3DA3, // Small 'cmovng'. - 0x20185713, // Large 'cmovn|ge'. - 0x98EB3DA3, // Small 'cmovnl'. - 0x21C45713, // Large 'cmovn|le'. + 0x0FFF5000, // Large 'cmovb' + 'cmov.b|nae|c' + 0x0FFF6012, // Large 'cmovbe' + 'cmov.be|na' + 0x0FFF5023, // Large 'cmovl' + 'cmov.l|nge' + 0x0FFF6033, // Large 'cmovle' + 'cmov.le|ng' + 0x0FFF6044, // Large 'cmovnb' + 'cmov.nb|ae|nc' + 0x0FFF7058, // Large 'cmovnbe' + 'cmov.nbe|a' + 0x0FFF606A, // Large 'cmovnl' + 'cmov.nl|ge' + 0x0FFF707B, // Large 'cmovnle' + 'cmov.nle|g' 0x9EEB3DA3, // Small 'cmovno'. - 0xA0EB3DA3, // Small 'cmovnp'. + 0x0FFF608D, // Large 'cmovnp' + 'cmov.np|po' 0xA6EB3DA3, // Small 'cmovns'. - 0xB4EB3DA3, // Small 'cmovnz'. + 0x0FFF609E, // Large 'cmovnz' + 'cmov.nz|ne' 0x80FB3DA3, // Small 'cmovo'. - 0x810B3DA3, // Small 'cmovp'. - 0x8B0B3DA3, // Small 'cmovpe'. - 0x9F0B3DA3, // Small 'cmovpo'. + 0x0FFF50AF, // Large 'cmovp' + 'cmov.p|pe' 0x813B3DA3, // Small 'cmovs'. - 0x81AB3DA3, // Small 'cmovz'. + 0x0FFF50BE, // Large 'cmovz' + 'cmov.z|e' 0x800041A3, // Small 'cmp'. - 0x309963D9, // Large 'cmpbex|add'. - 0x309955BD, // Large 'cmpbx|add'. - 0x309963DF, // Large 'cmplex|add'. - 0x309955C2, // Large 'cmplx|add'. - 0x309972A6, // Large 'cmpnbex|add'. - 0x309963E5, // Large 'cmpnbx|add'. - 0x309972AD, // Large 'cmpnlex|add'. - 0x309963EB, // Large 'cmpnlx|add'. - 0x309963F1, // Large 'cmpnox|add'. - 0x309963F7, // Large 'cmpnpx|add'. - 0x309963FD, // Large 'cmpnsx|add'. - 0x30996403, // Large 'cmpnzx|add'. - 0x309955C7, // Large 'cmpox|add'. + 0x329E65A7, // Large 'cmpbex|add'. + 0x329E5789, // Large 'cmpbx|add'. + 0x329E65AD, // Large 'cmplex|add'. + 0x329E578E, // Large 'cmplx|add'. + 0x329E748F, // Large 'cmpnbex|add'. + 0x329E65B3, // Large 'cmpnbx|add'. + 0x329E7496, // Large 'cmpnlex|add'. + 0x329E65B9, // Large 'cmpnlx|add'. + 0x329E65BF, // Large 'cmpnox|add'. + 0x329E65C5, // Large 'cmpnpx|add'. + 0x329E65CB, // Large 'cmpnsx|add'. + 0x329E65D1, // Large 'cmpnzx|add'. + 0x329E5793, // Large 'cmpox|add'. 0x804841A3, // Small 'cmppd'. 0x813841A3, // Small 'cmpps'. - 0x309955CC, // Large 'cmppx|add'. + 0x329E5798, // Large 'cmppx|add'. 0x8009C1A3, // Small 'cmps'. 0x8049C1A3, // Small 'cmpsd'. 0x8139C1A3, // Small 'cmpss'. - 0x309955D1, // Large 'cmpsx|add'. - 0x000072B4, // Large 'cmpxchg'. - 0x101092B4, // Large 'cmpxchg16|b'. - 0x240972B4, // Large 'cmpxchg|8b'. - 0x309955D6, // Large 'cmpzx|add'. + 0x329E579D, // Large 'cmpsx|add'. + 0x0000749D, // Large 'cmpxchg'. + 0x1004949D, // Large 'cmpxchg16|b'. + 0x25D7749D, // Large 'cmpxchg|8b'. + 0x329E57A2, // Large 'cmpzx|add'. 0x8934B5E3, // Small 'comisd'. 0xA734B5E3, // Small 'comiss'. 0x8044D603, // Small 'cpuid'. 0x80003E23, // Small 'cqo'. 0x81DF0E43, // Small 'crc32'. - 0x20A7647B, // Large 'cvtdq2|pd'. - 0x207D647B, // Large 'cvtdq2|ps'. - 0x20E562D5, // Large 'cvtpd2|dq'. - 0x222A62D5, // Large 'cvtpd2|pi'. - 0x207D62D5, // Large 'cvtpd2|ps'. - 0x352555DB, // Large 'cvtpi|2pd'. - 0x307C55DB, // Large 'cvtpi|2ps'. - 0x20E562E9, // Large 'cvtps2|dq'. - 0x102672E9, // Large 'cvtps2p|d'. - 0x100972E9, // Large 'cvtps2p|i'. - 0x201D62F2, // Large 'cvtsd2|si'. - 0x201C62F2, // Large 'cvtsd2|ss'. - 0x2144648B, // Large 'cvtsi2|sd'. - 0x201C648B, // Large 'cvtsi2|ss'. - 0x21446302, // Large 'cvtss2|sd'. - 0x201D6302, // Large 'cvtss2|si'. - 0x20E571EE, // Large 'cvttpd2|dq'. - 0x222A71EE, // Large 'cvttpd2|pi'. - 0x20E57202, // Large 'cvttps2|dq'. - 0x222A7202, // Large 'cvttps2|pi'. - 0x201D720B, // Large 'cvttsd2|si'. - 0x201D721D, // Large 'cvttss2|si'. + 0x22AC6646, // Large 'cvtdq2|pd'. + 0x22826646, // Large 'cvtdq2|ps'. + 0x34E154B2, // Large 'cvtpd|2dq'. + 0x35D954B2, // Large 'cvtpd|2pi'. + 0x328154B2, // Large 'cvtpd|2ps'. + 0x36F157A7, // Large 'cvtpi|2pd'. + 0x328157A7, // Large 'cvtpi|2ps'. + 0x23CF64C1, // Large 'cvtps2|dq'. + 0x122B74C1, // Large 'cvtps2p|d'. + 0x120F74C1, // Large 'cvtps2p|i'. + 0x222364CA, // Large 'cvtsd2|si'. + 0x222264CA, // Large 'cvtsd2|ss'. + 0x231D6656, // Large 'cvtsi2|sd'. + 0x22226656, // Large 'cvtsi2|ss'. + 0x231D64DA, // Large 'cvtss2|sd'. + 0x222364DA, // Large 'cvtss2|si'. + 0x23CF73C7, // Large 'cvttpd2|dq'. + 0x240473C7, // Large 'cvttpd2|pi'. + 0x34E163DE, // Large 'cvttps|2dq'. + 0x35D963DE, // Large 'cvttps|2pi'. + 0x222373E5, // Large 'cvttsd2|si'. + 0x222373F7, // Large 'cvttss2|si'. 0x800012E3, // Small 'cwd'. 0x800292E3, // Small 'cwde'. 0x80000424, // Small 'daa'. @@ -3159,12 +3105,12 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x80024204, // Small 'dppd'. 0x8009C204, // Small 'dpps'. 0x8009B5A5, // Small 'emms'. - 0x202C5718, // Large 'endbr|32'. - 0x20305718, // Large 'endbr|64'. + 0x223158D9, // Large 'endbr|32'. + 0x223558D9, // Large 'endbr|64'. 0x88D1C5C5, // Small 'enqcmd'. - 0x209B571D, // Large 'enqcm|ds'. + 0x22A058DE, // Large 'enqcm|ds'. 0x8122D1C5, // Small 'enter'. - 0x207D710D, // Large 'extract|ps'. + 0x228272F0, // Large 'extract|ps'. 0x81195305, // Small 'extrq'. 0x81C6E3A6, // Small 'f2xm1'. 0x80098826, // Small 'fabs'. @@ -3175,12 +3121,12 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x8009A066, // Small 'fchs'. 0x8182B066, // Small 'fclex'. 0x8567B466, // Small 'fcmovb'. - 0x22AA55E0, // Large 'fcmov|be'. + 0x40143500, // Large 'fcm|ovbe'. 0x8B67B466, // Small 'fcmove'. - 0x22A955E0, // Large 'fcmov|nb'. - 0x32A955E0, // Large 'fcmov|nbe'. - 0x200A55E0, // Large 'fcmov|ne'. - 0x272255E0, // Large 'fcmov|nu'. + 0x40463500, // Large 'fcm|ovnb'. + 0x505A3500, // Large 'fcm|ovnbe'. + 0x20AD58E3, // Large 'fcmov|ne'. + 0x28E858E3, // Large 'fcmov|nu'. 0xAB67B466, // Small 'fcmovu'. 0x8006BC66, // Small 'fcom'. 0x8096BC66, // Small 'fcomi'. @@ -3188,7 +3134,7 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x8106BC66, // Small 'fcomp'. 0xA106BC66, // Small 'fcompp'. 0x8009BC66, // Small 'fcos'. - 0x21F15724, // Large 'fdecs|tp'. + 0x21EF58EA, // Large 'fdecs|tp'. 0x800B2486, // Small 'fdiv'. 0x810B2486, // Small 'fdivp'. 0x812B2486, // Small 'fdivr'. @@ -3202,7 +3148,7 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0xA5649126, // Small 'fidivr'. 0x80023126, // Small 'fild'. 0x80CAB526, // Small 'fimul'. - 0x21F15729, // Large 'fincs|tp'. + 0x21EF58EF, // Large 'fincs|tp'. 0x8144B926, // Small 'finit'. 0x800A4D26, // Small 'fist'. 0x810A4D26, // Small 'fistp'. @@ -3226,18 +3172,18 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x80083DC6, // Small 'fnop'. 0x8B60CDC6, // Small 'fnsave'. 0xAE3A4DC6, // Small 'fnstcw'. - 0x200D572E, // Large 'fnste|nv'. + 0x221358F4, // Large 'fnste|nv'. 0xAF3A4DC6, // Small 'fnstsw'. 0x9C1A0606, // Small 'fpatan'. 0x80D2CA06, // Small 'fprem'. 0xB8D2CA06, // Small 'fprem1'. 0x80E0D206, // Small 'fptan'. - 0x31224733, // Large 'frnd|int'. + 0x32FB48F9, // Large 'frnd|int'. 0xA4FA4E46, // Small 'frstor'. 0x805B0666, // Small 'fsave'. 0x8AC08E66, // Small 'fscale'. 0x80072666, // Small 'fsin'. - 0x22655737, // Large 'fsinc|os'. + 0x21DD58FD, // Large 'fsinc|os'. 0x81494666, // Small 'fsqrt'. 0x80005266, // Small 'fst'. 0x8171D266, // Small 'fstcw'. @@ -3251,23 +3197,23 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x800A4E86, // Small 'ftst'. 0x80D78EA6, // Small 'fucom'. 0x92D78EA6, // Small 'fucomi'. - 0x260C573C, // Large 'fucom|ip'. + 0x27D45902, // Large 'fucom|ip'. 0xA0D78EA6, // Small 'fucomp'. - 0x25CE573C, // Large 'fucom|pp'. + 0x279A5902, // Large 'fucom|pp'. 0x814486E6, // Small 'fwait'. 0x80068706, // Small 'fxam'. 0x80040F06, // Small 'fxch'. - 0x0000740B, // Large 'fxrstor'. - 0x2030740B, // Large 'fxrstor|64'. + 0x000075DC, // Large 'fxrstor'. + 0x223575DC, // Large 'fxrstor|64'. 0x8B60CF06, // Small 'fxsave'. - 0x203065E5, // Large 'fxsave|64'. - 0x510F240B, // Large 'fx|tract'. + 0x223567AC, // Large 'fxsave|64'. + 0x52F225DC, // Large 'fx|tract'. 0x818EB326, // Small 'fyl2x'. - 0x206E5741, // Large 'fyl2x|p1'. + 0x22735907, // Large 'fyl2x|p1'. 0x8659D0A7, // Small 'getsec'. - 0x1010F001, // Large 'gf2p8affineinvq|b'. - 0x200FB001, // Large 'gf2p8affine|qb'. - 0x43385001, // Large 'gf2p8|mulb'. + 0x1004F207, // Large 'gf2p8affineinvq|b'. + 0x2215B207, // Large 'gf2p8affine|qb'. + 0x451E5207, // Large 'gf2p8|mulb'. 0x89021028, // Small 'haddpd'. 0xA7021028, // Small 'haddps'. 0x80005188, // Small 'hlt'. @@ -3278,56 +3224,42 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x800655A9, // Small 'imul'. 0x800001C9, // Small 'in'. 0x80000DC9, // Small 'inc'. - 0x20A75746, // Large 'incss|pd'. - 0x274B5746, // Large 'incss|pq'. + 0x22AC590C, // Large 'incss|pd'. + 0x2911590C, // Large 'incss|pq'. 0x80004DC9, // Small 'ins'. - 0x207D6184, // Large 'insert|ps'. - 0x100F6184, // Large 'insert|q'. + 0x2282635D, // Large 'insert|ps'. + 0x1215635D, // Large 'insert|q'. 0x800051C9, // Small 'int'. 0x800F51C9, // Small 'int3'. 0x8007D1C9, // Small 'into'. 0x800259C9, // Small 'invd'. 0xA902D9C9, // Small 'invept'. 0x8F0659C9, // Small 'invlpg'. - 0x336C474D, // Large 'invl|pga'. - 0x23995751, // Large 'invlp|gb'. - 0x24265756, // Large 'invpc|id'. - 0x2426575B, // Large 'invvp|id'. + 0x354A4913, // Large 'invl|pga'. + 0x25775917, // Large 'invlp|gb'. + 0x25F7591C, // Large 'invpc|id'. + 0x25F75921, // Large 'invvp|id'. 0x800A1649, // Small 'iret'. 0x804A1649, // Small 'iretd'. 0x811A1649, // Small 'iretq'. - 0x8000002A, // Small 'ja'. - 0x8000142A, // Small 'jae'. - 0x8000004A, // Small 'jb'. - 0x8000144A, // Small 'jbe'. - 0x8000006A, // Small 'jc'. - 0x800000AA, // Small 'je'. + 0x0FFF20CC, // Large 'jb' + 'jb|jnae|jc' + 0x0FFF30D9, // Large 'jbe' + 'jbe|jna' 0x81AC0CAA, // Small 'jecxz'. - 0x800000EA, // Small 'jg'. - 0x800014EA, // Small 'jge'. - 0x8000018A, // Small 'jl'. - 0x8000158A, // Small 'jle'. + 0x0FFF20E4, // Large 'jl' + 'jl|jnge' + 0x0FFF30EE, // Large 'jle' + 'jle|jng' 0x800041AA, // Small 'jmp'. - 0x800005CA, // Small 'jna'. - 0x800285CA, // Small 'jnae'. - 0x800009CA, // Small 'jnb'. - 0x800289CA, // Small 'jnbe'. - 0x80000DCA, // Small 'jnc'. - 0x800015CA, // Small 'jne'. - 0x80001DCA, // Small 'jng'. - 0x80029DCA, // Small 'jnge'. - 0x800031CA, // Small 'jnl'. - 0x8002B1CA, // Small 'jnle'. + 0x0FFF30F9, // Large 'jnb' + 'jnb|jae|jnc' + 0x0FFF4108, // Large 'jnbe' + 'jnbe|ja' + 0x0FFF3114, // Large 'jnl' + 'jnl|jge' + 0x0FFF411F, // Large 'jnle' + 'jnle|jg' 0x80003DCA, // Small 'jno'. - 0x800041CA, // Small 'jnp'. + 0x0FFF312B, // Large 'jnp' + 'jnp|jpo' 0x80004DCA, // Small 'jns'. - 0x800069CA, // Small 'jnz'. + 0x0FFF3136, // Large 'jnz' + 'jnz|jne' 0x800001EA, // Small 'jo'. - 0x8000020A, // Small 'jp'. - 0x8000160A, // Small 'jpe'. - 0x80003E0A, // Small 'jpo'. + 0x0FFF2141, // Large 'jp' + 'jp|jpe' 0x8000026A, // Small 'js'. - 0x8000034A, // Small 'jz'. + 0x0FFF214A, // Large 'jz' + 'jz|je' 0x8022102B, // Small 'kaddb'. 0x8042102B, // Small 'kaddd'. 0x8112102B, // Small 'kaddq'. @@ -3351,26 +3283,26 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x800149EB, // Small 'korb'. 0x800249EB, // Small 'kord'. 0x8008C9EB, // Small 'korq'. - 0x101075EB, // Large 'kortest|b'. - 0x102675EB, // Large 'kortest|d'. - 0x100F75EB, // Large 'kortest|q'. - 0x105F75EB, // Large 'kortest|w'. + 0x215467B2, // Large 'kortes|tb'. + 0x262667B2, // Large 'kortes|td'. + 0x236C67B2, // Large 'kortes|tq'. + 0x27B867B2, // Large 'kortes|tw'. 0x800BC9EB, // Small 'korw'. - 0x233A65F2, // Large 'kshift|lb'. - 0x23A165F2, // Large 'kshift|ld'. - 0x228865F2, // Large 'kshift|lq'. - 0x23A465F2, // Large 'kshift|lw'. - 0x25F865F2, // Large 'kshift|rb'. - 0x102675F2, // Large 'kshiftr|d'. - 0x100F75F2, // Large 'kshiftr|q'. - 0x105F75F2, // Large 'kshiftr|w'. + 0x252067BA, // Large 'kshift|lb'. + 0x257F67BA, // Large 'kshift|ld'. + 0x246267BA, // Large 'kshift|lq'. + 0x258267BA, // Large 'kshift|lw'. + 0x27C067BA, // Large 'kshift|rb'. + 0x122B77BA, // Large 'kshiftr|d'. + 0x121577BA, // Large 'kshiftr|q'. + 0x126477BA, // Large 'kshiftr|w'. 0x8549968B, // Small 'ktestb'. 0x8949968B, // Small 'ktestd'. 0xA349968B, // Small 'ktestq'. 0xAF49968B, // Small 'ktestw'. - 0x239A65FA, // Large 'kunpck|bw'. - 0x20E565FA, // Large 'kunpck|dq'. - 0x239C65FA, // Large 'kunpck|wd'. + 0x257867C2, // Large 'kunpck|bw'. + 0x23CF67C2, // Large 'kunpck|dq'. + 0x257A67C2, // Large 'kunpck|wd'. 0x8527BB0B, // Small 'kxnorb'. 0x8927BB0B, // Small 'kxnord'. 0xA327BB0B, // Small 'kxnorq'. @@ -3383,9 +3315,9 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x8000482C, // Small 'lar'. 0x80C6046C, // Small 'lcall'. 0x8158908C, // Small 'lddqu'. - 0x1023664B, // Large 'ldmxcs|r'. + 0x12286815, // Large 'ldmxcs|r'. 0x80004C8C, // Small 'lds'. - 0x10018412, // Large 'ldtilecf|g'. + 0x103185E3, // Large 'ldtilecf|g'. 0x800004AC, // Small 'lea'. 0x805B04AC, // Small 'leave'. 0x80004CAC, // Small 'les'. @@ -3408,61 +3340,61 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0xA6E4C2EC, // Small 'lwpins'. 0x981B42EC, // Small 'lwpval'. 0x81470F4C, // Small 'lzcnt'. - 0x109D9241, // Large 'maskmovdq|u'. - 0x100F7241, // Large 'maskmov|q'. + 0x12A2941B, // Large 'maskmovdq|u'. + 0x1215741B, // Large 'maskmov|q'. 0x8048602D, // Small 'maxpd'. 0x8138602D, // Small 'maxps'. 0x8049E02D, // Small 'maxsd'. 0x8139E02D, // Small 'maxss'. - 0x21925760, // Large 'mcomm|it'. + 0x236B5926, // Large 'mcomm|it'. 0x8A3714CD, // Small 'mfence'. 0x8048392D, // Small 'minpd'. 0x8138392D, // Small 'minps'. 0x8049B92D, // Small 'minsd'. 0x8139B92D, // Small 'minss'. - 0x00007600, // Large 'monitor'. - 0x102E7600, // Large 'monitor|x'. + 0x000077C8, // Large 'monitor'. + 0x123377C8, // Large 'monitor|x'. 0x800059ED, // Small 'mov'. 0xA620D9ED, // Small 'movabs'. 0x8900D9ED, // Small 'movapd'. 0xA700D9ED, // Small 'movaps'. 0x805159ED, // Small 'movbe'. 0x800259ED, // Small 'movd'. - 0x36574245, // Large 'movd|dup'. - 0x1010841A, // Large 'movdir64|b'. - 0x1009641A, // Large 'movdir|i'. - 0x268F5245, // Large 'movdq|2q'. + 0x3821441F, // Large 'movd|dup'. + 0x100485EB, // Large 'movdir64|b'. + 0x120F65EB, // Large 'movdir|i'. + 0x24E4541F, // Large 'movdq|2q'. 0x831259ED, // Small 'movdqa'. 0xAB1259ED, // Small 'movdqu'. - 0x359A465D, // Large 'movh|lps'. + 0x37664827, // Large 'movh|lps'. 0x890459ED, // Small 'movhpd'. 0xA70459ED, // Small 'movhps'. - 0x207D5662, // Large 'movlh|ps'. + 0x2282582C, // Large 'movlh|ps'. 0x890659ED, // Small 'movlpd'. 0xA70659ED, // Small 'movlps'. - 0x20A764D0, // Large 'movmsk|pd'. - 0x207D64D0, // Large 'movmsk|ps'. - 0x20E554D7, // Large 'movnt|dq'. - 0x34C354D7, // Large 'movnt|dqa'. + 0x22AC669C, // Large 'movmsk|pd'. + 0x2282669C, // Large 'movmsk|ps'. + 0x23CF56A3, // Large 'movnt|dq'. + 0x368F56A3, // Large 'movnt|dqa'. 0x934759ED, // Small 'movnti'. - 0x20A754D7, // Large 'movnt|pd'. - 0x207D54D7, // Large 'movnt|ps'. + 0x22AC56A3, // Large 'movnt|pd'. + 0x228256A3, // Large 'movnt|ps'. 0xA34759ED, // Small 'movntq'. - 0x214454D7, // Large 'movnt|sd'. - 0x201C54D7, // Large 'movnt|ss'. + 0x231D56A3, // Large 'movnt|sd'. + 0x222256A3, // Large 'movnt|ss'. 0x8008D9ED, // Small 'movq'. - 0x20E55765, // Large 'movq2|dq'. + 0x34E1492B, // Large 'movq|2dq'. 0x8009D9ED, // Small 'movs'. 0x8049D9ED, // Small 'movsd'. - 0x222964DD, // Large 'movshd|up'. - 0x222964E4, // Large 'movsld|up'. + 0x240366A9, // Large 'movshd|up'. + 0x240366B0, // Large 'movsld|up'. 0x8139D9ED, // Small 'movss'. 0x8189D9ED, // Small 'movsx'. 0x8989D9ED, // Small 'movsxd'. 0x890AD9ED, // Small 'movupd'. 0xA70AD9ED, // Small 'movups'. 0x818D59ED, // Small 'movzx'. - 0x239A5668, // Large 'mpsad|bw'. + 0x25785832, // Large 'mpsad|bw'. 0x800032AD, // Small 'mul'. 0x804832AD, // Small 'mulpd'. 0x813832AD, // Small 'mulps'. @@ -3482,41 +3414,41 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x80298830, // Small 'pabsb'. 0x80498830, // Small 'pabsd'. 0x81798830, // Small 'pabsw'. - 0x000084EB, // Large 'packssdw'. - 0x24F264EB, // Large 'packss|wb'. - 0x24F164F5, // Large 'packus|dw'. - 0x000084F5, // Large 'packuswb'. + 0x000086B7, // Large 'packssdw'. + 0x26BE66B7, // Large 'packss|wb'. + 0x26BD66C1, // Large 'packus|dw'. + 0x000086C1, // Large 'packuswb'. 0x80221030, // Small 'paddb'. 0x80421030, // Small 'paddd'. 0x81121030, // Small 'paddq'. 0x85321030, // Small 'paddsb'. 0xAF321030, // Small 'paddsw'. - 0x25BA5675, // Large 'paddu|sb'. - 0x23835675, // Large 'paddu|sw'. + 0x2786583F, // Large 'paddu|sb'. + 0x2561583F, // Large 'paddu|sw'. 0x81721030, // Small 'paddw'. - 0x1023667B, // Large 'palign|r'. + 0x12286845, // Large 'palign|r'. 0x80023830, // Small 'pand'. 0x80E23830, // Small 'pandn'. 0x8059D430, // Small 'pause'. 0x8023D830, // Small 'pavgb'. - 0x25BA576A, // Large 'pavgu|sb'. + 0x2786592F, // Large 'pavgu|sb'. 0x8173D830, // Small 'pavgw'. - 0x202164FE, // Large 'pblend|vb'. - 0x105F64FE, // Large 'pblend|w'. - 0x42885345, // Large 'pclmu|lqdq'. - 0x200F534B, // Large 'pcmpe|qb'. - 0x227D534B, // Large 'pcmpe|qd'. - 0x21F6534B, // Large 'pcmpe|qq'. - 0x2559534B, // Large 'pcmpe|qw'. - 0x1009834B, // Large 'pcmpestr|i'. - 0x105C834B, // Large 'pcmpestr|m'. - 0x368142A5, // Large 'pcmp|gtb'. - 0x368442A5, // Large 'pcmp|gtd'. - 0x368742A5, // Large 'pcmp|gtq'. - 0x368A42A5, // Large 'pcmp|gtw'. - 0x10098354, // Large 'pcmpistr|i'. - 0x105C8354, // Large 'pcmpistr|m'. - 0x267E5255, // Large 'pconf|ig'. + 0x200366CA, // Large 'pblend|vb'. + 0x126466CA, // Large 'pblend|w'. + 0x44625523, // Large 'pclmu|lqdq'. + 0x22155529, // Large 'pcmpe|qb'. + 0x24575529, // Large 'pcmpe|qd'. + 0x23D05529, // Large 'pcmpe|qq'. + 0x27255529, // Large 'pcmpe|qw'. + 0x120F8529, // Large 'pcmpestr|i'. + 0x10018529, // Large 'pcmpestr|m'. + 0x384B448E, // Large 'pcmp|gtb'. + 0x384E448E, // Large 'pcmp|gtd'. + 0x3851448E, // Large 'pcmp|gtq'. + 0x3854448E, // Large 'pcmp|gtw'. + 0x120F8532, // Large 'pcmpistr|i'. + 0x10018532, // Large 'pcmpistr|m'. + 0x2848542F, // Large 'pconf|ig'. 0x80081490, // Small 'pdep'. 0x800A60B0, // Small 'pext'. 0x852A60B0, // Small 'pextrb'. @@ -3527,29 +3459,29 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x8174F4D0, // Small 'pf2iw'. 0x803184D0, // Small 'pfacc'. 0x804204D0, // Small 'pfadd'. - 0x100F676F, // Large 'pfcmpe|q'. - 0x2018576F, // Large 'pfcmp|ge'. - 0x2681576F, // Large 'pfcmp|gt'. + 0x12156934, // Large 'pfcmpe|q'. + 0x20315934, // Large 'pfcmp|ge'. + 0x284B5934, // Large 'pfcmp|gt'. 0x8180B4D0, // Small 'pfmax'. 0x80E4B4D0, // Small 'pfmin'. 0x80CAB4D0, // Small 'pfmul'. 0x8630B8D0, // Small 'pfnacc'. - 0x24B15775, // Large 'pfpna|cc'. + 0x2011593A, // Large 'pfpna|cc'. 0x8101C8D0, // Small 'pfrcp'. - 0x21AD6607, // Large 'pfrcpi|t1'. - 0x22BF6607, // Large 'pfrcpi|t2'. + 0x238767CF, // Large 'pfrcpi|t1'. + 0x24A667CF, // Large 'pfrcpi|t2'. 0xAD01C8D0, // Small 'pfrcpv'. - 0x21AD660D, // Large 'pfrsqi|t1'. - 0x2188560D, // Large 'pfrsq|rt'. - 0x3613560D, // Large 'pfrsq|rtv'. + 0x238767D5, // Large 'pfrsqi|t1'. + 0x236157D5, // Large 'pfrsq|rt'. + 0x37DB57D5, // Large 'pfrsq|rtv'. 0x802ACCD0, // Small 'pfsub'. 0xA42ACCD0, // Small 'pfsubr'. 0x88420510, // Small 'phaddd'. - 0x23835536, // Large 'phadd|sw'. + 0x25615702, // Large 'phadd|sw'. 0xAE420510, // Small 'phaddw'. - 0x105F925F, // Large 'phminposu|w'. + 0x12649439, // Large 'phminposu|w'. 0x882ACD10, // Small 'phsubd'. - 0x23835696, // Large 'phsub|sw'. + 0x2561585E, // Large 'phsub|sw'. 0xAE2ACD10, // Small 'phsubw'. 0x80437530, // Small 'pi2fd'. 0x81737530, // Small 'pi2fw'. @@ -3557,8 +3489,8 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x8929B930, // Small 'pinsrd'. 0xA329B930, // Small 'pinsrq'. 0xAF29B930, // Small 'pinsrw'. - 0x43855269, // Large 'pmadd|ubsw'. - 0x239C5269, // Large 'pmadd|wd'. + 0x45635443, // Large 'pmadd|ubsw'. + 0x257A5443, // Large 'pmadd|wd'. 0x853C05B0, // Small 'pmaxsb'. 0x893C05B0, // Small 'pmaxsd'. 0xAF3C05B0, // Small 'pmaxsw'. @@ -3571,27 +3503,27 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x855725B0, // Small 'pminub'. 0x895725B0, // Small 'pminud'. 0xAF5725B0, // Small 'pminuw'. - 0x10107543, // Large 'pmovmsk|b'. - 0x1026754B, // Large 'pmovsxb|d'. - 0x100F754B, // Large 'pmovsxb|q'. - 0x105F754B, // Large 'pmovsxb|w'. - 0x20E5654B, // Large 'pmovsx|dq'. - 0x239C654B, // Large 'pmovsx|wd'. - 0x253D654B, // Large 'pmovsx|wq'. - 0x1026755C, // Large 'pmovzxb|d'. - 0x100F755C, // Large 'pmovzxb|q'. - 0x105F755C, // Large 'pmovzxb|w'. - 0x20E5655C, // Large 'pmovzx|dq'. - 0x239C655C, // Large 'pmovzx|wd'. - 0x253D655C, // Large 'pmovzx|wq'. + 0x1004770F, // Large 'pmovmsk|b'. + 0x122B7717, // Large 'pmovsxb|d'. + 0x12157717, // Large 'pmovsxb|q'. + 0x12647717, // Large 'pmovsxb|w'. + 0x23CF6717, // Large 'pmovsx|dq'. + 0x257A6717, // Large 'pmovsx|wd'. + 0x27096717, // Large 'pmovsx|wq'. + 0x122B7728, // Large 'pmovzxb|d'. + 0x12157728, // Large 'pmovzxb|q'. + 0x12647728, // Large 'pmovzxb|w'. + 0x23CF6728, // Large 'pmovzx|dq'. + 0x257A6728, // Large 'pmovzx|wd'. + 0x27096728, // Large 'pmovzx|wq'. 0xA24655B0, // Small 'pmuldq'. - 0x23836564, // Large 'pmulhr|sw'. - 0x105F6564, // Large 'pmulhr|w'. - 0x24815564, // Large 'pmulh|uw'. + 0x25616730, // Large 'pmulhr|sw'. + 0x12646730, // Large 'pmulhr|w'. + 0x264C5730, // Large 'pmulh|uw'. 0xAE8655B0, // Small 'pmulhw'. 0x88C655B0, // Small 'pmulld'. 0xAEC655B0, // Small 'pmullw'. - 0x32E540CF, // Large 'pmul|udq'. + 0x33CE42D4, // Large 'pmul|udq'. 0x800041F0, // Small 'pop'. 0x8000C1F0, // Small 'popa'. 0x8040C1F0, // Small 'popad'. @@ -3600,20 +3532,20 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x804341F0, // Small 'popfd'. 0x811341F0, // Small 'popfq'. 0x800049F0, // Small 'por'. - 0x0000819F, // Large 'prefetch'. - 0x10E4A19F, // Large 'prefetchit|0'. - 0x106BA19F, // Large 'prefetchit|1'. - 0x31A9819F, // Large 'prefetch|nta'. - 0x22BD819F, // Large 'prefetch|t0'. - 0x21AD819F, // Large 'prefetch|t1'. - 0x22BF819F, // Large 'prefetch|t2'. - 0x105F819F, // Large 'prefetch|w'. - 0x31AC819F, // Large 'prefetch|wt1'. + 0x00008378, // Large 'prefetch'. + 0x0000B378, // Large 'prefetchit0'. + 0x1270A378, // Large 'prefetchit|1'. + 0x33838378, // Large 'prefetch|nta'. + 0x23818378, // Large 'prefetch|t0'. + 0x23878378, // Large 'prefetch|t1'. + 0x24A68378, // Large 'prefetch|t2'. + 0x12648378, // Large 'prefetch|w'. + 0x33868378, // Large 'prefetch|wt1'. 0xAE220670, // Small 'psadbw'. 0x846AA270, // Small 'pshufb'. 0x886AA270, // Small 'pshufd'. - 0x26C3518C, // Large 'pshuf|hw'. - 0x23A4518C, // Large 'pshuf|lw'. + 0x288B5365, // Large 'pshuf|hw'. + 0x25825365, // Large 'pshuf|lw'. 0xAE6AA270, // Small 'pshufw'. 0x84E3A670, // Small 'psignb'. 0x88E3A670, // Small 'psignd'. @@ -3634,20 +3566,20 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x81115670, // Small 'psubq'. 0x85315670, // Small 'psubsb'. 0xAF315670, // Small 'psubsw'. - 0x25BA56C6, // Large 'psubu|sb'. - 0x238356C6, // Large 'psubu|sw'. + 0x2786588E, // Large 'psubu|sb'. + 0x2561588E, // Large 'psubu|sw'. 0x81715670, // Small 'psubw'. 0x8900DE70, // Small 'pswapd'. 0x81499690, // Small 'ptest'. - 0x20DF577A, // Large 'ptwri|te'. - 0x239A7280, // Large 'punpckh|bw'. - 0x20E57280, // Large 'punpckh|dq'. - 0x20E58280, // Large 'punpckhq|dq'. - 0x239C7280, // Large 'punpckh|wd'. - 0x339E6280, // Large 'punpck|lbw'. - 0x33A16280, // Large 'punpck|ldq'. - 0x42886280, // Large 'punpck|lqdq'. - 0x33A46280, // Large 'punpck|lwd'. + 0x22FD593F, // Large 'ptwri|te'. + 0x2578745A, // Large 'punpckh|bw'. + 0x23CF745A, // Large 'punpckh|dq'. + 0x23CF845A, // Large 'punpckhq|dq'. + 0x257A745A, // Large 'punpckh|wd'. + 0x357C645A, // Large 'punpck|lbw'. + 0x357F645A, // Large 'punpck|ldq'. + 0x4462645A, // Large 'punpck|lqdq'. + 0x3582645A, // Large 'punpck|lwd'. 0x80044EB0, // Small 'push'. 0x80144EB0, // Small 'pusha'. 0x88144EB0, // Small 'pushad'. @@ -3655,14 +3587,14 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x88644EB0, // Small 'pushfd'. 0xA2644EB0, // Small 'pushfq'. 0x81744EB0, // Small 'pushw'. - 0x20DF7422, // Large 'pvalida|te'. + 0x22FD75F3, // Large 'pvalida|te'. 0x80093F10, // Small 'pxor'. 0x80003072, // Small 'rcl'. 0x81384072, // Small 'rcpps'. 0x8139C072, // Small 'rcpss'. 0x80004872, // Small 'rcr'. - 0x34365616, // Large 'rdfsb|ase'. - 0x3436561B, // Large 'rdgsb|ase'. + 0x317057DE, // Large 'rdfsb|ase'. + 0x317057E3, // Large 'rdgsb|ase'. 0x8129B492, // Small 'rdmsr'. 0x8044C092, // Small 'rdpid'. 0xAB25C092, // Small 'rdpkru'. @@ -3676,71 +3608,56 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0xA039D092, // Small 'rdtscp'. 0x800050B2, // Small 'ret'. 0x800350B2, // Small 'retf'. - 0x201F7429, // Large 'rmpadju|st'. - 0x20DF7430, // Large 'rmpupda|te'. + 0x222E75FA, // Large 'rmpadju|st'. + 0x22FD7601, // Large 'rmpupda|te'. 0x800031F2, // Small 'rol'. 0x800049F2, // Small 'ror'. 0x800C49F2, // Small 'rorx'. - 0x20A756D8, // Large 'round|pd'. - 0x207D56D8, // Large 'round|ps'. - 0x000076D8, // Large 'roundsd'. - 0x101466D8, // Large 'rounds|s'. + 0x22AC58A0, // Large 'round|pd'. + 0x228258A0, // Large 'round|ps'. + 0x231D58A0, // Large 'round|sd'. + 0x222258A0, // Large 'round|ss'. 0x80003672, // Small 'rsm'. - 0x207D53A8, // Large 'rsqrt|ps'. - 0x201C53A8, // Large 'rsqrt|ss'. - 0x3620540D, // Large 'rstor|ssp'. + 0x22825586, // Large 'rsqrt|ps'. + 0x22225586, // Large 'rsqrt|ss'. + 0x37E855DE, // Large 'rstor|ssp'. 0x80032033, // Small 'sahf'. - 0x80003033, // Small 'sal'. 0x80004833, // Small 'sar'. 0x800C4833, // Small 'sarx'. - 0x1004A1AF, // Large 'saveprevss|p'. + 0x1092A389, // Large 'saveprevss|p'. 0x80000853, // Small 'sbb'. 0x80098473, // Small 'scas'. - 0x10D27623, // Large 'seamcal|l'. - 0x207D577F, // Large 'seamo|ps'. - 0x21A35784, // Large 'seamr|et'. - 0x222A662A, // Large 'sendui|pi'. - 0x23CB7437, // Large 'seriali|ze'. - 0x8000D0B3, // Small 'seta'. - 0x8050D0B3, // Small 'setae'. - 0x800150B3, // Small 'setb'. - 0x805150B3, // Small 'setbe'. - 0x8001D0B3, // Small 'setc'. - 0x8002D0B3, // Small 'sete'. - 0x8003D0B3, // Small 'setg'. - 0x8053D0B3, // Small 'setge'. - 0x800650B3, // Small 'setl'. - 0x805650B3, // Small 'setle'. - 0x801750B3, // Small 'setna'. - 0x8A1750B3, // Small 'setnae'. - 0x802750B3, // Small 'setnb'. - 0x8A2750B3, // Small 'setnbe'. - 0x803750B3, // Small 'setnc'. - 0x805750B3, // Small 'setne'. - 0x807750B3, // Small 'setng'. - 0x8A7750B3, // Small 'setnge'. - 0x80C750B3, // Small 'setnl'. - 0x8AC750B3, // Small 'setnle'. + 0x102777EB, // Large 'seamcal|l'. + 0x22825944, // Large 'seamo|ps'. + 0x21535949, // Large 'seamr|et'. + 0x240467F2, // Large 'sendui|pi'. + 0x25997608, // Large 'seriali|ze'. + 0x0FFF4152, // Large 'setb' + 'set.b|nae|c' + 0x0FFF5162, // Large 'setbe' + 'set.be|na' + 0x0FFF4171, // Large 'setl' + 'set.l|nge' + 0x0FFF517F, // Large 'setle' + 'set.le|ng' + 0x0FFF518E, // Large 'setnb' + 'set.nb|ae|nc' + 0x0FFF61A0, // Large 'setnbe' + 'set.nbe|a' + 0x0FFF51B0, // Large 'setnl' + 'set.nl|ge' + 0x0FFF61BF, // Large 'setnle' + 'set.nle|g' 0x80F750B3, // Small 'setno'. - 0x810750B3, // Small 'setnp'. + 0x0FFF51CF, // Large 'setnp' + 'set.np|po' 0x813750B3, // Small 'setns'. - 0x81A750B3, // Small 'setnz'. + 0x0FFF51DE, // Large 'setnz' + 'set.nz|ne' 0x8007D0B3, // Small 'seto'. - 0x800850B3, // Small 'setp'. - 0x805850B3, // Small 'setpe'. - 0x80F850B3, // Small 'setpo'. + 0x0FFF41ED, // Large 'setp' + 'set.p|pe' 0x8009D0B3, // Small 'sets'. - 0x10177630, // Large 'setssbs|y'. - 0x800D50B3, // Small 'setz'. + 0x121D77F8, // Large 'setssbs|y'. + 0x0FFF41FA, // Large 'setz' + 'set.z|e' 0x8A3714D3, // Small 'sfence'. 0x800A10F3, // Small 'sgdt'. - 0x4295443E, // Large 'sha1|msg1'. - 0x4299443E, // Large 'sha1|msg2'. - 0x20DF743E, // Large 'sha1nex|te'. - 0x102F8445, // Large 'sha1rnds|4'. - 0x429561B9, // Large 'sha256|msg1'. - 0x429961B9, // Large 'sha256|msg2'. - 0x207E91B9, // Large 'sha256rnd|s2'. + 0x447E460F, // Large 'sha1|msg1'. + 0x4482460F, // Large 'sha1|msg2'. + 0x22FD760F, // Large 'sha1nex|te'. + 0x12348616, // Large 'sha1rnds|4'. + 0x447E6393, // Large 'sha256|msg1'. + 0x44826393, // Large 'sha256|msg2'. + 0x22839393, // Large 'sha256rnd|s2'. 0x80003113, // Small 'shl'. 0x80023113, // Small 'shld'. 0x800C3113, // Small 'shlx'. @@ -3763,10 +3680,10 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x80001293, // Small 'std'. 0x80049E93, // Small 'stgi'. 0x80002693, // Small 'sti'. - 0x102366E7, // Large 'stmxcs|r'. + 0x122868AD, // Large 'stmxcs|r'. 0x8009BE93, // Small 'stos'. 0x80004A93, // Small 'str'. - 0x1001844D, // Large 'sttilecf|g'. + 0x1031861E, // Large 'sttilecf|g'. 0x8004D693, // Small 'stui'. 0x80000AB3, // Small 'sub'. 0x80480AB3, // Small 'subpd'. @@ -3774,388 +3691,374 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x80498AB3, // Small 'subsd'. 0x81398AB3, // Small 'subss'. 0xA67806F3, // Small 'swapgs'. - 0x36F34789, // Large 'sysc|all'. - 0x41234637, // Large 'syse|nter'. - 0x2192563B, // Large 'sysex|it'. - 0x3192563B, // Large 'sysex|itq'. + 0x38B9494E, // Large 'sysc|all'. + 0x42FC47FF, // Large 'syse|nter'. + 0x236B5803, // Large 'sysex|it'. + 0x336B5803, // Large 'sysex|itq'. 0xA8594F33, // Small 'sysret'. - 0x2193578D, // Large 'sysre|tq'. + 0x236C5952, // Large 'sysre|tq'. 0x86B9B794, // Small 't1mskc'. - 0x207DA12B, // Large 'tcmmimfp16|ps'. - 0x207DA135, // Large 'tcmmrlfp16|ps'. + 0x2282A304, // Large 'tcmmimfp16|ps'. + 0x2282A30E, // Large 'tcmmrlfp16|ps'. 0x98C08C94, // Small 'tdcall'. - 0x207D7455, // Large 'tdpbf16|ps'. - 0x31434455, // Large 'tdpb|ssd'. - 0x32E44455, // Large 'tdpb|sud'. - 0x21445792, // Large 'tdpbu|sd'. - 0x22E55792, // Large 'tdpbu|ud'. - 0x207D745C, // Large 'tdpfp16|ps'. + 0x22827626, // Large 'tdpbf16|ps'. + 0x331C4626, // Large 'tdpb|ssd'. + 0x36D84626, // Large 'tdpb|sud'. + 0x231D5957, // Large 'tdpbu|sd'. + 0x23CE5957, // Large 'tdpbu|ud'. + 0x2282762D, // Large 'tdpfp16|ps'. 0x800A4CB4, // Small 'test'. 0x935A4CB4, // Small 'testui'. - 0x000091C2, // Large 'tileloadd'. - 0x21AD91C2, // Large 'tileloadd|t1'. - 0x212791CB, // Large 'tilerelea|se'. - 0x102692C1, // Large 'tilestore|d'. - 0x43CB41C2, // Large 'tile|zero'. - 0x21E15797, // Large 'tlbsy|nc'. + 0x0000939C, // Large 'tileloadd'. + 0x2387939C, // Large 'tileloadd|t1'. + 0x317083A5, // Large 'tilerele|ase'. + 0x122B94A8, // Large 'tilestore|d'. + 0x4599439C, // Large 'tile|zero'. + 0x2056595C, // Large 'tlbsy|nc'. 0x8B3A8614, // Small 'tpause'. 0x81470F54, // Small 'tzcnt'. 0x80B9B754, // Small 'tzmsk'. - 0x214456EE, // Large 'ucomi|sd'. - 0x201C56EE, // Large 'ucomi|ss'. + 0x231D58B4, // Large 'ucomi|sd'. + 0x222258B4, // Large 'ucomi|ss'. 0x80006C95, // Small 'ud0'. 0x80007095, // Small 'ud1'. 0x80007495, // Small 'ud2'. 0x8142C935, // Small 'uiret'. - 0x7600109D, // Large 'u|monitor'. + 0x67C92808, // Large 'um|onitor'. 0xA890DDB5, // Small 'umwait'. - 0x20A76281, // Large 'unpckh|pd'. - 0x207D6281, // Large 'unpckh|ps'. - 0x35975281, // Large 'unpck|lpd'. - 0x359A5281, // Large 'unpck|lps'. - 0x30F16463, // Large 'v4fmad|dps'. - 0x32D16463, // Large 'v4fmad|dss'. - 0x30F172CA, // Large 'v4fnmad|dps'. - 0x32D172CA, // Large 'v4fnmad|dss'. + 0x22AC645B, // Large 'unpckh|pd'. + 0x2282645B, // Large 'unpckh|ps'. + 0x3763545B, // Large 'unpck|lpd'. + 0x3766545B, // Large 'unpck|lps'. 0x89021036, // Small 'vaddpd'. 0x91021036, // Small 'vaddph'. 0xA7021036, // Small 'vaddps'. 0x89321036, // Small 'vaddsd'. 0x91321036, // Small 'vaddsh'. 0xA7321036, // Small 'vaddss'. - 0x20A77469, // Large 'vaddsub|pd'. - 0x207D7469, // Large 'vaddsub|ps'. - 0x000071D4, // Large 'vaesdec'. - 0x302881D4, // Large 'vaesdecl|ast'. - 0x000071DC, // Large 'vaesenc'. - 0x302881DC, // Large 'vaesencl|ast'. - 0x2626579C, // Large 'vaesi|mc'. - 0x1020F011, // Large 'vaeskeygenassis|t'. - 0x219D57A1, // Large 'valig|nd'. - 0x271E57A1, // Large 'valig|nq'. - 0x20A757A6, // Large 'vandn|pd'. - 0x207D57A6, // Large 'vandn|ps'. + 0x22AC7634, // Large 'vaddsub|pd'. + 0x22827634, // Large 'vaddsub|ps'. + 0x000073AD, // Large 'vaesdec'. + 0x322D83AD, // Large 'vaesdecl|ast'. + 0x000073B5, // Large 'vaesenc'. + 0x322D83B5, // Large 'vaesencl|ast'. + 0x27EE5961, // Large 'vaesi|mc'. + 0x1154F217, // Large 'vaeskeygenassis|t'. + 0x23765966, // Large 'valig|nd'. + 0x28DF5966, // Large 'valig|nq'. + 0x22AC596B, // Large 'vandn|pd'. + 0x2282596B, // Large 'vandn|ps'. 0x89023836, // Small 'vandpd'. 0xA7023836, // Small 'vandps'. - 0x1014D062, // Large 'vbcstnebf162p|s'. - 0x513F7062, // Large 'vbcstne|sh2ps'. - 0x20A77470, // Large 'vblendm|pd'. - 0x207D7470, // Large 'vblendm|ps'. - 0x20A76470, // Large 'vblend|pd'. - 0x207D6470, // Large 'vblend|ps'. - 0x34776470, // Large 'vblend|vpd'. - 0x318B6470, // Large 'vblend|vps'. - 0x306FB021, // Large 'vbroadcastf|128'. - 0x1003E021, // Large 'vbroadcastf32x|2'. - 0x102FE021, // Large 'vbroadcastf32x|4'. - 0x1005E021, // Large 'vbroadcastf32x|8'. - 0x4030B021, // Large 'vbroadcastf|64x2'. - 0x4034B021, // Large 'vbroadcastf|64x4'. - 0x4072A021, // Large 'vbroadcast|i128'. - 0x5038A021, // Large 'vbroadcast|i32x2'. - 0x503DA021, // Large 'vbroadcast|i32x4'. - 0x5042A021, // Large 'vbroadcast|i32x8'. - 0x5047A021, // Large 'vbroadcast|i64x2'. - 0x504CA021, // Large 'vbroadcast|i64x4'. - 0x2144A021, // Large 'vbroadcast|sd'. - 0x201CA021, // Large 'vbroadcast|ss'. + 0x1152D267, // Large 'vbcstnebf162p|s'. + 0x53187267, // Large 'vbcstne|sh2ps'. + 0x22AC763B, // Large 'vblendm|pd'. + 0x2282763B, // Large 'vblendm|ps'. + 0x22AC663B, // Large 'vblend|pd'. + 0x2282663B, // Large 'vblend|ps'. + 0x3642663B, // Large 'vblend|vpd'. + 0x3364663B, // Large 'vblend|vps'. + 0x3274B226, // Large 'vbroadcastf|128'. + 0x1209E226, // Large 'vbroadcastf32x|2'. + 0x1234E226, // Large 'vbroadcastf32x|4'. + 0x120BE226, // Large 'vbroadcastf32x|8'. + 0x4235B226, // Large 'vbroadcastf|64x2'. + 0x4239B226, // Large 'vbroadcastf|64x4'. + 0x4277A226, // Large 'vbroadcast|i128'. + 0x523DA226, // Large 'vbroadcast|i32x2'. + 0x5242A226, // Large 'vbroadcast|i32x4'. + 0x5247A226, // Large 'vbroadcast|i32x8'. + 0x524CA226, // Large 'vbroadcast|i64x2'. + 0x5251A226, // Large 'vbroadcast|i64x4'. + 0x231DA226, // Large 'vbroadcast|sd'. + 0x2222A226, // Large 'vbroadcast|ss'. 0x89083476, // Small 'vcmppd'. 0x91083476, // Small 'vcmpph'. 0xA7083476, // Small 'vcmpps'. 0x89383476, // Small 'vcmpsd'. 0x91383476, // Small 'vcmpsh'. 0xA7383476, // Small 'vcmpss'. - 0x214457AB, // Large 'vcomi|sd'. - 0x20D557AB, // Large 'vcomi|sh'. - 0x201C57AB, // Large 'vcomi|ss'. - 0x20A791E4, // Large 'vcompress|pd'. - 0x207D91E4, // Large 'vcompress|ps'. - 0x20A7747A, // Large 'vcvtdq2|pd'. - 0x20A2747A, // Large 'vcvtdq2|ph'. - 0x207D747A, // Large 'vcvtdq2|ps'. - 0x4069A076, // Large 'vcvtne2ps2|bf16'. - 0x307CB080, // Large 'vcvtneebf16|2ps'. - 0x51467080, // Large 'vcvtnee|ph2ps'. - 0x307CB08B, // Large 'vcvtneobf16|2ps'. - 0x5146708B, // Large 'vcvtneo|ph2ps'. - 0x406990FC, // Large 'vcvtneps2|bf16'. - 0x20E572D4, // Large 'vcvtpd2|dq'. - 0x20A272D4, // Large 'vcvtpd2|ph'. - 0x207D72D4, // Large 'vcvtpd2|ps'. - 0x21F672D4, // Large 'vcvtpd2|qq'. - 0x20E582D4, // Large 'vcvtpd2u|dq'. - 0x21F682D4, // Large 'vcvtpd2u|qq'. - 0x20E572DC, // Large 'vcvtph2|dq'. - 0x102682DC, // Large 'vcvtph2p|d'. - 0x000092DC, // Large 'vcvtph2ps'. - 0x102E92DC, // Large 'vcvtph2ps|x'. - 0x21F672DC, // Large 'vcvtph2|qq'. - 0x32E572DC, // Large 'vcvtph2|udq'. - 0x31F572DC, // Large 'vcvtph2|uqq'. - 0x248172DC, // Large 'vcvtph2|uw'. - 0x105F72DC, // Large 'vcvtph2|w'. - 0x20E572E8, // Large 'vcvtps2|dq'. - 0x102682E8, // Large 'vcvtps2p|d'. - 0x000092E8, // Large 'vcvtps2ph'. - 0x102E92E8, // Large 'vcvtps2ph|x'. - 0x21F672E8, // Large 'vcvtps2|qq'. - 0x32E572E8, // Large 'vcvtps2|udq'. - 0x31F572E8, // Large 'vcvtps2|uqq'. - 0x20A77483, // Large 'vcvtqq2|pd'. - 0x20A27483, // Large 'vcvtqq2|ph'. - 0x207D7483, // Large 'vcvtqq2|ps'. - 0x20D572F1, // Large 'vcvtsd2|sh'. - 0x201D72F1, // Large 'vcvtsd2|si'. - 0x201C72F1, // Large 'vcvtsd2|ss'. - 0x201D82F1, // Large 'vcvtsd2u|si'. - 0x214472F9, // Large 'vcvtsh2|sd'. - 0x201D72F9, // Large 'vcvtsh2|si'. - 0x201C72F9, // Large 'vcvtsh2|ss'. - 0x201D82F9, // Large 'vcvtsh2u|si'. - 0x2144748A, // Large 'vcvtsi2|sd'. - 0x20D5748A, // Large 'vcvtsi2|sh'. - 0x201C748A, // Large 'vcvtsi2|ss'. - 0x21447301, // Large 'vcvtss2|sd'. - 0x20D57301, // Large 'vcvtss2|sh'. - 0x201D7301, // Large 'vcvtss2|si'. - 0x201D8301, // Large 'vcvtss2u|si'. - 0x20E581ED, // Large 'vcvttpd2|dq'. - 0x21F681ED, // Large 'vcvttpd2|qq'. - 0x20E591ED, // Large 'vcvttpd2u|dq'. - 0x21F691ED, // Large 'vcvttpd2u|qq'. - 0x20E581F8, // Large 'vcvttph2|dq'. - 0x21F681F8, // Large 'vcvttph2|qq'. - 0x20E591F8, // Large 'vcvttph2u|dq'. - 0x21F691F8, // Large 'vcvttph2u|qq'. - 0x105F91F8, // Large 'vcvttph2u|w'. - 0x105F81F8, // Large 'vcvttph2|w'. - 0x20E58201, // Large 'vcvttps2|dq'. - 0x21F68201, // Large 'vcvttps2|qq'. - 0x20E59201, // Large 'vcvttps2u|dq'. - 0x21F69201, // Large 'vcvttps2u|qq'. - 0x201D820A, // Large 'vcvttsd2|si'. - 0x201D920A, // Large 'vcvttsd2u|si'. - 0x201D8213, // Large 'vcvttsh2|si'. - 0x201D9213, // Large 'vcvttsh2u|si'. - 0x201D821C, // Large 'vcvttss2|si'. - 0x201D921C, // Large 'vcvttss2u|si'. - 0x20A78309, // Large 'vcvtudq2|pd'. - 0x20A28309, // Large 'vcvtudq2|ph'. - 0x207D8309, // Large 'vcvtudq2|ps'. - 0x20A78311, // Large 'vcvtuqq2|pd'. - 0x20A28311, // Large 'vcvtuqq2|ph'. - 0x207D8311, // Large 'vcvtuqq2|ps'. - 0x21448319, // Large 'vcvtusi2|sd'. - 0x20D58319, // Large 'vcvtusi2|sh'. - 0x201C8319, // Large 'vcvtusi2|ss'. - 0x30A16491, // Large 'vcvtuw|2ph'. - 0x30A15640, // Large 'vcvtw|2ph'. - 0x239A7497, // Large 'vdbpsad|bw'. + 0x231D5970, // Large 'vcomi|sd'. + 0x22DA5970, // Large 'vcomi|sh'. + 0x22225970, // Large 'vcomi|ss'. + 0x22AC93BD, // Large 'vcompress|pd'. + 0x228293BD, // Large 'vcompress|ps'. + 0x22AC7645, // Large 'vcvtdq2|pd'. + 0x22A77645, // Large 'vcvtdq2|ph'. + 0x22827645, // Large 'vcvtdq2|ps'. + 0x426EA27B, // Large 'vcvtne2ps2|bf16'. + 0x3281B285, // Large 'vcvtneebf16|2ps'. + 0x531F7285, // Large 'vcvtnee|ph2ps'. + 0x3281B290, // Large 'vcvtneobf16|2ps'. + 0x531F7290, // Large 'vcvtneo|ph2ps'. + 0x426E92DF, // Large 'vcvtneps2|bf16'. + 0x34E164B1, // Large 'vcvtpd|2dq'. + 0x32A664B1, // Large 'vcvtpd|2ph'. + 0x328164B1, // Large 'vcvtpd|2ps'. + 0x34E464B1, // Large 'vcvtpd|2qq'. + 0x63CB427B, // Large 'vcvt|pd2udq'. + 0x43D964B1, // Large 'vcvtpd|2uqq'. + 0x23CF74B7, // Large 'vcvtph2|dq'. + 0x122B84B7, // Large 'vcvtph2p|d'. + 0x000094B7, // Large 'vcvtph2ps'. + 0x123394B7, // Large 'vcvtph2ps|x'. + 0x23D074B7, // Large 'vcvtph2|qq'. + 0x33CE74B7, // Large 'vcvtph2|udq'. + 0x33DA74B7, // Large 'vcvtph2|uqq'. + 0x264C74B7, // Large 'vcvtph2|uw'. + 0x126474B7, // Large 'vcvtph2|w'. + 0x23CF74C0, // Large 'vcvtps2|dq'. + 0x122B84C0, // Large 'vcvtps2p|d'. + 0x000094C0, // Large 'vcvtps2ph'. + 0x123394C0, // Large 'vcvtps2ph|x'. + 0x23D074C0, // Large 'vcvtps2|qq'. + 0x33CE74C0, // Large 'vcvtps2|udq'. + 0x33DA74C0, // Large 'vcvtps2|uqq'. + 0x22AC764E, // Large 'vcvtqq2|pd'. + 0x22A7764E, // Large 'vcvtqq2|ph'. + 0x2282764E, // Large 'vcvtqq2|ps'. + 0x22DA74C9, // Large 'vcvtsd2|sh'. + 0x222374C9, // Large 'vcvtsd2|si'. + 0x222274C9, // Large 'vcvtsd2|ss'. + 0x222384C9, // Large 'vcvtsd2u|si'. + 0x231D74D1, // Large 'vcvtsh2|sd'. + 0x222374D1, // Large 'vcvtsh2|si'. + 0x222274D1, // Large 'vcvtsh2|ss'. + 0x222384D1, // Large 'vcvtsh2u|si'. + 0x231D7655, // Large 'vcvtsi2|sd'. + 0x22DA7655, // Large 'vcvtsi2|sh'. + 0x22227655, // Large 'vcvtsi2|ss'. + 0x231D74D9, // Large 'vcvtss2|sd'. + 0x22DA74D9, // Large 'vcvtss2|sh'. + 0x222374D9, // Large 'vcvtss2|si'. + 0x222384D9, // Large 'vcvtss2u|si'. + 0x23CF83C6, // Large 'vcvttpd2|dq'. + 0x23D083C6, // Large 'vcvttpd2|qq'. + 0x1215A3C6, // Large 'vcvttpd2ud|q'. + 0x23D093C6, // Large 'vcvttpd2u|qq'. + 0x23CF83D2, // Large 'vcvttph2|dq'. + 0x23D083D2, // Large 'vcvttph2|qq'. + 0x43CD73D2, // Large 'vcvttph|2udq'. + 0x43D973D2, // Large 'vcvttph|2uqq'. + 0x126493D2, // Large 'vcvttph2u|w'. + 0x126483D2, // Large 'vcvttph2|w'. + 0x34E173DD, // Large 'vcvttps|2dq'. + 0x34E473DD, // Large 'vcvttps|2qq'. + 0x43CD73DD, // Large 'vcvttps|2udq'. + 0x43D973DD, // Large 'vcvttps|2uqq'. + 0x222383E4, // Large 'vcvttsd2|si'. + 0x222393E4, // Large 'vcvttsd2u|si'. + 0x222383ED, // Large 'vcvttsh2|si'. + 0x222393ED, // Large 'vcvttsh2u|si'. + 0x222383F6, // Large 'vcvttss2|si'. + 0x222393F6, // Large 'vcvttss2u|si'. + 0x22AC84E7, // Large 'vcvtudq2|pd'. + 0x22A784E7, // Large 'vcvtudq2|ph'. + 0x228284E7, // Large 'vcvtudq2|ps'. + 0x22AC84EF, // Large 'vcvtuqq2|pd'. + 0x22A784EF, // Large 'vcvtuqq2|ph'. + 0x228284EF, // Large 'vcvtuqq2|ps'. + 0x231D84F7, // Large 'vcvtusi2|sd'. + 0x22DA84F7, // Large 'vcvtusi2|sh'. + 0x222284F7, // Large 'vcvtusi2|ss'. + 0x32A6665C, // Large 'vcvtuw|2ph'. + 0x32A6580A, // Large 'vcvtw|2ph'. + 0x25787662, // Large 'vdbpsad|bw'. 0x890B2496, // Small 'vdivpd'. 0x910B2496, // Small 'vdivph'. 0xA70B2496, // Small 'vdivps'. 0x893B2496, // Small 'vdivsd'. 0x913B2496, // Small 'vdivsh'. 0xA73B2496, // Small 'vdivss'. - 0x207D749E, // Large 'vdpbf16|ps'. + 0x22827669, // Large 'vdpbf16|ps'. 0x80484096, // Small 'vdppd'. 0x81384096, // Small 'vdpps'. 0x800948B6, // Small 'verr'. 0x800BC8B6, // Small 'verw'. - 0x352544A5, // Large 'vexp|2pd'. - 0x307C44A5, // Large 'vexp|2ps'. - 0x30ED64A5, // Large 'vexpan|dpd'. - 0x30F164A5, // Large 'vexpan|dps'. - 0x306F910C, // Large 'vextractf|128'. - 0x602A7105, // Large 'vextrac|tf32x4'. - 0x4043910C, // Large 'vextractf|32x8'. - 0x4030910C, // Large 'vextractf|64x2'. - 0x4034910C, // Large 'vextractf|64x4'. - 0x4072810C, // Large 'vextract|i128'. - 0x503D810C, // Large 'vextract|i32x4'. - 0x5042810C, // Large 'vextract|i32x8'. - 0x5047810C, // Large 'vextract|i64x2'. - 0x504C810C, // Large 'vextract|i64x4'. - 0x207D810C, // Large 'vextract|ps'. - 0x20A28321, // Large 'vfcmaddc|ph'. - 0x20D58321, // Large 'vfcmaddc|sh'. - 0x20A274AB, // Large 'vfcmulc|ph'. - 0x20D574AB, // Large 'vfcmulc|sh'. - 0x20A79225, // Large 'vfixupimm|pd'. - 0x207D9225, // Large 'vfixupimm|ps'. - 0x21449225, // Large 'vfixupimm|sd'. - 0x201C9225, // Large 'vfixupimm|ss'. - 0x20A7922E, // Large 'vfmadd132|pd'. - 0x20A2922E, // Large 'vfmadd132|ph'. - 0x207D922E, // Large 'vfmadd132|ps'. - 0x2144922E, // Large 'vfmadd132|sd'. - 0x20D5922E, // Large 'vfmadd132|sh'. - 0x201C922E, // Large 'vfmadd132|ss'. - 0x50A46096, // Large 'vfmadd|213pd'. - 0x50A96096, // Large 'vfmadd|213ph'. - 0x50AE6096, // Large 'vfmadd|213ps'. - 0x51556096, // Large 'vfmadd|213sd'. - 0x515A6096, // Large 'vfmadd|213sh'. - 0x515F6096, // Large 'vfmadd|213ss'. - 0x50B36096, // Large 'vfmadd|231pd'. - 0x50B86096, // Large 'vfmadd|231ph'. - 0x50BD6096, // Large 'vfmadd|231ps'. - 0x51646096, // Large 'vfmadd|231sd'. - 0x51696096, // Large 'vfmadd|231sh'. - 0x516E6096, // Large 'vfmadd|231ss'. - 0x34B26096, // Large 'vfmadd|cph'. - 0x34B56096, // Large 'vfmadd|csh'. - 0x20A76096, // Large 'vfmadd|pd'. - 0x207D6096, // Large 'vfmadd|ps'. - 0x10267096, // Large 'vfmadds|d'. - 0x10147096, // Large 'vfmadds|s'. - 0x1026D096, // Large 'vfmaddsub132p|d'. - 0x10A3D096, // Large 'vfmaddsub132p|h'. - 0x1014D096, // Large 'vfmaddsub132p|s'. - 0x50A49096, // Large 'vfmaddsub|213pd'. - 0x50A99096, // Large 'vfmaddsub|213ph'. - 0x50AE9096, // Large 'vfmaddsub|213ps'. - 0x50B39096, // Large 'vfmaddsub|231pd'. - 0x50B89096, // Large 'vfmaddsub|231ph'. - 0x50BD9096, // Large 'vfmaddsub|231ps'. - 0x20A79096, // Large 'vfmaddsub|pd'. - 0x207D9096, // Large 'vfmaddsub|ps'. - 0x20A79237, // Large 'vfmsub132|pd'. - 0x20A29237, // Large 'vfmsub132|ph'. - 0x207D9237, // Large 'vfmsub132|ps'. - 0x21449237, // Large 'vfmsub132|sd'. - 0x20D59237, // Large 'vfmsub132|sh'. - 0x201C9237, // Large 'vfmsub132|ss'. - 0x50A460C2, // Large 'vfmsub|213pd'. - 0x50A960C2, // Large 'vfmsub|213ph'. - 0x50AE60C2, // Large 'vfmsub|213ps'. - 0x515560C2, // Large 'vfmsub|213sd'. - 0x515A60C2, // Large 'vfmsub|213sh'. - 0x515F60C2, // Large 'vfmsub|213ss'. - 0x50B360C2, // Large 'vfmsub|231pd'. - 0x50B860C2, // Large 'vfmsub|231ph'. - 0x50BD60C2, // Large 'vfmsub|231ps'. - 0x516460C2, // Large 'vfmsub|231sd'. - 0x516960C2, // Large 'vfmsub|231sh'. - 0x516E60C2, // Large 'vfmsub|231ss'. - 0x20A7C0C2, // Large 'vfmsubadd132|pd'. - 0x20A2C0C2, // Large 'vfmsubadd132|ph'. - 0x207DC0C2, // Large 'vfmsubadd132|ps'. - 0x50A490C2, // Large 'vfmsubadd|213pd'. - 0x50A990C2, // Large 'vfmsubadd|213ph'. - 0x50AE90C2, // Large 'vfmsubadd|213ps'. - 0x50B390C2, // Large 'vfmsubadd|231pd'. - 0x50B890C2, // Large 'vfmsubadd|231ph'. - 0x50BD90C2, // Large 'vfmsubadd|231ps'. - 0x20A790C2, // Large 'vfmsubadd|pd'. - 0x207D90C2, // Large 'vfmsubadd|ps'. - 0x20A760C2, // Large 'vfmsub|pd'. - 0x207D60C2, // Large 'vfmsub|ps'. - 0x214460C2, // Large 'vfmsub|sd'. - 0x201C60C2, // Large 'vfmsub|ss'. - 0x34B25645, // Large 'vfmul|cph'. - 0x34B55645, // Large 'vfmul|csh'. - 0x20A7A14B, // Large 'vfnmadd132|pd'. - 0x20A2A14B, // Large 'vfnmadd132|ph'. - 0x207DA14B, // Large 'vfnmadd132|ps'. - 0x2144A14B, // Large 'vfnmadd132|sd'. - 0x20D5A14B, // Large 'vfnmadd132|sh'. - 0x201CA14B, // Large 'vfnmadd132|ss'. - 0x50A4714B, // Large 'vfnmadd|213pd'. - 0x50A9714B, // Large 'vfnmadd|213ph'. - 0x50AE714B, // Large 'vfnmadd|213ps'. - 0x5155714B, // Large 'vfnmadd|213sd'. - 0x515A714B, // Large 'vfnmadd|213sh'. - 0x515F714B, // Large 'vfnmadd|213ss'. - 0x50B3714B, // Large 'vfnmadd|231pd'. - 0x50B8714B, // Large 'vfnmadd|231ph'. - 0x50BD714B, // Large 'vfnmadd|231ps'. - 0x5164714B, // Large 'vfnmadd|231sd'. - 0x5169714B, // Large 'vfnmadd|231sh'. - 0x516E714B, // Large 'vfnmadd|231ss'. - 0x20A7714B, // Large 'vfnmadd|pd'. - 0x207D714B, // Large 'vfnmadd|ps'. - 0x2144714B, // Large 'vfnmadd|sd'. - 0x201C714B, // Large 'vfnmadd|ss'. - 0x20A7A173, // Large 'vfnmsub132|pd'. - 0x20A2A173, // Large 'vfnmsub132|ph'. - 0x207DA173, // Large 'vfnmsub132|ps'. - 0x2144A173, // Large 'vfnmsub132|sd'. - 0x20D5A173, // Large 'vfnmsub132|sh'. - 0x201CA173, // Large 'vfnmsub132|ss'. - 0x50A47173, // Large 'vfnmsub|213pd'. - 0x50A97173, // Large 'vfnmsub|213ph'. - 0x50AE7173, // Large 'vfnmsub|213ps'. - 0x51557173, // Large 'vfnmsub|213sd'. - 0x515A7173, // Large 'vfnmsub|213sh'. - 0x515F7173, // Large 'vfnmsub|213ss'. - 0x50B37173, // Large 'vfnmsub|231pd'. - 0x50B87173, // Large 'vfnmsub|231ph'. - 0x50BD7173, // Large 'vfnmsub|231ps'. - 0x51647173, // Large 'vfnmsub|231sd'. - 0x51697173, // Large 'vfnmsub|231sh'. - 0x516E7173, // Large 'vfnmsub|231ss'. - 0x20A77173, // Large 'vfnmsub|pd'. - 0x207D7173, // Large 'vfnmsub|ps'. - 0x21447173, // Large 'vfnmsub|sd'. - 0x201C7173, // Large 'vfnmsub|ss'. - 0x20A78329, // Large 'vfpclass|pd'. - 0x20A28329, // Large 'vfpclass|ph'. - 0x207D8329, // Large 'vfpclass|ps'. - 0x21448329, // Large 'vfpclass|sd'. - 0x20D58329, // Large 'vfpclass|sh'. - 0x201C8329, // Large 'vfpclass|ss'. - 0x20A757B0, // Large 'vfrcz|pd'. - 0x207D57B0, // Large 'vfrcz|ps'. - 0x214457B0, // Large 'vfrcz|sd'. - 0x201C57B0, // Large 'vfrcz|ss'. - 0x30ED7115, // Large 'vgather|dpd'. - 0x30F17115, // Large 'vgather|dps'. - 0x30EDA115, // Large 'vgatherpf0|dpd'. - 0x30F1A115, // Large 'vgatherpf0|dps'. - 0x30E6A115, // Large 'vgatherpf0|qpd'. - 0x30E9A115, // Large 'vgatherpf0|qps'. - 0x40EC9115, // Large 'vgatherpf|1dpd'. - 0x40F09115, // Large 'vgatherpf|1dps'. - 0x40F49115, // Large 'vgatherpf|1qpd'. - 0x40F89115, // Large 'vgatherpf|1qps'. - 0x30E67115, // Large 'vgather|qpd'. - 0x30E97115, // Large 'vgather|qps'. - 0x20A774B8, // Large 'vgetexp|pd'. - 0x20A274B8, // Large 'vgetexp|ph'. - 0x207D74B8, // Large 'vgetexp|ps'. - 0x214474B8, // Large 'vgetexp|sd'. - 0x20D574B8, // Large 'vgetexp|sh'. - 0x201C74B8, // Large 'vgetexp|ss'. - 0x31F17331, // Large 'vgetman|tpd'. - 0x31FC7331, // Large 'vgetman|tph'. - 0x32057331, // Large 'vgetman|tps'. - 0x320E7331, // Large 'vgetman|tsd'. - 0x32177331, // Large 'vgetman|tsh'. - 0x32207331, // Large 'vgetman|tss'. - 0x200FF000, // Large 'vgf2p8affineinv|qb'. - 0x200FC000, // Large 'vgf2p8affine|qb'. - 0x43386000, // Large 'vgf2p8|mulb'. - 0x30ED47B5, // Large 'vhad|dpd'. - 0x30F147B5, // Large 'vhad|dps'. - 0x20A757B9, // Large 'vhsub|pd'. - 0x207D57B9, // Large 'vhsub|ps'. - 0x306F8183, // Large 'vinsertf|128'. - 0x602A617D, // Large 'vinser|tf32x4'. - 0x40438183, // Large 'vinsertf|32x8'. - 0x40308183, // Large 'vinsertf|64x2'. - 0x40348183, // Large 'vinsertf|64x4'. - 0x40727183, // Large 'vinsert|i128'. - 0x503D7183, // Large 'vinsert|i32x4'. - 0x50427183, // Large 'vinsert|i32x8'. - 0x50477183, // Large 'vinsert|i64x2'. - 0x504C7183, // Large 'vinsert|i64x4'. - 0x207D7183, // Large 'vinsert|ps'. + 0x22AC7670, // Large 'vexpand|pd'. + 0x22827670, // Large 'vexpand|ps'. + 0x327492EF, // Large 'vextractf|128'. + 0x622F72E8, // Large 'vextrac|tf32x4'. + 0x424892EF, // Large 'vextractf|32x8'. + 0x423592EF, // Large 'vextractf|64x2'. + 0x423992EF, // Large 'vextractf|64x4'. + 0x427782EF, // Large 'vextract|i128'. + 0x524282EF, // Large 'vextract|i32x4'. + 0x524782EF, // Large 'vextract|i32x8'. + 0x524C82EF, // Large 'vextract|i64x2'. + 0x525182EF, // Large 'vextract|i64x4'. + 0x228282EF, // Large 'vextract|ps'. + 0x22A784FF, // Large 'vfcmaddc|ph'. + 0x22DA84FF, // Large 'vfcmaddc|sh'. + 0x22A77677, // Large 'vfcmulc|ph'. + 0x22DA7677, // Large 'vfcmulc|sh'. + 0x22AC93FF, // Large 'vfixupimm|pd'. + 0x228293FF, // Large 'vfixupimm|ps'. + 0x231D93FF, // Large 'vfixupimm|sd'. + 0x222293FF, // Large 'vfixupimm|ss'. + 0x22AC9408, // Large 'vfmadd132|pd'. + 0x22A79408, // Large 'vfmadd132|ph'. + 0x22829408, // Large 'vfmadd132|ps'. + 0x231D9408, // Large 'vfmadd132|sd'. + 0x22DA9408, // Large 'vfmadd132|sh'. + 0x22229408, // Large 'vfmadd132|ss'. + 0x52A9629B, // Large 'vfmadd|213pd'. + 0x52AE629B, // Large 'vfmadd|213ph'. + 0x52B3629B, // Large 'vfmadd|213ps'. + 0x532E629B, // Large 'vfmadd|213sd'. + 0x5333629B, // Large 'vfmadd|213sh'. + 0x5338629B, // Large 'vfmadd|213ss'. + 0x52B8629B, // Large 'vfmadd|231pd'. + 0x52BD629B, // Large 'vfmadd|231ph'. + 0x52C2629B, // Large 'vfmadd|231ps'. + 0x533D629B, // Large 'vfmadd|231sd'. + 0x5342629B, // Large 'vfmadd|231sh'. + 0x5347629B, // Large 'vfmadd|231ss'. + 0x367E629B, // Large 'vfmadd|cph'. + 0x3681629B, // Large 'vfmadd|csh'. + 0x22AC629B, // Large 'vfmadd|pd'. + 0x2282629B, // Large 'vfmadd|ps'. + 0x122B729B, // Large 'vfmadds|d'. + 0x1152729B, // Large 'vfmadds|s'. + 0x122BD29B, // Large 'vfmaddsub132p|d'. + 0x12A8D29B, // Large 'vfmaddsub132p|h'. + 0x1152D29B, // Large 'vfmaddsub132p|s'. + 0x52A9929B, // Large 'vfmaddsub|213pd'. + 0x52AE929B, // Large 'vfmaddsub|213ph'. + 0x52B3929B, // Large 'vfmaddsub|213ps'. + 0x52B8929B, // Large 'vfmaddsub|231pd'. + 0x52BD929B, // Large 'vfmaddsub|231ph'. + 0x52C2929B, // Large 'vfmaddsub|231ps'. + 0x22AC929B, // Large 'vfmaddsub|pd'. + 0x2282929B, // Large 'vfmaddsub|ps'. + 0x22AC9411, // Large 'vfmsub132|pd'. + 0x22A79411, // Large 'vfmsub132|ph'. + 0x22829411, // Large 'vfmsub132|ps'. + 0x231D9411, // Large 'vfmsub132|sd'. + 0x22DA9411, // Large 'vfmsub132|sh'. + 0x22229411, // Large 'vfmsub132|ss'. + 0x52A962C7, // Large 'vfmsub|213pd'. + 0x52AE62C7, // Large 'vfmsub|213ph'. + 0x52B362C7, // Large 'vfmsub|213ps'. + 0x532E62C7, // Large 'vfmsub|213sd'. + 0x533362C7, // Large 'vfmsub|213sh'. + 0x533862C7, // Large 'vfmsub|213ss'. + 0x52B862C7, // Large 'vfmsub|231pd'. + 0x52BD62C7, // Large 'vfmsub|231ph'. + 0x52C262C7, // Large 'vfmsub|231ps'. + 0x533D62C7, // Large 'vfmsub|231sd'. + 0x534262C7, // Large 'vfmsub|231sh'. + 0x534762C7, // Large 'vfmsub|231ss'. + 0x22ACC2C7, // Large 'vfmsubadd132|pd'. + 0x22A7C2C7, // Large 'vfmsubadd132|ph'. + 0x2282C2C7, // Large 'vfmsubadd132|ps'. + 0x52A992C7, // Large 'vfmsubadd|213pd'. + 0x52AE92C7, // Large 'vfmsubadd|213ph'. + 0x52B392C7, // Large 'vfmsubadd|213ps'. + 0x52B892C7, // Large 'vfmsubadd|231pd'. + 0x52BD92C7, // Large 'vfmsubadd|231ph'. + 0x52C292C7, // Large 'vfmsubadd|231ps'. + 0x22AC92C7, // Large 'vfmsubadd|pd'. + 0x228292C7, // Large 'vfmsubadd|ps'. + 0x22AC62C7, // Large 'vfmsub|pd'. + 0x228262C7, // Large 'vfmsub|ps'. + 0x231D62C7, // Large 'vfmsub|sd'. + 0x222262C7, // Large 'vfmsub|ss'. + 0x367E580F, // Large 'vfmul|cph'. + 0x3681580F, // Large 'vfmul|csh'. + 0x22ACA324, // Large 'vfnmadd132|pd'. + 0x22A7A324, // Large 'vfnmadd132|ph'. + 0x2282A324, // Large 'vfnmadd132|ps'. + 0x231DA324, // Large 'vfnmadd132|sd'. + 0x22DAA324, // Large 'vfnmadd132|sh'. + 0x2222A324, // Large 'vfnmadd132|ss'. + 0x52A97324, // Large 'vfnmadd|213pd'. + 0x52AE7324, // Large 'vfnmadd|213ph'. + 0x52B37324, // Large 'vfnmadd|213ps'. + 0x532E7324, // Large 'vfnmadd|213sd'. + 0x53337324, // Large 'vfnmadd|213sh'. + 0x53387324, // Large 'vfnmadd|213ss'. + 0x52B87324, // Large 'vfnmadd|231pd'. + 0x52BD7324, // Large 'vfnmadd|231ph'. + 0x52C27324, // Large 'vfnmadd|231ps'. + 0x533D7324, // Large 'vfnmadd|231sd'. + 0x53427324, // Large 'vfnmadd|231sh'. + 0x53477324, // Large 'vfnmadd|231ss'. + 0x22AC7324, // Large 'vfnmadd|pd'. + 0x22827324, // Large 'vfnmadd|ps'. + 0x231D7324, // Large 'vfnmadd|sd'. + 0x22227324, // Large 'vfnmadd|ss'. + 0x22ACA34C, // Large 'vfnmsub132|pd'. + 0x22A7A34C, // Large 'vfnmsub132|ph'. + 0x2282A34C, // Large 'vfnmsub132|ps'. + 0x231DA34C, // Large 'vfnmsub132|sd'. + 0x22DAA34C, // Large 'vfnmsub132|sh'. + 0x2222A34C, // Large 'vfnmsub132|ss'. + 0x52A9734C, // Large 'vfnmsub|213pd'. + 0x52AE734C, // Large 'vfnmsub|213ph'. + 0x52B3734C, // Large 'vfnmsub|213ps'. + 0x532E734C, // Large 'vfnmsub|213sd'. + 0x5333734C, // Large 'vfnmsub|213sh'. + 0x5338734C, // Large 'vfnmsub|213ss'. + 0x52B8734C, // Large 'vfnmsub|231pd'. + 0x52BD734C, // Large 'vfnmsub|231ph'. + 0x52C2734C, // Large 'vfnmsub|231ps'. + 0x533D734C, // Large 'vfnmsub|231sd'. + 0x5342734C, // Large 'vfnmsub|231sh'. + 0x5347734C, // Large 'vfnmsub|231ss'. + 0x22AC734C, // Large 'vfnmsub|pd'. + 0x2282734C, // Large 'vfnmsub|ps'. + 0x231D734C, // Large 'vfnmsub|sd'. + 0x2222734C, // Large 'vfnmsub|ss'. + 0x22AC8507, // Large 'vfpclass|pd'. + 0x22A78507, // Large 'vfpclass|ph'. + 0x22828507, // Large 'vfpclass|ps'. + 0x231D8507, // Large 'vfpclass|sd'. + 0x22DA8507, // Large 'vfpclass|sh'. + 0x22228507, // Large 'vfpclass|ss'. + 0x22AC5975, // Large 'vfrcz|pd'. + 0x22825975, // Large 'vfrcz|ps'. + 0x231D5975, // Large 'vfrcz|sd'. + 0x22225975, // Large 'vfrcz|ss'. + 0x22AC850F, // Large 'vgatherd|pd'. + 0x2282850F, // Large 'vgatherd|ps'. + 0x3478750F, // Large 'vgather|qpd'. + 0x347B750F, // Large 'vgather|qps'. + 0x22AC7684, // Large 'vgetexp|pd'. + 0x22A77684, // Large 'vgetexp|ph'. + 0x22827684, // Large 'vgetexp|ps'. + 0x231D7684, // Large 'vgetexp|sd'. + 0x22DA7684, // Large 'vgetexp|sh'. + 0x22227684, // Large 'vgetexp|ss'. + 0x33CA7517, // Large 'vgetman|tpd'. + 0x33D67517, // Large 'vgetman|tph'. + 0x33E17517, // Large 'vgetman|tps'. + 0x33E87517, // Large 'vgetman|tsd'. + 0x33F17517, // Large 'vgetman|tsh'. + 0x33FA7517, // Large 'vgetman|tss'. + 0x2215F206, // Large 'vgf2p8affineinv|qb'. + 0x2215C206, // Large 'vgf2p8affine|qb'. + 0x451E6206, // Large 'vgf2p8|mulb'. + 0x22AC597A, // Large 'vhadd|pd'. + 0x2282597A, // Large 'vhadd|ps'. + 0x22AC597F, // Large 'vhsub|pd'. + 0x2282597F, // Large 'vhsub|ps'. + 0x3274835C, // Large 'vinsertf|128'. + 0x622F6356, // Large 'vinser|tf32x4'. + 0x4248835C, // Large 'vinsertf|32x8'. + 0x4235835C, // Large 'vinsertf|64x2'. + 0x4239835C, // Large 'vinsertf|64x4'. + 0x4277735C, // Large 'vinsert|i128'. + 0x5242735C, // Large 'vinsert|i32x4'. + 0x5247735C, // Large 'vinsert|i32x8'. + 0x524C735C, // Large 'vinsert|i64x2'. + 0x5251735C, // Large 'vinsert|i64x4'. + 0x2282735C, // Large 'vinsert|ps'. 0xAB121196, // Small 'vlddqu'. - 0x1023764A, // Large 'vldmxcs|r'. - 0x109DA240, // Large 'vmaskmovdq|u'. - 0x20A78240, // Large 'vmaskmov|pd'. - 0x207D8240, // Large 'vmaskmov|ps'. + 0x12287814, // Large 'vldmxcs|r'. + 0x12A2A41A, // Large 'vmaskmovdq|u'. + 0x22AC841A, // Large 'vmaskmov|pd'. + 0x2282841A, // Large 'vmaskmov|ps'. 0x890C05B6, // Small 'vmaxpd'. 0x910C05B6, // Small 'vmaxph'. 0xA70C05B6, // Small 'vmaxps'. @@ -4163,56 +4066,56 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x913C05B6, // Small 'vmaxsh'. 0xA73C05B6, // Small 'vmaxss'. 0x98C08DB6, // Small 'vmcall'. - 0x242857BE, // Large 'vmcle|ar'. + 0x25F95984, // Large 'vmcle|ar'. 0x86EA99B6, // Small 'vmfunc'. - 0x219257C3, // Large 'vmgex|it'. + 0x236B5989, // Large 'vmgex|it'. 0x890725B6, // Small 'vminpd'. 0x910725B6, // Small 'vminph'. 0xA70725B6, // Small 'vminps'. 0x893725B6, // Small 'vminsd'. 0x913725B6, // Small 'vminsh'. 0xA73725B6, // Small 'vminss'. - 0x21A56651, // Large 'vmlaun|ch'. + 0x237E681B, // Large 'vmlaun|ch'. 0x8817B1B6, // Small 'vmload'. - 0x36F347C8, // Large 'vmmc|all'. - 0x20A757CC, // Large 'vmova|pd'. - 0x207D57CC, // Large 'vmova|ps'. + 0x38B9498E, // Large 'vmmc|all'. + 0x22AC5992, // Large 'vmova|pd'. + 0x22825992, // Large 'vmova|ps'. 0x804B3DB6, // Small 'vmovd'. - 0x365754BF, // Large 'vmovd|dup'. - 0x000074BF, // Large 'vmovdqa'. - 0x202C74BF, // Large 'vmovdqa|32'. - 0x203074BF, // Large 'vmovdqa|64'. - 0x109D64BF, // Large 'vmovdq|u'. - 0x34C664BF, // Large 'vmovdq|u16'. - 0x34C964BF, // Large 'vmovdq|u32'. - 0x34CC64BF, // Large 'vmovdq|u64'. - 0x265A64BF, // Large 'vmovdq|u8'. - 0x359A565C, // Large 'vmovh|lps'. - 0x20A7565C, // Large 'vmovh|pd'. - 0x207D565C, // Large 'vmovh|ps'. - 0x207D6661, // Large 'vmovlh|ps'. - 0x20A75661, // Large 'vmovl|pd'. - 0x207D5661, // Large 'vmovl|ps'. - 0x20A774CF, // Large 'vmovmsk|pd'. - 0x207D74CF, // Large 'vmovmsk|ps'. - 0x20E564D6, // Large 'vmovnt|dq'. - 0x34C364D6, // Large 'vmovnt|dqa'. - 0x20A764D6, // Large 'vmovnt|pd'. - 0x207D64D6, // Large 'vmovnt|ps'. + 0x3821568B, // Large 'vmovd|dup'. + 0x0000768B, // Large 'vmovdqa'. + 0x2231768B, // Large 'vmovdqa|32'. + 0x2235768B, // Large 'vmovdqa|64'. + 0x12A2668B, // Large 'vmovdq|u'. + 0x3692668B, // Large 'vmovdq|u16'. + 0x3695668B, // Large 'vmovdq|u32'. + 0x3698668B, // Large 'vmovdq|u64'. + 0x2824668B, // Large 'vmovdq|u8'. + 0x37665826, // Large 'vmovh|lps'. + 0x22AC5826, // Large 'vmovh|pd'. + 0x22825826, // Large 'vmovh|ps'. + 0x2282682B, // Large 'vmovlh|ps'. + 0x22AC582B, // Large 'vmovl|pd'. + 0x2282582B, // Large 'vmovl|ps'. + 0x22AC769B, // Large 'vmovmsk|pd'. + 0x2282769B, // Large 'vmovmsk|ps'. + 0x23CF66A2, // Large 'vmovnt|dq'. + 0x368F66A2, // Large 'vmovnt|dqa'. + 0x22AC66A2, // Large 'vmovnt|pd'. + 0x228266A2, // Large 'vmovnt|ps'. 0x811B3DB6, // Small 'vmovq'. 0x893B3DB6, // Small 'vmovsd'. 0x913B3DB6, // Small 'vmovsh'. - 0x222974DC, // Large 'vmovshd|up'. - 0x222974E3, // Large 'vmovsld|up'. + 0x240376A8, // Large 'vmovshd|up'. + 0x240376AF, // Large 'vmovsld|up'. 0xA73B3DB6, // Small 'vmovss'. - 0x343344BF, // Large 'vmov|upd'. - 0x207D57D1, // Large 'vmovu|ps'. + 0x3604468B, // Large 'vmov|upd'. + 0x22825997, // Large 'vmovu|ps'. 0x817B3DB6, // Small 'vmovw'. - 0x239A6667, // Large 'vmpsad|bw'. - 0x341147D6, // Large 'vmpt|rld'. - 0x340D47D6, // Large 'vmpt|rst'. + 0x25786831, // Large 'vmpsad|bw'. + 0x35E2499C, // Large 'vmpt|rld'. + 0x35DE499C, // Large 'vmpt|rst'. 0x8812C9B6, // Small 'vmread'. - 0x100B766D, // Large 'vmresum|e'. + 0x100F7837, // Large 'vmresum|e'. 0x80EAC9B6, // Small 'vmrun'. 0x8B60CDB6, // Small 'vmsave'. 0x890655B6, // Small 'vmulpd'. @@ -4221,460 +4124,442 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x893655B6, // Small 'vmulsd'. 0x913655B6, // Small 'vmulsh'. 0xA73655B6, // Small 'vmulss'. - 0x20DF57DA, // Large 'vmwri|te'. + 0x22FD59A0, // Large 'vmwri|te'. 0x8C67E1B6, // Small 'vmxoff'. 0x80E7E1B6, // Small 'vmxon'. 0x804849F6, // Small 'vorpd'. 0x813849F6, // Small 'vorps'. - 0x1026C11F, // Large 'vp2intersect|d'. - 0x100FC11F, // Large 'vp2intersect|q'. - 0x1026833C, // Large 'vp4dpwss|d'. - 0x209B833C, // Large 'vp4dpwss|ds'. + 0x122BC2F8, // Large 'vp2intersect|d'. + 0x1215C2F8, // Large 'vp2intersect|q'. 0x85310616, // Small 'vpabsb'. 0x89310616, // Small 'vpabsd'. 0xA3310616, // Small 'vpabsq'. 0xAF310616, // Small 'vpabsw'. - 0x105F84EA, // Large 'vpackssd|w'. - 0x24F274EA, // Large 'vpackss|wb'. - 0x34F064F4, // Large 'vpacku|sdw'. - 0x34FA64F4, // Large 'vpacku|swb'. + 0x126486B6, // Large 'vpackssd|w'. + 0x26BE76B6, // Large 'vpackss|wb'. + 0x36BC66C0, // Large 'vpacku|sdw'. + 0x36C666C0, // Large 'vpacku|swb'. 0x84420616, // Small 'vpaddb'. 0x88420616, // Small 'vpaddd'. 0xA2420616, // Small 'vpaddq'. - 0x25BA5674, // Large 'vpadd|sb'. - 0x23835674, // Large 'vpadd|sw'. - 0x25BA6674, // Large 'vpaddu|sb'. - 0x23836674, // Large 'vpaddu|sw'. + 0x2786583E, // Large 'vpadd|sb'. + 0x2561583E, // Large 'vpadd|sw'. + 0x2786683E, // Large 'vpaddu|sb'. + 0x2561683E, // Large 'vpaddu|sw'. 0xAE420616, // Small 'vpaddw'. - 0x1023767A, // Large 'vpalign|r'. + 0x12287844, // Large 'vpalign|r'. 0x80470616, // Small 'vpand'. 0x88470616, // Small 'vpandd'. 0x9C470616, // Small 'vpandn'. - 0x219D57DF, // Large 'vpand|nd'. - 0x271E57DF, // Large 'vpand|nq'. + 0x237659A5, // Large 'vpand|nd'. + 0x28DF59A5, // Large 'vpand|nq'. 0xA2470616, // Small 'vpandq'. 0x847B0616, // Small 'vpavgb'. 0xAE7B0616, // Small 'vpavgw'. - 0x102674FD, // Large 'vpblend|d'. - 0x205C74FD, // Large 'vpblend|mb'. - 0x250474FD, // Large 'vpblend|md'. - 0x100F84FD, // Large 'vpblendm|q'. - 0x105F84FD, // Large 'vpblendm|w'. - 0x202174FD, // Large 'vpblend|vb'. - 0x105F74FD, // Large 'vpblend|w'. - 0x1010B051, // Large 'vpbroadcast|b'. - 0x1026B051, // Large 'vpbroadcast|d'. - 0x100FE051, // Large 'vpbroadcastmb2|q'. - 0x305FC051, // Large 'vpbroadcastm|w2d'. - 0x100FB051, // Large 'vpbroadcast|q'. - 0x105FB051, // Large 'vpbroadcast|w'. - 0x42886344, // Large 'vpclmu|lqdq'. + 0x122B76C9, // Large 'vpblend|d'. + 0x226176C9, // Large 'vpblend|mb'. + 0x26D076C9, // Large 'vpblend|md'. + 0x121586C9, // Large 'vpblendm|q'. + 0x126486C9, // Large 'vpblendm|w'. + 0x200376C9, // Large 'vpblend|vb'. + 0x126476C9, // Large 'vpblend|w'. + 0x1004B256, // Large 'vpbroadcast|b'. + 0x122BB256, // Large 'vpbroadcast|d'. + 0x1215E256, // Large 'vpbroadcastmb2|q'. + 0x3264C256, // Large 'vpbroadcastm|w2d'. + 0x1215B256, // Large 'vpbroadcast|q'. + 0x1264B256, // Large 'vpbroadcast|w'. + 0x44626522, // Large 'vpclmu|lqdq'. 0xACF68E16, // Small 'vpcmov'. 0x85068E16, // Small 'vpcmpb'. 0x89068E16, // Small 'vpcmpd'. - 0x200F634A, // Large 'vpcmpe|qb'. - 0x227D634A, // Large 'vpcmpe|qd'. - 0x21F6634A, // Large 'vpcmpe|qq'. - 0x2559634A, // Large 'vpcmpe|qw'. - 0x1009934A, // Large 'vpcmpestr|i'. - 0x105C934A, // Large 'vpcmpestr|m'. - 0x3681534A, // Large 'vpcmp|gtb'. - 0x3684534A, // Large 'vpcmp|gtd'. - 0x3687534A, // Large 'vpcmp|gtq'. - 0x368A534A, // Large 'vpcmp|gtw'. - 0x10099353, // Large 'vpcmpistr|i'. - 0x105C9353, // Large 'vpcmpistr|m'. + 0x22156528, // Large 'vpcmpe|qb'. + 0x24576528, // Large 'vpcmpe|qd'. + 0x23D06528, // Large 'vpcmpe|qq'. + 0x27256528, // Large 'vpcmpe|qw'. + 0x120F9528, // Large 'vpcmpestr|i'. + 0x10019528, // Large 'vpcmpestr|m'. + 0x384B5528, // Large 'vpcmp|gtb'. + 0x384E5528, // Large 'vpcmp|gtd'. + 0x38515528, // Large 'vpcmp|gtq'. + 0x38545528, // Large 'vpcmp|gtw'. + 0x120F9531, // Large 'vpcmpistr|i'. + 0x10019531, // Large 'vpcmpistr|m'. 0xA3068E16, // Small 'vpcmpq'. - 0x209D534A, // Large 'vpcmp|ub'. - 0x22E5534A, // Large 'vpcmp|ud'. - 0x21F5534A, // Large 'vpcmp|uq'. - 0x2481534A, // Large 'vpcmp|uw'. + 0x22A25528, // Large 'vpcmp|ub'. + 0x23CE5528, // Large 'vpcmp|ud'. + 0x23DA5528, // Large 'vpcmp|uq'. + 0x264C5528, // Large 'vpcmp|uw'. 0xAF068E16, // Small 'vpcmpw'. 0x84D78E16, // Small 'vpcomb'. 0x88D78E16, // Small 'vpcomd'. - 0x1010A24A, // Large 'vpcompress|b'. - 0x1026A24A, // Large 'vpcompress|d'. - 0x100FA24A, // Large 'vpcompress|q'. - 0x105FA24A, // Large 'vpcompress|w'. + 0x1004A424, // Large 'vpcompress|b'. + 0x122BA424, // Large 'vpcompress|d'. + 0x1215A424, // Large 'vpcompress|q'. + 0x1264A424, // Large 'vpcompress|w'. 0xA2D78E16, // Small 'vpcomq'. - 0x209D524A, // Large 'vpcom|ub'. - 0x22E5524A, // Large 'vpcom|ud'. - 0x21F5524A, // Large 'vpcom|uq'. - 0x2481524A, // Large 'vpcom|uw'. + 0x22A25424, // Large 'vpcom|ub'. + 0x23CE5424, // Large 'vpcom|ud'. + 0x23DA5424, // Large 'vpcom|uq'. + 0x264C5424, // Large 'vpcom|uw'. 0xAED78E16, // Small 'vpcomw'. - 0x1026A254, // Large 'vpconflict|d'. - 0x100FA254, // Large 'vpconflict|q'. - 0x10267506, // Large 'vpdpbss|d'. - 0x209B7506, // Large 'vpdpbss|ds'. - 0x22E56506, // Large 'vpdpbs|ud'. - 0x350D6506, // Large 'vpdpbs|uds'. - 0x10267510, // Large 'vpdpbus|d'. - 0x209B7510, // Large 'vpdpbus|ds'. - 0x22E56510, // Large 'vpdpbu|ud'. - 0x350D6510, // Large 'vpdpbu|uds'. - 0x10267517, // Large 'vpdpwss|d'. - 0x209B7517, // Large 'vpdpwss|ds'. - 0x22E56517, // Large 'vpdpws|ud'. - 0x350D6517, // Large 'vpdpws|uds'. - 0x1026751E, // Large 'vpdpwus|d'. - 0x209B751E, // Large 'vpdpwus|ds'. - 0x22E5651E, // Large 'vpdpwu|ud'. - 0x350D651E, // Large 'vpdpwu|uds'. - 0x306F735C, // Large 'vperm2f|128'. - 0x4072635C, // Large 'vperm2|i128'. + 0x122BA42E, // Large 'vpconflict|d'. + 0x1215A42E, // Large 'vpconflict|q'. + 0x122B76D2, // Large 'vpdpbss|d'. + 0x22A076D2, // Large 'vpdpbss|ds'. + 0x23CE66D2, // Large 'vpdpbs|ud'. + 0x36D966D2, // Large 'vpdpbs|uds'. + 0x122B76DC, // Large 'vpdpbus|d'. + 0x22A076DC, // Large 'vpdpbus|ds'. + 0x23CE66DC, // Large 'vpdpbu|ud'. + 0x36D966DC, // Large 'vpdpbu|uds'. + 0x122B76E3, // Large 'vpdpwss|d'. + 0x22A076E3, // Large 'vpdpwss|ds'. + 0x23CE66E3, // Large 'vpdpws|ud'. + 0x36D966E3, // Large 'vpdpws|uds'. + 0x122B76EA, // Large 'vpdpwus|d'. + 0x22A076EA, // Large 'vpdpwus|ds'. + 0x23CE66EA, // Large 'vpdpwu|ud'. + 0x36D966EA, // Large 'vpdpwu|uds'. + 0x3274753A, // Large 'vperm2f|128'. + 0x4277653A, // Large 'vperm2|i128'. 0x84D91616, // Small 'vpermb'. 0x88D91616, // Small 'vpermd'. - 0x268D6363, // Large 'vpermi|2b'. - 0x20606363, // Large 'vpermi|2d'. - 0x35256363, // Large 'vpermi|2pd'. - 0x307C6363, // Large 'vpermi|2ps'. - 0x268F6363, // Large 'vpermi|2q'. - 0x205E6363, // Large 'vpermi|2w'. - 0x20A78363, // Large 'vpermil2|pd'. - 0x207D8363, // Large 'vpermil2|ps'. - 0x20A77363, // Large 'vpermil|pd'. - 0x207D7363, // Large 'vpermil|ps'. - 0x20A7535C, // Large 'vperm|pd'. - 0x207D535C, // Large 'vperm|ps'. + 0x28576541, // Large 'vpermi|2b'. + 0x22656541, // Large 'vpermi|2d'. + 0x36F16541, // Large 'vpermi|2pd'. + 0x32816541, // Large 'vpermi|2ps'. + 0x24E46541, // Large 'vpermi|2q'. + 0x22636541, // Large 'vpermi|2w'. + 0x22AC8541, // Large 'vpermil2|pd'. + 0x22828541, // Large 'vpermil2|ps'. + 0x22AC7541, // Large 'vpermil|pd'. + 0x22827541, // Large 'vpermil|ps'. + 0x22AC553A, // Large 'vperm|pd'. + 0x2282553A, // Large 'vperm|ps'. 0xA2D91616, // Small 'vpermq'. - 0x268D6528, // Large 'vpermt|2b'. - 0x20606528, // Large 'vpermt|2d'. - 0x35256528, // Large 'vpermt|2pd'. - 0x307C6528, // Large 'vpermt|2ps'. - 0x268F6528, // Large 'vpermt|2q'. - 0x205E6528, // Large 'vpermt|2w'. + 0x285766F4, // Large 'vpermt|2b'. + 0x226566F4, // Large 'vpermt|2d'. + 0x36F166F4, // Large 'vpermt|2pd'. + 0x328166F4, // Large 'vpermt|2ps'. + 0x24E466F4, // Large 'vpermt|2q'. + 0x226366F4, // Large 'vpermt|2w'. 0xAED91616, // Small 'vpermw'. - 0x2498752E, // Large 'vpexpan|db'. - 0x209A752E, // Large 'vpexpan|dd'. - 0x20E5752E, // Large 'vpexpan|dq'. - 0x24F1752E, // Large 'vpexpan|dw'. - 0x35F7452E, // Large 'vpex|trb'. - 0x261657E4, // Large 'vpext|rd'. - 0x227C57E4, // Large 'vpext|rq'. - 0x27E957E4, // Large 'vpext|rw'. - 0x209A836B, // Large 'vpgather|dd'. - 0x20E5836B, // Large 'vpgather|dq'. - 0x227D836B, // Large 'vpgather|qd'. - 0x21F6836B, // Large 'vpgather|qq'. - 0x26916535, // Large 'vphadd|bd'. - 0x26936535, // Large 'vphadd|bq'. - 0x239A6535, // Large 'vphadd|bw'. - 0x10266535, // Large 'vphadd|d'. - 0x20E56535, // Large 'vphadd|dq'. - 0x23836535, // Large 'vphadd|sw'. - 0x10268535, // Large 'vphaddub|d'. - 0x100F8535, // Large 'vphaddub|q'. - 0x105F8535, // Large 'vphaddub|w'. - 0x20E57535, // Large 'vphaddu|dq'. - 0x239C7535, // Large 'vphaddu|wd'. - 0x253D7535, // Large 'vphaddu|wq'. - 0x105F6535, // Large 'vphadd|w'. - 0x239C6535, // Large 'vphadd|wd'. - 0x253D6535, // Large 'vphadd|wq'. - 0x105FA25E, // Large 'vphminposu|w'. - 0x239A6695, // Large 'vphsub|bw'. - 0x10266695, // Large 'vphsub|d'. - 0x20E56695, // Large 'vphsub|dq'. - 0x23836695, // Large 'vphsub|sw'. - 0x105F6695, // Large 'vphsub|w'. - 0x239C6695, // Large 'vphsub|wd'. - 0x25F857EB, // Large 'vpins|rb'. - 0x261657EB, // Large 'vpins|rd'. - 0x227C57EB, // Large 'vpins|rq'. - 0x27E957EB, // Large 'vpins|rw'. - 0x2455669B, // Large 'vplzcn|td'. - 0x2193669B, // Large 'vplzcn|tq'. - 0x209A6373, // Large 'vpmacs|dd'. - 0x353F6373, // Large 'vpmacs|dqh'. - 0x33A26373, // Large 'vpmacs|dql'. - 0x10268373, // Large 'vpmacssd|d'. - 0x10A39373, // Large 'vpmacssdq|h'. - 0x10D29373, // Large 'vpmacssdq|l'. - 0x239C7373, // Large 'vpmacss|wd'. - 0x239B7373, // Large 'vpmacss|ww'. - 0x239C6373, // Large 'vpmacs|wd'. - 0x239B6373, // Large 'vpmacs|ww'. - 0x1026937C, // Large 'vpmadcssw|d'. - 0x239C737C, // Large 'vpmadcs|wd'. - 0x21F59268, // Large 'vpmadd52h|uq'. - 0x32718268, // Large 'vpmadd52|luq'. - 0x43856268, // Large 'vpmadd|ubsw'. - 0x239C6268, // Large 'vpmadd|wd'. - 0x62434268, // Large 'vpma|skmovd'. - 0x200E8389, // Large 'vpmaskmo|vq'. - 0x25BA57F0, // Large 'vpmax|sb'. - 0x214457F0, // Large 'vpmax|sd'. - 0x23A957F0, // Large 'vpmax|sq'. - 0x238357F0, // Large 'vpmax|sw'. - 0x209D57F0, // Large 'vpmax|ub'. - 0x22E557F0, // Large 'vpmax|ud'. - 0x21F557F0, // Large 'vpmax|uq'. - 0x248157F0, // Large 'vpmax|uw'. - 0x25BA57F5, // Large 'vpmin|sb'. - 0x214457F5, // Large 'vpmin|sd'. - 0x23A957F5, // Large 'vpmin|sq'. - 0x238357F5, // Large 'vpmin|sw'. - 0x209D57F5, // Large 'vpmin|ub'. - 0x22E557F5, // Large 'vpmin|ud'. - 0x21F557F5, // Large 'vpmin|uq'. - 0x248157F5, // Large 'vpmin|uw'. - 0x36A15542, // Large 'vpmov|b2m'. - 0x36A45542, // Large 'vpmov|d2m'. - 0x24985542, // Large 'vpmov|db'. - 0x24F15542, // Large 'vpmov|dw'. - 0x268D6542, // Large 'vpmovm|2b'. - 0x20606542, // Large 'vpmovm|2d'. - 0x268F6542, // Large 'vpmovm|2q'. - 0x205E6542, // Large 'vpmovm|2w'. - 0x10108542, // Large 'vpmovmsk|b'. - 0x36A75542, // Large 'vpmov|q2m'. - 0x200F5542, // Large 'vpmov|qb'. - 0x227D5542, // Large 'vpmov|qd'. - 0x25595542, // Large 'vpmov|qw'. - 0x2498654A, // Large 'vpmovs|db'. - 0x24F1654A, // Large 'vpmovs|dw'. - 0x200F654A, // Large 'vpmovs|qb'. - 0x227D654A, // Large 'vpmovs|qd'. - 0x2559654A, // Large 'vpmovs|qw'. - 0x24F2654A, // Large 'vpmovs|wb'. - 0x1026854A, // Large 'vpmovsxb|d'. - 0x100F854A, // Large 'vpmovsxb|q'. - 0x105F854A, // Large 'vpmovsxb|w'. - 0x20E5754A, // Large 'vpmovsx|dq'. - 0x239C754A, // Large 'vpmovsx|wd'. - 0x253D754A, // Large 'vpmovsx|wq'. - 0x24987552, // Large 'vpmovus|db'. - 0x24F17552, // Large 'vpmovus|dw'. - 0x200F7552, // Large 'vpmovus|qb'. - 0x227D7552, // Large 'vpmovus|qd'. - 0x25597552, // Large 'vpmovus|qw'. - 0x24F27552, // Large 'vpmovus|wb'. - 0x36AA5542, // Large 'vpmov|w2m'. - 0x24F25542, // Large 'vpmov|wb'. - 0x1026855B, // Large 'vpmovzxb|d'. - 0x100F855B, // Large 'vpmovzxb|q'. - 0x105F855B, // Large 'vpmovzxb|w'. - 0x20E5755B, // Large 'vpmovzx|dq'. - 0x239C755B, // Large 'vpmovzx|wd'. - 0x253D755B, // Large 'vpmovzx|wq'. - 0x20E550CE, // Large 'vpmul|dq'. - 0x23837563, // Large 'vpmulhr|sw'. - 0x24816563, // Large 'vpmulh|uw'. - 0x105F6563, // Large 'vpmulh|w'. - 0x23A150CE, // Large 'vpmul|ld'. - 0x228850CE, // Large 'vpmul|lq'. - 0x23A450CE, // Large 'vpmul|lw'. - 0x200FC0CE, // Large 'vpmultishift|qb'. - 0x32E550CE, // Large 'vpmul|udq'. - 0x268266AD, // Large 'vpopcn|tb'. - 0x245566AD, // Large 'vpopcn|td'. - 0x219366AD, // Large 'vpopcn|tq'. - 0x264366AD, // Large 'vpopcn|tw'. + 0x266376FA, // Large 'vpexpan|db'. + 0x229F76FA, // Large 'vpexpan|dd'. + 0x23CF76FA, // Large 'vpexpan|dq'. + 0x26BD76FA, // Large 'vpexpan|dw'. + 0x37BF46FA, // Large 'vpex|trb'. + 0x247659AA, // Large 'vpext|rd'. + 0x245659AA, // Large 'vpext|rq'. + 0x29AF59AA, // Large 'vpext|rw'. + 0x229F8549, // Large 'vpgather|dd'. + 0x23CF8549, // Large 'vpgather|dq'. + 0x24578549, // Large 'vpgather|qd'. + 0x23D08549, // Large 'vpgather|qq'. + 0x28596701, // Large 'vphadd|bd'. + 0x285B6701, // Large 'vphadd|bq'. + 0x25786701, // Large 'vphadd|bw'. + 0x122B6701, // Large 'vphadd|d'. + 0x23CF6701, // Large 'vphadd|dq'. + 0x25616701, // Large 'vphadd|sw'. + 0x122B8701, // Large 'vphaddub|d'. + 0x12158701, // Large 'vphaddub|q'. + 0x12648701, // Large 'vphaddub|w'. + 0x23CF7701, // Large 'vphaddu|dq'. + 0x257A7701, // Large 'vphaddu|wd'. + 0x27097701, // Large 'vphaddu|wq'. + 0x12646701, // Large 'vphadd|w'. + 0x257A6701, // Large 'vphadd|wd'. + 0x27096701, // Large 'vphadd|wq'. + 0x1264A438, // Large 'vphminposu|w'. + 0x2578685D, // Large 'vphsub|bw'. + 0x122B685D, // Large 'vphsub|d'. + 0x23CF685D, // Large 'vphsub|dq'. + 0x2561685D, // Large 'vphsub|sw'. + 0x1264685D, // Large 'vphsub|w'. + 0x257A685D, // Large 'vphsub|wd'. + 0x27C059B1, // Large 'vpins|rb'. + 0x247659B1, // Large 'vpins|rd'. + 0x245659B1, // Large 'vpins|rq'. + 0x29AF59B1, // Large 'vpins|rw'. + 0x26266863, // Large 'vplzcn|td'. + 0x236C6863, // Large 'vplzcn|tq'. + 0x229F6551, // Large 'vpmacs|dd'. + 0x370B6551, // Large 'vpmacs|dqh'. + 0x35806551, // Large 'vpmacs|dql'. + 0x122B8551, // Large 'vpmacssd|d'. + 0x12A89551, // Large 'vpmacssdq|h'. + 0x10279551, // Large 'vpmacssdq|l'. + 0x257A7551, // Large 'vpmacss|wd'. + 0x25797551, // Large 'vpmacss|ww'. + 0x257A6551, // Large 'vpmacs|wd'. + 0x25796551, // Large 'vpmacs|ww'. + 0x122B955A, // Large 'vpmadcssw|d'. + 0x257A755A, // Large 'vpmadcs|wd'. + 0x23DA9442, // Large 'vpmadd52h|uq'. + 0x344B8442, // Large 'vpmadd52|luq'. + 0x45636442, // Large 'vpmadd|ubsw'. + 0x257A6442, // Large 'vpmadd|wd'. + 0x641D4442, // Large 'vpma|skmovd'. + 0x22148567, // Large 'vpmaskmo|vq'. + 0x278659B6, // Large 'vpmax|sb'. + 0x231D59B6, // Large 'vpmax|sd'. + 0x258759B6, // Large 'vpmax|sq'. + 0x256159B6, // Large 'vpmax|sw'. + 0x22A259B6, // Large 'vpmax|ub'. + 0x23CE59B6, // Large 'vpmax|ud'. + 0x23DA59B6, // Large 'vpmax|uq'. + 0x264C59B6, // Large 'vpmax|uw'. + 0x278659BB, // Large 'vpmin|sb'. + 0x231D59BB, // Large 'vpmin|sd'. + 0x258759BB, // Large 'vpmin|sq'. + 0x256159BB, // Large 'vpmin|sw'. + 0x22A259BB, // Large 'vpmin|ub'. + 0x23CE59BB, // Large 'vpmin|ud'. + 0x23DA59BB, // Large 'vpmin|uq'. + 0x264C59BB, // Large 'vpmin|uw'. + 0x3869570E, // Large 'vpmov|b2m'. + 0x386C570E, // Large 'vpmov|d2m'. + 0x2663570E, // Large 'vpmov|db'. + 0x26BD570E, // Large 'vpmov|dw'. + 0x2857670E, // Large 'vpmovm|2b'. + 0x2265670E, // Large 'vpmovm|2d'. + 0x24E4670E, // Large 'vpmovm|2q'. + 0x2263670E, // Large 'vpmovm|2w'. + 0x1004870E, // Large 'vpmovmsk|b'. + 0x386F570E, // Large 'vpmov|q2m'. + 0x2215570E, // Large 'vpmov|qb'. + 0x2457570E, // Large 'vpmov|qd'. + 0x2725570E, // Large 'vpmov|qw'. + 0x26636716, // Large 'vpmovs|db'. + 0x26BD6716, // Large 'vpmovs|dw'. + 0x22156716, // Large 'vpmovs|qb'. + 0x24576716, // Large 'vpmovs|qd'. + 0x27256716, // Large 'vpmovs|qw'. + 0x26BE6716, // Large 'vpmovs|wb'. + 0x122B8716, // Large 'vpmovsxb|d'. + 0x12158716, // Large 'vpmovsxb|q'. + 0x12648716, // Large 'vpmovsxb|w'. + 0x23CF7716, // Large 'vpmovsx|dq'. + 0x257A7716, // Large 'vpmovsx|wd'. + 0x27097716, // Large 'vpmovsx|wq'. + 0x2663771E, // Large 'vpmovus|db'. + 0x26BD771E, // Large 'vpmovus|dw'. + 0x2215771E, // Large 'vpmovus|qb'. + 0x2457771E, // Large 'vpmovus|qd'. + 0x2725771E, // Large 'vpmovus|qw'. + 0x26BE771E, // Large 'vpmovus|wb'. + 0x3872570E, // Large 'vpmov|w2m'. + 0x26BE570E, // Large 'vpmov|wb'. + 0x122B8727, // Large 'vpmovzxb|d'. + 0x12158727, // Large 'vpmovzxb|q'. + 0x12648727, // Large 'vpmovzxb|w'. + 0x23CF7727, // Large 'vpmovzx|dq'. + 0x257A7727, // Large 'vpmovzx|wd'. + 0x27097727, // Large 'vpmovzx|wq'. + 0x23CF52D3, // Large 'vpmul|dq'. + 0x2561772F, // Large 'vpmulhr|sw'. + 0x264C672F, // Large 'vpmulh|uw'. + 0x1264672F, // Large 'vpmulh|w'. + 0x257F52D3, // Large 'vpmul|ld'. + 0x246252D3, // Large 'vpmul|lq'. + 0x258252D3, // Large 'vpmul|lw'. + 0x2215C2D3, // Large 'vpmultishift|qb'. + 0x33CE52D3, // Large 'vpmul|udq'. + 0x21546875, // Large 'vpopcn|tb'. + 0x26266875, // Large 'vpopcn|td'. + 0x236C6875, // Large 'vpopcn|tq'. + 0x27B86875, // Large 'vpopcn|tw'. 0x80093E16, // Small 'vpor'. 0x80493E16, // Small 'vpord'. 0x81193E16, // Small 'vporq'. 0x9B22C216, // Small 'vpperm'. 0x88C7CA16, // Small 'vprold'. 0xA2C7CA16, // Small 'vprolq'. - 0x224757FA, // Large 'vprol|vd'. - 0x200E57FA, // Large 'vprol|vq'. + 0x242159C0, // Large 'vprol|vd'. + 0x221459C0, // Large 'vprol|vq'. 0x8927CA16, // Small 'vprord'. 0xA327CA16, // Small 'vprorq'. - 0x224757FF, // Large 'vpror|vd'. - 0x200E57FF, // Large 'vpror|vq'. + 0x242159C5, // Large 'vpror|vd'. + 0x221459C5, // Large 'vpror|vq'. 0x8547CA16, // Small 'vprotb'. 0x8947CA16, // Small 'vprotd'. 0xA347CA16, // Small 'vprotq'. 0xAF47CA16, // Small 'vprotw'. - 0x239A5804, // Large 'vpsad|bw'. - 0x209A9274, // Large 'vpscatter|dd'. - 0x20E59274, // Large 'vpscatter|dq'. - 0x227D9274, // Large 'vpscatter|qd'. - 0x100FA274, // Large 'vpscatterq|q'. + 0x257859CA, // Large 'vpsad|bw'. + 0x229F944E, // Large 'vpscatter|dd'. + 0x23CF944E, // Large 'vpscatter|dq'. + 0x2457944E, // Large 'vpscatter|qd'. + 0x1215A44E, // Large 'vpscatterq|q'. 0x84144E16, // Small 'vpshab'. 0x88144E16, // Small 'vpshad'. 0xA2144E16, // Small 'vpshaq'. 0xAE144E16, // Small 'vpshaw'. 0x84C44E16, // Small 'vpshlb'. 0x88C44E16, // Small 'vpshld'. - 0x102666B3, // Large 'vpshld|d'. - 0x100F66B3, // Large 'vpshld|q'. - 0x349D56B3, // Large 'vpshl|dvd'. - 0x36B856B3, // Large 'vpshl|dvq'. - 0x105F76B3, // Large 'vpshldv|w'. - 0x105F66B3, // Large 'vpshld|w'. + 0x122B687B, // Large 'vpshld|d'. + 0x1215687B, // Large 'vpshld|q'. + 0x3668587B, // Large 'vpshl|dvd'. + 0x3880587B, // Large 'vpshl|dvq'. + 0x1264787B, // Large 'vpshldv|w'. + 0x1264687B, // Large 'vpshld|w'. 0xA2C44E16, // Small 'vpshlq'. 0xAEC44E16, // Small 'vpshlw'. - 0x102666BB, // Large 'vpshrd|d'. - 0x100F66BB, // Large 'vpshrd|q'. - 0x349D56BB, // Large 'vpshr|dvd'. - 0x36B856BB, // Large 'vpshr|dvq'. - 0x36C056BB, // Large 'vpshr|dvw'. - 0x105F66BB, // Large 'vpshrd|w'. - 0x0000718B, // Large 'vpshufb'. - 0x205CA18B, // Large 'vpshufbitq|mb'. - 0x1026618B, // Large 'vpshuf|d'. - 0x26C3618B, // Large 'vpshuf|hw'. - 0x23A4618B, // Large 'vpshuf|lw'. - 0x22A95809, // Large 'vpsig|nb'. - 0x219D5809, // Large 'vpsig|nd'. - 0x26FB5809, // Large 'vpsig|nw'. + 0x122B6883, // Large 'vpshrd|d'. + 0x12156883, // Large 'vpshrd|q'. + 0x36685883, // Large 'vpshr|dvd'. + 0x38805883, // Large 'vpshr|dvq'. + 0x38885883, // Large 'vpshr|dvw'. + 0x12646883, // Large 'vpshrd|w'. + 0x00007364, // Large 'vpshufb'. + 0x2261A364, // Large 'vpshufbitq|mb'. + 0x122B6364, // Large 'vpshuf|d'. + 0x288B6364, // Large 'vpshuf|hw'. + 0x25826364, // Large 'vpshuf|lw'. + 0x204859CF, // Large 'vpsig|nb'. + 0x237659CF, // Large 'vpsig|nd'. + 0x28C159CF, // Large 'vpsig|nw'. 0x88C64E16, // Small 'vpslld'. - 0x33A1480E, // Large 'vpsl|ldq'. + 0x357F49D4, // Large 'vpsl|ldq'. 0xA2C64E16, // Small 'vpsllq'. - 0x22475812, // Large 'vpsll|vd'. - 0x200E5812, // Large 'vpsll|vq'. - 0x26C15812, // Large 'vpsll|vw'. + 0x242159D8, // Large 'vpsll|vd'. + 0x221459D8, // Large 'vpsll|vq'. + 0x288959D8, // Large 'vpsll|vw'. 0xAEC64E16, // Small 'vpsllw'. 0x88194E16, // Small 'vpsrad'. 0xA2194E16, // Small 'vpsraq'. - 0x22475817, // Large 'vpsra|vd'. - 0x200E5817, // Large 'vpsra|vq'. - 0x26C15817, // Large 'vpsra|vw'. + 0x242159DD, // Large 'vpsra|vd'. + 0x221459DD, // Large 'vpsra|vq'. + 0x288959DD, // Large 'vpsra|vw'. 0xAE194E16, // Small 'vpsraw'. 0x88C94E16, // Small 'vpsrld'. - 0x33A14817, // Large 'vpsr|ldq'. + 0x357F49DD, // Large 'vpsr|ldq'. 0xA2C94E16, // Small 'vpsrlq'. - 0x2247581C, // Large 'vpsrl|vd'. - 0x200E581C, // Large 'vpsrl|vq'. - 0x26C1581C, // Large 'vpsrl|vw'. + 0x242159E2, // Large 'vpsrl|vd'. + 0x221459E2, // Large 'vpsrl|vq'. + 0x288959E2, // Large 'vpsrl|vw'. 0xAEC94E16, // Small 'vpsrlw'. 0x842ACE16, // Small 'vpsubb'. 0x882ACE16, // Small 'vpsubd'. 0xA22ACE16, // Small 'vpsubq'. - 0x25BA56C5, // Large 'vpsub|sb'. - 0x238356C5, // Large 'vpsub|sw'. - 0x25BA66C5, // Large 'vpsubu|sb'. - 0x238366C5, // Large 'vpsubu|sw'. + 0x2786588D, // Large 'vpsub|sb'. + 0x2561588D, // Large 'vpsub|sw'. + 0x2786688D, // Large 'vpsubu|sb'. + 0x2561688D, // Large 'vpsubu|sw'. 0xAE2ACE16, // Small 'vpsubw'. - 0x10269391, // Large 'vpternlog|d'. - 0x100F9391, // Large 'vpternlog|q'. + 0x122B956F, // Large 'vpternlog|d'. + 0x1215956F, // Large 'vpternlog|q'. 0xA932D216, // Small 'vptest'. - 0x205C656A, // Large 'vptest|mb'. - 0x2504656A, // Large 'vptest|md'. - 0x2571656A, // Large 'vptest|mq'. - 0x26A9656A, // Large 'vptest|mw'. - 0x205C756A, // Large 'vptestn|mb'. - 0x2504756A, // Large 'vptestn|md'. - 0x2571756A, // Large 'vptestn|mq'. - 0x105F856A, // Large 'vptestnm|w'. - 0x239A827F, // Large 'vpunpckh|bw'. - 0x20E5827F, // Large 'vpunpckh|dq'. - 0x20E5927F, // Large 'vpunpckhq|dq'. - 0x239C827F, // Large 'vpunpckh|wd'. - 0x339E727F, // Large 'vpunpck|lbw'. - 0x33A1727F, // Large 'vpunpck|ldq'. - 0x4288727F, // Large 'vpunpck|lqdq'. - 0x33A4727F, // Large 'vpunpck|lwd'. + 0x22616736, // Large 'vptest|mb'. + 0x26D06736, // Large 'vptest|md'. + 0x273D6736, // Large 'vptest|mq'. + 0x28716736, // Large 'vptest|mw'. + 0x22617736, // Large 'vptestn|mb'. + 0x26D07736, // Large 'vptestn|md'. + 0x273D7736, // Large 'vptestn|mq'. + 0x12648736, // Large 'vptestnm|w'. + 0x25788459, // Large 'vpunpckh|bw'. + 0x23CF8459, // Large 'vpunpckh|dq'. + 0x23CF9459, // Large 'vpunpckhq|dq'. + 0x257A8459, // Large 'vpunpckh|wd'. + 0x357C7459, // Large 'vpunpck|lbw'. + 0x357F7459, // Large 'vpunpck|ldq'. + 0x44627459, // Large 'vpunpck|lqdq'. + 0x35827459, // Large 'vpunpck|lwd'. 0x8127E216, // Small 'vpxor'. 0x8927E216, // Small 'vpxord'. 0xA327E216, // Small 'vpxorq'. - 0x20A766CB, // Large 'vrange|pd'. - 0x207D66CB, // Large 'vrange|ps'. - 0x214466CB, // Large 'vrange|sd'. - 0x201C66CB, // Large 'vrange|ss'. - 0x20A766D1, // Large 'vrcp14|pd'. - 0x207D66D1, // Large 'vrcp14|ps'. - 0x214466D1, // Large 'vrcp14|sd'. - 0x201C66D1, // Large 'vrcp14|ss'. - 0x43AF46D1, // Large 'vrcp|28pd'. - 0x43B346D1, // Large 'vrcp|28ps'. - 0x43B746D1, // Large 'vrcp|28sd'. - 0x43BB46D1, // Large 'vrcp|28ss'. + 0x22AC6893, // Large 'vrange|pd'. + 0x22826893, // Large 'vrange|ps'. + 0x231D6893, // Large 'vrange|sd'. + 0x22226893, // Large 'vrange|ss'. + 0x22AC6899, // Large 'vrcp14|pd'. + 0x22826899, // Large 'vrcp14|ps'. + 0x231D6899, // Large 'vrcp14|sd'. + 0x22226899, // Large 'vrcp14|ss'. 0x91080E56, // Small 'vrcpph'. 0xA7080E56, // Small 'vrcpps'. 0x91380E56, // Small 'vrcpsh'. 0xA7380E56, // Small 'vrcpss'. - 0x20A77573, // Large 'vreduce|pd'. - 0x20A27573, // Large 'vreduce|ph'. - 0x207D7573, // Large 'vreduce|ps'. - 0x21447573, // Large 'vreduce|sd'. - 0x20D57573, // Large 'vreduce|sh'. - 0x201C7573, // Large 'vreduce|ss'. - 0x20A7928C, // Large 'vrndscale|pd'. - 0x20A2928C, // Large 'vrndscale|ph'. - 0x207D928C, // Large 'vrndscale|ps'. - 0x2144928C, // Large 'vrndscale|sd'. - 0x20D5928C, // Large 'vrndscale|sh'. - 0x201C928C, // Large 'vrndscale|ss'. - 0x30ED56D7, // Large 'vroun|dpd'. - 0x30F156D7, // Large 'vroun|dps'. - 0x36DC56D7, // Large 'vroun|dsd'. - 0x101476D7, // Large 'vrounds|s'. - 0x20A783A7, // Large 'vrsqrt14|pd'. - 0x207D83A7, // Large 'vrsqrt14|ps'. - 0x214483A7, // Large 'vrsqrt14|sd'. - 0x201C83A7, // Large 'vrsqrt14|ss'. - 0x43AF63A7, // Large 'vrsqrt|28pd'. - 0x43B363A7, // Large 'vrsqrt|28ps'. - 0x43B763A7, // Large 'vrsqrt|28sd'. - 0x43BB63A7, // Large 'vrsqrt|28ss'. - 0x20A263A7, // Large 'vrsqrt|ph'. - 0x207D63A7, // Large 'vrsqrt|ps'. - 0x20D563A7, // Large 'vrsqrt|sh'. - 0x201C63A7, // Large 'vrsqrt|ss'. - 0x20A7757A, // Large 'vscalef|pd'. - 0x20A2757A, // Large 'vscalef|ph'. - 0x207D757A, // Large 'vscalef|ps'. - 0x2144757A, // Large 'vscalef|sd'. - 0x20D5757A, // Large 'vscalef|sh'. - 0x201C757A, // Large 'vscalef|ss'. - 0x30ED80DA, // Large 'vscatter|dpd'. - 0x30F180DA, // Large 'vscatter|dps'. - 0x20A7C0DA, // Large 'vscatterpf0d|pd'. - 0x207DC0DA, // Large 'vscatterpf0d|ps'. - 0x30E6B0DA, // Large 'vscatterpf0|qpd'. - 0x30E9B0DA, // Large 'vscatterpf0|qps'. - 0x40ECA0DA, // Large 'vscatterpf|1dpd'. - 0x40F0A0DA, // Large 'vscatterpf|1dps'. - 0x40F4A0DA, // Large 'vscatterpf|1qpd'. - 0x40F8A0DA, // Large 'vscatterpf|1qps'. - 0x30E680DA, // Large 'vscatter|qpd'. - 0x30E980DA, // Large 'vscatter|qps'. - 0x42957195, // Large 'vsha512|msg1'. - 0x42997195, // Large 'vsha512|msg2'. - 0x207EA195, // Large 'vsha512rnd|s2'. - 0x502B53BF, // Large 'vshuf|f32x4'. - 0x403063C4, // Large 'vshuff|64x2'. - 0x503D53BF, // Large 'vshuf|i32x4'. - 0x504753BF, // Large 'vshuf|i64x2'. - 0x20A753BF, // Large 'vshuf|pd'. - 0x207D53BF, // Large 'vshuf|ps'. - 0x42954581, // Large 'vsm3|msg1'. - 0x42994581, // Large 'vsm3|msg2'. - 0x207E7581, // Large 'vsm3rnd|s2'. - 0x102F76DF, // Large 'vsm4key|4'. - 0x102F8588, // Large 'vsm4rnds|4'. - 0x31F14821, // Large 'vsqr|tpd'. - 0x31FC4821, // Large 'vsqr|tph'. - 0x32054821, // Large 'vsqr|tps'. - 0x320E4821, // Large 'vsqr|tsd'. - 0x32174821, // Large 'vsqr|tsh'. - 0x32204821, // Large 'vsqr|tss'. - 0x102376E6, // Large 'vstmxcs|r'. + 0x22AC773F, // Large 'vreduce|pd'. + 0x22A7773F, // Large 'vreduce|ph'. + 0x2282773F, // Large 'vreduce|ps'. + 0x231D773F, // Large 'vreduce|sd'. + 0x22DA773F, // Large 'vreduce|sh'. + 0x2222773F, // Large 'vreduce|ss'. + 0x22AC9466, // Large 'vrndscale|pd'. + 0x22A79466, // Large 'vrndscale|ph'. + 0x22829466, // Large 'vrndscale|ps'. + 0x231D9466, // Large 'vrndscale|sd'. + 0x22DA9466, // Large 'vrndscale|sh'. + 0x22229466, // Large 'vrndscale|ss'. + 0x22AC689F, // Large 'vround|pd'. + 0x2282689F, // Large 'vround|ps'. + 0x231D689F, // Large 'vround|sd'. + 0x2222689F, // Large 'vround|ss'. + 0x22AC8585, // Large 'vrsqrt14|pd'. + 0x22828585, // Large 'vrsqrt14|ps'. + 0x231D8585, // Large 'vrsqrt14|sd'. + 0x22228585, // Large 'vrsqrt14|ss'. + 0x22A76585, // Large 'vrsqrt|ph'. + 0x22826585, // Large 'vrsqrt|ps'. + 0x22DA6585, // Large 'vrsqrt|sh'. + 0x22226585, // Large 'vrsqrt|ss'. + 0x22AC7746, // Large 'vscalef|pd'. + 0x22A77746, // Large 'vscalef|ph'. + 0x22827746, // Large 'vscalef|ps'. + 0x231D7746, // Large 'vscalef|sd'. + 0x22DA7746, // Large 'vscalef|sh'. + 0x22227746, // Large 'vscalef|ss'. + 0x22AC946F, // Large 'vscatterd|pd'. + 0x2282946F, // Large 'vscatterd|ps'. + 0x3478846F, // Large 'vscatter|qpd'. + 0x347B846F, // Large 'vscatter|qps'. + 0x447E736E, // Large 'vsha512|msg1'. + 0x4482736E, // Large 'vsha512|msg2'. + 0x2283A36E, // Large 'vsha512rnd|s2'. + 0x5230558D, // Large 'vshuf|f32x4'. + 0x42356592, // Large 'vshuff|64x2'. + 0x5242558D, // Large 'vshuf|i32x4'. + 0x524C558D, // Large 'vshuf|i64x2'. + 0x22AC558D, // Large 'vshuf|pd'. + 0x2282558D, // Large 'vshuf|ps'. + 0x447E474D, // Large 'vsm3|msg1'. + 0x4482474D, // Large 'vsm3|msg2'. + 0x2283774D, // Large 'vsm3rnd|s2'. + 0x123478A5, // Large 'vsm4key|4'. + 0x12348754, // Large 'vsm4rnds|4'. + 0x33CA49E7, // Large 'vsqr|tpd'. + 0x33D649E7, // Large 'vsqr|tph'. + 0x33E149E7, // Large 'vsqr|tps'. + 0x33E849E7, // Large 'vsqr|tsd'. + 0x33F149E7, // Large 'vsqr|tsh'. + 0x33FA49E7, // Large 'vsqr|tss'. + 0x122878AC, // Large 'vstmxcs|r'. 0x89015676, // Small 'vsubpd'. 0x91015676, // Small 'vsubph'. 0xA7015676, // Small 'vsubps'. 0x89315676, // Small 'vsubsd'. 0x91315676, // Small 'vsubsh'. 0xA7315676, // Small 'vsubss'. - 0x31F14825, // Large 'vtes|tpd'. - 0x32054825, // Large 'vtes|tps'. - 0x214466ED, // Large 'vucomi|sd'. - 0x20D566ED, // Large 'vucomi|sh'. - 0x201C66ED, // Large 'vucomi|ss'. - 0x20A77590, // Large 'vunpckh|pd'. - 0x207D7590, // Large 'vunpckh|ps'. - 0x35976590, // Large 'vunpck|lpd'. - 0x359A6590, // Large 'vunpck|lps'. + 0x33CA49EB, // Large 'vtes|tpd'. + 0x33E149EB, // Large 'vtes|tps'. + 0x231D68B3, // Large 'vucomi|sd'. + 0x22DA68B3, // Large 'vucomi|sh'. + 0x222268B3, // Large 'vucomi|ss'. + 0x22AC775C, // Large 'vunpckh|pd'. + 0x2282775C, // Large 'vunpckh|ps'. + 0x3763675C, // Large 'vunpck|lpd'. + 0x3766675C, // Large 'vunpck|lps'. 0x89093F16, // Small 'vxorpd'. 0xA7093F16, // Small 'vxorps'. - 0x36F353CA, // Large 'vzero|all'. - 0x335D73CA, // Large 'vzeroup|per'. + 0x38B95598, // Large 'vzero|all'. + 0x353B7598, // Large 'vzeroup|per'. 0x89672457, // Small 'wbinvd'. - 0x224766F6, // Large 'wbnoin|vd'. - 0x343656FC, // Large 'wrfsb|ase'. - 0x34365701, // Large 'wrgsb|ase'. + 0x242168BC, // Large 'wbnoin|vd'. + 0x317058C2, // Large 'wrfsb|ase'. + 0x317058C7, // Large 'wrgsb|ase'. 0x8129B657, // Small 'wrmsr'. 0x8049CE57, // Small 'wrssd'. 0x8119CE57, // Small 'wrssq'. @@ -4690,23 +4575,121 @@ const uint32_t InstDB::_instNameIndexTable[] = { 0x800049F8, // Small 'xor'. 0x804849F8, // Small 'xorpd'. 0x813849F8, // Small 'xorps'. - 0x1015859D, // Large 'xresldtr|k'. + 0x121B8769, // Large 'xresldtr|k'. 0xA4FA4E58, // Small 'xrstor'. - 0x2030640C, // Large 'xrstor|64'. - 0x1014640C, // Large 'xrstor|s'. - 0x35A5640C, // Large 'xrstor|s64'. + 0x223565DD, // Large 'xrstor|64'. + 0x115265DD, // Large 'xrstor|s'. + 0x377165DD, // Large 'xrstor|s64'. 0x805B0678, // Small 'xsave'. - 0x203053D1, // Large 'xsave|64'. + 0x2235559F, // Large 'xsave|64'. 0x865B0678, // Small 'xsavec'. - 0x370653D1, // Large 'xsave|c64'. - 0x000083D1, // Large 'xsaveopt'. - 0x203083D1, // Large 'xsaveopt|64'. + 0x38CC559F, // Large 'xsave|c64'. + 0x0000859F, // Large 'xsaveopt'. + 0x2235859F, // Large 'xsaveopt|64'. 0xA65B0678, // Small 'xsaves'. - 0x35A553D1, // Large 'xsave|s64'. + 0x3771559F, // Large 'xsave|s64'. 0xAC2A1678, // Small 'xsetbv'. - 0x101585A8, // Large 'xsusldtr|k'. + 0x121B8774, // Large 'xsusldtr|k'. 0x81499698 // Small 'xtest'. }; + +const char InstDB::_aliasNameStringTable[] = + "\x63\x6D\x6F\x76\x6E\x61\x65\x67\x65"; + + +const uint32_t InstDB::_aliasNameIndexTable[] = { + 0x801B3DA3, // Small 'cmova'. + 0x8A1B3DA3, // Small 'cmovae'. + 0x803B3DA3, // Small 'cmovc'. + 0x805B3DA3, // Small 'cmove'. + 0x807B3DA3, // Small 'cmovg'. + 0x8A7B3DA3, // Small 'cmovge'. + 0x82EB3DA3, // Small 'cmovna'. + 0x00007000, // Large 'cmovnae'. + 0x86EB3DA3, // Small 'cmovnc'. + 0x8AEB3DA3, // Small 'cmovne'. + 0x8EEB3DA3, // Small 'cmovng'. + 0x20075000, // Large 'cmovn|ge'. + 0x8B0B3DA3, // Small 'cmovpe'. + 0x9F0B3DA3, // Small 'cmovpo'. + 0x8000002A, // Small 'ja'. + 0x8000142A, // Small 'jae'. + 0x8000006A, // Small 'jc'. + 0x800000AA, // Small 'je'. + 0x800000EA, // Small 'jg'. + 0x800014EA, // Small 'jge'. + 0x800005CA, // Small 'jna'. + 0x800285CA, // Small 'jnae'. + 0x80000DCA, // Small 'jnc'. + 0x800015CA, // Small 'jne'. + 0x80001DCA, // Small 'jng'. + 0x80029DCA, // Small 'jnge'. + 0x8000160A, // Small 'jpe'. + 0x80003E0A, // Small 'jpo'. + 0x80003033, // Small 'sal'. + 0x8000D0B3, // Small 'seta'. + 0x8050D0B3, // Small 'setae'. + 0x8001D0B3, // Small 'setc'. + 0x8002D0B3, // Small 'sete'. + 0x8003D0B3, // Small 'setg'. + 0x8053D0B3, // Small 'setge'. + 0x801750B3, // Small 'setna'. + 0x8A1750B3, // Small 'setnae'. + 0x803750B3, // Small 'setnc'. + 0x805750B3, // Small 'setne'. + 0x807750B3, // Small 'setng'. + 0x8A7750B3, // Small 'setnge'. + 0x805850B3, // Small 'setpe'. + 0x80F850B3, // Small 'setpo'. + 0x800A2437 // Small 'wait'. +}; + +const uint32_t InstDB::_aliasIndexToInstId[] = { + Inst::kIdCmovnbe, // #0 + Inst::kIdCmovnb, // #1 + Inst::kIdCmovb, // #2 + Inst::kIdCmovz, // #3 + Inst::kIdCmovnle, // #4 + Inst::kIdCmovnl, // #5 + Inst::kIdCmovbe, // #6 + Inst::kIdCmovb, // #7 + Inst::kIdCmovnb, // #8 + Inst::kIdCmovnz, // #9 + Inst::kIdCmovle, // #10 + Inst::kIdCmovl, // #11 + Inst::kIdCmovp, // #12 + Inst::kIdCmovnp, // #13 + Inst::kIdJnbe, // #14 + Inst::kIdJnb, // #15 + Inst::kIdJb, // #16 + Inst::kIdJz, // #17 + Inst::kIdJnle, // #18 + Inst::kIdJnl, // #19 + Inst::kIdJbe, // #20 + Inst::kIdJb, // #21 + Inst::kIdJnb, // #22 + Inst::kIdJnz, // #23 + Inst::kIdJle, // #24 + Inst::kIdJl, // #25 + Inst::kIdJp, // #26 + Inst::kIdJnp, // #27 + Inst::kIdShl, // #28 + Inst::kIdSetnbe, // #29 + Inst::kIdSetnb, // #30 + Inst::kIdSetb, // #31 + Inst::kIdSetz, // #32 + Inst::kIdSetnle, // #33 + Inst::kIdSetnl, // #34 + Inst::kIdSetbe, // #35 + Inst::kIdSetb, // #36 + Inst::kIdSetnb, // #37 + Inst::kIdSetnz, // #38 + Inst::kIdSetle, // #39 + Inst::kIdSetl, // #40 + Inst::kIdSetp, // #41 + Inst::kIdSetnp, // #42 + Inst::kIdFwait // #43 +}; // ---------------------------------------------------------------------------- // ${NameData:End} #endif // !ASMJIT_NO_TEXT @@ -4733,10 +4716,10 @@ const InstDB::InstSignature InstDB::_instSignatureTable[] = { ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16} ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32} ROW(2, 0, 1, 0, 15 , 16 , 0 , 0 , 0 , 0 ), // {r64|m64, i32} - ROW(2, 0, 1, 0, 8 , 17 , 0 , 0 , 0 , 0 ), // {r64, i64|u64|m64|mem|sreg|creg|dreg} - ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} - ROW(2, 1, 1, 0, 4 , 19 , 0 , 0 , 0 , 0 ), // {r16, m16|mem|sreg} - ROW(2, 1, 1, 0, 6 , 20 , 0 , 0 , 0 , 0 ), // {r32, m32|mem|sreg} + ROW(2, 1, 1, 0, 2 , 17 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} + ROW(2, 1, 1, 0, 4 , 18 , 0 , 0 , 0 , 0 ), // {r16, m16|mem|sreg} + ROW(2, 1, 1, 0, 6 , 19 , 0 , 0 , 0 , 0 ), // {r32, m32|mem|sreg} + ROW(2, 0, 1, 0, 8 , 20 , 0 , 0 , 0 , 0 ), // {r64, m64|mem|i64|u64|sreg|creg|dreg} ROW(2, 1, 1, 0, 21 , 22 , 0 , 0 , 0 , 0 ), // {m16|mem, sreg} ROW(2, 1, 1, 0, 21 , 22 , 0 , 0 , 0 , 0 ), // {m16|mem, sreg} ROW(2, 0, 1, 0, 21 , 22 , 0 , 0 , 0 , 0 ), // {m16|mem, sreg} @@ -4745,561 +4728,589 @@ const InstDB::InstSignature InstDB::_instSignatureTable[] = { ROW(2, 0, 1, 0, 22 , 21 , 0 , 0 , 0 , 0 ), // {sreg, m16|mem} ROW(2, 1, 0, 0, 6 , 23 , 0 , 0 , 0 , 0 ), // {r32, creg|dreg} ROW(2, 1, 0, 0, 23 , 6 , 0 , 0 , 0 , 0 ), // {creg|dreg, r32} - ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // #20 {r8lo|r8hi|m8, i8|u8} + ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // #20 {r8lo|r8hi|m8|mem, r8lo|r8hi} + ROW(2, 1, 1, 0, 24 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 25 , 6 , 0 , 0 , 0 , 0 ), // #22 {r32|m32|mem, r32} + ROW(2, 0, 1, 0, 26 , 8 , 0 , 0 , 0 , 0 ), // #23 {r64|m64|mem, r64} + ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8, i8|u8} + ROW(2, 1, 1, 0, 27 , 28 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32, i8} + ROW(2, 0, 1, 0, 15 , 29 , 0 , 0 , 0 , 0 ), // {r64|m64, i8|i32} ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16} ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32} - ROW(2, 0, 1, 0, 15 , 24 , 0 , 0 , 0 , 0 ), // {r64|m64, i32|i8} - ROW(2, 1, 1, 0, 25 , 26 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32, i8} - ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // #25 {r8lo|r8hi|m8|mem, r8lo|r8hi} - ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // #27 {r32|m32|mem, r32} - ROW(2, 0, 1, 0, 29 , 8 , 0 , 0 , 0 , 0 ), // #28 {r64|m64|mem, r64} - ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} + ROW(2, 1, 1, 0, 2 , 17 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} ROW(2, 1, 1, 0, 6 , 30 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} ROW(2, 0, 1, 0, 8 , 31 , 0 , 0 , 0 , 0 ), // {r64, m64|mem} - ROW(2, 1, 1, 0, 32 , 10 , 0 , 0 , 0 , 0 ), // #33 {r8lo|r8hi|m8|r16|m16|r32|m32, i8|u8} + ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // #33 {r8lo|r8hi|m8, i8|u8} ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16} ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32} - ROW(2, 0, 1, 0, 8 , 33 , 0 , 0 , 0 , 0 ), // {r64, u32|i32|i8|u8|r64|m64|mem} - ROW(2, 0, 1, 0, 34 , 35 , 0 , 0 , 0 , 0 ), // {m64, i32|i8|u8} + ROW(2, 0, 1, 0, 8 , 32 , 0 , 0 , 0 , 0 ), // {r64, u32|i32|i8|r64|m64|mem} + ROW(2, 0, 1, 0, 33 , 29 , 0 , 0 , 0 , 0 ), // {m64, i32|i8} + ROW(2, 1, 1, 0, 27 , 28 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32, i8} ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8|mem, r8lo|r8hi} - ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 1, 1, 0, 24 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 25 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} ROW(2, 0, 1, 0, 31 , 8 , 0 , 0 , 0 , 0 ), // {m64|mem, r64} - ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} + ROW(2, 1, 1, 0, 2 , 17 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} ROW(2, 1, 1, 0, 6 , 30 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} - ROW(2, 1, 1, 1, 36 , 1 , 0 , 0 , 0 , 0 ), // #45 {, r8lo|r8hi|m8|mem} - ROW(3, 1, 1, 2, 37 , 36 , 27 , 0 , 0 , 0 ), // {, , r16|m16|mem} - ROW(3, 1, 1, 2, 38 , 39 , 28 , 0 , 0 , 0 ), // {, , r32|m32|mem} - ROW(3, 0, 1, 2, 40 , 41 , 29 , 0 , 0 , 0 ), // {, , r64|m64|mem} - ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #49 {r16, r16|m16|mem} - ROW(2, 1, 1, 0, 6 , 28 , 0 , 0 , 0 , 0 ), // #50 {r32, r32|m32|mem} - ROW(2, 0, 1, 0, 8 , 29 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem} - ROW(3, 1, 1, 0, 4 , 27 , 42 , 0 , 0 , 0 ), // {r16, r16|m16|mem, i8|i16|u16} - ROW(3, 1, 1, 0, 6 , 28 , 43 , 0 , 0 , 0 ), // {r32, r32|m32|mem, i8|i32|u32} - ROW(3, 0, 1, 0, 8 , 29 , 24 , 0 , 0 , 0 ), // {r64, r64|m64|mem, i8|i32} - ROW(2, 0, 1, 0, 8 , 44 , 0 , 0 , 0 , 0 ), // #55 {r64, i64|u64} - ROW(2, 1, 1, 0, 45 , 18 , 0 , 0 , 0 , 0 ), // {al, m8|mem} - ROW(2, 1, 1, 0, 46 , 21 , 0 , 0 , 0 , 0 ), // {ax, m16|mem} - ROW(2, 1, 1, 0, 47 , 30 , 0 , 0 , 0 , 0 ), // {eax, m32|mem} - ROW(2, 0, 1, 0, 48 , 31 , 0 , 0 , 0 , 0 ), // {rax, m64|mem} - ROW(2, 1, 1, 0, 18 , 45 , 0 , 0 , 0 , 0 ), // {m8|mem, al} - ROW(2, 1, 1, 0, 21 , 46 , 0 , 0 , 0 , 0 ), // {m16|mem, ax} - ROW(2, 1, 1, 0, 30 , 47 , 0 , 0 , 0 , 0 ), // {m32|mem, eax} - ROW(2, 0, 1, 0, 31 , 48 , 0 , 0 , 0 , 0 ), // {m64|mem, rax} - ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // #64 {r8lo|r8hi|m8, i8|u8} + ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // #46 {r8lo|r8hi|m8|mem, r8lo|r8hi} + ROW(2, 1, 1, 0, 24 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 25 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 0, 1, 0, 26 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} + ROW(2, 1, 1, 0, 2 , 34 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem|i8|u8} + ROW(2, 1, 1, 0, 4 , 35 , 0 , 0 , 0 , 0 ), // {r16, m16|mem|i8|i16|u16} + ROW(2, 1, 1, 0, 6 , 36 , 0 , 0 , 0 , 0 ), // {r32, m32|mem|i8|i32|u32} + ROW(2, 0, 1, 0, 8 , 37 , 0 , 0 , 0 , 0 ), // {r64, m64|mem|i8|i32} + ROW(2, 1, 1, 0, 38 , 10 , 0 , 0 , 0 , 0 ), // {m8, i8|u8} + ROW(2, 1, 1, 0, 39 , 28 , 0 , 0 , 0 , 0 ), // {m16|m32, i8} + ROW(2, 0, 1, 0, 33 , 29 , 0 , 0 , 0 , 0 ), // {m64, i8|i32} + ROW(2, 1, 1, 0, 40 , 12 , 0 , 0 , 0 , 0 ), // {m16, i16|u16} + ROW(2, 1, 1, 0, 41 , 14 , 0 , 0 , 0 , 0 ), // {m32, i32|u32} + ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // #59 {r8lo|r8hi|m8|mem, r8lo|r8hi} + ROW(2, 1, 1, 0, 24 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 25 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 0, 1, 0, 26 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} + ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8, i8|u8} + ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16} + ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32} + ROW(2, 0, 1, 0, 15 , 29 , 0 , 0 , 0 , 0 ), // {r64|m64, i32|i8} + ROW(2, 1, 1, 0, 27 , 28 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32, i8} + ROW(2, 1, 1, 0, 2 , 17 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} + ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} + ROW(2, 1, 1, 0, 6 , 30 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} + ROW(2, 0, 1, 0, 8 , 31 , 0 , 0 , 0 , 0 ), // {r64, m64|mem} + ROW(2, 1, 1, 1, 42 , 1 , 0 , 0 , 0 , 0 ), // #72 {, r8lo|r8hi|m8|mem} + ROW(3, 1, 1, 2, 43 , 42 , 24 , 0 , 0 , 0 ), // {, , r16|m16|mem} + ROW(3, 1, 1, 2, 44 , 45 , 25 , 0 , 0 , 0 ), // {, , r32|m32|mem} + ROW(3, 0, 1, 2, 46 , 47 , 26 , 0 , 0 , 0 ), // {, , r64|m64|mem} + ROW(2, 1, 1, 0, 4 , 24 , 0 , 0 , 0 , 0 ), // #76 {r16, r16|m16|mem} + ROW(2, 1, 1, 0, 6 , 25 , 0 , 0 , 0 , 0 ), // #77 {r32, r32|m32|mem} + ROW(2, 0, 1, 0, 8 , 26 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem} + ROW(3, 1, 1, 0, 4 , 24 , 48 , 0 , 0 , 0 ), // {r16, r16|m16|mem, i8|i16|u16} + ROW(3, 1, 1, 0, 6 , 25 , 49 , 0 , 0 , 0 ), // {r32, r32|m32|mem, i8|i32|u32} + ROW(3, 0, 1, 0, 8 , 26 , 29 , 0 , 0 , 0 ), // {r64, r64|m64|mem, i8|i32} + ROW(2, 0, 1, 0, 8 , 50 , 0 , 0 , 0 , 0 ), // #82 {r64, i64|u64} + ROW(2, 1, 1, 0, 51 , 17 , 0 , 0 , 0 , 0 ), // {al, m8|mem} + ROW(2, 1, 1, 0, 52 , 21 , 0 , 0 , 0 , 0 ), // {ax, m16|mem} + ROW(2, 1, 1, 0, 53 , 30 , 0 , 0 , 0 , 0 ), // {eax, m32|mem} + ROW(2, 0, 1, 0, 54 , 31 , 0 , 0 , 0 , 0 ), // {rax, m64|mem} + ROW(2, 1, 1, 0, 17 , 51 , 0 , 0 , 0 , 0 ), // {m8|mem, al} + ROW(2, 1, 1, 0, 21 , 52 , 0 , 0 , 0 , 0 ), // {m16|mem, ax} + ROW(2, 1, 1, 0, 30 , 53 , 0 , 0 , 0 , 0 ), // {m32|mem, eax} + ROW(2, 0, 1, 0, 31 , 54 , 0 , 0 , 0 , 0 ), // {m64|mem, rax} + ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // #91 {r8lo|r8hi|m8|mem, r8lo|r8hi} + ROW(2, 1, 1, 0, 24 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 25 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 0, 1, 0, 26 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} + ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8, i8|u8} ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16} ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32} ROW(2, 0, 1, 0, 15 , 16 , 0 , 0 , 0 , 0 ), // {r64|m64, i32} - ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8|mem, r8lo|r8hi} - ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} - ROW(2, 0, 1, 0, 29 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} - ROW(2, 1, 1, 0, 49 , 50 , 0 , 0 , 0 , 0 ), // #72 {xmm, xmm|m128|mem} - ROW(2, 1, 1, 0, 51 , 49 , 0 , 0 , 0 , 0 ), // #73 {m128|mem, xmm} - ROW(2, 1, 1, 0, 52 , 53 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} - ROW(2, 1, 1, 0, 54 , 52 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} - ROW(2, 1, 1, 0, 51 , 49 , 0 , 0 , 0 , 0 ), // {m128|mem, xmm} - ROW(2, 1, 1, 0, 54 , 52 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} - ROW(2, 1, 1, 0, 55 , 56 , 0 , 0 , 0 , 0 ), // #78 {zmm, zmm|m512|mem} - ROW(2, 1, 1, 0, 57 , 55 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm} - ROW(2, 1, 1, 0, 31 , 49 , 0 , 0 , 0 , 0 ), // #80 {m64|mem, xmm} - ROW(2, 1, 1, 0, 49 , 31 , 0 , 0 , 0 , 0 ), // {xmm, m64|mem} - ROW(3, 1, 1, 0, 49 , 49 , 49 , 0 , 0 , 0 ), // #82 {xmm, xmm, xmm} - ROW(3, 1, 1, 0, 49 , 49 , 49 , 0 , 0 , 0 ), // {xmm, xmm, xmm} - ROW(2, 1, 1, 0, 31 , 49 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} - ROW(2, 1, 1, 0, 49 , 31 , 0 , 0 , 0 , 0 ), // {xmm, m64|mem} - ROW(3, 1, 1, 0, 49 , 49 , 49 , 0 , 0 , 0 ), // {xmm, xmm, xmm} - ROW(3, 1, 1, 0, 49 , 49 , 49 , 0 , 0 , 0 ), // {xmm, xmm, xmm} - ROW(2, 1, 1, 0, 30 , 49 , 0 , 0 , 0 , 0 ), // #88 {m32|mem, xmm} - ROW(2, 1, 1, 0, 49 , 30 , 0 , 0 , 0 , 0 ), // {xmm, m32|mem} - ROW(3, 1, 1, 0, 49 , 49 , 49 , 0 , 0 , 0 ), // {xmm, xmm, xmm} - ROW(3, 1, 1, 0, 49 , 49 , 49 , 0 , 0 , 0 ), // {xmm, xmm, xmm} - ROW(2, 1, 1, 0, 30 , 49 , 0 , 0 , 0 , 0 ), // {m32|mem, xmm} - ROW(2, 1, 1, 0, 49 , 30 , 0 , 0 , 0 , 0 ), // {xmm, m32|mem} - ROW(3, 1, 1, 0, 49 , 49 , 49 , 0 , 0 , 0 ), // {xmm, xmm, xmm} - ROW(3, 1, 1, 0, 49 , 49 , 49 , 0 , 0 , 0 ), // {xmm, xmm, xmm} - ROW(3, 1, 1, 0, 49 , 49 , 58 , 0 , 0 , 0 ), // #96 {xmm, xmm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 49 , 51 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} - ROW(3, 1, 1, 0, 52 , 52 , 59 , 0 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem|i8|u8} - ROW(3, 1, 1, 0, 52 , 54 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} - ROW(3, 1, 1, 0, 55 , 55 , 60 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem|i8|u8} - ROW(3, 1, 1, 0, 49 , 51 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} - ROW(3, 1, 1, 0, 52 , 54 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} - ROW(3, 1, 1, 0, 55 , 57 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} - ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // #104 {r16, m16|mem} + ROW(2, 1, 1, 0, 55 , 56 , 0 , 0 , 0 , 0 ), // #99 {xmm, xmm|m128|mem} + ROW(2, 1, 1, 0, 57 , 58 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} + ROW(2, 1, 1, 0, 59 , 55 , 0 , 0 , 0 , 0 ), // #101 {m128|mem, xmm} + ROW(2, 1, 1, 0, 60 , 57 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} + ROW(2, 1, 1, 0, 61 , 62 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem} + ROW(2, 1, 1, 0, 59 , 55 , 0 , 0 , 0 , 0 ), // {m128|mem, xmm} + ROW(2, 1, 1, 0, 60 , 57 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} + ROW(2, 1, 1, 0, 63 , 61 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm} + ROW(2, 1, 1, 0, 31 , 55 , 0 , 0 , 0 , 0 ), // #107 {m64|mem, xmm} + ROW(2, 1, 1, 0, 55 , 31 , 0 , 0 , 0 , 0 ), // {xmm, m64|mem} + ROW(3, 1, 1, 0, 55 , 55 , 55 , 0 , 0 , 0 ), // #109 {xmm, xmm, xmm} + ROW(3, 1, 1, 0, 55 , 55 , 55 , 0 , 0 , 0 ), // {xmm, xmm, xmm} + ROW(2, 1, 1, 0, 31 , 55 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} + ROW(2, 1, 1, 0, 55 , 31 , 0 , 0 , 0 , 0 ), // {xmm, m64|mem} + ROW(3, 1, 1, 0, 55 , 55 , 55 , 0 , 0 , 0 ), // {xmm, xmm, xmm} + ROW(3, 1, 1, 0, 55 , 55 , 55 , 0 , 0 , 0 ), // {xmm, xmm, xmm} + ROW(2, 1, 1, 0, 30 , 55 , 0 , 0 , 0 , 0 ), // #115 {m32|mem, xmm} + ROW(2, 1, 1, 0, 55 , 30 , 0 , 0 , 0 , 0 ), // {xmm, m32|mem} + ROW(3, 1, 1, 0, 55 , 55 , 55 , 0 , 0 , 0 ), // {xmm, xmm, xmm} + ROW(3, 1, 1, 0, 55 , 55 , 55 , 0 , 0 , 0 ), // {xmm, xmm, xmm} + ROW(2, 1, 1, 0, 30 , 55 , 0 , 0 , 0 , 0 ), // {m32|mem, xmm} + ROW(2, 1, 1, 0, 55 , 30 , 0 , 0 , 0 , 0 ), // {xmm, m32|mem} + ROW(3, 1, 1, 0, 55 , 55 , 55 , 0 , 0 , 0 ), // {xmm, xmm, xmm} + ROW(3, 1, 1, 0, 55 , 55 , 55 , 0 , 0 , 0 ), // {xmm, xmm, xmm} + ROW(3, 1, 1, 0, 55 , 55 , 64 , 0 , 0 , 0 ), // #123 {xmm, xmm, xmm|m128|mem|i8|u8} + ROW(3, 1, 1, 0, 55 , 59 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} + ROW(3, 1, 1, 0, 57 , 57 , 65 , 0 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem|i8|u8} + ROW(3, 1, 1, 0, 57 , 60 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} + ROW(3, 1, 1, 0, 61 , 61 , 66 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem|i8|u8} + ROW(3, 1, 1, 0, 55 , 59 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} + ROW(3, 1, 1, 0, 57 , 60 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} + ROW(3, 1, 1, 0, 61 , 63 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} + ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // #131 {r8lo|r8hi|m8|mem, r8lo|r8hi} + ROW(2, 1, 1, 0, 24 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 25 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 0, 1, 0, 26 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} + ROW(2, 1, 1, 0, 2 , 17 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} + ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} + ROW(2, 1, 1, 0, 6 , 30 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} + ROW(2, 0, 1, 0, 8 , 31 , 0 , 0 , 0 , 0 ), // {r64, m64|mem} + ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // #139 {r16, m16|mem} ROW(2, 1, 1, 0, 6 , 30 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} ROW(2, 0, 1, 0, 8 , 31 , 0 , 0 , 0 , 0 ), // {r64, m64|mem} ROW(2, 1, 1, 0, 21 , 4 , 0 , 0 , 0 , 0 ), // {m16|mem, r16} - ROW(2, 1, 1, 0, 30 , 6 , 0 , 0 , 0 , 0 ), // #108 {m32|mem, r32} + ROW(2, 1, 1, 0, 30 , 6 , 0 , 0 , 0 , 0 ), // #143 {m32|mem, r32} ROW(2, 0, 1, 0, 31 , 8 , 0 , 0 , 0 , 0 ), // {m64|mem, r64} - ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #110 {} - ROW(1, 1, 1, 0, 25 , 0 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32} + ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #145 {} + ROW(1, 1, 1, 0, 27 , 0 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32} ROW(1, 0, 1, 0, 15 , 0 , 0 , 0 , 0 , 0 ), // {r64|m64} - ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} - ROW(2, 0, 1, 0, 29 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} - ROW(2, 1, 1, 0, 49 , 50 , 0 , 0 , 0 , 0 ), // #116 {xmm, xmm|m128|mem} - ROW(2, 1, 1, 0, 51 , 49 , 0 , 0 , 0 , 0 ), // {m128|mem, xmm} - ROW(2, 1, 1, 0, 52 , 53 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} - ROW(2, 1, 1, 0, 54 , 52 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} - ROW(2, 1, 1, 0, 55 , 56 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem} - ROW(2, 1, 1, 0, 57 , 55 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm} - ROW(3, 1, 1, 0, 49 , 49 , 58 , 0 , 0 , 0 ), // #122 {xmm, xmm, i8|u8|xmm|m128|mem} - ROW(3, 1, 1, 0, 52 , 52 , 58 , 0 , 0 , 0 ), // {ymm, ymm, i8|u8|xmm|m128|mem} - ROW(3, 1, 1, 0, 49 , 51 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} - ROW(3, 1, 1, 0, 52 , 54 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} - ROW(3, 1, 1, 0, 55 , 55 , 58 , 0 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 55 , 57 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} - ROW(3, 1, 1, 0, 49 , 49 , 58 , 0 , 0 , 0 ), // #128 {xmm, xmm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 49 , 51 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} - ROW(3, 1, 1, 0, 52 , 52 , 58 , 0 , 0 , 0 ), // {ymm, ymm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 52 , 54 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} - ROW(3, 1, 1, 0, 55 , 55 , 58 , 0 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 55 , 57 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} - ROW(2, 1, 1, 0, 25 , 10 , 0 , 0 , 0 , 0 ), // #134 {r16|m16|r32|m32, i8|u8} + ROW(2, 1, 1, 0, 24 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 25 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 0, 1, 0, 26 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} + ROW(2, 1, 1, 0, 55 , 56 , 0 , 0 , 0 , 0 ), // #151 {xmm, xmm|m128|mem} + ROW(2, 1, 1, 0, 57 , 58 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} + ROW(2, 1, 1, 0, 61 , 62 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem} + ROW(2, 1, 1, 0, 59 , 55 , 0 , 0 , 0 , 0 ), // {m128|mem, xmm} + ROW(2, 1, 1, 0, 60 , 57 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} + ROW(2, 1, 1, 0, 63 , 61 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm} + ROW(3, 1, 1, 0, 55 , 55 , 64 , 0 , 0 , 0 ), // #157 {xmm, xmm, xmm|m128|mem|i8|u8} + ROW(3, 1, 1, 0, 57 , 57 , 64 , 0 , 0 , 0 ), // {ymm, ymm, xmm|m128|mem|i8|u8} + ROW(3, 1, 1, 0, 61 , 61 , 64 , 0 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem|i8|u8} + ROW(3, 1, 1, 0, 55 , 59 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} + ROW(3, 1, 1, 0, 57 , 60 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} + ROW(3, 1, 1, 0, 61 , 63 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} + ROW(2, 1, 1, 0, 24 , 4 , 0 , 0 , 0 , 0 ), // #163 {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 25 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 0, 1, 0, 26 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} + ROW(2, 1, 1, 0, 27 , 10 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32, i8|u8} ROW(2, 0, 1, 0, 15 , 10 , 0 , 0 , 0 , 0 ), // {r64|m64, i8|u8} - ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} - ROW(2, 0, 1, 0, 29 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} - ROW(2, 1, 1, 0, 61 , 62 , 0 , 0 , 0 , 0 ), // #139 {mm, mm|m64|mem} - ROW(2, 0, 1, 0, 63 , 29 , 0 , 0 , 0 , 0 ), // {mm|xmm, r64|m64|mem} - ROW(2, 1, 1, 0, 31 , 63 , 0 , 0 , 0 , 0 ), // {m64|mem, mm|xmm} - ROW(2, 0, 1, 0, 29 , 63 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, mm|xmm} - ROW(2, 1, 1, 0, 49 , 64 , 0 , 0 , 0 , 0 ), // #143 {xmm, xmm|m64|mem} - ROW(1, 1, 1, 0, 11 , 0 , 0 , 0 , 0 , 0 ), // #144 {r16|m16} + ROW(2, 1, 1, 0, 67 , 68 , 0 , 0 , 0 , 0 ), // #168 {mm, mm|m64|mem} + ROW(2, 0, 1, 0, 69 , 26 , 0 , 0 , 0 , 0 ), // {mm|xmm, r64|m64|mem} + ROW(2, 1, 1, 0, 31 , 69 , 0 , 0 , 0 , 0 ), // {m64|mem, mm|xmm} + ROW(2, 0, 1, 0, 26 , 69 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, mm|xmm} + ROW(2, 1, 1, 0, 55 , 70 , 0 , 0 , 0 , 0 ), // #172 {xmm, xmm|m64|mem} + ROW(1, 1, 1, 0, 11 , 0 , 0 , 0 , 0 , 0 ), // #173 {r16|m16} ROW(1, 1, 0, 0, 13 , 0 , 0 , 0 , 0 , 0 ), // {r32|m32} ROW(1, 0, 1, 0, 15 , 0 , 0 , 0 , 0 , 0 ), // {r64|m64} - ROW(1, 1, 0, 0, 65 , 0 , 0 , 0 , 0 , 0 ), // {ds|es|ss} - ROW(1, 1, 1, 0, 66 , 0 , 0 , 0 , 0 , 0 ), // {fs|gs} - ROW(1, 1, 1, 0, 67 , 0 , 0 , 0 , 0 , 0 ), // #149 {r16|m16|i8} - ROW(1, 1, 0, 0, 68 , 0 , 0 , 0 , 0 , 0 ), // {r32|m32|i32|u32} - ROW(1, 0, 1, 0, 69 , 0 , 0 , 0 , 0 , 0 ), // {r64|m64|i32} - ROW(1, 1, 0, 0, 70 , 0 , 0 , 0 , 0 , 0 ), // {cs|ss|ds|es} - ROW(1, 1, 1, 0, 66 , 0 , 0 , 0 , 0 , 0 ), // {fs|gs} - ROW(3, 1, 1, 0, 49 , 71 , 49 , 0 , 0 , 0 ), // #154 {xmm, vm32x, xmm} - ROW(3, 1, 1, 0, 52 , 72 , 52 , 0 , 0 , 0 ), // {ymm, vm32y, ymm} - ROW(2, 1, 1, 0, 49 , 71 , 0 , 0 , 0 , 0 ), // {xmm, vm32x} - ROW(2, 1, 1, 0, 52 , 72 , 0 , 0 , 0 , 0 ), // {ymm, vm32y} - ROW(2, 1, 1, 0, 55 , 73 , 0 , 0 , 0 , 0 ), // {zmm, vm32z} - ROW(3, 1, 1, 0, 49 , 74 , 49 , 0 , 0 , 0 ), // #159 {xmm, vm64x, xmm} - ROW(3, 1, 1, 0, 52 , 75 , 52 , 0 , 0 , 0 ), // {ymm, vm64y, ymm} - ROW(2, 1, 1, 0, 49 , 74 , 0 , 0 , 0 , 0 ), // {xmm, vm64x} - ROW(2, 1, 1, 0, 52 , 75 , 0 , 0 , 0 , 0 ), // {ymm, vm64y} - ROW(2, 1, 1, 0, 55 , 76 , 0 , 0 , 0 , 0 ), // {zmm, vm64z} - ROW(2, 1, 1, 0, 51 , 49 , 0 , 0 , 0 , 0 ), // #164 {m128|mem, xmm} - ROW(2, 1, 1, 0, 54 , 52 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} - ROW(2, 1, 1, 0, 51 , 49 , 0 , 0 , 0 , 0 ), // {m128|mem, xmm} - ROW(2, 1, 1, 0, 54 , 52 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} - ROW(2, 1, 1, 0, 57 , 55 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm} - ROW(2, 1, 1, 0, 49 , 51 , 0 , 0 , 0 , 0 ), // #169 {xmm, m128|mem} - ROW(2, 1, 1, 0, 52 , 54 , 0 , 0 , 0 , 0 ), // {ymm, m256|mem} - ROW(2, 1, 1, 0, 49 , 51 , 0 , 0 , 0 , 0 ), // {xmm, m128|mem} - ROW(2, 1, 1, 0, 52 , 54 , 0 , 0 , 0 , 0 ), // {ymm, m256|mem} - ROW(2, 1, 1, 0, 55 , 57 , 0 , 0 , 0 , 0 ), // {zmm, m512|mem} - ROW(2, 0, 1, 0, 29 , 49 , 0 , 0 , 0 , 0 ), // #174 {r64|m64|mem, xmm} - ROW(2, 1, 1, 0, 49 , 64 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m64|mem} - ROW(2, 0, 1, 0, 49 , 29 , 0 , 0 , 0 , 0 ), // {xmm, r64|m64|mem} - ROW(2, 1, 1, 0, 31 , 49 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} - ROW(2, 1, 1, 0, 31 , 49 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} - ROW(2, 1, 1, 0, 77 , 78 , 0 , 0 , 0 , 0 ), // #179 {ds:[memBase|zsi|m8], es:[memBase|zdi|m8]} - ROW(2, 1, 1, 0, 79 , 80 , 0 , 0 , 0 , 0 ), // {ds:[memBase|zsi|m16], es:[memBase|zdi|m16]} - ROW(2, 1, 1, 0, 81 , 82 , 0 , 0 , 0 , 0 ), // {ds:[memBase|zsi|m32], es:[memBase|zdi|m32]} - ROW(2, 0, 1, 0, 83 , 84 , 0 , 0 , 0 , 0 ), // {ds:[memBase|zsi|m64], es:[memBase|zdi|m64]} - ROW(3, 1, 1, 1, 1 , 2 , 85 , 0 , 0 , 0 ), // #183 {r8lo|r8hi|m8|mem, r8lo|r8hi, } - ROW(3, 1, 1, 1, 27 , 4 , 36 , 0 , 0 , 0 ), // {r16|m16|mem, r16, } - ROW(3, 1, 1, 1, 28 , 6 , 39 , 0 , 0 , 0 ), // {r32|m32|mem, r32, } - ROW(3, 0, 1, 1, 29 , 8 , 41 , 0 , 0 , 0 ), // {r64|m64|mem, r64, } - ROW(2, 1, 1, 0, 86 , 87 , 0 , 0 , 0 , 0 ), // #187 {k, k|m64|mem} - ROW(2, 0, 1, 0, 86 , 8 , 0 , 0 , 0 , 0 ), // {k, r64} - ROW(2, 1, 1, 0, 31 , 86 , 0 , 0 , 0 , 0 ), // {m64|mem, k} - ROW(2, 0, 1, 0, 8 , 86 , 0 , 0 , 0 , 0 ), // {r64, k} - ROW(2, 1, 1, 0, 45 , 88 , 0 , 0 , 0 , 0 ), // #191 {al, ds:[memBase|zsi|m8|mem]} - ROW(2, 1, 1, 0, 46 , 89 , 0 , 0 , 0 , 0 ), // {ax, ds:[memBase|zsi|m16|mem]} - ROW(2, 1, 1, 0, 47 , 90 , 0 , 0 , 0 , 0 ), // {eax, ds:[memBase|zsi|m32|mem]} - ROW(2, 0, 1, 0, 48 , 91 , 0 , 0 , 0 , 0 ), // {rax, ds:[memBase|zsi|m64|mem]} - ROW(2, 1, 1, 0, 78 , 77 , 0 , 0 , 0 , 0 ), // #195 {es:[memBase|zdi|m8], ds:[memBase|zsi|m8]} - ROW(2, 1, 1, 0, 80 , 79 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m16], ds:[memBase|zsi|m16]} - ROW(2, 1, 1, 0, 82 , 81 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m32], ds:[memBase|zsi|m32]} - ROW(2, 0, 1, 0, 84 , 83 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m64], ds:[memBase|zsi|m64]} - ROW(2, 1, 1, 0, 45 , 92 , 0 , 0 , 0 , 0 ), // #199 {al, es:[memBase|zdi|m8|mem]} - ROW(2, 1, 1, 0, 46 , 93 , 0 , 0 , 0 , 0 ), // {ax, es:[memBase|zdi|m16|mem]} - ROW(2, 1, 1, 0, 47 , 94 , 0 , 0 , 0 , 0 ), // {eax, es:[memBase|zdi|m32|mem]} - ROW(2, 0, 1, 0, 48 , 95 , 0 , 0 , 0 , 0 ), // {rax, es:[memBase|zdi|m64|mem]} - ROW(2, 1, 1, 0, 92 , 45 , 0 , 0 , 0 , 0 ), // #203 {es:[memBase|zdi|m8|mem], al} - ROW(2, 1, 1, 0, 93 , 46 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m16|mem], ax} - ROW(2, 1, 1, 0, 94 , 47 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m32|mem], eax} - ROW(2, 0, 1, 0, 95 , 48 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m64|mem], rax} - ROW(4, 1, 1, 0, 49 , 49 , 49 , 50 , 0 , 0 ), // #207 {xmm, xmm, xmm, xmm|m128|mem} - ROW(4, 1, 1, 0, 49 , 49 , 51 , 49 , 0 , 0 ), // {xmm, xmm, m128|mem, xmm} - ROW(4, 1, 1, 0, 52 , 52 , 52 , 53 , 0 , 0 ), // {ymm, ymm, ymm, ymm|m256|mem} - ROW(4, 1, 1, 0, 52 , 52 , 54 , 52 , 0 , 0 ), // {ymm, ymm, m256|mem, ymm} - ROW(3, 1, 1, 0, 49 , 71 , 49 , 0 , 0 , 0 ), // #211 {xmm, vm32x, xmm} - ROW(3, 1, 1, 0, 52 , 71 , 52 , 0 , 0 , 0 ), // {ymm, vm32x, ymm} - ROW(2, 1, 1, 0, 96 , 71 , 0 , 0 , 0 , 0 ), // {xmm|ymm, vm32x} - ROW(2, 1, 1, 0, 55 , 72 , 0 , 0 , 0 , 0 ), // {zmm, vm32y} - ROW(3, 1, 1, 0, 51 , 49 , 49 , 0 , 0 , 0 ), // #215 {m128|mem, xmm, xmm} - ROW(3, 1, 1, 0, 54 , 52 , 52 , 0 , 0 , 0 ), // {m256|mem, ymm, ymm} - ROW(3, 1, 1, 0, 49 , 49 , 51 , 0 , 0 , 0 ), // {xmm, xmm, m128|mem} - ROW(3, 1, 1, 0, 52 , 52 , 54 , 0 , 0 , 0 ), // {ymm, ymm, m256|mem} - ROW(2, 1, 1, 0, 31 , 49 , 0 , 0 , 0 , 0 ), // #219 {m64|mem, xmm} - ROW(3, 1, 1, 0, 49 , 49 , 31 , 0 , 0 , 0 ), // {xmm, xmm, m64|mem} - ROW(2, 1, 1, 0, 31 , 49 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} - ROW(3, 1, 1, 0, 49 , 49 , 31 , 0 , 0 , 0 ), // {xmm, xmm, m64|mem} - ROW(2, 1, 1, 0, 21 , 49 , 0 , 0 , 0 , 0 ), // #223 {m16|mem, xmm} - ROW(2, 1, 1, 0, 49 , 21 , 0 , 0 , 0 , 0 ), // {xmm, m16|mem} - ROW(3, 1, 1, 0, 49 , 49 , 49 , 0 , 0 , 0 ), // {xmm, xmm, xmm} - ROW(3, 1, 1, 0, 49 , 49 , 49 , 0 , 0 , 0 ), // {xmm, xmm, xmm} - ROW(5, 1, 1, 0, 49 , 49 , 50 , 49 , 97 , 0 ), // #227 {xmm, xmm, xmm|m128|mem, xmm, i4|u4} - ROW(5, 1, 1, 0, 49 , 49 , 49 , 51 , 97 , 0 ), // {xmm, xmm, xmm, m128|mem, i4|u4} - ROW(5, 1, 1, 0, 52 , 52 , 53 , 52 , 97 , 0 ), // {ymm, ymm, ymm|m256|mem, ymm, i4|u4} - ROW(5, 1, 1, 0, 52 , 52 , 52 , 54 , 97 , 0 ), // {ymm, ymm, ymm, m256|mem, i4|u4} - ROW(3, 1, 1, 0, 52 , 53 , 10 , 0 , 0 , 0 ), // #231 {ymm, ymm|m256|mem, i8|u8} - ROW(3, 1, 1, 0, 52 , 52 , 53 , 0 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem} - ROW(3, 1, 1, 0, 55 , 55 , 60 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem|i8|u8} - ROW(3, 1, 1, 0, 55 , 57 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} - ROW(1, 1, 0, 0, 98 , 0 , 0 , 0 , 0 , 0 ), // #235 {rel16|r16|m16|mem|r32|m32} - ROW(1, 1, 1, 0, 99 , 0 , 0 , 0 , 0 , 0 ), // #236 {rel32} - ROW(1, 0, 1, 0, 29 , 0 , 0 , 0 , 0 , 0 ), // {r64|m64|mem} - ROW(1, 1, 0, 0, 100, 0 , 0 , 0 , 0 , 0 ), // #238 {r16|r32} - ROW(1, 1, 1, 0, 32 , 0 , 0 , 0 , 0 , 0 ), // #239 {r8lo|r8hi|m8|r16|m16|r32|m32} + ROW(1, 1, 0, 0, 71 , 0 , 0 , 0 , 0 , 0 ), // {ds|es|ss} + ROW(1, 1, 1, 0, 72 , 0 , 0 , 0 , 0 , 0 ), // {fs|gs} + ROW(1, 1, 1, 0, 73 , 0 , 0 , 0 , 0 , 0 ), // #178 {r16|m16|i8|u8|i16|u16} + ROW(1, 1, 0, 0, 74 , 0 , 0 , 0 , 0 , 0 ), // {r32|m32|i32|u32} + ROW(1, 0, 1, 0, 75 , 0 , 0 , 0 , 0 , 0 ), // {r64|m64|i32} + ROW(1, 1, 0, 0, 76 , 0 , 0 , 0 , 0 , 0 ), // {cs|ss|ds|es} + ROW(1, 1, 1, 0, 72 , 0 , 0 , 0 , 0 , 0 ), // {fs|gs} + ROW(3, 1, 1, 0, 55 , 77 , 55 , 0 , 0 , 0 ), // #183 {xmm, vm32x, xmm} + ROW(3, 1, 1, 0, 57 , 78 , 57 , 0 , 0 , 0 ), // {ymm, vm32y, ymm} + ROW(2, 1, 1, 0, 55 , 77 , 0 , 0 , 0 , 0 ), // {xmm, vm32x} + ROW(2, 1, 1, 0, 57 , 78 , 0 , 0 , 0 , 0 ), // {ymm, vm32y} + ROW(2, 1, 1, 0, 61 , 79 , 0 , 0 , 0 , 0 ), // {zmm, vm32z} + ROW(3, 1, 1, 0, 55 , 80 , 55 , 0 , 0 , 0 ), // #188 {xmm, vm64x, xmm} + ROW(3, 1, 1, 0, 57 , 81 , 57 , 0 , 0 , 0 ), // {ymm, vm64y, ymm} + ROW(2, 1, 1, 0, 55 , 80 , 0 , 0 , 0 , 0 ), // {xmm, vm64x} + ROW(2, 1, 1, 0, 57 , 81 , 0 , 0 , 0 , 0 ), // {ymm, vm64y} + ROW(2, 1, 1, 0, 61 , 82 , 0 , 0 , 0 , 0 ), // {zmm, vm64z} + ROW(2, 1, 1, 0, 59 , 55 , 0 , 0 , 0 , 0 ), // #193 {m128|mem, xmm} + ROW(2, 1, 1, 0, 60 , 57 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} + ROW(2, 1, 1, 0, 59 , 55 , 0 , 0 , 0 , 0 ), // {m128|mem, xmm} + ROW(2, 1, 1, 0, 60 , 57 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} + ROW(2, 1, 1, 0, 63 , 61 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm} + ROW(2, 1, 1, 0, 55 , 59 , 0 , 0 , 0 , 0 ), // #198 {xmm, m128|mem} + ROW(2, 1, 1, 0, 57 , 60 , 0 , 0 , 0 , 0 ), // {ymm, m256|mem} + ROW(2, 1, 1, 0, 55 , 59 , 0 , 0 , 0 , 0 ), // {xmm, m128|mem} + ROW(2, 1, 1, 0, 57 , 60 , 0 , 0 , 0 , 0 ), // {ymm, m256|mem} + ROW(2, 1, 1, 0, 61 , 63 , 0 , 0 , 0 , 0 ), // {zmm, m512|mem} + ROW(2, 0, 1, 0, 26 , 55 , 0 , 0 , 0 , 0 ), // #203 {r64|m64|mem, xmm} + ROW(2, 1, 1, 0, 55 , 70 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m64|mem} + ROW(2, 0, 1, 0, 55 , 26 , 0 , 0 , 0 , 0 ), // {xmm, r64|m64|mem} + ROW(2, 1, 1, 0, 31 , 55 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} + ROW(2, 1, 1, 0, 31 , 55 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} + ROW(2, 1, 1, 0, 83 , 84 , 0 , 0 , 0 , 0 ), // #208 {ds:[memBase|zsi|m8], es:[memBase|zdi|m8]} + ROW(2, 1, 1, 0, 85 , 86 , 0 , 0 , 0 , 0 ), // {ds:[memBase|zsi|m16], es:[memBase|zdi|m16]} + ROW(2, 1, 1, 0, 87 , 88 , 0 , 0 , 0 , 0 ), // {ds:[memBase|zsi|m32], es:[memBase|zdi|m32]} + ROW(2, 0, 1, 0, 89 , 90 , 0 , 0 , 0 , 0 ), // {ds:[memBase|zsi|m64], es:[memBase|zdi|m64]} + ROW(3, 1, 1, 1, 1 , 2 , 91 , 0 , 0 , 0 ), // #212 {r8lo|r8hi|m8|mem, r8lo|r8hi, } + ROW(3, 1, 1, 1, 24 , 4 , 42 , 0 , 0 , 0 ), // {r16|m16|mem, r16, } + ROW(3, 1, 1, 1, 25 , 6 , 45 , 0 , 0 , 0 ), // {r32|m32|mem, r32, } + ROW(3, 0, 1, 1, 26 , 8 , 47 , 0 , 0 , 0 ), // {r64|m64|mem, r64, } + ROW(2, 1, 1, 0, 92 , 93 , 0 , 0 , 0 , 0 ), // #216 {k, k|m64|mem} + ROW(2, 0, 1, 0, 92 , 8 , 0 , 0 , 0 , 0 ), // {k, r64} + ROW(2, 1, 1, 0, 31 , 92 , 0 , 0 , 0 , 0 ), // {m64|mem, k} + ROW(2, 0, 1, 0, 8 , 92 , 0 , 0 , 0 , 0 ), // {r64, k} + ROW(2, 1, 1, 0, 51 , 94 , 0 , 0 , 0 , 0 ), // #220 {al, ds:[memBase|zsi|m8|mem]} + ROW(2, 1, 1, 0, 52 , 95 , 0 , 0 , 0 , 0 ), // {ax, ds:[memBase|zsi|m16|mem]} + ROW(2, 1, 1, 0, 53 , 96 , 0 , 0 , 0 , 0 ), // {eax, ds:[memBase|zsi|m32|mem]} + ROW(2, 0, 1, 0, 54 , 97 , 0 , 0 , 0 , 0 ), // {rax, ds:[memBase|zsi|m64|mem]} + ROW(2, 1, 1, 0, 84 , 83 , 0 , 0 , 0 , 0 ), // #224 {es:[memBase|zdi|m8], ds:[memBase|zsi|m8]} + ROW(2, 1, 1, 0, 86 , 85 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m16], ds:[memBase|zsi|m16]} + ROW(2, 1, 1, 0, 88 , 87 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m32], ds:[memBase|zsi|m32]} + ROW(2, 0, 1, 0, 90 , 89 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m64], ds:[memBase|zsi|m64]} + ROW(2, 1, 1, 0, 51 , 98 , 0 , 0 , 0 , 0 ), // #228 {al, es:[memBase|zdi|m8|mem]} + ROW(2, 1, 1, 0, 52 , 99 , 0 , 0 , 0 , 0 ), // {ax, es:[memBase|zdi|m16|mem]} + ROW(2, 1, 1, 0, 53 , 100, 0 , 0 , 0 , 0 ), // {eax, es:[memBase|zdi|m32|mem]} + ROW(2, 0, 1, 0, 54 , 101, 0 , 0 , 0 , 0 ), // {rax, es:[memBase|zdi|m64|mem]} + ROW(2, 1, 1, 0, 98 , 51 , 0 , 0 , 0 , 0 ), // #232 {es:[memBase|zdi|m8|mem], al} + ROW(2, 1, 1, 0, 99 , 52 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m16|mem], ax} + ROW(2, 1, 1, 0, 100, 53 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m32|mem], eax} + ROW(2, 0, 1, 0, 101, 54 , 0 , 0 , 0 , 0 ), // {es:[memBase|zdi|m64|mem], rax} + ROW(4, 1, 1, 0, 55 , 55 , 55 , 56 , 0 , 0 ), // #236 {xmm, xmm, xmm, xmm|m128|mem} + ROW(4, 1, 1, 0, 57 , 57 , 57 , 58 , 0 , 0 ), // {ymm, ymm, ymm, ymm|m256|mem} + ROW(4, 1, 1, 0, 55 , 55 , 59 , 55 , 0 , 0 ), // {xmm, xmm, m128|mem, xmm} + ROW(4, 1, 1, 0, 57 , 57 , 60 , 57 , 0 , 0 ), // {ymm, ymm, m256|mem, ymm} + ROW(3, 1, 1, 0, 55 , 77 , 55 , 0 , 0 , 0 ), // #240 {xmm, vm32x, xmm} + ROW(3, 1, 1, 0, 57 , 77 , 57 , 0 , 0 , 0 ), // {ymm, vm32x, ymm} + ROW(2, 1, 1, 0, 102, 77 , 0 , 0 , 0 , 0 ), // {xmm|ymm, vm32x} + ROW(2, 1, 1, 0, 61 , 78 , 0 , 0 , 0 , 0 ), // {zmm, vm32y} + ROW(3, 1, 1, 0, 59 , 55 , 55 , 0 , 0 , 0 ), // #244 {m128|mem, xmm, xmm} + ROW(3, 1, 1, 0, 60 , 57 , 57 , 0 , 0 , 0 ), // {m256|mem, ymm, ymm} + ROW(3, 1, 1, 0, 55 , 55 , 59 , 0 , 0 , 0 ), // {xmm, xmm, m128|mem} + ROW(3, 1, 1, 0, 57 , 57 , 60 , 0 , 0 , 0 ), // {ymm, ymm, m256|mem} + ROW(2, 1, 1, 0, 31 , 55 , 0 , 0 , 0 , 0 ), // #248 {m64|mem, xmm} + ROW(3, 1, 1, 0, 55 , 55 , 31 , 0 , 0 , 0 ), // {xmm, xmm, m64|mem} + ROW(2, 1, 1, 0, 31 , 55 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} + ROW(3, 1, 1, 0, 55 , 55 , 31 , 0 , 0 , 0 ), // {xmm, xmm, m64|mem} + ROW(2, 1, 1, 0, 21 , 55 , 0 , 0 , 0 , 0 ), // #252 {m16|mem, xmm} + ROW(2, 1, 1, 0, 55 , 21 , 0 , 0 , 0 , 0 ), // {xmm, m16|mem} + ROW(3, 1, 1, 0, 55 , 55 , 55 , 0 , 0 , 0 ), // {xmm, xmm, xmm} + ROW(3, 1, 1, 0, 55 , 55 , 55 , 0 , 0 , 0 ), // {xmm, xmm, xmm} + ROW(4, 1, 1, 0, 55 , 55 , 55 , 56 , 0 , 0 ), // #256 {xmm, xmm, xmm, xmm|m128|mem} + ROW(4, 1, 1, 0, 55 , 55 , 59 , 55 , 0 , 0 ), // {xmm, xmm, m128|mem, xmm} + ROW(4, 1, 1, 0, 57 , 57 , 57 , 58 , 0 , 0 ), // {ymm, ymm, ymm, ymm|m256|mem} + ROW(4, 1, 1, 0, 57 , 57 , 60 , 57 , 0 , 0 ), // {ymm, ymm, m256|mem, ymm} + ROW(5, 1, 1, 0, 55 , 55 , 56 , 55 , 103, 0 ), // #260 {xmm, xmm, xmm|m128|mem, xmm, i4|u4} + ROW(5, 1, 1, 0, 55 , 55 , 55 , 59 , 103, 0 ), // {xmm, xmm, xmm, m128|mem, i4|u4} + ROW(5, 1, 1, 0, 57 , 57 , 58 , 57 , 103, 0 ), // {ymm, ymm, ymm|m256|mem, ymm, i4|u4} + ROW(5, 1, 1, 0, 57 , 57 , 57 , 60 , 103, 0 ), // {ymm, ymm, ymm, m256|mem, i4|u4} + ROW(3, 1, 1, 0, 57 , 58 , 10 , 0 , 0 , 0 ), // #264 {ymm, ymm|m256|mem, i8|u8} + ROW(3, 1, 1, 0, 57 , 57 , 58 , 0 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem} + ROW(3, 1, 1, 0, 61 , 61 , 66 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem|i8|u8} + ROW(3, 1, 1, 0, 61 , 63 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} + ROW(1, 1, 0, 0, 104, 0 , 0 , 0 , 0 , 0 ), // #268 {rel16|r16|m16|mem|r32|m32} + ROW(1, 1, 1, 0, 105, 0 , 0 , 0 , 0 , 0 ), // #269 {rel32} + ROW(1, 0, 1, 0, 26 , 0 , 0 , 0 , 0 , 0 ), // {r64|m64|mem} + ROW(1, 1, 0, 0, 106, 0 , 0 , 0 , 0 , 0 ), // #271 {r16|r32} + ROW(1, 1, 1, 0, 107, 0 , 0 , 0 , 0 , 0 ), // #272 {r8lo|r8hi|m8|r16|m16|r32|m32} ROW(1, 0, 1, 0, 15 , 0 , 0 , 0 , 0 , 0 ), // {r64|m64} - ROW(1, 1, 1, 0, 101, 0 , 0 , 0 , 0 , 0 ), // #241 {m32|m64} - ROW(2, 1, 1, 0, 102, 103, 0 , 0 , 0 , 0 ), // {st0, st} - ROW(2, 1, 1, 0, 103, 102, 0 , 0 , 0 , 0 ), // {st, st0} - ROW(1, 1, 1, 0, 104, 0 , 0 , 0 , 0 , 0 ), // #244 {rel8|rel32} - ROW(1, 1, 0, 0, 105, 0 , 0 , 0 , 0 , 0 ), // {rel16|r32|m32} + ROW(1, 1, 1, 0, 108, 0 , 0 , 0 , 0 , 0 ), // #274 {m32|m64} + ROW(2, 1, 1, 0, 109, 110, 0 , 0 , 0 , 0 ), // {st0, st} + ROW(2, 1, 1, 0, 110, 109, 0 , 0 , 0 , 0 ), // {st, st0} + ROW(1, 1, 1, 0, 111, 0 , 0 , 0 , 0 , 0 ), // #277 {rel8|rel32} + ROW(1, 1, 0, 0, 112, 0 , 0 , 0 , 0 , 0 ), // {rel16|r32|m32} ROW(1, 0, 1, 0, 15 , 0 , 0 , 0 , 0 , 0 ), // {r64|m64} - ROW(2, 1, 0, 0, 106, 107, 0 , 0 , 0 , 0 ), // #247 {i16, i16|i32} - ROW(1, 1, 1, 0, 108, 0 , 0 , 0 , 0 , 0 ), // {m32|mem|m48} - ROW(1, 0, 1, 0, 109, 0 , 0 , 0 , 0 , 0 ), // {m80|mem} - ROW(2, 1, 1, 0, 4 , 30 , 0 , 0 , 0 , 0 ), // #250 {r16, m32|mem} - ROW(2, 1, 1, 0, 6 , 110, 0 , 0 , 0 , 0 ), // {r32, m48|mem} - ROW(2, 0, 1, 0, 8 , 109, 0 , 0 , 0 , 0 ), // {r64, m80|mem} - ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #253 {r16, r16|m16|mem} - ROW(2, 1, 1, 0, 6 , 111, 0 , 0 , 0 , 0 ), // {r32, r32|m16|mem} - ROW(2, 0, 1, 0, 8 , 111, 0 , 0 , 0 , 0 ), // {r64, r32|m16|mem} - ROW(2, 1, 1, 0, 4 , 9 , 0 , 0 , 0 , 0 ), // #256 {r16, r8lo|r8hi|m8} - ROW(2, 1, 1, 0, 6 , 112, 0 , 0 , 0 , 0 ), // {r32, r8lo|r8hi|m8|r16|m16} - ROW(2, 0, 1, 0, 8 , 113, 0 , 0 , 0 , 0 ), // {r64, r8lo|m8|r16|m16} - ROW(3, 1, 1, 0, 27 , 4 , 114, 0 , 0 , 0 ), // #259 {r16|m16|mem, r16, cl|i8|u8} - ROW(3, 1, 1, 0, 28 , 6 , 114, 0 , 0 , 0 ), // {r32|m32|mem, r32, cl|i8|u8} - ROW(3, 0, 1, 0, 29 , 8 , 114, 0 , 0 , 0 ), // {r64|m64|mem, r64, cl|i8|u8} - ROW(3, 1, 1, 0, 49 , 49 , 50 , 0 , 0 , 0 ), // #262 {xmm, xmm, xmm|m128|mem} - ROW(3, 1, 1, 0, 52 , 52 , 53 , 0 , 0 , 0 ), // #263 {ymm, ymm, ymm|m256|mem} - ROW(3, 1, 1, 0, 55 , 55 , 56 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem} - ROW(4, 1, 1, 0, 49 , 49 , 50 , 10 , 0 , 0 ), // #265 {xmm, xmm, xmm|m128|mem, i8|u8} - ROW(4, 1, 1, 0, 52 , 52 , 53 , 10 , 0 , 0 ), // #266 {ymm, ymm, ymm|m256|mem, i8|u8} - ROW(4, 1, 1, 0, 55 , 55 , 56 , 10 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem, i8|u8} - ROW(4, 1, 1, 0, 115, 49 , 50 , 10 , 0 , 0 ), // #268 {xmm|k, xmm, xmm|m128|mem, i8|u8} - ROW(4, 1, 1, 0, 116, 52 , 53 , 10 , 0 , 0 ), // {ymm|k, ymm, ymm|m256|mem, i8|u8} - ROW(4, 1, 1, 0, 86 , 55 , 56 , 10 , 0 , 0 ), // {k, zmm, zmm|m512|mem, i8|u8} - ROW(4, 1, 1, 0, 86 , 49 , 50 , 10 , 0 , 0 ), // #271 {k, xmm, xmm|m128|mem, i8|u8} - ROW(4, 1, 1, 0, 86 , 52 , 53 , 10 , 0 , 0 ), // {k, ymm, ymm|m256|mem, i8|u8} - ROW(4, 1, 1, 0, 86 , 55 , 56 , 10 , 0 , 0 ), // {k, zmm, zmm|m512|mem, i8|u8} - ROW(2, 1, 1, 0, 50 , 49 , 0 , 0 , 0 , 0 ), // #274 {xmm|m128|mem, xmm} - ROW(2, 1, 1, 0, 53 , 52 , 0 , 0 , 0 , 0 ), // {ymm|m256|mem, ymm} - ROW(2, 1, 1, 0, 56 , 55 , 0 , 0 , 0 , 0 ), // {zmm|m512|mem, zmm} - ROW(2, 1, 1, 0, 49 , 64 , 0 , 0 , 0 , 0 ), // #277 {xmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 52 , 50 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m128|mem} - ROW(2, 1, 1, 0, 55 , 53 , 0 , 0 , 0 , 0 ), // {zmm, ymm|m256|mem} - ROW(2, 1, 1, 0, 49 , 50 , 0 , 0 , 0 , 0 ), // #280 {xmm, xmm|m128|mem} - ROW(2, 1, 1, 0, 52 , 53 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} - ROW(2, 1, 1, 0, 55 , 56 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem} - ROW(2, 1, 1, 0, 49 , 117, 0 , 0 , 0 , 0 ), // #283 {xmm, xmm|m32|mem} - ROW(2, 1, 1, 0, 52 , 64 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m64|mem} - ROW(2, 1, 1, 0, 55 , 50 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m128|mem} - ROW(3, 1, 1, 0, 64 , 49 , 10 , 0 , 0 , 0 ), // #286 {xmm|m64|mem, xmm, i8|u8} - ROW(3, 1, 1, 0, 50 , 52 , 10 , 0 , 0 , 0 ), // #287 {xmm|m128|mem, ymm, i8|u8} - ROW(3, 1, 1, 0, 53 , 55 , 10 , 0 , 0 , 0 ), // #288 {ymm|m256|mem, zmm, i8|u8} - ROW(3, 1, 1, 0, 49 , 118, 49 , 0 , 0 , 0 ), // #289 {xmm, vm64x|vm64y, xmm} - ROW(2, 1, 1, 0, 49 , 118, 0 , 0 , 0 , 0 ), // {xmm, vm64x|vm64y} - ROW(2, 1, 1, 0, 52 , 76 , 0 , 0 , 0 , 0 ), // {ymm, vm64z} - ROW(3, 1, 1, 0, 49 , 50 , 10 , 0 , 0 , 0 ), // #292 {xmm, xmm|m128|mem, i8|u8} - ROW(3, 1, 1, 0, 52 , 53 , 10 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem, i8|u8} - ROW(3, 1, 1, 0, 55 , 56 , 10 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem, i8|u8} - ROW(2, 1, 1, 0, 49 , 64 , 0 , 0 , 0 , 0 ), // #295 {xmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 52 , 53 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} - ROW(2, 1, 1, 0, 55 , 56 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem} - ROW(4, 1, 1, 0, 86 , 86 , 49 , 50 , 0 , 0 ), // #298 {k, k, xmm, xmm|m128|mem} - ROW(4, 1, 1, 0, 86 , 86 , 52 , 53 , 0 , 0 ), // {k, k, ymm, ymm|m256|mem} - ROW(4, 1, 1, 0, 86 , 86 , 55 , 56 , 0 , 0 ), // {k, k, zmm, zmm|m512|mem} - ROW(3, 1, 1, 0, 115, 49 , 50 , 0 , 0 , 0 ), // #301 {xmm|k, xmm, xmm|m128|mem} - ROW(3, 1, 1, 0, 116, 52 , 53 , 0 , 0 , 0 ), // {ymm|k, ymm, ymm|m256|mem} - ROW(3, 1, 1, 0, 86 , 55 , 56 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem} - ROW(2, 1, 1, 0, 117, 49 , 0 , 0 , 0 , 0 ), // #304 {xmm|m32|mem, xmm} - ROW(2, 1, 1, 0, 64 , 52 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, ymm} - ROW(2, 1, 1, 0, 50 , 55 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, zmm} - ROW(2, 1, 1, 0, 64 , 49 , 0 , 0 , 0 , 0 ), // #307 {xmm|m64|mem, xmm} - ROW(2, 1, 1, 0, 50 , 52 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, ymm} - ROW(2, 1, 1, 0, 53 , 55 , 0 , 0 , 0 , 0 ), // {ymm|m256|mem, zmm} - ROW(2, 1, 1, 0, 119, 49 , 0 , 0 , 0 , 0 ), // #310 {xmm|m16|mem, xmm} - ROW(2, 1, 1, 0, 117, 52 , 0 , 0 , 0 , 0 ), // {xmm|m32|mem, ymm} - ROW(2, 1, 1, 0, 64 , 55 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, zmm} - ROW(2, 1, 1, 0, 49 , 119, 0 , 0 , 0 , 0 ), // #313 {xmm, xmm|m16|mem} - ROW(2, 1, 1, 0, 52 , 117, 0 , 0 , 0 , 0 ), // {ymm, xmm|m32|mem} - ROW(2, 1, 1, 0, 55 , 64 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 71 , 49 , 0 , 0 , 0 , 0 ), // #316 {vm32x, xmm} - ROW(2, 1, 1, 0, 72 , 52 , 0 , 0 , 0 , 0 ), // {vm32y, ymm} - ROW(2, 1, 1, 0, 73 , 55 , 0 , 0 , 0 , 0 ), // {vm32z, zmm} - ROW(2, 1, 1, 0, 74 , 49 , 0 , 0 , 0 , 0 ), // #319 {vm64x, xmm} - ROW(2, 1, 1, 0, 75 , 52 , 0 , 0 , 0 , 0 ), // {vm64y, ymm} - ROW(2, 1, 1, 0, 76 , 55 , 0 , 0 , 0 , 0 ), // {vm64z, zmm} - ROW(3, 1, 1, 0, 86 , 49 , 50 , 0 , 0 , 0 ), // #322 {k, xmm, xmm|m128|mem} - ROW(3, 1, 1, 0, 86 , 52 , 53 , 0 , 0 , 0 ), // {k, ymm, ymm|m256|mem} - ROW(3, 1, 1, 0, 86 , 55 , 56 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem} - ROW(3, 1, 1, 0, 6 , 6 , 28 , 0 , 0 , 0 ), // #325 {r32, r32, r32|m32|mem} - ROW(3, 0, 1, 0, 8 , 8 , 29 , 0 , 0 , 0 ), // {r64, r64, r64|m64|mem} - ROW(3, 1, 1, 0, 6 , 28 , 6 , 0 , 0 , 0 ), // #327 {r32, r32|m32|mem, r32} - ROW(3, 0, 1, 0, 8 , 29 , 8 , 0 , 0 , 0 ), // {r64, r64|m64|mem, r64} - ROW(2, 1, 0, 0, 120, 28 , 0 , 0 , 0 , 0 ), // #329 {bnd, r32|m32|mem} - ROW(2, 0, 1, 0, 120, 29 , 0 , 0 , 0 , 0 ), // {bnd, r64|m64|mem} - ROW(2, 1, 1, 0, 120, 121, 0 , 0 , 0 , 0 ), // #331 {bnd, bnd|mem} - ROW(2, 1, 1, 0, 122, 120, 0 , 0 , 0 , 0 ), // {mem, bnd} - ROW(2, 1, 0, 0, 4 , 30 , 0 , 0 , 0 , 0 ), // #333 {r16, m32|mem} + ROW(2, 1, 0, 0, 12 , 113, 0 , 0 , 0 , 0 ), // #280 {i16|u16, i16|u16|i32|u32} + ROW(1, 1, 1, 0, 114, 0 , 0 , 0 , 0 , 0 ), // {m32|mem|m48} + ROW(1, 0, 1, 0, 115, 0 , 0 , 0 , 0 , 0 ), // {m80|mem} + ROW(2, 1, 1, 0, 4 , 30 , 0 , 0 , 0 , 0 ), // #283 {r16, m32|mem} + ROW(2, 1, 1, 0, 6 , 116, 0 , 0 , 0 , 0 ), // {r32, m48|mem} + ROW(2, 0, 1, 0, 8 , 115, 0 , 0 , 0 , 0 ), // {r64, m80|mem} + ROW(2, 1, 1, 0, 4 , 24 , 0 , 0 , 0 , 0 ), // #286 {r16, r16|m16|mem} + ROW(2, 1, 1, 0, 6 , 117, 0 , 0 , 0 , 0 ), // {r32, r32|m16|mem} + ROW(2, 0, 1, 0, 8 , 117, 0 , 0 , 0 , 0 ), // {r64, r32|m16|mem} + ROW(2, 1, 1, 0, 4 , 9 , 0 , 0 , 0 , 0 ), // #289 {r16, r8lo|r8hi|m8} + ROW(2, 1, 1, 0, 6 , 118, 0 , 0 , 0 , 0 ), // {r32, r8lo|r8hi|m8|r16|m16} + ROW(2, 0, 1, 0, 8 , 118, 0 , 0 , 0 , 0 ), // {r64, r8lo|r8hi|m8|r16|m16} + ROW(3, 1, 1, 3, 44 , 45 , 119, 0 , 0 , 0 ), // #292 {, , } + ROW(2, 0, 1, 0, 8 , 14 , 0 , 0 , 0 , 0 ), // {r64, i32|u32} + ROW(2, 0, 1, 0, 8 , 14 , 0 , 0 , 0 , 0 ), // {r64, i32|u32} + ROW(3, 1, 1, 0, 24 , 4 , 120, 0 , 0 , 0 ), // #295 {r16|m16|mem, r16, cl|i8|u8} + ROW(3, 1, 1, 0, 25 , 6 , 120, 0 , 0 , 0 ), // {r32|m32|mem, r32, cl|i8|u8} + ROW(3, 0, 1, 0, 26 , 8 , 120, 0 , 0 , 0 ), // {r64|m64|mem, r64, cl|i8|u8} + ROW(3, 1, 1, 0, 55 , 55 , 56 , 0 , 0 , 0 ), // #298 {xmm, xmm, xmm|m128|mem} + ROW(3, 1, 1, 0, 57 , 57 , 58 , 0 , 0 , 0 ), // #299 {ymm, ymm, ymm|m256|mem} + ROW(3, 1, 1, 0, 61 , 61 , 62 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem} + ROW(4, 1, 1, 0, 55 , 55 , 56 , 10 , 0 , 0 ), // #301 {xmm, xmm, xmm|m128|mem, i8|u8} + ROW(4, 1, 1, 0, 57 , 57 , 58 , 10 , 0 , 0 ), // #302 {ymm, ymm, ymm|m256|mem, i8|u8} + ROW(4, 1, 1, 0, 61 , 61 , 62 , 10 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem, i8|u8} + ROW(4, 1, 1, 0, 121, 55 , 56 , 10 , 0 , 0 ), // #304 {xmm|k, xmm, xmm|m128|mem, i8|u8} + ROW(4, 1, 1, 0, 122, 57 , 58 , 10 , 0 , 0 ), // {ymm|k, ymm, ymm|m256|mem, i8|u8} + ROW(4, 1, 1, 0, 92 , 61 , 62 , 10 , 0 , 0 ), // {k, zmm, zmm|m512|mem, i8|u8} + ROW(4, 1, 1, 0, 92 , 55 , 56 , 10 , 0 , 0 ), // #307 {k, xmm, xmm|m128|mem, i8|u8} + ROW(4, 1, 1, 0, 92 , 57 , 58 , 10 , 0 , 0 ), // {k, ymm, ymm|m256|mem, i8|u8} + ROW(4, 1, 1, 0, 92 , 61 , 62 , 10 , 0 , 0 ), // {k, zmm, zmm|m512|mem, i8|u8} + ROW(2, 1, 1, 0, 56 , 55 , 0 , 0 , 0 , 0 ), // #310 {xmm|m128|mem, xmm} + ROW(2, 1, 1, 0, 58 , 57 , 0 , 0 , 0 , 0 ), // {ymm|m256|mem, ymm} + ROW(2, 1, 1, 0, 62 , 61 , 0 , 0 , 0 , 0 ), // {zmm|m512|mem, zmm} + ROW(2, 1, 1, 0, 55 , 70 , 0 , 0 , 0 , 0 ), // #313 {xmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 57 , 56 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m128|mem} + ROW(2, 1, 1, 0, 61 , 58 , 0 , 0 , 0 , 0 ), // {zmm, ymm|m256|mem} + ROW(2, 1, 1, 0, 55 , 123, 0 , 0 , 0 , 0 ), // #316 {xmm, xmm|m32|mem} + ROW(2, 1, 1, 0, 57 , 70 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m64|mem} + ROW(2, 1, 1, 0, 61 , 56 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m128|mem} + ROW(3, 1, 1, 0, 70 , 55 , 10 , 0 , 0 , 0 ), // #319 {xmm|m64|mem, xmm, i8|u8} + ROW(3, 1, 1, 0, 56 , 57 , 10 , 0 , 0 , 0 ), // #320 {xmm|m128|mem, ymm, i8|u8} + ROW(3, 1, 1, 0, 58 , 61 , 10 , 0 , 0 , 0 ), // #321 {ymm|m256|mem, zmm, i8|u8} + ROW(3, 1, 1, 0, 55 , 124, 55 , 0 , 0 , 0 ), // #322 {xmm, vm64x|vm64y, xmm} + ROW(2, 1, 1, 0, 55 , 124, 0 , 0 , 0 , 0 ), // {xmm, vm64x|vm64y} + ROW(2, 1, 1, 0, 57 , 82 , 0 , 0 , 0 , 0 ), // {ymm, vm64z} + ROW(3, 1, 1, 0, 55 , 56 , 10 , 0 , 0 , 0 ), // #325 {xmm, xmm|m128|mem, i8|u8} + ROW(3, 1, 1, 0, 57 , 58 , 10 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem, i8|u8} + ROW(3, 1, 1, 0, 61 , 62 , 10 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem, i8|u8} + ROW(2, 1, 1, 0, 55 , 70 , 0 , 0 , 0 , 0 ), // #328 {xmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 57 , 58 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} + ROW(2, 1, 1, 0, 61 , 62 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem} + ROW(4, 1, 1, 0, 92 , 92 , 55 , 56 , 0 , 0 ), // #331 {k, k, xmm, xmm|m128|mem} + ROW(4, 1, 1, 0, 92 , 92 , 57 , 58 , 0 , 0 ), // {k, k, ymm, ymm|m256|mem} + ROW(4, 1, 1, 0, 92 , 92 , 61 , 62 , 0 , 0 ), // {k, k, zmm, zmm|m512|mem} + ROW(3, 1, 1, 0, 121, 55 , 56 , 0 , 0 , 0 ), // #334 {xmm|k, xmm, xmm|m128|mem} + ROW(3, 1, 1, 0, 122, 57 , 58 , 0 , 0 , 0 ), // {ymm|k, ymm, ymm|m256|mem} + ROW(3, 1, 1, 0, 92 , 61 , 62 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem} + ROW(2, 1, 1, 0, 123, 55 , 0 , 0 , 0 , 0 ), // #337 {xmm|m32|mem, xmm} + ROW(2, 1, 1, 0, 70 , 57 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, ymm} + ROW(2, 1, 1, 0, 56 , 61 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, zmm} + ROW(2, 1, 1, 0, 70 , 55 , 0 , 0 , 0 , 0 ), // #340 {xmm|m64|mem, xmm} + ROW(2, 1, 1, 0, 56 , 57 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, ymm} + ROW(2, 1, 1, 0, 58 , 61 , 0 , 0 , 0 , 0 ), // {ymm|m256|mem, zmm} + ROW(2, 1, 1, 0, 125, 55 , 0 , 0 , 0 , 0 ), // #343 {xmm|m16|mem, xmm} + ROW(2, 1, 1, 0, 123, 57 , 0 , 0 , 0 , 0 ), // {xmm|m32|mem, ymm} + ROW(2, 1, 1, 0, 70 , 61 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, zmm} + ROW(2, 1, 1, 0, 55 , 125, 0 , 0 , 0 , 0 ), // #346 {xmm, xmm|m16|mem} + ROW(2, 1, 1, 0, 57 , 123, 0 , 0 , 0 , 0 ), // {ymm, xmm|m32|mem} + ROW(2, 1, 1, 0, 61 , 70 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 77 , 55 , 0 , 0 , 0 , 0 ), // #349 {vm32x, xmm} + ROW(2, 1, 1, 0, 78 , 57 , 0 , 0 , 0 , 0 ), // {vm32y, ymm} + ROW(2, 1, 1, 0, 79 , 61 , 0 , 0 , 0 , 0 ), // {vm32z, zmm} + ROW(2, 1, 1, 0, 80 , 55 , 0 , 0 , 0 , 0 ), // #352 {vm64x, xmm} + ROW(2, 1, 1, 0, 81 , 57 , 0 , 0 , 0 , 0 ), // {vm64y, ymm} + ROW(2, 1, 1, 0, 82 , 61 , 0 , 0 , 0 , 0 ), // {vm64z, zmm} + ROW(3, 1, 1, 0, 92 , 55 , 56 , 0 , 0 , 0 ), // #355 {k, xmm, xmm|m128|mem} + ROW(3, 1, 1, 0, 92 , 57 , 58 , 0 , 0 , 0 ), // {k, ymm, ymm|m256|mem} + ROW(3, 1, 1, 0, 92 , 61 , 62 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem} + ROW(3, 1, 1, 0, 6 , 6 , 25 , 0 , 0 , 0 ), // #358 {r32, r32, r32|m32|mem} + ROW(3, 0, 1, 0, 8 , 8 , 26 , 0 , 0 , 0 ), // {r64, r64, r64|m64|mem} + ROW(3, 1, 1, 0, 6 , 25 , 6 , 0 , 0 , 0 ), // #360 {r32, r32|m32|mem, r32} + ROW(3, 0, 1, 0, 8 , 26 , 8 , 0 , 0 , 0 ), // {r64, r64|m64|mem, r64} + ROW(2, 1, 0, 0, 126, 25 , 0 , 0 , 0 , 0 ), // #362 {bnd, r32|m32|mem} + ROW(2, 0, 1, 0, 126, 26 , 0 , 0 , 0 , 0 ), // {bnd, r64|m64|mem} + ROW(2, 1, 1, 0, 126, 127, 0 , 0 , 0 , 0 ), // #364 {bnd, bnd|mem} + ROW(2, 1, 1, 0, 128, 126, 0 , 0 , 0 , 0 ), // {mem, bnd} + ROW(2, 1, 0, 0, 4 , 30 , 0 , 0 , 0 , 0 ), // #366 {r16, m32|mem} ROW(2, 1, 0, 0, 6 , 31 , 0 , 0 , 0 , 0 ), // {r32, m64|mem} - ROW(1, 1, 1, 0, 100, 0 , 0 , 0 , 0 , 0 ), // #335 {r16|r32} - ROW(1, 0, 1, 0, 8 , 0 , 0 , 0 , 0 , 0 ), // #336 {r64} - ROW(3, 1, 1, 0, 30 , 6 , 6 , 0 , 0 , 0 ), // #337 {m32|mem, r32, r32} + ROW(1, 1, 1, 0, 106, 0 , 0 , 0 , 0 , 0 ), // #368 {r16|r32} + ROW(1, 0, 1, 0, 8 , 0 , 0 , 0 , 0 , 0 ), // #369 {r64} + ROW(3, 1, 1, 0, 30 , 6 , 6 , 0 , 0 , 0 ), // #370 {m32|mem, r32, r32} ROW(3, 0, 1, 0, 31 , 8 , 8 , 0 , 0 , 0 ), // {m64|mem, r64, r64} - ROW(2, 1, 1, 0, 6 , 32 , 0 , 0 , 0 , 0 ), // #339 {r32, r8lo|r8hi|m8|r16|m16|r32|m32} - ROW(2, 0, 1, 0, 8 , 123, 0 , 0 , 0 , 0 ), // {r64, r8lo|m8|r64|m64} - ROW(2, 1, 1, 0, 6 , 64 , 0 , 0 , 0 , 0 ), // #341 {r32, xmm|m64|mem} - ROW(2, 0, 1, 0, 8 , 64 , 0 , 0 , 0 , 0 ), // {r64, xmm|m64|mem} - ROW(2, 1, 1, 0, 49 , 28 , 0 , 0 , 0 , 0 ), // #343 {xmm, r32|m32|mem} - ROW(2, 0, 1, 0, 49 , 29 , 0 , 0 , 0 , 0 ), // {xmm, r64|m64|mem} - ROW(2, 0, 1, 0, 49 , 29 , 0 , 0 , 0 , 0 ), // #345 {xmm, r64|m64|mem} - ROW(2, 1, 1, 0, 49 , 28 , 0 , 0 , 0 , 0 ), // {xmm, r32|m32|mem} - ROW(2, 1, 1, 0, 6 , 117, 0 , 0 , 0 , 0 ), // #347 {r32, xmm|m32|mem} - ROW(2, 0, 1, 0, 8 , 117, 0 , 0 , 0 , 0 ), // {r64, xmm|m32|mem} - ROW(2, 0, 1, 0, 8 , 117, 0 , 0 , 0 , 0 ), // #349 {r64, xmm|m32|mem} - ROW(2, 1, 1, 0, 6 , 117, 0 , 0 , 0 , 0 ), // {r32, xmm|m32|mem} - ROW(2, 1, 0, 0, 124, 57 , 0 , 0 , 0 , 0 ), // #351 {es:[mem|m512|memBase], m512|mem} - ROW(2, 0, 1, 0, 124, 57 , 0 , 0 , 0 , 0 ), // {es:[mem|m512|memBase], m512|mem} - ROW(3, 1, 1, 0, 49 , 10 , 10 , 0 , 0 , 0 ), // #353 {xmm, i8|u8, i8|u8} - ROW(2, 1, 1, 0, 49 , 49 , 0 , 0 , 0 , 0 ), // #354 {xmm, xmm} - ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #355 {} - ROW(1, 1, 1, 0, 103, 0 , 0 , 0 , 0 , 0 ), // #356 {st} - ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #357 {} - ROW(1, 1, 1, 0, 125, 0 , 0 , 0 , 0 , 0 ), // #358 {m32|m64|st} - ROW(2, 1, 1, 0, 49 , 49 , 0 , 0 , 0 , 0 ), // #359 {xmm, xmm} - ROW(4, 1, 1, 0, 49 , 49 , 10 , 10 , 0 , 0 ), // {xmm, xmm, i8|u8, i8|u8} - ROW(2, 1, 0, 0, 6 , 51 , 0 , 0 , 0 , 0 ), // #361 {r32, m128|mem} - ROW(2, 0, 1, 0, 8 , 51 , 0 , 0 , 0 , 0 ), // {r64, m128|mem} - ROW(2, 1, 0, 2, 39 , 126, 0 , 0 , 0 , 0 ), // #363 {, } - ROW(2, 0, 1, 2, 127, 126, 0 , 0 , 0 , 0 ), // {, } - ROW(3, 1, 0, 3, 39 , 38 , 126, 0 , 0 , 0 ), // #365 {, , } - ROW(3, 0, 1, 3, 127, 38 , 126, 0 , 0 , 0 ), // {, , } - ROW(2, 1, 0, 1, 128, 129, 0 , 0 , 0 , 0 ), // #367 {, rel8} - ROW(2, 0, 1, 1, 130, 129, 0 , 0 , 0 , 0 ), // {, rel8} - ROW(2, 1, 1, 0, 86 , 131, 0 , 0 , 0 , 0 ), // #369 {k, k|m8|mem|r32} - ROW(2, 1, 1, 0, 132, 86 , 0 , 0 , 0 , 0 ), // {m8|mem|r32, k} - ROW(2, 1, 1, 0, 86 , 133, 0 , 0 , 0 , 0 ), // #371 {k, k|m32|mem|r32} - ROW(2, 1, 1, 0, 28 , 86 , 0 , 0 , 0 , 0 ), // {m32|mem|r32, k} - ROW(2, 1, 1, 0, 86 , 134, 0 , 0 , 0 , 0 ), // #373 {k, k|m16|mem|r32} - ROW(2, 1, 1, 0, 111, 86 , 0 , 0 , 0 , 0 ), // {m16|mem|r32, k} - ROW(2, 1, 0, 0, 4 , 30 , 0 , 0 , 0 , 0 ), // #375 {r16, m32|mem} - ROW(2, 1, 0, 0, 6 , 110, 0 , 0 , 0 , 0 ), // {r32, m48|mem} - ROW(2, 1, 1, 0, 100, 135, 0 , 0 , 0 , 0 ), // #377 {r16|r32, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024} - ROW(2, 0, 1, 0, 8 , 135, 0 , 0 , 0 , 0 ), // {r64, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024} - ROW(1, 1, 1, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #379 {r32} + ROW(2, 1, 1, 0, 6 , 107, 0 , 0 , 0 , 0 ), // #372 {r32, r8lo|r8hi|m8|r16|m16|r32|m32} + ROW(2, 0, 1, 0, 8 , 129, 0 , 0 , 0 , 0 ), // {r64, r8lo|r8hi|m8|r64|m64} + ROW(2, 1, 1, 0, 6 , 70 , 0 , 0 , 0 , 0 ), // #374 {r32, xmm|m64|mem} + ROW(2, 0, 1, 0, 8 , 70 , 0 , 0 , 0 , 0 ), // {r64, xmm|m64|mem} + ROW(2, 1, 1, 0, 55 , 25 , 0 , 0 , 0 , 0 ), // #376 {xmm, r32|m32|mem} + ROW(2, 0, 1, 0, 55 , 26 , 0 , 0 , 0 , 0 ), // {xmm, r64|m64|mem} + ROW(2, 1, 1, 0, 6 , 123, 0 , 0 , 0 , 0 ), // #378 {r32, xmm|m32|mem} + ROW(2, 0, 1, 0, 8 , 123, 0 , 0 , 0 , 0 ), // {r64, xmm|m32|mem} + ROW(2, 1, 0, 0, 130, 63 , 0 , 0 , 0 , 0 ), // #380 {es:[mem|m512|memBase], m512|mem} + ROW(2, 0, 1, 0, 130, 63 , 0 , 0 , 0 , 0 ), // {es:[mem|m512|memBase], m512|mem} + ROW(3, 1, 1, 0, 55 , 10 , 10 , 0 , 0 , 0 ), // #382 {xmm, i8|u8, i8|u8} + ROW(2, 1, 1, 0, 55 , 55 , 0 , 0 , 0 , 0 ), // #383 {xmm, xmm} + ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #384 {} + ROW(1, 1, 1, 0, 110, 0 , 0 , 0 , 0 , 0 ), // #385 {st} + ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #386 {} + ROW(1, 1, 1, 0, 131, 0 , 0 , 0 , 0 , 0 ), // #387 {m32|m64|st} + ROW(2, 1, 1, 0, 55 , 55 , 0 , 0 , 0 , 0 ), // #388 {xmm, xmm} + ROW(4, 1, 1, 0, 55 , 55 , 10 , 10 , 0 , 0 ), // {xmm, xmm, i8|u8, i8|u8} + ROW(2, 1, 0, 0, 6 , 59 , 0 , 0 , 0 , 0 ), // #390 {r32, m128|mem} + ROW(2, 0, 1, 0, 8 , 59 , 0 , 0 , 0 , 0 ), // {r64, m128|mem} + ROW(2, 1, 0, 2, 45 , 119, 0 , 0 , 0 , 0 ), // #392 {, } + ROW(2, 0, 1, 2, 132, 119, 0 , 0 , 0 , 0 ), // {, } + ROW(3, 1, 0, 3, 45 , 44 , 119, 0 , 0 , 0 ), // #394 {, , } + ROW(3, 0, 1, 3, 132, 44 , 119, 0 , 0 , 0 ), // {, , } + ROW(1, 1, 1, 0, 111, 0 , 0 , 0 , 0 , 0 ), // #396 {rel8|rel32} + ROW(1, 1, 0, 0, 105, 0 , 0 , 0 , 0 , 0 ), // {rel16} + ROW(2, 1, 0, 1, 133, 134, 0 , 0 , 0 , 0 ), // #398 {, rel8} + ROW(2, 0, 1, 1, 135, 134, 0 , 0 , 0 , 0 ), // {, rel8} + ROW(2, 1, 1, 0, 92 , 136, 0 , 0 , 0 , 0 ), // #400 {k, k|m8|mem|r32} + ROW(2, 1, 1, 0, 137, 92 , 0 , 0 , 0 , 0 ), // {m8|mem|r32, k} + ROW(2, 1, 1, 0, 92 , 138, 0 , 0 , 0 , 0 ), // #402 {k, k|m32|mem|r32} + ROW(2, 1, 1, 0, 25 , 92 , 0 , 0 , 0 , 0 ), // {m32|mem|r32, k} + ROW(2, 1, 1, 0, 92 , 139, 0 , 0 , 0 , 0 ), // #404 {k, k|m16|mem|r32} + ROW(2, 1, 1, 0, 117, 92 , 0 , 0 , 0 , 0 ), // {m16|mem|r32, k} + ROW(2, 1, 0, 0, 4 , 30 , 0 , 0 , 0 , 0 ), // #406 {r16, m32|mem} + ROW(2, 1, 0, 0, 6 , 116, 0 , 0 , 0 , 0 ), // {r32, m48|mem} + ROW(2, 1, 1, 0, 106, 140, 0 , 0 , 0 , 0 ), // #408 {r16|r32, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024} + ROW(2, 0, 1, 0, 8 , 140, 0 , 0 , 0 , 0 ), // {r64, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024} + ROW(1, 1, 1, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #410 {r32} ROW(1, 0, 1, 0, 8 , 0 , 0 , 0 , 0 , 0 ), // {r64} - ROW(3, 1, 1, 0, 6 , 28 , 14 , 0 , 0 , 0 ), // #381 {r32, r32|m32|mem, i32|u32} - ROW(3, 0, 1, 0, 8 , 28 , 14 , 0 , 0 , 0 ), // {r64, r32|m32|mem, i32|u32} - ROW(2, 1, 1, 0, 63 , 28 , 0 , 0 , 0 , 0 ), // #383 {mm|xmm, r32|m32|mem} - ROW(2, 1, 1, 0, 28 , 63 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, mm|xmm} - ROW(2, 1, 1, 0, 124, 57 , 0 , 0 , 0 , 0 ), // #385 {es:[mem|m512|memBase], m512|mem} - ROW(2, 1, 1, 0, 124, 57 , 0 , 0 , 0 , 0 ), // {es:[mem|m512|memBase], m512|mem} - ROW(2, 1, 1, 0, 49 , 64 , 0 , 0 , 0 , 0 ), // #387 {xmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 31 , 49 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} - ROW(2, 1, 1, 0, 49 , 117, 0 , 0 , 0 , 0 ), // #389 {xmm, xmm|m32|mem} - ROW(2, 1, 1, 0, 30 , 49 , 0 , 0 , 0 , 0 ), // {m32|mem, xmm} - ROW(2, 0, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #391 {r16, r16|m16|mem} - ROW(2, 0, 1, 0, 136, 28 , 0 , 0 , 0 , 0 ), // {r32|r64, r32|m32|mem} - ROW(4, 1, 1, 1, 6 , 6 , 28 , 38 , 0 , 0 ), // #393 {r32, r32, r32|m32|mem, } - ROW(4, 0, 1, 1, 8 , 8 , 29 , 40 , 0 , 0 ), // {r64, r64, r64|m64|mem, } - ROW(2, 1, 1, 0, 61 , 62 , 0 , 0 , 0 , 0 ), // #395 {mm, mm|m64|mem} - ROW(2, 1, 1, 0, 49 , 50 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem} - ROW(3, 1, 1, 0, 61 , 62 , 10 , 0 , 0 , 0 ), // #397 {mm, mm|m64|mem, i8|u8} - ROW(3, 1, 1, 0, 49 , 50 , 10 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem, i8|u8} - ROW(3, 1, 1, 0, 6 , 63 , 10 , 0 , 0 , 0 ), // #399 {r32, mm|xmm, i8|u8} - ROW(3, 1, 1, 0, 21 , 49 , 10 , 0 , 0 , 0 ), // {m16|mem, xmm, i8|u8} - ROW(2, 1, 1, 0, 61 , 137, 0 , 0 , 0 , 0 ), // #401 {mm, i8|u8|mm|m64|mem} - ROW(2, 1, 1, 0, 49 , 58 , 0 , 0 , 0 , 0 ), // {xmm, i8|u8|xmm|m128|mem} - ROW(1, 1, 1, 0, 28 , 0 , 0 , 0 , 0 , 0 ), // #403 {r32|m32|mem} - ROW(1, 0, 1, 0, 29 , 0 , 0 , 0 , 0 , 0 ), // {r64|m64|mem} - ROW(2, 1, 1, 0, 61 , 138, 0 , 0 , 0 , 0 ), // #405 {mm, mm|m32|mem} - ROW(2, 1, 1, 0, 49 , 50 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem} - ROW(2, 1, 1, 0, 32 , 114, 0 , 0 , 0 , 0 ), // #407 {r8lo|r8hi|m8|r16|m16|r32|m32, cl|i8|u8} - ROW(2, 0, 1, 0, 15 , 114, 0 , 0 , 0 , 0 ), // {r64|m64, cl|i8|u8} - ROW(1, 1, 0, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #409 {r32} + ROW(3, 1, 1, 0, 6 , 25 , 14 , 0 , 0 , 0 ), // #412 {r32, r32|m32|mem, i32|u32} + ROW(3, 0, 1, 0, 8 , 25 , 14 , 0 , 0 , 0 ), // {r64, r32|m32|mem, i32|u32} + ROW(2, 1, 1, 0, 55 , 56 , 0 , 0 , 0 , 0 ), // #414 {xmm, xmm|m128|mem} + ROW(2, 1, 1, 0, 59 , 55 , 0 , 0 , 0 , 0 ), // {m128|mem, xmm} + ROW(2, 1, 1, 0, 69 , 25 , 0 , 0 , 0 , 0 ), // #416 {mm|xmm, r32|m32|mem} + ROW(2, 1, 1, 0, 25 , 69 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, mm|xmm} + ROW(2, 1, 1, 0, 130, 63 , 0 , 0 , 0 , 0 ), // #418 {es:[mem|m512|memBase], m512|mem} + ROW(2, 1, 1, 0, 130, 63 , 0 , 0 , 0 , 0 ), // {es:[mem|m512|memBase], m512|mem} + ROW(2, 1, 1, 0, 55 , 70 , 0 , 0 , 0 , 0 ), // #420 {xmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 31 , 55 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} + ROW(2, 1, 1, 0, 55 , 123, 0 , 0 , 0 , 0 ), // #422 {xmm, xmm|m32|mem} + ROW(2, 1, 1, 0, 30 , 55 , 0 , 0 , 0 , 0 ), // {m32|mem, xmm} + ROW(2, 0, 1, 0, 4 , 24 , 0 , 0 , 0 , 0 ), // #424 {r16, r16|m16|mem} + ROW(2, 0, 1, 0, 141, 25 , 0 , 0 , 0 , 0 ), // {r32|r64, r32|m32|mem} + ROW(4, 1, 1, 1, 6 , 6 , 25 , 44 , 0 , 0 ), // #426 {r32, r32, r32|m32|mem, } + ROW(4, 0, 1, 1, 8 , 8 , 26 , 46 , 0 , 0 ), // {r64, r64, r64|m64|mem, } + ROW(2, 1, 1, 0, 67 , 68 , 0 , 0 , 0 , 0 ), // #428 {mm, mm|m64|mem} + ROW(2, 1, 1, 0, 55 , 56 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem} + ROW(3, 1, 1, 0, 67 , 68 , 10 , 0 , 0 , 0 ), // #430 {mm, mm|m64|mem, i8|u8} + ROW(3, 1, 1, 0, 55 , 56 , 10 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem, i8|u8} + ROW(3, 1, 1, 0, 6 , 69 , 10 , 0 , 0 , 0 ), // #432 {r32, mm|xmm, i8|u8} + ROW(3, 1, 1, 0, 21 , 55 , 10 , 0 , 0 , 0 ), // {m16|mem, xmm, i8|u8} + ROW(2, 1, 1, 0, 67 , 142, 0 , 0 , 0 , 0 ), // #434 {mm, mm|m64|mem|i8|u8} + ROW(2, 1, 1, 0, 55 , 64 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem|i8|u8} + ROW(1, 1, 1, 0, 25 , 0 , 0 , 0 , 0 , 0 ), // #436 {r32|m32|mem} + ROW(1, 0, 1, 0, 26 , 0 , 0 , 0 , 0 , 0 ), // {r64|m64|mem} + ROW(2, 1, 1, 0, 67 , 143, 0 , 0 , 0 , 0 ), // #438 {mm, mm|m32|mem} + ROW(2, 1, 1, 0, 55 , 56 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem} + ROW(2, 1, 1, 0, 107, 120, 0 , 0 , 0 , 0 ), // #440 {r8lo|r8hi|m8|r16|m16|r32|m32, cl|i8|u8} + ROW(2, 0, 1, 0, 15 , 120, 0 , 0 , 0 , 0 ), // {r64|m64, cl|i8|u8} + ROW(1, 1, 0, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #442 {r32} ROW(1, 0, 1, 0, 8 , 0 , 0 , 0 , 0 , 0 ), // {r64} - ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #411 {} - ROW(1, 1, 1, 0, 139, 0 , 0 , 0 , 0 , 0 ), // {u16} - ROW(3, 1, 1, 0, 6 , 28 , 10 , 0 , 0 , 0 ), // #413 {r32, r32|m32|mem, i8|u8} - ROW(3, 0, 1, 0, 8 , 29 , 10 , 0 , 0 , 0 ), // {r64, r64|m64|mem, i8|u8} - ROW(1, 1, 1, 0, 140, 0 , 0 , 0 , 0 , 0 ), // #415 {r16|m16|mem|r32} - ROW(1, 0, 1, 0, 141, 0 , 0 , 0 , 0 , 0 ), // {r64|m16|mem} - ROW(1, 1, 0, 0, 142, 0 , 0 , 0 , 0 , 0 ), // #417 {ds:[mem|memBase]} - ROW(1, 0, 1, 0, 142, 0 , 0 , 0 , 0 , 0 ), // {ds:[mem|memBase]} - ROW(4, 1, 1, 0, 49 , 49 , 50 , 49 , 0 , 0 ), // #419 {xmm, xmm, xmm|m128|mem, xmm} - ROW(4, 1, 1, 0, 52 , 52 , 53 , 52 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem, ymm} - ROW(2, 1, 1, 0, 49 , 143, 0 , 0 , 0 , 0 ), // #421 {xmm, xmm|m128|ymm|m256} - ROW(2, 1, 1, 0, 52 , 56 , 0 , 0 , 0 , 0 ), // {ymm, zmm|m512|mem} - ROW(2, 1, 1, 0, 6 , 119, 0 , 0 , 0 , 0 ), // #423 {r32, xmm|m16|mem} - ROW(2, 0, 1, 0, 8 , 119, 0 , 0 , 0 , 0 ), // {r64, xmm|m16|mem} - ROW(3, 1, 1, 0, 49 , 49 , 28 , 0 , 0 , 0 ), // #425 {xmm, xmm, r32|m32|mem} - ROW(3, 0, 1, 0, 49 , 49 , 29 , 0 , 0 , 0 ), // {xmm, xmm, r64|m64|mem} - ROW(3, 1, 1, 0, 49 , 49 , 13 , 0 , 0 , 0 ), // #427 {xmm, xmm, r32|m32} - ROW(3, 0, 1, 0, 49 , 49 , 15 , 0 , 0 , 0 ), // {xmm, xmm, r64|m64} - ROW(4, 1, 1, 0, 49 , 49 , 49 , 64 , 0 , 0 ), // #429 {xmm, xmm, xmm, xmm|m64|mem} - ROW(4, 1, 1, 0, 49 , 49 , 31 , 49 , 0 , 0 ), // {xmm, xmm, m64|mem, xmm} - ROW(4, 1, 1, 0, 49 , 49 , 49 , 117, 0 , 0 ), // #431 {xmm, xmm, xmm, xmm|m32|mem} - ROW(4, 1, 1, 0, 49 , 49 , 30 , 49 , 0 , 0 ), // {xmm, xmm, m32|mem, xmm} - ROW(4, 1, 1, 0, 52 , 52 , 50 , 10 , 0 , 0 ), // #433 {ymm, ymm, xmm|m128|mem, i8|u8} - ROW(4, 1, 1, 0, 55 , 55 , 50 , 10 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem, i8|u8} - ROW(1, 1, 0, 1, 39 , 0 , 0 , 0 , 0 , 0 ), // #435 {} - ROW(1, 0, 1, 1, 41 , 0 , 0 , 0 , 0 , 0 ), // #436 {} - ROW(2, 1, 1, 0, 28 , 49 , 0 , 0 , 0 , 0 ), // #437 {r32|m32|mem, xmm} - ROW(2, 1, 1, 0, 49 , 28 , 0 , 0 , 0 , 0 ), // {xmm, r32|m32|mem} - ROW(2, 1, 1, 0, 111, 49 , 0 , 0 , 0 , 0 ), // #439 {r32|m16|mem, xmm} - ROW(2, 1, 1, 0, 49 , 111, 0 , 0 , 0 , 0 ), // {xmm, r32|m16|mem} - ROW(2, 1, 0, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // #441 {r32|m32|mem, r32} - ROW(2, 0, 1, 0, 29 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} - ROW(2, 1, 0, 0, 6 , 28 , 0 , 0 , 0 , 0 ), // #443 {r32, r32|m32|mem} - ROW(2, 0, 1, 0, 8 , 29 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem} - ROW(2, 1, 1, 0, 144, 64 , 0 , 0 , 0 , 0 ), // #445 {xmm|ymm|zmm, xmm|m64|mem} - ROW(2, 0, 1, 0, 144, 8 , 0 , 0 , 0 , 0 ), // {xmm|ymm|zmm, r64} - ROW(3, 1, 1, 0, 49 , 49 , 58 , 0 , 0 , 0 ), // #447 {xmm, xmm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 49 , 51 , 145, 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8|xmm} - ROW(2, 1, 1, 0, 71 , 96 , 0 , 0 , 0 , 0 ), // #449 {vm32x, xmm|ymm} - ROW(2, 1, 1, 0, 72 , 55 , 0 , 0 , 0 , 0 ), // {vm32y, zmm} - ROW(2, 1, 1, 0, 118, 49 , 0 , 0 , 0 , 0 ), // #451 {vm64x|vm64y, xmm} - ROW(2, 1, 1, 0, 76 , 52 , 0 , 0 , 0 , 0 ), // {vm64z, ymm} - ROW(3, 1, 1, 0, 49 , 49 , 50 , 0 , 0 , 0 ), // #453 {xmm, xmm, xmm|m128|mem} - ROW(3, 1, 1, 0, 49 , 51 , 49 , 0 , 0 , 0 ), // {xmm, m128|mem, xmm} - ROW(1, 1, 0, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #455 {} - ROW(2, 1, 0, 1, 36 , 10 , 0 , 0 , 0 , 0 ), // #456 {, i8|u8} - ROW(2, 1, 0, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // #457 {r16|m16|mem, r16} - ROW(3, 1, 1, 1, 49 , 50 , 146, 0 , 0 , 0 ), // #458 {xmm, xmm|m128|mem, } - ROW(2, 1, 1, 0, 120, 147, 0 , 0 , 0 , 0 ), // #459 {bnd, mib} - ROW(2, 1, 1, 0, 120, 122, 0 , 0 , 0 , 0 ), // #460 {bnd, mem} - ROW(2, 1, 1, 0, 147, 120, 0 , 0 , 0 , 0 ), // #461 {mib, bnd} - ROW(1, 1, 1, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #462 {} - ROW(2, 1, 1, 2, 38 , 39 , 0 , 0 , 0 , 0 ), // #463 {, } - ROW(1, 1, 1, 0, 122, 0 , 0 , 0 , 0 , 0 ), // #464 {mem} - ROW(1, 1, 1, 0, 31 , 0 , 0 , 0 , 0 , 0 ), // #465 {m64|mem} - ROW(0, 0, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #466 {} - ROW(1, 1, 1, 1, 148, 0 , 0 , 0 , 0 , 0 ), // #467 {} - ROW(3, 1, 1, 0, 49 , 64 , 10 , 0 , 0 , 0 ), // #468 {xmm, xmm|m64|mem, i8|u8} - ROW(3, 1, 1, 0, 49 , 117, 10 , 0 , 0 , 0 ), // #469 {xmm, xmm|m32|mem, i8|u8} - ROW(5, 0, 1, 4, 51 , 40 , 41 , 149, 150, 0 ), // #470 {m128|mem, , , , } - ROW(5, 1, 1, 4, 31 , 38 , 39 , 126, 151, 0 ), // #471 {m64|mem, , , , } - ROW(4, 1, 1, 4, 39 , 151, 126, 38 , 0 , 0 ), // #472 {, , , } - ROW(2, 0, 1, 2, 40 , 41 , 0 , 0 , 0 , 0 ), // #473 {, } - ROW(2, 1, 1, 0, 61 , 50 , 0 , 0 , 0 , 0 ), // #474 {mm, xmm|m128|mem} - ROW(2, 1, 1, 0, 49 , 62 , 0 , 0 , 0 , 0 ), // #475 {xmm, mm|m64|mem} - ROW(2, 1, 1, 0, 61 , 64 , 0 , 0 , 0 , 0 ), // #476 {mm, xmm|m64|mem} - ROW(2, 1, 1, 2, 37 , 36 , 0 , 0 , 0 , 0 ), // #477 {, } - ROW(1, 1, 1, 1, 39 , 0 , 0 , 0 , 0 , 0 ), // #478 {} - ROW(2, 1, 1, 0, 12 , 10 , 0 , 0 , 0 , 0 ), // #479 {i16|u16, i8|u8} - ROW(3, 1, 1, 0, 28 , 49 , 10 , 0 , 0 , 0 ), // #480 {r32|m32|mem, xmm, i8|u8} - ROW(1, 1, 1, 0, 109, 0 , 0 , 0 , 0 , 0 ), // #481 {m80|mem} - ROW(1, 1, 1, 0, 152, 0 , 0 , 0 , 0 , 0 ), // #482 {m16|m32} - ROW(1, 1, 1, 0, 153, 0 , 0 , 0 , 0 , 0 ), // #483 {m16|m32|m64} - ROW(1, 1, 1, 0, 154, 0 , 0 , 0 , 0 , 0 ), // #484 {m32|m64|m80|st} - ROW(1, 1, 1, 0, 21 , 0 , 0 , 0 , 0 , 0 ), // #485 {m16|mem} - ROW(1, 1, 1, 0, 155, 0 , 0 , 0 , 0 , 0 ), // #486 {ax|m16|mem} - ROW(1, 0, 1, 0, 122, 0 , 0 , 0 , 0 , 0 ), // #487 {mem} - ROW(2, 1, 1, 1, 10 , 39 , 0 , 0 , 0 , 0 ), // #488 {i8|u8, } - ROW(2, 1, 1, 0, 156, 157, 0 , 0 , 0 , 0 ), // #489 {al|ax|eax, i8|u8|dx} - ROW(2, 1, 1, 0, 158, 159, 0 , 0 , 0 , 0 ), // #490 {es:[memBase|zdi|m8|m16|m32], dx} - ROW(1, 1, 1, 0, 10 , 0 , 0 , 0 , 0 , 0 ), // #491 {i8|u8} - ROW(0, 1, 0, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #492 {} - ROW(3, 1, 1, 0, 86 , 86 , 86 , 0 , 0 , 0 ), // #493 {k, k, k} - ROW(2, 1, 1, 0, 86 , 86 , 0 , 0 , 0 , 0 ), // #494 {k, k} - ROW(3, 1, 1, 0, 86 , 86 , 10 , 0 , 0 , 0 ), // #495 {k, k, i8|u8} - ROW(1, 1, 1, 1, 160, 0 , 0 , 0 , 0 , 0 ), // #496 {} - ROW(1, 1, 1, 0, 30 , 0 , 0 , 0 , 0 , 0 ), // #497 {m32|mem} - ROW(1, 0, 1, 0, 57 , 0 , 0 , 0 , 0 , 0 ), // #498 {m512|mem} - ROW(1, 1, 1, 0, 27 , 0 , 0 , 0 , 0 , 0 ), // #499 {r16|m16|mem} - ROW(3, 1, 1, 1, 49 , 49 , 161, 0 , 0 , 0 ), // #500 {xmm, xmm, } - ROW(3, 1, 1, 1, 61 , 61 , 162, 0 , 0 , 0 ), // #501 {mm, mm, } - ROW(3, 1, 1, 3, 163, 126, 38 , 0 , 0 , 0 ), // #502 {, , } - ROW(2, 1, 1, 0, 61 , 49 , 0 , 0 , 0 , 0 ), // #503 {mm, xmm} - ROW(2, 1, 1, 0, 6 , 49 , 0 , 0 , 0 , 0 ), // #504 {r32, xmm} - ROW(2, 1, 1, 0, 31 , 61 , 0 , 0 , 0 , 0 ), // #505 {m64|mem, mm} - ROW(2, 1, 1, 0, 49 , 61 , 0 , 0 , 0 , 0 ), // #506 {xmm, mm} - ROW(2, 1, 1, 2, 39 , 126, 0 , 0 , 0 , 0 ), // #507 {, } - ROW(3, 1, 1, 3, 39 , 126, 151, 0 , 0 , 0 ), // #508 {, , } - ROW(2, 1, 1, 0, 164, 156, 0 , 0 , 0 , 0 ), // #509 {u8|dx, al|ax|eax} - ROW(2, 1, 1, 0, 159, 165, 0 , 0 , 0 , 0 ), // #510 {dx, ds:[memBase|zsi|m8|m16|m32]} - ROW(6, 1, 1, 3, 49 , 50 , 10 , 126, 39 , 38 ), // #511 {xmm, xmm|m128|mem, i8|u8, , , } - ROW(6, 1, 1, 3, 49 , 50 , 10 , 146, 39 , 38 ), // #512 {xmm, xmm|m128|mem, i8|u8, , , } - ROW(4, 1, 1, 1, 49 , 50 , 10 , 126, 0 , 0 ), // #513 {xmm, xmm|m128|mem, i8|u8, } - ROW(4, 1, 1, 1, 49 , 50 , 10 , 146, 0 , 0 ), // #514 {xmm, xmm|m128|mem, i8|u8, } - ROW(3, 1, 1, 0, 132, 49 , 10 , 0 , 0 , 0 ), // #515 {r32|m8|mem, xmm, i8|u8} - ROW(3, 0, 1, 0, 29 , 49 , 10 , 0 , 0 , 0 ), // #516 {r64|m64|mem, xmm, i8|u8} - ROW(3, 1, 1, 0, 49 , 132, 10 , 0 , 0 , 0 ), // #517 {xmm, r32|m8|mem, i8|u8} - ROW(3, 1, 1, 0, 49 , 28 , 10 , 0 , 0 , 0 ), // #518 {xmm, r32|m32|mem, i8|u8} - ROW(3, 0, 1, 0, 49 , 29 , 10 , 0 , 0 , 0 ), // #519 {xmm, r64|m64|mem, i8|u8} - ROW(3, 1, 1, 0, 63 , 111, 10 , 0 , 0 , 0 ), // #520 {mm|xmm, r32|m16|mem, i8|u8} - ROW(2, 1, 1, 0, 6 , 63 , 0 , 0 , 0 , 0 ), // #521 {r32, mm|xmm} - ROW(2, 1, 1, 0, 49 , 10 , 0 , 0 , 0 , 0 ), // #522 {xmm, i8|u8} - ROW(1, 1, 1, 0, 106, 0 , 0 , 0 , 0 , 0 ), // #523 {i16} - ROW(1, 0, 1, 0, 136, 0 , 0 , 0 , 0 , 0 ), // #524 {r32|r64} - ROW(3, 1, 1, 3, 38 , 39 , 126, 0 , 0 , 0 ), // #525 {, , } - ROW(1, 1, 1, 0, 1 , 0 , 0 , 0 , 0 , 0 ), // #526 {r8lo|r8hi|m8|mem} - ROW(3, 0, 1, 0, 166, 166, 166, 0 , 0 , 0 ), // #527 {tmm, tmm, tmm} - ROW(2, 0, 1, 0, 166, 167, 0 , 0 , 0 , 0 ), // #528 {tmm, tmem} - ROW(2, 0, 1, 0, 167, 166, 0 , 0 , 0 , 0 ), // #529 {tmem, tmm} - ROW(1, 0, 1, 0, 166, 0 , 0 , 0 , 0 , 0 ), // #530 {tmm} - ROW(3, 1, 1, 2, 6 , 38 , 39 , 0 , 0 , 0 ), // #531 {r32, , } - ROW(6, 1, 1, 0, 55 , 55 , 55 , 55 , 55 , 51 ), // #532 {zmm, zmm, zmm, zmm, zmm, m128|mem} - ROW(6, 1, 1, 0, 49 , 49 , 49 , 49 , 49 , 51 ), // #533 {xmm, xmm, xmm, xmm, xmm, m128|mem} - ROW(3, 1, 1, 0, 49 , 49 , 64 , 0 , 0 , 0 ), // #534 {xmm, xmm, xmm|m64|mem} - ROW(3, 1, 1, 0, 49 , 49 , 119, 0 , 0 , 0 ), // #535 {xmm, xmm, xmm|m16|mem} - ROW(3, 1, 1, 0, 49 , 49 , 117, 0 , 0 , 0 ), // #536 {xmm, xmm, xmm|m32|mem} - ROW(2, 1, 1, 0, 96 , 21 , 0 , 0 , 0 , 0 ), // #537 {xmm|ymm, m16|mem} - ROW(2, 1, 1, 0, 52 , 51 , 0 , 0 , 0 , 0 ), // #538 {ymm, m128|mem} - ROW(2, 1, 1, 0, 168, 64 , 0 , 0 , 0 , 0 ), // #539 {ymm|zmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 168, 51 , 0 , 0 , 0 , 0 ), // #540 {ymm|zmm, m128|mem} - ROW(2, 1, 1, 0, 55 , 54 , 0 , 0 , 0 , 0 ), // #541 {zmm, m256|mem} - ROW(2, 1, 1, 0, 144, 117, 0 , 0 , 0 , 0 ), // #542 {xmm|ymm|zmm, m32|mem|xmm} - ROW(4, 1, 1, 0, 115, 49 , 64 , 10 , 0 , 0 ), // #543 {xmm|k, xmm, xmm|m64|mem, i8|u8} - ROW(4, 1, 1, 0, 86 , 49 , 119, 10 , 0 , 0 ), // #544 {k, xmm, xmm|m16|mem, i8|u8} - ROW(4, 1, 1, 0, 115, 49 , 117, 10 , 0 , 0 ), // #545 {xmm|k, xmm, xmm|m32|mem, i8|u8} - ROW(2, 1, 1, 0, 49 , 169, 0 , 0 , 0 , 0 ), // #546 {xmm, xmm|m128|ymm|m256|zmm|m512} - ROW(3, 1, 1, 0, 50 , 168, 10 , 0 , 0 , 0 ), // #547 {xmm|m128|mem, ymm|zmm, i8|u8} - ROW(4, 1, 1, 0, 49 , 49 , 64 , 10 , 0 , 0 ), // #548 {xmm, xmm, xmm|m64|mem, i8|u8} - ROW(4, 1, 1, 0, 49 , 49 , 117, 10 , 0 , 0 ), // #549 {xmm, xmm, xmm|m32|mem, i8|u8} - ROW(3, 1, 1, 0, 86 , 169, 10 , 0 , 0 , 0 ), // #550 {k, xmm|m128|ymm|m256|zmm|m512, i8|u8} - ROW(3, 1, 1, 0, 86 , 64 , 10 , 0 , 0 , 0 ), // #551 {k, xmm|m64|mem, i8|u8} - ROW(3, 1, 1, 0, 86 , 119, 10 , 0 , 0 , 0 ), // #552 {k, xmm|m16|mem, i8|u8} - ROW(3, 1, 1, 0, 86 , 117, 10 , 0 , 0 , 0 ), // #553 {k, xmm|m32|mem, i8|u8} - ROW(1, 1, 1, 0, 72 , 0 , 0 , 0 , 0 , 0 ), // #554 {vm32y} - ROW(1, 1, 1, 0, 73 , 0 , 0 , 0 , 0 , 0 ), // #555 {vm32z} - ROW(1, 1, 1, 0, 76 , 0 , 0 , 0 , 0 , 0 ), // #556 {vm64z} - ROW(4, 1, 1, 0, 49 , 49 , 119, 10 , 0 , 0 ), // #557 {xmm, xmm, xmm|m16|mem, i8|u8} - ROW(4, 1, 1, 0, 55 , 55 , 53 , 10 , 0 , 0 ), // #558 {zmm, zmm, ymm|m256|mem, i8|u8} - ROW(2, 1, 1, 0, 6 , 96 , 0 , 0 , 0 , 0 ), // #559 {r32, xmm|ymm} - ROW(2, 1, 1, 0, 144, 170, 0 , 0 , 0 , 0 ), // #560 {xmm|ymm|zmm, xmm|m8|mem|r32} - ROW(2, 1, 1, 0, 144, 171, 0 , 0 , 0 , 0 ), // #561 {xmm|ymm|zmm, xmm|m32|mem|r32} - ROW(2, 1, 1, 0, 144, 86 , 0 , 0 , 0 , 0 ), // #562 {xmm|ymm|zmm, k} - ROW(2, 1, 1, 0, 144, 172, 0 , 0 , 0 , 0 ), // #563 {xmm|ymm|zmm, xmm|m16|mem|r32} - ROW(3, 1, 1, 0, 111, 49 , 10 , 0 , 0 , 0 ), // #564 {r32|m16|mem, xmm, i8|u8} - ROW(4, 1, 1, 0, 49 , 49 , 132, 10 , 0 , 0 ), // #565 {xmm, xmm, r32|m8|mem, i8|u8} - ROW(4, 1, 1, 0, 49 , 49 , 28 , 10 , 0 , 0 ), // #566 {xmm, xmm, r32|m32|mem, i8|u8} - ROW(4, 0, 1, 0, 49 , 49 , 29 , 10 , 0 , 0 ), // #567 {xmm, xmm, r64|m64|mem, i8|u8} - ROW(4, 1, 1, 0, 49 , 49 , 111, 10 , 0 , 0 ), // #568 {xmm, xmm, r32|m16|mem, i8|u8} - ROW(2, 1, 1, 0, 86 , 144, 0 , 0 , 0 , 0 ), // #569 {k, xmm|ymm|zmm} - ROW(2, 1, 1, 0, 52 , 49 , 0 , 0 , 0 , 0 ), // #570 {ymm, xmm} - ROW(2, 1, 1, 0, 52 , 52 , 0 , 0 , 0 , 0 ), // #571 {ymm, ymm} - ROW(3, 1, 1, 0, 52 , 52 , 49 , 0 , 0 , 0 ), // #572 {ymm, ymm, xmm} - ROW(3, 1, 1, 2, 122, 38 , 39 , 0 , 0 , 0 ), // #573 {mem, , } - ROW(3, 0, 1, 2, 122, 38 , 39 , 0 , 0 , 0 ) // #574 {mem, , } + ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #444 {} + ROW(1, 1, 1, 0, 144, 0 , 0 , 0 , 0 , 0 ), // {u16} + ROW(3, 1, 1, 0, 6 , 25 , 10 , 0 , 0 , 0 ), // #446 {r32, r32|m32|mem, i8|u8} + ROW(3, 0, 1, 0, 8 , 26 , 10 , 0 , 0 , 0 ), // {r64, r64|m64|mem, i8|u8} + ROW(1, 1, 1, 0, 145, 0 , 0 , 0 , 0 , 0 ), // #448 {r16|m16|mem|r32} + ROW(1, 0, 1, 0, 146, 0 , 0 , 0 , 0 , 0 ), // {r64|m16|mem} + ROW(1, 1, 0, 0, 147, 0 , 0 , 0 , 0 , 0 ), // #450 {ds:[mem|memBase]} + ROW(1, 0, 1, 0, 147, 0 , 0 , 0 , 0 , 0 ), // {ds:[mem|memBase]} + ROW(4, 1, 1, 0, 55 , 55 , 56 , 55 , 0 , 0 ), // #452 {xmm, xmm, xmm|m128|mem, xmm} + ROW(4, 1, 1, 0, 57 , 57 , 58 , 57 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem, ymm} + ROW(2, 1, 1, 0, 55 , 148, 0 , 0 , 0 , 0 ), // #454 {xmm, xmm|m128|ymm|m256} + ROW(2, 1, 1, 0, 57 , 62 , 0 , 0 , 0 , 0 ), // {ymm, zmm|m512|mem} + ROW(2, 1, 1, 0, 6 , 125, 0 , 0 , 0 , 0 ), // #456 {r32, xmm|m16|mem} + ROW(2, 0, 1, 0, 8 , 125, 0 , 0 , 0 , 0 ), // {r64, xmm|m16|mem} + ROW(3, 1, 1, 0, 55 , 55 , 25 , 0 , 0 , 0 ), // #458 {xmm, xmm, r32|m32|mem} + ROW(3, 0, 1, 0, 55 , 55 , 26 , 0 , 0 , 0 ), // {xmm, xmm, r64|m64|mem} + ROW(3, 1, 1, 0, 55 , 55 , 13 , 0 , 0 , 0 ), // #460 {xmm, xmm, r32|m32} + ROW(3, 0, 1, 0, 55 , 55 , 15 , 0 , 0 , 0 ), // {xmm, xmm, r64|m64} + ROW(4, 1, 1, 0, 55 , 55 , 55 , 70 , 0 , 0 ), // #462 {xmm, xmm, xmm, xmm|m64|mem} + ROW(4, 1, 1, 0, 55 , 55 , 31 , 55 , 0 , 0 ), // {xmm, xmm, m64|mem, xmm} + ROW(4, 1, 1, 0, 55 , 55 , 55 , 123, 0 , 0 ), // #464 {xmm, xmm, xmm, xmm|m32|mem} + ROW(4, 1, 1, 0, 55 , 55 , 30 , 55 , 0 , 0 ), // {xmm, xmm, m32|mem, xmm} + ROW(4, 1, 1, 0, 57 , 57 , 56 , 10 , 0 , 0 ), // #466 {ymm, ymm, xmm|m128|mem, i8|u8} + ROW(4, 1, 1, 0, 61 , 61 , 56 , 10 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem, i8|u8} + ROW(1, 1, 0, 1, 45 , 0 , 0 , 0 , 0 , 0 ), // #468 {} + ROW(1, 0, 1, 1, 47 , 0 , 0 , 0 , 0 , 0 ), // #469 {} + ROW(2, 1, 1, 0, 25 , 55 , 0 , 0 , 0 , 0 ), // #470 {r32|m32|mem, xmm} + ROW(2, 1, 1, 0, 55 , 25 , 0 , 0 , 0 , 0 ), // {xmm, r32|m32|mem} + ROW(2, 1, 1, 0, 117, 55 , 0 , 0 , 0 , 0 ), // #472 {r32|m16|mem, xmm} + ROW(2, 1, 1, 0, 55 , 117, 0 , 0 , 0 , 0 ), // {xmm, r32|m16|mem} + ROW(2, 1, 0, 0, 25 , 6 , 0 , 0 , 0 , 0 ), // #474 {r32|m32|mem, r32} + ROW(2, 0, 1, 0, 26 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} + ROW(2, 1, 0, 0, 6 , 25 , 0 , 0 , 0 , 0 ), // #476 {r32, r32|m32|mem} + ROW(2, 0, 1, 0, 8 , 26 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem} + ROW(2, 1, 1, 0, 149, 70 , 0 , 0 , 0 , 0 ), // #478 {xmm|ymm|zmm, xmm|m64|mem} + ROW(2, 0, 1, 0, 149, 8 , 0 , 0 , 0 , 0 ), // {xmm|ymm|zmm, r64} + ROW(3, 1, 1, 0, 55 , 55 , 64 , 0 , 0 , 0 ), // #480 {xmm, xmm, xmm|m128|mem|i8|u8} + ROW(3, 1, 1, 0, 55 , 59 , 150, 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8|xmm} + ROW(2, 1, 1, 0, 77 , 102, 0 , 0 , 0 , 0 ), // #482 {vm32x, xmm|ymm} + ROW(2, 1, 1, 0, 78 , 61 , 0 , 0 , 0 , 0 ), // {vm32y, zmm} + ROW(2, 1, 1, 0, 124, 55 , 0 , 0 , 0 , 0 ), // #484 {vm64x|vm64y, xmm} + ROW(2, 1, 1, 0, 82 , 57 , 0 , 0 , 0 , 0 ), // {vm64z, ymm} + ROW(3, 1, 1, 0, 55 , 55 , 56 , 0 , 0 , 0 ), // #486 {xmm, xmm, xmm|m128|mem} + ROW(3, 1, 1, 0, 55 , 59 , 55 , 0 , 0 , 0 ), // {xmm, m128|mem, xmm} + ROW(1, 1, 0, 1, 42 , 0 , 0 , 0 , 0 , 0 ), // #488 {} + ROW(2, 1, 0, 1, 42 , 10 , 0 , 0 , 0 , 0 ), // #489 {, i8|u8} + ROW(2, 1, 0, 0, 24 , 4 , 0 , 0 , 0 , 0 ), // #490 {r16|m16|mem, r16} + ROW(3, 1, 1, 1, 55 , 56 , 151, 0 , 0 , 0 ), // #491 {xmm, xmm|m128|mem, } + ROW(2, 1, 1, 0, 126, 152, 0 , 0 , 0 , 0 ), // #492 {bnd, mib} + ROW(2, 1, 1, 0, 126, 128, 0 , 0 , 0 , 0 ), // #493 {bnd, mem} + ROW(2, 1, 1, 0, 152, 126, 0 , 0 , 0 , 0 ), // #494 {mib, bnd} + ROW(1, 1, 1, 1, 42 , 0 , 0 , 0 , 0 , 0 ), // #495 {} + ROW(2, 1, 1, 2, 44 , 45 , 0 , 0 , 0 , 0 ), // #496 {, } + ROW(1, 1, 1, 0, 128, 0 , 0 , 0 , 0 , 0 ), // #497 {mem} + ROW(1, 1, 1, 0, 31 , 0 , 0 , 0 , 0 , 0 ), // #498 {m64|mem} + ROW(0, 0, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #499 {} + ROW(1, 1, 1, 1, 153, 0 , 0 , 0 , 0 , 0 ), // #500 {} + ROW(3, 1, 1, 0, 55 , 70 , 10 , 0 , 0 , 0 ), // #501 {xmm, xmm|m64|mem, i8|u8} + ROW(3, 1, 1, 0, 55 , 123, 10 , 0 , 0 , 0 ), // #502 {xmm, xmm|m32|mem, i8|u8} + ROW(5, 0, 1, 4, 59 , 46 , 47 , 154, 155, 0 ), // #503 {m128|mem, , , , } + ROW(5, 1, 1, 4, 31 , 44 , 45 , 119, 156, 0 ), // #504 {m64|mem, , , , } + ROW(4, 1, 1, 4, 45 , 156, 119, 44 , 0 , 0 ), // #505 {, , , } + ROW(2, 0, 1, 2, 46 , 47 , 0 , 0 , 0 , 0 ), // #506 {, } + ROW(2, 1, 1, 0, 67 , 56 , 0 , 0 , 0 , 0 ), // #507 {mm, xmm|m128|mem} + ROW(2, 1, 1, 0, 55 , 68 , 0 , 0 , 0 , 0 ), // #508 {xmm, mm|m64|mem} + ROW(2, 1, 1, 0, 67 , 70 , 0 , 0 , 0 , 0 ), // #509 {mm, xmm|m64|mem} + ROW(2, 1, 1, 2, 43 , 42 , 0 , 0 , 0 , 0 ), // #510 {, } + ROW(1, 1, 1, 1, 45 , 0 , 0 , 0 , 0 , 0 ), // #511 {} + ROW(2, 1, 1, 0, 12 , 10 , 0 , 0 , 0 , 0 ), // #512 {i16|u16, i8|u8} + ROW(3, 1, 1, 0, 25 , 55 , 10 , 0 , 0 , 0 ), // #513 {r32|m32|mem, xmm, i8|u8} + ROW(1, 1, 1, 0, 115, 0 , 0 , 0 , 0 , 0 ), // #514 {m80|mem} + ROW(1, 1, 1, 0, 39 , 0 , 0 , 0 , 0 , 0 ), // #515 {m16|m32} + ROW(1, 1, 1, 0, 157, 0 , 0 , 0 , 0 , 0 ), // #516 {m16|m32|m64} + ROW(1, 1, 1, 0, 158, 0 , 0 , 0 , 0 , 0 ), // #517 {m32|m64|m80|st} + ROW(1, 1, 1, 0, 21 , 0 , 0 , 0 , 0 , 0 ), // #518 {m16|mem} + ROW(1, 1, 1, 0, 159, 0 , 0 , 0 , 0 , 0 ), // #519 {ax|m16|mem} + ROW(1, 0, 1, 0, 128, 0 , 0 , 0 , 0 , 0 ), // #520 {mem} + ROW(2, 1, 1, 2, 45 , 156, 0 , 0 , 0 , 0 ), // #521 {, } + ROW(2, 1, 1, 1, 10 , 45 , 0 , 0 , 0 , 0 ), // #522 {i8|u8, } + ROW(2, 1, 1, 0, 160, 161, 0 , 0 , 0 , 0 ), // #523 {al|ax|eax, i8|u8|dx} + ROW(2, 1, 1, 0, 162, 163, 0 , 0 , 0 , 0 ), // #524 {es:[memBase|zdi|m8|m16|m32], dx} + ROW(1, 1, 1, 0, 10 , 0 , 0 , 0 , 0 , 0 ), // #525 {i8|u8} + ROW(0, 1, 0, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #526 {} + ROW(3, 1, 1, 0, 92 , 92 , 92 , 0 , 0 , 0 ), // #527 {k, k, k} + ROW(2, 1, 1, 0, 92 , 92 , 0 , 0 , 0 , 0 ), // #528 {k, k} + ROW(3, 1, 1, 0, 92 , 92 , 10 , 0 , 0 , 0 ), // #529 {k, k, i8|u8} + ROW(1, 1, 1, 1, 164, 0 , 0 , 0 , 0 , 0 ), // #530 {} + ROW(1, 1, 1, 0, 30 , 0 , 0 , 0 , 0 , 0 ), // #531 {m32|mem} + ROW(1, 0, 1, 0, 63 , 0 , 0 , 0 , 0 , 0 ), // #532 {m512|mem} + ROW(1, 1, 1, 0, 24 , 0 , 0 , 0 , 0 , 0 ), // #533 {r16|m16|mem} + ROW(3, 1, 1, 1, 55 , 55 , 165, 0 , 0 , 0 ), // #534 {xmm, xmm, } + ROW(3, 1, 1, 1, 67 , 67 , 166, 0 , 0 , 0 ), // #535 {mm, mm, } + ROW(3, 1, 1, 3, 167, 119, 44 , 0 , 0 , 0 ), // #536 {, , } + ROW(2, 1, 1, 0, 67 , 55 , 0 , 0 , 0 , 0 ), // #537 {mm, xmm} + ROW(2, 1, 1, 0, 6 , 55 , 0 , 0 , 0 , 0 ), // #538 {r32, xmm} + ROW(2, 1, 1, 0, 31 , 67 , 0 , 0 , 0 , 0 ), // #539 {m64|mem, mm} + ROW(2, 1, 1, 0, 55 , 67 , 0 , 0 , 0 , 0 ), // #540 {xmm, mm} + ROW(2, 1, 1, 2, 45 , 119, 0 , 0 , 0 , 0 ), // #541 {, } + ROW(3, 1, 1, 3, 45 , 119, 156, 0 , 0 , 0 ), // #542 {, , } + ROW(2, 1, 1, 0, 161, 160, 0 , 0 , 0 , 0 ), // #543 {i8|u8|dx, al|ax|eax} + ROW(2, 1, 1, 0, 163, 168, 0 , 0 , 0 , 0 ), // #544 {dx, ds:[memBase|zsi|m8|m16|m32]} + ROW(6, 1, 1, 3, 55 , 56 , 10 , 119, 45 , 44 ), // #545 {xmm, xmm|m128|mem, i8|u8, , , } + ROW(6, 1, 1, 3, 55 , 56 , 10 , 151, 45 , 44 ), // #546 {xmm, xmm|m128|mem, i8|u8, , , } + ROW(4, 1, 1, 1, 55 , 56 , 10 , 119, 0 , 0 ), // #547 {xmm, xmm|m128|mem, i8|u8, } + ROW(4, 1, 1, 1, 55 , 56 , 10 , 151, 0 , 0 ), // #548 {xmm, xmm|m128|mem, i8|u8, } + ROW(3, 1, 1, 0, 137, 55 , 10 , 0 , 0 , 0 ), // #549 {r32|m8|mem, xmm, i8|u8} + ROW(3, 0, 1, 0, 26 , 55 , 10 , 0 , 0 , 0 ), // #550 {r64|m64|mem, xmm, i8|u8} + ROW(3, 1, 1, 0, 55 , 137, 10 , 0 , 0 , 0 ), // #551 {xmm, r32|m8|mem, i8|u8} + ROW(3, 1, 1, 0, 55 , 25 , 10 , 0 , 0 , 0 ), // #552 {xmm, r32|m32|mem, i8|u8} + ROW(3, 0, 1, 0, 55 , 26 , 10 , 0 , 0 , 0 ), // #553 {xmm, r64|m64|mem, i8|u8} + ROW(3, 1, 1, 0, 69 , 117, 10 , 0 , 0 , 0 ), // #554 {mm|xmm, r32|m16|mem, i8|u8} + ROW(2, 1, 1, 0, 6 , 69 , 0 , 0 , 0 , 0 ), // #555 {r32, mm|xmm} + ROW(2, 1, 1, 0, 55 , 10 , 0 , 0 , 0 , 0 ), // #556 {xmm, i8|u8} + ROW(1, 1, 1, 0, 12 , 0 , 0 , 0 , 0 , 0 ), // #557 {i16|u16} + ROW(1, 0, 1, 0, 141, 0 , 0 , 0 , 0 , 0 ), // #558 {r32|r64} + ROW(1, 1, 1, 0, 1 , 0 , 0 , 0 , 0 , 0 ), // #559 {r8lo|r8hi|m8|mem} + ROW(3, 0, 1, 0, 169, 169, 169, 0 , 0 , 0 ), // #560 {tmm, tmm, tmm} + ROW(2, 0, 1, 0, 169, 170, 0 , 0 , 0 , 0 ), // #561 {tmm, tmem} + ROW(2, 0, 1, 0, 170, 169, 0 , 0 , 0 , 0 ), // #562 {tmem, tmm} + ROW(1, 0, 1, 0, 169, 0 , 0 , 0 , 0 , 0 ), // #563 {tmm} + ROW(3, 1, 1, 2, 6 , 44 , 45 , 0 , 0 , 0 ), // #564 {r32, , } + ROW(3, 1, 1, 0, 55 , 55 , 70 , 0 , 0 , 0 ), // #565 {xmm, xmm, xmm|m64|mem} + ROW(3, 1, 1, 0, 55 , 55 , 125, 0 , 0 , 0 ), // #566 {xmm, xmm, xmm|m16|mem} + ROW(3, 1, 1, 0, 55 , 55 , 123, 0 , 0 , 0 ), // #567 {xmm, xmm, xmm|m32|mem} + ROW(2, 1, 1, 0, 102, 21 , 0 , 0 , 0 , 0 ), // #568 {xmm|ymm, m16|mem} + ROW(2, 1, 1, 0, 57 , 59 , 0 , 0 , 0 , 0 ), // #569 {ymm, m128|mem} + ROW(2, 1, 1, 0, 171, 70 , 0 , 0 , 0 , 0 ), // #570 {ymm|zmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 171, 59 , 0 , 0 , 0 , 0 ), // #571 {ymm|zmm, m128|mem} + ROW(2, 1, 1, 0, 61 , 60 , 0 , 0 , 0 , 0 ), // #572 {zmm, m256|mem} + ROW(2, 1, 1, 0, 149, 123, 0 , 0 , 0 , 0 ), // #573 {xmm|ymm|zmm, m32|mem|xmm} + ROW(4, 1, 1, 0, 121, 55 , 70 , 10 , 0 , 0 ), // #574 {xmm|k, xmm, xmm|m64|mem, i8|u8} + ROW(4, 1, 1, 0, 92 , 55 , 125, 10 , 0 , 0 ), // #575 {k, xmm, xmm|m16|mem, i8|u8} + ROW(4, 1, 1, 0, 121, 55 , 123, 10 , 0 , 0 ), // #576 {xmm|k, xmm, xmm|m32|mem, i8|u8} + ROW(2, 1, 1, 0, 55 , 172, 0 , 0 , 0 , 0 ), // #577 {xmm, xmm|m128|ymm|m256|zmm|m512} + ROW(3, 1, 1, 0, 56 , 171, 10 , 0 , 0 , 0 ), // #578 {xmm|m128|mem, ymm|zmm, i8|u8} + ROW(4, 1, 1, 0, 55 , 55 , 70 , 10 , 0 , 0 ), // #579 {xmm, xmm, xmm|m64|mem, i8|u8} + ROW(4, 1, 1, 0, 55 , 55 , 123, 10 , 0 , 0 ), // #580 {xmm, xmm, xmm|m32|mem, i8|u8} + ROW(3, 1, 1, 0, 92 , 172, 10 , 0 , 0 , 0 ), // #581 {k, xmm|m128|ymm|m256|zmm|m512, i8|u8} + ROW(3, 1, 1, 0, 92 , 70 , 10 , 0 , 0 , 0 ), // #582 {k, xmm|m64|mem, i8|u8} + ROW(3, 1, 1, 0, 92 , 125, 10 , 0 , 0 , 0 ), // #583 {k, xmm|m16|mem, i8|u8} + ROW(3, 1, 1, 0, 92 , 123, 10 , 0 , 0 , 0 ), // #584 {k, xmm|m32|mem, i8|u8} + ROW(4, 1, 1, 0, 55 , 55 , 125, 10 , 0 , 0 ), // #585 {xmm, xmm, xmm|m16|mem, i8|u8} + ROW(4, 1, 1, 0, 61 , 61 , 58 , 10 , 0 , 0 ), // #586 {zmm, zmm, ymm|m256|mem, i8|u8} + ROW(2, 1, 1, 0, 6 , 102, 0 , 0 , 0 , 0 ), // #587 {r32, xmm|ymm} + ROW(2, 1, 1, 0, 149, 173, 0 , 0 , 0 , 0 ), // #588 {xmm|ymm|zmm, xmm|m8|mem|r32} + ROW(2, 1, 1, 0, 149, 174, 0 , 0 , 0 , 0 ), // #589 {xmm|ymm|zmm, xmm|m32|mem|r32} + ROW(2, 1, 1, 0, 149, 92 , 0 , 0 , 0 , 0 ), // #590 {xmm|ymm|zmm, k} + ROW(2, 1, 1, 0, 149, 175, 0 , 0 , 0 , 0 ), // #591 {xmm|ymm|zmm, xmm|m16|mem|r32} + ROW(3, 1, 1, 0, 117, 55 , 10 , 0 , 0 , 0 ), // #592 {r32|m16|mem, xmm, i8|u8} + ROW(4, 1, 1, 0, 55 , 55 , 137, 10 , 0 , 0 ), // #593 {xmm, xmm, r32|m8|mem, i8|u8} + ROW(4, 1, 1, 0, 55 , 55 , 25 , 10 , 0 , 0 ), // #594 {xmm, xmm, r32|m32|mem, i8|u8} + ROW(4, 0, 1, 0, 55 , 55 , 26 , 10 , 0 , 0 ), // #595 {xmm, xmm, r64|m64|mem, i8|u8} + ROW(4, 1, 1, 0, 55 , 55 , 117, 10 , 0 , 0 ), // #596 {xmm, xmm, r32|m16|mem, i8|u8} + ROW(2, 1, 1, 0, 92 , 149, 0 , 0 , 0 , 0 ), // #597 {k, xmm|ymm|zmm} + ROW(2, 1, 1, 0, 57 , 55 , 0 , 0 , 0 , 0 ), // #598 {ymm, xmm} + ROW(2, 1, 1, 0, 57 , 57 , 0 , 0 , 0 , 0 ), // #599 {ymm, ymm} + ROW(3, 1, 1, 0, 57 , 57 , 55 , 0 , 0 , 0 ), // #600 {ymm, ymm, xmm} + ROW(3, 1, 1, 2, 128, 44 , 45 , 0 , 0 , 0 ), // #601 {mem, , } + ROW(3, 0, 1, 2, 128, 44 , 45 , 0 , 0 , 0 ) // #602 {mem, , } }; #undef ROW @@ -5323,25 +5334,31 @@ const InstDB::OpSignature InstDB::_opSignatureTable[] = { ROW(F(ImmI32) | F(ImmU32), 0x00), ROW(F(RegGpq) | F(Mem64), 0x00), ROW(F(ImmI32), 0x00), - ROW(F(RegSReg) | F(RegCReg) | F(RegDReg) | F(MemUnspecified) | F(Mem64) | F(ImmI64) | F(ImmU64), 0x00), ROW(F(MemUnspecified) | F(Mem8), 0x00), ROW(F(RegSReg) | F(MemUnspecified) | F(Mem16), 0x00), ROW(F(RegSReg) | F(MemUnspecified) | F(Mem32), 0x00), + ROW(F(RegSReg) | F(RegCReg) | F(RegDReg) | F(MemUnspecified) | F(Mem64) | F(ImmI64) | F(ImmU64), 0x00), ROW(F(MemUnspecified) | F(Mem16), 0x00), ROW(F(RegSReg), 0x00), ROW(F(RegCReg) | F(RegDReg), 0x00), - ROW(F(ImmI8) | F(ImmI32), 0x00), - ROW(F(RegGpw) | F(RegGpd) | F(Mem16) | F(Mem32), 0x00), - ROW(F(ImmI8), 0x00), ROW(F(RegGpw) | F(MemUnspecified) | F(Mem16), 0x00), ROW(F(RegGpd) | F(MemUnspecified) | F(Mem32), 0x00), ROW(F(RegGpq) | F(MemUnspecified) | F(Mem64), 0x00), + ROW(F(RegGpw) | F(RegGpd) | F(Mem16) | F(Mem32), 0x00), + ROW(F(ImmI8), 0x00), + ROW(F(ImmI8) | F(ImmI32), 0x00), ROW(F(MemUnspecified) | F(Mem32), 0x00), ROW(F(MemUnspecified) | F(Mem64), 0x00), - ROW(F(RegGpbLo) | F(RegGpbHi) | F(RegGpw) | F(RegGpd) | F(Mem8) | F(Mem16) | F(Mem32), 0x00), - ROW(F(RegGpq) | F(MemUnspecified) | F(Mem64) | F(ImmI8) | F(ImmU8) | F(ImmI32) | F(ImmU32), 0x00), + ROW(F(RegGpq) | F(MemUnspecified) | F(Mem64) | F(ImmI8) | F(ImmI32) | F(ImmU32), 0x00), ROW(F(Mem64), 0x00), - ROW(F(ImmI8) | F(ImmU8) | F(ImmI32), 0x00), + ROW(F(MemUnspecified) | F(Mem8) | F(ImmI8) | F(ImmU8), 0x00), + ROW(F(MemUnspecified) | F(Mem16) | F(ImmI8) | F(ImmI16) | F(ImmU16), 0x00), + ROW(F(MemUnspecified) | F(Mem32) | F(ImmI8) | F(ImmI32) | F(ImmU32), 0x00), + ROW(F(MemUnspecified) | F(Mem64) | F(ImmI8) | F(ImmI32), 0x00), + ROW(F(Mem8), 0x00), + ROW(F(Mem16) | F(Mem32), 0x00), + ROW(F(Mem16), 0x00), + ROW(F(Mem32), 0x00), ROW(F(RegGpw) | F(FlagImplicit), 0x01), ROW(F(RegGpw) | F(FlagImplicit), 0x04), ROW(F(RegGpd) | F(FlagImplicit), 0x04), @@ -5357,9 +5374,9 @@ const InstDB::OpSignature InstDB::_opSignatureTable[] = { ROW(F(RegGpq), 0x01), ROW(F(RegXmm), 0x00), ROW(F(RegXmm) | F(MemUnspecified) | F(Mem128), 0x00), - ROW(F(MemUnspecified) | F(Mem128), 0x00), ROW(F(RegYmm), 0x00), ROW(F(RegYmm) | F(MemUnspecified) | F(Mem256), 0x00), + ROW(F(MemUnspecified) | F(Mem128), 0x00), ROW(F(MemUnspecified) | F(Mem256), 0x00), ROW(F(RegZmm), 0x00), ROW(F(RegZmm) | F(MemUnspecified) | F(Mem512), 0x00), @@ -5373,7 +5390,7 @@ const InstDB::OpSignature InstDB::_opSignatureTable[] = { ROW(F(RegXmm) | F(MemUnspecified) | F(Mem64), 0x00), ROW(F(RegSReg), 0x1A), ROW(F(RegSReg), 0x60), - ROW(F(RegGpw) | F(Mem16) | F(ImmI8), 0x00), + ROW(F(RegGpw) | F(Mem16) | F(ImmI8) | F(ImmU8) | F(ImmI16) | F(ImmU16), 0x00), ROW(F(RegGpd) | F(Mem32) | F(ImmI32) | F(ImmU32), 0x00), ROW(F(RegGpq) | F(Mem64) | F(ImmI32), 0x00), ROW(F(RegSReg), 0x1E), @@ -5407,19 +5424,19 @@ const InstDB::OpSignature InstDB::_opSignatureTable[] = { ROW(F(RegGpw) | F(RegGpd) | F(MemUnspecified) | F(Mem16) | F(Mem32) | F(ImmI32) | F(ImmI64) | F(Rel32), 0x00), ROW(F(ImmI32) | F(ImmI64) | F(Rel32), 0x00), ROW(F(RegGpw) | F(RegGpd), 0x00), + ROW(F(RegGpbLo) | F(RegGpbHi) | F(RegGpw) | F(RegGpd) | F(Mem8) | F(Mem16) | F(Mem32), 0x00), ROW(F(Mem32) | F(Mem64), 0x00), ROW(F(RegSt), 0x01), ROW(F(RegSt), 0x00), ROW(F(ImmI32) | F(ImmI64) | F(Rel8) | F(Rel32), 0x00), ROW(F(RegGpd) | F(Mem32) | F(ImmI32) | F(ImmI64) | F(Rel32), 0x00), - ROW(F(ImmI16), 0x00), - ROW(F(ImmI16) | F(ImmI32), 0x00), + ROW(F(ImmI16) | F(ImmU16) | F(ImmI32) | F(ImmU32), 0x00), ROW(F(MemUnspecified) | F(Mem32) | F(Mem48), 0x00), ROW(F(MemUnspecified) | F(Mem80), 0x00), ROW(F(MemUnspecified) | F(Mem48), 0x00), ROW(F(RegGpd) | F(MemUnspecified) | F(Mem16), 0x00), ROW(F(RegGpbLo) | F(RegGpbHi) | F(RegGpw) | F(Mem8) | F(Mem16), 0x00), - ROW(F(RegGpbLo) | F(RegGpw) | F(Mem8) | F(Mem16), 0x00), + ROW(F(RegGpd) | F(FlagImplicit), 0x02), ROW(F(RegGpbLo) | F(ImmI8) | F(ImmU8), 0x02), ROW(F(RegXmm) | F(RegKReg), 0x00), ROW(F(RegYmm) | F(RegKReg), 0x00), @@ -5429,10 +5446,9 @@ const InstDB::OpSignature InstDB::_opSignatureTable[] = { ROW(F(RegBnd), 0x00), ROW(F(RegBnd) | F(MemUnspecified), 0x00), ROW(F(MemUnspecified), 0x00), - ROW(F(RegGpbLo) | F(RegGpq) | F(Mem8) | F(Mem64), 0x00), + ROW(F(RegGpbLo) | F(RegGpbHi) | F(RegGpq) | F(Mem8) | F(Mem64), 0x00), ROW(F(MemUnspecified) | F(Mem512) | F(FlagMemBase) | F(FlagMemEs), 0x00), ROW(F(RegSt) | F(Mem32) | F(Mem64), 0x00), - ROW(F(RegGpd) | F(FlagImplicit), 0x02), ROW(F(RegGpd) | F(RegGpq) | F(FlagImplicit), 0x01), ROW(F(RegGpw) | F(RegGpd) | F(FlagImplicit), 0x02), ROW(F(ImmI32) | F(ImmI64) | F(Rel8), 0x00), @@ -5458,7 +5474,6 @@ const InstDB::OpSignature InstDB::_opSignatureTable[] = { ROW(F(RegGpq) | F(FlagImplicit), 0x02), ROW(F(RegGpq) | F(FlagImplicit), 0x08), ROW(F(RegGpd) | F(FlagImplicit), 0x08), - ROW(F(Mem16) | F(Mem32), 0x00), ROW(F(Mem16) | F(Mem32) | F(Mem64), 0x00), ROW(F(RegSt) | F(Mem32) | F(Mem64) | F(Mem80), 0x00), ROW(F(RegGpw) | F(MemUnspecified) | F(Mem16), 0x01), @@ -5470,7 +5485,6 @@ const InstDB::OpSignature InstDB::_opSignatureTable[] = { ROW(F(MemUnspecified) | F(Mem128) | F(FlagMemBase) | F(FlagMemDs) | F(FlagImplicit), 0x80), ROW(F(MemUnspecified) | F(Mem64) | F(FlagMemBase) | F(FlagMemDs) | F(FlagImplicit), 0x80), ROW(F(MemUnspecified) | F(FlagMemBase) | F(FlagMemDs) | F(FlagImplicit), 0x01), - ROW(F(RegGpw) | F(ImmU8), 0x04), ROW(F(Mem8) | F(Mem16) | F(Mem32) | F(FlagMemBase) | F(FlagMemDs), 0x40), ROW(F(RegTmm), 0x00), ROW(F(MemUnspecified) | F(FlagTMem), 0x00), @@ -5496,168 +5510,161 @@ const uint8_t InstDB::rwInfoIndexA[Inst::_kIdCount] = { 5, 5, 5, 2, 9, 2, 0, 10, 10, 10, 10, 10, 0, 0, 0, 0, 10, 10, 10, 10, 10, 11, 11, 11, 12, 12, 13, 14, 15, 10, 10, 0, 16, 17, 17, 17, 0, 0, 0, 18, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, - 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 20, 0, 0, 0, 0, 0, 0, 0, 21, 22, 0, 23, 24, 25, 8, 26, 26, - 26, 25, 27, 8, 25, 28, 29, 30, 31, 32, 33, 34, 26, 26, 8, 28, 29, 34, 35, 0, - 0, 0, 0, 36, 5, 5, 6, 7, 0, 0, 0, 0, 0, 37, 37, 0, 0, 38, 0, 0, 39, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 39, 0, 39, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 39, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 39, 0, 39, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 5, 5, 0, 40, 5, 5, 36, - 41, 42, 0, 0, 0, 43, 0, 38, 0, 0, 0, 0, 44, 0, 45, 0, 44, 44, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 46, 0, 0, 0, 0, 0, 0, 0, 0, 0, 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111, 10, 10, 10, 107, 0, 77, 107, - 10, 107, 10, 109, 108, 0, 29, 0, 29, 0, 112, 0, 112, 0, 0, 0, 0, 0, 34, 34, 108, - 10, 108, 10, 110, 111, 110, 111, 10, 10, 10, 107, 10, 107, 29, 29, 112, 112, - 34, 34, 107, 77, 10, 10, 109, 108, 0, 0, 0, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 113, 113, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 4, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 0, 0, 0, 0, 0, 0, + 0, 21, 22, 0, 23, 24, 25, 8, 26, 26, 26, 25, 27, 8, 25, 28, 29, 30, 31, 32, 33, + 34, 26, 26, 8, 28, 29, 34, 35, 0, 0, 0, 0, 36, 5, 5, 6, 7, 0, 0, 0, 0, 0, 37, + 37, 0, 0, 38, 0, 0, 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 39, 0, 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 39, 0, 39, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 40, 0, 0, 5, 5, 5, 0, 41, 5, 5, 36, 42, 43, 0, 0, 0, 44, 0, 38, 0, 0, 0, 0, + 45, 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0, 0, 0, 0, 0, 0, 0, 0, 0, 125, 34, 126, 126, 29, 114, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 108, 108, 108, 108, 0, + 0, 0, 0, 0, 0, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10, 10, + 10, 0, 0, 0, 0, 2, 2, 116, 2, 8, 8, 8, 0, 8, 0, 8, 8, 8, 8, 8, 8, 0, 8, 8, 85, + 8, 0, 8, 0, 0, 8, 0, 0, 0, 0, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 127, 127, 128, + 129, 126, 126, 126, 126, 86, 127, 130, 129, 128, 128, 129, 130, 129, 128, 129, + 112, 131, 109, 109, 109, 112, 128, 129, 130, 129, 128, 129, 127, 129, 112, 131, + 109, 109, 109, 112, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10, 10, 10, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 68, 68, 132, 68, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 10, 10, 10, 10, 0, 0, 0, 0, 2, 2, 115, 2, 8, 8, 8, 0, 8, 0, 8, 8, 8, 8, 8, - 8, 0, 8, 8, 84, 8, 0, 8, 0, 0, 8, 0, 0, 0, 0, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 127, 127, 128, 129, 125, 125, 125, 125, 85, 127, 130, 129, 128, 128, 129, 130, - 129, 128, 129, 131, 132, 107, 107, 107, 131, 128, 129, 130, 129, 128, 129, - 127, 129, 131, 132, 107, 107, 107, 131, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10, 10, - 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 67, 67, 133, 67, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 123, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 10, 10, 0, 0, 113, 113, 0, 0, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 10, 10, 0, 0, 113, 113, 0, 0, 10, 10, 0, 0, 0, 0, 0, 0, - 0, 0, 67, 67, 0, 0, 0, 0, 0, 0, 0, 0, 67, 133, 134, 135, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 10, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 123, 123, 21, 105, 22, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 136, 137, 136, 137, 0, 138, 0, 139, - 0, 0, 0, 3, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 124, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10, + 0, 0, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10, 0, + 0, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, 68, 68, 68, 132, 133, 134, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 10, 10, 10, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 124, 124, 21, + 107, 22, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 135, 136, 135, 136, 0, 137, 0, + 138, 0, 0, 0, 3, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; const uint8_t InstDB::rwInfoIndexB[Inst::_kIdCount] = { 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 3, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 5, 5, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 4, 8, 1, 0, 9, 0, 0, 0, 10, 10, 10, 0, 0, 11, 0, - 0, 10, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, - 13, 5, 5, 13, 0, 14, 15, 13, 16, 17, 18, 13, 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 20, 1, 1, 21, 22, 0, 0, 0, - 0, 5, 5, 0, 0, 0, 0, 0, 0, 23, 24, 0, 0, 25, 26, 27, 28, 0, 0, 26, 26, 26, 26, - 26, 26, 26, 26, 29, 30, 30, 29, 0, 0, 0, 25, 26, 25, 26, 0, 26, 25, 25, 25, - 25, 25, 25, 25, 0, 0, 31, 31, 31, 25, 25, 29, 0, 32, 10, 0, 0, 0, 0, 0, 0, 25, - 26, 0, 0, 0, 33, 34, 33, 35, 0, 0, 0, 0, 0, 10, 33, 0, 0, 0, 0, 36, 34, 33, 36, - 35, 25, 26, 25, 26, 0, 30, 30, 30, 30, 0, 0, 0, 26, 10, 10, 33, 33, 0, 0, 0, - 20, 5, 5, 0, 0, 0, 0, 0, 0, 0, 22, 37, 0, 21, 38, 39, 0, 40, 41, 0, 0, 0, 0, - 0, 10, 0, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 43, 44, 45, 46, 43, 44, 43, 44, - 45, 46, 45, 46, 0, 0, 0, 0, 0, 0, 0, 0, 43, 44, 45, 0, 0, 0, 0, 46, 47, 48, - 49, 50, 47, 48, 49, 50, 0, 0, 0, 0, 51, 52, 53, 43, 44, 45, 46, 43, 44, 45, 46, - 54, 0, 25, 0, 55, 0, 56, 0, 0, 0, 0, 0, 10, 0, 10, 25, 57, 58, 57, 0, 0, 0, - 0, 0, 0, 57, 59, 59, 0, 60, 61, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 62, 62, 0, 0, 0, + 0, 10, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 13, 13, 13, + 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 5, 5, 13, 0, 14, 15, 13, 16, 17, 18, 13, + 0, 0, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 20, 1, 1, 21, 22, 0, 0, 0, 0, 5, 5, 0, 0, 0, 0, 0, 0, 23, 24, 0, 0, + 25, 26, 27, 28, 0, 0, 26, 26, 26, 26, 26, 26, 26, 26, 29, 30, 30, 29, 0, 0, 0, + 25, 26, 25, 26, 0, 26, 25, 25, 25, 25, 25, 25, 25, 0, 0, 31, 31, 31, 25, 25, + 29, 0, 32, 10, 0, 0, 0, 0, 0, 0, 25, 26, 0, 0, 0, 33, 34, 33, 35, 0, 0, 0, 0, + 0, 10, 33, 0, 0, 0, 0, 36, 34, 33, 36, 35, 25, 26, 25, 26, 0, 30, 30, 30, 30, + 0, 0, 0, 26, 10, 10, 33, 33, 0, 0, 0, 0, 5, 5, 0, 0, 0, 0, 0, 0, 0, 22, 37, 0, + 21, 38, 38, 0, 39, 40, 0, 0, 0, 0, 0, 10, 0, 41, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 42, 43, 44, 45, 42, 43, 42, 43, 44, 45, + 44, 45, 0, 0, 0, 0, 0, 0, 0, 0, 42, 43, 44, 0, 0, 0, 0, 45, 46, 47, 48, 49, + 46, 47, 48, 49, 0, 0, 0, 0, 50, 51, 52, 42, 43, 44, 45, 42, 43, 44, 45, 53, 0, + 25, 0, 54, 0, 55, 0, 0, 0, 0, 0, 10, 0, 10, 25, 56, 57, 56, 0, 0, 0, 0, 0, 0, + 56, 58, 58, 0, 59, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 61, 61, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 63, 0, 0, 63, 0, 0, 0, 0, 0, 5, 64, 0, 0, 0, 0, 65, 0, 66, 21, 67, 21, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 68, 0, 0, 0, 0, 0, - 0, 6, 5, 5, 0, 0, 0, 0, 69, 70, 0, 0, 0, 0, 71, 72, 0, 3, 3, 73, 23, 74, 75, + 62, 0, 0, 62, 0, 0, 0, 0, 0, 5, 63, 0, 0, 0, 0, 64, 0, 65, 21, 66, 21, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 67, 0, 0, 0, 0, 0, 0, 6, + 5, 5, 0, 0, 0, 0, 68, 69, 0, 0, 0, 0, 70, 71, 0, 3, 3, 72, 23, 73, 74, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 76, 40, 77, 78, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 79, 0, 0, 0, 0, 0, 0, 0, - 10, 10, 10, 10, 10, 10, 10, 10, 10, 0, 0, 2, 2, 2, 80, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 67, 0, 0, 0, 0, 0, 0, 0, 0, - 67, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 81, 81, 82, 81, 82, 82, 82, 81, 81, 83, - 84, 0, 85, 0, 0, 0, 0, 0, 0, 86, 2, 2, 87, 88, 0, 0, 0, 11, 89, 0, 0, 4, 0, - 0, 0, 0, 0, 0, 90, 0, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, - 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 91, 0, 91, 0, 33, 0, - 0, 0, 5, 0, 0, 6, 0, 92, 4, 0, 92, 4, 5, 5, 33, 20, 93, 81, 93, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 94, 0, 93, 95, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 96, 96, - 0, 96, 96, 96, 96, 96, 96, 0, 0, 0, 0, 0, 0, 97, 0, 98, 0, 0, 0, 0, 0, 0, 0, 0, - 10, 98, 0, 0, 0, 0, 99, 100, 99, 100, 3, 3, 3, 101, 102, 103, 3, 3, 3, 3, 3, - 3, 0, 2, 3, 3, 3, 3, 3, 3, 0, 0, 3, 3, 3, 3, 104, 104, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 3, 105, 3, 106, 107, 108, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 109, 0, 0, 0, 0, - 0, 0, 0, 110, 0, 111, 0, 112, 0, 112, 0, 113, 114, 115, 116, 117, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 113, 114, - 115, 0, 0, 3, 3, 3, 3, 101, 112, 103, 3, 118, 3, 57, 57, 0, 0, 0, 0, 119, - 120, 121, 120, 121, 119, 120, 121, 120, 121, 23, 122, 123, 122, 123, 124, 124, - 125, 126, 124, 124, 124, 127, 128, 129, 124, 124, 124, 127, 128, 129, 124, 124, - 124, 127, 128, 129, 122, 123, 130, 130, 131, 132, 124, 124, 124, 124, 124, - 124, 124, 124, 124, 130, 130, 124, 124, 124, 127, 133, 129, 124, 124, 124, 127, - 133, 129, 124, 124, 124, 127, 133, 129, 124, 124, 124, 124, 124, 124, 124, 124, - 124, 130, 130, 130, 130, 131, 132, 122, 123, 124, 124, 124, 127, 128, 129, - 124, 124, 124, 127, 128, 129, 124, 124, 124, 127, 128, 129, 130, 130, 131, 132, - 124, 124, 124, 127, 133, 129, 124, 124, 124, 127, 133, 129, 124, 124, 124, - 134, 133, 135, 130, 130, 131, 132, 136, 136, 136, 80, 137, 138, 0, 0, 0, 0, 139, - 140, 10, 10, 10, 10, 10, 10, 10, 10, 140, 141, 0, 0, 0, 142, 143, 144, 86, - 86, 86, 142, 143, 144, 3, 3, 3, 3, 3, 3, 3, 145, 146, 147, 146, 147, 145, 146, - 147, 146, 147, 103, 0, 55, 60, 148, 148, 3, 3, 3, 101, 102, 103, 0, 149, 0, 0, - 3, 3, 3, 101, 102, 103, 0, 150, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 151, - 152, 152, 153, 154, 154, 0, 0, 0, 0, 0, 0, 0, 155, 156, 0, 0, 157, 0, 0, 0, 3, - 11, 149, 0, 0, 158, 150, 3, 3, 3, 101, 102, 103, 0, 0, 11, 3, 3, 159, 159, 160, - 160, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 104, 3, 0, 0, 0, 0, 0, 0, 3, 130, 105, 105, 3, 3, 3, 3, 69, - 70, 3, 3, 3, 3, 71, 72, 105, 105, 105, 105, 105, 105, 118, 118, 0, 0, 0, 0, - 118, 118, 118, 118, 118, 118, 0, 0, 124, 124, 124, 124, 124, 124, 124, 124, 124, - 124, 124, 124, 124, 124, 124, 124, 161, 161, 3, 3, 124, 124, 3, 3, 124, 124, - 130, 130, 162, 162, 162, 3, 162, 124, 124, 124, 124, 124, 124, 3, 0, 0, 0, 0, - 73, 23, 74, 163, 140, 139, 141, 140, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 0, 3, - 0, 0, 0, 0, 3, 0, 3, 3, 0, 164, 103, 101, 102, 0, 0, 165, 165, 165, 165, 165, - 165, 165, 165, 165, 165, 165, 165, 124, 124, 3, 3, 148, 148, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 3, 3, 3, 166, 86, 86, 3, 3, 86, 86, 3, 3, 167, - 167, 167, 167, 3, 0, 0, 0, 0, 167, 167, 167, 167, 167, 167, 3, 3, 124, 124, 124, - 3, 167, 167, 3, 3, 124, 124, 124, 3, 3, 105, 86, 86, 86, 3, 3, 3, 168, 169, - 168, 3, 3, 3, 170, 168, 171, 3, 3, 3, 170, 168, 169, 168, 3, 3, 3, 170, 3, 3, - 3, 3, 3, 3, 3, 3, 172, 172, 0, 105, 105, 105, 105, 105, 105, 105, 105, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 142, 144, 0, 0, 142, 144, 0, 0, 142, 144, 0, - 0, 143, 144, 86, 86, 86, 142, 143, 144, 86, 86, 86, 142, 143, 144, 86, 86, 142, - 144, 0, 0, 142, 144, 0, 0, 142, 144, 0, 0, 143, 144, 3, 3, 3, 101, 102, 103, - 0, 0, 10, 10, 10, 10, 10, 10, 10, 10, 0, 0, 0, 0, 173, 3, 3, 3, 3, 3, 3, 174, - 174, 174, 3, 3, 0, 0, 0, 142, 143, 144, 94, 3, 3, 3, 101, 102, 103, 0, 0, 0, - 0, 0, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 58, 58, 175, 0, 0, 0, 0, 0, 0, 0, 0, 0, 82, - 0, 0, 0, 0, 0, 176, 176, 176, 176, 177, 177, 177, 177, 177, 177, 177, 177, 175, - 0, 0 + 0, 75, 39, 76, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 78, 0, 0, 0, 0, 0, 0, 0, 10, 10, + 10, 10, 10, 10, 10, 10, 10, 0, 0, 2, 2, 2, 79, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 66, 0, 0, 0, 0, 0, 0, 0, 0, 66, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 80, 80, 81, 80, 81, 81, 81, 80, 80, 82, 83, + 0, 84, 0, 0, 0, 0, 0, 0, 85, 2, 2, 86, 87, 0, 0, 0, 11, 88, 0, 4, 0, 0, 0, 0, + 0, 0, 89, 0, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 90, 0, 90, + 0, 33, 0, 0, 0, 5, 0, 0, 6, 0, 91, 4, 0, 91, 4, 5, 5, 33, 20, 92, 80, 92, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 93, 0, 92, 94, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 95, 95, 0, 95, 95, 95, 95, 95, 95, 0, 0, 0, 0, 0, 0, 96, 0, 97, 0, 0, 0, 0, + 0, 0, 0, 0, 10, 97, 0, 0, 0, 0, 3, 3, 3, 98, 99, 100, 3, 3, 3, 3, 3, 3, 0, 2, + 3, 3, 3, 3, 3, 3, 0, 0, 3, 3, 3, 3, 101, 101, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 3, 102, 3, 103, 104, 105, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 106, 0, 0, 0, 0, 0, 0, 0, + 98, 0, 107, 0, 99, 0, 108, 0, 109, 110, 111, 112, 113, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 109, 110, 111, 0, + 0, 3, 3, 3, 3, 98, 99, 100, 3, 114, 3, 56, 56, 0, 0, 115, 116, 117, 116, 117, + 115, 116, 117, 116, 117, 23, 118, 119, 118, 119, 120, 120, 121, 122, 120, 120, + 120, 123, 124, 125, 120, 120, 120, 123, 124, 125, 120, 120, 120, 123, 124, + 125, 118, 119, 126, 126, 127, 128, 120, 120, 120, 120, 120, 120, 120, 120, 120, + 126, 126, 120, 120, 120, 123, 129, 125, 120, 120, 120, 123, 129, 125, 120, 120, + 120, 123, 129, 125, 120, 120, 120, 120, 120, 120, 120, 120, 120, 126, 126, + 126, 126, 127, 128, 118, 130, 120, 120, 120, 123, 124, 125, 120, 120, 120, 123, + 124, 125, 120, 120, 120, 123, 124, 125, 126, 126, 127, 128, 120, 120, 120, + 123, 129, 125, 120, 120, 120, 123, 129, 125, 120, 120, 120, 131, 129, 132, 126, + 126, 127, 128, 133, 133, 133, 79, 134, 135, 0, 0, 0, 0, 136, 137, 137, 138, + 0, 0, 0, 139, 140, 141, 85, 85, 85, 139, 140, 141, 3, 3, 3, 3, 3, 3, 3, 142, 143, + 144, 143, 144, 142, 143, 144, 143, 144, 100, 0, 54, 59, 145, 145, 3, 3, 3, + 98, 99, 100, 0, 11, 0, 0, 3, 3, 3, 98, 99, 100, 0, 146, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 147, 148, 148, 149, 150, 150, 0, 0, 0, 0, 0, 0, 0, 151, 152, + 0, 0, 153, 0, 0, 0, 3, 11, 154, 0, 0, 155, 146, 3, 3, 3, 98, 99, 100, 0, 0, 11, + 3, 3, 156, 156, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 101, 3, 0, 0, 0, 0, 0, 0, 3, 126, 102, 102, 3, + 3, 3, 3, 68, 69, 3, 3, 3, 3, 70, 71, 102, 102, 102, 102, 102, 102, 114, 114, 0, + 0, 0, 0, 114, 114, 114, 114, 114, 114, 0, 0, 120, 120, 120, 120, 120, 120, 120, + 120, 120, 120, 120, 120, 120, 120, 120, 120, 157, 157, 3, 3, 120, 120, 3, + 3, 120, 120, 126, 126, 158, 158, 158, 3, 158, 120, 120, 120, 120, 120, 120, 3, + 0, 0, 0, 0, 72, 23, 73, 159, 137, 136, 138, 137, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, + 0, 0, 3, 0, 0, 0, 0, 3, 0, 3, 3, 0, 160, 100, 98, 99, 0, 0, 161, 161, 161, 161, + 161, 161, 161, 161, 161, 161, 161, 161, 120, 120, 3, 3, 145, 145, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 3, 3, 3, 162, 85, 85, 3, 3, 85, 85, 3, + 3, 163, 163, 163, 163, 3, 0, 0, 0, 0, 163, 163, 163, 163, 163, 163, 3, 3, 120, + 120, 120, 3, 163, 163, 3, 3, 120, 120, 120, 3, 3, 102, 85, 85, 85, 3, 3, 3, + 164, 165, 164, 3, 3, 3, 166, 164, 167, 3, 3, 3, 166, 164, 165, 164, 3, 3, 3, 166, + 3, 3, 3, 3, 3, 3, 3, 3, 168, 168, 0, 102, 102, 102, 102, 102, 102, 102, 102, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 139, 141, 0, 0, 139, 141, 0, 0, 140, + 141, 85, 85, 85, 139, 140, 141, 85, 85, 85, 139, 140, 141, 85, 85, 139, 141, + 0, 0, 139, 141, 0, 0, 140, 141, 3, 3, 3, 98, 99, 100, 0, 0, 0, 0, 0, 0, 169, 3, + 3, 3, 3, 3, 3, 170, 170, 170, 3, 3, 0, 0, 0, 139, 140, 141, 93, 3, 3, 3, 98, + 99, 100, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 57, 57, 171, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 81, 0, 0, 0, 0, 0, 172, 172, 172, 172, 173, 173, 173, 173, 173, + 173, 173, 173, 171, 0, 0 }; const InstDB::RWInfo InstDB::rwInfoA[] = { - { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=1055x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=999x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 1 , 0 , 0 , 0 , 0 , 0 } }, // #1 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #2 [ref=15x] { InstDB::RWInfo::kCategoryGeneric , 1 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #3 [ref=7x] - { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #4 [ref=96x] + { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #4 [ref=82x] { InstDB::RWInfo::kCategoryGeneric , 3 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #5 [ref=55x] { InstDB::RWInfo::kCategoryGeneric , 4 , { 6 , 7 , 0 , 0 , 0 , 0 } }, // #6 [ref=6x] { InstDB::RWInfo::kCategoryGeneric , 5 , { 8 , 9 , 0 , 0 , 0 , 0 } }, // #7 [ref=6x] @@ -5693,110 +5700,109 @@ const InstDB::RWInfo InstDB::rwInfoA[] = { { InstDB::RWInfo::kCategoryGeneric , 13, { 43, 44, 0 , 0 , 0 , 0 } }, // #37 [ref=3x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #38 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 46, 47, 0 , 0 , 0 , 0 } }, // #39 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 51, 0 , 0 , 0 , 0 } }, // #40 [ref=1x] - { InstDB::RWInfo::kCategoryImul , 2 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #41 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 52, 53, 0 , 0 , 0 , 0 } }, // #42 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 14, { 55, 53, 0 , 0 , 0 , 0 } }, // #43 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 15, { 3 , 5 , 0 , 0 , 0 , 0 } }, // #44 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 29, 0 , 0 , 0 , 0 } }, // #45 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 57, 0 , 0 , 0 , 0 , 0 } }, // #46 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 23, { 58, 40, 0 , 0 , 0 , 0 } }, // #47 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 24, { 45, 9 , 0 , 0 , 0 , 0 } }, // #48 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 25, { 35, 7 , 0 , 0 , 0 , 0 } }, // #49 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 26, { 49, 13, 0 , 0 , 0 , 0 } }, // #50 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 58, 40, 0 , 0 , 0 , 0 } }, // #51 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 9 , 0 , 0 , 0 , 0 } }, // #52 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #53 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 13, 0 , 0 , 0 , 0 } }, // #54 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 40, 40, 0 , 0 , 0 , 0 } }, // #55 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 9 , 9 , 0 , 0 , 0 , 0 } }, // #56 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 7 , 0 , 0 , 0 , 0 } }, // #57 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 13, 13, 0 , 0 , 0 , 0 } }, // #58 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 3 , 0 , 0 , 0 , 0 } }, // #59 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 15, { 10, 5 , 0 , 0 , 0 , 0 } }, // #60 [ref=5x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #61 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 52, 20, 0 , 0 , 0 , 0 } }, // #62 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 60, 0 , 0 , 0 , 0 , 0 } }, // #63 [ref=3x] - { InstDB::RWInfo::kCategoryMov , 29, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #64 [ref=1x] - { InstDB::RWInfo::kCategoryMovabs , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #65 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 30, { 10, 5 , 0 , 0 , 0 , 0 } }, // #66 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #67 [ref=18x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 36, 64, 0 , 0 , 0 , 0 } }, // #68 [ref=1x] - { InstDB::RWInfo::kCategoryMovh64 , 12, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #69 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 65, 7 , 0 , 0 , 0 , 0 } }, // #70 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 7 , 0 , 0 , 0 , 0 } }, // #71 [ref=7x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 58, 5 , 0 , 0 , 0 , 0 } }, // #72 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 28, { 45, 9 , 0 , 0 , 0 , 0 } }, // #73 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 14, { 66, 20, 0 , 0 , 0 , 0 } }, // #74 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 31, { 35, 7 , 0 , 0 , 0 , 0 } }, // #75 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 33, { 45, 9 , 0 , 0 , 0 , 0 } }, // #76 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 16, { 11, 3 , 0 , 0 , 0 , 0 } }, // #77 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 17, 29, 0 , 0 , 0 , 0 } }, // #78 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 11, { 3 , 3 , 0 , 0 , 0 , 0 } }, // #79 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 22, 0 , 0 , 0 , 0 } }, // #80 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 14, { 53, 69, 0 , 0 , 0 , 0 } }, // #81 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 4 , { 26, 7 , 0 , 0 , 0 , 0 } }, // #82 [ref=18x] - { InstDB::RWInfo::kCategoryGeneric , 36, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #83 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 72, 5 , 0 , 0 , 0 , 0 } }, // #84 [ref=2x] - { InstDB::RWInfo::kCategoryVmov1_8 , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #85 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 10, 9 , 0 , 0 , 0 , 0 } }, // #86 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 27, { 10, 13, 0 , 0 , 0 , 0 } }, // #87 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #88 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 0 , 0 , 0 } }, // #89 [ref=1x] - { InstDB::RWInfo::kCategoryPunpcklxx , 38, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #90 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 73, 0 , 0 , 0 , 0 } }, // #91 [ref=8x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 37, 9 , 0 , 0 , 0 , 0 } }, // #92 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 51, 0 , 0 , 0 , 0 } }, // #93 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 21, 0 , 0 , 0 , 0 } }, // #94 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 66, 22, 0 , 0 , 0 , 0 } }, // #95 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 43, 3 , 0 , 0 , 0 , 0 } }, // #96 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 44, 0 , 0 , 0 , 0 } }, // #97 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 54, 9 , 0 , 0 , 0 , 0 } }, // #98 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 21, { 11, 13, 0 , 0 , 0 , 0 } }, // #99 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 15, { 81, 5 , 0 , 0 , 0 , 0 } }, // #100 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 15, { 11, 5 , 0 , 0 , 0 , 0 } }, // #101 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 43, { 43, 82, 0 , 0 , 0 , 0 } }, // #102 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 44, { 11, 7 , 0 , 0 , 0 , 0 } }, // #103 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 45, { 11, 9 , 0 , 0 , 0 , 0 } }, // #104 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 27, { 13, 13, 0 , 0 , 0 , 0 } }, // #105 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 11, { 11, 3 , 0 , 0 , 0 , 0 } }, // #106 [ref=7x] - { InstDB::RWInfo::kCategoryVmov2_1 , 46, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #107 [ref=14x] - { InstDB::RWInfo::kCategoryVmov1_2 , 16, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #108 [ref=7x] - { InstDB::RWInfo::kCategoryGeneric , 16, { 10, 3 , 0 , 0 , 0 , 0 } }, // #109 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 46, { 11, 3 , 0 , 0 , 0 , 0 } }, // #110 [ref=5x] - { InstDB::RWInfo::kCategoryGeneric , 47, { 11, 5 , 0 , 0 , 0 , 0 } }, // #111 [ref=5x] - { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 5 , 0 , 0 , 0 , 0 } }, // #112 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 51, { 43, 44, 0 , 0 , 0 , 0 } }, // #113 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 45, 9 , 0 , 0 , 0 , 0 } }, // #114 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 14, { 2 , 3 , 0 , 0 , 0 , 0 } }, // #115 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 58, { 11, 3 , 0 , 0 , 0 , 0 } }, // #116 [ref=12x] - { InstDB::RWInfo::kCategoryVmovddup , 38, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #117 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 64, 0 , 0 , 0 , 0 } }, // #118 [ref=2x] - { InstDB::RWInfo::kCategoryVmovmskpd , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #119 [ref=1x] - { InstDB::RWInfo::kCategoryVmovmskps , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #120 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 59, { 35, 7 , 0 , 0 , 0 , 0 } }, // #121 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 21, { 49, 13, 0 , 0 , 0 , 0 } }, // #122 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 2 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #123 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 17, { 11, 40, 0 , 0 , 0 , 0 } }, // #124 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 7 , 0 , 0 , 0 , 0 } }, // #125 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 13, 0 , 0 , 0 , 0 } }, // #126 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 51, 30, 0 , 0 , 0 , 0 } }, // #40 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 51, 0 , 0 , 0 , 0 } }, // #41 [ref=1x] + { InstDB::RWInfo::kCategoryImul , 2 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #42 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 52, 53, 0 , 0 , 0 , 0 } }, // #43 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 14, { 54, 53, 0 , 0 , 0 , 0 } }, // #44 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 15, { 3 , 5 , 0 , 0 , 0 , 0 } }, // #45 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 29, 0 , 0 , 0 , 0 } }, // #46 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 56, 0 , 0 , 0 , 0 , 0 } }, // #47 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 23, { 57, 40, 0 , 0 , 0 , 0 } }, // #48 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 24, { 45, 9 , 0 , 0 , 0 , 0 } }, // #49 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 25, { 35, 7 , 0 , 0 , 0 , 0 } }, // #50 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 26, { 49, 13, 0 , 0 , 0 , 0 } }, // #51 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 57, 40, 0 , 0 , 0 , 0 } }, // #52 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 9 , 0 , 0 , 0 , 0 } }, // #53 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #54 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 13, 0 , 0 , 0 , 0 } }, // #55 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 40, 40, 0 , 0 , 0 , 0 } }, // #56 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 9 , 9 , 0 , 0 , 0 , 0 } }, // #57 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 7 , 0 , 0 , 0 , 0 } }, // #58 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 13, 13, 0 , 0 , 0 , 0 } }, // #59 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 3 , 0 , 0 , 0 , 0 } }, // #60 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 15, { 10, 5 , 0 , 0 , 0 , 0 } }, // #61 [ref=5x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #62 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 52, 20, 0 , 0 , 0 , 0 } }, // #63 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 59, 0 , 0 , 0 , 0 , 0 } }, // #64 [ref=3x] + { InstDB::RWInfo::kCategoryMov , 29, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #65 [ref=1x] + { InstDB::RWInfo::kCategoryMovabs , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #66 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 30, { 10, 5 , 0 , 0 , 0 , 0 } }, // #67 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #68 [ref=18x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 36, 63, 0 , 0 , 0 , 0 } }, // #69 [ref=1x] + { InstDB::RWInfo::kCategoryMovh64 , 12, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #70 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 64, 7 , 0 , 0 , 0 , 0 } }, // #71 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 7 , 0 , 0 , 0 , 0 } }, // #72 [ref=7x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 57, 5 , 0 , 0 , 0 , 0 } }, // #73 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 28, { 45, 9 , 0 , 0 , 0 , 0 } }, // #74 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 14, { 65, 20, 0 , 0 , 0 , 0 } }, // #75 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 31, { 35, 7 , 0 , 0 , 0 , 0 } }, // #76 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 33, { 45, 9 , 0 , 0 , 0 , 0 } }, // #77 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 16, { 11, 3 , 0 , 0 , 0 , 0 } }, // #78 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 17, 29, 0 , 0 , 0 , 0 } }, // #79 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 11, { 3 , 3 , 0 , 0 , 0 , 0 } }, // #80 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 22, 0 , 0 , 0 , 0 } }, // #81 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 14, { 53, 68, 0 , 0 , 0 , 0 } }, // #82 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 4 , { 26, 7 , 0 , 0 , 0 , 0 } }, // #83 [ref=18x] + { InstDB::RWInfo::kCategoryGeneric , 36, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #84 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 71, 5 , 0 , 0 , 0 , 0 } }, // #85 [ref=2x] + { InstDB::RWInfo::kCategoryVmov1_8 , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #86 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 10, 9 , 0 , 0 , 0 , 0 } }, // #87 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 27, { 10, 13, 0 , 0 , 0 , 0 } }, // #88 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #89 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 0 , 0 , 0 } }, // #90 [ref=1x] + { InstDB::RWInfo::kCategoryPunpcklxx , 38, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #91 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 72, 0 , 0 , 0 , 0 } }, // #92 [ref=7x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 37, 9 , 0 , 0 , 0 , 0 } }, // #93 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 0 , 0 , 0 , 0 , 0 } }, // #94 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 51, 0 , 0 , 0 , 0 } }, // #95 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 21, 0 , 0 , 0 , 0 } }, // #96 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 65, 22, 0 , 0 , 0 , 0 } }, // #97 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 43, 3 , 0 , 0 , 0 , 0 } }, // #98 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 44, 0 , 0 , 0 , 0 } }, // #99 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 76, 9 , 0 , 0 , 0 , 0 } }, // #100 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 21, { 11, 13, 0 , 0 , 0 , 0 } }, // #101 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 15, { 77, 5 , 0 , 0 , 0 , 0 } }, // #102 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 15, { 11, 5 , 0 , 0 , 0 , 0 } }, // #103 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 43, { 43, 78, 0 , 0 , 0 , 0 } }, // #104 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 44, { 11, 7 , 0 , 0 , 0 , 0 } }, // #105 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 45, { 11, 9 , 0 , 0 , 0 , 0 } }, // #106 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 27, { 13, 13, 0 , 0 , 0 , 0 } }, // #107 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 11, { 11, 3 , 0 , 0 , 0 , 0 } }, // #108 [ref=7x] + { InstDB::RWInfo::kCategoryVmov2_1 , 46, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #109 [ref=19x] + { InstDB::RWInfo::kCategoryVmov1_2 , 16, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #110 [ref=11x] + { InstDB::RWInfo::kCategoryVmov1_4 , 16, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #111 [ref=2x] + { InstDB::RWInfo::kCategoryVmov4_1 , 47, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #112 [ref=9x] + { InstDB::RWInfo::kCategoryGeneric , 16, { 10, 3 , 0 , 0 , 0 , 0 } }, // #113 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 13, 0 , 0 , 0 , 0 } }, // #114 [ref=5x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 45, 9 , 0 , 0 , 0 , 0 } }, // #115 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 14, { 2 , 3 , 0 , 0 , 0 , 0 } }, // #116 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 57, { 11, 3 , 0 , 0 , 0 , 0 } }, // #117 [ref=12x] + { InstDB::RWInfo::kCategoryVmovddup , 38, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #118 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 63, 0 , 0 , 0 , 0 } }, // #119 [ref=2x] + { InstDB::RWInfo::kCategoryVmovmskpd , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #120 [ref=1x] + { InstDB::RWInfo::kCategoryVmovmskps , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #121 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 58, { 35, 7 , 0 , 0 , 0 , 0 } }, // #122 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 21, { 49, 13, 0 , 0 , 0 , 0 } }, // #123 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 2 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #124 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 17, { 11, 40, 0 , 0 , 0 , 0 } }, // #125 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 7 , 0 , 0 , 0 , 0 } }, // #126 [ref=6x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 3 , 0 , 0 , 0 , 0 } }, // #127 [ref=4x] - { InstDB::RWInfo::kCategoryVmov1_4 , 62, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #128 [ref=6x] + { InstDB::RWInfo::kCategoryVmov1_4 , 61, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #128 [ref=6x] { InstDB::RWInfo::kCategoryVmov1_2 , 48, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #129 [ref=9x] - { InstDB::RWInfo::kCategoryVmov1_8 , 63, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #130 [ref=3x] - { InstDB::RWInfo::kCategoryVmov4_1 , 47, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #131 [ref=4x] - { InstDB::RWInfo::kCategoryVmov8_1 , 64, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #132 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 14, { 11, 3 , 0 , 0 , 0 , 0 } }, // #133 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 90, 5 , 0 , 0 , 0 , 0 } }, // #134 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 90, 82, 0 , 0 , 0 , 0 } }, // #135 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 18, { 45, 9 , 0 , 0 , 0 , 0 } }, // #136 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 35, { 35, 7 , 0 , 0 , 0 , 0 } }, // #137 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 2 , 0 , 0 , 0 , 0 } }, // #138 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 58, { 2 , 2 , 0 , 0 , 0 , 0 } } // #139 [ref=1x] + { InstDB::RWInfo::kCategoryVmov1_8 , 62, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #130 [ref=3x] + { InstDB::RWInfo::kCategoryVmov8_1 , 63, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #131 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 14, { 11, 3 , 0 , 0 , 0 , 0 } }, // #132 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 88, 5 , 0 , 0 , 0 , 0 } }, // #133 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 88, 78, 0 , 0 , 0 , 0 } }, // #134 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 18, { 45, 9 , 0 , 0 , 0 , 0 } }, // #135 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 35, { 35, 7 , 0 , 0 , 0 , 0 } }, // #136 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 2 , 0 , 0 , 0 , 0 } }, // #137 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 57, { 2 , 2 , 0 , 0 , 0 , 0 } } // #138 [ref=1x] }; const InstDB::RWInfo InstDB::rwInfoB[] = { - { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=792x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=758x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 1 , 0 , 0 , 0 , 0 , 0 } }, // #1 [ref=5x] { InstDB::RWInfo::kCategoryGeneric , 3 , { 10, 5 , 0 , 0 , 0 , 0 } }, // #2 [ref=7x] { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 0 , 0 , 0 } }, // #3 [ref=193x] @@ -5806,8 +5812,8 @@ const InstDB::RWInfo InstDB::rwInfoB[] = { { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 0 , 0 , 0 , 0 , 0 } }, // #7 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 11, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #8 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 18, 0 , 0 , 0 , 0 , 0 } }, // #9 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #10 [ref=37x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 7 , 0 , 0 , 0 , 0 , 0 } }, // #11 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #10 [ref=21x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 7 , 0 , 0 , 0 , 0 , 0 } }, // #11 [ref=5x] { InstDB::RWInfo::kCategoryGeneric , 13, { 19, 0 , 0 , 0 , 0 , 0 } }, // #12 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 2 , 3 , 0 , 0 , 0 } }, // #13 [ref=16x] { InstDB::RWInfo::kCategoryGeneric , 4 , { 6 , 7 , 0 , 0 , 0 , 0 } }, // #14 [ref=1x] @@ -5816,7 +5822,7 @@ const InstDB::RWInfo InstDB::rwInfoB[] = { { InstDB::RWInfo::kCategoryGeneric , 15, { 4 , 23, 18, 24, 25, 0 } }, // #17 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 12, { 26, 27, 28, 29, 30, 0 } }, // #18 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 28, 31, 32, 16, 0 , 0 } }, // #19 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 28, 0 , 0 , 0 , 0 , 0 } }, // #20 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 28, 0 , 0 , 0 , 0 , 0 } }, // #20 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 0 , 0 , 0 , 0 , 0 } }, // #21 [ref=4x] { InstDB::RWInfo::kCategoryGeneric , 6 , { 41, 42, 3 , 0 , 0 , 0 } }, // #22 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 18, { 45, 5 , 0 , 0 , 0 , 0 } }, // #23 [ref=4x] @@ -5834,163 +5840,159 @@ const InstDB::RWInfo InstDB::rwInfoB[] = { { InstDB::RWInfo::kCategoryGeneric , 7 , { 50, 0 , 0 , 0 , 0 , 0 } }, // #35 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 20, { 11, 0 , 0 , 0 , 0 , 0 } }, // #36 [ref=2x] { InstDB::RWInfo::kCategoryImul , 22, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #37 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 54, 0 , 0 , 0 , 0 , 0 } }, // #38 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 26, 0 , 0 , 0 , 0 , 0 } }, // #39 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 4 , 9 , 0 , 0 , 0 , 0 } }, // #40 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #41 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 56, 57, 0 , 0 , 0 } }, // #42 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 58, 40, 40, 0 , 0 , 0 } }, // #43 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 9 , 9 , 0 , 0 , 0 } }, // #44 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 7 , 7 , 0 , 0 , 0 } }, // #45 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 13, 13, 0 , 0 , 0 } }, // #46 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 58, 40, 0 , 0 , 0 , 0 } }, // #47 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 9 , 0 , 0 , 0 , 0 } }, // #48 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #49 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 13, 0 , 0 , 0 , 0 } }, // #50 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 40, 40, 0 , 0 , 0 } }, // #51 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 9 , 9 , 0 , 0 , 0 } }, // #52 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 13, 13, 0 , 0 , 0 } }, // #53 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 59, 0 , 0 , 0 , 0 , 0 } }, // #54 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 28, { 9 , 0 , 0 , 0 , 0 , 0 } }, // #55 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 13, { 44, 0 , 0 , 0 , 0 , 0 } }, // #56 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 7 , { 13, 0 , 0 , 0 , 0 , 0 } }, // #57 [ref=5x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #58 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 3 , 9 , 0 , 0 , 0 , 0 } }, // #59 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 15, { 5 , 5 , 61, 0 , 0 , 0 } }, // #60 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 7 , 7 , 62, 0 , 0 , 0 } }, // #61 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 63, 29, 56, 0 , 0 , 0 } }, // #62 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 32, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #63 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 67, 42, 3 , 0 , 0 , 0 } }, // #64 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 11, 3 , 68, 0 , 0 } }, // #65 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 17, 29, 30, 0 , 0 , 0 } }, // #66 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 10, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #67 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #68 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 70, 17, 56 } }, // #69 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 71, 17, 56 } }, // #70 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 40, 0 , 0 , 0 , 0 , 0 } }, // #38 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 4 , 9 , 0 , 0 , 0 , 0 } }, // #39 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #40 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 55, 56, 0 , 0 , 0 } }, // #41 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 57, 40, 40, 0 , 0 , 0 } }, // #42 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 9 , 9 , 0 , 0 , 0 } }, // #43 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 7 , 7 , 0 , 0 , 0 } }, // #44 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 13, 13, 0 , 0 , 0 } }, // #45 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 57, 40, 0 , 0 , 0 , 0 } }, // #46 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 9 , 0 , 0 , 0 , 0 } }, // #47 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #48 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 13, 0 , 0 , 0 , 0 } }, // #49 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 40, 40, 0 , 0 , 0 } }, // #50 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 9 , 9 , 0 , 0 , 0 } }, // #51 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 13, 13, 0 , 0 , 0 } }, // #52 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 58, 0 , 0 , 0 , 0 , 0 } }, // #53 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 28, { 9 , 0 , 0 , 0 , 0 , 0 } }, // #54 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 44, 0 , 0 , 0 , 0 , 0 } }, // #55 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 7 , { 13, 0 , 0 , 0 , 0 , 0 } }, // #56 [ref=5x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #57 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 3 , 9 , 0 , 0 , 0 , 0 } }, // #58 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 15, { 5 , 5 , 60, 0 , 0 , 0 } }, // #59 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 7 , 7 , 61, 0 , 0 , 0 } }, // #60 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 62, 29, 55, 0 , 0 , 0 } }, // #61 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 32, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #62 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 66, 42, 3 , 0 , 0 , 0 } }, // #63 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 11, 3 , 67, 0 , 0 } }, // #64 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 17, 29, 30, 0 , 0 , 0 } }, // #65 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 10, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #66 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #67 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 69, 17, 55 } }, // #68 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 70, 17, 55 } }, // #69 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 69, 0 , 0 } }, // #70 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 70, 0 , 0 } }, // #71 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 71, 0 , 0 } }, // #72 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 34, { 58, 5 , 0 , 0 , 0 , 0 } }, // #73 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 35, { 35, 5 , 0 , 0 , 0 , 0 } }, // #74 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 37, { 49, 3 , 0 , 0 , 0 , 0 } }, // #75 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 17, { 4 , 40, 0 , 0 , 0 , 0 } }, // #76 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 4 , { 4 , 7 , 0 , 0 , 0 , 0 } }, // #77 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 27, { 2 , 13, 0 , 0 , 0 , 0 } }, // #78 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 10, { 11, 0 , 0 , 0 , 0 , 0 } }, // #79 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 4 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #80 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #81 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 51, 29, 0 , 0 , 0 } }, // #82 [ref=5x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 0 , 0 , 0 , 0 , 0 } }, // #83 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 0 , 0 , 0 , 0 , 0 } }, // #84 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 51, 70, 0 , 0 , 0 } }, // #85 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #86 [ref=19x] - { InstDB::RWInfo::kCategoryGeneric , 4 , { 36, 7 , 0 , 0 , 0 , 0 } }, // #87 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 37, 9 , 0 , 0 , 0 , 0 } }, // #88 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 74, 0 , 0 , 0 , 0 , 0 } }, // #89 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 0 , 0 , 0 , 0 , 0 } }, // #90 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 34, { 75, 0 , 0 , 0 , 0 , 0 } }, // #91 [ref=30x] - { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 73, 0 , 0 , 0 } }, // #92 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 39, { 11, 0 , 0 , 0 , 0 , 0 } }, // #93 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 28, { 45, 0 , 0 , 0 , 0 , 0 } }, // #94 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 13, { 43, 0 , 0 , 0 , 0 , 0 } }, // #95 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 76, 44, 44, 0 , 0 , 0 } }, // #96 [ref=8x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 0 , 0 , 0 , 0 , 0 } }, // #97 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 9 , 56, 17, 0 , 0 , 0 } }, // #98 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 15, { 76, 77, 78, 78, 78, 5 } }, // #99 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 15, { 4 , 79, 80, 80, 80, 5 } }, // #100 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 40, { 10, 5 , 7 , 0 , 0 , 0 } }, // #101 [ref=8x] - { InstDB::RWInfo::kCategoryGeneric , 41, { 10, 5 , 13, 0 , 0 , 0 } }, // #102 [ref=7x] - { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 5 , 9 , 0 , 0 , 0 } }, // #103 [ref=9x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 3 , 0 , 0 } }, // #104 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 35, 3 , 3 , 0 , 0 , 0 } }, // #105 [ref=18x] - { InstDB::RWInfo::kCategoryGeneric , 40, { 11, 5 , 7 , 0 , 0 , 0 } }, // #106 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 41, { 35, 13, 13, 0 , 0 , 0 } }, // #107 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 42, { 11, 5 , 9 , 0 , 0 , 0 } }, // #108 [ref=1x] - { InstDB::RWInfo::kCategoryVmov1_2 , 48, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #109 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 40, { 10, 5 , 5 , 0 , 0 , 0 } }, // #110 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 40, { 10, 83, 7 , 0 , 0 , 0 } }, // #111 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 41, { 10, 5 , 5 , 0 , 0 , 0 } }, // #112 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 49, { 10, 64, 3 , 0 , 0 , 0 } }, // #113 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 49, { 10, 3 , 3 , 0 , 0 , 0 } }, // #114 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 49, { 10, 83, 3 , 0 , 0 , 0 } }, // #115 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 64, 9 , 0 , 0 , 0 } }, // #116 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 5 , 5 , 0 , 0 , 0 } }, // #117 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 50, { 10, 5 , 5 , 0 , 0 , 0 } }, // #118 [ref=9x] - { InstDB::RWInfo::kCategoryGeneric , 52, { 10, 82, 0 , 0 , 0 , 0 } }, // #119 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 52, { 10, 3 , 0 , 0 , 0 , 0 } }, // #120 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 53, { 81, 44, 0 , 0 , 0 , 0 } }, // #121 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 84, 3 , 3 , 0 , 0 , 0 } }, // #122 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 42, { 85, 5 , 5 , 0 , 0 , 0 } }, // #123 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 2 , 3 , 3 , 0 , 0 , 0 } }, // #124 [ref=90x] - { InstDB::RWInfo::kCategoryGeneric , 40, { 4 , 64, 7 , 0 , 0 , 0 } }, // #125 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 42, { 4 , 83, 9 , 0 , 0 , 0 } }, // #126 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 40, { 6 , 7 , 7 , 0 , 0 , 0 } }, // #127 [ref=11x] - { InstDB::RWInfo::kCategoryGeneric , 41, { 4 , 5 , 5 , 0 , 0 , 0 } }, // #128 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 42, { 8 , 9 , 9 , 0 , 0 , 0 } }, // #129 [ref=11x] - { InstDB::RWInfo::kCategoryGeneric , 54, { 11, 3 , 3 , 3 , 0 , 0 } }, // #130 [ref=15x] - { InstDB::RWInfo::kCategoryGeneric , 55, { 35, 7 , 7 , 7 , 0 , 0 } }, // #131 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 56, { 45, 9 , 9 , 9 , 0 , 0 } }, // #132 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 41, { 4 , 5 , 13, 0 , 0 , 0 } }, // #133 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 40, { 26, 7 , 7 , 0 , 0 , 0 } }, // #134 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 42, { 54, 9 , 9 , 0 , 0 , 0 } }, // #135 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 16, { 35, 3 , 0 , 0 , 0 , 0 } }, // #136 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 27, { 35, 13, 0 , 0 , 0 , 0 } }, // #137 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 35, 9 , 0 , 0 , 0 , 0 } }, // #138 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #139 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #140 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 14, { 4 , 3 , 4 , 0 , 0 , 0 } }, // #141 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 40, { 10, 64, 7 , 0 , 0 , 0 } }, // #142 [ref=11x] - { InstDB::RWInfo::kCategoryGeneric , 41, { 10, 86, 13, 0 , 0 , 0 } }, // #143 [ref=7x] - { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 83, 9 , 0 , 0 , 0 } }, // #144 [ref=13x] - { InstDB::RWInfo::kCategoryGeneric , 50, { 81, 82, 5 , 0 , 0 , 0 } }, // #145 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 50, { 11, 3 , 5 , 0 , 0 , 0 } }, // #146 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 57, { 43, 44, 82, 0 , 0 , 0 } }, // #147 [ref=4x] - { InstDB::RWInfo::kCategoryVmaskmov , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #148 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 0 , 0 , 0 , 0 , 0 } }, // #149 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 0 , 0 , 0 , 0 , 0 } }, // #150 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 64, 64, 0 , 0 , 0 } }, // #151 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 10, 7 , 7 , 0 , 0 , 0 } }, // #152 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 7 , 7 , 0 , 0 , 0 } }, // #153 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 10, 64, 7 , 0 , 0 , 0 } }, // #154 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 64, 7 , 0 , 0 , 0 } }, // #155 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 86, 13, 0 , 0 , 0 } }, // #156 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 83, 9 , 0 , 0 , 0 } }, // #157 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 87, 0 , 0 , 0 , 0 , 0 } }, // #158 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 60, { 88, 89, 3 , 3 , 0 , 0 } }, // #159 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 15, { 43, 77, 78, 78, 78, 5 } }, // #160 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 57, { 81, 82, 82, 0 , 0 , 0 } }, // #161 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 3 , 0 , 0 , 0 } }, // #162 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 7 , { 49, 5 , 0 , 0 , 0 , 0 } }, // #163 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 61, { 10, 5 , 40, 0 , 0 , 0 } }, // #164 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 50, { 10, 5 , 5 , 5 , 0 , 0 } }, // #165 [ref=12x] - { InstDB::RWInfo::kCategoryGeneric , 65, { 10, 5 , 5 , 5 , 0 , 0 } }, // #166 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 66, { 10, 5 , 5 , 0 , 0 , 0 } }, // #167 [ref=12x] - { InstDB::RWInfo::kCategoryGeneric , 67, { 11, 3 , 5 , 0 , 0 , 0 } }, // #168 [ref=5x] - { InstDB::RWInfo::kCategoryGeneric , 68, { 11, 3 , 0 , 0 , 0 , 0 } }, // #169 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 69, { 11, 3 , 5 , 0 , 0 , 0 } }, // #170 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 5 , 0 , 0 , 0 } }, // #171 [ref=1x] - { InstDB::RWInfo::kCategoryGenericEx , 6 , { 2 , 3 , 3 , 0 , 0 , 0 } }, // #172 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 90, 82, 5 , 0 , 0 , 0 } }, // #173 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 50, { 4 , 5 , 5 , 0 , 0 , 0 } }, // #174 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 56, 17, 29, 0 , 0 , 0 } }, // #175 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 56, 17, 0 , 0 , 0 } }, // #176 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 56, 17, 0 , 0 , 0 } } // #177 [ref=8x] + { InstDB::RWInfo::kCategoryGeneric , 34, { 57, 5 , 0 , 0 , 0 , 0 } }, // #72 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 35, { 35, 5 , 0 , 0 , 0 , 0 } }, // #73 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 37, { 49, 3 , 0 , 0 , 0 , 0 } }, // #74 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 17, { 4 , 40, 0 , 0 , 0 , 0 } }, // #75 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 4 , { 4 , 7 , 0 , 0 , 0 , 0 } }, // #76 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 27, { 2 , 13, 0 , 0 , 0 , 0 } }, // #77 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 10, { 11, 0 , 0 , 0 , 0 , 0 } }, // #78 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 4 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #79 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #80 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 51, 29, 0 , 0 , 0 } }, // #81 [ref=5x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 0 , 0 , 0 , 0 , 0 } }, // #82 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 0 , 0 , 0 , 0 , 0 } }, // #83 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 51, 69, 0 , 0 , 0 } }, // #84 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #85 [ref=19x] + { InstDB::RWInfo::kCategoryGeneric , 4 , { 36, 7 , 0 , 0 , 0 , 0 } }, // #86 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 37, 9 , 0 , 0 , 0 , 0 } }, // #87 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 73, 0 , 0 , 0 , 0 , 0 } }, // #88 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 0 , 0 , 0 , 0 , 0 } }, // #89 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 34, { 74, 0 , 0 , 0 , 0 , 0 } }, // #90 [ref=16x] + { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 72, 0 , 0 , 0 } }, // #91 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 39, { 11, 0 , 0 , 0 , 0 , 0 } }, // #92 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 28, { 45, 0 , 0 , 0 , 0 , 0 } }, // #93 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 43, 0 , 0 , 0 , 0 , 0 } }, // #94 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 75, 44, 44, 0 , 0 , 0 } }, // #95 [ref=8x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 0 , 0 , 0 , 0 , 0 } }, // #96 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 9 , 55, 17, 0 , 0 , 0 } }, // #97 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 40, { 10, 5 , 7 , 0 , 0 , 0 } }, // #98 [ref=9x] + { InstDB::RWInfo::kCategoryGeneric , 41, { 10, 5 , 13, 0 , 0 , 0 } }, // #99 [ref=9x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 5 , 9 , 0 , 0 , 0 } }, // #100 [ref=9x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 3 , 0 , 0 } }, // #101 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 35, 3 , 3 , 0 , 0 , 0 } }, // #102 [ref=18x] + { InstDB::RWInfo::kCategoryGeneric , 40, { 11, 5 , 7 , 0 , 0 , 0 } }, // #103 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 41, { 35, 13, 13, 0 , 0 , 0 } }, // #104 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 11, 5 , 9 , 0 , 0 , 0 } }, // #105 [ref=1x] + { InstDB::RWInfo::kCategoryVmov1_2 , 48, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #106 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 40, { 10, 79, 7 , 0 , 0 , 0 } }, // #107 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 41, { 10, 5 , 5 , 0 , 0 , 0 } }, // #108 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 49, { 10, 63, 3 , 0 , 0 , 0 } }, // #109 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 49, { 10, 3 , 3 , 0 , 0 , 0 } }, // #110 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 49, { 10, 79, 3 , 0 , 0 , 0 } }, // #111 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 63, 9 , 0 , 0 , 0 } }, // #112 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 5 , 5 , 0 , 0 , 0 } }, // #113 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 50, { 10, 5 , 5 , 0 , 0 , 0 } }, // #114 [ref=9x] + { InstDB::RWInfo::kCategoryGeneric , 51, { 10, 78, 0 , 0 , 0 , 0 } }, // #115 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 51, { 10, 3 , 0 , 0 , 0 , 0 } }, // #116 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 52, { 77, 44, 0 , 0 , 0 , 0 } }, // #117 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 80, 3 , 3 , 0 , 0 , 0 } }, // #118 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 81, 5 , 5 , 0 , 0 , 0 } }, // #119 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 2 , 3 , 3 , 0 , 0 , 0 } }, // #120 [ref=90x] + { InstDB::RWInfo::kCategoryGeneric , 40, { 4 , 63, 7 , 0 , 0 , 0 } }, // #121 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 4 , 79, 9 , 0 , 0 , 0 } }, // #122 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 40, { 6 , 7 , 7 , 0 , 0 , 0 } }, // #123 [ref=11x] + { InstDB::RWInfo::kCategoryGeneric , 41, { 82, 5 , 5 , 0 , 0 , 0 } }, // #124 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 8 , 9 , 9 , 0 , 0 , 0 } }, // #125 [ref=11x] + { InstDB::RWInfo::kCategoryGeneric , 53, { 11, 3 , 3 , 3 , 0 , 0 } }, // #126 [ref=15x] + { InstDB::RWInfo::kCategoryGeneric , 54, { 35, 7 , 7 , 7 , 0 , 0 } }, // #127 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 55, { 45, 9 , 9 , 9 , 0 , 0 } }, // #128 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 41, { 82, 5 , 13, 0 , 0 , 0 } }, // #129 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 83, 5 , 5 , 0 , 0 , 0 } }, // #130 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 40, { 26, 7 , 7 , 0 , 0 , 0 } }, // #131 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 76, 9 , 9 , 0 , 0 , 0 } }, // #132 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 16, { 35, 3 , 0 , 0 , 0 , 0 } }, // #133 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 27, { 35, 13, 0 , 0 , 0 , 0 } }, // #134 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 35, 9 , 0 , 0 , 0 , 0 } }, // #135 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #136 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #137 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 14, { 4 , 3 , 4 , 0 , 0 , 0 } }, // #138 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 40, { 10, 63, 7 , 0 , 0 , 0 } }, // #139 [ref=9x] + { InstDB::RWInfo::kCategoryGeneric , 41, { 10, 84, 13, 0 , 0 , 0 } }, // #140 [ref=7x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 79, 9 , 0 , 0 , 0 } }, // #141 [ref=11x] + { InstDB::RWInfo::kCategoryGeneric , 50, { 77, 78, 5 , 0 , 0 , 0 } }, // #142 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 50, { 11, 3 , 5 , 0 , 0 , 0 } }, // #143 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 56, { 43, 44, 78, 0 , 0 , 0 } }, // #144 [ref=4x] + { InstDB::RWInfo::kCategoryVmaskmov , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #145 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 0 , 0 , 0 , 0 , 0 } }, // #146 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 63, 63, 0 , 0 , 0 } }, // #147 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 10, 7 , 7 , 0 , 0 , 0 } }, // #148 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 7 , 7 , 0 , 0 , 0 } }, // #149 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 10, 63, 7 , 0 , 0 , 0 } }, // #150 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 63, 7 , 0 , 0 , 0 } }, // #151 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 84, 13, 0 , 0 , 0 } }, // #152 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 79, 9 , 0 , 0 , 0 } }, // #153 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 0 , 0 , 0 , 0 , 0 } }, // #154 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 85, 0 , 0 , 0 , 0 , 0 } }, // #155 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 59, { 86, 87, 3 , 3 , 0 , 0 } }, // #156 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 56, { 77, 78, 78, 0 , 0 , 0 } }, // #157 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 3 , 0 , 0 , 0 } }, // #158 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 7 , { 49, 5 , 0 , 0 , 0 , 0 } }, // #159 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 60, { 10, 5 , 40, 0 , 0 , 0 } }, // #160 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 50, { 10, 5 , 5 , 5 , 0 , 0 } }, // #161 [ref=12x] + { InstDB::RWInfo::kCategoryGeneric , 64, { 10, 5 , 5 , 5 , 0 , 0 } }, // #162 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 65, { 10, 5 , 5 , 0 , 0 , 0 } }, // #163 [ref=12x] + { InstDB::RWInfo::kCategoryGeneric , 66, { 11, 3 , 5 , 0 , 0 , 0 } }, // #164 [ref=5x] + { InstDB::RWInfo::kCategoryGeneric , 67, { 11, 3 , 0 , 0 , 0 , 0 } }, // #165 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 68, { 11, 3 , 5 , 0 , 0 , 0 } }, // #166 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 5 , 0 , 0 , 0 } }, // #167 [ref=1x] + { InstDB::RWInfo::kCategoryGenericEx , 6 , { 2 , 3 , 3 , 0 , 0 , 0 } }, // #168 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 88, 78, 5 , 0 , 0 , 0 } }, // #169 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 50, { 4 , 5 , 5 , 0 , 0 , 0 } }, // #170 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 55, 17, 29, 0 , 0 , 0 } }, // #171 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 55, 17, 0 , 0 , 0 } }, // #172 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 55, 17, 0 , 0 , 0 } } // #173 [ref=8x] }; const InstDB::RWInfoOp InstDB::rwInfoOp[] = { - { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kNone }, // #0 [ref=17098x] + { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kNone }, // #0 [ref=16348x] { 0x0000000000000003u, 0x0000000000000003u, 0x00, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kRegPhysId }, // #1 [ref=10x] - { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt }, // #2 [ref=282x] - { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #3 [ref=1132x] - { 0x000000000000FFFFu, 0x000000000000FFFFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt }, // #4 [ref=107x] - { 0x000000000000FFFFu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #5 [ref=356x] + { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt }, // #2 [ref=267x] + { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #3 [ref=1091x] + { 0x000000000000FFFFu, 0x000000000000FFFFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt }, // #4 [ref=93x] + { 0x000000000000FFFFu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #5 [ref=338x] { 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, 0, { 0 }, OpRWFlags::kRW }, // #6 [ref=18x] { 0x00000000000000FFu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #7 [ref=186x] { 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, 0, { 0 }, OpRWFlags::kRW }, // #8 [ref=18x] - { 0x000000000000000Fu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #9 [ref=135x] - { 0x0000000000000000u, 0x000000000000FFFFu, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #10 [ref=184x] - { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #11 [ref=459x] + { 0x000000000000000Fu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #9 [ref=133x] + { 0x0000000000000000u, 0x000000000000FFFFu, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #10 [ref=178x] + { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #11 [ref=445x] { 0x0000000000000003u, 0x0000000000000003u, 0xFF, 0, { 0 }, OpRWFlags::kRW }, // #12 [ref=1x] - { 0x0000000000000003u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #13 [ref=65x] + { 0x0000000000000003u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #13 [ref=71x] { 0x000000000000FFFFu, 0x0000000000000000u, 0x00, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #14 [ref=4x] { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kMemBaseWrite | OpRWFlags::kMemIndexWrite }, // #15 [ref=1x] { 0x0000000000000000u, 0x000000000000000Fu, 0x02, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #16 [ref=9x] @@ -6003,11 +6005,11 @@ const InstDB::RWInfoOp InstDB::rwInfoOp[] = { { 0x00000000000000FFu, 0x00000000000000FFu, 0x02, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #23 [ref=1x] { 0x00000000000000FFu, 0x0000000000000000u, 0x01, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #24 [ref=1x] { 0x00000000000000FFu, 0x0000000000000000u, 0x03, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #25 [ref=1x] - { 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt }, // #26 [ref=21x] + { 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt }, // #26 [ref=20x] { 0x000000000000000Fu, 0x000000000000000Fu, 0x02, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #27 [ref=1x] - { 0x000000000000000Fu, 0x000000000000000Fu, 0x00, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #28 [ref=5x] + { 0x000000000000000Fu, 0x000000000000000Fu, 0x00, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #28 [ref=4x] { 0x000000000000000Fu, 0x0000000000000000u, 0x01, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #29 [ref=13x] - { 0x000000000000000Fu, 0x0000000000000000u, 0x03, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #30 [ref=2x] + { 0x000000000000000Fu, 0x0000000000000000u, 0x03, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #30 [ref=3x] { 0x0000000000000000u, 0x000000000000000Fu, 0x03, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #31 [ref=1x] { 0x000000000000000Fu, 0x000000000000000Fu, 0x01, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #32 [ref=1x] { 0x0000000000000000u, 0x00000000000000FFu, 0x02, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #33 [ref=1x] @@ -6017,76 +6019,74 @@ const InstDB::RWInfoOp InstDB::rwInfoOp[] = { { 0x0000000000000000u, 0x000000000000000Fu, 0xFF, 0, { 0 }, OpRWFlags::kWrite }, // #37 [ref=6x] { 0x0000000000000000u, 0x0000000000000003u, 0x02, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kRegPhysId }, // #38 [ref=1x] { 0x0000000000000003u, 0x0000000000000000u, 0x00, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #39 [ref=1x] - { 0x0000000000000001u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #40 [ref=28x] + { 0x0000000000000001u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #40 [ref=30x] { 0x0000000000000000u, 0x0000000000000000u, 0x02, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kRegPhysId | OpRWFlags::kZExt }, // #41 [ref=2x] { 0x0000000000000000u, 0x0000000000000000u, 0x00, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kRegPhysId | OpRWFlags::kZExt }, // #42 [ref=3x] - { 0x0000000000000000u, 0xFFFFFFFFFFFFFFFFu, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #43 [ref=23x] - { 0xFFFFFFFFFFFFFFFFu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #44 [ref=35x] + { 0x0000000000000000u, 0xFFFFFFFFFFFFFFFFu, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #43 [ref=15x] + { 0xFFFFFFFFFFFFFFFFu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #44 [ref=29x] { 0x0000000000000000u, 0x000000000000000Fu, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #45 [ref=30x] { 0x00000000000003FFu, 0x00000000000003FFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt }, // #46 [ref=22x] { 0x00000000000003FFu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #47 [ref=13x] { 0x0000000000000000u, 0x00000000000003FFu, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #48 [ref=1x] { 0x0000000000000000u, 0x0000000000000003u, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #49 [ref=17x] { 0x0000000000000000u, 0x0000000000000003u, 0x00, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kRegPhysId | OpRWFlags::kZExt }, // #50 [ref=2x] - { 0x0000000000000000u, 0x000000000000000Fu, 0x00, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #51 [ref=8x] + { 0x0000000000000000u, 0x000000000000000Fu, 0x00, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #51 [ref=9x] { 0x0000000000000000u, 0x0000000000000000u, 0x00, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kRegPhysId | OpRWFlags::kZExt }, // #52 [ref=2x] { 0x0000000000000003u, 0x0000000000000000u, 0x02, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #53 [ref=4x] - { 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt }, // #54 [ref=4x] - { 0x0000000000000000u, 0x0000000000000000u, 0x07, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kMemPhysId }, // #55 [ref=1x] - { 0x000000000000000Fu, 0x0000000000000000u, 0x02, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #56 [ref=23x] - { 0x0000000000000000u, 0x0000000000000000u, 0x01, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #57 [ref=2x] - { 0x0000000000000000u, 0x0000000000000001u, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #58 [ref=14x] - { 0x0000000000000000u, 0x0000000000000001u, 0x00, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kRegPhysId }, // #59 [ref=1x] - { 0x0000000000000000u, 0x0000000000000000u, 0x01, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kRegPhysId | OpRWFlags::kZExt }, // #60 [ref=3x] - { 0x000000000000FFFFu, 0x000000000000FFFFu, 0x07, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt | OpRWFlags::kMemPhysId }, // #61 [ref=2x] - { 0x00000000000000FFu, 0x00000000000000FFu, 0x07, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt | OpRWFlags::kMemPhysId }, // #62 [ref=1x] - { 0x0000000000000000u, 0x0000000000000000u, 0x00, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kMemPhysId }, // #63 [ref=2x] - { 0x000000000000FF00u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #64 [ref=23x] - { 0x0000000000000000u, 0x000000000000FF00u, 0xFF, 0, { 0 }, OpRWFlags::kWrite }, // #65 [ref=1x] - { 0x0000000000000000u, 0x0000000000000000u, 0x07, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kMemBaseRW | OpRWFlags::kMemBasePostModify | OpRWFlags::kMemPhysId }, // #66 [ref=2x] - { 0x0000000000000000u, 0x0000000000000000u, 0x02, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kRegPhysId | OpRWFlags::kZExt }, // #67 [ref=1x] - { 0x0000000000000000u, 0x0000000000000000u, 0x02, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #68 [ref=1x] - { 0x0000000000000000u, 0x0000000000000000u, 0x06, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kMemPhysId }, // #69 [ref=1x] - { 0x0000000000000000u, 0x000000000000000Fu, 0x01, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #70 [ref=5x] - { 0x0000000000000000u, 0x000000000000FFFFu, 0x00, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #71 [ref=4x] - { 0x0000000000000000u, 0x0000000000000007u, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #72 [ref=2x] - { 0x0000000000000001u, 0x0000000000000000u, 0x01, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #73 [ref=10x] - { 0x0000000000000001u, 0x0000000000000000u, 0x00, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #74 [ref=1x] - { 0x0000000000000000u, 0x0000000000000001u, 0xFF, 0, { 0 }, OpRWFlags::kWrite }, // #75 [ref=30x] - { 0xFFFFFFFFFFFFFFFFu, 0xFFFFFFFFFFFFFFFFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt }, // #76 [ref=10x] - { 0xFFFFFFFFFFFFFFFFu, 0x0000000000000000u, 0xFF, 4, { 0 }, OpRWFlags::kRead }, // #77 [ref=4x] - { 0xFFFFFFFFFFFFFFFFu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kConsecutive }, // #78 [ref=12x] - { 0x000000000000FFFFu, 0x0000000000000000u, 0xFF, 4, { 0 }, OpRWFlags::kRead }, // #79 [ref=2x] - { 0x000000000000FFFFu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kConsecutive }, // #80 [ref=6x] - { 0x0000000000000000u, 0x00000000FFFFFFFFu, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #81 [ref=10x] - { 0x00000000FFFFFFFFu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #82 [ref=18x] - { 0x000000000000FFF0u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #83 [ref=18x] - { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kUnique | OpRWFlags::kZExt }, // #84 [ref=4x] - { 0x000000000000FFFFu, 0x000000000000FFFFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kUnique | OpRWFlags::kZExt }, // #85 [ref=4x] - { 0x000000000000FFFCu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #86 [ref=8x] - { 0x0000000000000000u, 0x0000000000000000u, 0x00, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #87 [ref=1x] - { 0x0000000000000000u, 0x00000000000000FFu, 0xFF, 2, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #88 [ref=2x] - { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kConsecutive }, // #89 [ref=2x] - { 0x00000000FFFFFFFFu, 0x00000000FFFFFFFFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt } // #90 [ref=3x] + { 0x0000000000000000u, 0x0000000000000000u, 0x07, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kMemPhysId }, // #54 [ref=1x] + { 0x000000000000000Fu, 0x0000000000000000u, 0x02, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #55 [ref=23x] + { 0x0000000000000000u, 0x0000000000000000u, 0x01, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #56 [ref=2x] + { 0x0000000000000000u, 0x0000000000000001u, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #57 [ref=14x] + { 0x0000000000000000u, 0x0000000000000001u, 0x00, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kRegPhysId }, // #58 [ref=1x] + { 0x0000000000000000u, 0x0000000000000000u, 0x01, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kRegPhysId | OpRWFlags::kZExt }, // #59 [ref=3x] + { 0x000000000000FFFFu, 0x000000000000FFFFu, 0x07, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt | OpRWFlags::kMemPhysId }, // #60 [ref=2x] + { 0x00000000000000FFu, 0x00000000000000FFu, 0x07, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt | OpRWFlags::kMemPhysId }, // #61 [ref=1x] + { 0x0000000000000000u, 0x0000000000000000u, 0x00, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kMemPhysId }, // #62 [ref=2x] + { 0x000000000000FF00u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #63 [ref=21x] + { 0x0000000000000000u, 0x000000000000FF00u, 0xFF, 0, { 0 }, OpRWFlags::kWrite }, // #64 [ref=1x] + { 0x0000000000000000u, 0x0000000000000000u, 0x07, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kMemBaseRW | OpRWFlags::kMemBasePostModify | OpRWFlags::kMemPhysId }, // #65 [ref=2x] + { 0x0000000000000000u, 0x0000000000000000u, 0x02, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kRegPhysId | OpRWFlags::kZExt }, // #66 [ref=1x] + { 0x0000000000000000u, 0x0000000000000000u, 0x02, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #67 [ref=1x] + { 0x0000000000000000u, 0x0000000000000000u, 0x06, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kMemPhysId }, // #68 [ref=1x] + { 0x0000000000000000u, 0x000000000000000Fu, 0x01, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #69 [ref=5x] + { 0x0000000000000000u, 0x000000000000FFFFu, 0x00, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #70 [ref=4x] + { 0x0000000000000000u, 0x0000000000000007u, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #71 [ref=2x] + { 0x0000000000000001u, 0x0000000000000000u, 0x01, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #72 [ref=9x] + { 0x0000000000000001u, 0x0000000000000000u, 0x00, 0, { 0 }, OpRWFlags::kRead | OpRWFlags::kRegPhysId }, // #73 [ref=1x] + { 0x0000000000000000u, 0x0000000000000001u, 0xFF, 0, { 0 }, OpRWFlags::kWrite }, // #74 [ref=16x] + { 0xFFFFFFFFFFFFFFFFu, 0xFFFFFFFFFFFFFFFFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt }, // #75 [ref=8x] + { 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt }, // #76 [ref=3x] + { 0x0000000000000000u, 0x00000000FFFFFFFFu, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #77 [ref=10x] + { 0x00000000FFFFFFFFu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #78 [ref=18x] + { 0x000000000000FFF0u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #79 [ref=16x] + { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kUnique | OpRWFlags::kZExt }, // #80 [ref=4x] + { 0x000000000000FFFFu, 0x000000000000FFFFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kUnique }, // #81 [ref=3x] + { 0x000000000000FFFFu, 0x000000000000FFFFu, 0xFF, 0, { 0 }, OpRWFlags::kRW }, // #82 [ref=12x] + { 0x000000000000FFFFu, 0x000000000000FFFFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kUnique | OpRWFlags::kZExt }, // #83 [ref=1x] + { 0x000000000000FFFCu, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kRead }, // #84 [ref=8x] + { 0x0000000000000000u, 0x0000000000000000u, 0x00, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt | OpRWFlags::kRegPhysId }, // #85 [ref=1x] + { 0x0000000000000000u, 0x00000000000000FFu, 0xFF, 2, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt }, // #86 [ref=2x] + { 0x0000000000000000u, 0x0000000000000000u, 0xFF, 0, { 0 }, OpRWFlags::kWrite | OpRWFlags::kZExt | OpRWFlags::kConsecutive }, // #87 [ref=2x] + { 0x00000000FFFFFFFFu, 0x00000000FFFFFFFFu, 0xFF, 0, { 0 }, OpRWFlags::kRW | OpRWFlags::kZExt } // #88 [ref=3x] }; const InstDB::RWInfoRm InstDB::rwInfoRm[] = { - { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , 0, 0 }, // #0 [ref=2085x] + { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , 0, 0 }, // #0 [ref=1996x] { InstDB::RWInfoRm::kCategoryConsistent, 0x03, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #1 [ref=8x] - { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , 0, 0 }, // #2 [ref=204x] + { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , 0, 0 }, // #2 [ref=190x] { InstDB::RWInfoRm::kCategoryFixed , 0x02, 16, 0, 0 }, // #3 [ref=122x] { InstDB::RWInfoRm::kCategoryFixed , 0x02, 8 , 0, 0 }, // #4 [ref=66x] { InstDB::RWInfoRm::kCategoryFixed , 0x02, 4 , 0, 0 }, // #5 [ref=35x] { InstDB::RWInfoRm::kCategoryConsistent, 0x04, 0 , 0, 0 }, // #6 [ref=314x] { InstDB::RWInfoRm::kCategoryFixed , 0x01, 2 , 0, 0 }, // #7 [ref=9x] - { InstDB::RWInfoRm::kCategoryFixed , 0x00, 0 , 0, 0 }, // #8 [ref=68x] + { InstDB::RWInfoRm::kCategoryFixed , 0x00, 0 , 0, 0 }, // #8 [ref=52x] { InstDB::RWInfoRm::kCategoryFixed , 0x03, 0 , 0, 0 }, // #9 [ref=1x] - { InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #10 [ref=21x] + { InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #10 [ref=20x] { InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , 0, 0 }, // #11 [ref=14x] { InstDB::RWInfoRm::kCategoryFixed , 0x00, 8 , 0, 0 }, // #12 [ref=23x] { InstDB::RWInfoRm::kCategoryFixed , 0x00, 64, 0, 0 }, // #13 [ref=6x] { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #14 [ref=30x] - { InstDB::RWInfoRm::kCategoryFixed , 0x00, 16, 0, 0 }, // #15 [ref=23x] + { InstDB::RWInfoRm::kCategoryFixed , 0x00, 16, 0, 0 }, // #15 [ref=17x] { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #16 [ref=22x] { InstDB::RWInfoRm::kCategoryFixed , 0x02, 1 , 0, 0 }, // #17 [ref=5x] { InstDB::RWInfoRm::kCategoryFixed , 0x01, 4 , 0, 0 }, // #18 [ref=6x] @@ -6105,15 +6105,15 @@ const InstDB::RWInfoRm InstDB::rwInfoRm[] = { { InstDB::RWInfoRm::kCategoryFixed , 0x03, 8 , InstDB::RWInfoRm::kFlagMovssMovsd, 0 }, // #31 [ref=1x] { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , InstDB::RWInfoRm::kFlagMovssMovsd, 0 }, // #32 [ref=2x] { InstDB::RWInfoRm::kCategoryFixed , 0x03, 4 , InstDB::RWInfoRm::kFlagMovssMovsd, 0 }, // #33 [ref=1x] - { InstDB::RWInfoRm::kCategoryFixed , 0x01, 1 , 0, 0 }, // #34 [ref=32x] + { InstDB::RWInfoRm::kCategoryFixed , 0x01, 1 , 0, 0 }, // #34 [ref=18x] { InstDB::RWInfoRm::kCategoryFixed , 0x01, 8 , 0, 0 }, // #35 [ref=4x] { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , InstDB::RWInfoRm::kFlagPextrw, 0 }, // #36 [ref=1x] { InstDB::RWInfoRm::kCategoryFixed , 0x01, 2 , InstDB::RWInfoRm::kFlagPextrw, uint32_t(CpuFeatures::X86::kSSE4_1) }, // #37 [ref=1x] { InstDB::RWInfoRm::kCategoryNone , 0x02, 0 , 0, 0 }, // #38 [ref=4x] { InstDB::RWInfoRm::kCategoryFixed , 0x01, 2 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #39 [ref=3x] - { InstDB::RWInfoRm::kCategoryFixed , 0x04, 8 , 0, 0 }, // #40 [ref=35x] + { InstDB::RWInfoRm::kCategoryFixed , 0x04, 8 , 0, 0 }, // #40 [ref=33x] { InstDB::RWInfoRm::kCategoryFixed , 0x04, 2 , 0, 0 }, // #41 [ref=30x] - { InstDB::RWInfoRm::kCategoryFixed , 0x04, 4 , 0, 0 }, // #42 [ref=42x] + { InstDB::RWInfoRm::kCategoryFixed , 0x04, 4 , 0, 0 }, // #42 [ref=40x] { InstDB::RWInfoRm::kCategoryFixed , 0x00, 32, 0, 0 }, // #43 [ref=4x] { InstDB::RWInfoRm::kCategoryFixed , 0x02, 8 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #44 [ref=1x] { InstDB::RWInfoRm::kCategoryFixed , 0x02, 4 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #45 [ref=1x] @@ -6122,25 +6122,24 @@ const InstDB::RWInfoRm InstDB::rwInfoRm[] = { { InstDB::RWInfoRm::kCategoryHalf , 0x01, 0 , 0, 0 }, // #48 [ref=10x] { InstDB::RWInfoRm::kCategoryConsistent, 0x04, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #49 [ref=6x] { InstDB::RWInfoRm::kCategoryFixed , 0x04, 16, 0, 0 }, // #50 [ref=30x] - { InstDB::RWInfoRm::kCategoryFixed , 0x02, 64, 0, 0 }, // #51 [ref=6x] - { InstDB::RWInfoRm::kCategoryFixed , 0x01, 16, 0, 0 }, // #52 [ref=6x] - { InstDB::RWInfoRm::kCategoryFixed , 0x01, 32, 0, 0 }, // #53 [ref=4x] - { InstDB::RWInfoRm::kCategoryConsistent, 0x0C, 0 , 0, 0 }, // #54 [ref=15x] - { InstDB::RWInfoRm::kCategoryFixed , 0x0C, 8 , 0, 0 }, // #55 [ref=4x] - { InstDB::RWInfoRm::kCategoryFixed , 0x0C, 4 , 0, 0 }, // #56 [ref=4x] - { InstDB::RWInfoRm::kCategoryFixed , 0x04, 32, 0, 0 }, // #57 [ref=6x] - { InstDB::RWInfoRm::kCategoryConsistent, 0x03, 0 , 0, 0 }, // #58 [ref=13x] - { InstDB::RWInfoRm::kCategoryFixed , 0x03, 8 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #59 [ref=1x] - { InstDB::RWInfoRm::kCategoryConsistent, 0x08, 0 , 0, 0 }, // #60 [ref=2x] - { InstDB::RWInfoRm::kCategoryFixed , 0x04, 1 , 0, 0 }, // #61 [ref=1x] - { InstDB::RWInfoRm::kCategoryQuarter , 0x01, 0 , 0, 0 }, // #62 [ref=6x] - { InstDB::RWInfoRm::kCategoryEighth , 0x01, 0 , 0, 0 }, // #63 [ref=3x] - { InstDB::RWInfoRm::kCategoryEighth , 0x02, 0 , 0, 0 }, // #64 [ref=2x] - { InstDB::RWInfoRm::kCategoryFixed , 0x0C, 16, 0, 0 }, // #65 [ref=1x] - { InstDB::RWInfoRm::kCategoryFixed , 0x06, 16, 0, 0 }, // #66 [ref=12x] - { InstDB::RWInfoRm::kCategoryConsistent, 0x06, 0 , InstDB::RWInfoRm::kFlagFeatureIfRMI, uint32_t(CpuFeatures::X86::kAVX512_F) }, // #67 [ref=5x] - { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , InstDB::RWInfoRm::kFlagFeatureIfRMI, uint32_t(CpuFeatures::X86::kAVX512_BW) }, // #68 [ref=2x] - { InstDB::RWInfoRm::kCategoryConsistent, 0x06, 0 , InstDB::RWInfoRm::kFlagFeatureIfRMI, uint32_t(CpuFeatures::X86::kAVX512_BW) } // #69 [ref=3x] + { InstDB::RWInfoRm::kCategoryFixed , 0x01, 16, 0, 0 }, // #51 [ref=6x] + { InstDB::RWInfoRm::kCategoryFixed , 0x01, 32, 0, 0 }, // #52 [ref=4x] + { InstDB::RWInfoRm::kCategoryConsistent, 0x0C, 0 , 0, 0 }, // #53 [ref=15x] + { InstDB::RWInfoRm::kCategoryFixed , 0x0C, 8 , 0, 0 }, // #54 [ref=4x] + { InstDB::RWInfoRm::kCategoryFixed , 0x0C, 4 , 0, 0 }, // #55 [ref=4x] + { InstDB::RWInfoRm::kCategoryFixed , 0x04, 32, 0, 0 }, // #56 [ref=6x] + { InstDB::RWInfoRm::kCategoryConsistent, 0x03, 0 , 0, 0 }, // #57 [ref=13x] + { InstDB::RWInfoRm::kCategoryFixed , 0x03, 8 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #58 [ref=1x] + { InstDB::RWInfoRm::kCategoryConsistent, 0x08, 0 , 0, 0 }, // #59 [ref=2x] + { InstDB::RWInfoRm::kCategoryFixed , 0x04, 1 , 0, 0 }, // #60 [ref=1x] + { InstDB::RWInfoRm::kCategoryQuarter , 0x01, 0 , 0, 0 }, // #61 [ref=6x] + { InstDB::RWInfoRm::kCategoryEighth , 0x01, 0 , 0, 0 }, // #62 [ref=3x] + { InstDB::RWInfoRm::kCategoryEighth , 0x02, 0 , 0, 0 }, // #63 [ref=2x] + { InstDB::RWInfoRm::kCategoryFixed , 0x0C, 16, 0, 0 }, // #64 [ref=1x] + { InstDB::RWInfoRm::kCategoryFixed , 0x06, 16, 0, 0 }, // #65 [ref=12x] + { InstDB::RWInfoRm::kCategoryConsistent, 0x06, 0 , InstDB::RWInfoRm::kFlagFeatureIfRMI, uint32_t(CpuFeatures::X86::kAVX512_F) }, // #66 [ref=5x] + { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , InstDB::RWInfoRm::kFlagFeatureIfRMI, uint32_t(CpuFeatures::X86::kAVX512_BW) }, // #67 [ref=2x] + { InstDB::RWInfoRm::kCategoryConsistent, 0x06, 0 , InstDB::RWInfoRm::kFlagFeatureIfRMI, uint32_t(CpuFeatures::X86::kAVX512_BW) } // #68 [ref=3x] }; // ---------------------------------------------------------------------------- // ${InstRWInfoTable:End} diff --git a/src/asmjit/x86/x86instdb.h b/src/asmjit/x86/x86instdb.h index 2bf7d14..00623e2 100644 --- a/src/asmjit/x86/x86instdb.h +++ b/src/asmjit/x86/x86instdb.h @@ -319,8 +319,6 @@ enum class Avx512Flags : uint32_t { kB32 = 0x00000020u, //! Supports 64-bit broadcast 'b64'. kB64 = 0x00000040u, - //! Operates on a vector of consecutive registers (AVX512_4FMAPS and AVX512_4VNNIW). - kT4X = 0x00000080u, //! Implicit zeroing if {k} masking is used. Using {z} is not valid in this case as it's implicit. kImplicitZ = 0x00000100, diff --git a/src/asmjit/x86/x86instdb_p.h b/src/asmjit/x86/x86instdb_p.h index 335e17c..f53fe8a 100644 --- a/src/asmjit/x86/x86instdb_p.h +++ b/src/asmjit/x86/x86instdb_p.h @@ -122,7 +122,6 @@ enum EncodingId : uint32_t { kEncodingVexKmov, //!< VEX [RM|MR] (used by kmov[b|w|d|q]). kEncodingVexR_Wx, //!< VEX|EVEX [R] (propagatex VEX.W if GPQ used). kEncodingVexM, //!< VEX|EVEX [M]. - kEncodingVexM_VM, //!< VEX|EVEX [M] (propagates VEX|EVEX.L, VSIB support). kEncodingVexMr_Lx, //!< VEX|EVEX [MR] (propagates VEX|EVEX.L if YMM used). kEncodingVexMr_VM, //!< VEX|EVEX [MR] (VSIB support). kEncodingVexMri, //!< VEX|EVEX [MRI]. @@ -136,7 +135,6 @@ enum EncodingId : uint32_t { kEncodingVexRm_Lx_Narrow, //!< VEX|EVEX [RM] (the destination vector size is narrowed). kEncodingVexRm_Lx_Bcst, //!< VEX|EVEX [RM] (can handle broadcast r32/r64). kEncodingVexRm_VM, //!< VEX|EVEX [RM] (propagates VEX|EVEX.L, VSIB support). - kEncodingVexRm_T1_4X, //!< EVEX [RM] (used by NN instructions that use RM-T1_4X encoding). kEncodingVexRmi, //!< VEX|EVEX [RMI]. kEncodingVexRmi_Wx, //!< VEX|EVEX [RMI] (propagates VEX|EVEX.W if GPQ used). kEncodingVexRmi_Lx, //!< VEX|EVEX [RMI] (propagates VEX|EVEX.L if YMM used). @@ -288,9 +286,21 @@ extern const uint32_t _mainOpcodeTable[]; extern const uint32_t _altOpcodeTable[]; #ifndef ASMJIT_NO_TEXT + extern const InstNameIndex instNameIndex; extern const char _instNameStringTable[]; extern const uint32_t _instNameIndexTable[]; + +extern const char _aliasNameStringTable[]; +extern const uint32_t _aliasNameIndexTable[]; +extern const uint32_t _aliasIndexToInstId[]; + +// ${NameDataInfo:Begin} +// ------------------- Automatically generated, do not edit ------------------- +static constexpr uint32_t kAliasTableSize = 44; +// ---------------------------------------------------------------------------- +// ${NameDataInfo:End} + #endif // !ASMJIT_NO_TEXT extern const AdditionalInfo _additionalInfoTable[]; diff --git a/src/asmjit/x86/x86opcode_p.h b/src/asmjit/x86/x86opcode_p.h index ab0b13e..ba36a68 100644 --- a/src/asmjit/x86/x86opcode_p.h +++ b/src/asmjit/x86/x86opcode_p.h @@ -173,8 +173,6 @@ struct Opcode { kCDTT_FVM = kCDTT_ByLL, kCDTT_T1S = kCDTT_None, kCDTT_T1F = kCDTT_None, - kCDTT_T1_4X = kCDTT_None, - kCDTT_T4X = kCDTT_None, // Alias to have only 3 letters. kCDTT_T2 = kCDTT_None, kCDTT_T4 = kCDTT_None, kCDTT_T8 = kCDTT_None, diff --git a/test/asmjit_test_assembler_x64.cpp b/test/asmjit_test_assembler_x64.cpp index 786dd6e..7d7fe77 100644 --- a/test/asmjit_test_assembler_x64.cpp +++ b/test/asmjit_test_assembler_x64.cpp @@ -5545,14 +5545,6 @@ static void ASMJIT_NOINLINE testX64AssemblerAVX512(AssemblerTester 0 && /^(?:bndldx|bndstx)$/.test(dbInsts[0].name); + let mib = dbInsts.length > 0 && /^(?:bndldx|bndstx)$/.test(dbInsts[0].name); if (mib) f.Mib = true; - var mmx = false; - var vec = false; + let mmx = false; + let vec = false; - for (i = 0; i < dbInsts.length; i++) { + for (let i = 0; i < dbInsts.length; i++) { const dbInst = dbInsts[i]; const operands = dbInst.operands; @@ -222,7 +221,7 @@ class GenUtils { if (dbInst.name === "vzeroall" || dbInst.name === "vzeroupper") vec = true; - for (j = 0; j < operands.length; j++) { + for (let j = 0; j < operands.length; j++) { const op = operands[j]; if (op.reg === "mm") mmx = true; @@ -235,7 +234,7 @@ class GenUtils { if (mmx) f.Mmx = true; if (vec) f.Vec = true; - for (i = 0; i < dbInsts.length; i++) { + for (let i = 0; i < dbInsts.length; i++) { const dbInst = dbInsts[i]; const operands = dbInst.operands; @@ -249,7 +248,7 @@ class GenUtils { if (dbInst.k === "zeroing" ) f.Avx512ImplicitZ = true; if (dbInst.category.FPU) { - for (var j = 0; j < operands.length; j++) { + for (let j = 0; j < operands.length; j++) { const op = operands[j]; if (op.memSize === 16) f.FpuM16 = true; if (op.memSize === 32) f.FpuM32 = true; @@ -296,7 +295,7 @@ class GenUtils { } static eqOps(aOps, aFrom, bOps, bFrom) { - var x = 0; + let x = 0; for (;;) { const aIndex = x + aFrom; const bIndex = x + bFrom; @@ -462,7 +461,9 @@ class X86TableGen extends core.TableGen { // Get instructions (dbInsts) having the same name as understood by AsmJit. query(name) { - return x86isa.query(name); + return x86isa.query({ name: name, filter: function(inst) { + return !inst.ext.APX_F && !inst.ext.AVX10_1 && !inst.ext.AVX10_2; + }}); } // -------------------------------------------------------------------------- @@ -484,13 +485,13 @@ class X86TableGen extends core.TableGen { "([^\\)]+)" + "\\)", // [08] OperationDataIndex. "g"); - var m; + let m; while ((m = re.exec(data)) !== null) { - var enum_ = m[1]; - var name = enum_ === "None" ? "" : enum_.toLowerCase(); - var encoding = m[2].trim(); - var opcode0 = m[3].trim(); - var opcode1 = m[4].trim(); + let enum_ = m[1]; + let name = enum_ === "None" ? "" : enum_.toLowerCase(); + let encoding = m[2].trim(); + let opcode0 = m[3].trim(); + let opcode1 = m[4].trim(); const dbInsts = this.query(name); if (name && !dbInsts.length) @@ -500,7 +501,9 @@ class X86TableGen extends core.TableGen { const controlFlow = GenUtils.controlFlow(dbInsts); const singleRegCase = GenUtils.singleRegCase(name); - this.addInst({ + const aliasData = x86isa.aliasData(name); + + this.addInstruction({ id : 0, // Instruction id (numeric value). name : name, // Instruction name. displayName : name, // Instruction name to display. @@ -514,6 +517,8 @@ class X86TableGen extends core.TableGen { controlFlow : controlFlow, singleRegCase : singleRegCase, + aliases : aliasData, + mainOpcodeValue : -1, // Main opcode value (0.255 hex). mainOpcodeIndex : -1, // Index to InstDB::_mainOpcodeTable. altOpcodeIndex : -1, // Index to InstDB::_altOpcodeTable. @@ -533,7 +538,7 @@ class X86TableGen extends core.TableGen { } merge() { - var s = StringUtils.format(this.insts, "", true, function(inst) { + let s = StringUtils.format(this.insts, "", true, function(inst) { return "INST(" + String(inst.enum ).padEnd(17) + ", " + String(inst.encoding ).padEnd(19) + ", " + @@ -563,12 +568,12 @@ class X86TableGen extends core.TableGen { "wait" // Maps to `fwait`, which AsmJit uses instead. ]); - var out = ""; + let out = ""; x86isa.instructionNames.forEach(function(name) { - var dbInsts = x86isa.query(name); + let dbInsts = x86isa.query(name); if (!this.instMap[name] && ignored[name] !== true) { console.log(`MISSING INSTRUCTION '${name}'`); - var inst = this.newInstFromGroup(dbInsts); + let inst = this.newInstFromGroup(dbInsts); if (inst) { out += " INST(" + String(inst.enum ).padEnd(17) + ", " + @@ -593,10 +598,10 @@ class X86TableGen extends core.TableGen { } function GetAccess(dbInst) { - var operands = dbInst.operands; + let operands = dbInst.operands; if (!operands.length) return ""; - var op = operands[0]; + let op = operands[0]; if (op.read && op.write) return "RW"; else if (op.read) @@ -618,8 +623,8 @@ class X86TableGen extends core.TableGen { for (let j = 0; j < dbi.operands.length; j++) { s += ", "; const op = dbi.operands[j]; - var reg = op.reg; - var mem = op.mem; + let reg = op.reg; + let mem = op.mem; if (op.isReg() && op.isMem()) { if (choice == 0) mem = null; @@ -653,27 +658,27 @@ class X86TableGen extends core.TableGen { return results; } - var dbi = dbInsts[0]; + let dbi = dbInsts[0]; - var id = this.insts.length; - var name = dbi.name; - var enum_ = name[0].toUpperCase() + name.substr(1); + let id = this.insts.length; + let name = dbi.name; + let enum_ = name[0].toUpperCase() + name.substr(1); - var opcode = dbi.opcodeHex; - var modR = dbi.modR; - var mm = dbi.mm; - var pp = dbi.pp; - var encoding = dbi.encoding; - var isVec = isVecPrefix(dbi.prefix); - var evexCount = 0; + let opcode = dbi.opcode.byte; + let modR = dbi.opcode.modr; + let mm = dbi.opcode.mm; + let pp = dbi.opcode.pp; + let encoding = dbi.encoding; + let isVec = isVecPrefix(dbi.prefix); + let evexCount = 0; - var access = GetAccess(dbi); + let access = GetAccess(dbi); - var vexL = undefined; - var vexW = undefined; - var evexW = undefined; - var cdshl = "_"; - var tupleType = "_"; + let vexL = undefined; + let vexW = undefined; + let evexW = undefined; + let cdshl = "_"; + let tupleType = "_"; const tupleTypeToCDSHL = { "FVM": "4", @@ -687,12 +692,12 @@ class X86TableGen extends core.TableGen { const emitMap = {}; - for (var i = 0; i < dbInsts.length; i++) { + for (let i = 0; i < dbInsts.length; i++) { dbi = dbInsts[i]; if (dbi.prefix === "VEX" || dbi.prefix === "XOP") { - var newVexL = String(dbi.l === "128" ? 0 : dbi.l === "256" ? 1 : dbi.l === "512" ? 2 : "_"); - var newVexW = String(dbi.w === "W0" ? 0 : dbi.w === "W1" ? 1 : "_"); + let newVexL = String(dbi.opcode.l === "128" ? 0 : dbi.opcode.l === "256" ? 1 : dbi.opcode.l === "512" ? 2 : "_"); + let newVexW = String(dbi.opcode.w === "W0" ? 0 : dbi.opcode.w === "W1" ? 1 : "_"); if (vexL !== undefined && vexL !== newVexL) vexL = "x"; @@ -706,7 +711,7 @@ class X86TableGen extends core.TableGen { if (dbi.prefix === "EVEX") { evexCount++; - var newEvexW = String(dbi.w === "W0" ? 0 : dbi.w === "W1" ? 1 : "_"); + let newEvexW = String(dbi.opcode.w === "W0" ? 0 : dbi.opcode.w === "W1" ? 1 : "_"); if (evexW !== undefined && evexW !== newEvexW) evexW = "x"; else @@ -721,12 +726,12 @@ class X86TableGen extends core.TableGen { } } - if (opcode !== dbi.opcodeHex ) { console.log(`${dbi.name}: ISSUE: Opcode ${opcode} != ${dbi.opcodeHex}`); return null; } - if (modR !== dbi.modR ) { console.log(`${dbi.name}: ISSUE: ModR ${modR} != ${dbi.modR}`); return null; } - if (mm !== dbi.mm ) { console.log(`${dbi.name}: ISSUE: MM ${mm} != ${dbi.mm}`); return null; } - if (pp !== dbi.pp ) { console.log(`${dbi.name}: ISSUE: PP ${pp} != ${dbi.pp}`); return null; } - if (encoding !== dbi.encoding ) { console.log(`${dbi.name}: ISSUE: Enc ${encoding} != ${dbi.encoding}`); return null; } - if (access !== GetAccess(dbi)) { console.log(`${dbi.name}: ISSUE: Access ${access} != ${GetAccess(dbi)}`); return null; } + if (opcode !== dbi.opcode.byte) { console.log(`${dbi.name}: ISSUE: Opcode ${opcode} != ${dbi.opcode.byte}`); return null; } + if (modR !== dbi.opcode.modr) { console.log(`${dbi.name}: ISSUE: ModR ${modR} != ${dbi.opcode.modr}`); return null; } + if (mm !== dbi.opcode.mm ) { console.log(`${dbi.name}: ISSUE: MM ${mm} != ${dbi.opcode.mm}`); return null; } + if (pp !== dbi.opcode.pp ) { console.log(`${dbi.name}: ISSUE: PP ${pp} != ${dbi.opcode.pp}`); return null; } + if (encoding !== dbi.encoding ) { console.log(`${dbi.name}: ISSUE: Enc ${encoding} != ${dbi.encoding}`); return null; } + if (access !== GetAccess(dbi) ) { console.log(`${dbi.name}: ISSUE: Access ${access} != ${GetAccess(dbi)}`); return null; } if (isVec != isVecPrefix(dbi.prefix)) { console.log(`${dbi.name}: ISSUE: Vex/Non-Vex mismatch`); return null; } formatEmit(dbi).forEach((emit) => { @@ -740,10 +745,10 @@ class X86TableGen extends core.TableGen { if (tupleType !== "_") cdshl = tupleTypeToCDSHL[tupleType] || "?"; - var ppmm = pp.padEnd(2).replace(/ /g, "0") + + let ppmm = pp.padEnd(2).replace(/ /g, "0") + mm.padEnd(4).replace(/ /g, "0") ; - var composed = composeOpCode({ + let composed = composeOpCode({ type : evexCount == dbInsts.length ? "E" : isVec ? "V" : "O", prefix: ppmm, opcode: opcode, @@ -804,11 +809,11 @@ class IdEnum extends core.IdEnum { return features.filter(function(item) { return /^(AVX|FMA)/.test(item) === avx; }); } - var dbInsts = inst.dbInsts; + let dbInsts = inst.dbInsts; if (!dbInsts.length) return "Invalid instruction id."; - var text = ""; - var features = GenUtils.cpuFeaturesOf(dbInsts); + let text = ""; + let features = GenUtils.cpuFeaturesOf(dbInsts); const priorityFeatures = ["AVX_VNNI", "AVX_VNNI_INT8", "AVX_IFMA", "AVX_NE_CONVERT"]; @@ -840,7 +845,7 @@ class IdEnum extends core.IdEnum { text += "}"; } - var arch = GenUtils.cpuArchOf(dbInsts); + let arch = GenUtils.cpuArchOf(dbInsts); if (arch) text += (text ? " " : "") + arch; @@ -854,7 +859,7 @@ class IdEnum extends core.IdEnum { class NameTable extends core.NameTable { constructor() { - super("NameTable"); + super("NameTable", null, true); } } @@ -934,7 +939,7 @@ class AltOpcodeTable extends core.Task { if (opcode === "0") return ["00", 0]; - var opcodeByte = ""; + let opcodeByte = ""; const components = normalizeOpcodeComponents(splitOpcodeToComponents(opcode)); if (components[0] === "O_FPU") { @@ -1006,10 +1011,10 @@ const cmpOp = StringUtils.makePriorityCompare([ ]); function StringifyOpArray(a, map) { - var s = ""; - for (var i = 0; i < a.length; i++) { + let s = ""; + for (let i = 0; i < a.length; i++) { const op = a[i]; - var mapped = null; + let mapped = null; if (typeof map === "function") mapped = map(op); else if (hasOwn.call(map, op)) @@ -1039,11 +1044,10 @@ class OSignature { const af = this.flags; const bf = other.flags; - var k; - var indexKind = ""; - var hasReg = false; + let hasReg = false; + let indexKind = ""; - for (k in af) { + for (let k in af) { const index = asmdb.x86.Utils.regIndexOf(k); const kind = asmdb.x86.Utils.regKindOf(k); @@ -1055,7 +1059,7 @@ class OSignature { } if (hasReg) { - for (k in bf) { + for (let k in bf) { const index = asmdb.x86.Utils.regIndexOf(k); if (index !== null && index !== -1) { const kind = asmdb.x86.Utils.regKindOf(k); @@ -1066,20 +1070,20 @@ class OSignature { } // Can merge... - for (k in bf) + for (let k in bf) af[k] = true; return true; } toString() { - var s = ""; - var flags = this.flags; + let s = ""; + let flags = this.flags; - for (var k in flags) { + for (let k in flags) { if (k === "read" || k === "write" || k === "implicit" || k === "memDS" || k === "memES") continue; - var x = k; + let x = k; if (x === "memZAX") x = "zax"; if (x === "memZDI") x = "zdi"; if (x === "memZSI") x = "zsi"; @@ -1096,10 +1100,10 @@ class OSignature { } toAsmJitOpData() { - var opFlags = Object.create(null); - var regMask = 0; + let opFlags = Object.create(null); + let regMask = 0; - for (var k in this.flags) { + for (let k in this.flags) { switch (k) { case "r8lo" : opFlags.RegGpbLo = true; break; case "r8hi" : opFlags.RegGpbHi = true; break; @@ -1223,7 +1227,7 @@ class ISignature extends Array { const len = this.length; if (len !== other.length) return false; - for (var i = 0; i < len; i++) + for (let i = 0; i < len; i++) if (!this[i].equals(other[i])) return false; @@ -1239,8 +1243,9 @@ class ISignature extends Array { // ok = true; // It's not ok if both signatures have different number of implicit operands. - if (!sameArch || this.implicit !== other.implicit) + if (!sameArch || this.implicit !== other.implicit) { return false; + } // It's not ok if both signatures have different number of operands. const len = this.length; @@ -1250,7 +1255,8 @@ class ISignature extends Array { let xorIndex = -1; for (let i = 0; i < len; i++) { const xor = this[i].xor(other[i]); - if (xor === null) continue; + if (xor === null) + continue; if (xorIndex === -1) xorIndex = i; @@ -1258,7 +1264,7 @@ class ISignature extends Array { return false; } - // Bail if mergeWidth at operand-level failed. + // Bail if mergeWith at operand-level failed. if (xorIndex === -1 || !this[xorIndex].mergeWith(other[xorIndex])) return false; @@ -1271,12 +1277,16 @@ class ISignature extends Array { } class SignatureArray extends Array { + constructor(instructionName) { + super(); + this.instructionName = instructionName; + } // Iterate over all signatures and check which operands don't need explicit memory size. calcImplicitMemSize(instName) { // Calculates a hash-value (aka key) of all register operands specified by `regOps` in `inst`. function keyOf(inst, regOps) { - var s = ""; - for (var i = 0; i < inst.length; i++) { + let s = ""; + for (let i = 0; i < inst.length; i++) { const op = inst[i]; if (regOps & (1 << i)) s += "{" + ArrayUtils.sorted(ObjectUtils.and(op.flags, RegOp)).join("|") + "}"; @@ -1284,19 +1294,16 @@ class SignatureArray extends Array { return s || "?"; } - var i; - var aIndex, bIndex; - - for (aIndex = 0; aIndex < this.length; aIndex++) { + for (let aIndex = 0; aIndex < this.length; aIndex++) { const aInst = this[aIndex]; const len = aInst.length; - var memOp = ""; - var memPos = -1; - var regOps = 0; + let memOp = ""; + let memPos = -1; + let regOps = 0; // Check if this instruction signature has a memory operand of explicit size. - for (i = 0; i < len; i++) { + for (let i = 0; i < len; i++) { const aOp = aInst[i]; const mem = ObjectUtils.findKey(aOp.flags, MemOp); @@ -1328,12 +1335,12 @@ class SignatureArray extends Array { const diffSizeSet = []; const diffSizeHash = Object.create(null); - for (bIndex = 0; bIndex < this.length; bIndex++) { + for (let bIndex = 0; bIndex < this.length; bIndex++) { const bInst = this[bIndex]; if (aIndex === bIndex || len !== bInst.length) continue; - var hasMatch = 1; - for (i = 0; i < len; i++) { + let hasMatch = 1; + for (let i = 0; i < len; i++) { if (i === memPos) continue; const reg = ObjectUtils.hasAny(bInst[i].flags, RegOp); @@ -1368,14 +1375,14 @@ class SignatureArray extends Array { // // B) The memory operand has implicit-size if `diffSizeSet` contains different // register signatures than `sameSizeSet`. - var implicit = true; + let implicit = true; if (!diffSizeSet.length) { // Case A: } else { // Case B: Find collisions in `sameSizeSet` and `diffSizeSet`. - for (bIndex = 0; bIndex < sameSizeSet.length; bIndex++) { + for (let bIndex = 0; bIndex < sameSizeSet.length; bIndex++) { const bInst = sameSizeSet[bIndex]; const key = keyOf(bInst, regOps); @@ -1399,25 +1406,26 @@ class SignatureArray extends Array { } // Patch all instructions to accept implicit-size memory operand. - for (bIndex = 0; bIndex < sameSizeSet.length; bIndex++) { + for (let bIndex = 0; bIndex < sameSizeSet.length; bIndex++) { const bInst = sameSizeSet[bIndex]; if (implicit) { bInst[memPos].flags.mem = true; } - if (!implicit) + if (!implicit) { DEBUG(`${this.name}: Explicit: ${bInst}`); + } } } } compact() { - var didSomething = true; + let didSomething = true; while (didSomething) { didSomething = false; - for (var i = 0; i < this.length; i++) { - var row = this[i]; - var j = i + 1; + for (let i = 0; i < this.length; i++) { + let row = this[i]; + let j = i + 1; while (j < this.length) { if (row.mergeWith(this[j])) { this.splice(j, 1); @@ -1431,7 +1439,7 @@ class SignatureArray extends Array { } toString() { - return `[${this.join(", ")}]`; + return `[${this.join(",\n")}]`; } } @@ -1467,12 +1475,12 @@ class InstSignatureTable extends core.Task { const indexes = iSignatureMap[rows[0].data]; if (indexes === undefined) return -1; - for (var i = 0; i < indexes.length; i++) { + for (let i = 0; i < indexes.length; i++) { const index = indexes[i]; if (index + len > iSignatureArr.length) continue; - var ok = true; - for (var j = 0; j < len; j++) { + let ok = true; + for (let j = 0; j < len; j++) { if (iSignatureArr[index + j].data !== rows[j].data) { ok = false; break; @@ -1489,7 +1497,7 @@ class InstSignatureTable extends core.Task { function indexSignatures(signatures) { const result = iSignatureArr.length; - for (var i = 0; i < signatures.length; i++) { + for (let i = 0; i < signatures.length; i++) { const signature = signatures[i]; const idx = iSignatureArr.length; @@ -1503,21 +1511,21 @@ class InstSignatureTable extends core.Task { return result; } - for (var len = this.maxOpRows; len >= 0; len--) { + for (let len = this.maxOpRows; len >= 0; len--) { insts.forEach((inst) => { const signatures = inst.signatures; if (signatures.length === len) { const signatureEntries = []; - for (var j = 0; j < len; j++) { + for (let j = 0; j < len; j++) { const signature = signatures[j]; - var signatureEntry = `ROW(${signature.length}, ${signature.x86 ? 1 : 0}, ${signature.x64 ? 1 : 0}, ${signature.implicit}`; - var signatureComment = signature.toString(); + let signatureEntry = `ROW(${signature.length}, ${signature.x86 ? 1 : 0}, ${signature.x64 ? 1 : 0}, ${signature.implicit}`; + let signatureComment = signature.toString(); - var x = 0; + let x = 0; while (x < signature.length) { const h = signature[x].toAsmJitOpData(); - var index = -1; + let index = -1; if (!hasOwn.call(oSignatureMap, h)) { index = oSignatureArr.length; oSignatureMap[h] = index; @@ -1540,8 +1548,8 @@ class InstSignatureTable extends core.Task { signatureEntries.push({ data: signatureEntry, comment: signatureComment, refs: 0 }); } - var count = signatureEntries.length; - var index = findSignaturesIndex(signatureEntries); + let count = signatureEntries.length; + let index = findSignaturesIndex(signatureEntries); if (index === -1) index = indexSignatures(signatureEntries); @@ -1553,7 +1561,7 @@ class InstSignatureTable extends core.Task { }); } - var s = `#define ROW(count, x86, x64, implicit, o0, o1, o2, o3, o4, o5) \\\n` + + let s = `#define ROW(count, x86, x64, implicit, o0, o1, o2, o3, o4, o5) \\\n` + ` { count, uint8_t(x86 ? uint8_t(InstDB::Mode::kX86) : uint8_t(0)) | \\\n` + ` (x64 ? uint8_t(InstDB::Mode::kX64) : uint8_t(0)) , \\\n` + ` implicit, \\\n` + @@ -1573,9 +1581,9 @@ class InstSignatureTable extends core.Task { makeSignatures(dbInsts) { const instName = dbInsts.length ? dbInsts[0].name : ""; - const signatures = new SignatureArray(); + const signatures = new SignatureArray(instName); - for (var i = 0; i < dbInsts.length; i++) { + for (let i = 0; i < dbInsts.length; i++) { const inst = dbInsts[i]; const ops = inst.operands; @@ -1598,19 +1606,21 @@ class InstSignatureTable extends core.Task { // 1a. mov reg, reg // 1b. mov reg, mem // 2b. mov mem, reg - var modrmCount = 1; - for (var modrm = 0; modrm < modrmCount; modrm++) { - var row = new ISignature(inst.name); + let modrmCount = 1; + for (let modrm = 0; modrm < modrmCount; modrm++) { + let row = new ISignature(inst.name); + row.x86 = (inst.arch === "ANY" || inst.arch === "X86"); row.x64 = (inst.arch === "ANY" || inst.arch === "X64"); - for (var j = 0; j < ops.length; j++) { - var iop = ops[j]; + let j; + for (j = 0; j < ops.length; j++) { + let iop = ops[j]; - var reg = iop.reg; - var mem = iop.mem; - var imm = iop.imm; - var rel = iop.rel; + let reg = iop.reg; + let mem = iop.mem; + let imm = iop.imm; + let rel = iop.rel; // Skip all instructions having implicit `imm` operand of `1`. if (iop.immValue !== null) @@ -1731,8 +1741,9 @@ class InstSignatureTable extends core.Task { } // Not equal if we terminated the loop. - if (j === ops.length) + if (j === ops.length) { signatures.push(row); + } } } @@ -1765,10 +1776,10 @@ class AdditionalInfoTable extends core.Task { insts.forEach((inst) => { const dbInsts = inst.dbInsts; - var features = GenUtils.cpuFeaturesOf(dbInsts).map(function(f) { return `EXT(${f})`; }).join(", "); + let features = GenUtils.cpuFeaturesOf(dbInsts).map(function(f) { return `EXT(${f})`; }).join(", "); if (!features) features = "0"; - var [r, w] = this.rwFlagsOf(dbInsts); + let [r, w] = this.rwFlagsOf(dbInsts); const rData = r.map(function(flag) { return `FLAG(${flag})`; }).join(" | ") || "0"; const wData = w.map(function(flag) { return `FLAG(${flag})`; }).join(" | ") || "0"; const instFlags = Object.create(null); @@ -1815,7 +1826,7 @@ class AdditionalInfoTable extends core.Task { inst.additionalInfoIndex = additionaInfoTable.addIndexed(`{ ${instFlagsIndex}, ${rwInfoIndex}, { ${features} } }`); }); - var s = `#define EXT(VAL) uint32_t(CpuFeatures::X86::k##VAL)\n` + + let s = `#define EXT(VAL) uint32_t(CpuFeatures::X86::k##VAL)\n` + `const InstDB::AdditionalInfo InstDB::_additionalInfoTable[] = {\n${StringUtils.format(additionaInfoTable, kIndent, true)}\n};\n` + `#undef EXT\n` + `\n` + @@ -1833,7 +1844,7 @@ class AdditionalInfoTable extends core.Task { const r = Object.create(null); const w = Object.create(null); - for (var i = 0; i < dbInsts.length; i++) { + for (let i = 0; i < dbInsts.length; i++) { const dbInst = dbInsts[i]; // Omit special cases, this is handled well in C++ code. @@ -1848,8 +1859,8 @@ class AdditionalInfoTable extends core.Task { if (dbInst.name === "mov") continue; - for (var reg in regs) { - var flag = ""; + for (let reg in regs) { + let flag = ""; switch (reg) { case "CF": flag = "CF"; break; case "OF": flag = "OF"; break; @@ -2000,13 +2011,13 @@ class InstRWInfoTable extends core.Task { const rwInfoArray = [this.rwInfo(inst, o2Insts), this.rwInfo(inst, oxInsts)]; const rmInfoArray = [this.rmInfo(inst, o2Insts), this.rmInfo(inst, oxInsts)]; - for (var i = 0; i < 2; i++) { + for (let i = 0; i < 2; i++) { const rwInfo = rwInfoArray[i]; const rmInfo = rmInfoArray[i]; const rwOps = rwInfo.rwOps; const rwOpsIndex = []; - for (var j = 0; j < rwOps.length; j++) { + for (let j = 0; j < rwOps.length; j++) { const op = rwOps[j]; if (!op) { rwOpsIndex.push(this.opInfoTable.addIndexed(noOpInfo)); @@ -2066,7 +2077,7 @@ class InstRWInfoTable extends core.Task { } }); - var s = ""; + let s = ""; s += "const uint8_t InstDB::rwInfoIndexA[Inst::_kIdCount] = {\n" + StringUtils.format(this.rwInfoIndexA, kIndent, -1) + "\n};\n"; s += "\n"; s += "const uint8_t InstDB::rwInfoIndexB[Inst::_kIdCount] = {\n" + StringUtils.format(this.rwInfoIndexB, kIndent, -1) + "\n};\n"; @@ -2091,17 +2102,17 @@ class InstRWInfoTable extends core.Task { byteMaskFromBitRanges(ranges) { const arr = []; - for (var i = 0; i < 64; i++) + for (let i = 0; i < 64; i++) arr.push(0); - for (var i = 0; i < ranges.length; i++) { + for (let i = 0; i < ranges.length; i++) { const start = ranges[i].start; const end = ranges[i].end; if (start < 0) continue; - for (var j = start; j <= end; j++) { + for (let j = start; j <= end; j++) { const bytePos = j >> 3; if (bytePos < 0 || bytePos >= arr.length) FATAL(`Range ${start}:${end} cannot be used to create a byte-mask`); @@ -2109,8 +2120,8 @@ class InstRWInfoTable extends core.Task { } } - var s = "0x"; - for (var i = arr.length - 4; i >= 0; i -= 4) { + let s = "0x"; + for (let i = arr.length - 4; i >= 0; i -= 4) { const value = (arr[i + 3] << 3) | (arr[i + 2] << 2) | (arr[i + 1] << 1) | arr[i]; s += value.toString(16).toUpperCase(); } @@ -2142,18 +2153,18 @@ class InstRWInfoTable extends core.Task { } function queryRwGeneric(dbInsts, step) { - var rwOps = nullOps(); - for (var i = 0; i < dbInsts.length; i++) { + let rwOps = nullOps(); + for (let i = 0; i < dbInsts.length; i++) { const dbInst = dbInsts[i]; const operands = dbInst.operands; - for (var j = 0; j < operands.length; j++) { + for (let j = 0; j < operands.length; j++) { const op = operands[j]; if (!op.isRegOrMem()) continue; const opSize = op.isReg() ? op.regSize : op.memSize; - var d = { + let d = { access: op.read && op.write ? "X" : op.read ? "R" : op.write ? "W" : "?", clc: 0, flags: {}, @@ -2192,7 +2203,7 @@ class InstRWInfoTable extends core.Task { if (op.regIndexRel) d.flags.Consecutive = true; - for (var k in self.rwOpFlagsForInstruction(asmInst.name, j)) + for (let k in self.rwOpFlagsForInstruction(asmInst.name, j)) d.flags[k] = true; if ((step === -1 || step === j) || op.rwxIndex !== 0 || op.rwxWidth !== opSize) { @@ -2234,17 +2245,17 @@ class InstRWInfoTable extends core.Task { } function queryRwByData(dbInsts, rwOpsArray) { - for (var i = 0; i < dbInsts.length; i++) { + for (let i = 0; i < dbInsts.length; i++) { const dbInst = dbInsts[i]; const operands = dbInst.operands; const rwOps = nullOps(); - for (var j = 0; j < operands.length; j++) { + for (let j = 0; j < operands.length; j++) { rwOps[j] = makeRwFromOp(operands[j]) } - var match = 0; - for (var j = 0; j < rwOpsArray.length; j++) + let match = 0; + for (let j = 0; j < rwOpsArray.length; j++) match |= ObjectUtils.equals(rwOps, rwOpsArray[j]); if (!match) @@ -2256,12 +2267,12 @@ class InstRWInfoTable extends core.Task { function dumpRwToData(dbInsts) { const out = []; - for (var i = 0; i < dbInsts.length; i++) { + for (let i = 0; i < dbInsts.length; i++) { const dbInst = dbInsts[i]; const operands = dbInst.operands; const rwOps = nullOps(); - for (var j = 0; j < operands.length; j++) + for (let j = 0; j < operands.length; j++) rwOps[j] = makeRwFromOp(operands[j]) if (ArrayUtils.deepIndexOf(out, rwOps) !== -1) @@ -2278,18 +2289,18 @@ class InstRWInfoTable extends core.Task { return { category: this.rwCategoryByName[name], rwOps: nullOps() }; // Generic rules. - for (var i = -1; i <= 6; i++) { + for (let i = -1; i <= 6; i++) { const rwInfo = queryRwGeneric(dbInsts, i); if (rwInfo) return rwInfo; } // Specific rules. - for (var k in this.rwCategoryByData) + for (let k in this.rwCategoryByData) if (queryRwByData(dbInsts, this.rwCategoryByData[k])) return { category: k, rwOps: nullOps() }; - // FATALURE: Missing data to categorize this instruction. + // FATAL: Missing data to categorize this instruction. if (name) { const items = dumpRwToData(dbInsts) console.log(`RW: ${dbInsts.length ? dbInsts[0].name : ""}:`); @@ -2345,16 +2356,16 @@ class InstRWInfoTable extends core.Task { } rmReplaceableCategory(dbInsts) { - var category = null; + let category = null; - for (var i = 0; i < dbInsts.length; i++) { + for (let i = 0; i < dbInsts.length; i++) { const dbInst = dbInsts[i]; const operands = dbInst.operands; - var rs = -1; - var ms = -1; + let rs = -1; + let ms = -1; - for (var j = 0; j < operands.length; j++) { + for (let j = 0; j < operands.length; j++) { const op = operands[j]; if (op.isMem()) ms = op.memSize; @@ -2362,7 +2373,7 @@ class InstRWInfoTable extends core.Task { rs = Math.max(rs, op.regSize); } - var c = (rs === -1 ) ? "None" : + let c = (rs === -1 ) ? "None" : (ms === -1 ) ? "None" : (ms === rs ) ? "Fixed" : (ms === rs / 2) ? "Half" : @@ -2391,9 +2402,9 @@ class InstRWInfoTable extends core.Task { rmReplaceableIndexes(dbInsts) { function maskOf(inst, fn) { - var m = 0; - var operands = inst.operands; - for (var i = 0; i < operands.length; i++) + let m = 0; + let operands = inst.operands; + for (let i = 0; i < operands.length; i++) if (fn(operands[i])) m |= (1 << i); return m; @@ -2402,19 +2413,19 @@ class InstRWInfoTable extends core.Task { function getRegIndexes(inst) { return maskOf(inst, function(op) { return op.isReg(); }); }; function getMemIndexes(inst) { return maskOf(inst, function(op) { return op.isMem(); }); }; - var mask = 0; + let mask = 0; - for (var i = 0; i < dbInsts.length; i++) { + for (let i = 0; i < dbInsts.length; i++) { const dbInst = dbInsts[i]; - var mi = getMemIndexes(dbInst); - var ri = getRegIndexes(dbInst) & ~mi; + let mi = getMemIndexes(dbInst); + let ri = getRegIndexes(dbInst) & ~mi; if (!mi) continue; const match = dbInsts.some((inst) => { - var ti = getRegIndexes(inst); + let ti = getRegIndexes(inst); return ((ri & ti) === ri && (mi & ti) === mi); }); @@ -2427,13 +2438,13 @@ class InstRWInfoTable extends core.Task { } rmFixedSize(insts) { - var savedOp = null; + let savedOp = null; - for (var i = 0; i < insts.length; i++) { + for (let i = 0; i < insts.length; i++) { const inst = insts[i]; const operands = inst.operands; - for (var j = 0; j < operands.length; j++) { + for (let j = 0; j < operands.length; j++) { const op = operands[j]; if (op.mem) { if (savedOp && savedOp.mem !== op.mem) @@ -2447,11 +2458,11 @@ class InstRWInfoTable extends core.Task { } rmIsConsistent(insts) { - var hasMem = 0; - for (var i = 0; i < insts.length; i++) { + let hasMem = 0; + for (let i = 0; i < insts.length; i++) { const inst = insts[i]; const operands = inst.operands; - for (var j = 0; j < operands.length; j++) { + for (let j = 0; j < operands.length; j++) { const op = operands[j]; if (op.mem) { hasMem = 1; @@ -2470,16 +2481,16 @@ class InstRWInfoTable extends core.Task { const memMap = {}; const immMap = {}; - for (var i = 0; i < dbInsts.length; i++) { + for (let i = 0; i < dbInsts.length; i++) { const dbInst = dbInsts[i]; const operands = dbInst.operands; - var memStr = ""; - var immStr = ""; - var hasMem = false; - var hasImm = false; + let memStr = ""; + let immStr = ""; + let hasMem = false; + let hasImm = false; - for (var j = 0; j < operands.length; j++) { + for (let j = 0; j < operands.length; j++) { const op = operands[j]; if (j) { memStr += ", "; @@ -2607,7 +2618,7 @@ class InstCommonTable extends core.Task { inst.commonInfoIndex = table.addIndexed(row); }); - var s = `#define F(VAL) uint32_t(InstDB::InstFlags::k##VAL)\n` + + let s = `#define F(VAL) uint32_t(InstDB::InstFlags::k##VAL)\n` + `#define X(VAL) uint32_t(InstDB::Avx512Flags::k##VAL)\n` + `#define CONTROL_FLOW(VAL) uint8_t(InstControlFlow::k##VAL)\n` + `#define SAME_REG_HINT(VAL) uint8_t(InstSameRegHint::k##VAL)\n` + diff --git a/tools/tablegen.js b/tools/tablegen.js index a151805..5c1eb17 100644 --- a/tools/tablegen.js +++ b/tools/tablegen.js @@ -56,35 +56,50 @@ class InstructionNameData { this.maxNameLength = 0; } - add(s) { - // First try to encode the string with 5-bit characters that fit into a 32-bit int. - if (/^[a-z0-4]{0,6}$/.test(s)) { - let index = 0; - for (let i = 0; i < s.length; i++) - index |= charTo5Bit(s[i]) << (i * 5); + add(name, alt) { + if (name === alt) { + alt = ""; + } - this.names.push(s); + if (this.maxNameLength < name.length) { + this.maxNameLength = name.length; + } + + this.names.push(name); + + // First try to encode the string with 5-bit characters that fit into a 32-bit int. + if (/^[a-z0-4]{0,6}$/.test(name) && !alt) { + let index = 0; + for (let i = 0; i < name.length; i++) { + index |= charTo5Bit(name[i]) << (i * 5); + } + + this.indexComment.push(`Small '${name}'.`); this.primaryTable.push(index | (1 << 31)); - this.indexComment.push(`Small '${s}'.`); + } + else if (alt) { + const prefixIndex = this.addOrReferenceString(name + String.fromCharCode(alt.length) + alt); + + if (name === "jz") { + console.log(`jz prefix: ${prefixIndex}`); + } + + this.indexComment.push(`Large '${name}' + '${alt}'`); + this.primaryTable.push(prefixIndex | (name.length << 12) | (0xFFF << 16) | 0); } else { - // Put the string into a string table. - this.names.push(s); - this.primaryTable.push(-1); this.indexComment.push(``); + this.primaryTable.push(0); } - - if (this.maxNameLength < s.length) - this.maxNameLength = s.length; } index() { const kMaxPrefixSize = 15; - const kMaxSuffixSize = 7; + const kMaxSuffixSize = 6; const names = []; for (let idx = 0; idx < this.primaryTable.length; idx++) { - if (this.primaryTable[idx] === -1) { + if (this.primaryTable[idx] === 0) { names.push({ name: this.names[idx], index: idx }); } } @@ -205,11 +220,20 @@ class InstructionNameData { FATAL(`IndexedString.formatStringTable(): Not indexed yet, call index()`); let s = ""; - for (let i = 0; i < this.stringTable.length; i += 80) { - if (s) - s += "\n" - s += '"' + this.stringTable.substring(i, i + 80) + '"'; + let line = ""; + + for (let i = 0; i < this.stringTable.length; i++) { + const c = this.stringTable.charCodeAt(i); + line += "\\x" + cxx.Utils.toHexRaw(c, 2); + + if (line.length >= 115 || i === this.stringTable.length - 1) { + if (s) + s += "\n" + s += `"${line}"`; + line = ""; + } } + s += ";\n"; return `const char ${tableName}[] =\n${StringUtils.indent(s, " ")}\n`; @@ -288,7 +312,9 @@ class Injector { const path = kAsmJitRoot + "/" + file; console.log(`MODIFIED '${file}'`); - fs.writeFileSync(path + ".backup", obj.prev, "utf8"); + if (!fs.existsSync(path + ".backup")) { + fs.writeFileSync(path + ".backup", obj.prev, "utf8"); + } fs.writeFileSync(path, obj.data, "utf8"); } } @@ -346,7 +372,7 @@ exports.Injector = Injector; // Main context used to load, generate, and store instruction tables. The idea // is to be extensible, so it stores 'Task's to be executed with minimal deps // management. -class TableGen extends Injector{ +class TableGen extends Injector { constructor(arch) { super(); @@ -418,7 +444,7 @@ class TableGen extends Injector{ // [Instruction Management] // -------------------------------------------------------------------------- - addInst(inst) { + addInstruction(inst) { if (this.instMap[inst.name]) FATAL(`TableGen.addInst(): Instruction '${inst.name}' already added`); @@ -471,19 +497,35 @@ class IdEnum extends Task { run() { const insts = this.ctx.insts; - var s = ""; - for (var i = 0; i < insts.length; i++) { + let s = ""; + let aliases = ""; + + for (let i = 0; i < insts.length; i++) { const inst = insts[i]; - var line = "kId" + inst.enum + (i ? "" : " = 0") + ","; - var text = this.comment(inst); + let line = "kId" + inst.enum + (i ? "" : " = 0") + ","; + let text = this.comment(inst); if (text) line = line.padEnd(37) + "//!< " + text; s += line + "\n"; + + if (inst.aliases) { + for (let aliasName of inst.aliases.aliasNames) { + if (aliases) aliases += ",\n"; + aliases += `kId${StringUtils.makeEnumName(aliasName)} = kId${inst.enum}`; + } + } + } + s += "_kIdCount"; + + if (aliases) { + s += ",\n\n" + "// Aliases.\n" + aliases + "\n"; + } + else { + s += "\n"; } - s += "_kIdCount\n"; return this.ctx.inject("InstId", s); } @@ -507,16 +549,43 @@ class Output { }; exports.Output = Output; -function generateNameData(out, instructions) { +function cmp(a, b) { return (a < b) ? -1 : a > b ? 1 : 0; } + +function generateNameData(out, instructions, generateAliases) { const none = "Inst::kIdNone"; + const aliases = []; + const aliasNameData = new InstructionNameData(); + const aliasLinkData = []; + const instFirst = new Array(26); const instLast = new Array(26); const instNameData = new InstructionNameData(); - for (let i = 0; i < instructions.length; i++) - instNameData.add(instructions[i].displayName); + for (let i = 0; i < instructions.length; i++) { + const instruction = instructions[i]; + + if (instruction.aliases) { + instNameData.add(instruction.displayName, instruction.aliases.format); + for (let aliasName of instruction.aliases.aliasNames) { + aliases.push({ name: instruction.name, alt: aliasName }); + } + } + else { + instNameData.add(instruction.displayName); + } + } + + aliases.sort(function(a, b) { return cmp(a.alt, b.alt); }); + + for (let i = 0; i < aliases.length; i++) { + const alias = aliases[i]; + aliasNameData.add(alias.alt); + aliasLinkData.push(`Inst::kId${StringUtils.makeEnumName(alias.name)}`); + } + instNameData.index(); + aliasNameData.index(); for (let i = 0; i < instructions.length; i++) { const inst = instructions[i]; @@ -548,21 +617,41 @@ function generateNameData(out, instructions) { s += `\n`; s += instNameData.formatIndexTable("InstDB::_instNameIndexTable"); - const dataSize = instNameData.getSize() + 26 * 4; + let dataSize = instNameData.getSize() + 26 * 4; + + if (generateAliases) { + s += `\n`; + s += aliasNameData.formatStringTable("InstDB::_aliasNameStringTable"); + s += `\n`; + s += aliasNameData.formatIndexTable("InstDB::_aliasNameIndexTable"); + s += "\n"; + s += "const uint32_t InstDB::_aliasIndexToInstId[] = {\n" + StringUtils.format(aliasLinkData, " ", true, null) + "\n};\n"; + + dataSize += aliasNameData.getSize(); + let info = `static constexpr uint32_t kAliasTableSize = ${aliasLinkData.length};\n`; + out.add("NameDataInfo", StringUtils.disclaimer(info), 0); + } + out.add("NameData", StringUtils.disclaimer(s), dataSize); return out; } exports.generateNameData = generateNameData; class NameTable extends Task { - constructor(name, deps) { + constructor(name, deps, generateAliases) { super(name || "NameTable", deps); + this.generateAliases = generateAliases; } run() { const output = new Output(); - generateNameData(output, this.ctx.insts); + generateNameData(output, this.ctx.insts, this.generateAliases); + this.ctx.inject("NameData", output.content["NameData"], output.tableSize["NameData"]); + + if (this.generateAliases) { + this.ctx.inject("NameDataInfo", output.content["NameDataInfo"], output.tableSize["NameDataInfo"]); + } } } exports.NameTable = NameTable;