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https://github.com/stashapp/stash.git
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Update chromedp to fix console errors (#1521)
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peolic
161
vendor/golang.org/x/sys/cpu/cpu.go
generated
vendored
161
vendor/golang.org/x/sys/cpu/cpu.go
generated
vendored
@@ -6,6 +6,11 @@
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// various CPU architectures.
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package cpu
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import (
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"os"
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"strings"
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)
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// Initialized reports whether the CPU features were initialized.
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//
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// For some GOOS/GOARCH combinations initialization of the CPU features depends
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@@ -24,26 +29,46 @@ type CacheLinePad struct{ _ [cacheLineSize]byte }
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// and HasAVX2 are only set if the OS supports XMM and YMM
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// registers in addition to the CPUID feature bit being set.
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var X86 struct {
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_ CacheLinePad
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HasAES bool // AES hardware implementation (AES NI)
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HasADX bool // Multi-precision add-carry instruction extensions
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HasAVX bool // Advanced vector extension
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HasAVX2 bool // Advanced vector extension 2
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HasBMI1 bool // Bit manipulation instruction set 1
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HasBMI2 bool // Bit manipulation instruction set 2
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HasERMS bool // Enhanced REP for MOVSB and STOSB
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HasFMA bool // Fused-multiply-add instructions
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HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
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HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
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HasPOPCNT bool // Hamming weight instruction POPCNT.
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HasRDRAND bool // RDRAND instruction (on-chip random number generator)
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HasRDSEED bool // RDSEED instruction (on-chip random number generator)
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HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
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HasSSE3 bool // Streaming SIMD extension 3
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HasSSSE3 bool // Supplemental streaming SIMD extension 3
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HasSSE41 bool // Streaming SIMD extension 4 and 4.1
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HasSSE42 bool // Streaming SIMD extension 4 and 4.2
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_ CacheLinePad
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_ CacheLinePad
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HasAES bool // AES hardware implementation (AES NI)
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HasADX bool // Multi-precision add-carry instruction extensions
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HasAVX bool // Advanced vector extension
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HasAVX2 bool // Advanced vector extension 2
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HasAVX512 bool // Advanced vector extension 512
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HasAVX512F bool // Advanced vector extension 512 Foundation Instructions
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HasAVX512CD bool // Advanced vector extension 512 Conflict Detection Instructions
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HasAVX512ER bool // Advanced vector extension 512 Exponential and Reciprocal Instructions
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HasAVX512PF bool // Advanced vector extension 512 Prefetch Instructions Instructions
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HasAVX512VL bool // Advanced vector extension 512 Vector Length Extensions
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HasAVX512BW bool // Advanced vector extension 512 Byte and Word Instructions
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HasAVX512DQ bool // Advanced vector extension 512 Doubleword and Quadword Instructions
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HasAVX512IFMA bool // Advanced vector extension 512 Integer Fused Multiply Add
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HasAVX512VBMI bool // Advanced vector extension 512 Vector Byte Manipulation Instructions
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HasAVX5124VNNIW bool // Advanced vector extension 512 Vector Neural Network Instructions Word variable precision
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HasAVX5124FMAPS bool // Advanced vector extension 512 Fused Multiply Accumulation Packed Single precision
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HasAVX512VPOPCNTDQ bool // Advanced vector extension 512 Double and quad word population count instructions
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HasAVX512VPCLMULQDQ bool // Advanced vector extension 512 Vector carry-less multiply operations
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HasAVX512VNNI bool // Advanced vector extension 512 Vector Neural Network Instructions
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HasAVX512GFNI bool // Advanced vector extension 512 Galois field New Instructions
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HasAVX512VAES bool // Advanced vector extension 512 Vector AES instructions
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HasAVX512VBMI2 bool // Advanced vector extension 512 Vector Byte Manipulation Instructions 2
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HasAVX512BITALG bool // Advanced vector extension 512 Bit Algorithms
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HasAVX512BF16 bool // Advanced vector extension 512 BFloat16 Instructions
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HasBMI1 bool // Bit manipulation instruction set 1
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HasBMI2 bool // Bit manipulation instruction set 2
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HasERMS bool // Enhanced REP for MOVSB and STOSB
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HasFMA bool // Fused-multiply-add instructions
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HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers.
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HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM
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HasPOPCNT bool // Hamming weight instruction POPCNT.
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HasRDRAND bool // RDRAND instruction (on-chip random number generator)
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HasRDSEED bool // RDSEED instruction (on-chip random number generator)
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HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64)
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HasSSE3 bool // Streaming SIMD extension 3
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HasSSSE3 bool // Supplemental streaming SIMD extension 3
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HasSSE41 bool // Streaming SIMD extension 4 and 4.1
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HasSSE42 bool // Streaming SIMD extension 4 and 4.2
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_ CacheLinePad
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}
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// ARM64 contains the supported CPU features of the
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@@ -129,14 +154,13 @@ var MIPS64X struct {
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// For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
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// since there are no optional categories. There are some exceptions that also
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// require kernel support to work (DARN, SCV), so there are feature bits for
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// those as well. The minimum processor requirement is POWER8 (ISA 2.07).
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// The struct is padded to avoid false sharing.
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// those as well. The struct is padded to avoid false sharing.
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var PPC64 struct {
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_ CacheLinePad
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HasDARN bool // Hardware random number generator (requires kernel enablement)
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HasSCV bool // Syscall vectored (requires kernel enablement)
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IsPOWER8 bool // ISA v2.07 (POWER8)
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IsPOWER9 bool // ISA v3.00 (POWER9)
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IsPOWER9 bool // ISA v3.00 (POWER9), implies IsPOWER8
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_ CacheLinePad
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}
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@@ -169,3 +193,94 @@ var S390X struct {
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HasVXE bool // vector-enhancements facility 1
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_ CacheLinePad
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}
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func init() {
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archInit()
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initOptions()
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processOptions()
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}
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// options contains the cpu debug options that can be used in GODEBUG.
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// Options are arch dependent and are added by the arch specific initOptions functions.
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// Features that are mandatory for the specific GOARCH should have the Required field set
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// (e.g. SSE2 on amd64).
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var options []option
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// Option names should be lower case. e.g. avx instead of AVX.
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type option struct {
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Name string
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Feature *bool
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Specified bool // whether feature value was specified in GODEBUG
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Enable bool // whether feature should be enabled
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Required bool // whether feature is mandatory and can not be disabled
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}
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func processOptions() {
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env := os.Getenv("GODEBUG")
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field:
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for env != "" {
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field := ""
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i := strings.IndexByte(env, ',')
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if i < 0 {
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field, env = env, ""
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} else {
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field, env = env[:i], env[i+1:]
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}
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if len(field) < 4 || field[:4] != "cpu." {
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continue
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}
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i = strings.IndexByte(field, '=')
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if i < 0 {
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print("GODEBUG sys/cpu: no value specified for \"", field, "\"\n")
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continue
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}
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key, value := field[4:i], field[i+1:] // e.g. "SSE2", "on"
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var enable bool
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switch value {
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case "on":
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enable = true
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case "off":
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enable = false
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default:
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print("GODEBUG sys/cpu: value \"", value, "\" not supported for cpu option \"", key, "\"\n")
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continue field
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}
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if key == "all" {
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for i := range options {
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options[i].Specified = true
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options[i].Enable = enable || options[i].Required
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}
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continue field
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}
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for i := range options {
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if options[i].Name == key {
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options[i].Specified = true
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options[i].Enable = enable
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continue field
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}
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}
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print("GODEBUG sys/cpu: unknown cpu feature \"", key, "\"\n")
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}
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for _, o := range options {
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if !o.Specified {
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continue
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}
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if o.Enable && !*o.Feature {
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print("GODEBUG sys/cpu: can not enable \"", o.Name, "\", missing CPU support\n")
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continue
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}
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if !o.Enable && o.Required {
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print("GODEBUG sys/cpu: can not disable \"", o.Name, "\", required CPU feature\n")
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continue
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}
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*o.Feature = o.Enable
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}
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}
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