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https://github.com/asmjit/asmjit.git
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* Removed AVX512_ER, AVX512_PF, AVX512_4FMAPS, and AVX512_4VNNIW
extensions and corresponding instructions (these were never
advertised by any x86 CPU and were only used by Xeon Phi acc.,
which AsmJit never supported)
* Removed CPU extensions HLE, MPX, and TSX
* Kept extension RTM, which is only for backward compatibility to
recognize instructions, but it's no longer checked by CpuInfo as
it's been deprecated together with HLE and MPX
* The xtest instruction now reports it requires RTM
* Reorganized x86 extensions a bit - they are now reordered to group
them by category, preparing for the future where extension IDs will
be always added after existing records for ABI compatibility
* Instruction vcvtneps2bf16 no longer accepts form without an explicit
memory operand size
* Removed aliased instructions in CMOVcc, Jcc, And SETcc categories,
now there is only a single instruction id for all aliased instructions.
* Added a new feature to always show instruction aliases in Logger, which
includes formatting instructio nodes (Builder, Compiler)
Instruction DB-only updates (not applied to C++ yet):
* AsmJit DB from now uses the same license as AsmJit (Zlib) and
no longer applies dual licensing (Zlib and Public Domain)
* Added support for aggregated instruction definitions in
x86 instruction database, which should simplify the maintenance
and reduce bugs (also the syntax is comparable to descriptions
used by Intel APX instruction manuals)
* Added support for APX instructions and new features
* Added support for AVX10.1 and AVX10.2 instructions (both new
instructions and new encodings of existing instructions)
* Added support for MOVRS instructions
* Added support for KL instructions (loadiwkey)
* Added support for AESKLE instructions
* Added support for AESKLEWIDE_KL instructions
* Added support for AMX_[AVX512|MOVRS|FP8|TF32|TRANSPOSE]
* NOTE: None of the instruction additions is currently used by
Asmjit, it's a pure database update that needs more work to
make all the instructions available in future AsmJit
200 lines
6.3 KiB
C++
200 lines
6.3 KiB
C++
// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#include <asmjit/core.h>
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#if !defined(ASMJIT_NO_X86)
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#include <asmjit/x86.h>
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#endif
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#include <stdio.h>
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using namespace asmjit;
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namespace {
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#if !defined(ASMJIT_NO_X86)
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static char accessLetter(bool r, bool w) noexcept {
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return r && w ? 'X' : r ? 'R' : w ? 'W' : '_';
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}
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static void printInfo(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount) {
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StringTmp<512> sb;
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// Read & Write Information
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// ------------------------
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InstRWInfo rw;
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InstAPI::queryRWInfo(arch, inst, operands, opCount, &rw);
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#ifndef ASMJIT_NO_LOGGING
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Formatter::formatInstruction(sb, FormatFlags::kNone, nullptr, arch, inst, operands, opCount);
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#else
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sb.append("<Logging-Not-Available>");
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#endif
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sb.append("\n");
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sb.append(" Operands:\n");
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for (uint32_t i = 0; i < rw.opCount(); i++) {
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const OpRWInfo& op = rw.operand(i);
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sb.appendFormat(" [%u] Op=%c Read=%016llX Write=%016llX Extend=%016llX",
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i,
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accessLetter(op.isRead(), op.isWrite()),
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op.readByteMask(),
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op.writeByteMask(),
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op.extendByteMask());
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if (op.isMemBaseUsed()) {
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sb.appendFormat(" Base=%c", accessLetter(op.isMemBaseRead(), op.isMemBaseWrite()));
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if (op.isMemBasePreModify())
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sb.appendFormat(" <PRE>");
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if (op.isMemBasePostModify())
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sb.appendFormat(" <POST>");
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}
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if (op.isMemIndexUsed()) {
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sb.appendFormat(" Index=%c", accessLetter(op.isMemIndexRead(), op.isMemIndexWrite()));
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}
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sb.append("\n");
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}
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// CPU Flags (Read/Write)
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// ----------------------
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if ((rw.readFlags() | rw.writeFlags()) != CpuRWFlags::kNone) {
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sb.append(" Flags: \n");
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struct FlagMap {
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CpuRWFlags flag;
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char name[4];
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};
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static const FlagMap flagMap[] = {
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{ CpuRWFlags::kX86_CF, "CF" },
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{ CpuRWFlags::kX86_OF, "OF" },
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{ CpuRWFlags::kX86_SF, "SF" },
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{ CpuRWFlags::kX86_ZF, "ZF" },
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{ CpuRWFlags::kX86_AF, "AF" },
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{ CpuRWFlags::kX86_PF, "PF" },
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{ CpuRWFlags::kX86_DF, "DF" },
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{ CpuRWFlags::kX86_IF, "IF" },
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{ CpuRWFlags::kX86_AC, "AC" },
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{ CpuRWFlags::kX86_C0, "C0" },
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{ CpuRWFlags::kX86_C1, "C1" },
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{ CpuRWFlags::kX86_C2, "C2" },
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{ CpuRWFlags::kX86_C3, "C3" }
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};
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sb.append(" ");
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for (uint32_t f = 0; f < 13; f++) {
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char c = accessLetter((rw.readFlags() & flagMap[f].flag) != CpuRWFlags::kNone,
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(rw.writeFlags() & flagMap[f].flag) != CpuRWFlags::kNone);
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if (c != '_')
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sb.appendFormat("%s=%c ", flagMap[f].name, c);
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}
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sb.append("\n");
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}
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// CPU Features
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// ------------
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CpuFeatures features;
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InstAPI::queryFeatures(arch, inst, operands, opCount, &features);
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#ifndef ASMJIT_NO_LOGGING
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if (!features.empty()) {
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sb.append(" Features:\n");
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sb.append(" ");
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bool first = true;
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CpuFeatures::Iterator it(features.iterator());
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while (it.hasNext()) {
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uint32_t featureId = uint32_t(it.next());
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if (!first)
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sb.append(" & ");
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Formatter::formatFeature(sb, arch, featureId);
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first = false;
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}
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sb.append("\n");
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}
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#endif
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printf("%s\n", sb.data());
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}
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template<typename... Args>
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static void printInfoSimple(Arch arch,InstId instId, InstOptions options, Args&&... args) {
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BaseInst inst(instId);
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inst.addOptions(options);
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Operand_ opArray[] = { std::forward<Args>(args)... };
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printInfo(arch, inst, opArray, sizeof...(args));
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}
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template<typename... Args>
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static void printInfoExtra(Arch arch, InstId instId, InstOptions options, const BaseReg& extraReg, Args&&... args) {
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BaseInst inst(instId);
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inst.addOptions(options);
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inst.setExtraReg(extraReg);
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Operand_ opArray[] = { std::forward<Args>(args)... };
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printInfo(arch, inst, opArray, sizeof...(args));
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}
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#endif // !ASMJIT_NO_X86
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static void testX86Arch() {
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#if !defined(ASMJIT_NO_X86)
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using namespace x86;
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Arch arch = Arch::kX64;
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printInfoSimple(arch, Inst::kIdAdd, InstOptions::kNone, eax, ebx);
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printInfoSimple(arch, Inst::kIdXor, InstOptions::kNone, eax, eax);
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printInfoSimple(arch, Inst::kIdLods, InstOptions::kNone, eax, dword_ptr(rsi));
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printInfoSimple(arch, Inst::kIdPshufd, InstOptions::kNone, xmm0, xmm1, imm(0));
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printInfoSimple(arch, Inst::kIdPabsb, InstOptions::kNone, mm1, mm2);
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printInfoSimple(arch, Inst::kIdPabsb, InstOptions::kNone, xmm1, xmm2);
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printInfoSimple(arch, Inst::kIdPextrw, InstOptions::kNone, eax, mm1, imm(0));
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printInfoSimple(arch, Inst::kIdPextrw, InstOptions::kNone, eax, xmm1, imm(0));
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printInfoSimple(arch, Inst::kIdPextrw, InstOptions::kNone, ptr(rax), xmm1, imm(0));
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printInfoSimple(arch, Inst::kIdVpdpbusd, InstOptions::kNone, xmm0, xmm1, xmm2);
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printInfoSimple(arch, Inst::kIdVpdpbusd, InstOptions::kX86_Vex, xmm0, xmm1, xmm2);
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printInfoSimple(arch, Inst::kIdVaddpd, InstOptions::kNone, ymm0, ymm1, ymm2);
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printInfoSimple(arch, Inst::kIdVaddpd, InstOptions::kNone, ymm0, ymm30, ymm31);
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printInfoSimple(arch, Inst::kIdVaddpd, InstOptions::kNone, zmm0, zmm1, zmm2);
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printInfoSimple(arch, Inst::kIdVpternlogd, InstOptions::kNone, zmm0, zmm0, zmm0, imm(0xFF));
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printInfoSimple(arch, Inst::kIdVpternlogq, InstOptions::kNone, zmm0, zmm1, zmm2, imm(0x33));
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printInfoExtra(arch, Inst::kIdVaddpd, InstOptions::kNone, k1, zmm0, zmm1, zmm2);
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printInfoExtra(arch, Inst::kIdVaddpd, InstOptions::kX86_ZMask, k1, zmm0, zmm1, zmm2);
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printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, xmm0, xmm1);
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printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, ymm0, xmm1);
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printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, zmm0, ymm1);
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printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, xmm0, ptr(rsi));
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printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, ymm0, ptr(rsi));
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printInfoSimple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, zmm0, ptr(rsi));
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#endif // !ASMJIT_NO_X86
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}
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} // {anonymous}
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int main() {
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printf("AsmJit Instruction Info Test-Suite v%u.%u.%u\n",
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unsigned((ASMJIT_LIBRARY_VERSION >> 16) ),
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unsigned((ASMJIT_LIBRARY_VERSION >> 8) & 0xFF),
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unsigned((ASMJIT_LIBRARY_VERSION ) & 0xFF));
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printf("\n");
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testX86Arch();
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return 0;
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}
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