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* Refactored the whole codebase to use snake_case convention to
name functions and variables, including member variables.
Class naming is unchanged and each starts with upper-case
character. The intention of this change is to make the source
code more readable and consistent across multiple projects
where AsmJit is currently used.
* Refactored support.h to make it more shareable across projects.
* x86::Vec now inherits from UniVec
* minor changes in JitAllocator and WriteScope in order to make
the size of WriteScope smaller
* added ZoneStatistics and Zone::statistics() getter
* improved x86::EmitHelper to use tables instead of choose() and
other mechanisms to pick between SSE and AVX instructions
* Refactored the whole codebase to use snake_case convention for
for functions names, function parameter names, struct members,
and variables
* Added a non-owning asmjit::Span<T> type and use into public API
to hide the usage of ZoneVector in CodeHolder, Builder, and
Compiler. Users now only get Span (with data and size), which
doesn't require users to know about ZoneVector
* Removed RAWorkId from RATiedReg in favor of RAWorkReg*
* Removed GEN from LiveInfo as it's not needed by CFG construction
to save memory (GEN was merged with LIVE-IN bits). The remaining
LIVE-IN, LIVE-OUT, and KILL bits are enough, however KILL bits may
be removed in the future as KILL bits are not needed after LIVE-IN
and LIVE-OUT converged
* Optimized the representation of LIVE-IN, LIVE-OUT, and KILL bits
per block. Now only registers that live across multiple basic
blocks are included here, which means that virtual registers that
only live in a single block are not included and won't be overhead
during liveness analysis. This optimization alone can make liveness
analysis 90% faster depending on the code generated (more virtual
registers that only live in a single basic block -> more gains)
* Optimized building liveness information bits per block. The new
code uses an optimized algorithm to prevent too many traversals
and uses a more optimized code for a case in which not too many
registers are used (it avoids array operations if the number of
all virtual registers within the function fits a single BitWord)
* Optimized code that computes which virtual register is only used
in a single basic block - this aims to optimize register allocator
in the future by using a designed code path for allocating regs
only used in a single basic block
* Reduced the information required for each live-span, which is used
by bin-packing. Now the struct is 8 bytes, which is good for a lot
of optimizations C++ compiler can do
* Added UniCompiler (ujit) which can be used to share code paths
between X86, X86_64, and AArch64 code generation (experimental).
206 lines
6.6 KiB
C++
206 lines
6.6 KiB
C++
// This file is part of AsmJit project <https://asmjit.com>
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//
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// See <asmjit/core.h> or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#include <asmjit/core.h>
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#if !defined(ASMJIT_NO_X86)
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#include <asmjit/x86.h>
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#endif
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#include <stdio.h>
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#include "asmjitutils.h"
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using namespace asmjit;
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static void print_app_info() noexcept {
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printf("AsmJit Instruction Info Test Suite v%u.%u.%u [Arch=%s] [Mode=%s]\n\n",
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unsigned((ASMJIT_LIBRARY_VERSION >> 16) ),
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unsigned((ASMJIT_LIBRARY_VERSION >> 8) & 0xFF),
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unsigned((ASMJIT_LIBRARY_VERSION ) & 0xFF),
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asmjit_arch_as_string(Arch::kHost),
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asmjit_build_type()
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);
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}
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namespace {
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#if !defined(ASMJIT_NO_X86)
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static char access_letter(bool r, bool w) noexcept {
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return r && w ? 'X' : r ? 'R' : w ? 'W' : '_';
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}
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static void print_info(Arch arch, const BaseInst& inst, const Operand_* operands, size_t op_count) {
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StringTmp<512> sb;
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// Read & Write Information
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// ------------------------
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InstRWInfo rw;
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InstAPI::query_rw_info(arch, inst, operands, op_count, &rw);
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#ifndef ASMJIT_NO_LOGGING
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Formatter::format_instruction(sb, FormatFlags::kNone, nullptr, arch, inst, Span(operands, op_count));
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#else
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sb.append("<Logging-Not-Available>");
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#endif
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sb.append("\n");
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sb.append(" Operands:\n");
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for (uint32_t i = 0; i < rw.op_count(); i++) {
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const OpRWInfo& op = rw.operand(i);
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sb.append_format(" [%u] Op=%c Read=%016llX Write=%016llX Extend=%016llX",
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i,
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access_letter(op.is_read(), op.is_write()),
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op.read_byte_mask(),
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op.write_byte_mask(),
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op.extend_byte_mask());
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if (op.is_mem_base_used()) {
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sb.append_format(" Base=%c", access_letter(op.is_mem_base_read(), op.is_mem_base_write()));
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if (op.is_mem_base_pre_modify())
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sb.append_format(" <PRE>");
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if (op.is_mem_base_post_modify())
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sb.append_format(" <POST>");
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}
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if (op.is_mem_index_used()) {
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sb.append_format(" Index=%c", access_letter(op.is_mem_index_read(), op.is_mem_index_write()));
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}
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sb.append("\n");
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}
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// CPU Flags (Read/Write)
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// ----------------------
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if ((rw.read_flags() | rw.write_flags()) != CpuRWFlags::kNone) {
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sb.append(" Flags: \n");
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struct FlagMap {
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CpuRWFlags flag;
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char name[4];
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};
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static const FlagMap flag_map_table[] = {
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{ CpuRWFlags::kX86_CF, "CF" },
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{ CpuRWFlags::kX86_OF, "OF" },
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{ CpuRWFlags::kX86_SF, "SF" },
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{ CpuRWFlags::kX86_ZF, "ZF" },
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{ CpuRWFlags::kX86_AF, "AF" },
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{ CpuRWFlags::kX86_PF, "PF" },
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{ CpuRWFlags::kX86_DF, "DF" },
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{ CpuRWFlags::kX86_IF, "IF" },
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{ CpuRWFlags::kX86_AC, "AC" },
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{ CpuRWFlags::kX86_C0, "C0" },
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{ CpuRWFlags::kX86_C1, "C1" },
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{ CpuRWFlags::kX86_C2, "C2" },
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{ CpuRWFlags::kX86_C3, "C3" }
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};
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sb.append(" ");
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for (uint32_t f = 0; f < 13; f++) {
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char c = access_letter((rw.read_flags() & flag_map_table[f].flag) != CpuRWFlags::kNone,
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(rw.write_flags() & flag_map_table[f].flag) != CpuRWFlags::kNone);
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if (c != '_')
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sb.append_format("%s=%c ", flag_map_table[f].name, c);
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}
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sb.append("\n");
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}
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// CPU Features
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// ------------
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CpuFeatures features;
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InstAPI::query_features(arch, inst, operands, op_count, &features);
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#ifndef ASMJIT_NO_LOGGING
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if (!features.is_empty()) {
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sb.append(" Features:\n");
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sb.append(" ");
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bool first = true;
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CpuFeatures::Iterator it(features.iterator());
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while (it.has_next()) {
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uint32_t feature_id = uint32_t(it.next());
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if (!first)
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sb.append(" & ");
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Formatter::format_feature(sb, arch, feature_id);
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first = false;
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}
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sb.append("\n");
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}
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#endif
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printf("%s\n", sb.data());
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}
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template<typename... Args>
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static void print_info_simple(Arch arch,InstId inst_id, InstOptions options, Args&&... args) {
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BaseInst inst(inst_id);
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inst.add_options(options);
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Operand_ op_array[] = { std::forward<Args>(args)... };
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print_info(arch, inst, op_array, sizeof...(args));
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}
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template<typename... Args>
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static void print_info_extra(Arch arch, InstId inst_id, InstOptions options, const Reg& extra_reg, Args&&... args) {
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BaseInst inst(inst_id);
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inst.add_options(options);
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inst.set_extra_reg(extra_reg);
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Operand_ op_array[] = { std::forward<Args>(args)... };
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print_info(arch, inst, op_array, sizeof...(args));
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}
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#endif // !ASMJIT_NO_X86
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static void test_x86_arch() {
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#if !defined(ASMJIT_NO_X86)
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using namespace x86;
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Arch arch = Arch::kX64;
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print_info_simple(arch, Inst::kIdAdd, InstOptions::kNone, eax, ebx);
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print_info_simple(arch, Inst::kIdXor, InstOptions::kNone, eax, eax);
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print_info_simple(arch, Inst::kIdLods, InstOptions::kNone, eax, dword_ptr(rsi));
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print_info_simple(arch, Inst::kIdPshufd, InstOptions::kNone, xmm0, xmm1, imm(0));
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print_info_simple(arch, Inst::kIdPabsb, InstOptions::kNone, mm1, mm2);
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print_info_simple(arch, Inst::kIdPabsb, InstOptions::kNone, xmm1, xmm2);
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print_info_simple(arch, Inst::kIdPextrw, InstOptions::kNone, eax, mm1, imm(0));
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print_info_simple(arch, Inst::kIdPextrw, InstOptions::kNone, eax, xmm1, imm(0));
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print_info_simple(arch, Inst::kIdPextrw, InstOptions::kNone, ptr(rax), xmm1, imm(0));
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print_info_simple(arch, Inst::kIdVpdpbusd, InstOptions::kNone, xmm0, xmm1, xmm2);
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print_info_simple(arch, Inst::kIdVpdpbusd, InstOptions::kX86_Vex, xmm0, xmm1, xmm2);
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print_info_simple(arch, Inst::kIdVaddpd, InstOptions::kNone, ymm0, ymm1, ymm2);
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print_info_simple(arch, Inst::kIdVaddpd, InstOptions::kNone, ymm0, ymm30, ymm31);
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print_info_simple(arch, Inst::kIdVaddpd, InstOptions::kNone, zmm0, zmm1, zmm2);
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print_info_simple(arch, Inst::kIdVpternlogd, InstOptions::kNone, zmm0, zmm0, zmm0, imm(0xFF));
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print_info_simple(arch, Inst::kIdVpternlogq, InstOptions::kNone, zmm0, zmm1, zmm2, imm(0x33));
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print_info_extra(arch, Inst::kIdVaddpd, InstOptions::kNone, k1, zmm0, zmm1, zmm2);
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print_info_extra(arch, Inst::kIdVaddpd, InstOptions::kX86_ZMask, k1, zmm0, zmm1, zmm2);
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print_info_simple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, xmm0, xmm1);
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print_info_simple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, ymm0, xmm1);
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print_info_simple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, zmm0, ymm1);
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print_info_simple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, xmm0, ptr(rsi));
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print_info_simple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, ymm0, ptr(rsi));
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print_info_simple(arch, Inst::kIdVcvtdq2pd, InstOptions::kNone, zmm0, ptr(rsi));
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#endif // !ASMJIT_NO_X86
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}
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} // {anonymous}
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int main() {
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print_app_info();
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test_x86_arch();
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return 0;
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}
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