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2ff454d415
* Reworked register operands - all vector registers are now
platform::Vec deriving from UniVec (universal vector operand),
additionally, there is no platform::Reg, instead asmjit::Reg
provides all necessary features to make it a base register for
each target architecture
* Reworked casting between registers - now architecture agnostic
names are preferred - use Gp32 instead of Gpd or GpW, Gp64
instead of Gpq and GpX, etc...
* Reworked vector registers and their names - architecture
agnostic naming is now preferred Vec32, Vec64, Vec128, etc...
* Reworked naming conventions used across AsmJit - for clarity
Identifiers are now prefixed with the type, like sectionId(),
labelId(), etc...
* Reworked how Zone and ZoneAllocator are used across AsmJit,
prefering Zone in most cases and ZoneAllocator only for
containers - this change alone achieves around 5% better
performance of Builder and Compiler
* Reworked LabelEntry - decreased the size of the base entry
to 16 bytes for anonymous and unnamed labels. Avoided an
indirection when using labelEntries() - LabelEntry is now
a value and not a pointer
* Renamed LabelLink to Fixup
* Added a new header <asmjit/host.h> which would include
<asmjit/core.h> + target tools for the host architecture,
if enabled and supported
* Added new AArch64 instructions (BTI, CSSC, CHKFEAT)
* Added a mvn_ alternative of mvn instruction (fix for Windows
ARM64 SDK)
* Added more AArch64 CPU features to CpuInfo
* Added better support for Apple CPU detection (Apple M3, M4)
* Added a new benchmarking tool asmjit_bench_overhead, which
benchmarks the overhead of CodeHolder::init()/reset() and
creating/attaching emitters to it. Thanks to the benchmark the
most common code-paths were optimized
* Added a new benchmarking tool asmjit_bench_regalloc, which
aims to benchmark the cost and complexity of register allocation.
* Renamed asmjit_test_perf to asmjit_bench_codegen to make it
clear what is a test and what is a benchmark
78 lines
2.0 KiB
C++
78 lines
2.0 KiB
C++
// This file is part of AsmJit project <https://asmjit.com>
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//
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// See <asmjit/core.h> or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#ifndef ASMJIT_TEST_RANDOM_H_INCLUDED
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#define ASMJIT_TEST_RANDOM_H_INCLUDED
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#include <stdint.h>
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#include <string.h>
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namespace TestUtils {
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namespace {
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// A pseudo random number generator based on a paper by Sebastiano Vigna:
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// http://vigna.di.unimi.it/ftp/papers/xorshiftplus.pdf
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class Random {
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public:
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// Constants suggested as `23/18/5`.
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static inline constexpr uint32_t kStep1_SHL = 23;
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static inline constexpr uint32_t kStep2_SHR = 18;
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static inline constexpr uint32_t kStep3_SHR = 5;
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uint64_t _state[2];
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inline explicit Random(uint64_t seed = 0) noexcept { reset(seed); }
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inline Random(const Random& other) noexcept = default;
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inline void reset(uint64_t seed = 0) noexcept {
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// The number is arbitrary, it means nothing.
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constexpr uint64_t kZeroSeed = 0x1F0A2BE71D163FA0u;
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// Generate the state data by using splitmix64.
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for (uint32_t i = 0; i < 2; i++) {
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seed += 0x9E3779B97F4A7C15u;
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uint64_t x = seed;
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x = (x ^ (x >> 30)) * 0xBF58476D1CE4E5B9u;
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x = (x ^ (x >> 27)) * 0x94D049BB133111EBu;
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x = (x ^ (x >> 31));
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_state[i] = x != 0 ? x : kZeroSeed;
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}
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}
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inline uint32_t nextUInt32() noexcept {
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return uint32_t(nextUInt64() >> 32);
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}
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inline uint64_t nextUInt64() noexcept {
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uint64_t x = _state[0];
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uint64_t y = _state[1];
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x ^= x << kStep1_SHL;
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y ^= y >> kStep3_SHR;
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x ^= x >> kStep2_SHR;
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x ^= y;
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_state[0] = y;
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_state[1] = x;
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return x + y;
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}
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inline double nextDouble() noexcept {
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constexpr uint32_t kMantissaShift = 64 - 52;
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constexpr uint64_t kExpMsk = 0x3FF0000000000000u;
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uint64_t u = (nextUInt64() >> kMantissaShift) | kExpMsk;
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double d = 0.0;
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memcpy(&d, &u, 8);
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return d - 1.0;
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}
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};
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} // {anonymous}
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} // {TestUtils}
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#endif // ASMJIT_TEST_RANDOM_H_INCLUDED
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