mirror of
https://github.com/asmjit/asmjit.git
synced 2025-12-17 20:44:37 +03:00
6c9a6b2454
* Removed AVX512_ER, AVX512_PF, AVX512_4FMAPS, and AVX512_4VNNIW
extensions and corresponding instructions (these were never
advertised by any x86 CPU and were only used by Xeon Phi acc.,
which AsmJit never supported)
* Removed CPU extensions HLE, MPX, and TSX
* Kept extension RTM, which is only for backward compatibility to
recognize instructions, but it's no longer checked by CpuInfo as
it's been deprecated together with HLE and MPX
* The xtest instruction now reports it requires RTM
* Reorganized x86 extensions a bit - they are now reordered to group
them by category, preparing for the future where extension IDs will
be always added after existing records for ABI compatibility
* Instruction vcvtneps2bf16 no longer accepts form without an explicit
memory operand size
* Removed aliased instructions in CMOVcc, Jcc, And SETcc categories,
now there is only a single instruction id for all aliased instructions.
* Added a new feature to always show instruction aliases in Logger, which
includes formatting instructio nodes (Builder, Compiler)
Instruction DB-only updates (not applied to C++ yet):
* AsmJit DB from now uses the same license as AsmJit (Zlib) and
no longer applies dual licensing (Zlib and Public Domain)
* Added support for aggregated instruction definitions in
x86 instruction database, which should simplify the maintenance
and reduce bugs (also the syntax is comparable to descriptions
used by Intel APX instruction manuals)
* Added support for APX instructions and new features
* Added support for AVX10.1 and AVX10.2 instructions (both new
instructions and new encodings of existing instructions)
* Added support for MOVRS instructions
* Added support for KL instructions (loadiwkey)
* Added support for AESKLE instructions
* Added support for AESKLEWIDE_KL instructions
* Added support for AMX_[AVX512|MOVRS|FP8|TF32|TRANSPOSE]
* NOTE: None of the instruction additions is currently used by
Asmjit, it's a pure database update that needs more work to
make all the instructions available in future AsmJit
922 lines
27 KiB
JavaScript
922 lines
27 KiB
JavaScript
// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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(function($scope, $as) {
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"use strict";
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function FAIL(msg) { throw new Error("[AArch64] " + msg); }
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// Import
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// ======
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const base = $scope.base ? $scope.base : require("./base.js");
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const exp = $scope.exp ? $scope.exp : require("./exp.js")
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const hasOwn = Object.prototype.hasOwnProperty;
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const dict = base.dict;
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const NONE = base.NONE;
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const Parsing = base.Parsing;
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const MapUtils = base.MapUtils;
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// Export
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// ======
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const arm = $scope[$as] = dict();
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// Database
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// ========
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arm.dbName = "isa_aarch64.json";
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// asmdb.aarch64.Utils
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// ===================
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// Can be used to assign the number of bits each part of the opcode occupies.
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// NOTE: THUMB instructions that use halfword must always specify the width
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// of all registers as many instructions accept only LO (r0..r7) registers.
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const FieldInfo = {
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"P" : { "bits": 1 },
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"U" : { "bits": 1 },
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"W" : { "bits": 1 },
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"S" : { "bits": 1 },
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"R" : { "bits": 1 },
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"H" : { "bits": 1 },
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"F" : { "bits": 1 },
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"post" : { "bits": 1 },
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"!post" : { "bits": 1 },
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"op" : { "bits": 1 }, // TODO: This should be fixed.
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"s" : { "bits": 1 },
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"sz" : { "bits": 2 },
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"msz" : { "bits": 2 },
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"sop" : { "bits": 2 },
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"cond" : { "bits": 4 },
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"nzcv" : { "bits": 4 },
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"cmode" : { "bits": 4 },
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"CRn" : { "bits": 4 },
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"CRm" : { "bits": 4 },
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"Rx" : { "bits": 5, "read": true , "write": true },
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"Rx2" : { "bits": 5, "read": true , "write": true },
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"Rdn" : { "bits": 5, "read": true , "write": true },
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"Rd" : { "bits": 5, "read": false, "write": true },
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"Rd2" : { "bits": 5, "read": false, "write": true },
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"Rs" : { "bits": 5, "read": true , "write": false },
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"Rs2" : { "bits": 5, "read": true , "write": false },
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"Rn" : { "bits": 5, "read": true , "write": false },
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"Rm" : { "bits": 5, "read": true , "write": false },
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"Ra" : { "bits": 5, "read": true , "write": false },
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"Rt" : { "bits": 5, "read": true , "write": false },
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"Rt2" : { "bits": 5, "read": true , "write": false },
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"Wx" : { "bits": 5, "read": true , "write": true },
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"Wx2" : { "bits": 5, "read": true , "write": true },
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"Wdn" : { "bits": 5, "read": true , "write": true },
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"Wd" : { "bits": 5, "read": false, "write": true },
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"Wd2" : { "bits": 5, "read": false, "write": true },
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"Ws" : { "bits": 5, "read": true , "write": false },
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"Ws2" : { "bits": 5, "read": true , "write": false },
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"Wn" : { "bits": 5, "read": true , "write": false },
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"Wm" : { "bits": 5, "read": true , "write": false },
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"Wa" : { "bits": 5, "read": true , "write": false },
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"Wt" : { "bits": 5, "read": true , "write": false },
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"Wt2" : { "bits": 5, "read": true , "write": false },
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"Xx" : { "bits": 5, "read": true , "write": true },
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"Xx2" : { "bits": 5, "read": true , "write": true },
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"Xdn" : { "bits": 5, "read": true , "write": true },
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"Xd" : { "bits": 5, "read": false, "write": true },
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"Xd2" : { "bits": 5, "read": false, "write": true },
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"Xs" : { "bits": 5, "read": true , "write": false },
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"Xs2" : { "bits": 5, "read": true , "write": false },
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"Xn" : { "bits": 5, "read": true , "write": false },
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"Xm" : { "bits": 5, "read": true , "write": false },
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"Xa" : { "bits": 5, "read": true , "write": false },
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"Xt" : { "bits": 5, "read": true , "write": false },
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"Xt2" : { "bits": 5, "read": true , "write": false },
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"Bx" : { "bits": 5, "read": true , "write": true },
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"Bx2" : { "bits": 5, "read": true , "write": true },
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"Bdn" : { "bits": 5, "read": true , "write": true },
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"Bd" : { "bits": 5, "read": false, "write": true },
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"Bd2" : { "bits": 5, "read": false, "write": true },
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"Bs" : { "bits": 5, "read": true , "write": false },
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"Bs2" : { "bits": 5, "read": true , "write": false },
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"Bn" : { "bits": 5, "read": true , "write": false },
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"Bm" : { "bits": 5, "read": true , "write": false },
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"Ba" : { "bits": 5, "read": true , "write": false },
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"Hx" : { "bits": 5, "read": true , "write": true },
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"Hx2" : { "bits": 5, "read": true , "write": true },
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"Hdn" : { "bits": 5, "read": true , "write": true },
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"Hd" : { "bits": 5, "read": false, "write": true },
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"Hd2" : { "bits": 5, "read": false, "write": true },
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"Hs" : { "bits": 5, "read": true , "write": false },
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"Hs2" : { "bits": 5, "read": true , "write": false },
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"Hn" : { "bits": 5, "read": true , "write": false },
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"Hm" : { "bits": 5, "read": true , "write": false },
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"Ha" : { "bits": 5, "read": true , "write": false },
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"Sx" : { "bits": 5, "read": true , "write": true },
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"Sx2" : { "bits": 5, "read": true , "write": true },
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"Sdn" : { "bits": 5, "read": true , "write": true },
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"Sd" : { "bits": 5, "read": false, "write": true },
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"Sd2" : { "bits": 5, "read": false, "write": true },
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"Ss" : { "bits": 5, "read": true , "write": false },
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"Ss2" : { "bits": 5, "read": true , "write": false },
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"Sn" : { "bits": 5, "read": true , "write": false },
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"Sm" : { "bits": 5, "read": true , "write": false },
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"Sa" : { "bits": 5, "read": true , "write": false },
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"Dx" : { "bits": 5, "read": true , "write": true },
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"Dx2" : { "bits": 5, "read": true , "write": true },
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"Ddn" : { "bits": 5, "read": true , "write": true },
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"Dd" : { "bits": 5, "read": false, "write": true },
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"Dd2" : { "bits": 5, "read": false, "write": true },
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"Ds" : { "bits": 5, "read": true , "write": false },
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"Ds2" : { "bits": 5, "read": true , "write": false },
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"Dn" : { "bits": 5, "read": true , "write": false },
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"Dn2" : { "bits": 5, "read": true , "write": false },
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"Dm" : { "bits": 5, "read": true , "write": false },
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"Da" : { "bits": 5, "read": true , "write": false },
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"Qx" : { "bits": 5, "read": true , "write": true },
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"Qx2" : { "bits": 5, "read": true , "write": true },
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"Qdn" : { "bits": 5, "read": true , "write": true },
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"Qd" : { "bits": 5, "read": false, "write": true },
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"Qd2" : { "bits": 5, "read": false, "write": true },
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"Qs" : { "bits": 5, "read": true , "write": false },
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"Qs2" : { "bits": 5, "read": true , "write": false },
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"Qn" : { "bits": 5, "read": true , "write": false },
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"Qn2" : { "bits": 5, "read": true , "write": false },
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"Qm" : { "bits": 5, "read": true , "write": false },
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"Qa" : { "bits": 5, "read": true , "write": false },
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"Vx" : { "bits": 5, "read": true , "write": true },
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"Vx2" : { "bits": 5, "read": true , "write": true },
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"Vdn" : { "bits": 5, "read": true , "write": true },
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"Vd" : { "bits": 5, "read": false, "write": true },
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"Vd2" : { "bits": 5, "read": false, "write": true },
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"Vs" : { "bits": 5, "read": true , "write": false },
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"Vs2" : { "bits": 5, "read": true , "write": false },
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"Vn" : { "bits": 5, "read": true , "write": false },
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"Vm" : { "bits": 5, "read": true , "write": false },
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"Va" : { "bits": 5, "read": true , "write": false },
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"Zx" : { "bits": 5, "read": true , "write": true },
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"Zx2" : { "bits": 5, "read": true , "write": true },
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"Zda" : { "bits": 5, "read": true , "write": true },
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"Zdn" : { "bits": 5, "read": true , "write": true },
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"Zdn2" : { "bits": 5, "read": true , "write": true },
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"Zd" : { "bits": 5, "read": false, "write": true },
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"Zd2" : { "bits": 5, "read": false, "write": true },
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"Zs" : { "bits": 5, "read": true , "write": false },
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"Zs2" : { "bits": 5, "read": true , "write": false },
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"Zn" : { "bits": 5, "read": true , "write": false },
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"Zm" : { "bits": 5, "read": true , "write": false },
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"Zk" : { "bits": 5, "read": true , "write": false },
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"Za" : { "bits": 5, "read": true , "write": false },
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"Pdn" : { "bits": 4, "read": true , "write": true },
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"Pdm" : { "bits": 4, "read": true , "write": true },
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"Pd" : { "bits": 4, "read": false, "write": true },
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"Ps" : { "bits": 4, "read": true , "write": false },
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"Pn" : { "bits": 4, "read": true , "write": false },
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"Pm" : { "bits": 4, "read": true , "write": false },
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"Pg" : { "bits": 4, "read": true , "write": false }
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};
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arm.FieldInfo = FieldInfo;
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// AArch64 utilities.
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class Utils {
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static splitInstructionSignature(s) {
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const names = s.match(/^[\w\|]+/)[0];
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s = s.substring(names.length);
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const opOffset = s.indexOf(" ")
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const suffix = s.substring(0, opOffset).trim();
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const operands = opOffset === -1 ? "" : s.substring(opOffset + 1).trim();
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return {
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names: names.split("|").map((base)=>{ return base + suffix}),
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operands: operands
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}
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}
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static parseShiftOrExtendOp(s) {
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const space = s.indexOf(" ");
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if (space === -1)
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return "";
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const ops = s.substring(0, space).trim();
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for (let op of ops.split("|"))
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if (!/^(sop|extend|lsl|lsr|asr|uxtw|sxtw|sxtx|mul)$/.test(op))
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return "";
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return ops;
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}
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}
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arm.Utils = Utils;
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function normalizeNumber(n) {
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return n < 0 ? 0x100000000 + n : n;
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}
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function decomposeOperand(s) {
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let type = null;
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let element = null;
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let consecutive = 0;
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let maskType = "";
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const elementM = s.match(/\[#(\w+)\]$/);
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if (elementM) {
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element = elementM[1];
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s = s.substring(0, s.length - elementM[0].length);
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}
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const typeM = s.match(/\.(\w+)$/);
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if (typeM) {
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type = typeM[1];
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s = s.substring(0, s.length - typeM[0].length);
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}
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const maskM = s.match(/\/(M|Z|MZ)$/);
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if (maskM) {
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maskType = maskM[1];
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s = s.substring(0, s.length - maskM[0].length);
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}
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if (s.endsWith("++")) {
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consecutive = 2;
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s = s.substring(0, s.length - 2);
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}
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else if (s.endsWith("+")) {
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consecutive = 1;
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s = s.substring(0, s.length - 1);
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}
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let m = s.match(/==|\!=|>=|<=|\*/);
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let restrict = false;
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if (m) {
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restrict = s.substring(m.index);
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s = s.substring(0, m.index);
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}
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return {
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data : s,
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maskType : maskType,
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type : type,
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element : element,
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restrict : restrict,
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consecutive: consecutive
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};
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}
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function splitOpcodeFields(s) {
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const arr = s.split("|");
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const out = [];
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for (let i = 0; i < arr.length; i++) {
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const val = arr[i];
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if (/^[0-1A-Z]{2,}$/.test(val))
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out.push.apply(out, val.match(/([0-1]+)|[A-Z]/g));
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else
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out.push(val);
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}
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return out.map((field)=>{return field.trim(); });
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}
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// asmdb.aarch64.Operand
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// =====================
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// ARM operand.
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class Operand extends base.Operand {
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constructor(def) {
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super();
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this.data = def;
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// Register.
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this.sp = ""; // GP register stack access: ["", "WSP" or "SP"].
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this.mask = ""; // Masking specifier.
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}
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hasMemModes() {
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return Object.keys(this.memModes).length !== 0;
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}
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get name() {
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switch (this.type) {
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case "reg": return this.reg;
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case "mem": return this.mem;
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case "imm": return this.imm;
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case "rel": return this.rel;
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default : return "";
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}
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}
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get scale() {
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if (this.restrict && this.restrict.startsWith("*"))
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return parseInt(this.restrict.substring(1), 10);
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else
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return 0;
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}
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}
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arm.Operand = Operand;
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// asmdb.aarch64.Instruction
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// =========================
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function patternFromOperand(key) { return key; }
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// ARM instruction.
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class Instruction extends base.Instruction {
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constructor(db, data) {
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super(db, data);
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this.name = data.name;
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this.it = dict(); // THUMB's 'it' flags.
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this.apsr = dict();
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this.fpcsr = dict();
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this.calc = dict(); // Calculations required to generate opcode.
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this.immCond = []; // Immediate value conditions (array of conditions).
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this._assignOperands(data.operands);
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this._assignOpcode(data.op);
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for (let k in data) {
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if (k === "name" || k == "op" || k === "operands")
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continue;
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this._assignAttribute(k, data[k]);
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}
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this._updateOperandsInfo();
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this._postProcess();
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}
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_assignAttribute(key, value) {
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switch (key) {
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case "it":
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for (let it of value.split(" "))
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this.it[it.trim()] = true;
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break;
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case "apsr":
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case "fpcsr":
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this._assignAttributeKeyValue(key, value);
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break;
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case "imm":
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this.imm = exp.parse(value);
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break;
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case "calc":
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for (let calcKey in value)
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this.calc[calcKey] = exp.parse(value[calcKey]);
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break;
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default:
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super._assignAttribute(key, value);
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}
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}
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_assignAttributeKeyValue(name, content) {
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const attributes = content.trim().split(/[ ]+/);
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for (let i = 0; i < attributes.length; i++) {
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const attr = attributes[i].trim();
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if (!attr)
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continue;
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const eq = attr.indexOf("=");
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let key = eq === -1 ? attr : attr.substring(0, eq);
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let val = eq === -1 ? true : attr.substring(eq + 1);
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// If the key contains "|" it's a definition of multiple attributes.
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if (key.indexOf("|") !== -1) {
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const dot = key.indexOf(".");
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const base = dot === -1 ? "" : key.substring(0, dot + 1);
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const keys = (dot === -1 ? key : key.substring(dot + 1)).split("|");
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for (let j = 0; j < keys.length; j++)
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this[name][base + keys[j]] = val;
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}
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else {
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this[name][key] = val;
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}
|
|
}
|
|
}
|
|
|
|
_assignOperands(s) {
|
|
if (!s) return;
|
|
|
|
// Split into individual operands and push them to `operands`.
|
|
const arr = base.Parsing.splitOperands(s);
|
|
for (let i = 0; i < arr.length; i++) {
|
|
let def = arr[i].trim();
|
|
const op = new Operand(def);
|
|
|
|
const sp = def.match(/^(\w+)\|(SP|WSP)$/);
|
|
if (sp) {
|
|
def = sp[1];
|
|
op.sp = sp[2];
|
|
}
|
|
|
|
const consecutive = def.match(/(\d+)x\{(.*)\}([+]?[+]?)/);
|
|
if (consecutive)
|
|
def = consecutive[2];
|
|
|
|
op.sign = false;
|
|
op.element = null;
|
|
op.shiftOp = "";
|
|
op.shiftImm = null;
|
|
op.shiftCond = "";
|
|
|
|
// Handle {optional} attribute.
|
|
if (Parsing.isOptional(def)) {
|
|
op.optional = true;
|
|
def = Parsing.clearOptional(def);
|
|
}
|
|
|
|
// Handle commutativity <-> symbol.
|
|
if (Parsing.isCommutative(def)) {
|
|
op.commutative = true;
|
|
def = Parsing.clearCommutative(def);
|
|
}
|
|
|
|
// Handle shift operation.
|
|
let shiftOp = Utils.parseShiftOrExtendOp(def);
|
|
if (shiftOp) {
|
|
op.shiftOp = shiftOp;
|
|
def = def.substring(shiftOp.length + 1);
|
|
}
|
|
|
|
if (def.startsWith("[")) {
|
|
op.type = "mem";
|
|
op.memModes = dict();
|
|
|
|
op.base = null;
|
|
op.index = null;
|
|
op.offset = null;
|
|
|
|
let mem = def;
|
|
let didHaveMemMode = false;
|
|
|
|
for (;;) {
|
|
if (mem.endsWith("!")) {
|
|
op.memModes.preIndex = true;
|
|
mem = mem.substring(0, mem.length - 1);
|
|
|
|
didHaveMemMode = true;
|
|
break;
|
|
}
|
|
|
|
if (mem.endsWith("@")) {
|
|
op.memModes.postIndex = true;
|
|
mem = mem.substring(0, mem.length - 1);
|
|
|
|
didHaveMemMode = true;
|
|
break;
|
|
}
|
|
|
|
if (mem.endsWith("{!}")) {
|
|
op.memModes.offset = true;
|
|
op.memModes.preIndex = true;
|
|
mem = mem.substring(0, mem.length - 3);
|
|
|
|
didHaveMemMode = true;
|
|
continue;
|
|
}
|
|
|
|
if (mem.endsWith("{@}")) {
|
|
op.memModes.offset = true;
|
|
op.memModes.postIndex = true;
|
|
mem = mem.substring(0, mem.length - 3);
|
|
|
|
didHaveMemMode = true;
|
|
continue;
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
if (!mem.endsWith("]"))
|
|
FAIL(`Unknown memory operand '${mem}' in '${def}'`);
|
|
|
|
let parts = mem.substring(1, mem.length - 1).split(",").map(function(s) { return s.trim() });
|
|
for (let i = 0; i < parts.length; i++) {
|
|
const part = parts[i];
|
|
|
|
const m = part.match(/^\{(([a-z]+)(\|[a-z]+)*)\s+#(\w+)\s*(\*\s*\d+\s*)?\}$/);
|
|
if (m) {
|
|
op.shiftOp = m[1];
|
|
op.shiftImm = m[2];
|
|
if (m[3])
|
|
op.shiftCond = m[3]
|
|
continue;
|
|
}
|
|
|
|
if (i === 0) {
|
|
op.base = dict();
|
|
op.base.field = part;
|
|
op.base.exp = null;
|
|
|
|
const m = part.match(/^([A-Za-z]\w*(?:\.\w+)?)/);
|
|
if (m && m[1].length < part.length) {
|
|
op.base.exp = exp.parse(part);
|
|
op.base.field = m[1];
|
|
}
|
|
}
|
|
else if (part.startsWith("#")) {
|
|
let p = part.substring(1);
|
|
let u = "1";
|
|
|
|
let offExp = null;
|
|
let offMul = 1;
|
|
|
|
if (p.startsWith("+/-")) {
|
|
u = "U";
|
|
p = p.substring(3);
|
|
}
|
|
|
|
const expMatch = p.match(/^([A-Za-z]\w*)==/);
|
|
if (expMatch) {
|
|
offExp = exp.parse(p);
|
|
p = p.substring(0, expMatch[1].length);
|
|
}
|
|
|
|
const mulMatch = p.match(/\s*\*\s*(\d+)$/);
|
|
if (mulMatch) {
|
|
offMul = parseInt(mulMatch[1]);
|
|
p = p.substring(0, mulMatch.index);
|
|
}
|
|
|
|
op.offset = dict();
|
|
op.offset.field = p;
|
|
op.offset.u = u;
|
|
op.offset.exp = offExp;
|
|
op.offset.mul = offMul;
|
|
}
|
|
else {
|
|
let p = part;
|
|
let u = "1";
|
|
|
|
if (p.startsWith("+/-")) {
|
|
u = "U";
|
|
p = p.substring(3);
|
|
}
|
|
|
|
op.index = dict();
|
|
op.index.field = p;
|
|
op.index.u = u;
|
|
|
|
const m = p.match(/^([A-Za-z\|]\w*(?:\.\w+)?)/);
|
|
if (m && m[1].length < p.length) {
|
|
op.index.exp = exp.parse(p);
|
|
op.index.field = m[1];
|
|
}
|
|
}
|
|
}
|
|
|
|
if (!op.hasMemModes() && (op.offset || op.index))
|
|
op.memModes.offset = true;
|
|
|
|
op.mem = mem;
|
|
}
|
|
else if (def.startsWith("#")) {
|
|
const obj = decomposeOperand(def);
|
|
const imm = obj.data;
|
|
|
|
op.type = "imm";
|
|
op.imm = imm.substring(1); // Immediate operand name.
|
|
op.immSize = 0; // Immediate size in bits.
|
|
op.restrict = obj.restrict; // Immediate condition.
|
|
}
|
|
else {
|
|
// Some instructions use Reg! to specify that the register increments.
|
|
if (def.endsWith("!")) {
|
|
def = def.substring(0, def.length - 1)
|
|
op.regInc = true
|
|
}
|
|
|
|
const obj = decomposeOperand(def);
|
|
const reg = obj.data;
|
|
|
|
const type = reg.substring(0, 1).toLowerCase();
|
|
const info = FieldInfo[reg];
|
|
|
|
if (!info)
|
|
FAIL(`Unknown register operand '${reg}' in '${def}'`);
|
|
|
|
op.type = info.list ? "reg-list" : "reg";
|
|
op.reg = reg; // Register name (as specified in manual).
|
|
op.regType = type; // Register type.
|
|
op.regList = !!info.list; // Register list.
|
|
op.maskType = obj.maskType; // Mask type.
|
|
op.elementType = obj.type // Element type or t, ta, tb.
|
|
op.read = info.read; // Register access (read).
|
|
op.write = info.write; // Register access (write).
|
|
op.element = obj.element; // Register element[] access.
|
|
op.restrict = obj.restrict; // Register condition.
|
|
op.consecutive = obj.consecutive;
|
|
}
|
|
|
|
this.operands.push(op);
|
|
|
|
if (consecutive) {
|
|
const count = parseInt(consecutive[1]);
|
|
for (let n = 2; n <= count; n++) {
|
|
const def = consecutive[3].replace(op.reg, op.reg + n);
|
|
const opN = new Operand(def);
|
|
opN.type = "reg";
|
|
opN.reg = op.reg + n;
|
|
opN.regType = op.regType;
|
|
opN.read = op.read;
|
|
opN.write = op.write;
|
|
opN.element = op.element;
|
|
opN.consecutive = consecutive[3].length;
|
|
opN.artificial = true;
|
|
this.operands.push(opN);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
_assignOpcode(s) {
|
|
this.opcodeString = s;
|
|
|
|
let opcodeIndex = 0;
|
|
let opcodeValue = 0;
|
|
|
|
let patternMap = {};
|
|
|
|
// Split opcode into its fields.
|
|
const arr = splitOpcodeFields(s);
|
|
const dup = dict();
|
|
|
|
const fields = this.fields;
|
|
const pattern = [];
|
|
|
|
const fieldMap = Object.create(null);
|
|
for (let field of arr) {
|
|
fieldMap[field] = true;
|
|
}
|
|
|
|
for (let i = arr.length - 1; i >= 0; i--) {
|
|
let key = arr[i].trim();
|
|
let m;
|
|
|
|
if (/^[0-1]+$/.test(key)) {
|
|
// This part of the opcode is RAW bits, they contribute to the `opcodeValue`.
|
|
opcodeValue |= parseInt(key, 2) << opcodeIndex;
|
|
opcodeIndex += key.length;
|
|
pattern.unshift("_".repeat(key.length));
|
|
}
|
|
else {
|
|
pattern.unshift(patternFromOperand(key));
|
|
patternMap[patternFromOperand(key)] = true;
|
|
|
|
let size = 0;
|
|
let mask = 0;
|
|
let bits = 0;
|
|
let from = -1;
|
|
|
|
let lbit = key.startsWith("'");
|
|
let hbit = key.endsWith("'");
|
|
|
|
if ((m = key.match(/\[\s*(\d+)\s*\:\s*(\d+)\s*\]$/))) {
|
|
const a = parseInt(m[1], 10);
|
|
const b = parseInt(m[2], 10);
|
|
if (a < b)
|
|
FAIL(`Invalid bit range '${key}' in opcode '${s}'`);
|
|
from = b;
|
|
size = a - b + 1;
|
|
mask = ((1 << size) - 1) << b;
|
|
key = key.substring(0, m.index).trim();
|
|
}
|
|
else if ((m = key.match(/\[\s*(\d+)\s*\]$/))) {
|
|
from = parseInt(m[1], 10);
|
|
size = 1;
|
|
mask = 1 << from;
|
|
key = key.substring(0, m.index).trim();
|
|
}
|
|
else if ((m = key.match(/\:\s*(\d+)$/))) {
|
|
size = parseInt(m[1], 10);
|
|
bits = size;
|
|
key = key.substring(0, m.index).trim();
|
|
}
|
|
else {
|
|
const key_ = key;
|
|
|
|
if (lbit || hbit) {
|
|
from = 0;
|
|
|
|
if (lbit && hbit)
|
|
FAIL(`Couldn't recognize the format of '${key}' in opcode '${s}'`);
|
|
|
|
if (lbit) {
|
|
key = key.substring(1);
|
|
}
|
|
|
|
if (hbit) {
|
|
key = key.substring(0, key.length - 1);
|
|
from = 4;
|
|
}
|
|
|
|
size = 1;
|
|
}
|
|
else if (FieldInfo[key]) {
|
|
// Sizes of some standard fields can be assigned automatically.
|
|
size = FieldInfo[key].bits;
|
|
bits = size;
|
|
|
|
if (fieldMap["'" + key])
|
|
from = 1;
|
|
}
|
|
else if (key.length === 1) {
|
|
// Sizes of one-letter fields (like 'U', 'F', etc...) is 1 if not specified.
|
|
size = 1;
|
|
bits = 1;
|
|
}
|
|
else {
|
|
FAIL(`Couldn't recognize the size of '${key}' in opcode '${s}'`);
|
|
}
|
|
|
|
if (dup[key_] === true) {
|
|
bits = 0;
|
|
lbit = 0;
|
|
hbit = 0;
|
|
}
|
|
else {
|
|
dup[key_] = true;
|
|
}
|
|
}
|
|
|
|
let field = fields[key];
|
|
if (!field) {
|
|
field = {
|
|
index: opcodeIndex,
|
|
values: [],
|
|
bits: 0,
|
|
mask: 0,
|
|
lbit: 0,
|
|
hbit: 0 // Only 1 if a single quote (') was used.
|
|
}
|
|
fields[key] = field;
|
|
}
|
|
|
|
if (from === -1)
|
|
from = field.bits;
|
|
|
|
field.mask |= mask;
|
|
field.bits += bits;
|
|
field.lbit += lbit;
|
|
field.hbit += hbit;
|
|
field.values.push({
|
|
index: opcodeIndex,
|
|
from: from,
|
|
size: size
|
|
});
|
|
|
|
opcodeIndex += size;
|
|
}
|
|
}
|
|
|
|
for (let i = 0; i < pattern.length; i++)
|
|
if (pattern[i] === 'U')
|
|
pattern[i] = "_";
|
|
|
|
// Normalize all fields.
|
|
for (let key in fields) {
|
|
const field = fields[key];
|
|
|
|
// There should be either number of bits or mask, there shouldn't be both.
|
|
if (!field.bits && !field.mask)
|
|
FAIL(`Part '${key}' of opcode '${s}' contains neither size nor mask`);
|
|
|
|
if (field.bits && field.mask)
|
|
FAIL(`Part '${key}' of opcode '${s}' contains both size and mask`);
|
|
|
|
if (field.bits)
|
|
field.mask = ((1 << field.bits) - 1);
|
|
else if (field.mask)
|
|
field.bits = 32 - Math.clz32(field.mask);
|
|
|
|
// Handle field that used single-quote.
|
|
if (field.lbit) {
|
|
field.mask = (field.mask << 1) | 0x1;
|
|
field.bits++;
|
|
}
|
|
|
|
if (field.hbit) {
|
|
field.mask |= 1 << field.bits;
|
|
field.bits++;
|
|
}
|
|
|
|
const op = this.operandByName(key);
|
|
if (op && op.isImm())
|
|
op.immSize = field.bits;
|
|
}
|
|
|
|
// Check if the opcode value has the correct number of bits.
|
|
if (opcodeIndex !== 32)
|
|
FAIL(`The number of bits '${opcodeIndex}' used by the opcode '${s}' doesn't match 32`);
|
|
this.opcodeValue = normalizeNumber(opcodeValue);
|
|
}
|
|
|
|
_assignSpecificAttribute(key, value) {
|
|
switch (key) {
|
|
case "it": {
|
|
const values = String(value).split("|");
|
|
for (let i = 0; i < values.length; i++) {
|
|
const value = values[i];
|
|
switch (value) {
|
|
case "in" : this.it.IN = true; break;
|
|
case "out" : this.it.OUT = true; break;
|
|
case "any" : this.it.IN = true;
|
|
this.it.OUT = true; break;
|
|
case "last": this.it.LAST = true; break;
|
|
case "def" : this.it.DEF = true; break;
|
|
default:
|
|
this.report(`${this.name}: Unhandled IT value '${value}'`);
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
_postProcess() {}
|
|
|
|
operandByName(name) {
|
|
const operands = this.operands;
|
|
for (let i = 0; i < operands.length; i++) {
|
|
const op = operands[i];
|
|
if (op.name === name)
|
|
return op;
|
|
}
|
|
return null;
|
|
}
|
|
}
|
|
arm.Instruction = Instruction;
|
|
|
|
// asmdb.aarch64.ISA
|
|
// =================
|
|
|
|
function mergeGroupData(data, group) {
|
|
for (let k in group) {
|
|
switch (k) {
|
|
case "group":
|
|
case "data":
|
|
break;
|
|
|
|
case "ext":
|
|
data[k] = (data[k] ? data[k] + " " : "") + group[k];
|
|
break;
|
|
|
|
default:
|
|
if (data[k] === undefined)
|
|
data[k] = group[k]
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
class ISA extends base.ISA {
|
|
constructor(data) {
|
|
super(data);
|
|
this.addData(data || NONE);
|
|
}
|
|
|
|
_addInstructions(groups) {
|
|
for (let group of groups) {
|
|
for (let instructions of group.data) {
|
|
const sgn = Utils.splitInstructionSignature(instructions.inst);
|
|
const data = MapUtils.cloneExcept(instructions, { "inst": true });
|
|
|
|
mergeGroupData(data, group)
|
|
|
|
for (let j = 0; j < sgn.names.length; j++) {
|
|
data.name = sgn.names[j];
|
|
data.operands = sgn.operands;
|
|
if (j > 0)
|
|
data.aliasOf = sgn.names[0];
|
|
this._addInstruction(new Instruction(this, data));
|
|
}
|
|
}
|
|
}
|
|
|
|
return this;
|
|
}
|
|
}
|
|
arm.ISA = ISA;
|
|
|
|
}).apply(this, typeof module === "object" && module && module.exports
|
|
? [module, "exports"] : [this.asmdb || (this.asmdb = {}), "aarch64"]);
|