Extend option in ADD, ADDS, SUB, SUBS, CMP, and CMN instructions
doesn't always use the same second register type. For example when
extending from a BYTE the second source register must be W and not
X.
This change makes sure that the assembler accepts the correct
combination and refuses the incorrect one.
IMPORTANT: Although this is not an ABI change, the new behavior
can break AArch64 code that used the incorrect signatures.
* Instruction database is now part of asmjit to keep it in sync
* X86/X64 ISA data has been reworked, now in a proper JSON format
* ARM32 ISA data has been added (currently only DB, support later)
* ARM64 ISA data has been added
* ARM features detection has been updated
