The problem was that the sign/zero extension was not working with
TypeIds, but it was working with register IDs, when emitted. Thus,
even when TypeId was uint8, for example, the register could be
uint32, so the final instruction emitted was 'movzx eax, eax', for
example, which was wrong.
* Renamed all eq() methods to equals() (consistency) (ABI)
* Reorganized some X86 instructions in X86 database
* Properly detect RISC-V CPU at compile time (Environment)
* Removed CallConvId::kNone in favor of defaulting to kCDecl (ABI)
* CallConvId::kHost is now alias to CallConvId::kCDecl (ABI)
* Added FloatABI to Environment to disginguish between softfloat
and hardfloat
* Added more AArch64 CPU features and their detection (ABI)
* Because of CallConvId changes it's now possible to run
compiler tests on 32-bit ARM (fixes a bug in test cases)
* Added QEMU to CI build matrix to test different architectures
* Refactored workflows to use a single workflow for both VM and non-VM builds
* Compiler tests are now able to test compilation of different architectures
[ABI] Added ABI version as an inline namespace, which forms asmjit::_abi_MAJOR_MINOR
[ABI] Added support for AVX512_FP16, 16-bit broadcast, and AVX512_FP16 tests
[ABI] Added initial support for consecutive registers into instruction database and register allocator
[ABI] Added a possibility to use temporary memory in CodeHolder's zone
[ABI] Compiler::setArg() is now deprecated, use FuncNode::setArg()
[Bug] Fixed correct RW information of instructions that only support implicit zeroing with {k}
[Bug] Fixed broadcast to be able to broadcast bcst16 operands
