3 Commits

Author	SHA1	Message	Date
kobalicek	7bed2b0e14	[bug] Fixed tablegen to properly add implicit zeroing flag ... It was ignoring the flag and as a result the instruction such as vpcmpeqd k1 {k2}, zmm1, zmm2 would have k1 set as Read/Write, which is incorrect.	2024-11-22 20:26:31 +01:00
kobalicek	9e39b1e814	Added basic abstractions to CondCode, Gp, and Vec ... * Each architecture now provides r32() and r64() functions for register casting * Each architecture now provides v128() function for register casting, returning just Vec to make writing cross platform code easier * Added some basic condition code abstractions so it can be used interchangeably across architectures * Added back unlicense to asmjit database (now it's dual licensed)	2024-02-10 16:43:40 +01:00
kobalicek	e4e61c4f15	[ABI] Completely reworked instruction DB and generators ... * Instruction database is now part of asmjit to keep it in sync * X86/X64 ISA data has been reworked, now in a proper JSON format * ARM32 ISA data has been added (currently only DB, support later) * ARM64 ISA data has been added * ARM features detection has been updated	2023-09-10 09:55:17 +02:00