* Refactored workflows to use a single workflow for both VM and non-VM builds
* Compiler tests are now able to test compilation of different architectures
In addition, always enable DualMapping when RWX pages are not
possible to allocate in JitAllocator, because otherwise the
allocator would not be able to allocate memory for JIT code
execution.
New CI runners to test FreeBSD, NetBSD, and OpenBSD are also
provided.
[ABI] Added ABI version as an inline namespace, which forms asmjit::_abi_MAJOR_MINOR
[ABI] Added support for AVX512_FP16, 16-bit broadcast, and AVX512_FP16 tests
[ABI] Added initial support for consecutive registers into instruction database and register allocator
[ABI] Added a possibility to use temporary memory in CodeHolder's zone
[ABI] Compiler::setArg() is now deprecated, use FuncNode::setArg()
[Bug] Fixed correct RW information of instructions that only support implicit zeroing with {k}
[Bug] Fixed broadcast to be able to broadcast bcst16 operands
Fixed POP Sreg instruction, which was incorrectly implemented to emit nothing
Fixed CVTSD2SI, CVTSS2SI, CVTTSD2SI, and CVTTSS2SI instructions to not consider the size of the memory operand when calculagint REX.W prefix
Fixed VCMPPD, VCMPPS, VCMPSD, VCMPSS, VPCMPEQ*, VPCMPGT* instructions to always force EVEX prefix when the first operand is K register
Fixed ENDBR32 and ENDBR64 instructions (wrong opcode)
Fixed CLRSSBSY and RSTORSSP instructions (wrong logic in Assembler)
Fixed SLDT, SMSW, and STR instructions to not consider memory size when determining prefixes
Fixed UD0 and UD1 instructions to consider both operands
Fixed VCVTNE2PS2BF16, VCVTNEPS2BF16, and VDPBF16PS instructions (incorrect calculation of LL field) (AVX512)
Fixed VCVTPD2DQ, VCVTPD2PS, VCVTPD2UDQ, VCVTQQ2PS, VCVTTOD2DQ, VCVTTPD2UDQ, VCVTUQQ2PS in AVX512 case (incorrect calculation of LL field)
Fixed VGATHERPF* and VSCATTERPF* instructions (some instructions were encoded incorrectly by not considering the memory index register type in LL field)
Fixed VPBLENDVB (incorrect calculation of LL field)
Fixed VPEXTRW to use use a shorter encoding when possible (vpextrw r32, xmm, imm)
Fixed VPSLLD, VPSLLQ, VPSLLW, VPSRAD, VPSRAQ, VPSRAW, VPSRLD, VPSRLQ, VPSRLW instructions to always force EVEX prefix when the instruction is RMI (AVX512)
Fixed the accepted memory operand size of MMX PUNPCKL??? instructions from m64 to m32 (only affects validation)
Added explicit forms to XSAVE* and XRSTOR* instructions
Added HRESET and UINTR instructions
Changed MOV and all ARITH instructions to output the same binary as LLVM in 'reg, reg' case (it used an alternative encoding initially)
Renamed LRET to RETF
Renamed VBLENDM* instructions to VPBLENDM* (the name was incorrect)
Renamed VPBROADCASTMB2D to VPBROADCASTMW2D (the name was incorrect)
Renamed SYSEXIT64 to SYSEXITQ and SYSRET64 to SYSRETQ
Removed non-standard IRETW (use IRET, IRETD, or IRETQ to select the form)
