Having 'inline' is fine, however, when debugging a class that has
abstractions then sometimes to step over all of them can be very
frustrating. This is solved by ASMJIT_INLINE_NODEBUG, which tells
compiler that the body of a function doesn't have to be debuggable.
This mostly applies to getters, setters, and wrappers around API
functions.
In addition - some assembler tests were split to make the compilation
a little bit faster, especially when compiling with UBSAN.
* Instruction database is now part of asmjit to keep it in sync
* X86/X64 ISA data has been reworked, now in a proper JSON format
* ARM32 ISA data has been added (currently only DB, support later)
* ARM64 ISA data has been added
* ARM features detection has been updated
* Refactored workflows to use a single workflow for both VM and non-VM builds
* Compiler tests are now able to test compilation of different architectures
In addition, always enable DualMapping when RWX pages are not
possible to allocate in JitAllocator, because otherwise the
allocator would not be able to allocate memory for JIT code
execution.
New CI runners to test FreeBSD, NetBSD, and OpenBSD are also
provided.
[ABI] Added ABI version as an inline namespace, which forms asmjit::_abi_MAJOR_MINOR
[ABI] Added support for AVX512_FP16, 16-bit broadcast, and AVX512_FP16 tests
[ABI] Added initial support for consecutive registers into instruction database and register allocator
[ABI] Added a possibility to use temporary memory in CodeHolder's zone
[ABI] Compiler::setArg() is now deprecated, use FuncNode::setArg()
[Bug] Fixed correct RW information of instructions that only support implicit zeroing with {k}
[Bug] Fixed broadcast to be able to broadcast bcst16 operands
Fixed POP Sreg instruction, which was incorrectly implemented to emit nothing
Fixed CVTSD2SI, CVTSS2SI, CVTTSD2SI, and CVTTSS2SI instructions to not consider the size of the memory operand when calculagint REX.W prefix
Fixed VCMPPD, VCMPPS, VCMPSD, VCMPSS, VPCMPEQ*, VPCMPGT* instructions to always force EVEX prefix when the first operand is K register
Fixed ENDBR32 and ENDBR64 instructions (wrong opcode)
Fixed CLRSSBSY and RSTORSSP instructions (wrong logic in Assembler)
Fixed SLDT, SMSW, and STR instructions to not consider memory size when determining prefixes
Fixed UD0 and UD1 instructions to consider both operands
Fixed VCVTNE2PS2BF16, VCVTNEPS2BF16, and VDPBF16PS instructions (incorrect calculation of LL field) (AVX512)
Fixed VCVTPD2DQ, VCVTPD2PS, VCVTPD2UDQ, VCVTQQ2PS, VCVTTOD2DQ, VCVTTPD2UDQ, VCVTUQQ2PS in AVX512 case (incorrect calculation of LL field)
Fixed VGATHERPF* and VSCATTERPF* instructions (some instructions were encoded incorrectly by not considering the memory index register type in LL field)
Fixed VPBLENDVB (incorrect calculation of LL field)
Fixed VPEXTRW to use use a shorter encoding when possible (vpextrw r32, xmm, imm)
Fixed VPSLLD, VPSLLQ, VPSLLW, VPSRAD, VPSRAQ, VPSRAW, VPSRLD, VPSRLQ, VPSRLW instructions to always force EVEX prefix when the instruction is RMI (AVX512)
Fixed the accepted memory operand size of MMX PUNPCKL??? instructions from m64 to m32 (only affects validation)
Added explicit forms to XSAVE* and XRSTOR* instructions
Added HRESET and UINTR instructions
Changed MOV and all ARITH instructions to output the same binary as LLVM in 'reg, reg' case (it used an alternative encoding initially)
Renamed LRET to RETF
Renamed VBLENDM* instructions to VPBLENDM* (the name was incorrect)
Renamed VPBROADCASTMB2D to VPBROADCASTMW2D (the name was incorrect)
Renamed SYSEXIT64 to SYSEXITQ and SYSRET64 to SYSRETQ
Removed non-standard IRETW (use IRET, IRETD, or IRETQ to select the form)
Refactored build system macros (ASMJIT_BUILD_STATIC -> ASMJIT_STATIC)
Refactored AVX512 broadcast {1toN} - moved to operand from instruction.
Refactored naming - renamed getters to not use get prefix.
Refactored code structure - move arch-specific stuff into x86 namespace.
Refactored some compiler/arch-specific macros, respect rel/abs option in mov REG, [ADDR].
Refactored StringBuilder (Renamed to String, added small string optimization).
Refactored LabelId<->LabelEntry mapping, force label offset to 64-bits on all archs.
Renamed Runtime to Target (JitRuntime kept for now).
Renamed VirtMemManager to JitAllocator.
Renamed VirtMem to JitUtils.
Renamed FuncSignatureX to FuncSignatureBuilder.
Fixed xchg [mem], rex-lo, refactored RelocEntry.
Fixed Logger to always show abs|rel when formatting a memory operand
Fixed Logger to prefix HEX numbers with 0x prefix
Fixed Support::ctzGeneric to always return uint32_t, T doesn't matter.
Fixed LightCall to not save MMX and K registers
Fixed CpuInfo constructor to propagate NoInit (#243)
Added VAES, AVX512_VBMI2, AVX512_VNNI, and AVX512_BITALG cpu-features and instructions.
Added emscripten support (asmjit can be now compiled by emscripten).
Added asmjit.natvis for better MSVC experience
Added x86::ptr_abs|ptr_rel
Added support for multibyte nop r/m (#135)
Added support for 32-bit to 64-bit zero-extended addresses, improved validation of memory addresses, and removed wrt address type as this will be reworked
Added support for multiple sections, reworked address table support (previously known as trampolines)
Added the following x86 modifiers to the x86::Emitter - xacquire(), xrelease(), and k(kreg)
Added a possibility to use REP prefix with RET instruction
Added a possibility to relocate [rel addr] during relocate()
Added a variadic function-call support (Compiler), argument duplication (Compiler), better /dev/shm vs /tmp shared memory handling (VirtMem).
Removed imm_u imm_ptr helpers, imm() can now accept any integer and pointer.
Changed the default behavior of optimizing instructions to disabled with a possibility to enable that feature through kOptionOptimizedForSize
Use default copy construction / assignment to prevent new kind of warnings introduced by GCC 9
Fixed encoding of 'POPCNT|TZCNT|LZCNT r16, r16/m16' instruction
Fixed encoding of EVEX instructions that don't provide VEX prefix equivalent
Added 'LOCK MOV CR8' extension used by AMD processors in 32-bit mode and 'ALTMOVCR8' CPU feature
Renamed some CPU features to respect their names used in X86/X64 architecture manuals
Added validation of immediate operands (correct size, correct sign/zero extension)
Added validation of explicit/implicit size of memory operands
Added validation of LOCK/REP/REPNZ prefixes to x86 validator
Reorganized some X86 instruction tables, removed family specific tables, introduced OperationData
Improved instruction tables generator to automatically generate instruction flags
Regenerated all instruction tables to respect the current state of 'asmdb.x86data'
