diff --git a/CMakeLists.txt b/CMakeLists.txt
index 83c80ab..bfb4fb5 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -138,6 +138,8 @@ cxx_add_source(asmjit ASMJIT_SRC asmjit/base
   func.h
   globals.cpp
   globals.h
+  inst.cpp
+  inst.h
   logging.cpp
   logging.h
   misc_p.h
@@ -185,6 +187,8 @@ cxx_add_source(asmjit ASMJIT_SRC asmjit/x86
   x86internal_p.h
   x86inst.cpp
   x86inst.h
+  x86instimpl.cpp
+  x86instimpl_p.h
   x86logging.cpp
   x86logging_p.h
   x86misc.h
diff --git a/src/asmjit/base.h b/src/asmjit/base.h
index 8d4a916..70b7e82 100644
--- a/src/asmjit/base.h
+++ b/src/asmjit/base.h
@@ -19,6 +19,7 @@
 #include "./base/cpuinfo.h"
 #include "./base/func.h"
 #include "./base/globals.h"
+#include "./base/inst.h"
 #include "./base/logging.h"
 #include "./base/operand.h"
 #include "./base/osutils.h"
diff --git a/src/asmjit/base/assembler.cpp b/src/asmjit/base/assembler.cpp
index 807dbd8..79a2666 100644
--- a/src/asmjit/base/assembler.cpp
+++ b/src/asmjit/base/assembler.cpp
@@ -396,7 +396,7 @@ void Assembler::_emitLog(
   Logging::formatInstruction(
     sb, logOptions,
     this, getArchType(),
-    instId, options, _extraOp, opArray, 6);
+    Inst::Detail(instId, options, _extraReg), opArray, 6);
 
   if ((logOptions & Logger::kOptionBinaryForm) != 0)
     Logging::formatLine(sb, _bufferPtr, emittedSize, relSize, imLen, getInlineComment());
@@ -432,10 +432,10 @@ Error Assembler::_emitFailed(
   Logging::formatInstruction(
     sb, 0,
     this, getArchType(),
-    instId, options, _extraOp, opArray, 6);
+    Inst::Detail(instId, options, _extraReg), opArray, 6);
 
   resetOptions();
-  resetExtraOp();
+  resetExtraReg();
   resetInlineComment();
   return setLastError(err, sb.getData());
 }
diff --git a/src/asmjit/base/codebuilder.cpp b/src/asmjit/base/codebuilder.cpp
index 2f92dc8..1f00248 100644
--- a/src/asmjit/base/codebuilder.cpp
+++ b/src/asmjit/base/codebuilder.cpp
@@ -544,7 +544,7 @@ Error CodeBuilder::serialize(CodeEmitter* dst) {
       case CBNode::kNodeFuncCall: {
         CBInst* node = node_->as<CBInst>();
         dst->setOptions(node->getOptions());
-        dst->setExtraOp(node->getExtraOp());
+        dst->setExtraReg(node->getExtraReg());
         err = dst->emitOpArray(node->getInstId(), node->getOpArray(), node->getOpCount());
         break;
       }
diff --git a/src/asmjit/base/codebuilder.h b/src/asmjit/base/codebuilder.h
index fea0379..dd99e83 100644
--- a/src/asmjit/base/codebuilder.h
+++ b/src/asmjit/base/codebuilder.h
@@ -15,6 +15,7 @@
 #include "../base/assembler.h"
 #include "../base/codeholder.h"
 #include "../base/constpool.h"
+#include "../base/inst.h"
 #include "../base/operand.h"
 #include "../base/utils.h"
 #include "../base/zone.h"
@@ -468,9 +469,8 @@ public:
     : CBNode(cb, kNodeInst) {
 
     orFlags(kFlagIsRemovable);
-    _instId = static_cast<uint16_t>(instId);
-    _reserved = 0;
-    _options = options;
+    _instDetail.instId = static_cast<uint16_t>(instId);
+    _instDetail.options = options;
 
     _opCount = static_cast<uint8_t>(opCount);
     _opArray = opArray;
@@ -485,39 +485,40 @@ public:
   // [Accessors]
   // --------------------------------------------------------------------------
 
-  //! Get the instruction id, see \ref X86Inst::Id.
-  ASMJIT_INLINE uint32_t getInstId() const noexcept { return _instId; }
-  //! Set the instruction id to `instId`.
-  //!
-  //! NOTE: Please do not modify instruction code if you don't know what you
-  //! are doing. Incorrect instruction code and/or operands can cause random
-  //! errors in production builds and will most probably trigger assertion
-  //! failures in debug builds.
-  ASMJIT_INLINE void setInstId(uint32_t instId) noexcept { _instId = static_cast<uint16_t>(instId); }
+  ASMJIT_INLINE Inst::Detail& getInstDetail() noexcept { return _instDetail; }
+  ASMJIT_INLINE const Inst::Detail& getInstDetail() const noexcept { return _instDetail; }
 
-  //! Whether the instruction is either a jump or a conditional jump likely to
-  //! be taken.
+  //! Get the instruction id, see \ref Inst::Id.
+  ASMJIT_INLINE uint32_t getInstId() const noexcept { return _instDetail.instId; }
+  //! Set the instruction id to `instId`, see \ref Inst::Id.
+  ASMJIT_INLINE void setInstId(uint32_t instId) noexcept { _instDetail.instId = instId; }
+
+  //! Whether the instruction is either a jump or a conditional jump likely to be taken.
   ASMJIT_INLINE bool isTaken() const noexcept { return hasFlag(kFlagIsTaken); }
 
   //! Get emit options.
-  ASMJIT_INLINE uint32_t getOptions() const noexcept { return _options; }
+  ASMJIT_INLINE uint32_t getOptions() const noexcept { return _instDetail.options; }
   //! Set emit options.
-  ASMJIT_INLINE void setOptions(uint32_t options) noexcept { _options = options; }
+  ASMJIT_INLINE void setOptions(uint32_t options) noexcept { _instDetail.options = options; }
   //! Add emit options.
-  ASMJIT_INLINE void addOptions(uint32_t options) noexcept { _options |= options; }
+  ASMJIT_INLINE void addOptions(uint32_t options) noexcept { _instDetail.options |= options; }
   //! Mask emit options.
-  ASMJIT_INLINE void andOptions(uint32_t options) noexcept { _options &= options; }
+  ASMJIT_INLINE void andOptions(uint32_t options) noexcept { _instDetail.options &= options; }
   //! Clear emit options.
-  ASMJIT_INLINE void delOptions(uint32_t options) noexcept { _options &= ~options; }
+  ASMJIT_INLINE void delOptions(uint32_t options) noexcept { _instDetail.options &= ~options; }
 
-  //! Get if the node has extra operand.
-  ASMJIT_INLINE bool hasExtraOp() const noexcept { return !_extraOp.isNone(); }
-  //! Get extra operand operand.
-  ASMJIT_INLINE Operand& getExtraOp() noexcept { return _extraOp; }
+  //! Get if the node has an extra register operand.
+  ASMJIT_INLINE bool hasExtraOp() const noexcept { return !_instDetail.hasExtraReg(); }
+  //! Get extra register operand.
+  ASMJIT_INLINE RegOnly& getExtraReg() noexcept { return _instDetail.extraReg; }
   //! \overload
-  ASMJIT_INLINE const Operand& getExtraOp() const noexcept { return _extraOp; }
-  //! Set extra operand.
-  ASMJIT_INLINE void setExtraOp(const Operand& extraOp) noexcept { _extraOp = extraOp; }
+  ASMJIT_INLINE const RegOnly& getExtraReg() const noexcept { return _instDetail.extraReg; }
+  //! Set extra register operand to `reg`.
+  ASMJIT_INLINE void setExtraReg(const Reg& reg) noexcept { _instDetail.extraReg.init(reg); }
+  //! Set extra register operand to `reg`.
+  ASMJIT_INLINE void setExtraReg(const RegOnly& reg) noexcept { _instDetail.extraReg.init(reg); }
+  //! Reset extra register operand.
+  ASMJIT_INLINE void resetExtraReg() noexcept { _instDetail.extraReg.reset(); }
 
   //! Get operands count.
   ASMJIT_INLINE uint32_t getOpCount() const noexcept { return _opCount; }
@@ -570,11 +571,9 @@ Update:
   // [Members]
   // --------------------------------------------------------------------------
 
-  uint16_t _instId;                      //!< Instruction id (architecture dependent).
+  Inst::Detail _instDetail;              //!< Instruction id, options, and extra register.
   uint8_t _memOpIndex;                   //!< \internal
-  uint8_t _reserved;                     //!< \internal
-  uint32_t _options;                     //!< Instruction options.
-  Operand _extraOp;                      //!< Extra operand (REP {cx} or op-mask {k} on AVX-512).
+  uint8_t _reserved[7];                  //!< \internal
   Operand* _opArray;                     //!< Instruction operands.
 };
 
diff --git a/src/asmjit/base/codeemitter.cpp b/src/asmjit/base/codeemitter.cpp
index c4bdfd6..48a4c9a 100644
--- a/src/asmjit/base/codeemitter.cpp
+++ b/src/asmjit/base/codeemitter.cpp
@@ -42,8 +42,8 @@ CodeEmitter::CodeEmitter(uint32_t type) noexcept
     _globalHints(0),
     _globalOptions(kOptionMaybeFailureCase),
     _options(0),
+    _extraReg(),
     _inlineComment(nullptr),
-    _extraOp(),
     _none(),
     _nativeGpReg(),
     _nativeGpArray(nullptr) {}
@@ -79,9 +79,9 @@ Error CodeEmitter::onDetach(CodeHolder* code) noexcept {
   _globalOptions = kOptionMaybeFailureCase;
 
   _options = 0;
+  _extraReg.reset();
   _inlineComment = nullptr;
 
-  _extraOp.reset();
   _nativeGpReg.reset();
   _nativeGpArray = nullptr;
 
@@ -230,30 +230,6 @@ Error CodeEmitter::emit(uint32_t instId, OP o0, OP o1, OP o2, OP o3, OP o4, int6
 
 #undef OP
 
-// ============================================================================
-// [asmjit::CodeEmitter - Validation]
-// ============================================================================
-
-Error CodeEmitter::_validate(uint32_t instId, const Operand_* opArray, uint32_t opCount) const noexcept {
-#if !defined(ASMJIT_DISABLE_VALIDATION)
-  uint32_t archType = getArchType();
-  uint32_t options = getGlobalOptions() | getOptions();
-
-#if defined(ASMJIT_BUILD_X86)
-  if (ArchInfo::isX86Family(archType))
-    return X86Inst::validate(archType, instId, options, _extraOp, opArray, 6);
-#endif
-
-#if defined(ASMJIT_BUILD_ARM)
-  if (ArchInfo::isArmFamily(archType))
-    return ArmInst::validate(archType, instId, options, _extraOp, opArray, 6);
-#endif
-
-  return DebugUtils::errored(kErrorInvalidArch);
-#else
-  return DebugUtils::errored(kErrorFeatureNotEnabled);
-#endif // !ASMJIT_DISABLE_VALIDATION
-}
 } // asmjit namespace
 
 // [Api-End]
diff --git a/src/asmjit/base/codeemitter.h b/src/asmjit/base/codeemitter.h
index 0087a82..93a2de3 100644
--- a/src/asmjit/base/codeemitter.h
+++ b/src/asmjit/base/codeemitter.h
@@ -315,12 +315,16 @@ public:
   //! Reset options of the next instruction.
   ASMJIT_INLINE void resetOptions() noexcept { _options = 0; }
 
+  //! Get if the extra register operand is valid.
+  ASMJIT_INLINE bool hasExtraReg() const noexcept { return _extraReg.isValid(); }
   //! Get an extra operand that will be used by the next instruction (architecture specific).
-  ASMJIT_INLINE const Operand& getExtraOp() const noexcept { return static_cast<const Operand&>(_extraOp); }
+  ASMJIT_INLINE const RegOnly& getExtraReg() const noexcept { return _extraReg; }
   //! Set an extra operand that will be used by the next instruction (architecture specific).
-  ASMJIT_INLINE void setExtraOp(const Operand_& extraOp) noexcept { _extraOp = extraOp; }
+  ASMJIT_INLINE void setExtraReg(const Reg& reg) noexcept { _extraReg.init(reg); }
+  //! Set an extra operand that will be used by the next instruction (architecture specific).
+  ASMJIT_INLINE void setExtraReg(const RegOnly& reg) noexcept { _extraReg.init(reg); }
   //! Reset an extra operand that will be used by the next instruction (architecture specific).
-  ASMJIT_INLINE void resetExtraOp() noexcept { _extraOp.setSignature(0); }
+  ASMJIT_INLINE void resetExtraReg() noexcept { _extraReg.reset(); }
 
   //! Get annotation of the next instruction.
   ASMJIT_INLINE const char* getInlineComment() const noexcept { return _inlineComment; }
@@ -457,13 +461,6 @@ public:
     return _emitOpArray(instId, opArray, opCount);
   }
 
-  // --------------------------------------------------------------------------
-  // [Validation]
-  // --------------------------------------------------------------------------
-
-  //! Validate instruction with current options, called by `_emit()` if validation is enabled.
-  ASMJIT_API Error _validate(uint32_t instId, const Operand_* opArray, uint32_t opCount) const noexcept;
-
   // --------------------------------------------------------------------------
   // [Members]
   // --------------------------------------------------------------------------
@@ -482,9 +479,10 @@ public:
   uint32_t _globalHints;                 //!< Global hints, always in sync with CodeHolder.
   uint32_t _globalOptions;               //!< Global options, combined with `_options` before used by each instruction.
 
-  uint32_t _options;                     //!< Used to pass instruction options       (affects the next instruction).
-  const char* _inlineComment;            //!< Inline comment of the next instruction (affects the next instruction).
-  Operand_ _extraOp;                     //!< Extra operand (op-mask {k} on AVX-512) (affects the next instruction).
+  uint32_t _options;                     //!< Used to pass instruction options        (affects the next instruction).
+  RegOnly _extraReg;                     //!< Extra register (op-mask {k} on AVX-512) (affects the next instruction).
+  const char* _inlineComment;            //!< Inline comment of the next instruction  (affects the next instruction).
+
   Operand_ _none;                        //!< Used to pass unused operands to `_emit()` instead of passing null.
   Reg _nativeGpReg;                      //!< Native GP register with zero id.
   const Reg* _nativeGpArray;             //!< Array of native registers indexed from zero.
diff --git a/src/asmjit/base/cpuinfo.cpp b/src/asmjit/base/cpuinfo.cpp
index 3e0a9aa..bca2f4d 100644
--- a/src/asmjit/base/cpuinfo.cpp
+++ b/src/asmjit/base/cpuinfo.cpp
@@ -548,6 +548,8 @@ ASMJIT_FAVOR_SIZE static void x86DetectCpuInfo(CpuInfo* cpuInfo) noexcept {
 
     x86CallCpuId(&regs, 0xD, 1);
     if (regs.eax & 0x00000001U) cpuInfo->addFeature(CpuInfo::kX86FeatureXSAVEOPT);
+    if (regs.eax & 0x00000002U) cpuInfo->addFeature(CpuInfo::kX86FeatureXSAVEC);
+    if (regs.eax & 0x00000008U) cpuInfo->addFeature(CpuInfo::kX86FeatureXSAVES);
   }
 
   // --------------------------------------------------------------------------
diff --git a/src/asmjit/base/cpuinfo.h b/src/asmjit/base/cpuinfo.h
index a7a647d..268d37e 100644
--- a/src/asmjit/base/cpuinfo.h
+++ b/src/asmjit/base/cpuinfo.h
@@ -1,4 +1,4 @@
- // [AsmJit]
+// [AsmJit]
 // Complete x86/x64 JIT and Remote Assembler for C++.
 //
 // [License]
@@ -19,6 +19,90 @@ namespace asmjit {
 //! \addtogroup asmjit_base
 //! \{
 
+// ============================================================================
+// [asmjit::CpuFeatures]
+// ============================================================================
+
+class CpuFeatures {
+public:
+  typedef uintptr_t BitWord;
+
+  enum {
+    kMaxFeatures = 128,
+    kBitWordSize = static_cast<int>(sizeof(BitWord)) * 8,
+    kNumBitWords = kMaxFeatures / kBitWordSize
+  };
+
+  // --------------------------------------------------------------------------
+  // [Construction / Destruction]
+  // --------------------------------------------------------------------------
+
+  ASMJIT_INLINE CpuFeatures() noexcept { reset(); }
+  ASMJIT_INLINE CpuFeatures(const CpuFeatures& other) noexcept { init(other); }
+
+  // --------------------------------------------------------------------------
+  // [Init / Reset]
+  // --------------------------------------------------------------------------
+
+  ASMJIT_INLINE void init(const CpuFeatures& other) noexcept { ::memcpy(this, &other, sizeof(*this)); }
+  ASMJIT_INLINE void reset() noexcept { ::memset(this, 0, sizeof(*this)); }
+
+  // --------------------------------------------------------------------------
+  // [Ops]
+  // --------------------------------------------------------------------------
+
+  //! Get all features as `BitWord` array.
+  ASMJIT_INLINE BitWord* getBits() noexcept { return _bits; }
+  //! Get all features as `BitWord` array (const).
+  ASMJIT_INLINE const BitWord* getBits() const noexcept { return _bits; }
+
+  //! Get if feature `feature` is present.
+  ASMJIT_INLINE bool has(uint32_t feature) const noexcept {
+    ASMJIT_ASSERT(feature < kMaxFeatures);
+
+    uint32_t idx = feature / kBitWordSize;
+    uint32_t bit = feature % kBitWordSize;
+
+    return static_cast<bool>((_bits[idx] >> bit) & 0x1);
+  }
+
+  //! Get if all features as defined by `other` are  present.
+  ASMJIT_INLINE bool hasAll(const CpuFeatures& other) const noexcept {
+    for (uint32_t i = 0; i < kNumBitWords; i++)
+      if ((_bits[i] & other._bits[i]) != other._bits[i])
+        return false;
+    return true;
+  }
+
+  //! Add a CPU `feature`.
+  ASMJIT_INLINE CpuFeatures& add(uint32_t feature) noexcept {
+    ASMJIT_ASSERT(feature < kMaxFeatures);
+
+    uint32_t idx = feature / kBitWordSize;
+    uint32_t bit = feature % kBitWordSize;
+
+    _bits[idx] |= static_cast<BitWord>(1) << bit;
+    return *this;
+  }
+
+  //! Remove a CPU `feature`.
+  ASMJIT_INLINE CpuFeatures& remove(uint32_t feature) noexcept {
+    ASMJIT_ASSERT(feature < kMaxFeatures);
+
+    uint32_t idx = feature / kBitWordSize;
+    uint32_t bit = feature % kBitWordSize;
+
+    _bits[idx] &= ~(static_cast<BitWord>(1) << bit);
+    return *this;
+  }
+
+  // --------------------------------------------------------------------------
+  // [Members]
+  // --------------------------------------------------------------------------
+
+  BitWord _bits[kNumBitWords];
+};
+
 // ============================================================================
 // [asmjit::CpuInfo]
 // ============================================================================
@@ -105,8 +189,10 @@ public:
     kX86FeatureSMAP,                     //!< CPU has SMAP (supervisor-mode access prevention).
     kX86FeatureSMEP,                     //!< CPU has SMEP (supervisor-mode execution prevention).
     kX86FeatureSHA,                      //!< CPU has SHA-1 and SHA-256.
-    kX86FeatureXSAVE,                    //!< CPU has XSAVE support - XSAVE/XRSTOR, XSETBV/XGETBV, and XCR.
-    kX86FeatureXSAVEOPT,                 //!< CPU has XSAVEOPT support - XSAVEOPT/XSAVEOPT64.
+    kX86FeatureXSAVE,                    //!< CPU has XSAVE support (XSAVE/XRSTOR, XSETBV/XGETBV, and XCR).
+    kX86FeatureXSAVEC,                   //!< CPU has XSAVEC support (XSAVEC).
+    kX86FeatureXSAVES,                   //!< CPU has XSAVES support (XSAVES/XRSTORS).
+    kX86FeatureXSAVEOPT,                 //!< CPU has XSAVEOPT support (XSAVEOPT/XSAVEOPT64).
     kX86FeatureOSXSAVE,                  //!< CPU has XSAVE enabled by OS.
     kX86FeatureAVX,                      //!< CPU has AVX.
     kX86FeatureAVX2,                     //!< CPU has AVX2.
@@ -140,11 +226,6 @@ public:
     kX86FeaturesCount                    //!< Count of X86/X64 CPU features.
   };
 
-  //! \internal
-  enum {
-    kFeaturesPerUInt32 = static_cast<int>(sizeof(uint32_t)) * 8
-  };
-
   // --------------------------------------------------------------------------
   // [ArmInfo]
   // --------------------------------------------------------------------------
@@ -168,6 +249,7 @@ public:
   // --------------------------------------------------------------------------
 
   ASMJIT_INLINE CpuInfo() noexcept { reset(); }
+  ASMJIT_INLINE CpuInfo(const CpuInfo& other) noexcept { init(other); }
 
   // --------------------------------------------------------------------------
   // [Init / Reset]
@@ -178,7 +260,8 @@ public:
     _archInfo.init(archType, archMode);
   }
 
-  ASMJIT_INLINE void reset() noexcept { ::memset(this, 0, sizeof(CpuInfo)); }
+  ASMJIT_INLINE void init(const CpuInfo& other) noexcept { ::memcpy(this, &other, sizeof(*this)); }
+  ASMJIT_INLINE void reset() noexcept { ::memset(this, 0, sizeof(*this)); }
 
   // --------------------------------------------------------------------------
   // [Detect]
@@ -197,12 +280,7 @@ public:
   //! Get CPU architecture sub-type, see \ArchInfo::SubType.
   ASMJIT_INLINE uint32_t getArchSubType() const noexcept { return _archInfo.getSubType(); }
 
-  //! Get CPU vendor string.
-  ASMJIT_INLINE const char* getVendorString() const noexcept { return _vendorString; }
-  //! Get CPU brand string.
-  ASMJIT_INLINE const char* getBrandString() const noexcept { return _brandString; }
-
-  //! Get CPU vendor ID.
+    //! Get CPU vendor ID.
   ASMJIT_INLINE uint32_t getVendorId() const noexcept { return _vendorId; }
   //! Get CPU family ID.
   ASMJIT_INLINE uint32_t getFamily() const noexcept { return _family; }
@@ -216,26 +294,17 @@ public:
     return _hwThreadsCount;
   }
 
+  //! Get all CPU features.
+  ASMJIT_INLINE const CpuFeatures& getFeatures() const noexcept { return _features; }
   //! Get whether CPU has a `feature`.
-  ASMJIT_INLINE bool hasFeature(uint32_t feature) const noexcept {
-    ASMJIT_ASSERT(feature < sizeof(_features) * 8);
-
-    uint32_t pos = feature / kFeaturesPerUInt32;
-    uint32_t bit = feature % kFeaturesPerUInt32;
-
-    return static_cast<bool>((_features[pos] >> bit) & 0x1);
-  }
-
+  ASMJIT_INLINE bool hasFeature(uint32_t feature) const noexcept { return _features.has(feature); }
   //! Add a CPU `feature`.
-  ASMJIT_INLINE CpuInfo& addFeature(uint32_t feature) noexcept {
-    ASMJIT_ASSERT(feature < sizeof(_features) * 8);
+  ASMJIT_INLINE CpuInfo& addFeature(uint32_t feature) noexcept { _features.add(feature); return *this; }
 
-    uint32_t pos = feature / kFeaturesPerUInt32;
-    uint32_t bit = feature % kFeaturesPerUInt32;
-
-    _features[pos] |= static_cast<uint32_t>(1) << bit;
-    return *this;
-  }
+  //! Get CPU vendor string.
+  ASMJIT_INLINE const char* getVendorString() const noexcept { return _vendorString; }
+  //! Get CPU brand string.
+  ASMJIT_INLINE const char* getBrandString() const noexcept { return _brandString; }
 
   // --------------------------------------------------------------------------
   // [Accessors - ARM]
@@ -277,14 +346,14 @@ public:
   // --------------------------------------------------------------------------
 
   ArchInfo _archInfo;                    //!< CPU architecture information.
-  char _vendorString[16];                //!< CPU vendor string.
-  char _brandString[64];                 //!< CPU brand string.
   uint32_t _vendorId;                    //!< CPU vendor id, see \ref Vendor.
   uint32_t _family;                      //!< CPU family ID.
   uint32_t _model;                       //!< CPU model ID.
   uint32_t _stepping;                    //!< CPU stepping.
   uint32_t _hwThreadsCount;              //!< Number of hardware threads.
-  uint32_t _features[8];                 //!< CPU features (bit-array).
+  CpuFeatures _features;                 //!< CPU features.
+  char _vendorString[16];                //!< CPU vendor string.
+  char _brandString[64];                 //!< CPU brand string.
 
   // Architecture specific data.
   union {
diff --git a/src/asmjit/base/globals.h b/src/asmjit/base/globals.h
index 7923d75..74c7251 100644
--- a/src/asmjit/base/globals.h
+++ b/src/asmjit/base/globals.h
@@ -40,8 +40,6 @@ static const uint64_t kNoBaseAddress = ~static_cast<uint64_t>(0);
 
 //! Global definitions.
 ASMJIT_ENUM(Defs) {
-  //! Invalid instruction id.
-  kInvalidInstId = 0,
   //! Invalid register id.
   kInvalidRegId = 0xFF,
 
@@ -75,23 +73,6 @@ ASMJIT_ENUM(Limits) {
 
 } // Globals namespace
 
-// ============================================================================
-// [asmjit::AnyInst]
-// ============================================================================
-
-//! Definitions and utilities related to instructions used by all architectures.
-namespace AnyInst {
-
-ASMJIT_ENUM(JumpType) {
-  kJumpTypeNone        = 0,              //!< Instruction doesn't jump (regular instruction).
-  kJumpTypeDirect      = 1,              //!< Instruction is a unconditional (direct) jump.
-  kJumpTypeConditional = 2,              //!< Instruction is a conditional jump.
-  kJumpTypeCall        = 3,              //!< Instruction is a function call.
-  kJumpTypeReturn      = 4               //!< Instruction is a function return.
-};
-
-} // AnyInst namespace
-
 // ============================================================================
 // [asmjit::Error]
 // ============================================================================
diff --git a/src/asmjit/base/inst.cpp b/src/asmjit/base/inst.cpp
new file mode 100644
index 0000000..cc5ff39
--- /dev/null
+++ b/src/asmjit/base/inst.cpp
@@ -0,0 +1,77 @@
+// [AsmJit]
+// Complete x86/x64 JIT and Remote Assembler for C++.
+//
+// [License]
+// Zlib - See LICENSE.md file in the package.
+
+// [Export]
+#define ASMJIT_EXPORTS
+
+// [Guard]
+#include "../asmjit_build.h"
+#if defined(ASMJIT_BUILD_X86)
+
+// [Dependencies]
+#include "../base/arch.h"
+#include "../base/inst.h"
+
+#if defined(ASMJIT_BUILD_X86)
+# include "../x86/x86instimpl_p.h"
+#endif // ASMJIT_BUILD_X86
+
+#if defined(ASMJIT_BUILD_ARM)
+# include "../arm/arminstimpl_p.h"
+#endif // ASMJIT_BUILD_ARM
+
+// [Api-Begin]
+#include "../asmjit_apibegin.h"
+
+namespace asmjit {
+
+// ============================================================================
+// [asmjit::Inst - Validate]
+// ============================================================================
+
+#if !defined(ASMJIT_DISABLE_VALIDATION)
+Error Inst::validate(uint32_t archType, const Detail& detail, const Operand_* operands, uint32_t count) noexcept {
+  #if defined(ASMJIT_BUILD_X86)
+  if (ArchInfo::isX86Family(archType))
+    return X86InstImpl::validate(archType, detail, operands, count);
+  #endif
+
+  #if defined(ASMJIT_BUILD_ARM)
+  if (ArchInfo::isArmFamily(archType))
+    return ArmInstImpl::validate(archType, detail, operands, count);
+  #endif
+
+  return DebugUtils::errored(kErrorInvalidArch);
+}
+#endif
+
+// ============================================================================
+// [asmjit::Inst - CheckFeatures]
+// ============================================================================
+
+#if !defined(ASMJIT_DISABLE_EXTENSIONS)
+Error Inst::checkFeatures(uint32_t archType, const Detail& detail, const Operand_* operands, uint32_t count, CpuFeatures& out) noexcept {
+  #if defined(ASMJIT_BUILD_X86)
+  if (ArchInfo::isX86Family(archType))
+    return X86InstImpl::checkFeatures(archType, detail, operands, count, out);
+  #endif
+
+  #if defined(ASMJIT_BUILD_ARM)
+  if (ArchInfo::isArmFamily(archType))
+    return ArmInstImpl::checkFeatures(archType, detail, operands, count, out);
+  #endif
+
+  return DebugUtils::errored(kErrorInvalidArch);
+}
+#endif // !defined(ASMJIT_DISABLE_EXTENSIONS)
+
+} // asmjit namespace
+
+// [Api-End]
+#include "../asmjit_apiend.h"
+
+// [Guard]
+#endif // ASMJIT_BUILD_X86
diff --git a/src/asmjit/base/inst.h b/src/asmjit/base/inst.h
new file mode 100644
index 0000000..7bb210a
--- /dev/null
+++ b/src/asmjit/base/inst.h
@@ -0,0 +1,108 @@
+// [AsmJit]
+// Complete x86/x64 JIT and Remote Assembler for C++.
+//
+// [License]
+// Zlib - See LICENSE.md file in the package.
+
+// [Guard]
+#ifndef _ASMJIT_BASE_INST_H
+#define _ASMJIT_BASE_INST_H
+
+// [Dependencies]
+#include "../base/cpuinfo.h"
+#include "../base/operand.h"
+
+// [Api-Begin]
+#include "../asmjit_apibegin.h"
+
+namespace asmjit {
+
+//! \addtogroup asmjit_base
+//! \{
+
+// ============================================================================
+// [asmjit::Inst]
+// ============================================================================
+
+//! Definitions and utilities related to instructions used by all architectures.
+struct Inst {
+  ASMJIT_ENUM(Id) {
+    kIdNone = 0                          //!< Invalid or uninitialized instruction id.
+  };
+
+  //! Describes an instruction's jump type, if any.
+  ASMJIT_ENUM(JumpType) {
+    kJumpTypeNone        = 0,            //!< Instruction doesn't jump (regular instruction).
+    kJumpTypeDirect      = 1,            //!< Instruction is a unconditional (direct) jump.
+    kJumpTypeConditional = 2,            //!< Instruction is a conditional jump.
+    kJumpTypeCall        = 3,            //!< Instruction is a function call.
+    kJumpTypeReturn      = 4             //!< Instruction is a function return.
+  };
+
+  // --------------------------------------------------------------------------
+  // [Detail]
+  // --------------------------------------------------------------------------
+
+  //! Instruction id, options, and extraReg packed in a single structure. This
+  //! structure exists to simplify analysis and validation API that requires a
+  //! lot of information about the instruction to be processed.
+  class Detail {
+  public:
+    ASMJIT_INLINE Detail() noexcept
+      : instId(0),
+        options(0),
+        extraReg() {}
+
+    explicit ASMJIT_INLINE Detail(uint32_t instId, uint32_t options = 0) noexcept
+      : instId(instId),
+        options(options),
+        extraReg() {}
+
+    ASMJIT_INLINE Detail(uint32_t instId, uint32_t options, const RegOnly& reg) noexcept
+      : instId(instId),
+        options(options),
+        extraReg(reg) {}
+
+    ASMJIT_INLINE Detail(uint32_t instId, uint32_t options, const Reg& reg) noexcept
+      : instId(instId),
+        options(options) { extraReg.init(reg); }
+
+    // ------------------------------------------------------------------------
+    // [Accessors]
+    // ------------------------------------------------------------------------
+
+    ASMJIT_INLINE bool hasExtraReg() const noexcept { return extraReg.isValid(); }
+
+    // ------------------------------------------------------------------------
+    // [Members]
+    // ------------------------------------------------------------------------
+
+    uint32_t instId;
+    uint32_t options;
+    RegOnly extraReg;
+  };
+
+  // --------------------------------------------------------------------------
+  // [API]
+  // --------------------------------------------------------------------------
+
+#if !defined(ASMJIT_DISABLE_VALIDATION)
+  //! Validate the given instruction.
+  ASMJIT_API static Error validate(uint32_t archType, const Detail& detail, const Operand_* operands, uint32_t count) noexcept;
+#endif // !ASMJIT_DISABLE_VALIDATION
+
+#if !defined(ASMJIT_DISABLE_EXTENSIONS)
+  //! Check CPU features required to execute the given instruction.
+  ASMJIT_API static Error checkFeatures(uint32_t archType, const Detail& detail, const Operand_* operands, uint32_t count, CpuFeatures& out) noexcept;
+#endif // !defined(ASMJIT_DISABLE_EXTENSIONS)
+};
+
+//! \}
+
+} // asmjit namespace
+
+// [Api-End]
+#include "../asmjit_apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_BASE_INST_H
diff --git a/src/asmjit/base/logging.cpp b/src/asmjit/base/logging.cpp
index 67b9baf..efb4475 100644
--- a/src/asmjit/base/logging.cpp
+++ b/src/asmjit/base/logging.cpp
@@ -233,17 +233,14 @@ Error Logging::formatInstruction(
   uint32_t logOptions,
   const CodeEmitter* emitter,
   uint32_t archType,
-  uint32_t instId,
-  uint32_t options,
-  const Operand_& extraOp,
-  const Operand_* opArray, uint32_t opCount) noexcept {
+  const Inst::Detail& detail, const Operand_* opArray, uint32_t opCount) noexcept {
 
 #if defined(ASMJIT_BUILD_X86)
-  return X86Logging::formatInstruction(sb, logOptions, emitter, archType, instId, options, extraOp, opArray, opCount);
+  return X86Logging::formatInstruction(sb, logOptions, emitter, archType, detail, opArray, opCount);
 #endif // ASMJIT_BUILD_X86
 
 #if defined(ASMJIT_BUILD_ARM)
-  return ArmLogging::formatInstruction(sb, logOptions, emitter, archType, instId, options, extraOp, opArray, opCount);
+  return ArmLogging::formatInstruction(sb, logOptions, emitter, archType, detail, opArray, opCount);
 #endif // ASMJIT_BUILD_ARM
 
   return kErrorInvalidArch;
@@ -372,10 +369,7 @@ Error Logging::formatNode(
       ASMJIT_PROPAGATE(
         Logging::formatInstruction(sb, logOptions, cb,
           cb->getArchType(),
-          node->getInstId(),
-          node->getOptions(),
-          node->getExtraOp(),
-          node->getOpArray(), node->getOpCount()));
+          node->getInstDetail(), node->getOpArray(), node->getOpCount()));
       break;
     }
 
@@ -436,10 +430,7 @@ Error Logging::formatNode(
       ASMJIT_PROPAGATE(
         Logging::formatInstruction(sb, logOptions, cb,
           cb->getArchType(),
-          node->getInstId(),
-          node->getOptions(),
-          node->getExtraOp(),
-          node->getOpArray(), node->getOpCount()));
+          node->getInstDetail(), node->getOpArray(), node->getOpCount()));
       break;
     }
 #endif // !ASMJIT_DISABLE_COMPILER
diff --git a/src/asmjit/base/logging.h b/src/asmjit/base/logging.h
index 12a680b..609f188 100644
--- a/src/asmjit/base/logging.h
+++ b/src/asmjit/base/logging.h
@@ -8,9 +8,8 @@
 #ifndef _ASMJIT_BASE_LOGGING_H
 #define _ASMJIT_BASE_LOGGING_H
 
-#include "../asmjit_build.h"
-
 // [Dependencies]
+#include "../base/inst.h"
 #include "../base/string.h"
 
 // [Api-Begin]
@@ -249,10 +248,7 @@ struct Logging {
     uint32_t logOptions,
     const CodeEmitter* emitter,
     uint32_t archType,
-    uint32_t instId,
-    uint32_t options,
-    const Operand_& extraOp,
-    const Operand_* opArray, uint32_t opCount) noexcept;
+    const Inst::Detail& detail, const Operand_* opArray, uint32_t opCount) noexcept;
 
 #if !defined(ASMJIT_DISABLE_BUILDER)
   ASMJIT_API static Error formatNode(
@@ -262,7 +258,7 @@ struct Logging {
     const CBNode* node_) noexcept;
 #endif // !ASMJIT_DISABLE_BUILDER
 
-// Only used by AsmJit internals, not available for users.
+// Only used by AsmJit internals, not available to users.
 #if defined(ASMJIT_EXPORTS)
   enum {
     // Has to be big to be able to hold all metadata compiler can assign to a
diff --git a/src/asmjit/base/operand.h b/src/asmjit/base/operand.h
index 36def28..2353f98 100644
--- a/src/asmjit/base/operand.h
+++ b/src/asmjit/base/operand.h
@@ -709,10 +709,9 @@ public:
   //! some operands contains a garbage or other metadata in the upper 8 bytes
   //! then `isSame()` may return `true` in cases where `isEqual()` returns
   //! false. However. no such case is known at the moment.
-  ASMJIT_INLINE bool isSame(const Reg& other) const noexcept { return _packed[0] == _packed[1]; }
+  ASMJIT_INLINE bool isSame(const Reg& other) const noexcept { return _packed[0] == other._packed[0]; }
 
-  //! Get if the register type matches `rType`.
-  //! Same as `isReg(rType)`, provided for convenience.
+  //! Get if the register type matches `rType` - same as `isReg(rType)`, provided for convenience.
   ASMJIT_INLINE bool isType(uint32_t rType) const noexcept { return (_signature & kSignatureRegTypeMask) == (rType << kSignatureRegTypeShift); }
   //! Get if the register kind matches `rKind`.
   ASMJIT_INLINE bool isKind(uint32_t rKind) const noexcept { return (_signature & kSignatureRegKindMask) == (rKind << kSignatureRegKindShift); }
@@ -785,6 +784,77 @@ public:
   static ASMJIT_INLINE bool isVec(const Operand_& op, uint32_t rId) noexcept { return isVec(op) & (op.getId() == rId); }
 };
 
+// ============================================================================
+// [asmjit::RegOnly]
+// ============================================================================
+
+//! RegOnly is 8-byte version of `Reg` that only allows to store either `Reg`
+//! or nothing. This class was designed to decrease the space consumed by each
+//! extra "operand" in `CodeEmitter` and `CBInst` classes.
+struct RegOnly {
+  // --------------------------------------------------------------------------
+  // [Init / Reset]
+  // --------------------------------------------------------------------------
+
+  //! Initialize the `RegOnly` instance to hold register `signature` and `id`.
+  ASMJIT_INLINE void init(uint32_t signature, uint32_t id) noexcept {
+    _signature = signature;
+    _id = id;
+  }
+
+  ASMJIT_INLINE void init(const Reg& reg) noexcept { init(reg.getSignature(), reg.getId()); }
+  ASMJIT_INLINE void init(const RegOnly& reg) noexcept { init(reg.getSignature(), reg.getId()); }
+
+  //! Reset the `RegOnly` to none.
+  ASMJIT_INLINE void reset() noexcept { init(0, 0); }
+
+  // --------------------------------------------------------------------------
+  // [Accessors]
+  // --------------------------------------------------------------------------
+
+  //! Get if the `ExtraReg` is none (same as calling `Operand_::isNone()`).
+  ASMJIT_INLINE bool isNone() const noexcept { return _signature == 0; }
+  //! Get if the register is valid (either virtual or physical).
+  ASMJIT_INLINE bool isValid() const noexcept { return _signature != 0; }
+
+  //! Get if this is a physical register.
+  ASMJIT_INLINE bool isPhysReg() const noexcept { return _id < Globals::kInvalidRegId; }
+  //! Get if this is a virtual register (used by \ref CodeCompiler).
+  ASMJIT_INLINE bool isVirtReg() const noexcept { return Operand::isPackedId(_id); }
+
+  //! Get register signature or 0.
+  ASMJIT_INLINE uint32_t getSignature() const noexcept { return _signature; }
+  //! Get register id or 0.
+  ASMJIT_INLINE uint32_t getId() const noexcept { return _id; }
+
+  //! \internal
+  //!
+  //! Unpacks information from operand's signature.
+  ASMJIT_INLINE uint32_t _getSignatureData(uint32_t bits, uint32_t shift) const noexcept { return (_signature >> shift) & bits; }
+
+  //! Get the register type.
+  ASMJIT_INLINE uint32_t getType() const noexcept { return _getSignatureData(Operand::kSignatureRegTypeBits, Operand::kSignatureRegTypeShift); }
+  //! Get the register kind.
+  ASMJIT_INLINE uint32_t getKind() const noexcept { return _getSignatureData(Operand::kSignatureRegKindBits, Operand::kSignatureRegKindShift); }
+
+  // --------------------------------------------------------------------------
+  // [ToReg]
+  // --------------------------------------------------------------------------
+
+  //! Convert back to `RegT` operand.
+  template<typename RegT>
+  ASMJIT_INLINE RegT toReg() const noexcept { return RegT(Init, _signature, _id); }
+
+  // --------------------------------------------------------------------------
+  // [Members]
+  // --------------------------------------------------------------------------
+
+  //! Type of the operand, either `kOpNone` or `kOpReg`.
+  uint32_t _signature;
+  //! Physical or virtual register id.
+  uint32_t _id;
+};
+
 // ============================================================================
 // [asmjit::Mem]
 // ============================================================================
diff --git a/src/asmjit/x86/x86assembler.cpp b/src/asmjit/x86/x86assembler.cpp
index 6ef792e..75b86cd 100644
--- a/src/asmjit/x86/x86assembler.cpp
+++ b/src/asmjit/x86/x86assembler.cpp
@@ -560,6 +560,7 @@ Error X86Assembler::_emit(uint32_t instId, const Operand_& o0, const Operand_& o
         if (ASMJIT_UNLIKELY(err)) goto Failed;
 
         cursor = _bufferPtr;
+        options &= ~1;
       }
     }
 
@@ -582,7 +583,7 @@ Error X86Assembler::_emit(uint32_t instId, const Operand_& o0, const Operand_& o
         opArray[5].reset();
       }
 
-      err = _validate(instId, opArray, 6);
+      err = Inst::validate(getArchType(), Inst::Detail(instId, options, _extraReg), opArray, 6);
       if (ASMJIT_UNLIKELY(err)) goto Failed;
     }
 #endif // !ASMJIT_DISABLE_VALIDATION
@@ -614,7 +615,7 @@ Error X86Assembler::_emit(uint32_t instId, const Operand_& o0, const Operand_& o
       if (ASMJIT_UNLIKELY(!(iFlags & (X86Inst::kFlagRep | X86Inst::kFlagRepnz))))
         goto InvalidRepPrefix;
 
-      if (!_extraOp.isNone() && ASMJIT_UNLIKELY(!X86Reg::isGp(_extraOp, X86Gp::kIdCx)))
+      if (_extraReg.isValid() && ASMJIT_UNLIKELY(_extraReg.getKind() != X86Reg::kKindGp || _extraReg.getId() != X86Gp::kIdCx))
         goto InvalidRepPrefix;
 
       EMIT_BYTE((options & X86Inst::kOptionRepnz) ? 0xF2 : 0xF3);
@@ -4041,15 +4042,13 @@ EmitVexEvexR:
     // Construct `x` - a complete EVEX|VEX prefix.
     uint32_t x = ((opReg << 4) & 0xF980U) |              // [........|........|Vvvvv..R|R.......].
                  ((rbReg << 2) & 0x0060U) |              // [........|........|........|.BB.....].
-                 (x86ExtractLLMM(opCode, options));      // [........|.LL.....|Vvvvv..R|RBBmmmmm].
+                 (x86ExtractLLMM(opCode, options)) |     // [........|.LL.....|Vvvvv..R|RBBmmmmm].
+                 (_extraReg.getId() << 16);              // [........|.LL..aaa|Vvvvv..R|RBBmmmmm].
     opReg &= 0x7;
 
-    // Mark invalid VEX (force EVEX) case:               // [@.......|.LL.....|Vvvvv..R|RBBmmmmm].
+    // Mark invalid VEX (force EVEX) case:               // [@.......|.LL..aaa|Vvvvv..R|RBBmmmmm].
     x |= (~commonData->getFlags() & X86Inst::kFlagVex) << (31 - Utils::firstBitOfT<X86Inst::kFlagVex>());
 
-    if (X86Reg::isK(_extraOp))
-      x |= _extraOp.as<Reg>().getId() << 16;             // [@.......|.LL..aaa|Vvvvv..R|RBBmmmmm].
-
     // Handle AVX512 options by a single branch.
     const uint32_t kAvx512Options = X86Inst::kOptionZMask   |
                                     X86Inst::kOption1ToX    |
@@ -4150,15 +4149,13 @@ EmitVexEvexM:
                  ((rxReg << 3 ) & 0x00000040U) |         // [........|........|........|.X......].
                  ((rxReg << 15) & 0x00080000U) |         // [........|....X...|........|........].
                  ((rbReg << 2 ) & 0x00000020U) |         // [........|........|........|..B.....].
-                 (x86ExtractLLMM(opCode, options));      // [........|.LL.X...|Vvvvv..R|RXBmmmmm].
+                 (x86ExtractLLMM(opCode, options)) |     // [........|.LL.X...|Vvvvv..R|RXBmmmmm].
+                 (_extraReg.getId() << 16)         ;     // [........|.LL.Xaaa|Vvvvv..R|RXBmmmmm].
     opReg &= 0x07U;
 
-    // Mark invalid VEX (force EVEX) case:               // [@.......|.LL.X...|Vvvvv..R|RXBmmmmm].
+    // Mark invalid VEX (force EVEX) case:               // [@.......|.LL.Xaaa|Vvvvv..R|RXBmmmmm].
     x |= (~commonData->getFlags() & X86Inst::kFlagVex) << (31 - Utils::firstBitOfT<X86Inst::kFlagVex>());
 
-    if (X86Reg::isK(_extraOp))
-      x |= _extraOp.as<Reg>().getId() << 16;             // [@.......|.LL.Xaaa|Vvvvv..R|RXBmmmmm].
-
     // Handle AVX512 options by a single branch.
     const uint32_t kAvx512Options = X86Inst::kOption1ToX    |
                                     X86Inst::kOptionZMask   |
@@ -4483,7 +4480,7 @@ EmitDone:
 #endif // !ASMJIT_DISABLE_LOGGING
 
   resetOptions();
-  resetExtraOp();
+  resetExtraReg();
   resetInlineComment();
 
   _bufferPtr = cursor;
diff --git a/src/asmjit/x86/x86compiler.cpp b/src/asmjit/x86/x86compiler.cpp
index eff99cd..236e817 100644
--- a/src/asmjit/x86/x86compiler.cpp
+++ b/src/asmjit/x86/x86compiler.cpp
@@ -124,13 +124,15 @@ Error X86Compiler::_emit(uint32_t instId, const Operand_& o0, const Operand_& o1
         Operand(o3)
       };
 
-      Error err = X86Inst::validate(getArchType(), instId, options, _extraOp, opArray, opCount);
+      Inst::Detail instDetail(instId, options, _extraReg);
+      Error err = Inst::validate(getArchType(), instDetail, opArray, opCount);
+
       if (err) {
 #if !defined(ASMJIT_DISABLE_LOGGING)
         StringBuilderTmp<256> sb;
         sb.appendString(DebugUtils::errorAsString(err));
         sb.appendString(": ");
-        Logging::formatInstruction(sb, 0, this, getArchType(), instId, options, _extraOp, opArray, opCount);
+        Logging::formatInstruction(sb, 0, this, getArchType(), instDetail, opArray, opCount);
         return setLastError(err, sb.getData());
 #else
         return setLastError(err);
@@ -160,8 +162,8 @@ Error X86Compiler::_emit(uint32_t instId, const Operand_& o0, const Operand_& o1
     if (opCount > 3) opArray[3].copyFrom(o3);
 
     new(node) CBJump(this, instId, options, opArray, opCount);
-    node->_extraOp = _extraOp;
-    _extraOp.reset();
+    node->_instDetail.extraReg = _extraReg;
+    _extraReg.reset();
 
     CBLabel* jTarget = nullptr;
     if (!(options & kOptionUnfollow)) {
@@ -212,8 +214,8 @@ Error X86Compiler::_emit(uint32_t instId, const Operand_& o0, const Operand_& o1
     if (opCount > 3) opArray[3].copyFrom(o3);
 
     node = new(node) CBInst(this, instId, options, opArray, opCount);
-    node->_extraOp = _extraOp;
-    _extraOp.reset();
+    node->_instDetail.extraReg = _extraReg;
+    _extraReg.reset();
 
     if (inlineComment) {
       inlineComment = static_cast<char*>(_cbDataZone.dup(inlineComment, ::strlen(inlineComment), true));
@@ -258,13 +260,15 @@ Error X86Compiler::_emit(uint32_t instId, const Operand_& o0, const Operand_& o1
         Operand(o5)
       };
 
-      Error err = X86Inst::validate(getArchType(), instId, options, _extraOp, opArray, opCount);
+      Inst::Detail instDetail(instId, options, _extraReg);
+      Error err = Inst::validate(getArchType(), instDetail, opArray, opCount);
+
       if (err) {
 #if !defined(ASMJIT_DISABLE_LOGGING)
         StringBuilderTmp<256> sb;
         sb.appendString(DebugUtils::errorAsString(err));
         sb.appendString(": ");
-        Logging::formatInstruction(sb, 0, this, getArchType(), instId, options, _extraOp, opArray, opCount);
+        Logging::formatInstruction(sb, 0, this, getArchType(), instDetail, opArray, opCount);
         return setLastError(err, sb.getData());
 #else
         return setLastError(err);
@@ -296,8 +300,8 @@ Error X86Compiler::_emit(uint32_t instId, const Operand_& o0, const Operand_& o1
     if (opCount > 5) opArray[5].copyFrom(o5);
 
     new(node) CBJump(this, instId, options, opArray, opCount);
-    node->_extraOp = _extraOp;
-    _extraOp.reset();
+    node->_instDetail.extraReg = _extraReg;
+    _extraReg.reset();
 
     CBLabel* jTarget = nullptr;
     if (!(options & kOptionUnfollow)) {
@@ -350,8 +354,8 @@ Error X86Compiler::_emit(uint32_t instId, const Operand_& o0, const Operand_& o1
     if (opCount > 5) opArray[5].copyFrom(o5);
 
     node = new(node) CBInst(this, instId, options, opArray, opCount);
-    node->_extraOp = _extraOp;
-    _extraOp.reset();
+    node->_instDetail.extraReg = _extraReg;
+    _extraReg.reset();
 
     if (inlineComment) {
       inlineComment = static_cast<char*>(_cbDataZone.dup(inlineComment, ::strlen(inlineComment), true));
diff --git a/src/asmjit/x86/x86emitter.h b/src/asmjit/x86/x86emitter.h
index 04fb3a0..8237faf 100644
--- a/src/asmjit/x86/x86emitter.h
+++ b/src/asmjit/x86/x86emitter.h
@@ -360,12 +360,12 @@ public:
 
   //! Use REP/REPZ prefix.
   ASMJIT_INLINE This& rep(const X86Gp& zcx) noexcept {
-    static_cast<This*>(this)->_extraOp = zcx;
+    static_cast<This*>(this)->_extraReg.init(zcx);
     return _addOptions(X86Inst::kOptionRep);
   }
   //! Use REPNZ prefix.
   ASMJIT_INLINE This& repnz(const X86Gp& zcx) noexcept {
-    static_cast<This*>(this)->_extraOp = zcx;
+    static_cast<This*>(this)->_extraReg.init(zcx);
     return _addOptions(X86Inst::kOptionRepnz);
   }
 
diff --git a/src/asmjit/x86/x86inst.cpp b/src/asmjit/x86/x86inst.cpp
index 327261c..0050a64 100644
--- a/src/asmjit/x86/x86inst.cpp
+++ b/src/asmjit/x86/x86inst.cpp
@@ -33,7 +33,6 @@
 // [Dependencies]
 #include "../base/cpuinfo.h"
 #include "../base/utils.h"
-#include "../base/misc_p.h"
 #include "../x86/x86inst.h"
 #include "../x86/x86operand.h"
 
@@ -439,122 +438,122 @@ const X86Inst X86InstDB::instData[] = {
   INST(Insertq         , ExtInsertq         , O(F20F00,79,_,_,_,_,_,_  ), O(F20F00,78,_,_,_,_,_,_  ), 0 , 0 , 1172, 97 , 46 , 0 ),
   INST(Int             , X86Int             , O(000000,CD,_,_,_,_,_,_  ), 0                         , 0 , 0 , 963 , 98 , 45 , 0 ),
   INST(Int3            , X86Op              , O(000000,CC,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1180, 34 , 45 , 0 ),
-  INST(Into            , X86Op              , O(000000,CE,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1185, 34 , 54 , 0 ),
+  INST(Into            , X86Op              , O(000000,CE,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1185, 99 , 54 , 0 ),
   INST(Invd            , X86Op              , O(000F00,08,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9463, 34 , 55 , 0 ),
   INST(Invlpg          , X86M_Only          , O(000F00,01,7,_,_,_,_,_  ), 0                         , 0 , 0 , 1190, 35 , 55 , 0 ),
-  INST(Invpcid         , X86Rm_NoRexW       , O(660F38,82,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1197, 99 , 55 , 0 ),
+  INST(Invpcid         , X86Rm_NoRexW       , O(660F38,82,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1197, 100, 55 , 0 ),
   INST(Iret            , X86Op              , O(000000,CF,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1205, 34 , 16 , 0 ),
   INST(Iretd           , X86Op              , O(000000,CF,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1210, 34 , 16 , 0 ),
-  INST(Iretq           , X86Op              , O(000000,CF,_,_,1,_,_,_  ), 0                         , 0 , 0 , 1216, 100, 16 , 0 ),
+  INST(Iretq           , X86Op              , O(000000,CF,_,_,1,_,_,_  ), 0                         , 0 , 0 , 1216, 101, 16 , 0 ),
   INST(Iretw           , X86Op              , O(660000,CF,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1222, 34 , 16 , 0 ),
-  INST(Ja              , X86Jcc             , O(000F00,87,_,_,_,_,_,_  ), O(000000,77,_,_,_,_,_,_  ), 0 , 0 , 1228, 101, 56 , 0 ),
-  INST(Jae             , X86Jcc             , O(000F00,83,_,_,_,_,_,_  ), O(000000,73,_,_,_,_,_,_  ), 0 , 0 , 1231, 102, 57 , 0 ),
-  INST(Jb              , X86Jcc             , O(000F00,82,_,_,_,_,_,_  ), O(000000,72,_,_,_,_,_,_  ), 0 , 0 , 1235, 103, 57 , 0 ),
-  INST(Jbe             , X86Jcc             , O(000F00,86,_,_,_,_,_,_  ), O(000000,76,_,_,_,_,_,_  ), 0 , 0 , 1238, 104, 56 , 0 ),
-  INST(Jc              , X86Jcc             , O(000F00,82,_,_,_,_,_,_  ), O(000000,72,_,_,_,_,_,_  ), 0 , 0 , 1242, 105, 57 , 0 ),
-  INST(Je              , X86Jcc             , O(000F00,84,_,_,_,_,_,_  ), O(000000,74,_,_,_,_,_,_  ), 0 , 0 , 1245, 106, 58 , 0 ),
-  INST(Jecxz           , X86JecxzLoop       , 0                         , O(000000,E3,_,_,_,_,_,_  ), 0 , 0 , 1248, 107, 45 , 0 ),
-  INST(Jg              , X86Jcc             , O(000F00,8F,_,_,_,_,_,_  ), O(000000,7F,_,_,_,_,_,_  ), 0 , 0 , 1254, 108, 59 , 0 ),
-  INST(Jge             , X86Jcc             , O(000F00,8D,_,_,_,_,_,_  ), O(000000,7D,_,_,_,_,_,_  ), 0 , 0 , 1257, 109, 60 , 0 ),
-  INST(Jl              , X86Jcc             , O(000F00,8C,_,_,_,_,_,_  ), O(000000,7C,_,_,_,_,_,_  ), 0 , 0 , 1261, 110, 60 , 0 ),
-  INST(Jle             , X86Jcc             , O(000F00,8E,_,_,_,_,_,_  ), O(000000,7E,_,_,_,_,_,_  ), 0 , 0 , 1264, 111, 59 , 0 ),
-  INST(Jmp             , X86Jmp             , O(000000,FF,4,_,_,_,_,_  ), O(000000,EB,_,_,_,_,_,_  ), 0 , 0 , 1268, 112, 45 , 0 ),
-  INST(Jna             , X86Jcc             , O(000F00,86,_,_,_,_,_,_  ), O(000000,76,_,_,_,_,_,_  ), 0 , 0 , 1272, 104, 56 , 0 ),
-  INST(Jnae            , X86Jcc             , O(000F00,82,_,_,_,_,_,_  ), O(000000,72,_,_,_,_,_,_  ), 0 , 0 , 1276, 103, 57 , 0 ),
-  INST(Jnb             , X86Jcc             , O(000F00,83,_,_,_,_,_,_  ), O(000000,73,_,_,_,_,_,_  ), 0 , 0 , 1281, 102, 57 , 0 ),
-  INST(Jnbe            , X86Jcc             , O(000F00,87,_,_,_,_,_,_  ), O(000000,77,_,_,_,_,_,_  ), 0 , 0 , 1285, 101, 56 , 0 ),
-  INST(Jnc             , X86Jcc             , O(000F00,83,_,_,_,_,_,_  ), O(000000,73,_,_,_,_,_,_  ), 0 , 0 , 1290, 113, 57 , 0 ),
-  INST(Jne             , X86Jcc             , O(000F00,85,_,_,_,_,_,_  ), O(000000,75,_,_,_,_,_,_  ), 0 , 0 , 1294, 114, 58 , 0 ),
-  INST(Jng             , X86Jcc             , O(000F00,8E,_,_,_,_,_,_  ), O(000000,7E,_,_,_,_,_,_  ), 0 , 0 , 1298, 111, 59 , 0 ),
-  INST(Jnge            , X86Jcc             , O(000F00,8C,_,_,_,_,_,_  ), O(000000,7C,_,_,_,_,_,_  ), 0 , 0 , 1302, 110, 60 , 0 ),
-  INST(Jnl             , X86Jcc             , O(000F00,8D,_,_,_,_,_,_  ), O(000000,7D,_,_,_,_,_,_  ), 0 , 0 , 1307, 109, 60 , 0 ),
-  INST(Jnle            , X86Jcc             , O(000F00,8F,_,_,_,_,_,_  ), O(000000,7F,_,_,_,_,_,_  ), 0 , 0 , 1311, 108, 59 , 0 ),
-  INST(Jno             , X86Jcc             , O(000F00,81,_,_,_,_,_,_  ), O(000000,71,_,_,_,_,_,_  ), 0 , 0 , 1316, 115, 54 , 0 ),
-  INST(Jnp             , X86Jcc             , O(000F00,8B,_,_,_,_,_,_  ), O(000000,7B,_,_,_,_,_,_  ), 0 , 0 , 1320, 116, 61 , 0 ),
-  INST(Jns             , X86Jcc             , O(000F00,89,_,_,_,_,_,_  ), O(000000,79,_,_,_,_,_,_  ), 0 , 0 , 1324, 117, 62 , 0 ),
-  INST(Jnz             , X86Jcc             , O(000F00,85,_,_,_,_,_,_  ), O(000000,75,_,_,_,_,_,_  ), 0 , 0 , 1328, 114, 58 , 0 ),
-  INST(Jo              , X86Jcc             , O(000F00,80,_,_,_,_,_,_  ), O(000000,70,_,_,_,_,_,_  ), 0 , 0 , 1332, 118, 54 , 0 ),
-  INST(Jp              , X86Jcc             , O(000F00,8A,_,_,_,_,_,_  ), O(000000,7A,_,_,_,_,_,_  ), 0 , 0 , 1335, 119, 61 , 0 ),
-  INST(Jpe             , X86Jcc             , O(000F00,8A,_,_,_,_,_,_  ), O(000000,7A,_,_,_,_,_,_  ), 0 , 0 , 1338, 119, 61 , 0 ),
-  INST(Jpo             , X86Jcc             , O(000F00,8B,_,_,_,_,_,_  ), O(000000,7B,_,_,_,_,_,_  ), 0 , 0 , 1342, 116, 61 , 0 ),
-  INST(Js              , X86Jcc             , O(000F00,88,_,_,_,_,_,_  ), O(000000,78,_,_,_,_,_,_  ), 0 , 0 , 1346, 120, 62 , 0 ),
-  INST(Jz              , X86Jcc             , O(000F00,84,_,_,_,_,_,_  ), O(000000,74,_,_,_,_,_,_  ), 0 , 0 , 1349, 106, 58 , 0 ),
-  INST(Kaddb           , VexRvm             , V(660F00,4A,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1352, 121, 63 , 0 ),
-  INST(Kaddd           , VexRvm             , V(660F00,4A,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1358, 121, 64 , 0 ),
-  INST(Kaddq           , VexRvm             , V(000F00,4A,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1364, 121, 64 , 0 ),
-  INST(Kaddw           , VexRvm             , V(000F00,4A,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1370, 121, 63 , 0 ),
-  INST(Kandb           , VexRvm             , V(660F00,41,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1376, 121, 63 , 0 ),
-  INST(Kandd           , VexRvm             , V(660F00,41,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1382, 121, 64 , 0 ),
-  INST(Kandnb          , VexRvm             , V(660F00,42,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1388, 121, 63 , 0 ),
-  INST(Kandnd          , VexRvm             , V(660F00,42,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1395, 121, 64 , 0 ),
-  INST(Kandnq          , VexRvm             , V(000F00,42,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1402, 121, 64 , 0 ),
-  INST(Kandnw          , VexRvm             , V(000F00,42,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1409, 121, 65 , 0 ),
-  INST(Kandq           , VexRvm             , V(000F00,41,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1416, 121, 64 , 0 ),
-  INST(Kandw           , VexRvm             , V(000F00,41,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1422, 121, 65 , 0 ),
-  INST(Kmovb           , VexKmov            , V(660F00,90,_,0,0,_,_,_  ), V(660F00,92,_,0,0,_,_,_  ), 0 , 0 , 1428, 122, 63 , 0 ),
-  INST(Kmovd           , VexKmov            , V(660F00,90,_,0,1,_,_,_  ), V(F20F00,92,_,0,0,_,_,_  ), 0 , 0 , 7344, 123, 64 , 0 ),
-  INST(Kmovq           , VexKmov            , V(000F00,90,_,0,1,_,_,_  ), V(F20F00,92,_,0,1,_,_,_  ), 0 , 0 , 7355, 124, 64 , 0 ),
-  INST(Kmovw           , VexKmov            , V(000F00,90,_,0,0,_,_,_  ), V(000F00,92,_,0,0,_,_,_  ), 0 , 0 , 1434, 125, 65 , 0 ),
-  INST(Knotb           , VexRm              , V(660F00,44,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1440, 126, 63 , 0 ),
-  INST(Knotd           , VexRm              , V(660F00,44,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1446, 126, 64 , 0 ),
-  INST(Knotq           , VexRm              , V(000F00,44,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1452, 126, 64 , 0 ),
-  INST(Knotw           , VexRm              , V(000F00,44,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1458, 126, 65 , 0 ),
-  INST(Korb            , VexRvm             , V(660F00,45,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1464, 121, 63 , 0 ),
-  INST(Kord            , VexRvm             , V(660F00,45,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1469, 121, 64 , 0 ),
-  INST(Korq            , VexRvm             , V(000F00,45,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1474, 121, 64 , 0 ),
-  INST(Kortestb        , VexRm              , V(660F00,98,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1479, 127, 66 , 0 ),
-  INST(Kortestd        , VexRm              , V(660F00,98,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1488, 127, 67 , 0 ),
-  INST(Kortestq        , VexRm              , V(000F00,98,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1497, 127, 67 , 0 ),
-  INST(Kortestw        , VexRm              , V(000F00,98,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1506, 127, 68 , 0 ),
-  INST(Korw            , VexRvm             , V(000F00,45,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1515, 121, 65 , 0 ),
-  INST(Kshiftlb        , VexRmi             , V(660F3A,32,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1520, 128, 63 , 0 ),
-  INST(Kshiftld        , VexRmi             , V(660F3A,33,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1529, 128, 64 , 0 ),
-  INST(Kshiftlq        , VexRmi             , V(660F3A,33,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1538, 128, 64 , 0 ),
-  INST(Kshiftlw        , VexRmi             , V(660F3A,32,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1547, 128, 65 , 0 ),
-  INST(Kshiftrb        , VexRmi             , V(660F3A,30,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1556, 128, 63 , 0 ),
-  INST(Kshiftrd        , VexRmi             , V(660F3A,31,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1565, 128, 64 , 0 ),
-  INST(Kshiftrq        , VexRmi             , V(660F3A,31,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1574, 128, 64 , 0 ),
-  INST(Kshiftrw        , VexRmi             , V(660F3A,30,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1583, 128, 65 , 0 ),
-  INST(Ktestb          , VexRm              , V(660F00,99,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1592, 127, 66 , 0 ),
-  INST(Ktestd          , VexRm              , V(660F00,99,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1599, 127, 67 , 0 ),
-  INST(Ktestq          , VexRm              , V(000F00,99,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1606, 127, 67 , 0 ),
-  INST(Ktestw          , VexRm              , V(000F00,99,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1613, 127, 66 , 0 ),
-  INST(Kunpckbw        , VexRvm             , V(660F00,4B,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1620, 121, 65 , 0 ),
-  INST(Kunpckdq        , VexRvm             , V(000F00,4B,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1629, 121, 64 , 0 ),
-  INST(Kunpckwd        , VexRvm             , V(000F00,4B,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1638, 121, 64 , 0 ),
-  INST(Kxnorb          , VexRvm             , V(660F00,46,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1647, 121, 63 , 0 ),
-  INST(Kxnord          , VexRvm             , V(660F00,46,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1654, 121, 64 , 0 ),
-  INST(Kxnorq          , VexRvm             , V(000F00,46,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1661, 121, 64 , 0 ),
-  INST(Kxnorw          , VexRvm             , V(000F00,46,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1668, 121, 65 , 0 ),
-  INST(Kxorb           , VexRvm             , V(660F00,47,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1675, 121, 63 , 0 ),
-  INST(Kxord           , VexRvm             , V(660F00,47,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1681, 121, 64 , 0 ),
-  INST(Kxorq           , VexRvm             , V(000F00,47,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1687, 121, 64 , 0 ),
-  INST(Kxorw           , VexRvm             , V(000F00,47,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1693, 121, 65 , 0 ),
-  INST(Lahf            , X86Op              , O(000000,9F,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1699, 129, 69 , 0 ),
-  INST(Lar             , X86Rm              , O(000F00,02,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1704, 130, 70 , 0 ),
-  INST(Lddqu           , ExtRm              , O(F20F00,F0,_,_,_,_,_,_  ), 0                         , 0 , 16, 5552, 131, 6  , 24),
-  INST(Ldmxcsr         , X86M_Only          , O(000F00,AE,2,_,_,_,_,_  ), 0                         , 0 , 0 , 5559, 132, 5  , 0 ),
-  INST(Lds             , X86Rm              , O(000000,C5,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1708, 133, 45 , 0 ),
-  INST(Lea             , X86Lea             , O(000000,8D,_,_,x,_,_,_  ), 0                         , 0 , 0 , 1712, 134, 0  , 0 ),
+  INST(Ja              , X86Jcc             , O(000F00,87,_,_,_,_,_,_  ), O(000000,77,_,_,_,_,_,_  ), 0 , 0 , 1228, 102, 56 , 0 ),
+  INST(Jae             , X86Jcc             , O(000F00,83,_,_,_,_,_,_  ), O(000000,73,_,_,_,_,_,_  ), 0 , 0 , 1231, 103, 57 , 0 ),
+  INST(Jb              , X86Jcc             , O(000F00,82,_,_,_,_,_,_  ), O(000000,72,_,_,_,_,_,_  ), 0 , 0 , 1235, 104, 57 , 0 ),
+  INST(Jbe             , X86Jcc             , O(000F00,86,_,_,_,_,_,_  ), O(000000,76,_,_,_,_,_,_  ), 0 , 0 , 1238, 105, 56 , 0 ),
+  INST(Jc              , X86Jcc             , O(000F00,82,_,_,_,_,_,_  ), O(000000,72,_,_,_,_,_,_  ), 0 , 0 , 1242, 106, 57 , 0 ),
+  INST(Je              , X86Jcc             , O(000F00,84,_,_,_,_,_,_  ), O(000000,74,_,_,_,_,_,_  ), 0 , 0 , 1245, 107, 58 , 0 ),
+  INST(Jecxz           , X86JecxzLoop       , 0                         , O(000000,E3,_,_,_,_,_,_  ), 0 , 0 , 1248, 108, 45 , 0 ),
+  INST(Jg              , X86Jcc             , O(000F00,8F,_,_,_,_,_,_  ), O(000000,7F,_,_,_,_,_,_  ), 0 , 0 , 1254, 109, 59 , 0 ),
+  INST(Jge             , X86Jcc             , O(000F00,8D,_,_,_,_,_,_  ), O(000000,7D,_,_,_,_,_,_  ), 0 , 0 , 1257, 110, 60 , 0 ),
+  INST(Jl              , X86Jcc             , O(000F00,8C,_,_,_,_,_,_  ), O(000000,7C,_,_,_,_,_,_  ), 0 , 0 , 1261, 111, 60 , 0 ),
+  INST(Jle             , X86Jcc             , O(000F00,8E,_,_,_,_,_,_  ), O(000000,7E,_,_,_,_,_,_  ), 0 , 0 , 1264, 112, 59 , 0 ),
+  INST(Jmp             , X86Jmp             , O(000000,FF,4,_,_,_,_,_  ), O(000000,EB,_,_,_,_,_,_  ), 0 , 0 , 1268, 113, 45 , 0 ),
+  INST(Jna             , X86Jcc             , O(000F00,86,_,_,_,_,_,_  ), O(000000,76,_,_,_,_,_,_  ), 0 , 0 , 1272, 105, 56 , 0 ),
+  INST(Jnae            , X86Jcc             , O(000F00,82,_,_,_,_,_,_  ), O(000000,72,_,_,_,_,_,_  ), 0 , 0 , 1276, 104, 57 , 0 ),
+  INST(Jnb             , X86Jcc             , O(000F00,83,_,_,_,_,_,_  ), O(000000,73,_,_,_,_,_,_  ), 0 , 0 , 1281, 103, 57 , 0 ),
+  INST(Jnbe            , X86Jcc             , O(000F00,87,_,_,_,_,_,_  ), O(000000,77,_,_,_,_,_,_  ), 0 , 0 , 1285, 102, 56 , 0 ),
+  INST(Jnc             , X86Jcc             , O(000F00,83,_,_,_,_,_,_  ), O(000000,73,_,_,_,_,_,_  ), 0 , 0 , 1290, 114, 57 , 0 ),
+  INST(Jne             , X86Jcc             , O(000F00,85,_,_,_,_,_,_  ), O(000000,75,_,_,_,_,_,_  ), 0 , 0 , 1294, 115, 58 , 0 ),
+  INST(Jng             , X86Jcc             , O(000F00,8E,_,_,_,_,_,_  ), O(000000,7E,_,_,_,_,_,_  ), 0 , 0 , 1298, 112, 59 , 0 ),
+  INST(Jnge            , X86Jcc             , O(000F00,8C,_,_,_,_,_,_  ), O(000000,7C,_,_,_,_,_,_  ), 0 , 0 , 1302, 111, 60 , 0 ),
+  INST(Jnl             , X86Jcc             , O(000F00,8D,_,_,_,_,_,_  ), O(000000,7D,_,_,_,_,_,_  ), 0 , 0 , 1307, 110, 60 , 0 ),
+  INST(Jnle            , X86Jcc             , O(000F00,8F,_,_,_,_,_,_  ), O(000000,7F,_,_,_,_,_,_  ), 0 , 0 , 1311, 109, 59 , 0 ),
+  INST(Jno             , X86Jcc             , O(000F00,81,_,_,_,_,_,_  ), O(000000,71,_,_,_,_,_,_  ), 0 , 0 , 1316, 116, 54 , 0 ),
+  INST(Jnp             , X86Jcc             , O(000F00,8B,_,_,_,_,_,_  ), O(000000,7B,_,_,_,_,_,_  ), 0 , 0 , 1320, 117, 61 , 0 ),
+  INST(Jns             , X86Jcc             , O(000F00,89,_,_,_,_,_,_  ), O(000000,79,_,_,_,_,_,_  ), 0 , 0 , 1324, 118, 62 , 0 ),
+  INST(Jnz             , X86Jcc             , O(000F00,85,_,_,_,_,_,_  ), O(000000,75,_,_,_,_,_,_  ), 0 , 0 , 1328, 115, 58 , 0 ),
+  INST(Jo              , X86Jcc             , O(000F00,80,_,_,_,_,_,_  ), O(000000,70,_,_,_,_,_,_  ), 0 , 0 , 1332, 119, 54 , 0 ),
+  INST(Jp              , X86Jcc             , O(000F00,8A,_,_,_,_,_,_  ), O(000000,7A,_,_,_,_,_,_  ), 0 , 0 , 1335, 120, 61 , 0 ),
+  INST(Jpe             , X86Jcc             , O(000F00,8A,_,_,_,_,_,_  ), O(000000,7A,_,_,_,_,_,_  ), 0 , 0 , 1338, 120, 61 , 0 ),
+  INST(Jpo             , X86Jcc             , O(000F00,8B,_,_,_,_,_,_  ), O(000000,7B,_,_,_,_,_,_  ), 0 , 0 , 1342, 117, 61 , 0 ),
+  INST(Js              , X86Jcc             , O(000F00,88,_,_,_,_,_,_  ), O(000000,78,_,_,_,_,_,_  ), 0 , 0 , 1346, 121, 62 , 0 ),
+  INST(Jz              , X86Jcc             , O(000F00,84,_,_,_,_,_,_  ), O(000000,74,_,_,_,_,_,_  ), 0 , 0 , 1349, 107, 58 , 0 ),
+  INST(Kaddb           , VexRvm             , V(660F00,4A,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1352, 122, 63 , 0 ),
+  INST(Kaddd           , VexRvm             , V(660F00,4A,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1358, 122, 64 , 0 ),
+  INST(Kaddq           , VexRvm             , V(000F00,4A,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1364, 122, 64 , 0 ),
+  INST(Kaddw           , VexRvm             , V(000F00,4A,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1370, 122, 63 , 0 ),
+  INST(Kandb           , VexRvm             , V(660F00,41,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1376, 122, 63 , 0 ),
+  INST(Kandd           , VexRvm             , V(660F00,41,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1382, 122, 64 , 0 ),
+  INST(Kandnb          , VexRvm             , V(660F00,42,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1388, 122, 63 , 0 ),
+  INST(Kandnd          , VexRvm             , V(660F00,42,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1395, 122, 64 , 0 ),
+  INST(Kandnq          , VexRvm             , V(000F00,42,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1402, 122, 64 , 0 ),
+  INST(Kandnw          , VexRvm             , V(000F00,42,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1409, 122, 65 , 0 ),
+  INST(Kandq           , VexRvm             , V(000F00,41,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1416, 122, 64 , 0 ),
+  INST(Kandw           , VexRvm             , V(000F00,41,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1422, 122, 65 , 0 ),
+  INST(Kmovb           , VexKmov            , V(660F00,90,_,0,0,_,_,_  ), V(660F00,92,_,0,0,_,_,_  ), 0 , 0 , 1428, 123, 63 , 0 ),
+  INST(Kmovd           , VexKmov            , V(660F00,90,_,0,1,_,_,_  ), V(F20F00,92,_,0,0,_,_,_  ), 0 , 0 , 7344, 124, 64 , 0 ),
+  INST(Kmovq           , VexKmov            , V(000F00,90,_,0,1,_,_,_  ), V(F20F00,92,_,0,1,_,_,_  ), 0 , 0 , 7355, 125, 64 , 0 ),
+  INST(Kmovw           , VexKmov            , V(000F00,90,_,0,0,_,_,_  ), V(000F00,92,_,0,0,_,_,_  ), 0 , 0 , 1434, 126, 65 , 0 ),
+  INST(Knotb           , VexRm              , V(660F00,44,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1440, 127, 63 , 0 ),
+  INST(Knotd           , VexRm              , V(660F00,44,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1446, 127, 64 , 0 ),
+  INST(Knotq           , VexRm              , V(000F00,44,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1452, 127, 64 , 0 ),
+  INST(Knotw           , VexRm              , V(000F00,44,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1458, 127, 65 , 0 ),
+  INST(Korb            , VexRvm             , V(660F00,45,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1464, 122, 63 , 0 ),
+  INST(Kord            , VexRvm             , V(660F00,45,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1469, 122, 64 , 0 ),
+  INST(Korq            , VexRvm             , V(000F00,45,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1474, 122, 64 , 0 ),
+  INST(Kortestb        , VexRm              , V(660F00,98,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1479, 128, 66 , 0 ),
+  INST(Kortestd        , VexRm              , V(660F00,98,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1488, 128, 67 , 0 ),
+  INST(Kortestq        , VexRm              , V(000F00,98,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1497, 128, 67 , 0 ),
+  INST(Kortestw        , VexRm              , V(000F00,98,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1506, 128, 68 , 0 ),
+  INST(Korw            , VexRvm             , V(000F00,45,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1515, 122, 65 , 0 ),
+  INST(Kshiftlb        , VexRmi             , V(660F3A,32,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1520, 129, 63 , 0 ),
+  INST(Kshiftld        , VexRmi             , V(660F3A,33,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1529, 129, 64 , 0 ),
+  INST(Kshiftlq        , VexRmi             , V(660F3A,33,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1538, 129, 64 , 0 ),
+  INST(Kshiftlw        , VexRmi             , V(660F3A,32,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1547, 129, 65 , 0 ),
+  INST(Kshiftrb        , VexRmi             , V(660F3A,30,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1556, 129, 63 , 0 ),
+  INST(Kshiftrd        , VexRmi             , V(660F3A,31,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1565, 129, 64 , 0 ),
+  INST(Kshiftrq        , VexRmi             , V(660F3A,31,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1574, 129, 64 , 0 ),
+  INST(Kshiftrw        , VexRmi             , V(660F3A,30,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1583, 129, 65 , 0 ),
+  INST(Ktestb          , VexRm              , V(660F00,99,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1592, 128, 66 , 0 ),
+  INST(Ktestd          , VexRm              , V(660F00,99,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1599, 128, 67 , 0 ),
+  INST(Ktestq          , VexRm              , V(000F00,99,_,0,1,_,_,_  ), 0                         , 0 , 0 , 1606, 128, 67 , 0 ),
+  INST(Ktestw          , VexRm              , V(000F00,99,_,0,0,_,_,_  ), 0                         , 0 , 0 , 1613, 128, 66 , 0 ),
+  INST(Kunpckbw        , VexRvm             , V(660F00,4B,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1620, 122, 65 , 0 ),
+  INST(Kunpckdq        , VexRvm             , V(000F00,4B,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1629, 122, 64 , 0 ),
+  INST(Kunpckwd        , VexRvm             , V(000F00,4B,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1638, 122, 64 , 0 ),
+  INST(Kxnorb          , VexRvm             , V(660F00,46,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1647, 122, 63 , 0 ),
+  INST(Kxnord          , VexRvm             , V(660F00,46,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1654, 122, 64 , 0 ),
+  INST(Kxnorq          , VexRvm             , V(000F00,46,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1661, 122, 64 , 0 ),
+  INST(Kxnorw          , VexRvm             , V(000F00,46,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1668, 122, 65 , 0 ),
+  INST(Kxorb           , VexRvm             , V(660F00,47,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1675, 122, 63 , 0 ),
+  INST(Kxord           , VexRvm             , V(660F00,47,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1681, 122, 64 , 0 ),
+  INST(Kxorq           , VexRvm             , V(000F00,47,_,1,1,_,_,_  ), 0                         , 0 , 0 , 1687, 122, 64 , 0 ),
+  INST(Kxorw           , VexRvm             , V(000F00,47,_,1,0,_,_,_  ), 0                         , 0 , 0 , 1693, 122, 65 , 0 ),
+  INST(Lahf            , X86Op              , O(000000,9F,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1699, 130, 69 , 0 ),
+  INST(Lar             , X86Rm              , O(000F00,02,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1704, 131, 70 , 0 ),
+  INST(Lddqu           , ExtRm              , O(F20F00,F0,_,_,_,_,_,_  ), 0                         , 0 , 16, 5552, 132, 6  , 24),
+  INST(Ldmxcsr         , X86M_Only          , O(000F00,AE,2,_,_,_,_,_  ), 0                         , 0 , 0 , 5559, 133, 5  , 0 ),
+  INST(Lds             , X86Rm              , O(000000,C5,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1708, 134, 45 , 0 ),
+  INST(Lea             , X86Lea             , O(000000,8D,_,_,x,_,_,_  ), 0                         , 0 , 0 , 1712, 135, 0  , 0 ),
   INST(Leave           , X86Op              , O(000000,C9,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1716, 34 , 45 , 0 ),
-  INST(Les             , X86Rm              , O(000000,C4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1722, 133, 45 , 0 ),
+  INST(Les             , X86Rm              , O(000000,C4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1722, 134, 45 , 0 ),
   INST(Lfence          , X86Fence           , O(000F00,AE,5,_,_,_,_,_  ), 0                         , 0 , 0 , 1726, 34 , 71 , 0 ),
-  INST(Lfs             , X86Rm              , O(000F00,B4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1733, 135, 45 , 0 ),
+  INST(Lfs             , X86Rm              , O(000F00,B4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1733, 136, 45 , 0 ),
   INST(Lgdt            , X86M_Only          , O(000F00,01,2,_,_,_,_,_  ), 0                         , 0 , 0 , 1737, 35 , 23 , 0 ),
-  INST(Lgs             , X86Rm              , O(000F00,B5,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1742, 135, 45 , 0 ),
+  INST(Lgs             , X86Rm              , O(000F00,B5,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1742, 136, 45 , 0 ),
   INST(Lidt            , X86M_Only          , O(000F00,01,3,_,_,_,_,_  ), 0                         , 0 , 0 , 1746, 35 , 23 , 0 ),
-  INST(Lldt            , X86M               , O(000F00,00,2,_,_,_,_,_  ), 0                         , 0 , 0 , 1751, 136, 23 , 0 ),
-  INST(Lmsw            , X86M               , O(000F00,01,6,_,_,_,_,_  ), 0                         , 0 , 0 , 1756, 136, 23 , 0 ),
-  INST(Lods            , X86StrRm           , O(000000,AC,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1761, 137, 72 , 0 ),
-  INST(Loop            , X86JecxzLoop       , 0                         , O(000000,E2,_,_,_,_,_,_  ), 0 , 0 , 1766, 138, 45 , 0 ),
-  INST(Loope           , X86JecxzLoop       , 0                         , O(000000,E1,_,_,_,_,_,_  ), 0 , 0 , 1771, 139, 58 , 0 ),
-  INST(Loopne          , X86JecxzLoop       , 0                         , O(000000,E0,_,_,_,_,_,_  ), 0 , 0 , 1777, 140, 58 , 0 ),
-  INST(Lsl             , X86Rm              , O(000F00,03,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1784, 141, 70 , 0 ),
-  INST(Lss             , X86Rm              , O(000F00,B2,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5959, 135, 45 , 0 ),
-  INST(Ltr             , X86M               , O(000F00,00,3,_,_,_,_,_  ), 0                         , 0 , 0 , 1788, 136, 23 , 0 ),
-  INST(Lzcnt           , X86Rm_Raw66H       , O(F30F00,BD,_,_,x,_,_,_  ), 0                         , 0 , 0 , 1792, 142, 73 , 0 ),
-  INST(Maskmovdqu      , ExtRm_ZDI          , O(660F00,57,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5568, 143, 4  , 25),
-  INST(Maskmovq        , ExtRm_ZDI          , O(000F00,F7,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7352, 144, 74 , 0 ),
+  INST(Lldt            , X86M               , O(000F00,00,2,_,_,_,_,_  ), 0                         , 0 , 0 , 1751, 137, 23 , 0 ),
+  INST(Lmsw            , X86M               , O(000F00,01,6,_,_,_,_,_  ), 0                         , 0 , 0 , 1756, 137, 23 , 0 ),
+  INST(Lods            , X86StrRm           , O(000000,AC,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1761, 138, 72 , 0 ),
+  INST(Loop            , X86JecxzLoop       , 0                         , O(000000,E2,_,_,_,_,_,_  ), 0 , 0 , 1766, 139, 45 , 0 ),
+  INST(Loope           , X86JecxzLoop       , 0                         , O(000000,E1,_,_,_,_,_,_  ), 0 , 0 , 1771, 140, 58 , 0 ),
+  INST(Loopne          , X86JecxzLoop       , 0                         , O(000000,E0,_,_,_,_,_,_  ), 0 , 0 , 1777, 141, 58 , 0 ),
+  INST(Lsl             , X86Rm              , O(000F00,03,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1784, 142, 70 , 0 ),
+  INST(Lss             , X86Rm              , O(000F00,B2,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5959, 136, 45 , 0 ),
+  INST(Ltr             , X86M               , O(000F00,00,3,_,_,_,_,_  ), 0                         , 0 , 0 , 1788, 137, 23 , 0 ),
+  INST(Lzcnt           , X86Rm_Raw66H       , O(F30F00,BD,_,_,x,_,_,_  ), 0                         , 0 , 0 , 1792, 143, 73 , 0 ),
+  INST(Maskmovdqu      , ExtRm_ZDI          , O(660F00,57,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5568, 144, 4  , 25),
+  INST(Maskmovq        , ExtRm_ZDI          , O(000F00,F7,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7352, 145, 74 , 0 ),
   INST(Maxpd           , ExtRm              , O(660F00,5F,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5602, 5  , 4  , 26),
   INST(Maxps           , ExtRm              , O(000F00,5F,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5609, 5  , 5  , 26),
   INST(Maxsd           , ExtRm              , O(F20F00,5F,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7371, 6  , 4  , 26),
@@ -564,181 +563,181 @@ const X86Inst X86InstDB::instData[] = {
   INST(Minps           , ExtRm              , O(000F00,5D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5637, 5  , 5  , 27),
   INST(Minsd           , ExtRm              , O(F20F00,5D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7435, 6  , 4  , 27),
   INST(Minss           , ExtRm              , O(F30F00,5D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5651, 7  , 5  , 27),
-  INST(Monitor         , X86Op              , O(000F01,C8,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1805, 145, 75 , 0 ),
-  INST(Mov             , X86Mov             , 0                         , 0                         , 0 , 0 , 138 , 146, 76 , 0 ),
-  INST(Movapd          , ExtMov             , O(660F00,28,_,_,_,_,_,_  ), O(660F00,29,_,_,_,_,_,_  ), 0 , 16, 5658, 147, 4  , 28),
-  INST(Movaps          , ExtMov             , O(000F00,28,_,_,_,_,_,_  ), O(000F00,29,_,_,_,_,_,_  ), 0 , 16, 5666, 148, 5  , 28),
-  INST(Movbe           , ExtMovbe           , O(000F38,F0,_,_,x,_,_,_  ), O(000F38,F1,_,_,x,_,_,_  ), 0 , 0 , 597 , 149, 77 , 0 ),
-  INST(Movd            , ExtMovd            , O(000F00,6E,_,_,_,_,_,_  ), O(000F00,7E,_,_,_,_,_,_  ), 0 , 16, 7345, 150, 78 , 29),
+  INST(Monitor         , X86Op              , O(000F01,C8,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1805, 146, 75 , 0 ),
+  INST(Mov             , X86Mov             , 0                         , 0                         , 0 , 0 , 138 , 147, 76 , 0 ),
+  INST(Movapd          , ExtMov             , O(660F00,28,_,_,_,_,_,_  ), O(660F00,29,_,_,_,_,_,_  ), 0 , 16, 5658, 148, 4  , 28),
+  INST(Movaps          , ExtMov             , O(000F00,28,_,_,_,_,_,_  ), O(000F00,29,_,_,_,_,_,_  ), 0 , 16, 5666, 149, 5  , 28),
+  INST(Movbe           , ExtMovbe           , O(000F38,F0,_,_,x,_,_,_  ), O(000F38,F1,_,_,x,_,_,_  ), 0 , 0 , 597 , 150, 77 , 0 ),
+  INST(Movd            , ExtMovd            , O(000F00,6E,_,_,_,_,_,_  ), O(000F00,7E,_,_,_,_,_,_  ), 0 , 16, 7345, 151, 78 , 29),
   INST(Movddup         , ExtMov             , O(F20F00,12,_,_,_,_,_,_  ), 0                         , 0 , 16, 5680, 49 , 6  , 29),
-  INST(Movdq2q         , ExtMov             , O(F20F00,D6,_,_,_,_,_,_  ), 0                         , 0 , 8 , 1813, 151, 4  , 0 ),
-  INST(Movdqa          , ExtMov             , O(660F00,6F,_,_,_,_,_,_  ), O(660F00,7F,_,_,_,_,_,_  ), 0 , 16, 5689, 152, 4  , 30),
-  INST(Movdqu          , ExtMov             , O(F30F00,6F,_,_,_,_,_,_  ), O(F30F00,7F,_,_,_,_,_,_  ), 0 , 16, 5572, 153, 4  , 28),
-  INST(Movhlps         , ExtMov             , O(000F00,12,_,_,_,_,_,_  ), 0                         , 0 , 8 , 5764, 154, 5  , 31),
-  INST(Movhpd          , ExtMov             , O(660F00,16,_,_,_,_,_,_  ), O(660F00,17,_,_,_,_,_,_  ), 8 , 8 , 5773, 155, 4  , 32),
-  INST(Movhps          , ExtMov             , O(000F00,16,_,_,_,_,_,_  ), O(000F00,17,_,_,_,_,_,_  ), 8 , 8 , 5781, 156, 5  , 32),
-  INST(Movlhps         , ExtMov             , O(000F00,16,_,_,_,_,_,_  ), 0                         , 8 , 8 , 5789, 157, 5  , 31),
-  INST(Movlpd          , ExtMov             , O(660F00,12,_,_,_,_,_,_  ), O(660F00,13,_,_,_,_,_,_  ), 0 , 8 , 5798, 158, 4  , 32),
-  INST(Movlps          , ExtMov             , O(000F00,12,_,_,_,_,_,_  ), O(000F00,13,_,_,_,_,_,_  ), 0 , 8 , 5806, 159, 5  , 32),
-  INST(Movmskpd        , ExtMov             , O(660F00,50,_,_,_,_,_,_  ), 0                         , 0 , 8 , 5814, 160, 4  , 33),
-  INST(Movmskps        , ExtMov             , O(000F00,50,_,_,_,_,_,_  ), 0                         , 0 , 8 , 5824, 160, 5  , 33),
-  INST(Movntdq         , ExtMov             , 0                         , O(660F00,E7,_,_,_,_,_,_  ), 0 , 16, 5834, 161, 4  , 33),
-  INST(Movntdqa        , ExtMov             , O(660F38,2A,_,_,_,_,_,_  ), 0                         , 0 , 16, 5843, 131, 12 , 33),
-  INST(Movnti          , ExtMovnti          , O(000F00,C3,_,_,x,_,_,_  ), 0                         , 0 , 8 , 1821, 162, 4  , 0 ),
-  INST(Movntpd         , ExtMov             , 0                         , O(660F00,2B,_,_,_,_,_,_  ), 0 , 16, 5853, 163, 4  , 34),
-  INST(Movntps         , ExtMov             , 0                         , O(000F00,2B,_,_,_,_,_,_  ), 0 , 16, 5862, 164, 5  , 34),
-  INST(Movntq          , ExtMov             , 0                         , O(000F00,E7,_,_,_,_,_,_  ), 0 , 8 , 1828, 165, 74 , 0 ),
-  INST(Movntsd         , ExtMov             , 0                         , O(F20F00,2B,_,_,_,_,_,_  ), 0 , 8 , 1835, 166, 46 , 0 ),
-  INST(Movntss         , ExtMov             , 0                         , O(F30F00,2B,_,_,_,_,_,_  ), 0 , 4 , 1843, 167, 46 , 0 ),
-  INST(Movq            , ExtMovq            , O(000F00,6E,_,_,x,_,_,_  ), O(000F00,7E,_,_,x,_,_,_  ), 0 , 16, 7356, 168, 78 , 28),
-  INST(Movq2dq         , ExtRm              , O(F30F00,D6,_,_,_,_,_,_  ), 0                         , 0 , 16, 1851, 169, 4  , 0 ),
-  INST(Movs            , X86StrMm           , O(000000,A4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 411 , 170, 72 , 0 ),
-  INST(Movsd           , ExtMov             , O(F20F00,10,_,_,_,_,_,_  ), O(F20F00,11,_,_,_,_,_,_  ), 0 , 8 , 5877, 171, 79 , 35),
+  INST(Movdq2q         , ExtMov             , O(F20F00,D6,_,_,_,_,_,_  ), 0                         , 0 , 8 , 1813, 152, 4  , 0 ),
+  INST(Movdqa          , ExtMov             , O(660F00,6F,_,_,_,_,_,_  ), O(660F00,7F,_,_,_,_,_,_  ), 0 , 16, 5689, 153, 4  , 30),
+  INST(Movdqu          , ExtMov             , O(F30F00,6F,_,_,_,_,_,_  ), O(F30F00,7F,_,_,_,_,_,_  ), 0 , 16, 5572, 154, 4  , 28),
+  INST(Movhlps         , ExtMov             , O(000F00,12,_,_,_,_,_,_  ), 0                         , 0 , 8 , 5764, 155, 5  , 31),
+  INST(Movhpd          , ExtMov             , O(660F00,16,_,_,_,_,_,_  ), O(660F00,17,_,_,_,_,_,_  ), 8 , 8 , 5773, 156, 4  , 32),
+  INST(Movhps          , ExtMov             , O(000F00,16,_,_,_,_,_,_  ), O(000F00,17,_,_,_,_,_,_  ), 8 , 8 , 5781, 157, 5  , 32),
+  INST(Movlhps         , ExtMov             , O(000F00,16,_,_,_,_,_,_  ), 0                         , 8 , 8 , 5789, 158, 5  , 31),
+  INST(Movlpd          , ExtMov             , O(660F00,12,_,_,_,_,_,_  ), O(660F00,13,_,_,_,_,_,_  ), 0 , 8 , 5798, 159, 4  , 32),
+  INST(Movlps          , ExtMov             , O(000F00,12,_,_,_,_,_,_  ), O(000F00,13,_,_,_,_,_,_  ), 0 , 8 , 5806, 160, 5  , 32),
+  INST(Movmskpd        , ExtMov             , O(660F00,50,_,_,_,_,_,_  ), 0                         , 0 , 8 , 5814, 161, 4  , 33),
+  INST(Movmskps        , ExtMov             , O(000F00,50,_,_,_,_,_,_  ), 0                         , 0 , 8 , 5824, 161, 5  , 33),
+  INST(Movntdq         , ExtMov             , 0                         , O(660F00,E7,_,_,_,_,_,_  ), 0 , 16, 5834, 162, 4  , 33),
+  INST(Movntdqa        , ExtMov             , O(660F38,2A,_,_,_,_,_,_  ), 0                         , 0 , 16, 5843, 132, 12 , 33),
+  INST(Movnti          , ExtMovnti          , O(000F00,C3,_,_,x,_,_,_  ), 0                         , 0 , 8 , 1821, 163, 4  , 0 ),
+  INST(Movntpd         , ExtMov             , 0                         , O(660F00,2B,_,_,_,_,_,_  ), 0 , 16, 5853, 164, 4  , 34),
+  INST(Movntps         , ExtMov             , 0                         , O(000F00,2B,_,_,_,_,_,_  ), 0 , 16, 5862, 165, 5  , 34),
+  INST(Movntq          , ExtMov             , 0                         , O(000F00,E7,_,_,_,_,_,_  ), 0 , 8 , 1828, 166, 74 , 0 ),
+  INST(Movntsd         , ExtMov             , 0                         , O(F20F00,2B,_,_,_,_,_,_  ), 0 , 8 , 1835, 167, 46 , 0 ),
+  INST(Movntss         , ExtMov             , 0                         , O(F30F00,2B,_,_,_,_,_,_  ), 0 , 4 , 1843, 168, 46 , 0 ),
+  INST(Movq            , ExtMovq            , O(000F00,6E,_,_,x,_,_,_  ), O(000F00,7E,_,_,x,_,_,_  ), 0 , 16, 7356, 169, 78 , 28),
+  INST(Movq2dq         , ExtRm              , O(F30F00,D6,_,_,_,_,_,_  ), 0                         , 0 , 16, 1851, 170, 4  , 0 ),
+  INST(Movs            , X86StrMm           , O(000000,A4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 411 , 171, 72 , 0 ),
+  INST(Movsd           , ExtMov             , O(F20F00,10,_,_,_,_,_,_  ), O(F20F00,11,_,_,_,_,_,_  ), 0 , 8 , 5877, 172, 79 , 35),
   INST(Movshdup        , ExtRm              , O(F30F00,16,_,_,_,_,_,_  ), 0                         , 0 , 16, 5884, 50 , 6  , 30),
   INST(Movsldup        , ExtRm              , O(F30F00,12,_,_,_,_,_,_  ), 0                         , 0 , 16, 5894, 50 , 6  , 30),
-  INST(Movss           , ExtMov             , O(F30F00,10,_,_,_,_,_,_  ), O(F30F00,11,_,_,_,_,_,_  ), 0 , 4 , 5904, 172, 80 , 35),
-  INST(Movsx           , X86MovsxMovzx      , O(000F00,BE,_,_,x,_,_,_  ), 0                         , 0 , 0 , 1859, 173, 0  , 0 ),
-  INST(Movsxd          , X86Rm              , O(000000,63,_,_,1,_,_,_  ), 0                         , 0 , 0 , 1865, 174, 0  , 0 ),
-  INST(Movupd          , ExtMov             , O(660F00,10,_,_,_,_,_,_  ), O(660F00,11,_,_,_,_,_,_  ), 0 , 16, 5911, 175, 4  , 36),
-  INST(Movups          , ExtMov             , O(000F00,10,_,_,_,_,_,_  ), O(000F00,11,_,_,_,_,_,_  ), 0 , 16, 5919, 176, 5  , 36),
-  INST(Movzx           , X86MovsxMovzx      , O(000F00,B6,_,_,x,_,_,_  ), 0                         , 0 , 0 , 1872, 173, 0  , 0 ),
+  INST(Movss           , ExtMov             , O(F30F00,10,_,_,_,_,_,_  ), O(F30F00,11,_,_,_,_,_,_  ), 0 , 4 , 5904, 173, 80 , 35),
+  INST(Movsx           , X86MovsxMovzx      , O(000F00,BE,_,_,x,_,_,_  ), 0                         , 0 , 0 , 1859, 174, 0  , 0 ),
+  INST(Movsxd          , X86Rm              , O(000000,63,_,_,1,_,_,_  ), 0                         , 0 , 0 , 1865, 175, 0  , 0 ),
+  INST(Movupd          , ExtMov             , O(660F00,10,_,_,_,_,_,_  ), O(660F00,11,_,_,_,_,_,_  ), 0 , 16, 5911, 176, 4  , 36),
+  INST(Movups          , ExtMov             , O(000F00,10,_,_,_,_,_,_  ), O(000F00,11,_,_,_,_,_,_  ), 0 , 16, 5919, 177, 5  , 36),
+  INST(Movzx           , X86MovsxMovzx      , O(000F00,B6,_,_,x,_,_,_  ), 0                         , 0 , 0 , 1872, 174, 0  , 0 ),
   INST(Mpsadbw         , ExtRmi             , O(660F3A,42,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5927, 16 , 12 , 37),
-  INST(Mul             , X86M_GPB_MulDiv    , O(000000,F6,4,_,x,_,_,_  ), 0                         , 0 , 0 , 769 , 177, 1  , 0 ),
+  INST(Mul             , X86M_GPB_MulDiv    , O(000000,F6,4,_,x,_,_,_  ), 0                         , 0 , 0 , 769 , 178, 1  , 0 ),
   INST(Mulpd           , ExtRm              , O(660F00,59,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5936, 5  , 4  , 38),
   INST(Mulps           , ExtRm              , O(000F00,59,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5943, 5  , 5  , 38),
   INST(Mulsd           , ExtRm              , O(F20F00,59,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5950, 6  , 4  , 38),
   INST(Mulss           , ExtRm              , O(F30F00,59,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5957, 7  , 5  , 38),
-  INST(Mulx            , VexRvm_ZDX_Wx      , V(F20F38,F6,_,0,x,_,_,_  ), 0                         , 0 , 0 , 1878, 178, 81 , 0 ),
-  INST(Mwait           , X86Op              , O(000F01,C9,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1883, 179, 75 , 0 ),
-  INST(Neg             , X86M_GPB           , O(000000,F6,3,_,x,_,_,_  ), 0                         , 0 , 0 , 1889, 180, 1  , 0 ),
-  INST(Nop             , X86Op              , O(000000,90,_,_,_,_,_,_  ), 0                         , 0 , 0 , 900 , 181, 0  , 0 ),
-  INST(Not             , X86M_GPB           , O(000000,F6,2,_,x,_,_,_  ), 0                         , 0 , 0 , 1893, 180, 0  , 0 ),
-  INST(Or              , X86Arith           , O(000000,08,1,_,x,_,_,_  ), 0                         , 0 , 0 , 1109, 182, 1  , 0 ),
+  INST(Mulx            , VexRvm_ZDX_Wx      , V(F20F38,F6,_,0,x,_,_,_  ), 0                         , 0 , 0 , 1878, 179, 81 , 0 ),
+  INST(Mwait           , X86Op              , O(000F01,C9,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1883, 180, 75 , 0 ),
+  INST(Neg             , X86M_GPB           , O(000000,F6,3,_,x,_,_,_  ), 0                         , 0 , 0 , 1889, 181, 1  , 0 ),
+  INST(Nop             , X86Op              , O(000000,90,_,_,_,_,_,_  ), 0                         , 0 , 0 , 900 , 182, 0  , 0 ),
+  INST(Not             , X86M_GPB           , O(000000,F6,2,_,x,_,_,_  ), 0                         , 0 , 0 , 1893, 181, 0  , 0 ),
+  INST(Or              , X86Arith           , O(000000,08,1,_,x,_,_,_  ), 0                         , 0 , 0 , 1109, 183, 1  , 0 ),
   INST(Orpd            , ExtRm              , O(660F00,56,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9429, 12 , 4  , 39),
   INST(Orps            , ExtRm              , O(000F00,56,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9436, 12 , 5  , 39),
-  INST(Out             , X86Out             , O(000000,EE,_,_,_,_,_,_  ), O(000000,E6,_,_,_,_,_,_  ), 0 , 0 , 1897, 183, 45 , 0 ),
-  INST(Outs            , X86Outs            , O(000000,6E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1901, 184, 45 , 0 ),
-  INST(Pabsb           , ExtRm_P            , O(000F38,1C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5997, 185, 82 , 40),
-  INST(Pabsd           , ExtRm_P            , O(000F38,1E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6004, 185, 82 , 40),
-  INST(Pabsw           , ExtRm_P            , O(000F38,1D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6018, 185, 82 , 41),
-  INST(Packssdw        , ExtRm_P            , O(000F00,6B,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6025, 186, 78 , 42),
-  INST(Packsswb        , ExtRm_P            , O(000F00,63,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6035, 186, 78 , 42),
+  INST(Out             , X86Out             , O(000000,EE,_,_,_,_,_,_  ), O(000000,E6,_,_,_,_,_,_  ), 0 , 0 , 1897, 184, 45 , 0 ),
+  INST(Outs            , X86Outs            , O(000000,6E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1901, 185, 45 , 0 ),
+  INST(Pabsb           , ExtRm_P            , O(000F38,1C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5997, 186, 82 , 40),
+  INST(Pabsd           , ExtRm_P            , O(000F38,1E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6004, 186, 82 , 40),
+  INST(Pabsw           , ExtRm_P            , O(000F38,1D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6018, 186, 82 , 41),
+  INST(Packssdw        , ExtRm_P            , O(000F00,6B,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6025, 187, 78 , 42),
+  INST(Packsswb        , ExtRm_P            , O(000F00,63,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6035, 187, 78 , 42),
   INST(Packusdw        , ExtRm              , O(660F38,2B,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6045, 5  , 12 , 42),
-  INST(Packuswb        , ExtRm_P            , O(000F00,67,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6055, 186, 78 , 42),
-  INST(Paddb           , ExtRm_P            , O(000F00,FC,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6065, 186, 78 , 42),
-  INST(Paddd           , ExtRm_P            , O(000F00,FE,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6072, 186, 78 , 42),
-  INST(Paddq           , ExtRm_P            , O(000F00,D4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6079, 186, 4  , 42),
-  INST(Paddsb          , ExtRm_P            , O(000F00,EC,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6086, 186, 78 , 42),
-  INST(Paddsw          , ExtRm_P            , O(000F00,ED,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6094, 186, 78 , 42),
-  INST(Paddusb         , ExtRm_P            , O(000F00,DC,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6102, 186, 78 , 42),
-  INST(Paddusw         , ExtRm_P            , O(000F00,DD,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6111, 186, 78 , 42),
-  INST(Paddw           , ExtRm_P            , O(000F00,FD,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6120, 186, 78 , 42),
-  INST(Palignr         , ExtRmi_P           , O(000F3A,0F,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6127, 187, 6  , 42),
-  INST(Pand            , ExtRm_P            , O(000F00,DB,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6136, 188, 78 , 42),
-  INST(Pandn           , ExtRm_P            , O(000F00,DF,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6149, 189, 78 , 43),
+  INST(Packuswb        , ExtRm_P            , O(000F00,67,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6055, 187, 78 , 42),
+  INST(Paddb           , ExtRm_P            , O(000F00,FC,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6065, 187, 78 , 42),
+  INST(Paddd           , ExtRm_P            , O(000F00,FE,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6072, 187, 78 , 42),
+  INST(Paddq           , ExtRm_P            , O(000F00,D4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6079, 187, 4  , 42),
+  INST(Paddsb          , ExtRm_P            , O(000F00,EC,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6086, 187, 78 , 42),
+  INST(Paddsw          , ExtRm_P            , O(000F00,ED,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6094, 187, 78 , 42),
+  INST(Paddusb         , ExtRm_P            , O(000F00,DC,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6102, 187, 78 , 42),
+  INST(Paddusw         , ExtRm_P            , O(000F00,DD,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6111, 187, 78 , 42),
+  INST(Paddw           , ExtRm_P            , O(000F00,FD,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6120, 187, 78 , 42),
+  INST(Palignr         , ExtRmi_P           , O(000F3A,0F,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6127, 188, 6  , 42),
+  INST(Pand            , ExtRm_P            , O(000F00,DB,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6136, 189, 78 , 42),
+  INST(Pandn           , ExtRm_P            , O(000F00,DF,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6149, 190, 78 , 43),
   INST(Pause           , X86Op              , O(F30000,90,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1906, 34 , 45 , 0 ),
-  INST(Pavgb           , ExtRm_P            , O(000F00,E0,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6179, 186, 83 , 44),
-  INST(Pavgusb         , Ext3dNow           , O(000F0F,BF,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1912, 190, 84 , 0 ),
-  INST(Pavgw           , ExtRm_P            , O(000F00,E3,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6186, 186, 83 , 45),
+  INST(Pavgb           , ExtRm_P            , O(000F00,E0,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6179, 187, 83 , 44),
+  INST(Pavgusb         , Ext3dNow           , O(000F0F,BF,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1912, 191, 84 , 0 ),
+  INST(Pavgw           , ExtRm_P            , O(000F00,E3,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6186, 187, 83 , 45),
   INST(Pblendvb        , ExtRm_XMM0         , O(660F38,10,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6202, 17 , 12 , 46),
   INST(Pblendw         , ExtRmi             , O(660F3A,0E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6212, 16 , 12 , 44),
   INST(Pclmulqdq       , ExtRmi             , O(660F3A,44,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6305, 16 , 85 , 47),
-  INST(Pcmpeqb         , ExtRm_P            , O(000F00,74,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6337, 189, 78 , 48),
-  INST(Pcmpeqd         , ExtRm_P            , O(000F00,76,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6346, 189, 78 , 48),
-  INST(Pcmpeqq         , ExtRm              , O(660F38,29,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6355, 191, 12 , 48),
-  INST(Pcmpeqw         , ExtRm_P            , O(000F00,75,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6364, 189, 78 , 48),
-  INST(Pcmpestri       , ExtRmi             , O(660F3A,61,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6373, 192, 86 , 49),
-  INST(Pcmpestrm       , ExtRmi             , O(660F3A,60,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6384, 193, 86 , 49),
-  INST(Pcmpgtb         , ExtRm_P            , O(000F00,64,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6395, 189, 78 , 48),
-  INST(Pcmpgtd         , ExtRm_P            , O(000F00,66,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6404, 189, 78 , 48),
-  INST(Pcmpgtq         , ExtRm              , O(660F38,37,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6413, 191, 42 , 48),
-  INST(Pcmpgtw         , ExtRm_P            , O(000F00,65,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6422, 189, 78 , 48),
-  INST(Pcmpistri       , ExtRmi             , O(660F3A,63,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6431, 194, 86 , 49),
-  INST(Pcmpistrm       , ExtRmi             , O(660F3A,62,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6442, 195, 86 , 49),
+  INST(Pcmpeqb         , ExtRm_P            , O(000F00,74,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6337, 190, 78 , 48),
+  INST(Pcmpeqd         , ExtRm_P            , O(000F00,76,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6346, 190, 78 , 48),
+  INST(Pcmpeqq         , ExtRm              , O(660F38,29,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6355, 192, 12 , 48),
+  INST(Pcmpeqw         , ExtRm_P            , O(000F00,75,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6364, 190, 78 , 48),
+  INST(Pcmpestri       , ExtRmi             , O(660F3A,61,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6373, 193, 86 , 49),
+  INST(Pcmpestrm       , ExtRmi             , O(660F3A,60,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6384, 194, 86 , 49),
+  INST(Pcmpgtb         , ExtRm_P            , O(000F00,64,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6395, 190, 78 , 48),
+  INST(Pcmpgtd         , ExtRm_P            , O(000F00,66,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6404, 190, 78 , 48),
+  INST(Pcmpgtq         , ExtRm              , O(660F38,37,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6413, 192, 42 , 48),
+  INST(Pcmpgtw         , ExtRm_P            , O(000F00,65,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6422, 190, 78 , 48),
+  INST(Pcmpistri       , ExtRmi             , O(660F3A,63,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6431, 195, 86 , 49),
+  INST(Pcmpistrm       , ExtRmi             , O(660F3A,62,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6442, 196, 86 , 49),
   INST(Pcommit         , X86Op_O            , O(660F00,AE,7,_,_,_,_,_  ), 0                         , 0 , 0 , 1920, 34 , 87 , 0 ),
   INST(Pdep            , VexRvm_Wx          , V(F20F38,F5,_,0,x,_,_,_  ), 0                         , 0 , 0 , 1928, 11 , 81 , 0 ),
   INST(Pext            , VexRvm_Wx          , V(F30F38,F5,_,0,x,_,_,_  ), 0                         , 0 , 0 , 1933, 11 , 81 , 0 ),
-  INST(Pextrb          , ExtExtract         , O(000F3A,14,_,_,_,_,_,_  ), 0                         , 0 , 8 , 6847, 196, 12 , 50),
+  INST(Pextrb          , ExtExtract         , O(000F3A,14,_,_,_,_,_,_  ), 0                         , 0 , 8 , 6847, 197, 12 , 50),
   INST(Pextrd          , ExtExtract         , O(000F3A,16,_,_,_,_,_,_  ), 0                         , 0 , 8 , 6855, 67 , 12 , 50),
-  INST(Pextrq          , ExtExtract         , O(000F3A,16,_,_,1,_,_,_  ), 0                         , 0 , 8 , 6863, 197, 12 , 50),
-  INST(Pextrw          , ExtPextrw          , O(000F00,C5,_,_,_,_,_,_  ), O(000F3A,15,_,_,_,_,_,_  ), 0 , 8 , 6871, 198, 88 , 50),
-  INST(Pf2id           , Ext3dNow           , O(000F0F,1D,_,_,_,_,_,_  ), 0                         , 0 , 8 , 1938, 199, 84 , 0 ),
-  INST(Pf2iw           , Ext3dNow           , O(000F0F,1C,_,_,_,_,_,_  ), 0                         , 0 , 8 , 1944, 199, 89 , 0 ),
-  INST(Pfacc           , Ext3dNow           , O(000F0F,AE,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1950, 190, 84 , 0 ),
-  INST(Pfadd           , Ext3dNow           , O(000F0F,9E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1956, 190, 84 , 0 ),
-  INST(Pfcmpeq         , Ext3dNow           , O(000F0F,B0,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1962, 190, 84 , 0 ),
-  INST(Pfcmpge         , Ext3dNow           , O(000F0F,90,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1970, 190, 84 , 0 ),
-  INST(Pfcmpgt         , Ext3dNow           , O(000F0F,A0,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1978, 190, 84 , 0 ),
-  INST(Pfmax           , Ext3dNow           , O(000F0F,A4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1986, 190, 84 , 0 ),
-  INST(Pfmin           , Ext3dNow           , O(000F0F,94,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1992, 190, 84 , 0 ),
-  INST(Pfmul           , Ext3dNow           , O(000F0F,B4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1998, 190, 84 , 0 ),
-  INST(Pfnacc          , Ext3dNow           , O(000F0F,8A,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2004, 190, 89 , 0 ),
-  INST(Pfpnacc         , Ext3dNow           , O(000F0F,8E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2011, 190, 89 , 0 ),
-  INST(Pfrcp           , Ext3dNow           , O(000F0F,96,_,_,_,_,_,_  ), 0                         , 0 , 8 , 2019, 199, 84 , 0 ),
-  INST(Pfrcpit1        , Ext3dNow           , O(000F0F,A6,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2025, 190, 84 , 0 ),
-  INST(Pfrcpit2        , Ext3dNow           , O(000F0F,B6,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2034, 190, 84 , 0 ),
-  INST(Pfrcpv          , Ext3dNow           , O(000F0F,86,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2043, 190, 90 , 0 ),
-  INST(Pfrsqit1        , Ext3dNow           , O(000F0F,A7,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2050, 200, 84 , 0 ),
-  INST(Pfrsqrt         , Ext3dNow           , O(000F0F,97,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2059, 200, 84 , 0 ),
-  INST(Pfrsqrtv        , Ext3dNow           , O(000F0F,87,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2067, 190, 90 , 0 ),
-  INST(Pfsub           , Ext3dNow           , O(000F0F,9A,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2076, 190, 84 , 0 ),
-  INST(Pfsubr          , Ext3dNow           , O(000F0F,AA,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2082, 190, 84 , 0 ),
-  INST(Phaddd          , ExtRm_P            , O(000F38,02,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6950, 186, 82 , 51),
-  INST(Phaddsw         , ExtRm_P            , O(000F38,03,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6967, 186, 82 , 52),
-  INST(Phaddw          , ExtRm_P            , O(000F38,01,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7036, 186, 82 , 53),
+  INST(Pextrq          , ExtExtract         , O(000F3A,16,_,_,1,_,_,_  ), 0                         , 0 , 8 , 6863, 198, 12 , 50),
+  INST(Pextrw          , ExtPextrw          , O(000F00,C5,_,_,_,_,_,_  ), O(000F3A,15,_,_,_,_,_,_  ), 0 , 8 , 6871, 199, 88 , 50),
+  INST(Pf2id           , Ext3dNow           , O(000F0F,1D,_,_,_,_,_,_  ), 0                         , 0 , 8 , 1938, 200, 84 , 0 ),
+  INST(Pf2iw           , Ext3dNow           , O(000F0F,1C,_,_,_,_,_,_  ), 0                         , 0 , 8 , 1944, 200, 89 , 0 ),
+  INST(Pfacc           , Ext3dNow           , O(000F0F,AE,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1950, 191, 84 , 0 ),
+  INST(Pfadd           , Ext3dNow           , O(000F0F,9E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1956, 191, 84 , 0 ),
+  INST(Pfcmpeq         , Ext3dNow           , O(000F0F,B0,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1962, 191, 84 , 0 ),
+  INST(Pfcmpge         , Ext3dNow           , O(000F0F,90,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1970, 191, 84 , 0 ),
+  INST(Pfcmpgt         , Ext3dNow           , O(000F0F,A0,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1978, 191, 84 , 0 ),
+  INST(Pfmax           , Ext3dNow           , O(000F0F,A4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1986, 191, 84 , 0 ),
+  INST(Pfmin           , Ext3dNow           , O(000F0F,94,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1992, 191, 84 , 0 ),
+  INST(Pfmul           , Ext3dNow           , O(000F0F,B4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 1998, 191, 84 , 0 ),
+  INST(Pfnacc          , Ext3dNow           , O(000F0F,8A,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2004, 191, 89 , 0 ),
+  INST(Pfpnacc         , Ext3dNow           , O(000F0F,8E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2011, 191, 89 , 0 ),
+  INST(Pfrcp           , Ext3dNow           , O(000F0F,96,_,_,_,_,_,_  ), 0                         , 0 , 8 , 2019, 200, 84 , 0 ),
+  INST(Pfrcpit1        , Ext3dNow           , O(000F0F,A6,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2025, 191, 84 , 0 ),
+  INST(Pfrcpit2        , Ext3dNow           , O(000F0F,B6,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2034, 191, 84 , 0 ),
+  INST(Pfrcpv          , Ext3dNow           , O(000F0F,86,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2043, 191, 90 , 0 ),
+  INST(Pfrsqit1        , Ext3dNow           , O(000F0F,A7,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2050, 201, 84 , 0 ),
+  INST(Pfrsqrt         , Ext3dNow           , O(000F0F,97,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2059, 201, 84 , 0 ),
+  INST(Pfrsqrtv        , Ext3dNow           , O(000F0F,87,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2067, 191, 90 , 0 ),
+  INST(Pfsub           , Ext3dNow           , O(000F0F,9A,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2076, 191, 84 , 0 ),
+  INST(Pfsubr          , Ext3dNow           , O(000F0F,AA,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2082, 191, 84 , 0 ),
+  INST(Phaddd          , ExtRm_P            , O(000F38,02,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6950, 187, 82 , 51),
+  INST(Phaddsw         , ExtRm_P            , O(000F38,03,_,_,_,_,_,_  ), 0                         , 0 , 0 , 6967, 187, 82 , 52),
+  INST(Phaddw          , ExtRm_P            , O(000F38,01,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7036, 187, 82 , 53),
   INST(Phminposuw      , ExtRm              , O(660F38,41,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7062, 5  , 12 , 54),
-  INST(Phsubd          , ExtRm_P            , O(000F38,06,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7083, 186, 82 , 55),
-  INST(Phsubsw         , ExtRm_P            , O(000F38,07,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7100, 186, 82 , 56),
-  INST(Phsubw          , ExtRm_P            , O(000F38,05,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7109, 186, 82 , 56),
-  INST(Pi2fd           , Ext3dNow           , O(000F0F,0D,_,_,_,_,_,_  ), 0                         , 0 , 8 , 2089, 199, 84 , 0 ),
-  INST(Pi2fw           , Ext3dNow           , O(000F0F,0C,_,_,_,_,_,_  ), 0                         , 0 , 8 , 2095, 199, 89 , 0 ),
-  INST(Pinsrb          , ExtRmi             , O(660F3A,20,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7126, 201, 12 , 57),
-  INST(Pinsrd          , ExtRmi             , O(660F3A,22,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7134, 202, 12 , 57),
-  INST(Pinsrq          , ExtRmi             , O(660F3A,22,_,_,1,_,_,_  ), 0                         , 0 , 0 , 7142, 203, 12 , 57),
-  INST(Pinsrw          , ExtRmi_P           , O(000F00,C4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7150, 204, 83 , 55),
-  INST(Pmaddubsw       , ExtRm_P            , O(000F38,04,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7320, 186, 82 , 58),
-  INST(Pmaddwd         , ExtRm_P            , O(000F00,F5,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7331, 186, 78 , 58),
+  INST(Phsubd          , ExtRm_P            , O(000F38,06,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7083, 187, 82 , 55),
+  INST(Phsubsw         , ExtRm_P            , O(000F38,07,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7100, 187, 82 , 56),
+  INST(Phsubw          , ExtRm_P            , O(000F38,05,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7109, 187, 82 , 56),
+  INST(Pi2fd           , Ext3dNow           , O(000F0F,0D,_,_,_,_,_,_  ), 0                         , 0 , 8 , 2089, 200, 84 , 0 ),
+  INST(Pi2fw           , Ext3dNow           , O(000F0F,0C,_,_,_,_,_,_  ), 0                         , 0 , 8 , 2095, 200, 89 , 0 ),
+  INST(Pinsrb          , ExtRmi             , O(660F3A,20,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7126, 202, 12 , 57),
+  INST(Pinsrd          , ExtRmi             , O(660F3A,22,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7134, 203, 12 , 57),
+  INST(Pinsrq          , ExtRmi             , O(660F3A,22,_,_,1,_,_,_  ), 0                         , 0 , 0 , 7142, 204, 12 , 57),
+  INST(Pinsrw          , ExtRmi_P           , O(000F00,C4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7150, 205, 83 , 55),
+  INST(Pmaddubsw       , ExtRm_P            , O(000F38,04,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7320, 187, 82 , 58),
+  INST(Pmaddwd         , ExtRm_P            , O(000F00,F5,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7331, 187, 78 , 58),
   INST(Pmaxsb          , ExtRm              , O(660F38,3C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7362, 12 , 12 , 59),
   INST(Pmaxsd          , ExtRm              , O(660F38,3D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7370, 12 , 12 , 59),
-  INST(Pmaxsw          , ExtRm_P            , O(000F00,EE,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7386, 188, 83 , 60),
-  INST(Pmaxub          , ExtRm_P            , O(000F00,DE,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7394, 188, 83 , 60),
+  INST(Pmaxsw          , ExtRm_P            , O(000F00,EE,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7386, 189, 83 , 60),
+  INST(Pmaxub          , ExtRm_P            , O(000F00,DE,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7394, 189, 83 , 60),
   INST(Pmaxud          , ExtRm              , O(660F38,3F,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7402, 12 , 12 , 60),
   INST(Pmaxuw          , ExtRm              , O(660F38,3E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7418, 12 , 12 , 61),
   INST(Pminsb          , ExtRm              , O(660F38,38,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7426, 12 , 12 , 61),
   INST(Pminsd          , ExtRm              , O(660F38,39,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7434, 12 , 12 , 61),
-  INST(Pminsw          , ExtRm_P            , O(000F00,EA,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7450, 188, 83 , 62),
-  INST(Pminub          , ExtRm_P            , O(000F00,DA,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7458, 188, 83 , 62),
+  INST(Pminsw          , ExtRm_P            , O(000F00,EA,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7450, 189, 83 , 62),
+  INST(Pminub          , ExtRm_P            , O(000F00,DA,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7458, 189, 83 , 62),
   INST(Pminud          , ExtRm              , O(660F38,3B,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7466, 12 , 12 , 62),
   INST(Pminuw          , ExtRm              , O(660F38,3A,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7482, 12 , 12 , 63),
-  INST(Pmovmskb        , ExtRm_P            , O(000F00,D7,_,_,_,_,_,_  ), 0                         , 0 , 8 , 7560, 205, 83 , 64),
-  INST(Pmovsxbd        , ExtRm              , O(660F38,21,_,_,_,_,_,_  ), 0                         , 0 , 16, 7657, 206, 12 , 14),
-  INST(Pmovsxbq        , ExtRm              , O(660F38,22,_,_,_,_,_,_  ), 0                         , 0 , 16, 7667, 207, 12 , 14),
+  INST(Pmovmskb        , ExtRm_P            , O(000F00,D7,_,_,_,_,_,_  ), 0                         , 0 , 8 , 7560, 206, 83 , 64),
+  INST(Pmovsxbd        , ExtRm              , O(660F38,21,_,_,_,_,_,_  ), 0                         , 0 , 16, 7657, 207, 12 , 14),
+  INST(Pmovsxbq        , ExtRm              , O(660F38,22,_,_,_,_,_,_  ), 0                         , 0 , 16, 7667, 208, 12 , 14),
   INST(Pmovsxbw        , ExtRm              , O(660F38,20,_,_,_,_,_,_  ), 0                         , 0 , 16, 7677, 49 , 12 , 14),
   INST(Pmovsxdq        , ExtRm              , O(660F38,25,_,_,_,_,_,_  ), 0                         , 0 , 16, 7687, 49 , 12 , 14),
   INST(Pmovsxwd        , ExtRm              , O(660F38,23,_,_,_,_,_,_  ), 0                         , 0 , 16, 7697, 49 , 12 , 14),
-  INST(Pmovsxwq        , ExtRm              , O(660F38,24,_,_,_,_,_,_  ), 0                         , 0 , 16, 7707, 206, 12 , 14),
-  INST(Pmovzxbd        , ExtRm              , O(660F38,31,_,_,_,_,_,_  ), 0                         , 0 , 16, 7794, 206, 12 , 65),
-  INST(Pmovzxbq        , ExtRm              , O(660F38,32,_,_,_,_,_,_  ), 0                         , 0 , 16, 7804, 207, 12 , 65),
+  INST(Pmovsxwq        , ExtRm              , O(660F38,24,_,_,_,_,_,_  ), 0                         , 0 , 16, 7707, 207, 12 , 14),
+  INST(Pmovzxbd        , ExtRm              , O(660F38,31,_,_,_,_,_,_  ), 0                         , 0 , 16, 7794, 207, 12 , 65),
+  INST(Pmovzxbq        , ExtRm              , O(660F38,32,_,_,_,_,_,_  ), 0                         , 0 , 16, 7804, 208, 12 , 65),
   INST(Pmovzxbw        , ExtRm              , O(660F38,30,_,_,_,_,_,_  ), 0                         , 0 , 16, 7814, 49 , 12 , 65),
   INST(Pmovzxdq        , ExtRm              , O(660F38,35,_,_,_,_,_,_  ), 0                         , 0 , 16, 7824, 49 , 12 , 65),
   INST(Pmovzxwd        , ExtRm              , O(660F38,33,_,_,_,_,_,_  ), 0                         , 0 , 16, 7834, 49 , 12 , 65),
-  INST(Pmovzxwq        , ExtRm              , O(660F38,34,_,_,_,_,_,_  ), 0                         , 0 , 16, 7844, 206, 12 , 65),
+  INST(Pmovzxwq        , ExtRm              , O(660F38,34,_,_,_,_,_,_  ), 0                         , 0 , 16, 7844, 207, 12 , 65),
   INST(Pmuldq          , ExtRm              , O(660F38,28,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7854, 5  , 12 , 19),
-  INST(Pmulhrsw        , ExtRm_P            , O(000F38,0B,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7862, 186, 82 , 19),
-  INST(Pmulhrw         , Ext3dNow           , O(000F0F,B7,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2101, 190, 84 , 0 ),
-  INST(Pmulhuw         , ExtRm_P            , O(000F00,E4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7872, 186, 83 , 66),
-  INST(Pmulhw          , ExtRm_P            , O(000F00,E5,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7881, 186, 78 , 66),
+  INST(Pmulhrsw        , ExtRm_P            , O(000F38,0B,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7862, 187, 82 , 19),
+  INST(Pmulhrw         , Ext3dNow           , O(000F0F,B7,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2101, 191, 84 , 0 ),
+  INST(Pmulhuw         , ExtRm_P            , O(000F00,E4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7872, 187, 83 , 66),
+  INST(Pmulhw          , ExtRm_P            , O(000F00,E5,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7881, 187, 78 , 66),
   INST(Pmulld          , ExtRm              , O(660F38,40,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7889, 5  , 12 , 66),
-  INST(Pmullw          , ExtRm_P            , O(000F00,D5,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7905, 186, 78 , 19),
-  INST(Pmuludq         , ExtRm_P            , O(000F00,F4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7928, 186, 4  , 67),
-  INST(Pop             , X86Pop             , O(000000,8F,0,_,_,_,_,_  ), O(000000,58,_,_,_,_,_,_  ), 0 , 0 , 2109, 208, 45 , 0 ),
-  INST(Popa            , X86Op              , O(660000,61,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2113, 209, 45 , 0 ),
-  INST(Popad           , X86Op              , O(000000,61,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2118, 209, 45 , 0 ),
-  INST(Popcnt          , X86Rm_Raw66H       , O(F30F00,B8,_,_,x,_,_,_  ), 0                         , 0 , 0 , 2124, 142, 91 , 0 ),
+  INST(Pmullw          , ExtRm_P            , O(000F00,D5,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7905, 187, 78 , 19),
+  INST(Pmuludq         , ExtRm_P            , O(000F00,F4,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7928, 187, 4  , 67),
+  INST(Pop             , X86Pop             , O(000000,8F,0,_,_,_,_,_  ), O(000000,58,_,_,_,_,_,_  ), 0 , 0 , 2109, 209, 45 , 0 ),
+  INST(Popa            , X86Op              , O(660000,61,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2113, 99 , 45 , 0 ),
+  INST(Popad           , X86Op              , O(000000,61,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2118, 99 , 45 , 0 ),
+  INST(Popcnt          , X86Rm_Raw66H       , O(F30F00,B8,_,_,x,_,_,_  ), 0                         , 0 , 0 , 2124, 143, 91 , 0 ),
   INST(Popf            , X86Op              , O(660000,9D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2131, 34 , 16 , 0 ),
-  INST(Popfd           , X86Op              , O(000000,9D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2136, 209, 16 , 0 ),
-  INST(Popfq           , X86Op              , O(000000,9D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2142, 100, 16 , 0 ),
-  INST(Por             , ExtRm_P            , O(000F00,EB,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7955, 188, 78 , 68),
+  INST(Popfd           , X86Op              , O(000000,9D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2136, 99 , 16 , 0 ),
+  INST(Popfq           , X86Op              , O(000000,9D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2142, 101, 16 , 0 ),
+  INST(Por             , ExtRm_P            , O(000F00,EB,_,_,_,_,_,_  ), 0                         , 0 , 0 , 7955, 189, 78 , 68),
   INST(Prefetch        , X86M_Only          , O(000F00,0D,0,_,_,_,_,_  ), 0                         , 0 , 0 , 2148, 35 , 92 , 0 ),
   INST(Prefetchnta     , X86M_Only          , O(000F00,18,0,_,_,_,_,_  ), 0                         , 0 , 0 , 2157, 35 , 93 , 0 ),
   INST(Prefetcht0      , X86M_Only          , O(000F00,18,1,_,_,_,_,_  ), 0                         , 0 , 0 , 2169, 35 , 93 , 0 ),
@@ -746,15 +745,15 @@ const X86Inst X86InstDB::instData[] = {
   INST(Prefetcht2      , X86M_Only          , O(000F00,18,3,_,_,_,_,_  ), 0                         , 0 , 0 , 2191, 35 , 93 , 0 ),
   INST(Prefetchw       , X86M_Only          , O(000F00,0D,1,_,_,_,_,_  ), 0                         , 0 , 0 , 2202, 35 , 94 , 0 ),
   INST(Prefetchwt1     , X86M_Only          , O(000F00,0D,2,_,_,_,_,_  ), 0                         , 0 , 0 , 2212, 35 , 95 , 0 ),
-  INST(Psadbw          , ExtRm_P            , O(000F00,F6,_,_,_,_,_,_  ), 0                         , 0 , 0 , 3795, 186, 83 , 69),
-  INST(Pshufb          , ExtRm_P            , O(000F38,00,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8179, 186, 82 , 70),
+  INST(Psadbw          , ExtRm_P            , O(000F00,F6,_,_,_,_,_,_  ), 0                         , 0 , 0 , 3795, 187, 83 , 69),
+  INST(Pshufb          , ExtRm_P            , O(000F38,00,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8179, 187, 82 , 70),
   INST(Pshufd          , ExtRmi             , O(660F00,70,_,_,_,_,_,_  ), 0                         , 0 , 16, 8187, 210, 4  , 71),
   INST(Pshufhw         , ExtRmi             , O(F30F00,70,_,_,_,_,_,_  ), 0                         , 0 , 16, 8195, 210, 4  , 71),
   INST(Pshuflw         , ExtRmi             , O(F20F00,70,_,_,_,_,_,_  ), 0                         , 0 , 16, 8204, 210, 4  , 71),
   INST(Pshufw          , ExtRmi_P           , O(000F00,70,_,_,_,_,_,_  ), 0                         , 0 , 8 , 2224, 211, 74 , 0 ),
-  INST(Psignb          , ExtRm_P            , O(000F38,08,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8213, 186, 82 , 72),
-  INST(Psignd          , ExtRm_P            , O(000F38,0A,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8221, 186, 82 , 72),
-  INST(Psignw          , ExtRm_P            , O(000F38,09,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8229, 186, 82 , 72),
+  INST(Psignb          , ExtRm_P            , O(000F38,08,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8213, 187, 82 , 72),
+  INST(Psignd          , ExtRm_P            , O(000F38,0A,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8221, 187, 82 , 72),
+  INST(Psignw          , ExtRm_P            , O(000F38,09,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8229, 187, 82 , 72),
   INST(Pslld           , ExtRmRi_P          , O(000F00,F2,_,_,_,_,_,_  ), O(000F00,72,6,_,_,_,_,_  ), 0 , 0 , 8237, 212, 78 , 72),
   INST(Pslldq          , ExtRmRi            , 0                         , O(660F00,73,7,_,_,_,_,_  ), 0 , 0 , 8244, 213, 4  , 72),
   INST(Psllq           , ExtRmRi_P          , O(000F00,F3,_,_,_,_,_,_  ), O(000F00,73,6,_,_,_,_,_  ), 0 , 0 , 8252, 214, 78 , 72),
@@ -765,31 +764,31 @@ const X86Inst X86InstDB::instData[] = {
   INST(Psrldq          , ExtRmRi            , 0                         , O(660F00,73,3,_,_,_,_,_  ), 0 , 0 , 8342, 219, 4  , 74),
   INST(Psrlq           , ExtRmRi_P          , O(000F00,D3,_,_,_,_,_,_  ), O(000F00,73,2,_,_,_,_,_  ), 0 , 0 , 8350, 220, 78 , 74),
   INST(Psrlw           , ExtRmRi_P          , O(000F00,D1,_,_,_,_,_,_  ), O(000F00,71,2,_,_,_,_,_  ), 0 , 0 , 8381, 221, 78 , 75),
-  INST(Psubb           , ExtRm_P            , O(000F00,F8,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8388, 189, 78 , 75),
-  INST(Psubd           , ExtRm_P            , O(000F00,FA,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8395, 189, 78 , 75),
-  INST(Psubq           , ExtRm_P            , O(000F00,FB,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8402, 189, 4  , 75),
-  INST(Psubsb          , ExtRm_P            , O(000F00,E8,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8409, 189, 78 , 75),
-  INST(Psubsw          , ExtRm_P            , O(000F00,E9,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8417, 189, 78 , 75),
-  INST(Psubusb         , ExtRm_P            , O(000F00,D8,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8425, 189, 78 , 75),
-  INST(Psubusw         , ExtRm_P            , O(000F00,D9,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8434, 189, 78 , 75),
-  INST(Psubw           , ExtRm_P            , O(000F00,F9,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8443, 189, 78 , 75),
-  INST(Pswapd          , Ext3dNow           , O(000F0F,BB,_,_,_,_,_,_  ), 0                         , 0 , 8 , 2231, 199, 89 , 0 ),
+  INST(Psubb           , ExtRm_P            , O(000F00,F8,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8388, 190, 78 , 75),
+  INST(Psubd           , ExtRm_P            , O(000F00,FA,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8395, 190, 78 , 75),
+  INST(Psubq           , ExtRm_P            , O(000F00,FB,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8402, 190, 4  , 75),
+  INST(Psubsb          , ExtRm_P            , O(000F00,E8,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8409, 190, 78 , 75),
+  INST(Psubsw          , ExtRm_P            , O(000F00,E9,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8417, 190, 78 , 75),
+  INST(Psubusb         , ExtRm_P            , O(000F00,D8,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8425, 190, 78 , 75),
+  INST(Psubusw         , ExtRm_P            , O(000F00,D9,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8434, 190, 78 , 75),
+  INST(Psubw           , ExtRm_P            , O(000F00,F9,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8443, 190, 78 , 75),
+  INST(Pswapd          , Ext3dNow           , O(000F0F,BB,_,_,_,_,_,_  ), 0                         , 0 , 8 , 2231, 200, 89 , 0 ),
   INST(Ptest           , ExtRm              , O(660F38,17,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8472, 222, 96 , 76),
-  INST(Punpckhbw       , ExtRm_P            , O(000F00,68,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8555, 186, 78 , 77),
-  INST(Punpckhdq       , ExtRm_P            , O(000F00,6A,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8566, 186, 78 , 77),
+  INST(Punpckhbw       , ExtRm_P            , O(000F00,68,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8555, 187, 78 , 77),
+  INST(Punpckhdq       , ExtRm_P            , O(000F00,6A,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8566, 187, 78 , 77),
   INST(Punpckhqdq      , ExtRm              , O(660F00,6D,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8577, 5  , 4  , 77),
-  INST(Punpckhwd       , ExtRm_P            , O(000F00,69,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8589, 186, 78 , 77),
-  INST(Punpcklbw       , ExtRm_P            , O(000F00,60,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8600, 186, 78 , 77),
-  INST(Punpckldq       , ExtRm_P            , O(000F00,62,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8611, 186, 78 , 77),
+  INST(Punpckhwd       , ExtRm_P            , O(000F00,69,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8589, 187, 78 , 77),
+  INST(Punpcklbw       , ExtRm_P            , O(000F00,60,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8600, 187, 78 , 77),
+  INST(Punpckldq       , ExtRm_P            , O(000F00,62,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8611, 187, 78 , 77),
   INST(Punpcklqdq      , ExtRm              , O(660F00,6C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8622, 5  , 4  , 77),
-  INST(Punpcklwd       , ExtRm_P            , O(000F00,61,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8634, 186, 78 , 77),
+  INST(Punpcklwd       , ExtRm_P            , O(000F00,61,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8634, 187, 78 , 77),
   INST(Push            , X86Push            , O(000000,FF,6,_,_,_,_,_  ), O(000000,50,_,_,_,_,_,_  ), 0 , 0 , 2238, 223, 45 , 0 ),
-  INST(Pusha           , X86Op              , O(660000,60,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2243, 209, 45 , 0 ),
-  INST(Pushad          , X86Op              , O(000000,60,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2249, 209, 45 , 0 ),
+  INST(Pusha           , X86Op              , O(660000,60,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2243, 99 , 45 , 0 ),
+  INST(Pushad          , X86Op              , O(000000,60,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2249, 99 , 45 , 0 ),
   INST(Pushf           , X86Op              , O(660000,9C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2256, 34 , 45 , 0 ),
-  INST(Pushfd          , X86Op              , O(000000,9C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2262, 209, 45 , 0 ),
-  INST(Pushfq          , X86Op              , O(000000,9C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2269, 100, 45 , 0 ),
-  INST(Pxor            , ExtRm_P            , O(000F00,EF,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8645, 189, 78 , 78),
+  INST(Pushfd          , X86Op              , O(000000,9C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2262, 99 , 45 , 0 ),
+  INST(Pushfq          , X86Op              , O(000000,9C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2269, 101, 45 , 0 ),
+  INST(Pxor            , ExtRm_P            , O(000F00,EF,_,_,_,_,_,_  ), 0                         , 0 , 0 , 8645, 190, 78 , 78),
   INST(Rcl             , X86Rot             , O(000000,D0,2,_,x,_,_,_  ), 0                         , 0 , 0 , 2276, 224, 97 , 0 ),
   INST(Rcpps           , ExtRm              , O(000F00,53,_,_,_,_,_,_  ), 0                         , 0 , 16, 8773, 50 , 5  , 79),
   INST(Rcpss           , ExtRm              , O(F30F00,53,_,_,_,_,_,_  ), 0                         , 0 , 4 , 8780, 225, 5  , 80),
@@ -810,7 +809,7 @@ const X86Inst X86InstDB::instData[] = {
   INST(Roundps         , ExtRmi             , O(660F3A,08,_,_,_,_,_,_  ), 0                         , 0 , 16, 8884, 210, 12 , 81),
   INST(Roundsd         , ExtRmi             , O(660F3A,0B,_,_,_,_,_,_  ), 0                         , 0 , 8 , 8893, 233, 12 , 82),
   INST(Roundss         , ExtRmi             , O(660F3A,0A,_,_,_,_,_,_  ), 0                         , 0 , 4 , 8902, 234, 12 , 82),
-  INST(Rsm             , X86Op              , O(000F00,AA,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2354, 209, 16 , 0 ),
+  INST(Rsm             , X86Op              , O(000F00,AA,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2354, 99 , 16 , 0 ),
   INST(Rsqrtps         , ExtRm              , O(000F00,52,_,_,_,_,_,_  ), 0                         , 0 , 16, 8999, 50 , 5  , 3 ),
   INST(Rsqrtss         , ExtRm              , O(F30F00,52,_,_,_,_,_,_  ), 0                         , 0 , 4 , 9008, 225, 5  , 2 ),
   INST(Sahf            , X86Op              , O(000000,9E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2358, 235, 104, 0 ),
@@ -885,16 +884,16 @@ const X86Inst X86InstDB::instData[] = {
   INST(Subps           , ExtRm              , O(000F00,5C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 4373, 5  , 5  , 86),
   INST(Subsd           , ExtRm              , O(F20F00,5C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5049, 6  , 4  , 86),
   INST(Subss           , ExtRm              , O(F30F00,5C,_,_,_,_,_,_  ), 0                         , 0 , 0 , 5059, 7  , 5  , 86),
-  INST(Swapgs          , X86Op              , O(000F01,F8,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2703, 100, 23 , 0 ),
-  INST(Syscall         , X86Op              , O(000F00,05,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2710, 100, 45 , 0 ),
+  INST(Swapgs          , X86Op              , O(000F01,F8,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2703, 101, 23 , 0 ),
+  INST(Syscall         , X86Op              , O(000F00,05,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2710, 101, 45 , 0 ),
   INST(Sysenter        , X86Op              , O(000F00,34,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2718, 34 , 45 , 0 ),
   INST(Sysexit         , X86Op              , O(000F00,35,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2727, 34 , 23 , 0 ),
   INST(Sysexit64       , X86Op              , O(000F00,35,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2735, 34 , 23 , 0 ),
-  INST(Sysret          , X86Op              , O(000F00,07,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2745, 100, 23 , 0 ),
-  INST(Sysret64        , X86Op              , O(000F00,07,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2752, 100, 23 , 0 ),
+  INST(Sysret          , X86Op              , O(000F00,07,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2745, 101, 23 , 0 ),
+  INST(Sysret64        , X86Op              , O(000F00,07,_,_,_,_,_,_  ), 0                         , 0 , 0 , 2752, 101, 23 , 0 ),
   INST(T1mskc          , VexVm_Wx           , V(XOP_M9,01,7,0,x,_,_,_  ), 0                         , 0 , 0 , 2761, 15 , 11 , 0 ),
   INST(Test            , X86Test            , O(000000,84,_,_,x,_,_,_  ), O(000000,F6,_,_,x,_,_,_  ), 0 , 0 , 8473, 244, 1  , 0 ),
-  INST(Tzcnt           , X86Rm_Raw66H       , O(F30F00,BC,_,_,x,_,_,_  ), 0                         , 0 , 0 , 2768, 142, 9  , 0 ),
+  INST(Tzcnt           , X86Rm_Raw66H       , O(F30F00,BC,_,_,x,_,_,_  ), 0                         , 0 , 0 , 2768, 143, 9  , 0 ),
   INST(Tzmsk           , VexVm_Wx           , V(XOP_M9,01,4,0,x,_,_,_  ), 0                         , 0 , 0 , 2774, 15 , 11 , 0 ),
   INST(Ucomisd         , ExtRm              , O(660F00,2E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9370, 44 , 39 , 15),
   INST(Ucomiss         , ExtRm              , O(000F00,2E,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9379, 45 , 40 , 15),
@@ -1004,8 +1003,8 @@ const X86Inst X86InstDB::instData[] = {
   INST(Vdivss          , VexRvm             , V(F30F00,5E,_,I,I,0,2,T1S), 0                         , 0 , 0 , 3823, 249, 117, 19),
   INST(Vdppd           , VexRvmi_Lx         , V(660F3A,41,_,x,I,_,_,_  ), 0                         , 0 , 0 , 3830, 310, 118, 19),
   INST(Vdpps           , VexRvmi_Lx         , V(660F3A,40,_,x,I,_,_,_  ), 0                         , 0 , 0 , 3836, 263, 118, 19),
-  INST(Verr            , X86M               , O(000F00,00,4,_,_,_,_,_  ), 0                         , 0 , 0 , 3842, 136, 70 , 0 ),
-  INST(Verw            , X86M               , O(000F00,00,5,_,_,_,_,_  ), 0                         , 0 , 0 , 3847, 136, 70 , 0 ),
+  INST(Verr            , X86M               , O(000F00,00,4,_,_,_,_,_  ), 0                         , 0 , 0 , 3842, 137, 70 , 0 ),
+  INST(Verw            , X86M               , O(000F00,00,5,_,_,_,_,_  ), 0                         , 0 , 0 , 3847, 137, 70 , 0 ),
   INST(Vexp2pd         , VexRm              , V(660F38,C8,_,2,_,1,4,FV ), 0                         , 0 , 0 , 3852, 311, 128, 0 ),
   INST(Vexp2ps         , VexRm              , V(660F38,C8,_,2,_,0,4,FV ), 0                         , 0 , 0 , 3860, 312, 128, 0 ),
   INST(Vexpandpd       , VexRm_Lx           , V(660F38,88,_,x,_,1,3,T1S), 0                         , 0 , 0 , 3868, 313, 120, 0 ),
@@ -1193,8 +1192,8 @@ const X86Inst X86InstDB::instData[] = {
   INST(Vmovupd         , VexRmMr_Lx         , V(660F00,10,_,x,I,1,4,FVM), V(660F00,11,_,x,I,1,4,FVM), 0 , 0 , 5910, 385, 116, 36),
   INST(Vmovups         , VexRmMr_Lx         , V(000F00,10,_,x,I,0,4,FVM), V(000F00,11,_,x,I,0,4,FVM), 0 , 0 , 5918, 386, 116, 36),
   INST(Vmpsadbw        , VexRvmi_Lx         , V(660F3A,42,_,x,I,_,_,_  ), 0                         , 0 , 0 , 5926, 263, 135, 37),
-  INST(Vmulpd          , VexRvm_Lx          , V(660F00,59,_,x,I,1,4,FV ), 0                         , 0 , 0 , 5935, 246, 125, 38),
-  INST(Vmulps          , VexRvm_Lx          , V(000F00,59,_,x,I,0,4,FV ), 0                         , 0 , 0 , 5942, 247, 125, 38),
+  INST(Vmulpd          , VexRvm_Lx          , V(660F00,59,_,x,I,1,4,FV ), 0                         , 0 , 0 , 5935, 246, 116, 38),
+  INST(Vmulps          , VexRvm_Lx          , V(000F00,59,_,x,I,0,4,FV ), 0                         , 0 , 0 , 5942, 247, 116, 38),
   INST(Vmulsd          , VexRvm_Lx          , V(F20F00,59,_,I,I,1,3,T1S), 0                         , 0 , 0 , 5949, 248, 117, 38),
   INST(Vmulss          , VexRvm_Lx          , V(F30F00,59,_,I,I,0,2,T1S), 0                         , 0 , 0 , 5956, 249, 117, 38),
   INST(Vorpd           , VexRvm_Lx          , V(660F00,56,_,x,I,1,4,FV ), 0                         , 0 , 0 , 5963, 258, 121, 39),
@@ -1564,8 +1563,8 @@ const X86Inst X86InstDB::instData[] = {
   INST(Vsqrtsd         , VexRvm             , V(F20F00,51,_,I,I,1,3,T1S), 0                         , 0 , 0 , 9300, 248, 117, 85),
   INST(Vsqrtss         , VexRvm             , V(F30F00,51,_,I,I,0,2,T1S), 0                         , 0 , 0 , 9308, 249, 117, 85),
   INST(Vstmxcsr        , VexM               , V(000F00,AE,3,0,I,_,_,_  ), 0                         , 0 , 0 , 9316, 506, 118, 0 ),
-  INST(Vsubpd          , VexRvm_Lx          , V(660F00,5C,_,x,I,1,4,FV ), 0                         , 0 , 0 , 9325, 246, 125, 86),
-  INST(Vsubps          , VexRvm_Lx          , V(000F00,5C,_,x,I,0,4,FV ), 0                         , 0 , 0 , 9332, 247, 125, 86),
+  INST(Vsubpd          , VexRvm_Lx          , V(660F00,5C,_,x,I,1,4,FV ), 0                         , 0 , 0 , 9325, 246, 116, 86),
+  INST(Vsubps          , VexRvm_Lx          , V(000F00,5C,_,x,I,0,4,FV ), 0                         , 0 , 0 , 9332, 247, 116, 86),
   INST(Vsubsd          , VexRvm             , V(F20F00,5C,_,I,I,1,3,T1S), 0                         , 0 , 0 , 9339, 248, 117, 86),
   INST(Vsubss          , VexRvm             , V(F30F00,5C,_,I,I,0,2,T1S), 0                         , 0 , 0 , 9346, 249, 117, 86),
   INST(Vtestpd         , VexRm_Lx           , V(660F38,0F,_,x,0,_,_,_  ), 0                         , 0 , 0 , 9353, 478, 142, 0 ),
@@ -1592,22 +1591,22 @@ const X86Inst X86InstDB::instData[] = {
   INST(Xgetbv          , X86Op              , O(000F01,D0,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9516, 227, 150, 0 ),
   INST(Xlatb           , X86Op              , O(000000,D7,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9523, 34 , 45 , 0 ),
   INST(Xor             , X86Arith           , O(000000,30,6,_,x,_,_,_  ), 0                         , 0 , 0 , 8646, 243, 1  , 0 ),
-  INST(Xorpd           , ExtRm              , O(660F00,57,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9428, 191, 4  , 87),
-  INST(Xorps           , ExtRm              , O(000F00,57,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9435, 191, 5  , 87),
+  INST(Xorpd           , ExtRm              , O(660F00,57,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9428, 192, 4  , 87),
+  INST(Xorps           , ExtRm              , O(000F00,57,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9435, 192, 5  , 87),
   INST(Xrstor          , X86M_Only          , O(000F00,AE,5,_,_,_,_,_  ), 0                         , 0 , 0 , 1105, 513, 150, 0 ),
   INST(Xrstor64        , X86M_Only          , O(000F00,AE,5,_,1,_,_,_  ), 0                         , 0 , 0 , 1113, 514, 150, 0 ),
-  INST(Xrstors         , X86M_Only          , O(000F00,C7,3,_,_,_,_,_  ), 0                         , 0 , 0 , 9529, 513, 150, 0 ),
-  INST(Xrstors64       , X86M_Only          , O(000F00,C7,3,_,1,_,_,_  ), 0                         , 0 , 0 , 9537, 514, 150, 0 ),
+  INST(Xrstors         , X86M_Only          , O(000F00,C7,3,_,_,_,_,_  ), 0                         , 0 , 0 , 9529, 513, 151, 0 ),
+  INST(Xrstors64       , X86M_Only          , O(000F00,C7,3,_,1,_,_,_  ), 0                         , 0 , 0 , 9537, 514, 151, 0 ),
   INST(Xsave           , X86M_Only          , O(000F00,AE,4,_,_,_,_,_  ), 0                         , 0 , 0 , 1123, 515, 150, 0 ),
   INST(Xsave64         , X86M_Only          , O(000F00,AE,4,_,1,_,_,_  ), 0                         , 0 , 0 , 1130, 516, 150, 0 ),
-  INST(Xsavec          , X86M_Only          , O(000F00,C7,4,_,_,_,_,_  ), 0                         , 0 , 0 , 9547, 515, 150, 0 ),
-  INST(Xsavec64        , X86M_Only          , O(000F00,C7,4,_,1,_,_,_  ), 0                         , 0 , 0 , 9554, 516, 150, 0 ),
-  INST(Xsaveopt        , X86M_Only          , O(000F00,AE,6,_,_,_,_,_  ), 0                         , 0 , 0 , 9563, 515, 151, 0 ),
-  INST(Xsaveopt64      , X86M_Only          , O(000F00,AE,6,_,1,_,_,_  ), 0                         , 0 , 0 , 9572, 516, 151, 0 ),
-  INST(Xsaves          , X86M_Only          , O(000F00,C7,5,_,_,_,_,_  ), 0                         , 0 , 0 , 9583, 515, 150, 0 ),
-  INST(Xsaves64        , X86M_Only          , O(000F00,C7,5,_,1,_,_,_  ), 0                         , 0 , 0 , 9590, 516, 150, 0 ),
-  INST(Xsetbv          , X86Op              , O(000F01,D1,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9599, 509, 152, 0 ),
-  INST(Xtest           , X86Op              , O(000F01,D6,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9606, 34 , 153, 0 )
+  INST(Xsavec          , X86M_Only          , O(000F00,C7,4,_,_,_,_,_  ), 0                         , 0 , 0 , 9547, 515, 152, 0 ),
+  INST(Xsavec64        , X86M_Only          , O(000F00,C7,4,_,1,_,_,_  ), 0                         , 0 , 0 , 9554, 516, 152, 0 ),
+  INST(Xsaveopt        , X86M_Only          , O(000F00,AE,6,_,_,_,_,_  ), 0                         , 0 , 0 , 9563, 515, 153, 0 ),
+  INST(Xsaveopt64      , X86M_Only          , O(000F00,AE,6,_,1,_,_,_  ), 0                         , 0 , 0 , 9572, 516, 153, 0 ),
+  INST(Xsaves          , X86M_Only          , O(000F00,C7,5,_,_,_,_,_  ), 0                         , 0 , 0 , 9583, 515, 151, 0 ),
+  INST(Xsaves64        , X86M_Only          , O(000F00,C7,5,_,1,_,_,_  ), 0                         , 0 , 0 , 9590, 516, 151, 0 ),
+  INST(Xsetbv          , X86Op              , O(000F01,D1,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9599, 509, 154, 0 ),
+  INST(Xtest           , X86Op              , O(000F01,D6,_,_,_,_,_,_  ), 0                         , 0 , 0 , 9606, 34 , 155, 0 )
   // ${instData:End}
 };
 #undef NAME_DATA_INDEX
@@ -1754,7 +1753,7 @@ const uint32_t X86InstDB::altOpCodeData[] = {
 // ${commonData:Begin}
 // ------------------- Automatically generated, do not edit -------------------
 #define F(VAL) X86Inst::kFlag##VAL
-#define JUMP_TYPE(VAL) AnyInst::kJumpType##VAL
+#define JUMP_TYPE(VAL) Inst::kJumpType##VAL
 #define SINGLE_REG(VAL) X86Inst::kSingleReg##VAL
 const X86Inst::CommonData X86InstDB::commonData[] = {
   { F(UseR)                                               , 0  , 0  , 0  , 0  , 0 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #0
@@ -1856,117 +1855,117 @@ const X86Inst::CommonData X86InstDB::commonData[] = {
   { F(UseW)|F(FixedRM)|F(Rep)|F(Repnz)                    , 0  , 0  , 0  , 433, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #96
   { F(UseX)|F(Vec)                                        , 0  , 0  , 17 , 297, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #97
   { F(UseR)                                               , 0  , 0  , 0  , 434, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #98
-  { F(UseR)                                               , 0  , 0  , 0  , 299, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #99
-  { F(UseR)                                               , 0  , 0  , 0  , 435, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #100
-  { F(UseR)                                               , 0  , 0  , 18 , 436, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #101
-  { F(UseR)                                               , 0  , 0  , 19 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #102
-  { F(UseR)                                               , 0  , 0  , 20 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #103
-  { F(UseR)                                               , 0  , 0  , 21 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #104
-  { F(UseR)                                               , 0  , 0  , 20 , 437, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #105
-  { F(UseR)                                               , 0  , 0  , 22 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #106
-  { F(UseR)|F(FixedReg)                                   , 0  , 0  , 23 , 301, 2 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #107
-  { F(UseR)                                               , 0  , 0  , 24 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #108
-  { F(UseR)                                               , 0  , 0  , 25 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #109
-  { F(UseR)                                               , 0  , 0  , 26 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #110
-  { F(UseR)                                               , 0  , 0  , 27 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #111
-  { F(UseR)                                               , 0  , 0  , 28 , 303, 2 , JUMP_TYPE(Direct)     , SINGLE_REG(None), 0 }, // #112
-  { F(UseR)                                               , 0  , 0  , 19 , 437, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #113
-  { F(UseR)                                               , 0  , 0  , 29 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #114
-  { F(UseR)                                               , 0  , 0  , 30 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #115
-  { F(UseR)                                               , 0  , 0  , 31 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #116
-  { F(UseR)                                               , 0  , 0  , 32 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #117
-  { F(UseR)                                               , 0  , 0  , 33 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #118
-  { F(UseR)                                               , 0  , 0  , 34 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #119
-  { F(UseR)                                               , 0  , 0  , 35 , 436, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #120
-  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 438, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #121
-  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 36 , 305, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #122
-  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 37 , 307, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #123
-  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 38 , 309, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #124
-  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 39 , 311, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #125
-  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 439, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #126
-  { F(UseR)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 440, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #127
-  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 441, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #128
-  { F(UseW)|F(FixedReg)                                   , 0  , 0  , 0  , 442, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #129
-  { F(UseW)                                               , 0  , 0  , 0  , 313, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #130
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 0  , 228, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #131
-  { F(UseR)                                               , 0  , 0  , 0  , 443, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #132
-  { F(UseX)                                               , 0  , 0  , 0  , 315, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #133
-  { F(UseW)                                               , 0  , 0  , 0  , 444, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #134
-  { F(UseX)                                               , 0  , 0  , 0  , 180, 3 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #135
-  { F(UseR)                                               , 0  , 0  , 0  , 445, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #136
-  { F(UseW)|F(FixedRM)|F(Rep)|F(Repnz)                    , 0  , 0  , 0  , 446, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #137
-  { F(UseX)|F(FixedReg)                                   , 0  , 0  , 40 , 317, 2 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #138
-  { F(UseX)|F(FixedReg)                                   , 0  , 0  , 41 , 317, 2 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #139
-  { F(UseX)|F(FixedReg)                                   , 0  , 0  , 42 , 317, 2 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #140
-  { F(UseW)                                               , 0  , 0  , 0  , 319, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #141
-  { F(UseW)                                               , 0  , 0  , 0  , 183, 3 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #142
-  { F(UseX)|F(FixedRM)|F(Vec)                             , 0  , 0  , 0  , 447, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #143
-  { F(UseX)|F(FixedRM)|F(Mmx)                             , 0  , 0  , 0  , 448, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #144
-  { F(UseR)|F(FixedRM)                                    , 0  , 0  , 0  , 449, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #145
-  { F(UseW)|F(XRelease)                                   , 0  , 0  , 0  , 0  , 15, JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #146
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 43 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #147
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 44 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #148
-  { F(UseW)                                               , 0  , 0  , 45 , 75 , 6 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #149
-  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 16 , 46 , 321, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #150
-  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 8  , 0  , 450, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #151
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 47 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #152
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 48 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #153
-  { F(UseW)|F(Vec)                                        , 0  , 8  , 0  , 451, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #154
-  { F(UseW)|F(Vec)                                        , 8  , 8  , 49 , 234, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #155
-  { F(UseW)|F(Vec)                                        , 8  , 8  , 50 , 234, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #156
-  { F(UseW)|F(Vec)                                        , 8  , 8  , 0  , 451, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #157
-  { F(UseW)|F(Vec)                                        , 0  , 8  , 51 , 234, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #158
-  { F(UseW)|F(Vec)                                        , 0  , 8  , 52 , 234, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #159
-  { F(UseW)|F(Vec)                                        , 0  , 8  , 0  , 452, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #160
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 53 , 225, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #161
-  { F(UseW)                                               , 0  , 8  , 0  , 79 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #162
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 54 , 225, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #163
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 55 , 225, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #164
-  { F(UseW)|F(Mmx)                                        , 0  , 8  , 56 , 453, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #165
-  { F(UseW)|F(Vec)                                        , 0  , 8  , 57 , 234, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #166
-  { F(UseW)|F(Vec)                                        , 0  , 4  , 58 , 237, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #167
-  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 16 , 59 , 81 , 6 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #168
-  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 16 , 0  , 454, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #169
-  { F(UseX)|F(FixedRM)|F(Rep)|F(Repnz)                    , 0  , 0  , 0  , 455, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #170
-  { F(UseW)|F(Vec)                                        , 0  , 8  , 60 , 323, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #171
-  { F(UseW)|F(Vec)                                        , 0  , 4  , 61 , 325, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #172
-  { F(UseW)                                               , 0  , 0  , 0  , 327, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #173
-  { F(UseW)                                               , 0  , 0  , 0  , 456, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #174
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 62 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #175
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 63 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #176
-  { F(UseA)|F(FixedReg)                                   , 0  , 0  , 0  , 50 , 4 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #177
-  { F(UseW)|F(FixedReg)|F(Vex)                            , 0  , 0  , 0  , 329, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #178
-  { F(UseR)|F(FixedReg)                                   , 0  , 0  , 0  , 457, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #179
-  { F(UseX)|F(Lock)|F(XAcquire)|F(XRelease)               , 0  , 0  , 0  , 288, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #180
-  { F(UseR)                                               , 0  , 0  , 0  , 331, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #181
-  { F(UseX)|F(Lock)|F(XAcquire)|F(XRelease)               , 0  , 0  , 0  , 15 , 12, JUMP_TYPE(None)       , SINGLE_REG(RO)  , 0 }, // #182
-  { F(UseR)|F(FixedReg)                                   , 0  , 0  , 64 , 458, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #183
-  { F(UseR)|F(FixedRM)|F(Rep)|F(Repnz)                    , 0  , 0  , 0  , 459, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #184
-  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 333, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #185
-  { F(UseX)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 335, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #186
-  { F(UseX)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 337, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #187
-  { F(UseX)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 335, 2 , JUMP_TYPE(None)       , SINGLE_REG(RO)  , 0 }, // #188
-  { F(UseX)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 335, 2 , JUMP_TYPE(None)       , SINGLE_REG(WO)  , 0 }, // #189
-  { F(UseX)|F(Mmx)                                        , 0  , 0  , 0  , 335, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #190
-  { F(UseX)|F(Vec)                                        , 0  , 0  , 0  , 336, 1 , JUMP_TYPE(None)       , SINGLE_REG(WO)  , 0 }, // #191
-  { F(UseR)|F(FixedReg)|F(Vec)                            , 0  , 0  , 0  , 460, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #192
+  { F(UseR)                                               , 0  , 0  , 0  , 435, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #99
+  { F(UseR)                                               , 0  , 0  , 0  , 299, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #100
+  { F(UseR)                                               , 0  , 0  , 0  , 436, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #101
+  { F(UseR)                                               , 0  , 0  , 18 , 437, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #102
+  { F(UseR)                                               , 0  , 0  , 19 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #103
+  { F(UseR)                                               , 0  , 0  , 20 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #104
+  { F(UseR)                                               , 0  , 0  , 21 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #105
+  { F(UseR)                                               , 0  , 0  , 20 , 438, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #106
+  { F(UseR)                                               , 0  , 0  , 22 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #107
+  { F(UseR)|F(FixedReg)                                   , 0  , 0  , 23 , 301, 2 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #108
+  { F(UseR)                                               , 0  , 0  , 24 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #109
+  { F(UseR)                                               , 0  , 0  , 25 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #110
+  { F(UseR)                                               , 0  , 0  , 26 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #111
+  { F(UseR)                                               , 0  , 0  , 27 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #112
+  { F(UseR)                                               , 0  , 0  , 28 , 303, 2 , JUMP_TYPE(Direct)     , SINGLE_REG(None), 0 }, // #113
+  { F(UseR)                                               , 0  , 0  , 19 , 438, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #114
+  { F(UseR)                                               , 0  , 0  , 29 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #115
+  { F(UseR)                                               , 0  , 0  , 30 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #116
+  { F(UseR)                                               , 0  , 0  , 31 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #117
+  { F(UseR)                                               , 0  , 0  , 32 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #118
+  { F(UseR)                                               , 0  , 0  , 33 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #119
+  { F(UseR)                                               , 0  , 0  , 34 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #120
+  { F(UseR)                                               , 0  , 0  , 35 , 437, 1 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #121
+  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 439, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #122
+  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 36 , 305, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #123
+  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 37 , 307, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #124
+  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 38 , 309, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #125
+  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 39 , 311, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #126
+  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 440, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #127
+  { F(UseR)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 441, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #128
+  { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 442, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #129
+  { F(UseW)|F(FixedReg)                                   , 0  , 0  , 0  , 443, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #130
+  { F(UseW)                                               , 0  , 0  , 0  , 313, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #131
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 0  , 228, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #132
+  { F(UseR)                                               , 0  , 0  , 0  , 444, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #133
+  { F(UseX)                                               , 0  , 0  , 0  , 315, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #134
+  { F(UseW)                                               , 0  , 0  , 0  , 445, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #135
+  { F(UseX)                                               , 0  , 0  , 0  , 180, 3 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #136
+  { F(UseR)                                               , 0  , 0  , 0  , 446, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #137
+  { F(UseW)|F(FixedRM)|F(Rep)|F(Repnz)                    , 0  , 0  , 0  , 447, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #138
+  { F(UseX)|F(FixedReg)                                   , 0  , 0  , 40 , 317, 2 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #139
+  { F(UseX)|F(FixedReg)                                   , 0  , 0  , 41 , 317, 2 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #140
+  { F(UseX)|F(FixedReg)                                   , 0  , 0  , 42 , 317, 2 , JUMP_TYPE(Conditional), SINGLE_REG(None), 0 }, // #141
+  { F(UseW)                                               , 0  , 0  , 0  , 319, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #142
+  { F(UseW)                                               , 0  , 0  , 0  , 183, 3 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #143
+  { F(UseX)|F(FixedRM)|F(Vec)                             , 0  , 0  , 0  , 448, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #144
+  { F(UseX)|F(FixedRM)|F(Mmx)                             , 0  , 0  , 0  , 449, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #145
+  { F(UseR)|F(FixedRM)                                    , 0  , 0  , 0  , 450, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #146
+  { F(UseW)|F(XRelease)                                   , 0  , 0  , 0  , 0  , 15, JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #147
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 43 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #148
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 44 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #149
+  { F(UseW)                                               , 0  , 0  , 45 , 75 , 6 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #150
+  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 16 , 46 , 321, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #151
+  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 8  , 0  , 451, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #152
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 47 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #153
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 48 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #154
+  { F(UseW)|F(Vec)                                        , 0  , 8  , 0  , 452, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #155
+  { F(UseW)|F(Vec)                                        , 8  , 8  , 49 , 234, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #156
+  { F(UseW)|F(Vec)                                        , 8  , 8  , 50 , 234, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #157
+  { F(UseW)|F(Vec)                                        , 8  , 8  , 0  , 452, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #158
+  { F(UseW)|F(Vec)                                        , 0  , 8  , 51 , 234, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #159
+  { F(UseW)|F(Vec)                                        , 0  , 8  , 52 , 234, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #160
+  { F(UseW)|F(Vec)                                        , 0  , 8  , 0  , 453, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #161
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 53 , 225, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #162
+  { F(UseW)                                               , 0  , 8  , 0  , 79 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #163
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 54 , 225, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #164
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 55 , 225, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #165
+  { F(UseW)|F(Mmx)                                        , 0  , 8  , 56 , 454, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #166
+  { F(UseW)|F(Vec)                                        , 0  , 8  , 57 , 234, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #167
+  { F(UseW)|F(Vec)                                        , 0  , 4  , 58 , 237, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #168
+  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 16 , 59 , 81 , 6 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #169
+  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 16 , 0  , 455, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #170
+  { F(UseX)|F(FixedRM)|F(Rep)|F(Repnz)                    , 0  , 0  , 0  , 456, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #171
+  { F(UseW)|F(Vec)                                        , 0  , 8  , 60 , 323, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #172
+  { F(UseW)|F(Vec)                                        , 0  , 4  , 61 , 325, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #173
+  { F(UseW)                                               , 0  , 0  , 0  , 327, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #174
+  { F(UseW)                                               , 0  , 0  , 0  , 457, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #175
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 62 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #176
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 63 , 87 , 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #177
+  { F(UseA)|F(FixedReg)                                   , 0  , 0  , 0  , 50 , 4 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #178
+  { F(UseW)|F(FixedReg)|F(Vex)                            , 0  , 0  , 0  , 329, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #179
+  { F(UseR)|F(FixedReg)                                   , 0  , 0  , 0  , 458, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #180
+  { F(UseX)|F(Lock)|F(XAcquire)|F(XRelease)               , 0  , 0  , 0  , 288, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #181
+  { F(UseR)                                               , 0  , 0  , 0  , 331, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #182
+  { F(UseX)|F(Lock)|F(XAcquire)|F(XRelease)               , 0  , 0  , 0  , 15 , 12, JUMP_TYPE(None)       , SINGLE_REG(RO)  , 0 }, // #183
+  { F(UseR)|F(FixedReg)                                   , 0  , 0  , 64 , 459, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #184
+  { F(UseR)|F(FixedRM)|F(Rep)|F(Repnz)                    , 0  , 0  , 0  , 460, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #185
+  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 333, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #186
+  { F(UseX)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 335, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #187
+  { F(UseX)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 337, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #188
+  { F(UseX)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 335, 2 , JUMP_TYPE(None)       , SINGLE_REG(RO)  , 0 }, // #189
+  { F(UseX)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 335, 2 , JUMP_TYPE(None)       , SINGLE_REG(WO)  , 0 }, // #190
+  { F(UseX)|F(Mmx)                                        , 0  , 0  , 0  , 335, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #191
+  { F(UseX)|F(Vec)                                        , 0  , 0  , 0  , 336, 1 , JUMP_TYPE(None)       , SINGLE_REG(WO)  , 0 }, // #192
   { F(UseR)|F(FixedReg)|F(Vec)                            , 0  , 0  , 0  , 461, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #193
   { F(UseR)|F(FixedReg)|F(Vec)                            , 0  , 0  , 0  , 462, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #194
   { F(UseR)|F(FixedReg)|F(Vec)                            , 0  , 0  , 0  , 463, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #195
-  { F(UseW)|F(Vec)                                        , 0  , 8  , 0  , 464, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #196
+  { F(UseR)|F(FixedReg)|F(Vec)                            , 0  , 0  , 0  , 464, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #196
   { F(UseW)|F(Vec)                                        , 0  , 8  , 0  , 465, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #197
-  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 8  , 65 , 339, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #198
-  { F(UseW)|F(Mmx)                                        , 0  , 8  , 0  , 333, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #199
-  { F(UseW)|F(Mmx)                                        , 0  , 0  , 0  , 333, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #200
-  { F(UseX)|F(Vec)                                        , 0  , 0  , 0  , 466, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #201
+  { F(UseW)|F(Vec)                                        , 0  , 8  , 0  , 466, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #198
+  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 8  , 65 , 339, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #199
+  { F(UseW)|F(Mmx)                                        , 0  , 8  , 0  , 333, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #200
+  { F(UseW)|F(Mmx)                                        , 0  , 0  , 0  , 333, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #201
   { F(UseX)|F(Vec)                                        , 0  , 0  , 0  , 467, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #202
   { F(UseX)|F(Vec)                                        , 0  , 0  , 0  , 468, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #203
-  { F(UseX)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 469, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #204
-  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 8  , 0  , 470, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #205
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 0  , 255, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #206
-  { F(UseW)|F(Vec)                                        , 0  , 16 , 0  , 258, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #207
-  { F(UseW)|F(FixedReg)                                   , 0  , 0  , 66 , 142, 4 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #208
-  { F(UseR)                                               , 0  , 0  , 0  , 471, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #209
+  { F(UseX)|F(Vec)                                        , 0  , 0  , 0  , 469, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #204
+  { F(UseX)|F(Mmx)|F(Vec)                                 , 0  , 0  , 0  , 470, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #205
+  { F(UseW)|F(Mmx)|F(Vec)                                 , 0  , 8  , 0  , 471, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #206
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 0  , 255, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #207
+  { F(UseW)|F(Vec)                                        , 0  , 16 , 0  , 258, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #208
+  { F(UseW)|F(FixedReg)                                   , 0  , 0  , 66 , 142, 4 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #209
   { F(UseW)|F(Vec)                                        , 0  , 16 , 0  , 94 , 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #210
   { F(UseW)|F(Mmx)                                        , 0  , 8  , 0  , 472, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #211
   { F(UseX)|F(Mmx)|F(Vec)                                 , 0  , 0  , 67 , 341, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #212
@@ -2093,13 +2092,13 @@ const X86Inst::CommonData X86InstDB::commonData[] = {
   { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 204, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #333
   { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 85 , 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #334
   { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 255, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #335
-  { F(UseW)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 79 , 111, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #336
-  { F(UseW)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 80 , 116, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #337
+  { F(UseX)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 79 , 111, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #336
+  { F(UseX)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 80 , 116, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #337
   { F(UseR)|F(Vsib)|F(Evex)|F(Avx512K)                    , 0  , 0  , 0  , 507, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #338
   { F(UseR)|F(Vsib)|F(Evex)|F(Avx512K)                    , 0  , 0  , 0  , 508, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #339
   { F(UseR)|F(Vsib)|F(Evex)|F(Avx512K)                    , 0  , 0  , 0  , 509, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #340
-  { F(UseW)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 81 , 121, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #341
-  { F(UseW)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 82 , 154, 4 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #342
+  { F(UseX)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 81 , 121, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #341
+  { F(UseX)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 82 , 154, 4 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #342
   { F(UseW)|F(Vec)|F(Evex)|F(Avx512KZ_SAE)                , 0  , 0  , 0  , 85 , 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #343
   { F(UseW)|F(Vec)|F(Evex)|F(Avx512KZ_SAE)                , 0  , 0  , 0  , 255, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #344
   { F(UseW)|F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64)            , 0  , 0  , 0  , 219, 3 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #345
@@ -2111,7 +2110,7 @@ const X86Inst::CommonData X86InstDB::commonData[] = {
   { F(UseW)|F(Vec)|F(Evex)|F(Avx512KZ)                    , 0  , 0  , 0  , 510, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #351
   { F(UseW)|F(Vec)|F(Vex)|F(Evex)                         , 0  , 0  , 0  , 511, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #352
   { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 228, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #353
-  { F(UseR)|F(Vex)                                        , 0  , 0  , 0  , 443, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #354
+  { F(UseR)|F(Vex)                                        , 0  , 0  , 0  , 444, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #354
   { F(UseR)|F(FixedRM)|F(Vec)|F(Vex)                      , 0  , 0  , 0  , 512, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #355
   { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 83 , 158, 4 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #356
   { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 84 , 158, 4 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #357
@@ -2163,10 +2162,10 @@ const X86Inst::CommonData X86InstDB::commonData[] = {
   { F(UseW)|F(Vec)|F(Vex)|F(Evex)|F(Avx512K)              , 0  , 0  , 0  , 243, 3 , JUMP_TYPE(None)       , SINGLE_REG(WO)  , 0 }, // #403
   { F(UseW)|F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B32)          , 0  , 0  , 0  , 243, 3 , JUMP_TYPE(None)       , SINGLE_REG(WO)  , 0 }, // #404
   { F(UseW)|F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B64)          , 0  , 0  , 0  , 243, 3 , JUMP_TYPE(None)       , SINGLE_REG(WO)  , 0 }, // #405
-  { F(UseR)|F(FixedReg)|F(Vec)|F(Vex)                     , 0  , 0  , 0  , 460, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #406
-  { F(UseR)|F(FixedReg)|F(Vec)|F(Vex)                     , 0  , 0  , 0  , 461, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #407
-  { F(UseR)|F(FixedReg)|F(Vec)|F(Vex)                     , 0  , 0  , 0  , 462, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #408
-  { F(UseR)|F(FixedReg)|F(Vec)|F(Vex)                     , 0  , 0  , 0  , 463, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #409
+  { F(UseR)|F(FixedReg)|F(Vec)|F(Vex)                     , 0  , 0  , 0  , 461, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #406
+  { F(UseR)|F(FixedReg)|F(Vec)|F(Vex)                     , 0  , 0  , 0  , 462, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #407
+  { F(UseR)|F(FixedReg)|F(Vec)|F(Vex)                     , 0  , 0  , 0  , 463, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #408
+  { F(UseR)|F(FixedReg)|F(Vec)|F(Vex)                     , 0  , 0  , 0  , 464, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #409
   { F(UseW)|F(Vec)|F(Evex)|F(Avx512K_B64)                 , 0  , 0  , 0  , 240, 3 , JUMP_TYPE(None)       , SINGLE_REG(WO)  , 0 }, // #410
   { F(UseW)|F(Vec)|F(Evex)|F(Avx512KZ_B32)                , 0  , 0  , 0  , 204, 3 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #411
   { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 193, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #412
@@ -2180,13 +2179,13 @@ const X86Inst::CommonData X86InstDB::commonData[] = {
   { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 96 , 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #420
   { F(UseW)|F(Vec)|F(Vex)                                 , 0  , 0  , 0  , 95 , 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #421
   { F(UseW)|F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64)         , 0  , 0  , 107, 166, 4 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #422
-  { F(UseW)|F(Vec)|F(Vex)|F(Evex)                         , 0  , 0  , 0  , 464, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #423
-  { F(UseW)|F(Vec)|F(Vex)|F(Evex)                         , 0  , 0  , 0  , 465, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #424
+  { F(UseW)|F(Vec)|F(Vex)|F(Evex)                         , 0  , 0  , 0  , 465, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #423
+  { F(UseW)|F(Vec)|F(Vex)|F(Evex)                         , 0  , 0  , 0  , 466, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #424
   { F(UseW)|F(Vec)|F(Vex)|F(Evex)                         , 0  , 0  , 0  , 340, 1 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #425
-  { F(UseW)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 108, 116, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #426
-  { F(UseW)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 109, 111, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #427
-  { F(UseW)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 110, 154, 4 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #428
-  { F(UseW)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 111, 121, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #429
+  { F(UseX)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 108, 116, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #426
+  { F(UseX)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 109, 111, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #427
+  { F(UseX)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 110, 154, 4 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #428
+  { F(UseX)|F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K)      , 0  , 0  , 111, 121, 5 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #429
   { F(UseW)|F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)             , 0  , 0  , 0  , 367, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #430
   { F(UseW)|F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)             , 0  , 0  , 0  , 369, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #431
   { F(UseW)|F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ)             , 0  , 0  , 0  , 371, 2 , JUMP_TYPE(None)       , SINGLE_REG(None), 0 }, // #432
@@ -2438,9 +2437,11 @@ const X86Inst::OperationData X86InstDB::operationData[] = {
   { OP_FLAG(Volatile) | OP_FLAG(Privileged), { FEATURE(MSR) }, 0, SPECIAL(MSR) }, // #148
   { OP_FLAG(Volatile), { FEATURE(RTM) }, 0, 0 }, // #149
   { OP_FLAG(Volatile), { FEATURE(XSAVE) }, SPECIAL(XCR), 0 }, // #150
-  { OP_FLAG(Volatile), { FEATURE(XSAVEOPT) }, SPECIAL(XCR), 0 }, // #151
-  { OP_FLAG(Volatile) | OP_FLAG(Privileged), { FEATURE(XSAVE) }, 0, SPECIAL(XCR) }, // #152
-  { OP_FLAG(Volatile), { FEATURE(TSX) }, 0, SPECIAL(FLAGS_AF) | SPECIAL(FLAGS_CF) | SPECIAL(FLAGS_OF) | SPECIAL(FLAGS_PF) | SPECIAL(FLAGS_SF) | SPECIAL(FLAGS_ZF) }  // #153
+  { OP_FLAG(Volatile), { FEATURE(XSAVES) }, SPECIAL(XCR), 0 }, // #151
+  { OP_FLAG(Volatile), { FEATURE(XSAVEC) }, SPECIAL(XCR), 0 }, // #152
+  { OP_FLAG(Volatile), { FEATURE(XSAVEOPT) }, SPECIAL(XCR), 0 }, // #153
+  { OP_FLAG(Volatile) | OP_FLAG(Privileged), { FEATURE(XSAVE) }, 0, SPECIAL(XCR) }, // #154
+  { OP_FLAG(Volatile), { FEATURE(TSX) }, 0, SPECIAL(FLAGS_AF) | SPECIAL(FLAGS_CF) | SPECIAL(FLAGS_OF) | SPECIAL(FLAGS_PF) | SPECIAL(FLAGS_SF) | SPECIAL(FLAGS_ZF) }  // #155
 };
 #undef SPECIAL
 #undef FEATURE
@@ -2792,21 +2793,21 @@ static const InstNameAZ X86InstNameAZ[26] = {
 
 uint32_t X86Inst::getIdByName(const char* name, size_t len) noexcept {
   if (ASMJIT_UNLIKELY(!name))
-    return Globals::kInvalidInstId;
+    return Inst::kIdNone;
 
   if (len == Globals::kInvalidIndex)
     len = ::strlen(name);
 
   if (ASMJIT_UNLIKELY(len == 0 || len > kX86InstMaxLength))
-    return Globals::kInvalidInstId;
+    return Inst::kIdNone;
 
   uint32_t prefix = static_cast<uint32_t>(name[0]) - 'a';
   if (ASMJIT_UNLIKELY(prefix > 'z' - 'a'))
-    return Globals::kInvalidInstId;
+    return Inst::kIdNone;
 
   uint32_t index = X86InstNameAZ[prefix].start;
   if (ASMJIT_UNLIKELY(!index))
-    return Globals::kInvalidInstId;
+    return Inst::kIdNone;
 
   const char* nameData = X86InstDB::nameData;
   const X86Inst* instData = X86InstDB::instData;
@@ -2830,7 +2831,7 @@ uint32_t X86Inst::getIdByName(const char* name, size_t len) noexcept {
     return static_cast<uint32_t>((size_t)(cur - instData));
   }
 
-  return Globals::kInvalidInstId;
+  return Inst::kIdNone;
 }
 
 const char* X86Inst::getNameById(uint32_t id) noexcept {
@@ -2943,8 +2944,11 @@ const X86Inst::OSignature X86InstDB::oSignatureData[] = {
   OSIGNATURE(FLAG(R) | FLAG(Zmm), 0, 0, 0x00),
   OSIGNATURE(FLAG(R) | FLAG(U8), 0, 0, 0x00),
   OSIGNATURE(FLAG(R) | FLAG(Xmm) | FLAG(Mem) | FLAG(U8), MEM(Any) | MEM(M128), 0, 0x00),
+  OSIGNATURE(FLAG(X) | FLAG(Xmm), 0, 0, 0x00),
   OSIGNATURE(FLAG(R) | FLAG(Vm), MEM(Vm32x), 0, 0x00),
+  OSIGNATURE(FLAG(X) | FLAG(Ymm), 0, 0, 0x00),
   OSIGNATURE(FLAG(R) | FLAG(Vm), MEM(Vm32y), 0, 0x00),
+  OSIGNATURE(FLAG(X) | FLAG(Zmm), 0, 0, 0x00),
   OSIGNATURE(FLAG(R) | FLAG(Vm), MEM(Vm32z), 0, 0x00),
   OSIGNATURE(FLAG(R) | FLAG(Vm), MEM(Vm64x), 0, 0x00),
   OSIGNATURE(FLAG(R) | FLAG(Vm), MEM(Vm64y), 0, 0x00),
@@ -2986,9 +2990,6 @@ const X86Inst::OSignature X86InstDB::oSignatureData[] = {
   OSIGNATURE(FLAG(R) | FLAG(Xmm) | FLAG(Ymm) | FLAG(Mem), MEM(M64) | MEM(M128) | MEM(M256), 0, 0x00),
   OSIGNATURE(FLAG(R) | FLAG(Xmm) | FLAG(Mem), MEM(M128), 0, 0x00),
   OSIGNATURE(FLAG(R) | FLAG(Ymm) | FLAG(Mem), MEM(M256), 0, 0x00),
-  OSIGNATURE(FLAG(X) | FLAG(Xmm), 0, 0, 0x00),
-  OSIGNATURE(FLAG(X) | FLAG(Ymm), 0, 0, 0x00),
-  OSIGNATURE(FLAG(X) | FLAG(Zmm), 0, 0, 0x00),
   OSIGNATURE(FLAG(W) | FLAG(Mem), MEM(Any) | MEM(M512), 0, 0x00),
   OSIGNATURE(FLAG(R) | FLAG(Mem), MEM(Any) | MEM(M512), 0, 0x00),
   OSIGNATURE(FLAG(R) | FLAG(Gpq) | FLAG(Xmm) | FLAG(Mem), MEM(Any) | MEM(M64), 0, 0x00),
@@ -3220,61 +3221,61 @@ const X86Inst::ISignature X86InstDB::iSignatureData[] = {
   ISIGNATURE(3, 1, 1, 0, 79 , 80 , 87 , 0  , 0  , 0  ), //      {W:ymm, R:ymm|m256|mem, R:u8}
   ISIGNATURE(3, 1, 1, 0, 83 , 86 , 77 , 0  , 0  , 0  ), //      {W:zmm, R:zmm, R:xmm|m128|mem}
   ISIGNATURE(3, 1, 1, 0, 83 , 84 , 87 , 0  , 0  , 0  ), //      {W:zmm, R:zmm|m512|mem, R:u8}
-  ISIGNATURE(3, 1, 1, 0, 74 , 89 , 73 , 0  , 0  , 0  ), // #111 {W:xmm, R:vm32x, R:xmm}
-  ISIGNATURE(3, 1, 1, 0, 79 , 89 , 82 , 0  , 0  , 0  ), //      {W:ymm, R:vm32x, R:ymm}
-  ISIGNATURE(2, 1, 1, 0, 74 , 89 , 0  , 0  , 0  , 0  ), //      {W:xmm, R:vm32x}
-  ISIGNATURE(2, 1, 1, 0, 79 , 90 , 0  , 0  , 0  , 0  ), //      {W:ymm, R:vm32y}
-  ISIGNATURE(2, 1, 1, 0, 83 , 91 , 0  , 0  , 0  , 0  ), //      {W:zmm, R:vm32z}
-  ISIGNATURE(3, 1, 1, 0, 74 , 89 , 73 , 0  , 0  , 0  ), // #116 {W:xmm, R:vm32x, R:xmm}
-  ISIGNATURE(3, 1, 1, 0, 79 , 90 , 82 , 0  , 0  , 0  ), //      {W:ymm, R:vm32y, R:ymm}
-  ISIGNATURE(2, 1, 1, 0, 74 , 89 , 0  , 0  , 0  , 0  ), //      {W:xmm, R:vm32x}
-  ISIGNATURE(2, 1, 1, 0, 79 , 90 , 0  , 0  , 0  , 0  ), //      {W:ymm, R:vm32y}
-  ISIGNATURE(2, 1, 1, 0, 83 , 91 , 0  , 0  , 0  , 0  ), //      {W:zmm, R:vm32z}
-  ISIGNATURE(3, 1, 1, 0, 74 , 92 , 73 , 0  , 0  , 0  ), // #121 {W:xmm, R:vm64x, R:xmm}
-  ISIGNATURE(3, 1, 1, 0, 79 , 93 , 82 , 0  , 0  , 0  ), //      {W:ymm, R:vm64y, R:ymm}
-  ISIGNATURE(2, 1, 1, 0, 74 , 92 , 0  , 0  , 0  , 0  ), //      {W:xmm, R:vm64x}
-  ISIGNATURE(2, 1, 1, 0, 79 , 93 , 0  , 0  , 0  , 0  ), //      {W:ymm, R:vm64y}
-  ISIGNATURE(2, 1, 1, 0, 83 , 94 , 0  , 0  , 0  , 0  ), //      {W:zmm, R:vm64z}
+  ISIGNATURE(3, 1, 1, 0, 89 , 90 , 89 , 0  , 0  , 0  ), // #111 {X:xmm, R:vm32x, X:xmm}
+  ISIGNATURE(3, 1, 1, 0, 91 , 90 , 91 , 0  , 0  , 0  ), //      {X:ymm, R:vm32x, X:ymm}
+  ISIGNATURE(2, 1, 1, 0, 89 , 90 , 0  , 0  , 0  , 0  ), //      {X:xmm, R:vm32x}
+  ISIGNATURE(2, 1, 1, 0, 91 , 92 , 0  , 0  , 0  , 0  ), //      {X:ymm, R:vm32y}
+  ISIGNATURE(2, 1, 1, 0, 93 , 94 , 0  , 0  , 0  , 0  ), //      {X:zmm, R:vm32z}
+  ISIGNATURE(3, 1, 1, 0, 89 , 90 , 89 , 0  , 0  , 0  ), // #116 {X:xmm, R:vm32x, X:xmm}
+  ISIGNATURE(3, 1, 1, 0, 91 , 92 , 91 , 0  , 0  , 0  ), //      {X:ymm, R:vm32y, X:ymm}
+  ISIGNATURE(2, 1, 1, 0, 89 , 90 , 0  , 0  , 0  , 0  ), //      {X:xmm, R:vm32x}
+  ISIGNATURE(2, 1, 1, 0, 91 , 92 , 0  , 0  , 0  , 0  ), //      {X:ymm, R:vm32y}
+  ISIGNATURE(2, 1, 1, 0, 93 , 94 , 0  , 0  , 0  , 0  ), //      {X:zmm, R:vm32z}
+  ISIGNATURE(3, 1, 1, 0, 89 , 95 , 89 , 0  , 0  , 0  ), // #121 {X:xmm, R:vm64x, X:xmm}
+  ISIGNATURE(3, 1, 1, 0, 91 , 96 , 91 , 0  , 0  , 0  ), //      {X:ymm, R:vm64y, X:ymm}
+  ISIGNATURE(2, 1, 1, 0, 89 , 95 , 0  , 0  , 0  , 0  ), //      {X:xmm, R:vm64x}
+  ISIGNATURE(2, 1, 1, 0, 91 , 96 , 0  , 0  , 0  , 0  ), //      {X:ymm, R:vm64y}
+  ISIGNATURE(2, 1, 1, 0, 93 , 97 , 0  , 0  , 0  , 0  ), //      {X:zmm, R:vm64z}
   ISIGNATURE(2, 1, 1, 0, 12 , 37 , 0  , 0  , 0  , 0  ), // #126 {R:r16|m16|mem, R:r16}
   ISIGNATURE(2, 1, 1, 0, 43 , 6  , 0  , 0  , 0  , 0  ), //      {R:r32|m32|mem, R:r32}
-  ISIGNATURE(2, 0, 1, 0, 16 , 95 , 0  , 0  , 0  , 0  ), //      {R:r64|m64|mem, R:r64|u8}
-  ISIGNATURE(2, 1, 1, 0, 96 , 87 , 0  , 0  , 0  , 0  ), //      {R:r16|m16|r32|m32, R:u8}
+  ISIGNATURE(2, 0, 1, 0, 16 , 98 , 0  , 0  , 0  , 0  ), //      {R:r64|m64|mem, R:r64|u8}
+  ISIGNATURE(2, 1, 1, 0, 99 , 87 , 0  , 0  , 0  , 0  ), //      {R:r16|m16|r32|m32, R:u8}
   ISIGNATURE(2, 1, 1, 0, 36 , 37 , 0  , 0  , 0  , 0  ), // #130 {X:r16|m16|mem, R:r16}
   ISIGNATURE(2, 1, 1, 0, 38 , 6  , 0  , 0  , 0  , 0  ), //      {X:r32|m32|mem, R:r32}
-  ISIGNATURE(2, 0, 1, 0, 31 , 95 , 0  , 0  , 0  , 0  ), //      {X:r64|m64|mem, R:r64|u8}
-  ISIGNATURE(2, 1, 1, 0, 97 , 87 , 0  , 0  , 0  , 0  ), //      {X:r16|m16|r32|m32, R:u8}
-  ISIGNATURE(3, 1, 1, 1, 35 , 2  , 98 , 0  , 0  , 0  ), // #134 {X:r8lo|r8hi|m8|mem, R:r8lo|r8hi, R:<al>}
-  ISIGNATURE(3, 1, 1, 1, 36 , 37 , 99 , 0  , 0  , 0  ), //      {X:r16|m16|mem, R:r16, R:<ax>}
-  ISIGNATURE(3, 1, 1, 1, 38 , 6  , 100, 0  , 0  , 0  ), //      {X:r32|m32|mem, R:r32, R:<eax>}
-  ISIGNATURE(3, 0, 1, 1, 31 , 27 , 101, 0  , 0  , 0  ), //      {X:r64|m64|mem, R:r64, R:<rax>}
+  ISIGNATURE(2, 0, 1, 0, 31 , 98 , 0  , 0  , 0  , 0  ), //      {X:r64|m64|mem, R:r64|u8}
+  ISIGNATURE(2, 1, 1, 0, 100, 87 , 0  , 0  , 0  , 0  ), //      {X:r16|m16|r32|m32, R:u8}
+  ISIGNATURE(3, 1, 1, 1, 35 , 2  , 101, 0  , 0  , 0  ), // #134 {X:r8lo|r8hi|m8|mem, R:r8lo|r8hi, R:<al>}
+  ISIGNATURE(3, 1, 1, 1, 36 , 37 , 102, 0  , 0  , 0  ), //      {X:r16|m16|mem, R:r16, R:<ax>}
+  ISIGNATURE(3, 1, 1, 1, 38 , 6  , 103, 0  , 0  , 0  ), //      {X:r32|m32|mem, R:r32, R:<eax>}
+  ISIGNATURE(3, 0, 1, 1, 31 , 27 , 104, 0  , 0  , 0  ), //      {X:r64|m64|mem, R:r64, R:<rax>}
   ISIGNATURE(2, 1, 1, 1, 50 , 40 , 0  , 0  , 0  , 0  ), // #138 {X:<ax>, R:r8lo|r8hi|m8|mem}
-  ISIGNATURE(3, 1, 1, 2, 102, 50 , 12 , 0  , 0  , 0  ), //      {X:<dx>, X:<ax>, R:r16|m16|mem}
-  ISIGNATURE(3, 1, 1, 2, 103, 53 , 43 , 0  , 0  , 0  ), //      {X:<edx>, X:<eax>, R:r32|m32|mem}
-  ISIGNATURE(3, 0, 1, 2, 104, 55 , 16 , 0  , 0  , 0  ), //      {X:<rdx>, X:<rax>, R:r64|m64|mem}
-  ISIGNATURE(1, 1, 1, 0, 105, 0  , 0  , 0  , 0  , 0  ), // #142 {W:r16|m16|r64|m64|mem}
+  ISIGNATURE(3, 1, 1, 2, 105, 50 , 12 , 0  , 0  , 0  ), //      {X:<dx>, X:<ax>, R:r16|m16|mem}
+  ISIGNATURE(3, 1, 1, 2, 106, 53 , 43 , 0  , 0  , 0  ), //      {X:<edx>, X:<eax>, R:r32|m32|mem}
+  ISIGNATURE(3, 0, 1, 2, 107, 55 , 16 , 0  , 0  , 0  ), //      {X:<rdx>, X:<rax>, R:r64|m64|mem}
+  ISIGNATURE(1, 1, 1, 0, 108, 0  , 0  , 0  , 0  , 0  ), // #142 {W:r16|m16|r64|m64|mem}
   ISIGNATURE(1, 1, 0, 0, 23 , 0  , 0  , 0  , 0  , 0  ), //      {W:r32|m32}
-  ISIGNATURE(1, 1, 0, 0, 106, 0  , 0  , 0  , 0  , 0  ), //      {W:ds|es|ss}
-  ISIGNATURE(1, 1, 1, 0, 107, 0  , 0  , 0  , 0  , 0  ), //      {W:fs|gs}
-  ISIGNATURE(1, 1, 1, 0, 108, 0  , 0  , 0  , 0  , 0  ), // #146 {R:r16|m16|r64|m64|mem|i8|i16|i32}
+  ISIGNATURE(1, 1, 0, 0, 109, 0  , 0  , 0  , 0  , 0  ), //      {W:ds|es|ss}
+  ISIGNATURE(1, 1, 1, 0, 110, 0  , 0  , 0  , 0  , 0  ), //      {W:fs|gs}
+  ISIGNATURE(1, 1, 1, 0, 111, 0  , 0  , 0  , 0  , 0  ), // #146 {R:r16|m16|r64|m64|mem|i8|i16|i32}
   ISIGNATURE(1, 1, 0, 0, 47 , 0  , 0  , 0  , 0  , 0  ), //      {R:r32|m32}
-  ISIGNATURE(1, 1, 0, 0, 109, 0  , 0  , 0  , 0  , 0  ), //      {R:cs|ss|ds|es}
-  ISIGNATURE(1, 1, 1, 0, 110, 0  , 0  , 0  , 0  , 0  ), //      {R:fs|gs}
+  ISIGNATURE(1, 1, 0, 0, 112, 0  , 0  , 0  , 0  , 0  ), //      {R:cs|ss|ds|es}
+  ISIGNATURE(1, 1, 1, 0, 113, 0  , 0  , 0  , 0  , 0  ), //      {R:fs|gs}
   ISIGNATURE(4, 1, 1, 0, 74 , 73 , 73 , 77 , 0  , 0  ), // #150 {W:xmm, R:xmm, R:xmm, R:xmm|m128|mem}
   ISIGNATURE(4, 1, 1, 0, 74 , 73 , 77 , 73 , 0  , 0  ), // #151 {W:xmm, R:xmm, R:xmm|m128|mem, R:xmm}
   ISIGNATURE(4, 1, 1, 0, 79 , 82 , 82 , 80 , 0  , 0  ), //      {W:ymm, R:ymm, R:ymm, R:ymm|m256|mem}
   ISIGNATURE(4, 1, 1, 0, 79 , 82 , 80 , 82 , 0  , 0  ), //      {W:ymm, R:ymm, R:ymm|m256|mem, R:ymm}
-  ISIGNATURE(3, 1, 1, 0, 74 , 111, 73 , 0  , 0  , 0  ), // #154 {W:xmm, R:vm64x|vm64y, R:xmm}
-  ISIGNATURE(2, 1, 1, 0, 74 , 92 , 0  , 0  , 0  , 0  ), //      {W:xmm, R:vm64x}
-  ISIGNATURE(2, 1, 1, 0, 79 , 93 , 0  , 0  , 0  , 0  ), //      {W:ymm, R:vm64y}
-  ISIGNATURE(2, 1, 1, 0, 83 , 94 , 0  , 0  , 0  , 0  ), //      {W:zmm, R:vm64z}
-  ISIGNATURE(3, 1, 1, 0, 112, 73 , 73 , 0  , 0  , 0  ), // #158 {W:m128|mem, R:xmm, R:xmm}
-  ISIGNATURE(3, 1, 1, 0, 113, 82 , 82 , 0  , 0  , 0  ), //      {W:m256|mem, R:ymm, R:ymm}
-  ISIGNATURE(3, 1, 1, 0, 74 , 73 , 114, 0  , 0  , 0  ), //      {W:xmm, R:xmm, R:m128|mem}
-  ISIGNATURE(3, 1, 1, 0, 79 , 82 , 115, 0  , 0  , 0  ), //      {W:ymm, R:ymm, R:m256|mem}
-  ISIGNATURE(5, 1, 1, 0, 74 , 73 , 77 , 73 , 116, 0  ), // #162 {W:xmm, R:xmm, R:xmm|m128|mem, R:xmm, R:u4}
-  ISIGNATURE(5, 1, 1, 0, 74 , 73 , 73 , 77 , 116, 0  ), //      {W:xmm, R:xmm, R:xmm, R:xmm|m128|mem, R:u4}
-  ISIGNATURE(5, 1, 1, 0, 79 , 82 , 80 , 82 , 116, 0  ), //      {W:ymm, R:ymm, R:ymm|m256|mem, R:ymm, R:u4}
-  ISIGNATURE(5, 1, 1, 0, 79 , 82 , 82 , 80 , 116, 0  ), //      {W:ymm, R:ymm, R:ymm, R:ymm|m256|mem, R:u4}
+  ISIGNATURE(3, 1, 1, 0, 89 , 114, 89 , 0  , 0  , 0  ), // #154 {X:xmm, R:vm64x|vm64y, X:xmm}
+  ISIGNATURE(2, 1, 1, 0, 89 , 95 , 0  , 0  , 0  , 0  ), //      {X:xmm, R:vm64x}
+  ISIGNATURE(2, 1, 1, 0, 91 , 96 , 0  , 0  , 0  , 0  ), //      {X:ymm, R:vm64y}
+  ISIGNATURE(2, 1, 1, 0, 93 , 97 , 0  , 0  , 0  , 0  ), //      {X:zmm, R:vm64z}
+  ISIGNATURE(3, 1, 1, 0, 115, 73 , 73 , 0  , 0  , 0  ), // #158 {W:m128|mem, R:xmm, R:xmm}
+  ISIGNATURE(3, 1, 1, 0, 116, 82 , 82 , 0  , 0  , 0  ), //      {W:m256|mem, R:ymm, R:ymm}
+  ISIGNATURE(3, 1, 1, 0, 74 , 73 , 117, 0  , 0  , 0  ), //      {W:xmm, R:xmm, R:m128|mem}
+  ISIGNATURE(3, 1, 1, 0, 79 , 82 , 118, 0  , 0  , 0  ), //      {W:ymm, R:ymm, R:m256|mem}
+  ISIGNATURE(5, 1, 1, 0, 74 , 73 , 77 , 73 , 119, 0  ), // #162 {W:xmm, R:xmm, R:xmm|m128|mem, R:xmm, R:u4}
+  ISIGNATURE(5, 1, 1, 0, 74 , 73 , 73 , 77 , 119, 0  ), //      {W:xmm, R:xmm, R:xmm, R:xmm|m128|mem, R:u4}
+  ISIGNATURE(5, 1, 1, 0, 79 , 82 , 80 , 82 , 119, 0  ), //      {W:ymm, R:ymm, R:ymm|m256|mem, R:ymm, R:u4}
+  ISIGNATURE(5, 1, 1, 0, 79 , 82 , 82 , 80 , 119, 0  ), //      {W:ymm, R:ymm, R:ymm, R:ymm|m256|mem, R:u4}
   ISIGNATURE(3, 1, 1, 0, 79 , 80 , 87 , 0  , 0  , 0  ), // #166 {W:ymm, R:ymm|m256|mem, R:u8}
   ISIGNATURE(3, 1, 1, 0, 79 , 82 , 80 , 0  , 0  , 0  ), // #167 {W:ymm, R:ymm, R:ymm|m256|mem}
   ISIGNATURE(3, 1, 1, 0, 83 , 86 , 84 , 0  , 0  , 0  ), //      {W:zmm, R:zmm, R:zmm|m512|mem}
@@ -3283,30 +3284,30 @@ const X86Inst::ISignature X86InstDB::iSignatureData[] = {
   ISIGNATURE(2, 1, 1, 0, 36 , 41 , 0  , 0  , 0  , 0  ), //      {X:r16|m16|mem, X:r16}
   ISIGNATURE(2, 1, 1, 0, 38 , 42 , 0  , 0  , 0  , 0  ), //      {X:r32|m32|mem, X:r32}
   ISIGNATURE(2, 0, 1, 0, 31 , 44 , 0  , 0  , 0  , 0  ), //      {X:r64|m64|mem, X:r64}
-  ISIGNATURE(1, 1, 1, 0, 117, 0  , 0  , 0  , 0  , 0  ), // #174 {R:m32|m64}
-  ISIGNATURE(2, 1, 1, 0, 118, 119, 0  , 0  , 0  , 0  ), //      {X:fp0, R:fp}
-  ISIGNATURE(2, 1, 1, 0, 120, 121, 0  , 0  , 0  , 0  ), //      {X:fp, R:fp0}
-  ISIGNATURE(1, 1, 1, 0, 122, 0  , 0  , 0  , 0  , 0  ), // #177 {X:m32|m64}
-  ISIGNATURE(2, 1, 1, 0, 118, 119, 0  , 0  , 0  , 0  ), //      {X:fp0, R:fp}
-  ISIGNATURE(2, 1, 1, 0, 120, 121, 0  , 0  , 0  , 0  ), //      {X:fp, R:fp0}
+  ISIGNATURE(1, 1, 1, 0, 120, 0  , 0  , 0  , 0  , 0  ), // #174 {R:m32|m64}
+  ISIGNATURE(2, 1, 1, 0, 121, 122, 0  , 0  , 0  , 0  ), //      {X:fp0, R:fp}
+  ISIGNATURE(2, 1, 1, 0, 123, 124, 0  , 0  , 0  , 0  ), //      {X:fp, R:fp0}
+  ISIGNATURE(1, 1, 1, 0, 125, 0  , 0  , 0  , 0  , 0  ), // #177 {X:m32|m64}
+  ISIGNATURE(2, 1, 1, 0, 121, 122, 0  , 0  , 0  , 0  ), //      {X:fp0, R:fp}
+  ISIGNATURE(2, 1, 1, 0, 123, 124, 0  , 0  , 0  , 0  ), //      {X:fp, R:fp0}
   ISIGNATURE(2, 1, 1, 0, 41 , 64 , 0  , 0  , 0  , 0  ), // #180 {X:r16, R:m32|mem}
-  ISIGNATURE(2, 1, 1, 0, 42 , 123, 0  , 0  , 0  , 0  ), //      {X:r32, R:m48|mem}
-  ISIGNATURE(2, 0, 1, 0, 44 , 124, 0  , 0  , 0  , 0  ), //      {X:r64, R:m80|mem}
+  ISIGNATURE(2, 1, 1, 0, 42 , 126, 0  , 0  , 0  , 0  ), //      {X:r32, R:m48|mem}
+  ISIGNATURE(2, 0, 1, 0, 44 , 127, 0  , 0  , 0  , 0  ), //      {X:r64, R:m80|mem}
   ISIGNATURE(2, 1, 1, 0, 59 , 12 , 0  , 0  , 0  , 0  ), // #183 {W:r16, R:r16|m16|mem}
   ISIGNATURE(2, 1, 1, 0, 13 , 43 , 0  , 0  , 0  , 0  ), // #184 {W:r32, R:r32|m32|mem}
   ISIGNATURE(2, 0, 1, 0, 19 , 16 , 0  , 0  , 0  , 0  ), //      {W:r64, R:r64|m64|mem}
-  ISIGNATURE(3, 1, 1, 0, 36 , 37 , 125, 0  , 0  , 0  ), // #186 {X:r16|m16|mem, R:r16, R:u8|cl}
-  ISIGNATURE(3, 1, 1, 0, 38 , 6  , 125, 0  , 0  , 0  ), //      {X:r32|m32|mem, R:r32, R:u8|cl}
-  ISIGNATURE(3, 0, 1, 0, 31 , 27 , 125, 0  , 0  , 0  ), //      {X:r64|m64|mem, R:r64, R:u8|cl}
+  ISIGNATURE(3, 1, 1, 0, 36 , 37 , 128, 0  , 0  , 0  ), // #186 {X:r16|m16|mem, R:r16, R:u8|cl}
+  ISIGNATURE(3, 1, 1, 0, 38 , 6  , 128, 0  , 0  , 0  ), //      {X:r32|m32|mem, R:r32, R:u8|cl}
+  ISIGNATURE(3, 0, 1, 0, 31 , 27 , 128, 0  , 0  , 0  ), //      {X:r64|m64|mem, R:r64, R:u8|cl}
   ISIGNATURE(3, 1, 1, 0, 74 , 73 , 77 , 0  , 0  , 0  ), // #189 {W:xmm, R:xmm, R:xmm|m128|mem}
   ISIGNATURE(3, 1, 1, 0, 79 , 82 , 80 , 0  , 0  , 0  ), //      {W:ymm, R:ymm, R:ymm|m256|mem}
   ISIGNATURE(3, 1, 1, 0, 83 , 86 , 84 , 0  , 0  , 0  ), //      {W:zmm, R:zmm, R:zmm|m512|mem}
   ISIGNATURE(4, 1, 1, 0, 74 , 73 , 77 , 87 , 0  , 0  ), // #192 {W:xmm, R:xmm, R:xmm|m128|mem, R:u8}
   ISIGNATURE(4, 1, 1, 0, 79 , 82 , 80 , 87 , 0  , 0  ), // #193 {W:ymm, R:ymm, R:ymm|m256|mem, R:u8}
   ISIGNATURE(4, 1, 1, 0, 83 , 86 , 84 , 87 , 0  , 0  ), //      {W:zmm, R:zmm, R:zmm|m512|mem, R:u8}
-  ISIGNATURE(4, 1, 1, 0, 126, 73 , 77 , 87 , 0  , 0  ), // #195 {W:xmm|k, R:xmm, R:xmm|m128|mem, R:u8}
-  ISIGNATURE(4, 1, 1, 0, 127, 82 , 80 , 87 , 0  , 0  ), //      {W:ymm|k, R:ymm, R:ymm|m256|mem, R:u8}
-  ISIGNATURE(4, 1, 1, 0, 128, 86 , 84 , 87 , 0  , 0  ), //      {W:k, R:zmm, R:zmm|m512|mem, R:u8}
+  ISIGNATURE(4, 1, 1, 0, 129, 73 , 77 , 87 , 0  , 0  ), // #195 {W:xmm|k, R:xmm, R:xmm|m128|mem, R:u8}
+  ISIGNATURE(4, 1, 1, 0, 130, 82 , 80 , 87 , 0  , 0  ), //      {W:ymm|k, R:ymm, R:ymm|m256|mem, R:u8}
+  ISIGNATURE(4, 1, 1, 0, 131, 86 , 84 , 87 , 0  , 0  ), //      {W:k, R:zmm, R:zmm|m512|mem, R:u8}
   ISIGNATURE(2, 1, 1, 0, 78 , 73 , 0  , 0  , 0  , 0  ), // #198 {W:xmm|m128|mem, R:xmm}
   ISIGNATURE(2, 1, 1, 0, 81 , 82 , 0  , 0  , 0  , 0  ), //      {W:ymm|m256|mem, R:ymm}
   ISIGNATURE(2, 1, 1, 0, 85 , 86 , 0  , 0  , 0  , 0  ), //      {W:zmm|m512|mem, R:zmm}
@@ -3316,29 +3317,29 @@ const X86Inst::ISignature X86InstDB::iSignatureData[] = {
   ISIGNATURE(2, 1, 1, 0, 74 , 77 , 0  , 0  , 0  , 0  ), // #204 {W:xmm, R:xmm|m128|mem}
   ISIGNATURE(2, 1, 1, 0, 79 , 80 , 0  , 0  , 0  , 0  ), //      {W:ymm, R:ymm|m256|mem}
   ISIGNATURE(2, 1, 1, 0, 83 , 84 , 0  , 0  , 0  , 0  ), //      {W:zmm, R:zmm|m512|mem}
-  ISIGNATURE(2, 1, 1, 0, 74 , 129, 0  , 0  , 0  , 0  ), // #207 {W:xmm, R:xmm|m128|ymm|m256|m64}
-  ISIGNATURE(2, 1, 1, 0, 79 , 130, 0  , 0  , 0  , 0  ), //      {W:ymm, R:xmm|m128}
-  ISIGNATURE(2, 1, 1, 0, 83 , 131, 0  , 0  , 0  , 0  ), //      {W:zmm, R:ymm|m256}
+  ISIGNATURE(2, 1, 1, 0, 74 , 132, 0  , 0  , 0  , 0  ), // #207 {W:xmm, R:xmm|m128|ymm|m256|m64}
+  ISIGNATURE(2, 1, 1, 0, 79 , 133, 0  , 0  , 0  , 0  ), //      {W:ymm, R:xmm|m128}
+  ISIGNATURE(2, 1, 1, 0, 83 , 134, 0  , 0  , 0  , 0  ), //      {W:zmm, R:ymm|m256}
   ISIGNATURE(3, 1, 1, 0, 76 , 73 , 87 , 0  , 0  , 0  ), // #210 {W:xmm|m64|mem, R:xmm, R:u8}
   ISIGNATURE(3, 1, 1, 0, 78 , 82 , 87 , 0  , 0  , 0  ), // #211 {W:xmm|m128|mem, R:ymm, R:u8}
   ISIGNATURE(3, 1, 1, 0, 81 , 86 , 87 , 0  , 0  , 0  ), // #212 {W:ymm|m256|mem, R:zmm, R:u8}
-  ISIGNATURE(4, 1, 1, 0, 132, 73 , 77 , 87 , 0  , 0  ), // #213 {X:xmm, R:xmm, R:xmm|m128|mem, R:u8}
-  ISIGNATURE(4, 1, 1, 0, 133, 82 , 80 , 87 , 0  , 0  ), //      {X:ymm, R:ymm, R:ymm|m256|mem, R:u8}
-  ISIGNATURE(4, 1, 1, 0, 134, 86 , 84 , 87 , 0  , 0  ), //      {X:zmm, R:zmm, R:zmm|m512|mem, R:u8}
-  ISIGNATURE(3, 1, 1, 0, 132, 73 , 77 , 0  , 0  , 0  ), // #216 {X:xmm, R:xmm, R:xmm|m128|mem}
-  ISIGNATURE(3, 1, 1, 0, 133, 82 , 80 , 0  , 0  , 0  ), //      {X:ymm, R:ymm, R:ymm|m256|mem}
-  ISIGNATURE(3, 1, 1, 0, 134, 86 , 84 , 0  , 0  , 0  ), //      {X:zmm, R:zmm, R:zmm|m512|mem}
+  ISIGNATURE(4, 1, 1, 0, 89 , 73 , 77 , 87 , 0  , 0  ), // #213 {X:xmm, R:xmm, R:xmm|m128|mem, R:u8}
+  ISIGNATURE(4, 1, 1, 0, 91 , 82 , 80 , 87 , 0  , 0  ), //      {X:ymm, R:ymm, R:ymm|m256|mem, R:u8}
+  ISIGNATURE(4, 1, 1, 0, 93 , 86 , 84 , 87 , 0  , 0  ), //      {X:zmm, R:zmm, R:zmm|m512|mem, R:u8}
+  ISIGNATURE(3, 1, 1, 0, 89 , 73 , 77 , 0  , 0  , 0  ), // #216 {X:xmm, R:xmm, R:xmm|m128|mem}
+  ISIGNATURE(3, 1, 1, 0, 91 , 82 , 80 , 0  , 0  , 0  ), //      {X:ymm, R:ymm, R:ymm|m256|mem}
+  ISIGNATURE(3, 1, 1, 0, 93 , 86 , 84 , 0  , 0  , 0  ), //      {X:zmm, R:zmm, R:zmm|m512|mem}
   ISIGNATURE(3, 1, 1, 0, 74 , 77 , 87 , 0  , 0  , 0  ), // #219 {W:xmm, R:xmm|m128|mem, R:u8}
   ISIGNATURE(3, 1, 1, 0, 79 , 80 , 87 , 0  , 0  , 0  ), //      {W:ymm, R:ymm|m256|mem, R:u8}
   ISIGNATURE(3, 1, 1, 0, 83 , 84 , 87 , 0  , 0  , 0  ), //      {W:zmm, R:zmm|m512|mem, R:u8}
   ISIGNATURE(2, 1, 1, 0, 74 , 75 , 0  , 0  , 0  , 0  ), // #222 {W:xmm, R:xmm|m64|mem}
   ISIGNATURE(2, 1, 1, 0, 79 , 80 , 0  , 0  , 0  , 0  ), //      {W:ymm, R:ymm|m256|mem}
   ISIGNATURE(2, 1, 1, 0, 83 , 84 , 0  , 0  , 0  , 0  ), //      {W:zmm, R:zmm|m512|mem}
-  ISIGNATURE(2, 1, 1, 0, 112, 73 , 0  , 0  , 0  , 0  ), // #225 {W:m128|mem, R:xmm}
-  ISIGNATURE(2, 1, 1, 0, 113, 82 , 0  , 0  , 0  , 0  ), //      {W:m256|mem, R:ymm}
+  ISIGNATURE(2, 1, 1, 0, 115, 73 , 0  , 0  , 0  , 0  ), // #225 {W:m128|mem, R:xmm}
+  ISIGNATURE(2, 1, 1, 0, 116, 82 , 0  , 0  , 0  , 0  ), //      {W:m256|mem, R:ymm}
   ISIGNATURE(2, 1, 1, 0, 135, 86 , 0  , 0  , 0  , 0  ), //      {W:m512|mem, R:zmm}
-  ISIGNATURE(2, 1, 1, 0, 74 , 114, 0  , 0  , 0  , 0  ), // #228 {W:xmm, R:m128|mem}
-  ISIGNATURE(2, 1, 1, 0, 79 , 115, 0  , 0  , 0  , 0  ), //      {W:ymm, R:m256|mem}
+  ISIGNATURE(2, 1, 1, 0, 74 , 117, 0  , 0  , 0  , 0  ), // #228 {W:xmm, R:m128|mem}
+  ISIGNATURE(2, 1, 1, 0, 79 , 118, 0  , 0  , 0  , 0  ), //      {W:ymm, R:m256|mem}
   ISIGNATURE(2, 1, 1, 0, 83 , 136, 0  , 0  , 0  , 0  ), //      {W:zmm, R:m512|mem}
   ISIGNATURE(2, 0, 1, 0, 7  , 73 , 0  , 0  , 0  , 0  ), // #231 {W:r64|m64|mem, R:xmm}
   ISIGNATURE(2, 1, 1, 0, 74 , 137, 0  , 0  , 0  , 0  ), //      {W:xmm, R:xmm|m64|mem|r64}
@@ -3349,12 +3350,12 @@ const X86Inst::ISignature X86InstDB::iSignatureData[] = {
   ISIGNATURE(2, 1, 1, 0, 67 , 73 , 0  , 0  , 0  , 0  ), // #237 {W:m32|mem, R:xmm}
   ISIGNATURE(2, 1, 1, 0, 74 , 64 , 0  , 0  , 0  , 0  ), //      {W:xmm, R:m32|mem}
   ISIGNATURE(3, 1, 1, 0, 74 , 73 , 73 , 0  , 0  , 0  ), //      {W:xmm, R:xmm, R:xmm}
-  ISIGNATURE(4, 1, 1, 0, 128, 73 , 77 , 87 , 0  , 0  ), // #240 {W:k, R:xmm, R:xmm|m128|mem, R:u8}
-  ISIGNATURE(4, 1, 1, 0, 128, 82 , 80 , 87 , 0  , 0  ), //      {W:k, R:ymm, R:ymm|m256|mem, R:u8}
-  ISIGNATURE(4, 1, 1, 0, 128, 86 , 84 , 87 , 0  , 0  ), //      {W:k, R:zmm, R:zmm|m512|mem, R:u8}
-  ISIGNATURE(3, 1, 1, 0, 126, 73 , 77 , 0  , 0  , 0  ), // #243 {W:xmm|k, R:xmm, R:xmm|m128|mem}
-  ISIGNATURE(3, 1, 1, 0, 127, 82 , 80 , 0  , 0  , 0  ), //      {W:ymm|k, R:ymm, R:ymm|m256|mem}
-  ISIGNATURE(3, 1, 1, 0, 128, 86 , 84 , 0  , 0  , 0  ), //      {W:k, R:zmm, R:zmm|m512|mem}
+  ISIGNATURE(4, 1, 1, 0, 131, 73 , 77 , 87 , 0  , 0  ), // #240 {W:k, R:xmm, R:xmm|m128|mem, R:u8}
+  ISIGNATURE(4, 1, 1, 0, 131, 82 , 80 , 87 , 0  , 0  ), //      {W:k, R:ymm, R:ymm|m256|mem, R:u8}
+  ISIGNATURE(4, 1, 1, 0, 131, 86 , 84 , 87 , 0  , 0  ), //      {W:k, R:zmm, R:zmm|m512|mem, R:u8}
+  ISIGNATURE(3, 1, 1, 0, 129, 73 , 77 , 0  , 0  , 0  ), // #243 {W:xmm|k, R:xmm, R:xmm|m128|mem}
+  ISIGNATURE(3, 1, 1, 0, 130, 82 , 80 , 0  , 0  , 0  ), //      {W:ymm|k, R:ymm, R:ymm|m256|mem}
+  ISIGNATURE(3, 1, 1, 0, 131, 86 , 84 , 0  , 0  , 0  ), //      {W:k, R:zmm, R:zmm|m512|mem}
   ISIGNATURE(2, 1, 1, 0, 138, 73 , 0  , 0  , 0  , 0  ), // #246 {W:xmm|m32|mem, R:xmm}
   ISIGNATURE(2, 1, 1, 0, 76 , 82 , 0  , 0  , 0  , 0  ), //      {W:xmm|m64|mem, R:ymm}
   ISIGNATURE(2, 1, 1, 0, 78 , 86 , 0  , 0  , 0  , 0  ), //      {W:xmm|m128|mem, R:zmm}
@@ -3379,9 +3380,9 @@ const X86Inst::ISignature X86InstDB::iSignatureData[] = {
   ISIGNATURE(2, 1, 1, 0, 146, 73 , 0  , 0  , 0  , 0  ), // #267 {W:vm64x, R:xmm}
   ISIGNATURE(2, 1, 1, 0, 147, 82 , 0  , 0  , 0  , 0  ), //      {W:vm64y, R:ymm}
   ISIGNATURE(2, 1, 1, 0, 148, 86 , 0  , 0  , 0  , 0  ), //      {W:vm64z, R:zmm}
-  ISIGNATURE(3, 1, 1, 0, 128, 73 , 77 , 0  , 0  , 0  ), // #270 {W:k, R:xmm, R:xmm|m128|mem}
-  ISIGNATURE(3, 1, 1, 0, 128, 82 , 80 , 0  , 0  , 0  ), //      {W:k, R:ymm, R:ymm|m256|mem}
-  ISIGNATURE(3, 1, 1, 0, 128, 86 , 84 , 0  , 0  , 0  ), //      {W:k, R:zmm, R:zmm|m512|mem}
+  ISIGNATURE(3, 1, 1, 0, 131, 73 , 77 , 0  , 0  , 0  ), // #270 {W:k, R:xmm, R:xmm|m128|mem}
+  ISIGNATURE(3, 1, 1, 0, 131, 82 , 80 , 0  , 0  , 0  ), //      {W:k, R:ymm, R:ymm|m256|mem}
+  ISIGNATURE(3, 1, 1, 0, 131, 86 , 84 , 0  , 0  , 0  ), //      {W:k, R:zmm, R:zmm|m512|mem}
   ISIGNATURE(3, 1, 1, 0, 13 , 6  , 43 , 0  , 0  , 0  ), // #273 {W:r32, R:r32, R:r32|m32|mem}
   ISIGNATURE(3, 0, 1, 0, 19 , 27 , 16 , 0  , 0  , 0  ), //      {W:r64, R:r64, R:r64|m64|mem}
   ISIGNATURE(3, 1, 1, 0, 13 , 43 , 6  , 0  , 0  , 0  ), // #275 {W:r32, R:r32|m32|mem, R:r32}
@@ -3398,34 +3399,34 @@ const X86Inst::ISignature X86InstDB::iSignatureData[] = {
   ISIGNATURE(2, 0, 1, 0, 44 , 155, 0  , 0  , 0  , 0  ), //      {X:r64, R:r8lo|r8hi|m8|r64|m64}
   ISIGNATURE(1, 1, 0, 0, 156, 0  , 0  , 0  , 0  , 0  ), // #287 {X:r16|r32}
   ISIGNATURE(1, 1, 1, 0, 49 , 0  , 0  , 0  , 0  , 0  ), // #288 {X:r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem}
-  ISIGNATURE(3, 1, 1, 0, 132, 87 , 87 , 0  , 0  , 0  ), // #289 {X:xmm, R:u8, R:u8}
-  ISIGNATURE(2, 1, 1, 0, 132, 73 , 0  , 0  , 0  , 0  ), //      {X:xmm, R:xmm}
+  ISIGNATURE(3, 1, 1, 0, 89 , 87 , 87 , 0  , 0  , 0  ), // #289 {X:xmm, R:u8, R:u8}
+  ISIGNATURE(2, 1, 1, 0, 89 , 73 , 0  , 0  , 0  , 0  ), //      {X:xmm, R:xmm}
   ISIGNATURE(0, 1, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #291 {}
-  ISIGNATURE(1, 1, 1, 0, 120, 0  , 0  , 0  , 0  , 0  ), // #292 {X:fp}
+  ISIGNATURE(1, 1, 1, 0, 123, 0  , 0  , 0  , 0  , 0  ), // #292 {X:fp}
   ISIGNATURE(0, 1, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #293 {}
   ISIGNATURE(1, 1, 1, 0, 157, 0  , 0  , 0  , 0  , 0  ), //      {R:m32|m64|fp}
   ISIGNATURE(0, 1, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #295 {}
-  ISIGNATURE(1, 1, 1, 0, 119, 0  , 0  , 0  , 0  , 0  ), // #296 {R:fp}
-  ISIGNATURE(2, 1, 1, 0, 132, 73 , 0  , 0  , 0  , 0  ), // #297 {X:xmm, R:xmm}
-  ISIGNATURE(4, 1, 1, 0, 132, 73 , 87 , 87 , 0  , 0  ), //      {X:xmm, R:xmm, R:u8, R:u8}
-  ISIGNATURE(2, 1, 0, 0, 6  , 114, 0  , 0  , 0  , 0  ), // #299 {R:r32, R:m128|mem}
-  ISIGNATURE(2, 0, 1, 0, 27 , 114, 0  , 0  , 0  , 0  ), //      {R:r64, R:m128|mem}
+  ISIGNATURE(1, 1, 1, 0, 122, 0  , 0  , 0  , 0  , 0  ), // #296 {R:fp}
+  ISIGNATURE(2, 1, 1, 0, 89 , 73 , 0  , 0  , 0  , 0  ), // #297 {X:xmm, R:xmm}
+  ISIGNATURE(4, 1, 1, 0, 89 , 73 , 87 , 87 , 0  , 0  ), //      {X:xmm, R:xmm, R:u8, R:u8}
+  ISIGNATURE(2, 1, 0, 0, 6  , 117, 0  , 0  , 0  , 0  ), // #299 {R:r32, R:m128|mem}
+  ISIGNATURE(2, 0, 1, 0, 27 , 117, 0  , 0  , 0  , 0  ), //      {R:r64, R:m128|mem}
   ISIGNATURE(2, 1, 0, 1, 158, 159, 0  , 0  , 0  , 0  ), // #301 {R:<cx|ecx>, R:rel8}
   ISIGNATURE(2, 0, 1, 1, 160, 159, 0  , 0  , 0  , 0  ), //      {R:<ecx|rcx>, R:rel8}
   ISIGNATURE(1, 1, 1, 0, 161, 0  , 0  , 0  , 0  , 0  ), // #303 {R:rel8|rel32|r64|m64|mem}
   ISIGNATURE(1, 1, 0, 0, 43 , 0  , 0  , 0  , 0  , 0  ), //      {R:r32|m32|mem}
-  ISIGNATURE(2, 1, 1, 0, 128, 162, 0  , 0  , 0  , 0  ), // #305 {W:k, R:k|m8|mem|r32|r64|r8lo|r8hi|r16}
+  ISIGNATURE(2, 1, 1, 0, 131, 162, 0  , 0  , 0  , 0  ), // #305 {W:k, R:k|m8|mem|r32|r64|r8lo|r8hi|r16}
   ISIGNATURE(2, 1, 1, 0, 163, 164, 0  , 0  , 0  , 0  ), //      {W:m8|mem|r32|r64|r8lo|r8hi|r16, R:k}
-  ISIGNATURE(2, 1, 1, 0, 128, 165, 0  , 0  , 0  , 0  ), // #307 {W:k, R:k|m32|mem|r32|r64}
+  ISIGNATURE(2, 1, 1, 0, 131, 165, 0  , 0  , 0  , 0  ), // #307 {W:k, R:k|m32|mem|r32|r64}
   ISIGNATURE(2, 1, 1, 0, 166, 164, 0  , 0  , 0  , 0  ), //      {W:m32|mem|r32|r64, R:k}
-  ISIGNATURE(2, 1, 1, 0, 128, 167, 0  , 0  , 0  , 0  ), // #309 {W:k, R:k|m64|mem|r64}
+  ISIGNATURE(2, 1, 1, 0, 131, 167, 0  , 0  , 0  , 0  ), // #309 {W:k, R:k|m64|mem|r64}
   ISIGNATURE(2, 1, 1, 0, 7  , 164, 0  , 0  , 0  , 0  ), //      {W:m64|mem|r64, R:k}
-  ISIGNATURE(2, 1, 1, 0, 128, 168, 0  , 0  , 0  , 0  ), // #311 {W:k, R:k|m16|mem|r32|r64|r16}
+  ISIGNATURE(2, 1, 1, 0, 131, 168, 0  , 0  , 0  , 0  ), // #311 {W:k, R:k|m16|mem|r32|r64|r16}
   ISIGNATURE(2, 1, 1, 0, 169, 164, 0  , 0  , 0  , 0  ), //      {W:m16|mem|r32|r64|r16, R:k}
   ISIGNATURE(2, 1, 1, 0, 59 , 12 , 0  , 0  , 0  , 0  ), // #313 {W:r16, R:r16|m16|mem}
   ISIGNATURE(2, 1, 1, 0, 13 , 170, 0  , 0  , 0  , 0  ), //      {W:r32, R:r32|m16|mem|r16}
   ISIGNATURE(2, 1, 0, 0, 41 , 64 , 0  , 0  , 0  , 0  ), // #315 {X:r16, R:m32|mem}
-  ISIGNATURE(2, 1, 0, 0, 42 , 123, 0  , 0  , 0  , 0  ), //      {X:r32, R:m48|mem}
+  ISIGNATURE(2, 1, 0, 0, 42 , 126, 0  , 0  , 0  , 0  ), //      {X:r32, R:m48|mem}
   ISIGNATURE(2, 1, 0, 1, 171, 159, 0  , 0  , 0  , 0  ), // #317 {X:<cx|ecx>, R:rel8}
   ISIGNATURE(2, 0, 1, 1, 172, 159, 0  , 0  , 0  , 0  ), //      {X:<ecx|rcx>, R:rel8}
   ISIGNATURE(2, 1, 1, 0, 59 , 12 , 0  , 0  , 0  , 0  ), // #319 {W:r16, R:r16|m16|mem}
@@ -3441,17 +3442,17 @@ const X86Inst::ISignature X86InstDB::iSignatureData[] = {
   ISIGNATURE(4, 1, 1, 1, 13 , 13 , 43 , 178, 0  , 0  ), // #329 {W:r32, W:r32, R:r32|m32|mem, R:<edx>}
   ISIGNATURE(4, 0, 1, 1, 19 , 19 , 16 , 179, 0  , 0  ), //      {W:r64, W:r64, R:r64|m64|mem, R:<rdx>}
   ISIGNATURE(0, 1, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #331 {}
-  ISIGNATURE(1, 1, 1, 0, 96 , 0  , 0  , 0  , 0  , 0  ), //      {R:r16|m16|r32|m32}
+  ISIGNATURE(1, 1, 1, 0, 99 , 0  , 0  , 0  , 0  , 0  ), //      {R:r16|m16|r32|m32}
   ISIGNATURE(2, 1, 1, 0, 69 , 180, 0  , 0  , 0  , 0  ), // #333 {W:mm, R:mm|m64|mem}
   ISIGNATURE(2, 1, 1, 0, 74 , 77 , 0  , 0  , 0  , 0  ), //      {W:xmm, R:xmm|m128|mem}
   ISIGNATURE(2, 1, 1, 0, 181, 180, 0  , 0  , 0  , 0  ), // #335 {X:mm, R:mm|m64|mem}
-  ISIGNATURE(2, 1, 1, 0, 132, 77 , 0  , 0  , 0  , 0  ), // #336 {X:xmm, R:xmm|m128|mem}
+  ISIGNATURE(2, 1, 1, 0, 89 , 77 , 0  , 0  , 0  , 0  ), // #336 {X:xmm, R:xmm|m128|mem}
   ISIGNATURE(3, 1, 1, 0, 181, 180, 87 , 0  , 0  , 0  ), // #337 {X:mm, R:mm|m64|mem, R:u8}
-  ISIGNATURE(3, 1, 1, 0, 132, 77 , 87 , 0  , 0  , 0  ), // #338 {X:xmm, R:xmm|m128|mem, R:u8}
+  ISIGNATURE(3, 1, 1, 0, 89 , 77 , 87 , 0  , 0  , 0  ), // #338 {X:xmm, R:xmm|m128|mem, R:u8}
   ISIGNATURE(3, 1, 1, 0, 173, 72 , 87 , 0  , 0  , 0  ), // #339 {W:r32|r64, R:mm, R:u8}
   ISIGNATURE(3, 1, 1, 0, 169, 73 , 87 , 0  , 0  , 0  ), // #340 {W:r32|r64|m16|mem|r16, R:xmm, R:u8}
   ISIGNATURE(2, 1, 1, 0, 181, 182, 0  , 0  , 0  , 0  ), // #341 {X:mm, R:u8|mm|m64|mem}
-  ISIGNATURE(2, 1, 1, 0, 132, 88 , 0  , 0  , 0  , 0  ), //      {X:xmm, R:u8|xmm|m128|mem}
+  ISIGNATURE(2, 1, 1, 0, 89 , 88 , 0  , 0  , 0  , 0  ), //      {X:xmm, R:u8|xmm|m128|mem}
   ISIGNATURE(0, 1, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #343 {}
   ISIGNATURE(1, 1, 1, 0, 183, 0  , 0  , 0  , 0  , 0  ), //      {R:u16}
   ISIGNATURE(3, 1, 1, 0, 13 , 43 , 87 , 0  , 0  , 0  ), // #345 {W:r32, R:r32|m32|mem, R:u8}
@@ -3494,39 +3495,39 @@ const X86Inst::ISignature X86InstDB::iSignatureData[] = {
   ISIGNATURE(2, 1, 1, 0, 144, 86 , 0  , 0  , 0  , 0  ), //      {W:vm32y, R:zmm}
   ISIGNATURE(1, 1, 0, 1, 50 , 0  , 0  , 0  , 0  , 0  ), // #383 {X:<ax>}
   ISIGNATURE(2, 1, 0, 1, 50 , 87 , 0  , 0  , 0  , 0  ), // #384 {X:<ax>, R:u8}
-  ISIGNATURE(2, 1, 1, 0, 132, 75 , 0  , 0  , 0  , 0  ), // #385 {X:xmm, R:xmm|m64|mem}
-  ISIGNATURE(2, 1, 1, 0, 132, 140, 0  , 0  , 0  , 0  ), // #386 {X:xmm, R:xmm|m32|mem}
+  ISIGNATURE(2, 1, 1, 0, 89 , 75 , 0  , 0  , 0  , 0  ), // #385 {X:xmm, R:xmm|m64|mem}
+  ISIGNATURE(2, 1, 1, 0, 89 , 140, 0  , 0  , 0  , 0  ), // #386 {X:xmm, R:xmm|m32|mem}
   ISIGNATURE(2, 1, 0, 0, 36 , 37 , 0  , 0  , 0  , 0  ), // #387 {X:r16|m16|mem, R:r16}
-  ISIGNATURE(3, 1, 1, 1, 132, 77 , 192, 0  , 0  , 0  ), // #388 {X:xmm, R:xmm|m128|mem, R:<xmm0>}
+  ISIGNATURE(3, 1, 1, 1, 89 , 77 , 192, 0  , 0  , 0  ), // #388 {X:xmm, R:xmm|m128|mem, R:<xmm0>}
   ISIGNATURE(2, 1, 1, 0, 150, 193, 0  , 0  , 0  , 0  ), // #389 {W:bnd, R:mib}
   ISIGNATURE(2, 1, 1, 0, 150, 194, 0  , 0  , 0  , 0  ), // #390 {W:bnd, R:mem}
   ISIGNATURE(2, 1, 1, 0, 195, 149, 0  , 0  , 0  , 0  ), // #391 {W:mib, R:bnd}
   ISIGNATURE(1, 1, 1, 0, 196, 0  , 0  , 0  , 0  , 0  ), // #392 {X:r32|r64}
   ISIGNATURE(1, 1, 1, 1, 50 , 0  , 0  , 0  , 0  , 0  ), // #393 {X:<ax>}
-  ISIGNATURE(2, 1, 1, 2, 52 , 100, 0  , 0  , 0  , 0  ), // #394 {W:<edx>, R:<eax>}
+  ISIGNATURE(2, 1, 1, 2, 52 , 103, 0  , 0  , 0  , 0  ), // #394 {W:<edx>, R:<eax>}
   ISIGNATURE(1, 0, 1, 1, 55 , 0  , 0  , 0  , 0  , 0  ), // #395 {X:<rax>}
   ISIGNATURE(1, 1, 1, 0, 194, 0  , 0  , 0  , 0  , 0  ), // #396 {R:mem}
   ISIGNATURE(1, 1, 1, 1, 197, 0  , 0  , 0  , 0  , 0  ), // #397 {R:<ds:[zax]>}
   ISIGNATURE(2, 1, 1, 2, 198, 199, 0  , 0  , 0  , 0  ), // #398 {X:<ds:[zsi]>, X:<es:[zdi]>}
-  ISIGNATURE(3, 1, 1, 0, 132, 75 , 87 , 0  , 0  , 0  ), // #399 {X:xmm, R:xmm|m64|mem, R:u8}
-  ISIGNATURE(3, 1, 1, 0, 132, 140, 87 , 0  , 0  , 0  ), // #400 {X:xmm, R:xmm|m32|mem, R:u8}
-  ISIGNATURE(5, 0, 1, 4, 200, 104, 55 , 201, 202, 0  ), // #401 {X:m128|mem, X:<rdx>, X:<rax>, R:<rcx>, R:<rbx>}
-  ISIGNATURE(5, 1, 1, 4, 203, 103, 53 , 204, 205, 0  ), // #402 {X:m64|mem, X:<edx>, X:<eax>, R:<ecx>, R:<ebx>}
+  ISIGNATURE(3, 1, 1, 0, 89 , 75 , 87 , 0  , 0  , 0  ), // #399 {X:xmm, R:xmm|m64|mem, R:u8}
+  ISIGNATURE(3, 1, 1, 0, 89 , 140, 87 , 0  , 0  , 0  ), // #400 {X:xmm, R:xmm|m32|mem, R:u8}
+  ISIGNATURE(5, 0, 1, 4, 200, 107, 55 , 201, 202, 0  ), // #401 {X:m128|mem, X:<rdx>, X:<rax>, R:<rcx>, R:<rbx>}
+  ISIGNATURE(5, 1, 1, 4, 203, 106, 53 , 204, 205, 0  ), // #402 {X:m64|mem, X:<edx>, X:<eax>, R:<ecx>, R:<ebx>}
   ISIGNATURE(2, 1, 1, 0, 73 , 75 , 0  , 0  , 0  , 0  ), // #403 {R:xmm, R:xmm|m64|mem}
   ISIGNATURE(2, 1, 1, 0, 73 , 140, 0  , 0  , 0  , 0  ), // #404 {R:xmm, R:xmm|m32|mem}
   ISIGNATURE(4, 1, 1, 4, 53 , 206, 207, 52 , 0  , 0  ), // #405 {X:<eax>, W:<ebx>, X:<ecx>, W:<edx>}
-  ISIGNATURE(2, 0, 1, 2, 54 , 101, 0  , 0  , 0  , 0  ), // #406 {W:<rdx>, R:<rax>}
+  ISIGNATURE(2, 0, 1, 2, 54 , 104, 0  , 0  , 0  , 0  ), // #406 {W:<rdx>, R:<rax>}
   ISIGNATURE(2, 1, 1, 0, 69 , 77 , 0  , 0  , 0  , 0  ), // #407 {W:mm, R:xmm|m128|mem}
   ISIGNATURE(2, 1, 1, 0, 74 , 180, 0  , 0  , 0  , 0  ), // #408 {W:xmm, R:mm|m64|mem}
   ISIGNATURE(2, 1, 1, 0, 69 , 75 , 0  , 0  , 0  , 0  ), // #409 {W:mm, R:xmm|m64|mem}
   ISIGNATURE(2, 1, 1, 0, 173, 75 , 0  , 0  , 0  , 0  ), // #410 {W:r32|r64, R:xmm|m64|mem}
   ISIGNATURE(2, 1, 1, 0, 74 , 208, 0  , 0  , 0  , 0  ), // #411 {W:xmm, R:r32|m32|mem|r64|m64}
   ISIGNATURE(2, 1, 1, 0, 173, 140, 0  , 0  , 0  , 0  ), // #412 {W:r32|r64, R:xmm|m32|mem}
-  ISIGNATURE(2, 1, 1, 2, 51 , 99 , 0  , 0  , 0  , 0  ), // #413 {W:<dx>, R:<ax>}
+  ISIGNATURE(2, 1, 1, 2, 51 , 102, 0  , 0  , 0  , 0  ), // #413 {W:<dx>, R:<ax>}
   ISIGNATURE(1, 1, 1, 1, 53 , 0  , 0  , 0  , 0  , 0  ), // #414 {X:<eax>}
   ISIGNATURE(2, 1, 1, 0, 183, 87 , 0  , 0  , 0  , 0  ), // #415 {R:u16, R:u8}
   ISIGNATURE(3, 1, 1, 0, 166, 73 , 87 , 0  , 0  , 0  ), // #416 {W:r32|m32|mem|r64, R:xmm, R:u8}
-  ISIGNATURE(1, 1, 1, 0, 124, 0  , 0  , 0  , 0  , 0  ), // #417 {R:m80|mem}
+  ISIGNATURE(1, 1, 1, 0, 127, 0  , 0  , 0  , 0  , 0  ), // #417 {R:m80|mem}
   ISIGNATURE(1, 1, 1, 0, 209, 0  , 0  , 0  , 0  , 0  ), // #418 {W:m80|mem}
   ISIGNATURE(1, 1, 1, 0, 210, 0  , 0  , 0  , 0  , 0  ), // #419 {R:m16|m32}
   ISIGNATURE(1, 1, 1, 0, 211, 0  , 0  , 0  , 0  , 0  ), // #420 {R:m16|m32|m64}
@@ -3544,46 +3545,46 @@ const X86Inst::ISignature X86InstDB::iSignatureData[] = {
   ISIGNATURE(2, 1, 1, 0, 219, 220, 0  , 0  , 0  , 0  ), // #432 {W:al|ax|eax, R:u8|dx}
   ISIGNATURE(2, 1, 1, 0, 221, 222, 0  , 0  , 0  , 0  ), // #433 {W:es:[zdi], R:dx}
   ISIGNATURE(1, 1, 1, 0, 87 , 0  , 0  , 0  , 0  , 0  ), // #434 {R:u8}
-  ISIGNATURE(0, 0, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #435 {}
-  ISIGNATURE(1, 1, 1, 0, 223, 0  , 0  , 0  , 0  , 0  ), // #436 {R:rel8|rel32}
-  ISIGNATURE(1, 1, 1, 0, 159, 0  , 0  , 0  , 0  , 0  ), // #437 {R:rel8}
-  ISIGNATURE(3, 1, 1, 0, 128, 164, 164, 0  , 0  , 0  ), // #438 {W:k, R:k, R:k}
-  ISIGNATURE(2, 1, 1, 0, 128, 164, 0  , 0  , 0  , 0  ), // #439 {W:k, R:k}
-  ISIGNATURE(2, 1, 1, 0, 164, 164, 0  , 0  , 0  , 0  ), // #440 {R:k, R:k}
-  ISIGNATURE(3, 1, 1, 0, 128, 164, 87 , 0  , 0  , 0  ), // #441 {W:k, R:k, R:u8}
-  ISIGNATURE(1, 1, 1, 1, 224, 0  , 0  , 0  , 0  , 0  ), // #442 {W:<ah>}
-  ISIGNATURE(1, 1, 1, 0, 64 , 0  , 0  , 0  , 0  , 0  ), // #443 {R:m32|mem}
-  ISIGNATURE(2, 1, 1, 0, 177, 225, 0  , 0  , 0  , 0  ), // #444 {W:r16|r32|r64, R:mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024}
-  ISIGNATURE(1, 1, 1, 0, 226, 0  , 0  , 0  , 0  , 0  ), // #445 {R:r16|m16|mem|r32|r64}
-  ISIGNATURE(2, 1, 1, 2, 227, 198, 0  , 0  , 0  , 0  ), // #446 {W:<al|ax|eax|rax>, X:<ds:[zsi]>}
-  ISIGNATURE(3, 1, 1, 1, 132, 73 , 228, 0  , 0  , 0  ), // #447 {X:xmm, R:xmm, R:<ds:[zdi]>}
-  ISIGNATURE(3, 1, 1, 1, 181, 72 , 228, 0  , 0  , 0  ), // #448 {X:mm, R:mm, R:<ds:[zdi]>}
-  ISIGNATURE(3, 1, 1, 3, 197, 204, 178, 0  , 0  , 0  ), // #449 {R:<ds:[zax]>, R:<ecx>, R:<edx>}
-  ISIGNATURE(2, 1, 1, 0, 69 , 73 , 0  , 0  , 0  , 0  ), // #450 {W:mm, R:xmm}
-  ISIGNATURE(2, 1, 1, 0, 74 , 73 , 0  , 0  , 0  , 0  ), // #451 {W:xmm, R:xmm}
-  ISIGNATURE(2, 1, 1, 0, 173, 73 , 0  , 0  , 0  , 0  ), // #452 {W:r32|r64, R:xmm}
-  ISIGNATURE(2, 1, 1, 0, 68 , 72 , 0  , 0  , 0  , 0  ), // #453 {W:m64|mem, R:mm}
-  ISIGNATURE(2, 1, 1, 0, 74 , 72 , 0  , 0  , 0  , 0  ), // #454 {W:xmm, R:mm}
-  ISIGNATURE(2, 1, 1, 2, 199, 198, 0  , 0  , 0  , 0  ), // #455 {X:<es:[zdi]>, X:<ds:[zsi]>}
-  ISIGNATURE(2, 0, 1, 0, 19 , 43 , 0  , 0  , 0  , 0  ), // #456 {W:r64, R:r32|m32|mem}
-  ISIGNATURE(2, 1, 1, 2, 100, 204, 0  , 0  , 0  , 0  ), // #457 {R:<eax>, R:<ecx>}
-  ISIGNATURE(2, 1, 1, 0, 220, 229, 0  , 0  , 0  , 0  ), // #458 {R:u8|dx, R:al|ax|eax}
-  ISIGNATURE(2, 1, 1, 0, 222, 230, 0  , 0  , 0  , 0  ), // #459 {R:dx, R:ds:[zsi]}
-  ISIGNATURE(6, 1, 1, 3, 73 , 77 , 87 , 231, 100, 178), // #460 {R:xmm, R:xmm|m128|mem, R:u8, W:<ecx>, R:<eax>, R:<edx>}
-  ISIGNATURE(6, 1, 1, 3, 73 , 77 , 87 , 232, 100, 178), // #461 {R:xmm, R:xmm|m128|mem, R:u8, W:<xmm0>, R:<eax>, R:<edx>}
-  ISIGNATURE(4, 1, 1, 1, 73 , 77 , 87 , 231, 0  , 0  ), // #462 {R:xmm, R:xmm|m128|mem, R:u8, W:<ecx>}
-  ISIGNATURE(4, 1, 1, 1, 73 , 77 , 87 , 232, 0  , 0  ), // #463 {R:xmm, R:xmm|m128|mem, R:u8, W:<xmm0>}
-  ISIGNATURE(3, 1, 1, 0, 163, 73 , 87 , 0  , 0  , 0  ), // #464 {W:r32|m8|mem|r8lo|r8hi|r16|r64, R:xmm, R:u8}
-  ISIGNATURE(3, 0, 1, 0, 7  , 73 , 87 , 0  , 0  , 0  ), // #465 {W:r64|m64|mem, R:xmm, R:u8}
-  ISIGNATURE(3, 1, 1, 0, 132, 188, 87 , 0  , 0  , 0  ), // #466 {X:xmm, R:r32|m8|mem|r8lo|r8hi|r16|r64, R:u8}
-  ISIGNATURE(3, 1, 1, 0, 132, 175, 87 , 0  , 0  , 0  ), // #467 {X:xmm, R:r32|m32|mem|r64, R:u8}
-  ISIGNATURE(3, 0, 1, 0, 132, 16 , 87 , 0  , 0  , 0  ), // #468 {X:xmm, R:r64|m64|mem, R:u8}
-  ISIGNATURE(3, 1, 1, 0, 233, 226, 87 , 0  , 0  , 0  ), // #469 {X:mm|xmm, R:r32|m16|mem|r16|r64, R:u8}
-  ISIGNATURE(2, 1, 1, 0, 173, 176, 0  , 0  , 0  , 0  ), // #470 {W:r32|r64, R:mm|xmm}
-  ISIGNATURE(0, 1, 0, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #471 {}
+  ISIGNATURE(0, 1, 0, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #435 {}
+  ISIGNATURE(0, 0, 1, 0, 0  , 0  , 0  , 0  , 0  , 0  ), // #436 {}
+  ISIGNATURE(1, 1, 1, 0, 223, 0  , 0  , 0  , 0  , 0  ), // #437 {R:rel8|rel32}
+  ISIGNATURE(1, 1, 1, 0, 159, 0  , 0  , 0  , 0  , 0  ), // #438 {R:rel8}
+  ISIGNATURE(3, 1, 1, 0, 131, 164, 164, 0  , 0  , 0  ), // #439 {W:k, R:k, R:k}
+  ISIGNATURE(2, 1, 1, 0, 131, 164, 0  , 0  , 0  , 0  ), // #440 {W:k, R:k}
+  ISIGNATURE(2, 1, 1, 0, 164, 164, 0  , 0  , 0  , 0  ), // #441 {R:k, R:k}
+  ISIGNATURE(3, 1, 1, 0, 131, 164, 87 , 0  , 0  , 0  ), // #442 {W:k, R:k, R:u8}
+  ISIGNATURE(1, 1, 1, 1, 224, 0  , 0  , 0  , 0  , 0  ), // #443 {W:<ah>}
+  ISIGNATURE(1, 1, 1, 0, 64 , 0  , 0  , 0  , 0  , 0  ), // #444 {R:m32|mem}
+  ISIGNATURE(2, 1, 1, 0, 177, 225, 0  , 0  , 0  , 0  ), // #445 {W:r16|r32|r64, R:mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024}
+  ISIGNATURE(1, 1, 1, 0, 226, 0  , 0  , 0  , 0  , 0  ), // #446 {R:r16|m16|mem|r32|r64}
+  ISIGNATURE(2, 1, 1, 2, 227, 198, 0  , 0  , 0  , 0  ), // #447 {W:<al|ax|eax|rax>, X:<ds:[zsi]>}
+  ISIGNATURE(3, 1, 1, 1, 89 , 73 , 228, 0  , 0  , 0  ), // #448 {X:xmm, R:xmm, R:<ds:[zdi]>}
+  ISIGNATURE(3, 1, 1, 1, 181, 72 , 228, 0  , 0  , 0  ), // #449 {X:mm, R:mm, R:<ds:[zdi]>}
+  ISIGNATURE(3, 1, 1, 3, 197, 204, 178, 0  , 0  , 0  ), // #450 {R:<ds:[zax]>, R:<ecx>, R:<edx>}
+  ISIGNATURE(2, 1, 1, 0, 69 , 73 , 0  , 0  , 0  , 0  ), // #451 {W:mm, R:xmm}
+  ISIGNATURE(2, 1, 1, 0, 74 , 73 , 0  , 0  , 0  , 0  ), // #452 {W:xmm, R:xmm}
+  ISIGNATURE(2, 1, 1, 0, 173, 73 , 0  , 0  , 0  , 0  ), // #453 {W:r32|r64, R:xmm}
+  ISIGNATURE(2, 1, 1, 0, 68 , 72 , 0  , 0  , 0  , 0  ), // #454 {W:m64|mem, R:mm}
+  ISIGNATURE(2, 1, 1, 0, 74 , 72 , 0  , 0  , 0  , 0  ), // #455 {W:xmm, R:mm}
+  ISIGNATURE(2, 1, 1, 2, 199, 198, 0  , 0  , 0  , 0  ), // #456 {X:<es:[zdi]>, X:<ds:[zsi]>}
+  ISIGNATURE(2, 0, 1, 0, 19 , 43 , 0  , 0  , 0  , 0  ), // #457 {W:r64, R:r32|m32|mem}
+  ISIGNATURE(2, 1, 1, 2, 103, 204, 0  , 0  , 0  , 0  ), // #458 {R:<eax>, R:<ecx>}
+  ISIGNATURE(2, 1, 1, 0, 220, 229, 0  , 0  , 0  , 0  ), // #459 {R:u8|dx, R:al|ax|eax}
+  ISIGNATURE(2, 1, 1, 0, 222, 230, 0  , 0  , 0  , 0  ), // #460 {R:dx, R:ds:[zsi]}
+  ISIGNATURE(6, 1, 1, 3, 73 , 77 , 87 , 231, 103, 178), // #461 {R:xmm, R:xmm|m128|mem, R:u8, W:<ecx>, R:<eax>, R:<edx>}
+  ISIGNATURE(6, 1, 1, 3, 73 , 77 , 87 , 232, 103, 178), // #462 {R:xmm, R:xmm|m128|mem, R:u8, W:<xmm0>, R:<eax>, R:<edx>}
+  ISIGNATURE(4, 1, 1, 1, 73 , 77 , 87 , 231, 0  , 0  ), // #463 {R:xmm, R:xmm|m128|mem, R:u8, W:<ecx>}
+  ISIGNATURE(4, 1, 1, 1, 73 , 77 , 87 , 232, 0  , 0  ), // #464 {R:xmm, R:xmm|m128|mem, R:u8, W:<xmm0>}
+  ISIGNATURE(3, 1, 1, 0, 163, 73 , 87 , 0  , 0  , 0  ), // #465 {W:r32|m8|mem|r8lo|r8hi|r16|r64, R:xmm, R:u8}
+  ISIGNATURE(3, 0, 1, 0, 7  , 73 , 87 , 0  , 0  , 0  ), // #466 {W:r64|m64|mem, R:xmm, R:u8}
+  ISIGNATURE(3, 1, 1, 0, 89 , 188, 87 , 0  , 0  , 0  ), // #467 {X:xmm, R:r32|m8|mem|r8lo|r8hi|r16|r64, R:u8}
+  ISIGNATURE(3, 1, 1, 0, 89 , 175, 87 , 0  , 0  , 0  ), // #468 {X:xmm, R:r32|m32|mem|r64, R:u8}
+  ISIGNATURE(3, 0, 1, 0, 89 , 16 , 87 , 0  , 0  , 0  ), // #469 {X:xmm, R:r64|m64|mem, R:u8}
+  ISIGNATURE(3, 1, 1, 0, 233, 226, 87 , 0  , 0  , 0  ), // #470 {X:mm|xmm, R:r32|m16|mem|r16|r64, R:u8}
+  ISIGNATURE(2, 1, 1, 0, 173, 176, 0  , 0  , 0  , 0  ), // #471 {W:r32|r64, R:mm|xmm}
   ISIGNATURE(3, 1, 1, 0, 69 , 180, 87 , 0  , 0  , 0  ), // #472 {W:mm, R:mm|m64|mem, R:u8}
-  ISIGNATURE(2, 1, 1, 0, 132, 87 , 0  , 0  , 0  , 0  ), // #473 {X:xmm, R:u8}
-  ISIGNATURE(2, 1, 1, 0, 49 , 125, 0  , 0  , 0  , 0  ), // #474 {X:r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, R:cl|u8}
+  ISIGNATURE(2, 1, 1, 0, 89 , 87 , 0  , 0  , 0  , 0  ), // #473 {X:xmm, R:u8}
+  ISIGNATURE(2, 1, 1, 0, 49 , 128, 0  , 0  , 0  , 0  ), // #474 {X:r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, R:cl|u8}
   ISIGNATURE(1, 0, 1, 0, 173, 0  , 0  , 0  , 0  , 0  ), // #475 {W:r32|r64}
   ISIGNATURE(3, 1, 1, 3, 52 , 234, 204, 0  , 0  , 0  ), // #476 {W:<edx>, W:<eax>, R:<ecx>}
   ISIGNATURE(1, 1, 1, 0, 177, 0  , 0  , 0  , 0  , 0  ), // #477 {W:r16|r32|r64}
@@ -3597,618 +3598,49 @@ const X86Inst::ISignature X86InstDB::iSignatureData[] = {
   ISIGNATURE(1, 1, 1, 0, 169, 0  , 0  , 0  , 0  , 0  ), // #485 {W:r16|m16|mem|r32|r64}
   ISIGNATURE(1, 1, 1, 0, 67 , 0  , 0  , 0  , 0  , 0  ), // #486 {W:m32|mem}
   ISIGNATURE(2, 1, 1, 2, 199, 236, 0  , 0  , 0  , 0  ), // #487 {X:<es:[zdi]>, R:<al|ax|eax|rax>}
-  ISIGNATURE(6, 1, 1, 0, 134, 86 , 86 , 86 , 86 , 114), // #488 {X:zmm, R:zmm, R:zmm, R:zmm, R:zmm, R:m128|mem}
+  ISIGNATURE(6, 1, 1, 0, 93 , 86 , 86 , 86 , 86 , 117), // #488 {X:zmm, R:zmm, R:zmm, R:zmm, R:zmm, R:m128|mem}
   ISIGNATURE(3, 1, 1, 0, 74 , 73 , 75 , 0  , 0  , 0  ), // #489 {W:xmm, R:xmm, R:xmm|m64|mem}
   ISIGNATURE(3, 1, 1, 0, 74 , 73 , 140, 0  , 0  , 0  ), // #490 {W:xmm, R:xmm, R:xmm|m32|mem}
-  ISIGNATURE(2, 1, 1, 0, 79 , 114, 0  , 0  , 0  , 0  ), // #491 {W:ymm, R:m128|mem}
+  ISIGNATURE(2, 1, 1, 0, 79 , 117, 0  , 0  , 0  , 0  ), // #491 {W:ymm, R:m128|mem}
   ISIGNATURE(2, 1, 1, 0, 237, 75 , 0  , 0  , 0  , 0  ), // #492 {W:ymm|zmm, R:xmm|m64|mem}
-  ISIGNATURE(2, 1, 1, 0, 237, 114, 0  , 0  , 0  , 0  ), // #493 {W:ymm|zmm, R:m128|mem}
-  ISIGNATURE(2, 1, 1, 0, 83 , 115, 0  , 0  , 0  , 0  ), // #494 {W:zmm, R:m256|mem}
+  ISIGNATURE(2, 1, 1, 0, 237, 117, 0  , 0  , 0  , 0  ), // #493 {W:ymm|zmm, R:m128|mem}
+  ISIGNATURE(2, 1, 1, 0, 83 , 118, 0  , 0  , 0  , 0  ), // #494 {W:zmm, R:m256|mem}
   ISIGNATURE(2, 1, 1, 0, 185, 75 , 0  , 0  , 0  , 0  ), // #495 {W:xmm|ymm|zmm, R:xmm|m64|mem}
-  ISIGNATURE(4, 1, 1, 0, 126, 73 , 75 , 87 , 0  , 0  ), // #496 {W:xmm|k, R:xmm, R:xmm|m64|mem, R:u8}
-  ISIGNATURE(4, 1, 1, 0, 126, 73 , 140, 87 , 0  , 0  ), // #497 {W:xmm|k, R:xmm, R:xmm|m32|mem, R:u8}
+  ISIGNATURE(4, 1, 1, 0, 129, 73 , 75 , 87 , 0  , 0  ), // #496 {W:xmm|k, R:xmm, R:xmm|m64|mem, R:u8}
+  ISIGNATURE(4, 1, 1, 0, 129, 73 , 140, 87 , 0  , 0  ), // #497 {W:xmm|k, R:xmm, R:xmm|m32|mem, R:u8}
   ISIGNATURE(3, 1, 1, 0, 74 , 73 , 208, 0  , 0  , 0  ), // #498 {W:xmm, R:xmm, R:r32|m32|mem|r64|m64}
   ISIGNATURE(3, 1, 1, 0, 78 , 238, 87 , 0  , 0  , 0  ), // #499 {W:xmm|m128|mem, R:ymm|zmm, R:u8}
-  ISIGNATURE(4, 1, 1, 0, 132, 73 , 75 , 87 , 0  , 0  ), // #500 {X:xmm, R:xmm, R:xmm|m64|mem, R:u8}
-  ISIGNATURE(4, 1, 1, 0, 132, 73 , 140, 87 , 0  , 0  ), // #501 {X:xmm, R:xmm, R:xmm|m32|mem, R:u8}
-  ISIGNATURE(3, 1, 1, 0, 132, 73 , 75 , 0  , 0  , 0  ), // #502 {X:xmm, R:xmm, R:xmm|m64|mem}
-  ISIGNATURE(3, 1, 1, 0, 132, 73 , 140, 0  , 0  , 0  ), // #503 {X:xmm, R:xmm, R:xmm|m32|mem}
-  ISIGNATURE(3, 1, 1, 0, 128, 239, 87 , 0  , 0  , 0  ), // #504 {W:k, R:xmm|m128|ymm|m256|zmm|m512, R:u8}
-  ISIGNATURE(3, 1, 1, 0, 128, 75 , 87 , 0  , 0  , 0  ), // #505 {W:k, R:xmm|m64|mem, R:u8}
-  ISIGNATURE(3, 1, 1, 0, 128, 140, 87 , 0  , 0  , 0  ), // #506 {W:k, R:xmm|m32|mem, R:u8}
-  ISIGNATURE(1, 1, 1, 0, 90 , 0  , 0  , 0  , 0  , 0  ), // #507 {R:vm32y}
-  ISIGNATURE(1, 1, 1, 0, 91 , 0  , 0  , 0  , 0  , 0  ), // #508 {R:vm32z}
-  ISIGNATURE(1, 1, 1, 0, 94 , 0  , 0  , 0  , 0  , 0  ), // #509 {R:vm64z}
+  ISIGNATURE(4, 1, 1, 0, 89 , 73 , 75 , 87 , 0  , 0  ), // #500 {X:xmm, R:xmm, R:xmm|m64|mem, R:u8}
+  ISIGNATURE(4, 1, 1, 0, 89 , 73 , 140, 87 , 0  , 0  ), // #501 {X:xmm, R:xmm, R:xmm|m32|mem, R:u8}
+  ISIGNATURE(3, 1, 1, 0, 89 , 73 , 75 , 0  , 0  , 0  ), // #502 {X:xmm, R:xmm, R:xmm|m64|mem}
+  ISIGNATURE(3, 1, 1, 0, 89 , 73 , 140, 0  , 0  , 0  ), // #503 {X:xmm, R:xmm, R:xmm|m32|mem}
+  ISIGNATURE(3, 1, 1, 0, 131, 239, 87 , 0  , 0  , 0  ), // #504 {W:k, R:xmm|m128|ymm|m256|zmm|m512, R:u8}
+  ISIGNATURE(3, 1, 1, 0, 131, 75 , 87 , 0  , 0  , 0  ), // #505 {W:k, R:xmm|m64|mem, R:u8}
+  ISIGNATURE(3, 1, 1, 0, 131, 140, 87 , 0  , 0  , 0  ), // #506 {W:k, R:xmm|m32|mem, R:u8}
+  ISIGNATURE(1, 1, 1, 0, 92 , 0  , 0  , 0  , 0  , 0  ), // #507 {R:vm32y}
+  ISIGNATURE(1, 1, 1, 0, 94 , 0  , 0  , 0  , 0  , 0  ), // #508 {R:vm32z}
+  ISIGNATURE(1, 1, 1, 0, 97 , 0  , 0  , 0  , 0  , 0  ), // #509 {R:vm64z}
   ISIGNATURE(4, 1, 1, 0, 83 , 86 , 80 , 87 , 0  , 0  ), // #510 {W:zmm, R:zmm, R:ymm|m256|mem, R:u8}
   ISIGNATURE(4, 1, 1, 0, 74 , 73 , 140, 87 , 0  , 0  ), // #511 {W:xmm, R:xmm, R:xmm|m32|mem, R:u8}
   ISIGNATURE(3, 1, 1, 1, 73 , 73 , 228, 0  , 0  , 0  ), // #512 {R:xmm, R:xmm, R:<ds:[zdi]>}
   ISIGNATURE(2, 1, 1, 0, 173, 191, 0  , 0  , 0  , 0  ), // #513 {W:r32|r64, R:xmm|ymm}
-  ISIGNATURE(6, 1, 1, 0, 83 , 86 , 86 , 86 , 86 , 114), // #514 {W:zmm, R:zmm, R:zmm, R:zmm, R:zmm, R:m128|mem}
+  ISIGNATURE(6, 1, 1, 0, 83 , 86 , 86 , 86 , 86 , 117), // #514 {W:zmm, R:zmm, R:zmm, R:zmm, R:zmm, R:m128|mem}
   ISIGNATURE(2, 1, 1, 0, 185, 164, 0  , 0  , 0  , 0  ), // #515 {W:xmm|ymm|zmm, R:k}
   ISIGNATURE(2, 1, 1, 0, 185, 137, 0  , 0  , 0  , 0  ), // #516 {W:xmm|ymm|zmm, R:xmm|m64|mem|r64}
   ISIGNATURE(4, 1, 1, 0, 74 , 73 , 226, 87 , 0  , 0  ), // #517 {W:xmm, R:xmm, R:r32|m16|mem|r16|r64, R:u8}
-  ISIGNATURE(2, 1, 1, 0, 128, 240, 0  , 0  , 0  , 0  ), // #518 {W:k, R:xmm|ymm|zmm}
+  ISIGNATURE(2, 1, 1, 0, 131, 240, 0  , 0  , 0  , 0  ), // #518 {W:k, R:xmm|ymm|zmm}
   ISIGNATURE(4, 1, 1, 0, 74 , 73 , 75 , 87 , 0  , 0  ), // #519 {W:xmm, R:xmm, R:xmm|m64|mem, R:u8}
   ISIGNATURE(1, 0, 1, 0, 187, 0  , 0  , 0  , 0  , 0  ), // #520 {R:r32|r64}
-  ISIGNATURE(3, 1, 1, 3, 178, 100, 204, 0  , 0  , 0  ), // #521 {R:<edx>, R:<eax>, R:<ecx>}
+  ISIGNATURE(3, 1, 1, 3, 178, 103, 204, 0  , 0  , 0  ), // #521 {R:<edx>, R:<eax>, R:<ecx>}
   ISIGNATURE(1, 1, 1, 0, 241, 0  , 0  , 0  , 0  , 0  ), // #522 {R:rel16|rel32}
-  ISIGNATURE(3, 1, 1, 2, 194, 178, 100, 0  , 0  , 0  ), // #523 {R:mem, R:<edx>, R:<eax>}
-  ISIGNATURE(3, 0, 1, 2, 194, 178, 100, 0  , 0  , 0  ), // #524 {R:mem, R:<edx>, R:<eax>}
-  ISIGNATURE(3, 1, 1, 2, 215, 178, 100, 0  , 0  , 0  ), // #525 {W:mem, R:<edx>, R:<eax>}
-  ISIGNATURE(3, 0, 1, 2, 215, 178, 100, 0  , 0  , 0  )  // #526 {W:mem, R:<edx>, R:<eax>}
+  ISIGNATURE(3, 1, 1, 2, 194, 178, 103, 0  , 0  , 0  ), // #523 {R:mem, R:<edx>, R:<eax>}
+  ISIGNATURE(3, 0, 1, 2, 194, 178, 103, 0  , 0  , 0  ), // #524 {R:mem, R:<edx>, R:<eax>}
+  ISIGNATURE(3, 1, 1, 2, 215, 178, 103, 0  , 0  , 0  ), // #525 {W:mem, R:<edx>, R:<eax>}
+  ISIGNATURE(3, 0, 1, 2, 215, 178, 103, 0  , 0  , 0  )  // #526 {W:mem, R:<edx>, R:<eax>}
 };
 #undef ISIGNATURE
 // ----------------------------------------------------------------------------
 // ${signatureData:End}
-
-template<uint32_t RegType>
-struct X86OpTypeFromRegTypeT {
-  enum {
-    kValue = (RegType == X86Reg::kRegGpbLo) ? X86Inst::kOpGpbLo :
-             (RegType == X86Reg::kRegGpbHi) ? X86Inst::kOpGpbHi :
-             (RegType == X86Reg::kRegGpw  ) ? X86Inst::kOpGpw   :
-             (RegType == X86Reg::kRegGpd  ) ? X86Inst::kOpGpd   :
-             (RegType == X86Reg::kRegGpq  ) ? X86Inst::kOpGpq   :
-             (RegType == X86Reg::kRegXmm  ) ? X86Inst::kOpXmm   :
-             (RegType == X86Reg::kRegYmm  ) ? X86Inst::kOpYmm   :
-             (RegType == X86Reg::kRegZmm  ) ? X86Inst::kOpZmm   :
-             (RegType == X86Reg::kRegRip  ) ? X86Inst::kOpNone  :
-             (RegType == X86Reg::kRegSeg  ) ? X86Inst::kOpSeg   :
-             (RegType == X86Reg::kRegFp   ) ? X86Inst::kOpFp    :
-             (RegType == X86Reg::kRegMm   ) ? X86Inst::kOpMm    :
-             (RegType == X86Reg::kRegK    ) ? X86Inst::kOpK     :
-             (RegType == X86Reg::kRegBnd  ) ? X86Inst::kOpBnd   :
-             (RegType == X86Reg::kRegCr   ) ? X86Inst::kOpCr    :
-             (RegType == X86Reg::kRegDr   ) ? X86Inst::kOpDr    : X86Inst::kOpNone
-  };
-};
-
-template<uint32_t RegType>
-struct X86RegMaskFromRegTypeT {
-  enum {
-    kMask = (RegType == X86Reg::kRegGpbLo) ? 0x0000000FU :
-            (RegType == X86Reg::kRegGpbHi) ? 0x0000000FU :
-            (RegType == X86Reg::kRegGpw  ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegGpd  ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegGpq  ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegXmm  ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegYmm  ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegZmm  ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegRip  ) ? 0x00000001U :
-            (RegType == X86Reg::kRegSeg  ) ? 0x0000007EU : // [ES|CS|SS|DS|FS|GS]
-            (RegType == X86Reg::kRegFp   ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegMm   ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegK    ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegBnd  ) ? 0x0000000FU :
-            (RegType == X86Reg::kRegCr   ) ? 0x0000FFFFU :
-            (RegType == X86Reg::kRegDr   ) ? 0x000000FFU : X86Inst::kOpNone
-  };
-};
-
-template<uint32_t RegType>
-struct X64RegMaskFromRegTypeT {
-  enum {
-    kMask = (RegType == X86Reg::kRegGpbLo) ? 0x0000FFFFU :
-            (RegType == X86Reg::kRegGpbHi) ? 0x0000000FU :
-            (RegType == X86Reg::kRegGpw  ) ? 0x0000FFFFU :
-            (RegType == X86Reg::kRegGpd  ) ? 0x0000FFFFU :
-            (RegType == X86Reg::kRegGpq  ) ? 0x0000FFFFU :
-            (RegType == X86Reg::kRegXmm  ) ? 0xFFFFFFFFU :
-            (RegType == X86Reg::kRegYmm  ) ? 0xFFFFFFFFU :
-            (RegType == X86Reg::kRegZmm  ) ? 0xFFFFFFFFU :
-            (RegType == X86Reg::kRegRip  ) ? 0x00000001U :
-            (RegType == X86Reg::kRegSeg  ) ? 0x0000007EU : // [ES|CS|SS|DS|FS|GS]
-            (RegType == X86Reg::kRegFp   ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegMm   ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegK    ) ? 0x000000FFU :
-            (RegType == X86Reg::kRegBnd  ) ? 0x0000000FU :
-            (RegType == X86Reg::kRegCr   ) ? 0x0000FFFFU :
-            (RegType == X86Reg::kRegDr   ) ? 0x0000FFFFU : X86Inst::kOpNone
-  };
-};
-
-struct X86ValidationData {
-  //! Allowed registers by reg-type (X86::kReg...).
-  uint32_t allowedRegMask[X86Reg::kRegMax + 1];
-  uint32_t allowedMemBaseRegs;
-  uint32_t allowedMemIndexRegs;
-};
-
-static const uint32_t _x86OpFlagFromRegType[X86Reg::kRegMax + 1] = {
-  ASMJIT_TABLE_T_32(X86OpTypeFromRegTypeT, kValue, 0)
-};
-
-static const X86ValidationData _x86ValidationData = {
-  { ASMJIT_TABLE_T_32(X86RegMaskFromRegTypeT, kMask, 0) },
-  (1U << X86Reg::kRegGpw) | (1U << X86Reg::kRegGpd) | (1U << X86Reg::kRegRip) | (1U << Label::kLabelTag),
-  (1U << X86Reg::kRegGpw) | (1U << X86Reg::kRegGpd) | (1U << X86Reg::kRegXmm) | (1U << X86Reg::kRegYmm) | (1U << X86Reg::kRegZmm)
-};
-
-static const X86ValidationData _x64ValidationData = {
-  { ASMJIT_TABLE_T_32(X64RegMaskFromRegTypeT, kMask, 0) },
-  (1U << X86Reg::kRegGpd) | (1U << X86Reg::kRegGpq) | (1U << X86Reg::kRegRip) | (1U << Label::kLabelTag),
-  (1U << X86Reg::kRegGpd) | (1U << X86Reg::kRegGpq) | (1U << X86Reg::kRegXmm) | (1U << X86Reg::kRegYmm) | (1U << X86Reg::kRegZmm)
-};
-
-static ASMJIT_INLINE bool X86Inst_checkOSig(const X86Inst::OSignature& op, const X86Inst::OSignature& ref, bool& immOutOfRange) noexcept {
-  // Fail if operand types are incompatible.
-  uint32_t opFlags = op.flags;
-  if ((opFlags & ref.flags) == 0) {
-    // Mark temporarily `immOutOfRange` so we can return a more descriptive error.
-    if ((opFlags & X86Inst::kOpAllImm) && (ref.flags & X86Inst::kOpAllImm)) {
-      immOutOfRange = true;
-      return true;
-    }
-
-    return false;
-  }
-
-  // Fail if memory specific flags and sizes are incompatibles.
-  uint32_t opMemFlags = op.memFlags;
-  if (opMemFlags != 0) {
-    uint32_t refMemFlags = ref.memFlags;
-    if ((refMemFlags & opMemFlags) == 0)
-      return false;
-
-    if ((refMemFlags & X86Inst::kMemOpBaseOnly) && !(opMemFlags && X86Inst::kMemOpBaseOnly))
-      return false;
-  }
-
-  // Specific register index.
-  if (opFlags & X86Inst::kOpAllRegs) {
-    uint32_t refRegMask = ref.regMask;
-    if (refRegMask && !(op.regMask & refRegMask))
-      return false;
-  }
-
-  return true;
-}
-
-ASMJIT_FAVOR_SIZE Error X86Inst::validate(
-  uint32_t archType,
-  uint32_t instId, uint32_t options,
-  const Operand_& extraOp, const Operand_* opArray, uint32_t opCount) noexcept {
-
-  uint32_t i;
-  uint32_t archMask;
-  const X86ValidationData* vd;
-
-  if (!ArchInfo::isX86Family(archType))
-    return DebugUtils::errored(kErrorInvalidArch);
-
-  if (archType == ArchInfo::kTypeX86) {
-    vd = &_x86ValidationData;
-    archMask = X86Inst::kArchMaskX86;
-  }
-  else {
-    vd = &_x64ValidationData;
-    archMask = X86Inst::kArchMaskX64;
-  }
-
-  // Get the instruction data.
-  if (ASMJIT_UNLIKELY(instId >= X86Inst::_kIdCount))
-    return DebugUtils::errored(kErrorInvalidArgument);
-
-  const X86Inst* iData = &X86InstDB::instData[instId];
-  uint32_t iFlags = iData->getFlags();
-
-  // Validate LOCK, XACQUIRE, and XRELEASE prefixes.
-  const uint32_t kLockXAcqRel = X86Inst::kOptionXAcquire | X86Inst::kOptionXRelease;
-  if (options & (X86Inst::kOptionLock | kLockXAcqRel)) {
-    if (options & X86Inst::kOptionLock) {
-      if (ASMJIT_UNLIKELY(!(iFlags & X86Inst::kFlagLock) && !(options & kLockXAcqRel)))
-        return DebugUtils::errored(kErrorInvalidLockPrefix);
-
-      if (ASMJIT_UNLIKELY(opCount < 1 || !opArray[0].isMem()))
-        return DebugUtils::errored(kErrorInvalidLockPrefix);
-    }
-
-    if (options & kLockXAcqRel) {
-      if (ASMJIT_UNLIKELY(!(options & X86Inst::kOptionLock) || (options & kLockXAcqRel) == kLockXAcqRel))
-        return DebugUtils::errored(kErrorInvalidPrefixCombination);
-
-      if (ASMJIT_UNLIKELY((options & X86Inst::kOptionXAcquire) && !(iFlags & X86Inst::kFlagXAcquire)))
-        return DebugUtils::errored(kErrorInvalidXAcquirePrefix);
-
-      if (ASMJIT_UNLIKELY((options & X86Inst::kOptionXRelease) && !(iFlags & X86Inst::kFlagXRelease)))
-        return DebugUtils::errored(kErrorInvalidXReleasePrefix);
-    }
-  }
-
-  // Validate REP and REPNZ prefixes.
-  const uint32_t kRepRepnz = X86Inst::kOptionRep | X86Inst::kOptionRepnz;
-  if (options & kRepRepnz) {
-    if (ASMJIT_UNLIKELY((options & kRepRepnz) == kRepRepnz))
-      return DebugUtils::errored(kErrorInvalidPrefixCombination);
-
-    if (ASMJIT_UNLIKELY((options & X86Inst::kOptionRep) && !(iFlags & X86Inst::kFlagRep)))
-      return DebugUtils::errored(kErrorInvalidRepPrefix);
-
-    if (ASMJIT_UNLIKELY((options & X86Inst::kOptionRepnz) && !(iFlags & X86Inst::kFlagRepnz)))
-      return DebugUtils::errored(kErrorInvalidRepPrefix);
-  }
-
-  // Translate the given operands to `X86Inst::OSignature`.
-  X86Inst::OSignature oSigTranslated[6];
-  uint32_t combinedOpFlags = 0;
-  uint32_t combinedRegMask = 0;
-
-  const X86Mem* memOp = nullptr;
-
-  for (i = 0; i < opCount; i++) {
-    const Operand_& op = opArray[i];
-    if (op.getOp() == Operand::kOpNone) break;
-
-    uint32_t opFlags = 0;
-    uint32_t memFlags = 0;
-    uint32_t regMask = 0;
-
-    switch (op.getOp()) {
-      case Operand::kOpReg: {
-        uint32_t regType = op.as<Reg>().getType();
-        if (ASMJIT_UNLIKELY(regType >= X86Reg::kRegCount))
-          return DebugUtils::errored(kErrorInvalidRegType);
-
-        opFlags = _x86OpFlagFromRegType[regType];
-        if (ASMJIT_UNLIKELY(opFlags == 0))
-          return DebugUtils::errored(kErrorInvalidRegType);
-
-        // If `regId` is equal or greater than Operand::kPackedIdMin it means
-        // that the register is virtual and its index will be assigned later
-        // by the register allocator. We must pass unless asked to disallow
-        // virtual registers.
-        // TODO: We need an option to refuse virtual regs here.
-        uint32_t regId = op.getId();
-        if (regId < Operand::kPackedIdMin) {
-          if (ASMJIT_UNLIKELY(regId >= 32))
-            return DebugUtils::errored(kErrorInvalidPhysId);
-
-          regMask = Utils::mask(regId);
-          if (ASMJIT_UNLIKELY((vd->allowedRegMask[regType] & regMask) == 0))
-            return DebugUtils::errored(kErrorInvalidPhysId);
-
-          combinedRegMask |= regMask;
-        }
-        else {
-          regMask = 0xFFFFFFFFU;
-        }
-        break;
-      }
-
-      // TODO: Validate base and index and combine with `combinedRegMask`.
-      case Operand::kOpMem: {
-        const X86Mem& m = op.as<X86Mem>();
-
-        uint32_t baseType = m.getBaseType();
-        uint32_t indexType = m.getIndexType();
-
-        memOp = &m;
-
-        if (m.getSegmentId() > 6)
-          return DebugUtils::errored(kErrorInvalidSegment);
-
-        if (baseType) {
-          uint32_t baseId = m.getBaseId();
-
-          if (m.isRegHome()) {
-            // Home address of virtual register. In such case we don't want to
-            // validate the type of the base register as it will always be patched
-            // to ESP|RSP.
-          }
-          else {
-            if (ASMJIT_UNLIKELY((vd->allowedMemBaseRegs & (1U << baseType)) == 0))
-              return DebugUtils::errored(kErrorInvalidAddress);
-          }
-
-          // Create information that will be validated only if this is an implicit
-          // memory operand. Basically only usable for string instructions and other
-          // instructions where memory operand is implicit and has 'seg:[reg]' form.
-          if (baseId < Operand::kPackedIdMin) {
-            // Physical base id.
-            regMask = Utils::mask(baseId);
-            combinedRegMask |= regMask;
-          }
-          else {
-            // Virtual base id - will the whole mask for implicit mem validation.
-            // The register is not assigned yet, so we cannot predict the phys id.
-            regMask = 0xFFFFFFFFU;
-          }
-
-          if (!indexType && !m.getOffsetLo32())
-            memFlags |= X86Inst::kMemOpBaseOnly;
-        }
-        else {
-          // Base is an address, make sure that the address doesn't overflow 32-bit
-          // integer (either int32_t or uint32_t) in 32-bit targets.
-          int64_t offset = m.getOffset();
-          if (archMask == X86Inst::kArchMaskX86 && !Utils::isInt32(offset) && !Utils::isUInt32(offset))
-            return DebugUtils::errored(kErrorInvalidAddress);
-        }
-
-        if (indexType) {
-          if (ASMJIT_UNLIKELY((vd->allowedMemIndexRegs & (1U << indexType)) == 0))
-            return DebugUtils::errored(kErrorInvalidAddress);
-
-          if (indexType == X86Reg::kRegXmm) {
-            opFlags |= X86Inst::kOpVm;
-            memFlags |= X86Inst::kMemOpVm32x | X86Inst::kMemOpVm64x;
-          }
-          else if (indexType == X86Reg::kRegYmm) {
-            opFlags |= X86Inst::kOpVm;
-            memFlags |= X86Inst::kMemOpVm32y | X86Inst::kMemOpVm64y;
-          }
-          else if (indexType == X86Reg::kRegZmm) {
-            opFlags |= X86Inst::kOpVm;
-            memFlags |= X86Inst::kMemOpVm32z | X86Inst::kMemOpVm64z;
-          }
-          else {
-            opFlags |= X86Inst::kOpMem;
-            if (baseType)
-              memFlags |= X86Inst::kMemOpMib;
-          }
-
-          // [RIP + {XMM|YMM|ZMM}] is not allowed.
-          if (baseType == X86Reg::kRegRip && (opFlags & X86Inst::kOpVm))
-            return DebugUtils::errored(kErrorInvalidAddress);
-
-          uint32_t indexId = m.getIndexId();
-          if (indexId < Operand::kPackedIdMin)
-            combinedRegMask |= Utils::mask(indexId);
-
-          // Only used for implicit memory operands having 'seg:[reg]' form, so clear it.
-          regMask = 0;
-        }
-        else {
-          opFlags |= X86Inst::kOpMem;
-        }
-
-        switch (m.getSize()) {
-          case  0: memFlags |= X86Inst::kMemOpAny ; break;
-          case  1: memFlags |= X86Inst::kMemOpM8  ; break;
-          case  2: memFlags |= X86Inst::kMemOpM16 ; break;
-          case  4: memFlags |= X86Inst::kMemOpM32 ; break;
-          case  6: memFlags |= X86Inst::kMemOpM48 ; break;
-          case  8: memFlags |= X86Inst::kMemOpM64 ; break;
-          case 10: memFlags |= X86Inst::kMemOpM80 ; break;
-          case 16: memFlags |= X86Inst::kMemOpM128; break;
-          case 32: memFlags |= X86Inst::kMemOpM256; break;
-          case 64: memFlags |= X86Inst::kMemOpM512; break;
-          default:
-            return DebugUtils::errored(kErrorInvalidOperandSize);
-        }
-
-        break;
-      }
-
-      case Operand::kOpImm: {
-        uint64_t immValue = op.as<Imm>().getUInt64();
-        uint32_t immFlags = 0;
-
-        if (static_cast<int64_t>(immValue) >= 0) {
-          const uint32_t k32AndMore = X86Inst::kOpI32 | X86Inst::kOpU32 |
-                                      X86Inst::kOpI64 | X86Inst::kOpU64 ;
-
-          if (immValue <= 0xFU)
-            immFlags = X86Inst::kOpU4 | X86Inst::kOpI8 | X86Inst::kOpU8 | X86Inst::kOpI16 | X86Inst::kOpU16 | k32AndMore;
-          else if (immValue <= 0x7FU)
-            immFlags = X86Inst::kOpI8 | X86Inst::kOpU8 | X86Inst::kOpI16 | X86Inst::kOpU16 | k32AndMore;
-          else if (immValue <= 0xFFU)
-            immFlags = X86Inst::kOpU8 | X86Inst::kOpI16 | X86Inst::kOpU16 | k32AndMore;
-          else if (immValue <= 0x7FFFU)
-            immFlags = X86Inst::kOpI16 | X86Inst::kOpU16 | k32AndMore;
-          else if (immValue <= 0xFFFFU)
-            immFlags = X86Inst::kOpU16 | k32AndMore;
-          else if (immValue <= 0x7FFFFFFFU)
-            immFlags = k32AndMore;
-          else if (immValue <= 0xFFFFFFFFU)
-            immFlags = X86Inst::kOpU32 | X86Inst::kOpI64 | X86Inst::kOpU64;
-          else if (immValue <= ASMJIT_UINT64_C(0x7FFFFFFFFFFFFFFF))
-            immFlags = X86Inst::kOpI64 | X86Inst::kOpU64;
-          else
-            immFlags = X86Inst::kOpU64;
-        }
-        else {
-          // 2s complement negation, as our number is unsigned...
-          immValue = (~immValue + 1);
-
-          if (immValue <= 0x80U)
-            immFlags = X86Inst::kOpI8 | X86Inst::kOpI16 | X86Inst::kOpI32 | X86Inst::kOpI64;
-          else if (immValue <= 0x8000U)
-            immFlags = X86Inst::kOpI16 | X86Inst::kOpI32 | X86Inst::kOpI64;
-          else if (immValue <= 0x80000000U)
-            immFlags = X86Inst::kOpI32 | X86Inst::kOpI64;
-          else
-            immFlags = X86Inst::kOpI64;
-        }
-        opFlags |= immFlags;
-        break;
-      }
-
-      case Operand::kOpLabel: {
-        opFlags |= X86Inst::kOpRel8 | X86Inst::kOpRel32;
-        break;
-      }
-
-      default:
-        return DebugUtils::errored(kErrorInvalidState);
-    }
-
-    X86Inst::OSignature& tod = oSigTranslated[i];
-    tod.flags = opFlags;
-    tod.memFlags = static_cast<uint16_t>(memFlags);
-    tod.regMask = static_cast<uint8_t>(regMask & 0xFFU);
-    combinedOpFlags |= opFlags;
-  }
-
-  // Decrease the number of operands of those that are none. This is important
-  // as Assembler and CodeCompiler may just pass more operands where some of
-  // them are none (it means that no operand is given at that index). However,
-  // validate that there are no gaps (like [reg, none, reg] or [none, reg]).
-  if (i < opCount) {
-    while (--opCount > i)
-      if (ASMJIT_UNLIKELY(!opArray[opCount].isNone()))
-        return DebugUtils::errored(kErrorInvalidState);
-  }
-
-  // Validate X86 and X64 specific cases.
-  if (archMask == kArchMaskX86) {
-    // Illegal use of 64-bit register in 32-bit mode.
-    if (ASMJIT_UNLIKELY((combinedOpFlags & X86Inst::kOpGpq) != 0))
-      return DebugUtils::errored(kErrorInvalidUseOfGpq);
-  }
-  else {
-    // Illegal use of a high 8-bit register with REX prefix.
-    if (ASMJIT_UNLIKELY((combinedOpFlags & X86Inst::kOpGpbHi) != 0 && (combinedRegMask & 0xFFFFFF00U) != 0))
-      return DebugUtils::errored(kErrorInvalidUseOfGpbHi);
-  }
-
-  // Validate instruction operands.
-  const X86Inst::CommonData* commonData = &iData->getCommonData();
-  const X86Inst::ISignature* iSig = X86InstDB::iSignatureData + commonData->_iSignatureIndex;
-  const X86Inst::ISignature* iEnd = iSig                      + commonData->_iSignatureCount;
-
-  if (iSig != iEnd) {
-    const X86Inst::OSignature* oSigData = X86InstDB::oSignatureData;
-
-    // If set it means that we matched a signature where only immediate value
-    // was out of bounds. We can return a more descriptive error if we know this.
-    bool globalImmOutOfRange = false;
-
-    do {
-      // Check if the architecture is compatible.
-      if ((iSig->archMask & archMask) == 0) continue;
-
-      // Compare the operands table with reference operands.
-      uint32_t j = 0;
-      uint32_t iCount = iSig->opCount;
-      bool localImmOutOfRange = false;
-
-      if (iCount == opCount) {
-        for (j = 0; j < opCount; j++)
-          if (!X86Inst_checkOSig(oSigTranslated[j], oSigData[iSig->operands[j]], localImmOutOfRange))
-            break;
-      }
-      else if (iCount - iSig->implicit == opCount) {
-        uint32_t r = 0;
-        for (j = 0; j < opCount && r < iCount; j++, r++) {
-          const X86Inst::OSignature* oChk = oSigTranslated + j;
-          const X86Inst::OSignature* oRef;
-Next:
-          oRef = oSigData + iSig->operands[r];
-          // Skip implicit.
-          if ((oRef->flags & X86Inst::kOpImplicit) != 0) {
-            if (++r >= iCount)
-              break;
-            else
-              goto Next;
-          }
-
-          if (!X86Inst_checkOSig(*oChk, *oRef, localImmOutOfRange))
-            break;
-        }
-      }
-
-      if (j == opCount) {
-        if (!localImmOutOfRange) {
-          // Match, must clear possible `globalImmOutOfRange`.
-          globalImmOutOfRange = false;
-          break;
-        }
-        globalImmOutOfRange = localImmOutOfRange;
-      }
-    } while (++iSig != iEnd);
-
-    if (iSig == iEnd) {
-      if (globalImmOutOfRange)
-        return DebugUtils::errored(kErrorInvalidImmediate);
-      else
-        return DebugUtils::errored(kErrorInvalidInstruction);
-    }
-  }
-
-  // Validate AVX-512 options:
-  const uint32_t kAvx512Options = X86Inst::kOptionZMask   |
-                                  X86Inst::kOption1ToX    |
-                                  X86Inst::kOptionER      |
-                                  X86Inst::kOptionSAE     ;
-
-  if (!extraOp.isNone() || (options & kAvx512Options)) {
-    if (commonData->hasFlag(X86Inst::kFlagEvex)) {
-      // Validate AVX-512 {k} and {k}{z}.
-      if (!extraOp.isNone()) {
-        // Mask can only be specified by a 'k' register.
-        if (ASMJIT_UNLIKELY(!X86Reg::isK(extraOp)))
-          return DebugUtils::errored(kErrorInvalidKMaskReg);
-
-        if (ASMJIT_UNLIKELY(!commonData->hasAvx512K()))
-          return DebugUtils::errored(kErrorInvalidKMaskUse);
-      }
-
-      if ((options & X86Inst::kOptionZMask)) {
-        if (ASMJIT_UNLIKELY((options & X86Inst::kOptionZMask) != 0 && !commonData->hasAvx512Z()))
-          return DebugUtils::errored(kErrorInvalidKZeroUse);
-      }
-
-      // Validate AVX-512 broadcast {1tox}.
-      if (options & X86Inst::kOption1ToX) {
-        if (ASMJIT_UNLIKELY(!memOp))
-          return DebugUtils::errored(kErrorInvalidBroadcast);
-
-        uint32_t size = memOp->getSize();
-        if (size != 0) {
-          // The the size is specified it has to match the broadcast size.
-          if (ASMJIT_UNLIKELY(commonData->hasAvx512B32() && size != 4))
-            return DebugUtils::errored(kErrorInvalidBroadcast);
-
-          if (ASMJIT_UNLIKELY(commonData->hasAvx512B64() && size != 8))
-            return DebugUtils::errored(kErrorInvalidBroadcast);
-        }
-      }
-
-      // Validate AVX-512 {sae} and {er}.
-      if (options & (X86Inst::kOptionSAE | X86Inst::kOptionER)) {
-        // Rounding control is impossible if the instruction is not reg-to-reg.
-        if (ASMJIT_UNLIKELY(memOp))
-          return DebugUtils::errored(kErrorInvalidEROrSAE);
-
-        // Check if {sae} or {er} is supported by the instruction.
-        if (options & X86Inst::kOptionER) {
-          // NOTE: if both {sae} and {er} are set, we don't care, as {sae} is implied.
-          if (ASMJIT_UNLIKELY(!commonData->hasAvx512ER()))
-            return DebugUtils::errored(kErrorInvalidEROrSAE);
-
-          // {er} is defined for scalar ops or vector ops using zmm (LL = 10). We
-          // don't need any more bits in the instruction database to be able to
-          // validate this, as each AVX512 instruction that has broadcast is vector
-          // instruction (in this case we require zmm registers), otherwise it's a
-          // scalar instruction, which is valid.
-          if (commonData->hasAvx512B()) {
-            // Supports broadcast, thus we require LL to be '10', which means there
-            // have to be zmm registers used. We don't calculate LL here, but we know
-            // that it would be '10' if there is at least one ZMM register used.
-
-            // There is no 'ER' enabled instruction with less than two operands.
-            ASMJIT_ASSERT(opCount >= 2);
-            if (ASMJIT_UNLIKELY(!X86Reg::isZmm(opArray[0]) && !X86Reg::isZmm(opArray[1])))
-              return DebugUtils::errored(kErrorInvalidEROrSAE);
-          }
-        }
-        else {
-          // {sae} doesn't have the same limitations as {er}, this is enough.
-          if (ASMJIT_UNLIKELY(!commonData->hasAvx512SAE()))
-            return DebugUtils::errored(kErrorInvalidEROrSAE);
-        }
-      }
-    }
-    else {
-      // Not AVX512 instruction - maybe OpExtra is xCX register used by REP/REPNZ prefix. Otherwise the instruction is invalid.
-      if ((options & kAvx512Options) || (options & (X86Inst::kOptionRep | X86Inst::kOptionRepnz)) == 0)
-        return DebugUtils::errored(kErrorInvalidInstruction);
-    }
-  }
-
-  return kErrorOk;
-}
 #endif // !ASMJIT_DISABLE_VALIDATION
 
 // ============================================================================
@@ -4278,93 +3710,15 @@ UNIT(x86_inst_names) {
         X86Inst::getInst(b).getName(), b);
   }
 
-  // Everything else should return `kInvalidInstId`.
+  // Everything else should return `Inst::kIdNone`.
   INFO("Trying to look-up instructions that don't exist");
-  EXPECT(X86Inst::getIdByName(nullptr) == Globals::kInvalidInstId,
-    "Should return kInvalidInstId for null input");
-
-  EXPECT(X86Inst::getIdByName("") == Globals::kInvalidInstId,
-    "Should return kInvalidInstId for empty string");
-
-  EXPECT(X86Inst::getIdByName("_") == Globals::kInvalidInstId,
-    "Should return kInvalidInstId for unknown instruction");
-
-  EXPECT(X86Inst::getIdByName("123xyz") == Globals::kInvalidInstId,
-    "Should return kInvalidInstId for unknown instruction");
+  EXPECT(X86Inst::getIdByName(nullptr)  == Inst::kIdNone, "Should return Inst::kIdNone for null input");
+  EXPECT(X86Inst::getIdByName("")       == Inst::kIdNone, "Should return Inst::kIdNone for empty string");
+  EXPECT(X86Inst::getIdByName("_")      == Inst::kIdNone, "Should return Inst::kIdNone for unknown instruction");
+  EXPECT(X86Inst::getIdByName("123xyz") == Inst::kIdNone, "Should return Inst::kIdNone for unknown instruction");
 }
 #endif // ASMJIT_TEST && !ASMJIT_DISABLE_TEXT
 
-#if defined(ASMJIT_TEST) && !defined(ASMJIT_DISABLE_VALIDATION)
-static Error x86_validate(uint32_t instId, const Operand& o0 = Operand(), const Operand& o1 = Operand(), const Operand& o2 = Operand()) {
-  Operand opArray[] = { o0, o1, o2 };
-  return X86Inst::validate(ArchInfo::kTypeX86, instId, 0, Operand(), opArray, 3);
-}
-
-static Error x64_validate(uint32_t instId, const Operand& o0 = Operand(), const Operand& o1 = Operand(), const Operand& o2 = Operand()) {
-  Operand opArray[] = { o0, o1, o2 };
-  return X86Inst::validate(ArchInfo::kTypeX64, instId, 0, Operand(), opArray, 3);
-}
-
-UNIT(x86_inst_validation) {
-  INFO("Validating instructions that use GP registers");
-  EXPECT(x86_validate(X86Inst::kIdCmp   , x86::eax , x86::edx ) == kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdCmp   , x86::rax , x86::rdx ) == kErrorOk);
-
-  EXPECT(x86_validate(X86Inst::kIdCmp   , x86::eax            ) != kErrorOk);
-  EXPECT(x86_validate(X86Inst::kIdCmp   , x86::rax , x86::rdx ) != kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdCmp   , x86::rax , x86::al  ) != kErrorOk);
-
-  INFO("Validating instructions that use FP registers");
-  EXPECT(x86_validate(X86Inst::kIdFadd  , x86::fp0 , x86::fp7 ) == kErrorOk);
-  EXPECT(x86_validate(X86Inst::kIdFadd  , x86::fp7 , x86::fp0 ) == kErrorOk);
-  EXPECT(x86_validate(X86Inst::kIdFadd  , x86::fp0 , x86::eax ) != kErrorOk);
-  EXPECT(x86_validate(X86Inst::kIdFadd  , x86::fp4 , x86::fp3 ) != kErrorOk);
-
-  INFO("Validating instructions that use MM registers");
-  EXPECT(x86_validate(X86Inst::kIdPand  , x86::mm0 , x86::mm1 ) == kErrorOk);
-  EXPECT(x86_validate(X86Inst::kIdPand  , x86::mm0 , x86::eax ) != kErrorOk);
-
-  INFO("Validating instructions that use XMM registers");
-  EXPECT(x86_validate(X86Inst::kIdPand  , x86::xmm0, x86::xmm1) == kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdPand  , x86::xmm8, x86::xmm9) == kErrorOk);
-  EXPECT(x86_validate(X86Inst::kIdPand  , x86::xmm0, x86::eax ) != kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdPand  , x86::xmm0, x86::rax ) != kErrorOk);
-
-  INFO("Validating instructions that use YMM registers");
-  EXPECT(x86_validate(X86Inst::kIdVpand , x86::ymm0, x86::ymm1, x86::ymm2) == kErrorOk);
-  EXPECT(x86_validate(X86Inst::kIdVpand , x86::ymm0, x86::ymm1, x86::eax ) != kErrorOk);
-
-  INFO("Validating instructions that use ZMM registers");
-  EXPECT(x86_validate(X86Inst::kIdVpaddw, x86::zmm0, x86::zmm1, x86::zmm2) == kErrorOk);
-  EXPECT(x86_validate(X86Inst::kIdVpaddw, x86::zmm0, x86::zmm1, x86::eax ) != kErrorOk);
-
-  INFO("Validating instructions that use CR registers");
-  EXPECT(x86_validate(X86Inst::kIdMov   , x86::eax , x86::cr0 ) == kErrorOk);
-  EXPECT(x86_validate(X86Inst::kIdMov   , x86::eax , x86::cr8 ) == kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdMov   , x86::rax , x86::cr8 ) == kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdMov   , x86::eax , x86::cr0 ) != kErrorOk);
-
-  INFO("Validating instructions that use DR registers");
-  EXPECT(x86_validate(X86Inst::kIdMov   , x86::eax , x86::dr0 ) == kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdMov   , x86::rax , x86::dr7 ) == kErrorOk);
-  EXPECT(x86_validate(X86Inst::kIdMov   , x86::ax  , x86::dr0 ) != kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdMov   , x86::eax , x86::dr7 ) != kErrorOk);
-
-  INFO("Validating instructions that use segment registers");
-  EXPECT(x86_validate(X86Inst::kIdMov   , x86::ax  , x86::fs  ) == kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdMov   , x86::ax  , x86::fs  ) == kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdPush  , x86::cs             ) != kErrorOk);
-
-  INFO("Validating instructions that use memory operands");
-  EXPECT(x86_validate(X86Inst::kIdMov   , x86::eax , x86::ptr(x86::ebx)) == kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdMov   , x86::rax , x86::ptr(x86::rbx)) == kErrorOk);
-
-  INFO("Validating instructions that use immediate values");
-  EXPECT(x86_validate(X86Inst::kIdMov   , x86::eax , imm(1)) == kErrorOk);
-  EXPECT(x64_validate(X86Inst::kIdMov   , x86::rax , imm(1)) == kErrorOk);
-}
-#endif // ASMJIT_TEST && !ASMJIT_DISABLE_VALIDATION
-
 } // asmjit namespace
 
 // [Api-End]
diff --git a/src/asmjit/x86/x86inst.h b/src/asmjit/x86/x86inst.h
index a028f1e..7cc640e 100644
--- a/src/asmjit/x86/x86inst.h
+++ b/src/asmjit/x86/x86inst.h
@@ -9,7 +9,8 @@
 #define _ASMJIT_X86_X86INST_H
 
 // [Dependencies]
-#include "../base/assembler.h"
+#include "../base/assembler.h" // TODO: Is that necessary?
+#include "../base/inst.h"
 #include "../base/operand.h"
 #include "../base/utils.h"
 #include "../x86/x86globals.h"
@@ -301,7 +302,7 @@ struct X86Inst {
     kIdInsertq,                          // [ANY] {SSE4A}
     kIdInt,                              // [ANY]
     kIdInt3,                             // [ANY]
-    kIdInto,                             // [ANY]
+    kIdInto,                             // [X86]
     kIdInvd,                             // [ANY] {I486}
     kIdInvlpg,                           // [ANY] {I486}
     kIdInvpcid,                          // [ANY] {I486}
@@ -1055,8 +1056,8 @@ struct X86Inst {
     kIdVmovupd,                          // [ANY] {AVX|AVX512_F+VL}
     kIdVmovups,                          // [ANY] {AVX|AVX512_F+VL}
     kIdVmpsadbw,                         // [ANY] {AVX|AVX2}
-    kIdVmulpd,                           // [ANY] {AVX|AVX2|AVX512_F+VL}
-    kIdVmulps,                           // [ANY] {AVX|AVX2|AVX512_F+VL}
+    kIdVmulpd,                           // [ANY] {AVX|AVX512_F+VL}
+    kIdVmulps,                           // [ANY] {AVX|AVX512_F+VL}
     kIdVmulsd,                           // [ANY] {AVX|AVX512_F}
     kIdVmulss,                           // [ANY] {AVX|AVX512_F}
     kIdVorpd,                            // [ANY] {AVX|AVX512_DQ+VL}
@@ -1426,8 +1427,8 @@ struct X86Inst {
     kIdVsqrtsd,                          // [ANY] {AVX|AVX512_F}
     kIdVsqrtss,                          // [ANY] {AVX|AVX512_F}
     kIdVstmxcsr,                         // [ANY] {AVX}
-    kIdVsubpd,                           // [ANY] {AVX|AVX2|AVX512_F+VL}
-    kIdVsubps,                           // [ANY] {AVX|AVX2|AVX512_F+VL}
+    kIdVsubpd,                           // [ANY] {AVX|AVX512_F+VL}
+    kIdVsubps,                           // [ANY] {AVX|AVX512_F+VL}
     kIdVsubsd,                           // [ANY] {AVX|AVX512_F}
     kIdVsubss,                           // [ANY] {AVX|AVX512_F}
     kIdVtestpd,                          // [ANY] {AVX}
@@ -1458,16 +1459,16 @@ struct X86Inst {
     kIdXorps,                            // [ANY] {SSE}
     kIdXrstor,                           // [ANY] {XSAVE}
     kIdXrstor64,                         // [X64] {XSAVE}
-    kIdXrstors,                          // [ANY] {XSAVE}
-    kIdXrstors64,                        // [X64] {XSAVE}
+    kIdXrstors,                          // [ANY] {XSAVES}
+    kIdXrstors64,                        // [X64] {XSAVES}
     kIdXsave,                            // [ANY] {XSAVE}
     kIdXsave64,                          // [X64] {XSAVE}
-    kIdXsavec,                           // [ANY] {XSAVE}
-    kIdXsavec64,                         // [X64] {XSAVE}
+    kIdXsavec,                           // [ANY] {XSAVEC}
+    kIdXsavec64,                         // [X64] {XSAVEC}
     kIdXsaveopt,                         // [ANY] {XSAVEOPT}
     kIdXsaveopt64,                       // [X64] {XSAVEOPT}
-    kIdXsaves,                           // [ANY] {XSAVE}
-    kIdXsaves64,                         // [X64] {XSAVE}
+    kIdXsaves,                           // [ANY] {XSAVES}
+    kIdXsaves64,                         // [X64] {XSAVES}
     kIdXsetbv,                           // [ANY] {XSAVE}
     kIdXtest,                            // [ANY] {TSX}
     _kIdCount
@@ -1996,13 +1997,13 @@ struct X86Inst {
 
     kOptionER             = 0x00040000U, //!< AVX-512: 'embedded-rounding' {er} and {sae}.
     kOptionSAE            = 0x00080000U, //!< AVX-512: 'suppress-all-exceptions' {sae}.
-
     kOption1ToX           = 0x00100000U, //!< AVX-512: broadcast the first element to all {1tox}.
     kOptionRN_SAE         = 0x00000000U, //!< AVX-512: round-to-nearest (even)      {rn-sae} (bits 00).
     kOptionRD_SAE         = 0x00200000U, //!< AVX-512: round-down (toward -inf)     {rd-sae} (bits 01).
     kOptionRU_SAE         = 0x00400000U, //!< AVX-512: round-up (toward +inf)       {ru-sae} (bits 10).
     kOptionRZ_SAE         = 0x00600000U, //!< AVX-512: round-toward-zero (truncate) {rz-sae} (bits 11).
     kOptionZMask          = 0x00800000U, //!< AVX-512: Use zeroing {k}{z} instead of merging {k}.
+    _kOptionAvx512Mask    = 0x00FC0000U, //!< AVX-512: Mask of all possible AVX-512 options except EVEX prefix flag.
 
     _kOptionInvalidRex    = 0x01000000U, //!< REX prefix can't be emitted (internal).
     kOptionOpCodeB        = 0x02000000U, //!< REX.B and/or VEX.B field (X64).
@@ -2147,8 +2148,13 @@ struct X86Inst {
     ASMJIT_INLINE bool isFpu() const noexcept { return hasFlag(kFlagFpu); }
     //! Get if the instruction is MMX|3DNOW instruction that accesses MMX registers (includes EMMS).
     ASMJIT_INLINE bool isMmx() const noexcept { return hasFlag(kFlagMmx); }
+
     //! Get if the instruction is SSE|AVX|AVX512 instruction that accesses XMM|YMM|ZMM registers (includes VZEROALL|VZEROUPPER).
     ASMJIT_INLINE bool isVec() const noexcept { return hasFlag(kFlagVec); }
+    //! Get if the instruction is SSE+ (SSE4.2, AES, SHA included) instruction that accesses XMM registers.
+    ASMJIT_INLINE bool isSse() const noexcept { return (getFlags() & (kFlagVec | kFlagVex | kFlagEvex)) == kFlagVec; }
+    //! Get if the instruction is AVX+ (FMA included) instruction that accesses XMM|YMM|ZMM registers.
+    ASMJIT_INLINE bool isAvx() const noexcept { return isVec() && isVexOrEvex(); }
 
     //! Get if the instruction can be prefixed by LOCK prefix.
     ASMJIT_INLINE bool isLockEnabled() const noexcept { return hasFlag(kFlagLock); }
@@ -2167,6 +2173,8 @@ struct X86Inst {
     ASMJIT_INLINE bool isVex() const noexcept { return hasFlag(kFlagVex); }
     //! Get if the instruction uses EVEX (can be set together with VEX if both are encodable).
     ASMJIT_INLINE bool isEvex() const noexcept { return hasFlag(kFlagEvex); }
+    //! Get if the instruction uses VEX and/or EVEX.
+    ASMJIT_INLINE bool isVexOrEvex() const noexcept { return hasFlag(kFlagVex | kFlagEvex); }
 
     //! Get if the instruction supports AVX512 masking {k}.
     ASMJIT_INLINE bool hasAvx512K() const noexcept { return hasFlag(kFlagAvx512K); }
@@ -2184,7 +2192,7 @@ struct X86Inst {
     ASMJIT_INLINE bool hasAvx512B64() const noexcept { return hasFlag(kFlagAvx512B64); }
 
     //! Get if the instruction may or will jump (returns true also for calls and returns).
-    ASMJIT_INLINE bool doesJump() const noexcept { return _jumpType != AnyInst::kJumpTypeNone; }
+    ASMJIT_INLINE bool doesJump() const noexcept { return _jumpType != Inst::kJumpTypeNone; }
 
     //! Get the destination index of WRITE operation.
     ASMJIT_INLINE uint32_t getWriteIndex() const noexcept { return _writeIndex; }
@@ -2219,7 +2227,7 @@ struct X86Inst {
     uint32_t _altOpCodeIndex     : 8;    //!< Index to table with alternative opcodes.
     uint32_t _iSignatureIndex    :10;    //!< First `ISignature` entry in the database.
     uint32_t _iSignatureCount    : 4;    //!< Number of relevant `ISignature` entries.
-    uint32_t _jumpType           : 3;    //!< Jump type, see `AnyInst::JumpType`.
+    uint32_t _jumpType           : 3;    //!< Jump type, see `Inst::JumpType`.
     uint32_t _singleRegCase      : 2;    //!< Specifies what happens if all source operands share the same register.
     uint32_t _reserved           : 5;    //!< \internal
   };
@@ -2326,8 +2334,13 @@ struct X86Inst {
   ASMJIT_INLINE bool isFpu() const noexcept { return getCommonData().isFpu(); }
   //! Get if the instruction is MMX instruction that accesses MMX registersm, including EMMS.
   ASMJIT_INLINE bool isMmx() const noexcept { return getCommonData().isMmx(); }
+
   //! Get if the instruction is SSE|AVX|AVX512 instruction that accesses XMM|YMM|ZMM registers.
   ASMJIT_INLINE bool isVec() const noexcept { return getCommonData().isVec(); }
+  //! Get if the instruction is SSE+ (SSE4.2, AES, SHA included) instruction that accesses XMM registers.
+  ASMJIT_INLINE bool isSse() const noexcept { return getCommonData().isSse(); }
+  //! Get if the instruction is AVX+ (FMA included) instruction that accesses XMM|YMM|ZMM registers.
+  ASMJIT_INLINE bool isAvx() const noexcept { return getCommonData().isAvx(); }
 
   //! Get if the instruction can be prefixed by LOCK prefix.
   ASMJIT_INLINE bool isLockEnabled() const noexcept { return getCommonData().isLockEnabled(); }
@@ -2372,7 +2385,7 @@ struct X86Inst {
   // [Get]
   // --------------------------------------------------------------------------
 
-  //! Get if the `instId` is defined (counts also kInvalidInstId, which is zero).
+  //! Get if the `instId` is defined (counts also Inst::kIdNone, which must be zero).
   static ASMJIT_INLINE bool isDefinedId(uint32_t instId) noexcept { return instId < _kIdCount; }
 
   //! Get instruction information based on the instruction `instId`.
@@ -2442,17 +2455,6 @@ struct X86Inst {
   ASMJIT_API static const char* getNameById(uint32_t instId) noexcept;
 #endif // !ASMJIT_DISABLE_TEXT
 
-  // --------------------------------------------------------------------------
-  // [Validation]
-  // --------------------------------------------------------------------------
-
-#if !defined(ASMJIT_DISABLE_VALIDATION)
-  ASMJIT_API static Error validate(
-    uint32_t archType, uint32_t instId, uint32_t options,
-    const Operand_& extraOp,
-    const Operand_* opArray, uint32_t opCount) noexcept;
-#endif // !ASMJIT_DISABLE_VALIDATION
-
   // --------------------------------------------------------------------------
   // [Members]
   // --------------------------------------------------------------------------
diff --git a/src/asmjit/x86/x86instimpl.cpp b/src/asmjit/x86/x86instimpl.cpp
new file mode 100644
index 0000000..a45fbed
--- /dev/null
+++ b/src/asmjit/x86/x86instimpl.cpp
@@ -0,0 +1,731 @@
+// [AsmJit]
+// Complete x86/x64 JIT and Remote Assembler for C++.
+//
+// [License]
+// Zlib - See LICENSE.md file in the package.
+
+// [Export]
+#define ASMJIT_EXPORTS
+
+// [Dependencies]
+#include "../base/misc_p.h"
+#include "../base/utils.h"
+#include "../x86/x86instimpl_p.h"
+#include "../x86/x86operand.h"
+
+// [Api-Begin]
+#include "../asmjit_apibegin.h"
+
+namespace asmjit {
+
+// ============================================================================
+// [asmjit::X86InstImpl - Validate]
+// ============================================================================
+
+#if !defined(ASMJIT_DISABLE_VALIDATION)
+template<uint32_t RegType>
+struct X86OpTypeFromRegTypeT {
+  enum {
+    kValue = (RegType == X86Reg::kRegGpbLo) ? X86Inst::kOpGpbLo :
+             (RegType == X86Reg::kRegGpbHi) ? X86Inst::kOpGpbHi :
+             (RegType == X86Reg::kRegGpw  ) ? X86Inst::kOpGpw   :
+             (RegType == X86Reg::kRegGpd  ) ? X86Inst::kOpGpd   :
+             (RegType == X86Reg::kRegGpq  ) ? X86Inst::kOpGpq   :
+             (RegType == X86Reg::kRegXmm  ) ? X86Inst::kOpXmm   :
+             (RegType == X86Reg::kRegYmm  ) ? X86Inst::kOpYmm   :
+             (RegType == X86Reg::kRegZmm  ) ? X86Inst::kOpZmm   :
+             (RegType == X86Reg::kRegRip  ) ? X86Inst::kOpNone  :
+             (RegType == X86Reg::kRegSeg  ) ? X86Inst::kOpSeg   :
+             (RegType == X86Reg::kRegFp   ) ? X86Inst::kOpFp    :
+             (RegType == X86Reg::kRegMm   ) ? X86Inst::kOpMm    :
+             (RegType == X86Reg::kRegK    ) ? X86Inst::kOpK     :
+             (RegType == X86Reg::kRegBnd  ) ? X86Inst::kOpBnd   :
+             (RegType == X86Reg::kRegCr   ) ? X86Inst::kOpCr    :
+             (RegType == X86Reg::kRegDr   ) ? X86Inst::kOpDr    : X86Inst::kOpNone
+  };
+};
+
+template<uint32_t RegType>
+struct X86RegMaskFromRegTypeT {
+  enum {
+    kMask = (RegType == X86Reg::kRegGpbLo) ? 0x0000000FU :
+            (RegType == X86Reg::kRegGpbHi) ? 0x0000000FU :
+            (RegType == X86Reg::kRegGpw  ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegGpd  ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegGpq  ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegXmm  ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegYmm  ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegZmm  ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegRip  ) ? 0x00000001U :
+            (RegType == X86Reg::kRegSeg  ) ? 0x0000007EU : // [ES|CS|SS|DS|FS|GS]
+            (RegType == X86Reg::kRegFp   ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegMm   ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegK    ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegBnd  ) ? 0x0000000FU :
+            (RegType == X86Reg::kRegCr   ) ? 0x0000FFFFU :
+            (RegType == X86Reg::kRegDr   ) ? 0x000000FFU : X86Inst::kOpNone
+  };
+};
+
+template<uint32_t RegType>
+struct X64RegMaskFromRegTypeT {
+  enum {
+    kMask = (RegType == X86Reg::kRegGpbLo) ? 0x0000FFFFU :
+            (RegType == X86Reg::kRegGpbHi) ? 0x0000000FU :
+            (RegType == X86Reg::kRegGpw  ) ? 0x0000FFFFU :
+            (RegType == X86Reg::kRegGpd  ) ? 0x0000FFFFU :
+            (RegType == X86Reg::kRegGpq  ) ? 0x0000FFFFU :
+            (RegType == X86Reg::kRegXmm  ) ? 0xFFFFFFFFU :
+            (RegType == X86Reg::kRegYmm  ) ? 0xFFFFFFFFU :
+            (RegType == X86Reg::kRegZmm  ) ? 0xFFFFFFFFU :
+            (RegType == X86Reg::kRegRip  ) ? 0x00000001U :
+            (RegType == X86Reg::kRegSeg  ) ? 0x0000007EU : // [ES|CS|SS|DS|FS|GS]
+            (RegType == X86Reg::kRegFp   ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegMm   ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegK    ) ? 0x000000FFU :
+            (RegType == X86Reg::kRegBnd  ) ? 0x0000000FU :
+            (RegType == X86Reg::kRegCr   ) ? 0x0000FFFFU :
+            (RegType == X86Reg::kRegDr   ) ? 0x0000FFFFU : X86Inst::kOpNone
+  };
+};
+
+struct X86ValidationData {
+  //! Allowed registers by reg-type (X86::kReg...).
+  uint32_t allowedRegMask[X86Reg::kRegMax + 1];
+  uint32_t allowedMemBaseRegs;
+  uint32_t allowedMemIndexRegs;
+};
+
+static const uint32_t _x86OpFlagFromRegType[X86Reg::kRegMax + 1] = {
+  ASMJIT_TABLE_T_32(X86OpTypeFromRegTypeT, kValue, 0)
+};
+
+static const X86ValidationData _x86ValidationData = {
+  { ASMJIT_TABLE_T_32(X86RegMaskFromRegTypeT, kMask, 0) },
+  (1U << X86Reg::kRegGpw) | (1U << X86Reg::kRegGpd) | (1U << X86Reg::kRegRip) | (1U << Label::kLabelTag),
+  (1U << X86Reg::kRegGpw) | (1U << X86Reg::kRegGpd) | (1U << X86Reg::kRegXmm) | (1U << X86Reg::kRegYmm) | (1U << X86Reg::kRegZmm)
+};
+
+static const X86ValidationData _x64ValidationData = {
+  { ASMJIT_TABLE_T_32(X64RegMaskFromRegTypeT, kMask, 0) },
+  (1U << X86Reg::kRegGpd) | (1U << X86Reg::kRegGpq) | (1U << X86Reg::kRegRip) | (1U << Label::kLabelTag),
+  (1U << X86Reg::kRegGpd) | (1U << X86Reg::kRegGpq) | (1U << X86Reg::kRegXmm) | (1U << X86Reg::kRegYmm) | (1U << X86Reg::kRegZmm)
+};
+
+static ASMJIT_INLINE bool x86CheckOSig(const X86Inst::OSignature& op, const X86Inst::OSignature& ref, bool& immOutOfRange) noexcept {
+  // Fail if operand types are incompatible.
+  uint32_t opFlags = op.flags;
+  if ((opFlags & ref.flags) == 0) {
+    // Mark temporarily `immOutOfRange` so we can return a more descriptive error.
+    if ((opFlags & X86Inst::kOpAllImm) && (ref.flags & X86Inst::kOpAllImm)) {
+      immOutOfRange = true;
+      return true;
+    }
+
+    return false;
+  }
+
+  // Fail if memory specific flags and sizes are incompatibles.
+  uint32_t opMemFlags = op.memFlags;
+  if (opMemFlags != 0) {
+    uint32_t refMemFlags = ref.memFlags;
+    if ((refMemFlags & opMemFlags) == 0)
+      return false;
+
+    if ((refMemFlags & X86Inst::kMemOpBaseOnly) && !(opMemFlags && X86Inst::kMemOpBaseOnly))
+      return false;
+  }
+
+  // Specific register index.
+  if (opFlags & X86Inst::kOpAllRegs) {
+    uint32_t refRegMask = ref.regMask;
+    if (refRegMask && !(op.regMask & refRegMask))
+      return false;
+  }
+
+  return true;
+}
+
+ASMJIT_FAVOR_SIZE Error X86InstImpl::validate(uint32_t archType, const Inst::Detail& detail, const Operand_* operands, uint32_t count) noexcept {
+  uint32_t i;
+  uint32_t archMask;
+  const X86ValidationData* vd;
+
+  if (!ArchInfo::isX86Family(archType))
+    return DebugUtils::errored(kErrorInvalidArch);
+
+  if (archType == ArchInfo::kTypeX86) {
+    vd = &_x86ValidationData;
+    archMask = X86Inst::kArchMaskX86;
+  }
+  else {
+    vd = &_x64ValidationData;
+    archMask = X86Inst::kArchMaskX64;
+  }
+
+  // Get the instruction data.
+  uint32_t instId = detail.instId;
+  uint32_t options = detail.options;
+
+  if (ASMJIT_UNLIKELY(instId >= X86Inst::_kIdCount))
+    return DebugUtils::errored(kErrorInvalidArgument);
+
+  const X86Inst* iData = &X86InstDB::instData[instId];
+  uint32_t iFlags = iData->getFlags();
+
+  // Validate LOCK, XACQUIRE, and XRELEASE prefixes.
+  const uint32_t kLockXAcqRel = X86Inst::kOptionXAcquire | X86Inst::kOptionXRelease;
+  if (options & (X86Inst::kOptionLock | kLockXAcqRel)) {
+    if (options & X86Inst::kOptionLock) {
+      if (ASMJIT_UNLIKELY(!(iFlags & X86Inst::kFlagLock) && !(options & kLockXAcqRel)))
+        return DebugUtils::errored(kErrorInvalidLockPrefix);
+
+      if (ASMJIT_UNLIKELY(count < 1 || !operands[0].isMem()))
+        return DebugUtils::errored(kErrorInvalidLockPrefix);
+    }
+
+    if (options & kLockXAcqRel) {
+      if (ASMJIT_UNLIKELY(!(options & X86Inst::kOptionLock) || (options & kLockXAcqRel) == kLockXAcqRel))
+        return DebugUtils::errored(kErrorInvalidPrefixCombination);
+
+      if (ASMJIT_UNLIKELY((options & X86Inst::kOptionXAcquire) && !(iFlags & X86Inst::kFlagXAcquire)))
+        return DebugUtils::errored(kErrorInvalidXAcquirePrefix);
+
+      if (ASMJIT_UNLIKELY((options & X86Inst::kOptionXRelease) && !(iFlags & X86Inst::kFlagXRelease)))
+        return DebugUtils::errored(kErrorInvalidXReleasePrefix);
+    }
+  }
+
+  // Validate REP and REPNZ prefixes.
+  const uint32_t kRepRepRepnz = X86Inst::kOptionRep | X86Inst::kOptionRepnz;
+  if (options & kRepRepRepnz) {
+    if (ASMJIT_UNLIKELY((options & kRepRepRepnz) == kRepRepRepnz))
+      return DebugUtils::errored(kErrorInvalidPrefixCombination);
+
+    if (ASMJIT_UNLIKELY((options & X86Inst::kOptionRep) && !(iFlags & X86Inst::kFlagRep)))
+      return DebugUtils::errored(kErrorInvalidRepPrefix);
+
+    if (ASMJIT_UNLIKELY((options & X86Inst::kOptionRepnz) && !(iFlags & X86Inst::kFlagRepnz)))
+      return DebugUtils::errored(kErrorInvalidRepPrefix);
+
+    // TODO: Validate extraReg {cx|ecx|rcx}.
+  }
+
+  // Translate the given operands to `X86Inst::OSignature`.
+  X86Inst::OSignature oSigTranslated[6];
+  uint32_t combinedOpFlags = 0;
+  uint32_t combinedRegMask = 0;
+
+  const X86Mem* memOp = nullptr;
+
+  for (i = 0; i < count; i++) {
+    const Operand_& op = operands[i];
+    if (op.getOp() == Operand::kOpNone) break;
+
+    uint32_t opFlags = 0;
+    uint32_t memFlags = 0;
+    uint32_t regMask = 0;
+
+    switch (op.getOp()) {
+      case Operand::kOpReg: {
+        uint32_t regType = op.as<Reg>().getType();
+        if (ASMJIT_UNLIKELY(regType >= X86Reg::kRegCount))
+          return DebugUtils::errored(kErrorInvalidRegType);
+
+        opFlags = _x86OpFlagFromRegType[regType];
+        if (ASMJIT_UNLIKELY(opFlags == 0))
+          return DebugUtils::errored(kErrorInvalidRegType);
+
+        // If `regId` is equal or greater than Operand::kPackedIdMin it means
+        // that the register is virtual and its index will be assigned later
+        // by the register allocator. We must pass unless asked to disallow
+        // virtual registers.
+        // TODO: We need an option to refuse virtual regs here.
+        uint32_t regId = op.getId();
+        if (regId < Operand::kPackedIdMin) {
+          if (ASMJIT_UNLIKELY(regId >= 32))
+            return DebugUtils::errored(kErrorInvalidPhysId);
+
+          regMask = Utils::mask(regId);
+          if (ASMJIT_UNLIKELY((vd->allowedRegMask[regType] & regMask) == 0))
+            return DebugUtils::errored(kErrorInvalidPhysId);
+
+          combinedRegMask |= regMask;
+        }
+        else {
+          regMask = 0xFFFFFFFFU;
+        }
+        break;
+      }
+
+      // TODO: Validate base and index and combine with `combinedRegMask`.
+      case Operand::kOpMem: {
+        const X86Mem& m = op.as<X86Mem>();
+
+        uint32_t baseType = m.getBaseType();
+        uint32_t indexType = m.getIndexType();
+
+        memOp = &m;
+
+        if (m.getSegmentId() > 6)
+          return DebugUtils::errored(kErrorInvalidSegment);
+
+        if (baseType) {
+          uint32_t baseId = m.getBaseId();
+
+          if (m.isRegHome()) {
+            // Home address of virtual register. In such case we don't want to
+            // validate the type of the base register as it will always be patched
+            // to ESP|RSP.
+          }
+          else {
+            if (ASMJIT_UNLIKELY((vd->allowedMemBaseRegs & (1U << baseType)) == 0))
+              return DebugUtils::errored(kErrorInvalidAddress);
+          }
+
+          // Create information that will be validated only if this is an implicit
+          // memory operand. Basically only usable for string instructions and other
+          // instructions where memory operand is implicit and has 'seg:[reg]' form.
+          if (baseId < Operand::kPackedIdMin) {
+            // Physical base id.
+            regMask = Utils::mask(baseId);
+            combinedRegMask |= regMask;
+          }
+          else {
+            // Virtual base id - will the whole mask for implicit mem validation.
+            // The register is not assigned yet, so we cannot predict the phys id.
+            regMask = 0xFFFFFFFFU;
+          }
+
+          if (!indexType && !m.getOffsetLo32())
+            memFlags |= X86Inst::kMemOpBaseOnly;
+        }
+        else {
+          // Base is an address, make sure that the address doesn't overflow 32-bit
+          // integer (either int32_t or uint32_t) in 32-bit targets.
+          int64_t offset = m.getOffset();
+          if (archMask == X86Inst::kArchMaskX86 && !Utils::isInt32(offset) && !Utils::isUInt32(offset))
+            return DebugUtils::errored(kErrorInvalidAddress);
+        }
+
+        if (indexType) {
+          if (ASMJIT_UNLIKELY((vd->allowedMemIndexRegs & (1U << indexType)) == 0))
+            return DebugUtils::errored(kErrorInvalidAddress);
+
+          if (indexType == X86Reg::kRegXmm) {
+            opFlags |= X86Inst::kOpVm;
+            memFlags |= X86Inst::kMemOpVm32x | X86Inst::kMemOpVm64x;
+          }
+          else if (indexType == X86Reg::kRegYmm) {
+            opFlags |= X86Inst::kOpVm;
+            memFlags |= X86Inst::kMemOpVm32y | X86Inst::kMemOpVm64y;
+          }
+          else if (indexType == X86Reg::kRegZmm) {
+            opFlags |= X86Inst::kOpVm;
+            memFlags |= X86Inst::kMemOpVm32z | X86Inst::kMemOpVm64z;
+          }
+          else {
+            opFlags |= X86Inst::kOpMem;
+            if (baseType)
+              memFlags |= X86Inst::kMemOpMib;
+          }
+
+          // [RIP + {XMM|YMM|ZMM}] is not allowed.
+          if (baseType == X86Reg::kRegRip && (opFlags & X86Inst::kOpVm))
+            return DebugUtils::errored(kErrorInvalidAddress);
+
+          uint32_t indexId = m.getIndexId();
+          if (indexId < Operand::kPackedIdMin)
+            combinedRegMask |= Utils::mask(indexId);
+
+          // Only used for implicit memory operands having 'seg:[reg]' form, so clear it.
+          regMask = 0;
+        }
+        else {
+          opFlags |= X86Inst::kOpMem;
+        }
+
+        switch (m.getSize()) {
+          case  0: memFlags |= X86Inst::kMemOpAny ; break;
+          case  1: memFlags |= X86Inst::kMemOpM8  ; break;
+          case  2: memFlags |= X86Inst::kMemOpM16 ; break;
+          case  4: memFlags |= X86Inst::kMemOpM32 ; break;
+          case  6: memFlags |= X86Inst::kMemOpM48 ; break;
+          case  8: memFlags |= X86Inst::kMemOpM64 ; break;
+          case 10: memFlags |= X86Inst::kMemOpM80 ; break;
+          case 16: memFlags |= X86Inst::kMemOpM128; break;
+          case 32: memFlags |= X86Inst::kMemOpM256; break;
+          case 64: memFlags |= X86Inst::kMemOpM512; break;
+          default:
+            return DebugUtils::errored(kErrorInvalidOperandSize);
+        }
+
+        break;
+      }
+
+      case Operand::kOpImm: {
+        uint64_t immValue = op.as<Imm>().getUInt64();
+        uint32_t immFlags = 0;
+
+        if (static_cast<int64_t>(immValue) >= 0) {
+          const uint32_t k32AndMore = X86Inst::kOpI32 | X86Inst::kOpU32 |
+                                      X86Inst::kOpI64 | X86Inst::kOpU64 ;
+
+          if (immValue <= 0xFU)
+            immFlags = X86Inst::kOpU4 | X86Inst::kOpI8 | X86Inst::kOpU8 | X86Inst::kOpI16 | X86Inst::kOpU16 | k32AndMore;
+          else if (immValue <= 0x7FU)
+            immFlags = X86Inst::kOpI8 | X86Inst::kOpU8 | X86Inst::kOpI16 | X86Inst::kOpU16 | k32AndMore;
+          else if (immValue <= 0xFFU)
+            immFlags = X86Inst::kOpU8 | X86Inst::kOpI16 | X86Inst::kOpU16 | k32AndMore;
+          else if (immValue <= 0x7FFFU)
+            immFlags = X86Inst::kOpI16 | X86Inst::kOpU16 | k32AndMore;
+          else if (immValue <= 0xFFFFU)
+            immFlags = X86Inst::kOpU16 | k32AndMore;
+          else if (immValue <= 0x7FFFFFFFU)
+            immFlags = k32AndMore;
+          else if (immValue <= 0xFFFFFFFFU)
+            immFlags = X86Inst::kOpU32 | X86Inst::kOpI64 | X86Inst::kOpU64;
+          else if (immValue <= ASMJIT_UINT64_C(0x7FFFFFFFFFFFFFFF))
+            immFlags = X86Inst::kOpI64 | X86Inst::kOpU64;
+          else
+            immFlags = X86Inst::kOpU64;
+        }
+        else {
+          // 2s complement negation, as our number is unsigned...
+          immValue = (~immValue + 1);
+
+          if (immValue <= 0x80U)
+            immFlags = X86Inst::kOpI8 | X86Inst::kOpI16 | X86Inst::kOpI32 | X86Inst::kOpI64;
+          else if (immValue <= 0x8000U)
+            immFlags = X86Inst::kOpI16 | X86Inst::kOpI32 | X86Inst::kOpI64;
+          else if (immValue <= 0x80000000U)
+            immFlags = X86Inst::kOpI32 | X86Inst::kOpI64;
+          else
+            immFlags = X86Inst::kOpI64;
+        }
+        opFlags |= immFlags;
+        break;
+      }
+
+      case Operand::kOpLabel: {
+        opFlags |= X86Inst::kOpRel8 | X86Inst::kOpRel32;
+        break;
+      }
+
+      default:
+        return DebugUtils::errored(kErrorInvalidState);
+    }
+
+    X86Inst::OSignature& tod = oSigTranslated[i];
+    tod.flags = opFlags;
+    tod.memFlags = static_cast<uint16_t>(memFlags);
+    tod.regMask = static_cast<uint8_t>(regMask & 0xFFU);
+    combinedOpFlags |= opFlags;
+  }
+
+  // Decrease the number of operands of those that are none. This is important
+  // as Assembler and CodeCompiler may just pass more operands where some of
+  // them are none (it means that no operand is given at that index). However,
+  // validate that there are no gaps (like [reg, none, reg] or [none, reg]).
+  if (i < count) {
+    while (--count > i)
+      if (ASMJIT_UNLIKELY(!operands[count].isNone()))
+        return DebugUtils::errored(kErrorInvalidState);
+  }
+
+  // Validate X86 and X64 specific cases.
+  if (archMask == X86Inst::kArchMaskX86) {
+    // Illegal use of 64-bit register in 32-bit mode.
+    if (ASMJIT_UNLIKELY((combinedOpFlags & X86Inst::kOpGpq) != 0))
+      return DebugUtils::errored(kErrorInvalidUseOfGpq);
+  }
+  else {
+    // Illegal use of a high 8-bit register with REX prefix.
+    if (ASMJIT_UNLIKELY((combinedOpFlags & X86Inst::kOpGpbHi) != 0 && (combinedRegMask & 0xFFFFFF00U) != 0))
+      return DebugUtils::errored(kErrorInvalidUseOfGpbHi);
+  }
+
+  // Validate instruction operands.
+  const X86Inst::CommonData* commonData = &iData->getCommonData();
+  const X86Inst::ISignature* iSig = X86InstDB::iSignatureData + commonData->_iSignatureIndex;
+  const X86Inst::ISignature* iEnd = iSig                      + commonData->_iSignatureCount;
+
+  if (iSig != iEnd) {
+    const X86Inst::OSignature* oSigData = X86InstDB::oSignatureData;
+
+    // If set it means that we matched a signature where only immediate value
+    // was out of bounds. We can return a more descriptive error if we know this.
+    bool globalImmOutOfRange = false;
+
+    do {
+      // Check if the architecture is compatible.
+      if ((iSig->archMask & archMask) == 0) continue;
+
+      // Compare the operands table with reference operands.
+      uint32_t j = 0;
+      uint32_t iSigCount = iSig->opCount;
+      bool localImmOutOfRange = false;
+
+      if (iSigCount == count) {
+        for (j = 0; j < count; j++)
+          if (!x86CheckOSig(oSigTranslated[j], oSigData[iSig->operands[j]], localImmOutOfRange))
+            break;
+      }
+      else if (iSigCount - iSig->implicit == count) {
+        uint32_t r = 0;
+        for (j = 0; j < count && r < iSigCount; j++, r++) {
+          const X86Inst::OSignature* oChk = oSigTranslated + j;
+          const X86Inst::OSignature* oRef;
+Next:
+          oRef = oSigData + iSig->operands[r];
+          // Skip implicit.
+          if ((oRef->flags & X86Inst::kOpImplicit) != 0) {
+            if (++r >= iSigCount)
+              break;
+            else
+              goto Next;
+          }
+
+          if (!x86CheckOSig(*oChk, *oRef, localImmOutOfRange))
+            break;
+        }
+      }
+
+      if (j == count) {
+        if (!localImmOutOfRange) {
+          // Match, must clear possible `globalImmOutOfRange`.
+          globalImmOutOfRange = false;
+          break;
+        }
+        globalImmOutOfRange = localImmOutOfRange;
+      }
+    } while (++iSig != iEnd);
+
+    if (iSig == iEnd) {
+      if (globalImmOutOfRange)
+        return DebugUtils::errored(kErrorInvalidImmediate);
+      else
+        return DebugUtils::errored(kErrorInvalidInstruction);
+    }
+  }
+
+  // Validate AVX-512 options:
+  const RegOnly& extraReg = detail.extraReg;
+  const uint32_t kAvx512Options = X86Inst::kOptionZMask   |
+                                  X86Inst::kOption1ToX    |
+                                  X86Inst::kOptionER      |
+                                  X86Inst::kOptionSAE     ;
+
+  if (!extraReg.isNone() || (options & kAvx512Options)) {
+    if (commonData->hasFlag(X86Inst::kFlagEvex)) {
+      // Validate AVX-512 {k} and {k}{z}.
+      if (!extraReg.isNone()) {
+        // Mask can only be specified by a 'k' register.
+        if (ASMJIT_UNLIKELY(extraReg.getType() != X86Reg::kRegK))
+          return DebugUtils::errored(kErrorInvalidKMaskReg);
+
+        if (ASMJIT_UNLIKELY(!commonData->hasAvx512K()))
+          return DebugUtils::errored(kErrorInvalidKMaskUse);
+      }
+
+      if ((options & X86Inst::kOptionZMask)) {
+        if (ASMJIT_UNLIKELY((options & X86Inst::kOptionZMask) != 0 && !commonData->hasAvx512Z()))
+          return DebugUtils::errored(kErrorInvalidKZeroUse);
+      }
+
+      // Validate AVX-512 broadcast {1tox}.
+      if (options & X86Inst::kOption1ToX) {
+        if (ASMJIT_UNLIKELY(!memOp))
+          return DebugUtils::errored(kErrorInvalidBroadcast);
+
+        uint32_t size = memOp->getSize();
+        if (size != 0) {
+          // The the size is specified it has to match the broadcast size.
+          if (ASMJIT_UNLIKELY(commonData->hasAvx512B32() && size != 4))
+            return DebugUtils::errored(kErrorInvalidBroadcast);
+
+          if (ASMJIT_UNLIKELY(commonData->hasAvx512B64() && size != 8))
+            return DebugUtils::errored(kErrorInvalidBroadcast);
+        }
+      }
+
+      // Validate AVX-512 {sae} and {er}.
+      if (options & (X86Inst::kOptionSAE | X86Inst::kOptionER)) {
+        // Rounding control is impossible if the instruction is not reg-to-reg.
+        if (ASMJIT_UNLIKELY(memOp))
+          return DebugUtils::errored(kErrorInvalidEROrSAE);
+
+        // Check if {sae} or {er} is supported by the instruction.
+        if (options & X86Inst::kOptionER) {
+          // NOTE: if both {sae} and {er} are set, we don't care, as {sae} is implied.
+          if (ASMJIT_UNLIKELY(!commonData->hasAvx512ER()))
+            return DebugUtils::errored(kErrorInvalidEROrSAE);
+
+          // {er} is defined for scalar ops or vector ops using zmm (LL = 10). We
+          // don't need any more bits in the instruction database to be able to
+          // validate this, as each AVX512 instruction that has broadcast is vector
+          // instruction (in this case we require zmm registers), otherwise it's a
+          // scalar instruction, which is valid.
+          if (commonData->hasAvx512B()) {
+            // Supports broadcast, thus we require LL to be '10', which means there
+            // have to be zmm registers used. We don't calculate LL here, but we know
+            // that it would be '10' if there is at least one ZMM register used.
+
+            // There is no 'ER' enabled instruction with less than two operands.
+            ASMJIT_ASSERT(count >= 2);
+            if (ASMJIT_UNLIKELY(!X86Reg::isZmm(operands[0]) && !X86Reg::isZmm(operands[1])))
+              return DebugUtils::errored(kErrorInvalidEROrSAE);
+          }
+        }
+        else {
+          // {sae} doesn't have the same limitations as {er}, this is enough.
+          if (ASMJIT_UNLIKELY(!commonData->hasAvx512SAE()))
+            return DebugUtils::errored(kErrorInvalidEROrSAE);
+        }
+      }
+    }
+    else {
+      // Not AVX512 instruction - maybe OpExtra is xCX register used by REP/REPNZ prefix. Otherwise the instruction is invalid.
+      if ((options & kAvx512Options) || (options & (X86Inst::kOptionRep | X86Inst::kOptionRepnz)) == 0)
+        return DebugUtils::errored(kErrorInvalidInstruction);
+    }
+  }
+
+  return kErrorOk;
+}
+#endif
+
+// ============================================================================
+// [asmjit::X86InstImpl - CheckFeatures]
+// ============================================================================
+
+#if !defined(ASMJIT_DISABLE_EXTENSIONS)
+ASMJIT_FAVOR_SIZE static uint32_t x86GetRegTypesMask(const Operand_* operands, uint32_t count) noexcept {
+  uint32_t mask = 0;
+  for (uint32_t i = 0; i < count; i++) {
+    const Operand_& op = operands[i];
+    if (op.isReg()) {
+      const Reg& reg = op.as<Reg>();
+      mask |= Utils::mask(reg.getType());
+    }
+    else if (op.isMem()) {
+      const Mem& mem = op.as<Mem>();
+      if (mem.hasBaseReg()) mask |= Utils::mask(mem.getBaseType());
+      if (mem.hasIndexReg()) mask |= Utils::mask(mem.getIndexType());
+    }
+  }
+  return mask;
+}
+
+ASMJIT_FAVOR_SIZE Error X86InstImpl::checkFeatures(uint32_t archType, const Inst::Detail& detail, const Operand_* operands, uint32_t count, CpuFeatures& out) noexcept {
+  if (!ArchInfo::isX86Family(archType))
+    return DebugUtils::errored(kErrorInvalidArch);
+
+  // Get the instruction data.
+  uint32_t instId = detail.instId;
+  if (ASMJIT_UNLIKELY(instId >= X86Inst::_kIdCount))
+    return DebugUtils::errored(kErrorInvalidArgument);
+
+  const X86Inst* iData = &X86InstDB::instData[instId];
+  const X86Inst::OperationData& od = iData->getOperationData();
+
+  const uint8_t* fData = od.getFeaturesData();
+  const uint8_t* fEnd = od.getFeaturesEnd();
+
+  // Copy all features to `out`.
+  out.reset();
+  do {
+    uint32_t feature = fData[0];
+    if (!feature)
+      break;
+    out.add(feature);
+  } while (++fData != fEnd);
+
+  // Since AsmJit merges all instructions that share the same name we have to
+  // deal with some special cases and also with MMX/SSE and AVX/AVX2 overlaps.
+
+  // Only proceed if there were some CPU flags set.
+  if (fData != od.getFeaturesData()) {
+    uint32_t mask = x86GetRegTypesMask(operands, count);
+
+    // Check for MMX vs SSE overlap.
+    if (out.has(CpuInfo::kX86FeatureMMX) || out.has(CpuInfo::kX86FeatureMMX2)) {
+      // Only instructions defined by SSE and SSE2 overlap. Instructions introduced
+      // by newer instruction sets like SSE3+ don't state MMX as they require SSE3+.
+      if (out.has(CpuInfo::kX86FeatureSSE) || out.has(CpuInfo::kX86FeatureSSE2)) {
+        if (!(mask & Utils::mask(X86Reg::kRegXmm))) {
+          // The instruction doesn't use XMM register(s), thus it's MMX/MMX2 only.
+          out.remove(CpuInfo::kX86FeatureSSE);
+          out.remove(CpuInfo::kX86FeatureSSE2);
+        }
+        else {
+          out.remove(CpuInfo::kX86FeatureMMX);
+          out.remove(CpuInfo::kX86FeatureMMX2);
+        }
+
+        // Special case: PEXTRW instruction is MMX/SSE2 instruction. However, this
+        // instruction couldn't access memory (only register to register extract) so
+        // when SSE4.1 introduced the whole family of PEXTR/PINSR instructions they
+        // also introduced PEXTRW with a new opcode 0x15 that can extract directly to
+        // memory. This instruction is, of course, not compatible with MMX/SSE2 one.
+        if (instId == X86Inst::kIdPextrw && count > 0 && !operands[0].isMem()) {
+          out.remove(CpuInfo::kX86FeatureSSE4_1);
+        }
+      }
+    }
+
+    // Check for AVX vs AVX2 overlap.
+    if (out.has(CpuInfo::kX86FeatureAVX) && out.has(CpuInfo::kX86FeatureAVX2)) {
+      bool isAVX2 = true;
+      // Special case: VBROADCASTSS and VBROADCASTSD were introduced in AVX, but
+      // only version that uses memory as a source operand. AVX2 then added support
+      // for register source operand.
+      if (instId == X86Inst::kIdVbroadcastss || instId == X86Inst::kIdVbroadcastsd) {
+        if (count > 1 && operands[0].isMem())
+          isAVX2 = false;
+      }
+      else {
+        // AVX instruction set doesn't support integer operations on YMM registers
+        // as these were later introcuced by AVX2. In our case we have to check if
+        // YMM register(s) are in use and if that is the case this is an AVX2 instruction.
+        if (!(mask & Utils::mask(X86Reg::kRegYmm, X86Reg::kRegZmm)))
+          isAVX2 = false;
+      }
+
+      if (isAVX2)
+        out.remove(CpuInfo::kX86FeatureAVX);
+      else
+        out.remove(CpuInfo::kX86FeatureAVX2);
+    }
+
+    // Check for AVX|AVX2|FMA|F16C vs AVX512 overlap.
+    if (out.has(CpuInfo::kX86FeatureAVX) || out.has(CpuInfo::kX86FeatureAVX2) || out.has(CpuInfo::kX86FeatureFMA) || out.has(CpuInfo::kX86FeatureF16C)) {
+      // Only AVX512-F|BW|DQ allow to encode AVX/AVX2 instructions
+      if (out.has(CpuInfo::kX86FeatureAVX512_F) || out.has(CpuInfo::kX86FeatureAVX512_BW) || out.has(CpuInfo::kX86FeatureAVX512_DQ)) {
+        uint32_t options = detail.options;
+        uint32_t kAvx512Options = X86Inst::kOptionEvex | X86Inst::_kOptionAvx512Mask;
+
+        if (!(mask & Utils::mask(X86Reg::kRegZmm, X86Reg::kRegK)) && !(options & (kAvx512Options)) && detail.extraReg.getType() != X86Reg::kRegK) {
+          out.remove(CpuInfo::kX86FeatureAVX512_F)
+             .remove(CpuInfo::kX86FeatureAVX512_BW)
+             .remove(CpuInfo::kX86FeatureAVX512_DQ)
+             .remove(CpuInfo::kX86FeatureAVX512_VL);
+        }
+      }
+    }
+
+    // Remove or keep AVX512_VL feature.
+    if (out.has(CpuInfo::kX86FeatureAVX512_VL)) {
+      if (!(mask & Utils::mask(X86Reg::kRegZmm)))
+        out.remove(CpuInfo::kX86FeatureAVX512_VL);
+    }
+  }
+
+  return kErrorOk;
+}
+#endif
+
+} // asmjit namespace
+
+// [Api-End]
+#include "../asmjit_apiend.h"
diff --git a/src/asmjit/x86/x86instimpl_p.h b/src/asmjit/x86/x86instimpl_p.h
new file mode 100644
index 0000000..40a8130
--- /dev/null
+++ b/src/asmjit/x86/x86instimpl_p.h
@@ -0,0 +1,45 @@
+// [AsmJit]
+// Complete x86/x64 JIT and Remote Assembler for C++.
+//
+// [License]
+// Zlib - See LICENSE.md file in the package.
+
+// [Guard]
+#ifndef _ASMJIT_X86_X86INSTIMPL_P_H
+#define _ASMJIT_X86_X86INSTIMPL_P_H
+
+// [Dependencies]
+#include "../x86/x86inst.h"
+
+// [Api-Begin]
+#include "../asmjit_apibegin.h"
+
+namespace asmjit {
+
+//! \addtogroup asmjit_x86
+//! \{
+
+//! \internal
+//!
+//! Contains X86/X64 specific implementation of APIs provided by `asmjit::Inst`.
+//!
+//! The purpose of `X86InstImpl` is to move most of the logic out of `X86Inst`.
+struct X86InstImpl {
+  #if !defined(ASMJIT_DISABLE_VALIDATION)
+  static Error validate(uint32_t archType, const Inst::Detail& detail, const Operand_* operands, uint32_t count) noexcept;
+  #endif
+
+  #if !defined(ASMJIT_DISABLE_EXTENSIONS)
+  static Error checkFeatures(uint32_t archType, const Inst::Detail& detail, const Operand_* operands, uint32_t count, CpuFeatures& out) noexcept;
+  #endif
+};
+
+//! \}
+
+} // asmjit namespace
+
+// [Api-End]
+#include "../asmjit_apiend.h"
+
+// [Guard]
+#endif // _ASMJIT_X86_X86INSTIMPL_P_H
diff --git a/src/asmjit/x86/x86internal.cpp b/src/asmjit/x86/x86internal.cpp
index 2e46f37..e0b3836 100644
--- a/src/asmjit/x86/x86internal.cpp
+++ b/src/asmjit/x86/x86internal.cpp
@@ -725,7 +725,7 @@ ASMJIT_FAVOR_SIZE Error X86Internal::emitRegMove(X86Emitter* emitter,
   Operand dst(dst_);
   Operand src(src_);
 
-  uint32_t instId = Globals::kInvalidInstId;
+  uint32_t instId = Inst::kIdNone;
   uint32_t memFlags = 0;
 
   enum MemFlags {
@@ -831,7 +831,7 @@ ASMJIT_FAVOR_SIZE Error X86Internal::emitArgMove(X86Emitter* emitter,
   uint32_t dstSize = TypeId::sizeOf(dstTypeId);
   uint32_t srcSize = TypeId::sizeOf(srcTypeId);
 
-  int32_t instId = Globals::kInvalidInstId;
+  int32_t instId = Inst::kIdNone;
 
   // Not a real loop, just 'break' is nicer than 'goto'.
   for (;;) {
diff --git a/src/asmjit/x86/x86logging.cpp b/src/asmjit/x86/x86logging.cpp
index 301efb3..e54ae06 100644
--- a/src/asmjit/x86/x86logging.cpp
+++ b/src/asmjit/x86/x86logging.cpp
@@ -580,10 +580,10 @@ ASMJIT_FAVOR_SIZE Error X86Logging::formatInstruction(
   uint32_t logOptions,
   const CodeEmitter* emitter,
   uint32_t archType,
-  uint32_t instId,
-  uint32_t options,
-  const Operand_& extraOp,
-  const Operand_* opArray, uint32_t opCount) noexcept {
+  const Inst::Detail& detail, const Operand_* opArray, uint32_t opCount) noexcept {
+
+  uint32_t instId = detail.instId;
+  uint32_t options = detail.options;
 
   // Format instruction options and instruction mnemonic.
   if (instId < X86Inst::_kIdCount) {
@@ -601,9 +601,9 @@ ASMJIT_FAVOR_SIZE Error X86Logging::formatInstruction(
     // REP|REPNZ options.
     if (options & (X86Inst::kOptionRep | X86Inst::kOptionRepnz)) {
       sb.appendString((options & X86Inst::kOptionRep) ? "rep " : "repnz ");
-      if (!extraOp.isNone()) {
+      if (detail.hasExtraReg()) {
         ASMJIT_PROPAGATE(sb.appendChar('{'));
-        ASMJIT_PROPAGATE(formatOperand(sb, logOptions, emitter, archType, extraOp));
+        ASMJIT_PROPAGATE(formatOperand(sb, logOptions, emitter, archType, detail.extraReg.toReg<Reg>()));
         ASMJIT_PROPAGATE(sb.appendString("} "));
       }
     }
@@ -654,9 +654,9 @@ ASMJIT_FAVOR_SIZE Error X86Logging::formatInstruction(
 
     // Support AVX-512 {k}{z}.
     if (i == 0) {
-      if (X86Reg::isK(extraOp)) {
+      if (detail.extraReg.getKind() == X86Reg::kKindK) {
         ASMJIT_PROPAGATE(sb.appendString(" {"));
-        ASMJIT_PROPAGATE(formatOperand(sb, logOptions, emitter, archType, extraOp));
+        ASMJIT_PROPAGATE(formatOperand(sb, logOptions, emitter, archType, detail.extraReg.toReg<Reg>()));
         ASMJIT_PROPAGATE(sb.appendChar('}'));
 
         if (options & X86Inst::kOptionZMask)
diff --git a/src/asmjit/x86/x86logging_p.h b/src/asmjit/x86/x86logging_p.h
index 1639359..3163206 100644
--- a/src/asmjit/x86/x86logging_p.h
+++ b/src/asmjit/x86/x86logging_p.h
@@ -48,10 +48,7 @@ struct X86Logging {
     uint32_t logOptions,
     const CodeEmitter* emitter,
     uint32_t archType,
-    uint32_t instId,
-    uint32_t options,
-    const Operand_& extraOp,
-    const Operand_* opArray, uint32_t opCount) noexcept;
+    const Inst::Detail& detail, const Operand_* opArray, uint32_t opCount) noexcept;
 };
 
 //! \}
diff --git a/src/asmjit/x86/x86regalloc.cpp b/src/asmjit/x86/x86regalloc.cpp
index 9e77fcb..48c73d6 100644
--- a/src/asmjit/x86/x86regalloc.cpp
+++ b/src/asmjit/x86/x86regalloc.cpp
@@ -1723,9 +1723,9 @@ _NextGroup:
             _avxEnabled = true;
         }
 
-        const Operand_& extraOp = node->getExtraOp();
-        if (extraOp.isReg()) {
-          uint32_t id = extraOp.as<Reg>().getId();
+        const RegOnly& extraReg = node->getExtraReg();
+        if (extraReg.isValid()) {
+          uint32_t id = extraReg.getId();
           if (cc()->isVirtRegValid(id)) {
             VirtReg* vreg = cc()->getVirtRegById(id);
             TiedReg* tied;
@@ -2117,10 +2117,7 @@ Error X86RAPass::annotate() {
           0,
           cc(),
           cc()->getArchType(),
-          node->getInstId(),
-          node->getOptions(),
-          node->getExtraOp(),
-          node->getOpArray(), node->getOpCount());
+          node->getInstDetail(), node->getOpArray(), node->getOpCount());
 
         node_->setInlineComment(
           static_cast<char*>(dataZone.dup(sb.getData(), sb.getLength(), true)));
@@ -2423,8 +2420,11 @@ Error X86VarAlloc::run(CBNode* node_) {
     // Translate node operands.
     if (node_->getType() == CBNode::kNodeInst) {
       CBInst* node = static_cast<CBInst*>(node_);
-      if (node->hasExtraOp())
-        ASMJIT_PROPAGATE(X86RAPass_translateOperands(_context, &node->_extraOp, 1));
+      if (node->hasExtraOp()) {
+        Reg reg = node->getExtraReg().toReg<Reg>();
+        ASMJIT_PROPAGATE(X86RAPass_translateOperands(_context, &reg, 1));
+        node->setExtraReg(reg);
+      }
       ASMJIT_PROPAGATE(X86RAPass_translateOperands(_context, node->getOpArray(), node->getOpCount()));
     }
     else if (node_->getType() == CBNode::kNodePushArg) {
diff --git a/test/asmjit_test_unit.cpp b/test/asmjit_test_unit.cpp
index 1cc2a7e..8b6501a 100644
--- a/test/asmjit_test_unit.cpp
+++ b/test/asmjit_test_unit.cpp
@@ -114,6 +114,8 @@ static void dumpCpu(void) {
     { CpuInfo::kX86FeatureSMEP            , "SMEP"                 },
     { CpuInfo::kX86FeatureSHA             , "SHA"                  },
     { CpuInfo::kX86FeatureXSAVE           , "XSAVE"                },
+    { CpuInfo::kX86FeatureXSAVEC          , "XSAVEC"               },
+    { CpuInfo::kX86FeatureXSAVES          , "XSAVES"               },
     { CpuInfo::kX86FeatureXSAVEOPT        , "XSAVEOPT"             },
     { CpuInfo::kX86FeatureOSXSAVE         , "OSXSAVE"              },
     { CpuInfo::kX86FeatureAVX             , "AVX"                  },
diff --git a/tools/generate-x86.js b/tools/generate-x86.js
index 764df71..976256c 100644
--- a/tools/generate-x86.js
+++ b/tools/generate-x86.js
@@ -1639,7 +1639,7 @@ class X86Generator extends base.BaseGenerator {
     }
 
     var s = `#define F(VAL) X86Inst::kFlag##VAL\n` +
-            `#define JUMP_TYPE(VAL) AnyInst::kJumpType##VAL\n` +
+            `#define JUMP_TYPE(VAL) Inst::kJumpType##VAL\n` +
             `#define SINGLE_REG(VAL) X86Inst::kSingleReg##VAL\n` +
             `const X86Inst::CommonData X86InstDB::commonData[] = {\n${StringUtils.format(table, kIndent, true)}\n};\n` +
             `#undef SINGLE_REG\n` +