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[Bug] Fixed X86 instruction info query asserting on MMX variation of pextrw (Fixes #330)

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This commit is contained in:
kobalicek
2021-03-19 09:31:12 +01:00
parent e822fba53e
commit e7a728018e
2 changed files with 17 additions and 48 deletions
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4
src/asmjit/x86/x86instapi.cpp
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@@ -1519,6 +1519,7 @@ Error InstInternal::queryFeatures(uint32_t arch, const BaseInst& inst, const Ope
// The instruction doesn't use XMM register(s), thus it's MMX/MMX2 only. // The instruction doesn't use XMM register(s), thus it's MMX/MMX2 only.
out->remove(Features::kSSE); out->remove(Features::kSSE);
out->remove(Features::kSSE2); out->remove(Features::kSSE2);
out->remove(Features::kSSE4_1);
} }
else { else {
out->remove(Features::kMMX); out->remove(Features::kMMX);
@@ -1532,9 +1533,6 @@ Error InstInternal::queryFeatures(uint32_t arch, const BaseInst& inst, const Ope
// can extract directly to memory. This instruction is, of course, not // can extract directly to memory. This instruction is, of course, not
// compatible with MMX/SSE2 and would #UD if SSE4.1 is not supported. // compatible with MMX/SSE2 and would #UD if SSE4.1 is not supported.
if (instId == Inst::kIdPextrw) { if (instId == Inst::kIdPextrw) {
ASMJIT_ASSERT(out->has(Features::kSSE2));
ASMJIT_ASSERT(out->has(Features::kSSE4_1));
if (opCount >= 1 && operands[0].isMem()) if (opCount >= 1 && operands[0].isMem())
out->remove(Features::kSSE2); out->remove(Features::kSSE2);
else else

61
test/asmjit_test_instinfo.cpp
View File

@@ -158,57 +158,28 @@ static void printInfoExtra(uint32_t arch, uint32_t instId, uint32_t options, con
static void testX86Arch() { static void testX86Arch() {
#if defined(ASMJIT_BUILD_X86) #if defined(ASMJIT_BUILD_X86)
using namespace x86;
uint32_t arch = Environment::kArchX64; uint32_t arch = Environment::kArchX64;
printInfoSimple(arch, printInfoSimple(arch, Inst::kIdAdd, 0, eax, ebx);
x86::Inst::kIdAdd, 0, printInfoSimple(arch, Inst::kIdLods, 0, eax, dword_ptr(rsi));
x86::eax, x86::ebx);
printInfoSimple(arch, printInfoSimple(arch, Inst::kIdPshufd, 0, xmm0, xmm1, imm(0));
x86::Inst::kIdLods, 0, printInfoSimple(arch, Inst::kIdPabsb, 0, mm1, mm2);
x86::eax , dword_ptr(x86::rsi)); printInfoSimple(arch, Inst::kIdPabsb, 0, xmm1, xmm2);
printInfoSimple(arch, Inst::kIdPextrw, 0, eax, mm1, imm(0));
printInfoSimple(arch, Inst::kIdPextrw, 0, eax, xmm1, imm(0));
printInfoSimple(arch, Inst::kIdPextrw, 0, ptr(rax), xmm1, imm(0));
printInfoSimple(arch, printInfoSimple(arch, Inst::kIdVpdpbusd, 0, xmm0, xmm1, xmm2);
x86::Inst::kIdPshufd, 0, printInfoSimple(arch, Inst::kIdVpdpbusd, Inst::kOptionVex, xmm0, xmm1, xmm2);
x86::xmm0, x86::xmm1, imm(0));
printInfoSimple(arch, printInfoSimple(arch, Inst::kIdVaddpd, 0, ymm0, ymm1, ymm2);
x86::Inst::kIdPextrw, 0, printInfoSimple(arch, Inst::kIdVaddpd, 0, ymm0, ymm30, ymm31);
x86::eax, x86::xmm1, imm(0)); printInfoSimple(arch, Inst::kIdVaddpd, 0, zmm0, zmm1, zmm2);
printInfoSimple(arch, printInfoExtra(arch, Inst::kIdVaddpd, 0, k1, zmm0, zmm1, zmm2);
x86::Inst::kIdPextrw, 0, printInfoExtra(arch, Inst::kIdVaddpd, Inst::kOptionZMask, k1, zmm0, zmm1, zmm2);
x86::ptr(x86::rax), x86::xmm1, imm(0));
printInfoSimple(arch,
x86::Inst::kIdVpdpbusd, 0,
x86::xmm0, x86::xmm1, x86::xmm2);
printInfoSimple(arch,
x86::Inst::kIdVpdpbusd, x86::Inst::kOptionVex,
x86::xmm0, x86::xmm1, x86::xmm2);
printInfoSimple(arch,
x86::Inst::kIdVaddpd, 0,
x86::ymm0, x86::ymm1, x86::ymm2);
printInfoSimple(arch,
x86::Inst::kIdVaddpd, 0,
x86::ymm0, x86::ymm30, x86::ymm31);
printInfoSimple(arch,
x86::Inst::kIdVaddpd, 0,
x86::zmm0, x86::zmm1, x86::zmm2);
printInfoExtra(arch,
x86::Inst::kIdVaddpd, 0,
x86::k1,
x86::zmm0, x86::zmm1, x86::zmm2);
printInfoExtra(arch,
x86::Inst::kIdVaddpd, x86::Inst::kOptionZMask,
x86::k1,
x86::zmm0, x86::zmm1, x86::zmm2);
#endif #endif
} }