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Workaround for issue #427

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MSVC incorrectly auto-vectorizes a loop that is used in liveness
analysis. Due to this bug the result is wrong, which then affects
how registers are allocated. This workarounds a C++ compiler bug.
This commit is contained in:
kobalicek
2024-01-23 23:46:27 +01:00
parent 03b784c9fe
commit bfa0bf690c
1 changed files with 9 additions and 2 deletions
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11
src/asmjit/core/rapass.cpp
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@@ -762,6 +762,13 @@ namespace LiveOps {
static ASMJIT_FORCE_INLINE bool op(BitWord* dst, const BitWord* a, const BitWord* b, const BitWord* c, uint32_t n) noexcept { static ASMJIT_FORCE_INLINE bool op(BitWord* dst, const BitWord* a, const BitWord* b, const BitWord* c, uint32_t n) noexcept {
BitWord changed = 0; BitWord changed = 0;
#if defined(_MSC_VER) && _MSC_VER <= 1938
// MSVC workaround (see #427).
//
// MSVC incorrectly auto-vectorizes this loop when used with <In> operator. For some reason it trashes a content
// of a register, which causes the result to be incorrect. It's a compiler bug we have to prevent unfortunately.
#pragma loop(no_vector)
#endif
for (uint32_t i = 0; i < n; i++) { for (uint32_t i = 0; i < n; i++) {
BitWord before = dst[i]; BitWord before = dst[i];
BitWord after = Operator::op(before, a[i], b[i], c[i]); BitWord after = Operator::op(before, a[i], b[i], c[i]);
@@ -773,7 +780,7 @@ namespace LiveOps {
return changed != 0; return changed != 0;
} }
static ASMJIT_FORCE_INLINE bool recalcInOut(RABlock* block, uint32_t numBitWords, bool initial = false) noexcept { static ASMJIT_NOINLINE bool recalcInOut(RABlock* block, uint32_t numBitWords, bool initial = false) noexcept {
bool changed = initial; bool changed = initial;
const RABlocks& successors = block->successors(); const RABlocks& successors = block->successors();
@@ -873,7 +880,7 @@ ASMJIT_FAVOR_SPEED Error BaseRAPass::buildLiveness() noexcept {
if (tiedReg->hasConsecutiveParent()) { if (tiedReg->hasConsecutiveParent()) {
RAWorkReg* consecutiveParentReg = workRegById(tiedReg->consecutiveParent()); RAWorkReg* consecutiveParentReg = workRegById(tiedReg->consecutiveParent());
consecutiveParentReg->addImmediateConsecutive(allocator(), workId); ASMJIT_PROPAGATE(consecutiveParentReg->addImmediateConsecutive(allocator(), workId));
} }
} }