mirror of
https://github.com/asmjit/asmjit.git
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[ABI] Updated instruction DB, operands, and minor API changes
This changeset contains an updated instruction database that brings ARM32 instructions for the first time. It also updates instruction database tooling especially for ARM64, which will also be used by ARM32 generator. Additionally, new operan has been added, which represents a register list as used by ARM32 instruction set. Other minor changes are related to ARM - some stuff had to be moved to a64 namespace from arm namespace as it's incompatible between 32-bit and 64-bit ISA.
This commit is contained in:
kobalicek
@@ -1,13 +1,14 @@
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AsmJit Instruction Database
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---------------------------
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This is a database of instructions that is used by AsmJit to generate its internal database and also assembler implementations. This project started initially as AsmDB, but was merged to AsmJit later to make the maintenance easier. The database was created in a way so that each instruction definition would only need a single line in JSON data. The data is then processed by architecture specific data readers that make the data canonical and ready for processing.
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This is a database of instructions that is used by AsmJit to generate its internal database and also assembler implementations. This project started initially as AsmDB, but was merged to AsmJit later to make the maintenance easier. The database was created in a way so that each instruction definition would only need a single line in JSON data file. The data is then processed by architecture specific data readers that make the data canonical and ready for processing.
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AsmJit database provides the following ISAs:
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* `isa_x86.json` - provides X86 instruction data (both 32-bit and 64-bit)
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* `isa_arm.json` - provides AArch32 instruction data (both ARM32 and THUMB)
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* `isa_a64.json` - provides AArch64 instruction data
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* `isa_aarch32.json` - provides AArch32 instruction data (A32/T16/T32 encoding)
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* `isa_aarch64.json` - provides AArch64 instruction data (A64 encoding)
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* `isa_aarch64_sme.json` - provides AArch64 SME instruction data (work-in-progress)
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To Be Documented
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----------------
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@@ -29,14 +29,14 @@ const arm = $scope[$as] = dict();
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// Database
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// ========
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arm.dbName = "isa_arm.json";
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arm.dbName = "isa_aarch32.json";
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// asmdb.arm.Utils
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// ===============
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// asmdb.aarch32.Utils
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// ===================
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// Can be used to assign the number of bits each part of the opcode occupies.
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// NOTE: THUMB instructions that use halfword must always specify the width
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// of all registers as many instructictions accept only LO (r0..r7) registers.
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// of all registers as many instructions accept only LO (r0..r7) registers.
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const FieldInfo = {
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"P" : { "bits": 1 },
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"U" : { "bits": 1 },
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@@ -56,6 +56,7 @@ const FieldInfo = {
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"cmode" : { "bits": 4 },
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"Cn" : { "bits": 4 },
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"Cm" : { "bits": 4 },
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"Rd" : { "bits": 4, "read": false, "write": true },
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"Rd2" : { "bits": 4, "read": false, "write": true },
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"RdLo" : { "bits": 4, "read": false, "write": true },
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@@ -70,17 +71,22 @@ const FieldInfo = {
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"Rs" : { "bits": 4, "read": true , "write": false },
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"Rs2" : { "bits": 4, "read": true , "write": false },
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"RsList": { "bits": 4, "read": true , "write": false , "list": true },
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"Sd" : { "bits": 4, "read": false, "write": true },
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"Sd2" : { "bits": 4, "read": false, "write": true },
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"SdList": { "bits": 4, "read": false, "write": true , "list": true },
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"Sx" : { "bits": 4, "read": true , "write": true },
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"Sn" : { "bits": 4, "read": true , "write": false },
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"Sm" : { "bits": 4, "read": true , "write": false },
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"Ss" : { "bits": 4, "read": true , "write": false },
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"Ss2" : { "bits": 4, "read": true , "write": false },
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"SsList": { "bits": 4, "read": true , "write": false , "list": true },
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"Dd" : { "bits": 4, "read": false, "write": true },
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"Dd2" : { "bits": 4, "read": false, "write": true },
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"Dd3" : { "bits": 4, "read": false, "write": true },
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"Dd4" : { "bits": 4, "read": false, "write": true },
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"DdList": { "bits": 4, "read": false, "write": true , "list": true },
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"Dx" : { "bits": 4, "read": true , "write": true },
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"Dx2" : { "bits": 4, "read": true , "write": true },
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"Dn" : { "bits": 4, "read": true , "write": false },
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@@ -92,18 +98,18 @@ const FieldInfo = {
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"Ds2" : { "bits": 4, "read": true , "write": false },
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"Ds3" : { "bits": 4, "read": true , "write": false },
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"Ds4" : { "bits": 4, "read": true , "write": false },
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"DsList": { "bits": 4, "read": true , "write": false , "list": true },
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"Vd" : { "bits": 4, "read": false, "write": true },
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"Vd2" : { "bits": 4, "read": false, "write": true },
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"Vd3" : { "bits": 4, "read": false, "write": true },
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"Vd4" : { "bits": 4, "read": false, "write": true },
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"VdList": { "bits": 4, "read": false, "write": true , "list": true },
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"Vx" : { "bits": 4, "read": true , "write": true },
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"Vx2" : { "bits": 4, "read": true , "write": true },
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"Vn" : { "bits": 4, "read": true , "write": false },
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"Vm" : { "bits": 4, "read": true , "write": false },
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"Vs" : { "bits": 4, "read": true , "write": false },
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"Vs2" : { "bits": 4, "read": true , "write": false },
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"VsList": { "bits": 4, "read": true , "write": false , "list": true }
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};
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arm.FieldInfo = FieldInfo;
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@@ -192,10 +198,16 @@ function decomposeOperand(s) {
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const elementSuffix = "[#i]";
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let element = null;
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let consecutive = 0;
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let userRegList = false;
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if (s.endsWith("^")) {
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userRegList = true;
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s = s.substring(0, s.length - 1);
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}
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if (s.endsWith(elementSuffix)) {
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element = "#i";
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s = s.substr(0, s.length - elementSuffix.length);
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s = s.substring(0, s.length - elementSuffix.length);
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}
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if (s.endsWith("++")) {
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@@ -219,7 +231,8 @@ function decomposeOperand(s) {
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data : s,
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element : element,
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restrict: restrict,
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consecutive: consecutive
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consecutive: consecutive,
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userRegList: true
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};
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}
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@@ -238,8 +251,8 @@ function splitOpcodeFields(s) {
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return out.map((field) => { return field.trim(); });
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}
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// asmdb.arm.Operand
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// =================
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// asmdb.aarch32.Operand
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// =====================
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// ARM operand.
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class Operand extends base.Operand {
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@@ -267,17 +280,44 @@ class Operand extends base.Operand {
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else
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return 0;
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}
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isRelative() {
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if (this.type === "imm")
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return this.name === "relA" || this.name === "relS" || this.name === "relZ";
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else
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return false;
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}
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}
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arm.Operand = Operand;
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// asmdb.arm.Instruction
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// =====================
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// asmdb.aarch32.Instruction
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// =========================
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function patternFromOperand(key) {
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return key;
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// return key.replace(/\b(?:[RVDS](?:d|s|n|m|x|x2))\b/, "R");
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}
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// Rewrite a memory operand expression (either base or index) to a simplified one, which is okay
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// to be generated as C++ expression. In general, we want to simplify != to a more favorable code.
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function simplifyMemoryExpression(e) {
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if (e.type === "binary" && e.op === "!=" && e.right.type === "var") {
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// Rewrite A != PC to A < PC
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if (e.right.name === "PC") { e.op = "<"; }
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// Rewrite A != HI to A < 8
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if (e.right.name === "HI") { e.op = "<"; e.right = exp.Imm(8); }
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// Rewrite A != XX to A < SP || A == LR
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if (e.right.name === "XX") {
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return exp.Or(exp.Lt(e.left, exp.Var("SP")),
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exp.Eq(e.left.clone(), exp.Var("LR")));
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}
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}
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return e;
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}
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// ARM instruction.
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class Instruction extends base.Instruction {
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constructor(db, data) {
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@@ -482,13 +522,14 @@ class Instruction extends base.Instruction {
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const m = part.match(/^([A-Za-z]\w*)/);
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if (m.length < part.length) {
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op.base.exp = exp.parse(part);
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op.base.exp = simplifyMemoryExpression(exp.parse(part));
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op.base.field = m[1];
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}
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}
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else if (part.startsWith("#")) {
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let p = part.substring(1);
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let u = "1";
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let alwaysNegative = false;
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let offExp = null;
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let offMul = 1;
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@@ -498,6 +539,11 @@ class Instruction extends base.Instruction {
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p = p.substring(3);
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}
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if (p.startsWith("-")) {
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alwaysNegative = false;
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p = p.substring(1);
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}
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const expMatch = p.match(/^([A-Za-z]\w*)==/);
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if (expMatch) {
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offExp = exp.parse(p);
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@@ -515,6 +561,7 @@ class Instruction extends base.Instruction {
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op.offset.u = u;
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op.offset.exp = offExp;
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op.offset.mul = offMul;
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op.offset.negative = alwaysNegative;
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}
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else {
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let p = part;
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@@ -531,7 +578,7 @@ class Instruction extends base.Instruction {
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const m = p.match(/^([A-Za-z]\w*)/);
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if (m.length < p.length) {
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op.index.exp = exp.parse(p);
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op.index.exp = simplifyMemoryExpression(exp.parse(p));
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op.index.field = m[1];
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}
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}
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@@ -858,8 +905,8 @@ class Instruction extends base.Instruction {
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}
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arm.Instruction = Instruction;
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// asmdb.arm.ISA
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// =============
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// asmdb.aarch32.ISA
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// =================
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function mergeGroupData(data, group) {
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for (let k in group) {
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@@ -921,7 +968,7 @@ class ISA extends base.ISA {
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hasOwn.call(obj, "t16") ? "t16" : "";
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if (!encoding)
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FAIL(`Instrution ${names.join("/")} doesn't encoding, it must provide either a32, t32, or t16 field`);
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FAIL(`Instruction ${names.join("/")} doesn't encoding, it must provide either a32, t32, or t16 field`);
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for (let j = 0; j < names.length; j++) {
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const inst = new Instruction(this, names[j], operands, encoding.toUpperCase(), obj[encoding], obj);
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@@ -938,4 +985,4 @@ class ISA extends base.ISA {
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arm.ISA = ISA;
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}).apply(this, typeof module === "object" && module && module.exports
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? [module, "exports"] : [this.asmdb || (this.asmdb = {}), "arm"]);
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? [module, "exports"] : [this.asmdb || (this.asmdb = {}), "aarch32"]);
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@@ -36,7 +36,7 @@ arm.dbName = "isa_aarch64.json";
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// Can be used to assign the number of bits each part of the opcode occupies.
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// NOTE: THUMB instructions that use halfword must always specify the width
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// of all registers as many instructictions accept only LO (r0..r7) registers.
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// of all registers as many instructions accept only LO (r0..r7) registers.
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const FieldInfo = {
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"P" : { "bits": 1 },
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"U" : { "bits": 1 },
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16
db/base.js
16
db/base.js
@@ -205,7 +205,7 @@ class Operand {
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toString() { return this.data; }
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isReg() { return !!this.reg; }
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isReg() { return !!this.reg && this.type !== "reg-list"; }
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isMem() { return !!this.mem; }
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isImm() { return !!this.imm; }
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isRel() { return !!this.rel; }
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@@ -259,6 +259,20 @@ class Instruction {
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return out;
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}
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get operandCount() {
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return this.operands.length;
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}
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get minimumOperandCount() {
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const count = this.operands.length;
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for (let i = 0; i < count; i++) {
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if (this.operands[i].optional) {
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return i;
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}
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}
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return count
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}
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_assignAttribute(key, value) {
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switch (key) {
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case "ext":
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165
db/exp.js
165
db/exp.js
@@ -87,6 +87,7 @@ class ExpNode {
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info() { return null; }
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clone() { throw new Error("ExpNode.clone() must be overridden"); }
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evaluate(ctx) { throw new Error("ExpNode.evaluate() must be overridden"); }
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toString(ctx) { throw new Error("ExpNode.toString() must be overridden"); }
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}
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@@ -97,6 +98,7 @@ class ImmNode extends ExpNode {
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}
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clone() { return new ImmNode(this.imm); }
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evaluate(ctx) { return this.imm; }
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toString(ctx) { return ctx ? ctx.stringifyImmediate(this.imm) : String(this.imm); }
|
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}
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@@ -106,7 +108,8 @@ class VarNode extends ExpNode {
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this.name = name || "";
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}
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clone() { return new VarNode(this.var); }
|
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clone() { return new VarNode(this.name); }
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evaluate(ctx) { return ctx.variable(this.name); }
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toString(ctx) { return ctx ? ctx.stringifyVariable(this.name) : String(this.name); }
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}
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@@ -117,7 +120,14 @@ class CallNode extends ExpNode {
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this.args = args || [];
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}
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|
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clone() { return new CallNode(this.name, this.args.map(function(arg) { return arg.clone(); })); }
|
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clone() {
|
||||
return new CallNode(this.name, this.args.map(function(arg) { return arg.clone(); }));
|
||||
}
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||||
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||||
evaluate(ctx) {
|
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const evaluatedArgs = this.args.map(function(arg) { return arg.evaluate(ctx); });
|
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return ctx.function(this.name, evaluatedArgs);
|
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}
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||||
|
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toString(ctx) {
|
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if (this.name === "$bit") {
|
||||
@@ -143,8 +153,23 @@ class UnaryNode extends ExpNode {
|
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this.child = child || null;
|
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}
|
||||
|
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info() { return kUnaryOperators[this.op]; }
|
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clone() { return new UnaryNode(this.op, this.left ? this.left.clone() : null); }
|
||||
info() {
|
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return kUnaryOperators[this.op];
|
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}
|
||||
|
||||
clone() {
|
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return new UnaryNode(this.op, this.left ? this.left.clone() : null);
|
||||
}
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||||
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||||
evaluate(ctx) {
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const val = this.child.evaluate(ctx);
|
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switch (this.op) {
|
||||
case "-": return (-val);
|
||||
case "~": return (~val);
|
||||
case "!": return (val ? 0 : 1);
|
||||
default : return ctx.unary(this.op, val);
|
||||
}
|
||||
}
|
||||
|
||||
toString(ctx) {
|
||||
return this.info().emit.replace(/@1/g, () => {
|
||||
@@ -166,8 +191,40 @@ class BinaryNode extends ExpNode {
|
||||
this.right = right || null;
|
||||
}
|
||||
|
||||
info() { return kBinaryOperators[this.op]; }
|
||||
clone() { return new BinaryNode(this.op, this.left ? this.left.clone() : null, this.right ? this.right.clone() : null); }
|
||||
info() {
|
||||
return kBinaryOperators[this.op];
|
||||
}
|
||||
|
||||
clone() {
|
||||
return new BinaryNode(this.op, this.left ? this.left.clone() : null, this.right ? this.right.clone() : null);
|
||||
}
|
||||
|
||||
evaluate(ctx) {
|
||||
const left = this.left.evaluate(ctx);
|
||||
const right = this.right.evaluate(ctx);
|
||||
|
||||
switch (this.op) {
|
||||
case "-" : return left - right;
|
||||
case "+" : return left + right;
|
||||
case "*" : return left * right;
|
||||
case "/" : return (left / right)|0;
|
||||
case "%" : return (left % right)|0;
|
||||
case "&" : return left & right;
|
||||
case "|" : return left | right;
|
||||
case "^" : return left ^ right;
|
||||
case "<<": return left << right;
|
||||
case ">>": return left >> right;
|
||||
case "==": return left == right ? 1 : 0;
|
||||
case "!=": return left != right ? 1 : 0;
|
||||
case "<" : return left < right ? 1 : 0;
|
||||
case "<=": return left <= right ? 1 : 0;
|
||||
case ">" : return left > right ? 1 : 0;
|
||||
case ">=": return left >= right ? 1 : 0;
|
||||
case "&&": return left && right ? 1 : 0;
|
||||
case "||": return left || right ? 1 : 0;
|
||||
default : return ctx.binary(this.op, left, right);
|
||||
}
|
||||
}
|
||||
|
||||
toString(ctx) {
|
||||
return this.info().emit.replace(/@[1-2]/g, (p) => {
|
||||
@@ -184,8 +241,6 @@ function Call(name, args) { return new CallNode(name, args); }
|
||||
function Unary(op, child) { return new UnaryNode(op, child); }
|
||||
function Binary(op, left, right) { return new BinaryNode(op, left, right); }
|
||||
|
||||
/*
|
||||
// TODO: Unused, remove?
|
||||
function Negate(child) { return Unary("-", child); }
|
||||
function BitNot(child) { return Unary("~", child); }
|
||||
|
||||
@@ -207,7 +262,8 @@ function Gt(left, right) { return Binary(">", left, right); }
|
||||
function Ge(left, right) { return Binary(">=", left, right); }
|
||||
function And(left, right) { return Binary("&&", left, right); }
|
||||
function Or(left, right) { return Binary("||", left, right); }
|
||||
*/
|
||||
|
||||
|
||||
|
||||
// Expression Tokenizer
|
||||
// --------------------
|
||||
@@ -256,7 +312,44 @@ function newToken(type, position, data, value) {
|
||||
const NoToken = newToken(kTokenNone, -1, "<end>", null);
|
||||
|
||||
// Must be reset before it can be used, use `RegExp.lastIndex`.
|
||||
const reValue = /(?:(?:\d*\.\d+|\d+)(?:[E|e][+|-]?\d+)?)/g;
|
||||
const reNumValue = /(?:(?:\d*\.\d+|\d+)(?:[E|e][+|-]?\d+)?)/g;
|
||||
|
||||
function parseHex(source, from) {
|
||||
let i = from;
|
||||
let number = 0;
|
||||
|
||||
while (i < source.length) {
|
||||
let c = source.charCodeAt(i);
|
||||
let n = 0;
|
||||
|
||||
if (c >= '0'.charCodeAt(0) && c <= '9'.charCodeAt(0)) {
|
||||
n = c - '0'.charCodeAt(0);
|
||||
}
|
||||
else if (c >= 'a'.charCodeAt(0) && c <= 'f'.charCodeAt(0)) {
|
||||
n = c - 'a'.charCodeAt(0) + 10;
|
||||
}
|
||||
else if (c >= 'A'.charCodeAt(0) && c <= 'F'.charCodeAt(0)) {
|
||||
n = c - 'A'.charCodeAt(0) + 10;
|
||||
}
|
||||
else if (c >= 'g'.charCodeAt(0) && c <= 'z'.charCodeAt(0) || c >= 'g'.charCodeAt(0) && c <= 'Z'.charCodeAt(0)) {
|
||||
throwExpressionError(`Invalid hex number 0x${source.substring(from, i + 1)}`);
|
||||
}
|
||||
else {
|
||||
break;
|
||||
}
|
||||
|
||||
number = (number << 4) | n;
|
||||
i++;
|
||||
}
|
||||
|
||||
if (i === from)
|
||||
throwExpressionError(`Invalid number starting with 0x`);
|
||||
|
||||
return {
|
||||
number: number,
|
||||
end: i
|
||||
};
|
||||
}
|
||||
|
||||
function tokenize(source) {
|
||||
const len = source.length;
|
||||
@@ -268,22 +361,33 @@ function tokenize(source) {
|
||||
let c, cat; // Current character code and category.
|
||||
|
||||
while (i < len) {
|
||||
cat = Category(c = source.charCodeAt(i));
|
||||
c = source.charCodeAt(i);
|
||||
cat = Category(c);
|
||||
|
||||
if (cat === kCharSpace) {
|
||||
i++;
|
||||
}
|
||||
else if (cat === kCharDigit) {
|
||||
const n = tokens.length - 1;
|
||||
if (n >= 0 && tokens[n].data === "." && source[i - 1] === ".") {
|
||||
tokens.length = n;
|
||||
i--;
|
||||
}
|
||||
reValue.lastIndex = i;
|
||||
data = reValue.exec(source)[0];
|
||||
|
||||
tokens.push(newToken(kTokenValue, i, data, parseFloat(data)));
|
||||
i += data.length;
|
||||
// Hex number.
|
||||
if (c === '0'.charCodeAt(0) && i + 1 < len && source.charCodeAt(i + 1) === 'x'.charCodeAt(0)) {
|
||||
const status = parseHex(source, i + 2);
|
||||
tokens.push(newToken(kTokenValue, i, source.substring(i, status.end), status.number));
|
||||
i = status.end;
|
||||
}
|
||||
else {
|
||||
if (n >= 0 && tokens[n].data === "." && source[i - 1] === ".") {
|
||||
tokens.length = n;
|
||||
i--;
|
||||
}
|
||||
|
||||
reNumValue.lastIndex = i;
|
||||
data = reNumValue.exec(source)[0];
|
||||
|
||||
tokens.push(newToken(kTokenValue, i, data, parseFloat(data)));
|
||||
i += data.length;
|
||||
}
|
||||
}
|
||||
else if (cat === kCharAlpha) {
|
||||
start = i;
|
||||
@@ -623,6 +727,29 @@ $scope[$as] = {
|
||||
Call: Call,
|
||||
Unary: Unary,
|
||||
Binary: Binary,
|
||||
|
||||
Negate: Negate,
|
||||
BitNot: BitNot,
|
||||
|
||||
Add: Add,
|
||||
Sub: Sub,
|
||||
Mul: Mul,
|
||||
Div: Div,
|
||||
Mod: Mod,
|
||||
Shl: Shl,
|
||||
Shr: Shr,
|
||||
BitAnd: BitAnd,
|
||||
BitOr: BitOr,
|
||||
BitXor: BitXor,
|
||||
Eq: Eq,
|
||||
Ne: Ne,
|
||||
Lt: Lt,
|
||||
Le: Le,
|
||||
Gt: Gt,
|
||||
Ge: Ge,
|
||||
And: And,
|
||||
Or: Or,
|
||||
|
||||
Visitor: Visitor,
|
||||
ExpressionError: ExpressionError,
|
||||
|
||||
|
||||
@@ -6,6 +6,6 @@
|
||||
"use strict";
|
||||
|
||||
exports.base = require("./base.js");
|
||||
exports.arm = require("./arm.js");
|
||||
exports.aarch32 = require("./aarch32.js");
|
||||
exports.aarch64 = require("./aarch64.js");
|
||||
exports.x86 = require("./x86.js");
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -139,70 +139,70 @@
|
||||
{"inst": "ldaxr Xd, [Xn|SP]" , "op": "11001000|010|11111|1|11111|Rn|Rd"},
|
||||
{"inst": "ldaxrb Wd, [Xn|SP]" , "op": "00001000|010|11111|1|11111|Rn|Rd"},
|
||||
{"inst": "ldaxrh Xd, [Xn|SP]" , "op": "01001000|010|11111|1|11111|Rn|Rd"},
|
||||
{"inst": "ldnp Wd, Wd2, [Xn|SP, #soff*4]" , "op": "00101000|01|soff:7|Rd2|Rn|Rd"},
|
||||
{"inst": "ldnp Xd, Xd2, [Xn|SP, #soff*8]" , "op": "10101000|01|soff:7|Rd2|Rn|Rd"},
|
||||
{"inst": "ldp Wd, Wd2, [Xn|SP, #soff*4]{@}{!}" , "op": "0010100|!post|W|1|soff:7|Rd2|Rn|Rd"},
|
||||
{"inst": "ldp Xd, Xd2, [Xn|SP, #soff*8]{@}{!}" , "op": "1010100|!post|W|1|soff:7|Rd2|Rn|Rd"},
|
||||
{"inst": "ldpsw Xd, Xd2, [Xn|SP, #soff*4]{@}{!}" , "op": "0110100|!post|W|1|soff:7|Rd2|Rn|Rd"},
|
||||
{"inst": "ldr Wd, [Xn|SP, #zoff*4]" , "op": "10111001|01|zoff:12|Rn|Rd"},
|
||||
{"inst": "ldr Xd, [Xn|SP, #zoff*8]" , "op": "11111001|01|zoff:12|Rn|Rd"},
|
||||
{"inst": "ldr Wd, [Xn|SP, #soff*4]@" , "op": "10111000|010|soff:9|01|Rn|Rd"},
|
||||
{"inst": "ldr Xd, [Xn|SP, #soff*8]@" , "op": "11111000|010|soff:9|01|Rn|Rd"},
|
||||
{"inst": "ldr Wd, [Xn|SP, #soff*4]!" , "op": "10111000|010|soff:9|11|Rn|Rd"},
|
||||
{"inst": "ldr Xd, [Xn|SP, #soff*8]!" , "op": "11111000|010|soff:9|11|Rn|Rd"},
|
||||
{"inst": "ldnp Wd, Wd2, [Xn|SP, #offS*4]" , "op": "00101000|01|offS:7|Rd2|Rn|Rd"},
|
||||
{"inst": "ldnp Xd, Xd2, [Xn|SP, #offS*8]" , "op": "10101000|01|offS:7|Rd2|Rn|Rd"},
|
||||
{"inst": "ldp Wd, Wd2, [Xn|SP, #offS*4]{@}{!}" , "op": "0010100|!post|W|1|offS:7|Rd2|Rn|Rd"},
|
||||
{"inst": "ldp Xd, Xd2, [Xn|SP, #offS*8]{@}{!}" , "op": "1010100|!post|W|1|offS:7|Rd2|Rn|Rd"},
|
||||
{"inst": "ldpsw Xd, Xd2, [Xn|SP, #offS*4]{@}{!}" , "op": "0110100|!post|W|1|offS:7|Rd2|Rn|Rd"},
|
||||
{"inst": "ldr Wd, [Xn|SP, #offZ*4]" , "op": "10111001|01|offZ:12|Rn|Rd"},
|
||||
{"inst": "ldr Xd, [Xn|SP, #offZ*8]" , "op": "11111001|01|offZ:12|Rn|Rd"},
|
||||
{"inst": "ldr Wd, [Xn|SP, #offS*4]@" , "op": "10111000|010|offS:9|01|Rn|Rd"},
|
||||
{"inst": "ldr Xd, [Xn|SP, #offS*8]@" , "op": "11111000|010|offS:9|01|Rn|Rd"},
|
||||
{"inst": "ldr Wd, [Xn|SP, #offS*4]!" , "op": "10111000|010|offS:9|11|Rn|Rd"},
|
||||
{"inst": "ldr Xd, [Xn|SP, #offS*8]!" , "op": "11111000|010|offS:9|11|Rn|Rd"},
|
||||
{"inst": "ldr Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDR(iop, n)"},
|
||||
{"inst": "ldr Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "11111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDR(iop, n)"},
|
||||
{"inst": "ldr Wd, [PC, #soff*4]" , "op": "00011000|soff:19|Rd"},
|
||||
{"inst": "ldr Xd, [PC, #soff*4]" , "op": "01011000|soff:19|Rd"},
|
||||
{"inst": "ldrb Wd, [Xn|SP, #zoff]" , "op": "00111001|01|zoff:12|Rn|Rd"},
|
||||
{"inst": "ldrb Wd, [Xn|SP, #soff]@" , "op": "00111000|010|soff:9|01|Rn|Rd"},
|
||||
{"inst": "ldrb Wd, [Xn|SP, #soff]!" , "op": "00111000|010|soff:9|11|Rn|Rd"},
|
||||
{"inst": "ldr Wd, [PC, #offS*4]" , "op": "00011000|offS:19|Rd"},
|
||||
{"inst": "ldr Xd, [PC, #offS*4]" , "op": "01011000|offS:19|Rd"},
|
||||
{"inst": "ldrb Wd, [Xn|SP, #offZ]" , "op": "00111001|01|offZ:12|Rn|Rd"},
|
||||
{"inst": "ldrb Wd, [Xn|SP, #offS]@" , "op": "00111000|010|offS:9|01|Rn|Rd"},
|
||||
{"inst": "ldrb Wd, [Xn|SP, #offS]!" , "op": "00111000|010|offS:9|11|Rn|Rd"},
|
||||
{"inst": "ldrb Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"},
|
||||
{"inst": "ldrh Wd, [Xn|SP, #zoff*2]" , "op": "01111001|01|zoff:12|Rn|Rd"},
|
||||
{"inst": "ldrh Wd, [Xn|SP, #soff*2]@" , "op": "01111000|010|soff:9|01|Rn|Rd"},
|
||||
{"inst": "ldrh Wd, [Xn|SP, #soff*2]!" , "op": "01111000|010|soff:9|11|Rn|Rd"},
|
||||
{"inst": "ldrh Wd, [Xn|SP, #offZ*2]" , "op": "01111001|01|offZ:12|Rn|Rd"},
|
||||
{"inst": "ldrh Wd, [Xn|SP, #offS*2]@" , "op": "01111000|010|offS:9|01|Rn|Rd"},
|
||||
{"inst": "ldrh Wd, [Xn|SP, #offS*2]!" , "op": "01111000|010|offS:9|11|Rn|Rd"},
|
||||
{"inst": "ldrh Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|011|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"},
|
||||
{"inst": "ldrsb Wd, [Xn|SP, #zoff]" , "op": "00111001|11|zoff:12|Rn|Rd"},
|
||||
{"inst": "ldrsb Xd, [Xn|SP, #zoff]" , "op": "00111001|10|zoff:12|Rn|Rd"},
|
||||
{"inst": "ldrsb Wd, [Xn|SP, #soff]@" , "op": "00111000|110|soff:9|01|Rn|Rd"},
|
||||
{"inst": "ldrsb Xd, [Xn|SP, #soff]@" , "op": "00111000|100|soff:9|01|Rn|Rd"},
|
||||
{"inst": "ldrsb Wd, [Xn|SP, #soff]!" , "op": "00111000|110|soff:9|11|Rn|Rd"},
|
||||
{"inst": "ldrsb Xd, [Xn|SP, #soff]!" , "op": "00111000|100|soff:9|11|Rn|Rd"},
|
||||
{"inst": "ldrsb Wd, [Xn|SP, #offZ]" , "op": "00111001|11|offZ:12|Rn|Rd"},
|
||||
{"inst": "ldrsb Xd, [Xn|SP, #offZ]" , "op": "00111001|10|offZ:12|Rn|Rd"},
|
||||
{"inst": "ldrsb Wd, [Xn|SP, #offS]@" , "op": "00111000|110|offS:9|01|Rn|Rd"},
|
||||
{"inst": "ldrsb Xd, [Xn|SP, #offS]@" , "op": "00111000|100|offS:9|01|Rn|Rd"},
|
||||
{"inst": "ldrsb Wd, [Xn|SP, #offS]!" , "op": "00111000|110|offS:9|11|Rn|Rd"},
|
||||
{"inst": "ldrsb Xd, [Xn|SP, #offS]!" , "op": "00111000|100|offS:9|11|Rn|Rd"},
|
||||
{"inst": "ldrsb Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|111|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"},
|
||||
{"inst": "ldrsb Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRB(iop, n)"},
|
||||
{"inst": "ldrsh Wd, [Xn|SP, #zoff*2]" , "op": "01111001|11|zoff:12|Rn|Rd"},
|
||||
{"inst": "ldrsh Xd, [Xn|SP, #zoff*2]" , "op": "01111001|10|zoff:12|Rn|Rd"},
|
||||
{"inst": "ldrsh Wd, [Xn|SP, #soff*2]@" , "op": "01111000|110|soff:9|01|Rn|Rd"},
|
||||
{"inst": "ldrsh Xd, [Xn|SP, #soff*2]@" , "op": "01111000|100|soff:9|01|Rn|Rd"},
|
||||
{"inst": "ldrsh Wd, [Xn|SP, #soff*2]!" , "op": "01111000|110|soff:9|11|Rn|Rd"},
|
||||
{"inst": "ldrsh Xd, [Xn|SP, #soff*2]!" , "op": "01111000|100|soff:9|11|Rn|Rd"},
|
||||
{"inst": "ldrsh Wd, [Xn|SP, #offZ*2]" , "op": "01111001|11|offZ:12|Rn|Rd"},
|
||||
{"inst": "ldrsh Xd, [Xn|SP, #offZ*2]" , "op": "01111001|10|offZ:12|Rn|Rd"},
|
||||
{"inst": "ldrsh Wd, [Xn|SP, #offS*2]@" , "op": "01111000|110|offS:9|01|Rn|Rd"},
|
||||
{"inst": "ldrsh Xd, [Xn|SP, #offS*2]@" , "op": "01111000|100|offS:9|01|Rn|Rd"},
|
||||
{"inst": "ldrsh Wd, [Xn|SP, #offS*2]!" , "op": "01111000|110|offS:9|11|Rn|Rd"},
|
||||
{"inst": "ldrsh Xd, [Xn|SP, #offS*2]!" , "op": "01111000|100|offS:9|11|Rn|Rd"},
|
||||
{"inst": "ldrsh Wd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|111|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"},
|
||||
{"inst": "ldrsh Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRH(iop, n)"},
|
||||
{"inst": "ldrsw Xd, [Xn|SP, #zoff*4]" , "op": "10111001|10|zoff:12|Rn|Rd"},
|
||||
{"inst": "ldrsw Xd, [Xn|SP, #soff*4]@" , "op": "10111000|100|soff:9|01|Rn|Rd"},
|
||||
{"inst": "ldrsw Xd, [Xn|SP, #soff*4]!" , "op": "10111000|100|soff:9|11|Rn|Rd"},
|
||||
{"inst": "ldrsw Xd, [PC, #soff*4]" , "op": "10011000|soff:19|Rd"},
|
||||
{"inst": "ldrsw Xd, [Xn|SP, #offZ*4]" , "op": "10111001|10|offZ:12|Rn|Rd"},
|
||||
{"inst": "ldrsw Xd, [Xn|SP, #offS*4]@" , "op": "10111000|100|offS:9|01|Rn|Rd"},
|
||||
{"inst": "ldrsw Xd, [Xn|SP, #offS*4]!" , "op": "10111000|100|offS:9|11|Rn|Rd"},
|
||||
{"inst": "ldrsw Xd, [PC, #offS*4]" , "op": "10011000|offS:19|Rd"},
|
||||
{"inst": "ldrsw Xd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|101|Rm|option:3|s:1|10|Rn|Rd" , "imm": "ImmLDRW(iop, n)"},
|
||||
{"inst": "ldtr Wd, [Xn|SP, #soff]" , "op": "10111000|010|soff:9|10|Rn|Rd"},
|
||||
{"inst": "ldtr Xd, [Xn|SP, #soff]" , "op": "11111000|010|soff:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrb Wd, [Xn|SP, #soff]" , "op": "00111000|010|soff:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrh Wd, [Xn|SP, #soff]" , "op": "01111000|010|soff:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrsb Wd, [Xn|SP, #soff]" , "op": "00111000|100|soff:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrsb Xd, [Xn|SP, #soff]" , "op": "00111000|110|soff:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrsh Wd, [Xn|SP, #soff]" , "op": "01111000|100|soff:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrsh Xd, [Xn|SP, #soff]" , "op": "01111000|110|soff:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrsw Xd, [Xn|SP, #soff]" , "op": "10111000|100|soff:9|10|Rn|Rd"},
|
||||
{"inst": "ldur Wd, [Xn|SP, #soff]" , "op": "10111000|010|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldur Xd, [Xn|SP, #soff]" , "op": "11111000|010|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldurb Wd, [Xn|SP, #soff]" , "op": "00111000|010|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldurh Wd, [Xn|SP, #soff]" , "op": "01111000|010|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldursb Wd, [Xn|SP, #soff]" , "op": "00111000|100|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldursb Xd, [Xn|SP, #soff]" , "op": "00111000|110|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldursh Wd, [Xn|SP, #soff]" , "op": "01111000|100|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldursh Xd, [Xn|SP, #soff]" , "op": "01111000|110|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldursw Xd, [Xn|SP, #soff]" , "op": "10111000|100|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldxp Wd, Wd2, [Xn|SP, #soff*4]" , "op": "10001000|011|11111|0|Rd2|Rn|Rd"},
|
||||
{"inst": "ldxp Xd, Xd2, [Xn|SP, #soff*8]" , "op": "11001000|011|11111|0|Rd2|Rn|Rd"},
|
||||
{"inst": "ldtr Wd, [Xn|SP, #offS]" , "op": "10111000|010|offS:9|10|Rn|Rd"},
|
||||
{"inst": "ldtr Xd, [Xn|SP, #offS]" , "op": "11111000|010|offS:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrb Wd, [Xn|SP, #offS]" , "op": "00111000|010|offS:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrh Wd, [Xn|SP, #offS]" , "op": "01111000|010|offS:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrsb Wd, [Xn|SP, #offS]" , "op": "00111000|100|offS:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrsb Xd, [Xn|SP, #offS]" , "op": "00111000|110|offS:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrsh Wd, [Xn|SP, #offS]" , "op": "01111000|100|offS:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrsh Xd, [Xn|SP, #offS]" , "op": "01111000|110|offS:9|10|Rn|Rd"},
|
||||
{"inst": "ldtrsw Xd, [Xn|SP, #offS]" , "op": "10111000|100|offS:9|10|Rn|Rd"},
|
||||
{"inst": "ldur Wd, [Xn|SP, #offS]" , "op": "10111000|010|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldur Xd, [Xn|SP, #offS]" , "op": "11111000|010|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldurb Wd, [Xn|SP, #offS]" , "op": "00111000|010|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldurh Wd, [Xn|SP, #offS]" , "op": "01111000|010|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldursb Wd, [Xn|SP, #offS]" , "op": "00111000|100|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldursb Xd, [Xn|SP, #offS]" , "op": "00111000|110|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldursh Wd, [Xn|SP, #offS]" , "op": "01111000|100|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldursh Xd, [Xn|SP, #offS]" , "op": "01111000|110|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldursw Xd, [Xn|SP, #offS]" , "op": "10111000|100|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldxp Wd, Wd2, [Xn|SP, #offS*4]" , "op": "10001000|011|11111|0|Rd2|Rn|Rd"},
|
||||
{"inst": "ldxp Xd, Xd2, [Xn|SP, #offS*8]" , "op": "11001000|011|11111|0|Rd2|Rn|Rd"},
|
||||
{"inst": "ldxr Wd, [Xn|SP]" , "op": "10001000|010|11111|0|11111|Rn|Rd"},
|
||||
{"inst": "ldxr Xd, [Xn|SP]" , "op": "11001000|010|11111|0|11111|Rn|Rd"},
|
||||
{"inst": "ldxrb Wd, [Xn|SP]" , "op": "00001000|010|11111|0|11111|Rn|Rd"},
|
||||
@@ -260,9 +260,9 @@
|
||||
{"inst": "orr Wd|WSP, Wn, #log_imm" , "op": "00110010|0|imm:13|Rn|Rd" , "imm": "ImmLogical(log_imm, 0)"},
|
||||
{"inst": "orr Xd|SP, Xn, #log_imm" , "op": "10110010|0|imm:13|Rn|Rd" , "imm": "ImmLogical(log_imm, 1)"},
|
||||
{"inst": "prfm #prf_op, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*8}]" , "op": "11111000|101|Rm|option:3|n:1|10|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"},
|
||||
{"inst": "prfm #prf_op, [Xn|SP, #zoff]" , "op": "11111001|10|zoff:12|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"},
|
||||
{"inst": "prfm #prf_op, [PC, #soff*4]" , "op": "11011000|soff:19|prf_op:5" , "imm": "ImmPRF(prf_op)"},
|
||||
{"inst": "prfum #prf_op, [Xn|SP, #soff]" , "op": "11111000|100|soff:9|00|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"},
|
||||
{"inst": "prfm #prf_op, [Xn|SP, #offZ]" , "op": "11111001|10|offZ:12|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"},
|
||||
{"inst": "prfm #prf_op, [PC, #offS*4]" , "op": "11011000|offS:19|prf_op:5" , "imm": "ImmPRF(prf_op)"},
|
||||
{"inst": "prfum #prf_op, [Xn|SP, #offS]" , "op": "11111000|100|offS:9|00|Rn|prf_op:5" , "imm": "ImmPRF(prf_op)"},
|
||||
{"inst": "pssbb" , "op": "11010101|000|00011|0011|0100|100|11111"},
|
||||
{"inst": "rbit Wd, Wn" , "op": "01011010|110|00000|0|00000|Rn|Rd"},
|
||||
{"inst": "rbit Xd, Xn" , "op": "11011010|110|00000|0|00000|Rn|Rd"},
|
||||
@@ -291,7 +291,7 @@
|
||||
{"inst": "sev" , "op": "11010101|000|00011|0010|0000|100|11111"},
|
||||
{"inst": "sevl" , "op": "11010101|000|00011|0010|0000|101|11111"},
|
||||
{"inst": "smaddl Xd, Wn, Wm, Xa" , "op": "10011011|001|Rm|0|Ra|Rn|Rd"},
|
||||
{"inst": "smc #zimm" , "op": "11010100|000|zimm:16|00011"},
|
||||
{"inst": "smc #immZ" , "op": "11010100|000|immZ:16|00011"},
|
||||
{"inst": "smnegl Xd, Wn, Wm" , "op": "10011011|001|Rm|1|11111|Rn|Rd"},
|
||||
{"inst": "smsubl Xd, Wn, Wm, Xa" , "op": "10011011|001|Rm|1|Ra|Rn|Rd"},
|
||||
{"inst": "smulh Xd, Xn, Xm" , "op": "10011011|010|Rm|0|11111|Rn|Rd"},
|
||||
@@ -307,34 +307,34 @@
|
||||
{"inst": "stlxr Wd, Xs, [Xn|SP]" , "op": "11001000|000|Rd|1|11111|Rn|Rs"},
|
||||
{"inst": "stlxrb Wd, Ws, [Xn|SP]" , "op": "00001000|000|Rd|1|11111|Rn|Rs"},
|
||||
{"inst": "stlxrh Wd, Xs, [Xn|SP]" , "op": "01001000|000|Rd|1|11111|Rn|Rs"},
|
||||
{"inst": "stnp Ws, Ws2, [Xn|SP, #simm*4]" , "op": "00101000|00|simm:7|Rs2|Rn|Rs"},
|
||||
{"inst": "stnp Xs, Xs2, [Xn|SP, #simm*8]" , "op": "10101000|00|simm:7|Rs2|Rn|Rs"},
|
||||
{"inst": "stp Ws, Ws2, [Xn|SP, #simm*4]{@}{!}" , "op": "0010100|!post|W|0|simm:7|Rs2|Rn|Rs"},
|
||||
{"inst": "stp Xs, Xs2, [Xn|SP, #simm*8]{@}{!}" , "op": "1010100|!post|W|0|simm:7|Rs2|Rn|Rs"},
|
||||
{"inst": "str Ws, [Xn|SP, #zoff*4]" , "op": "10111001|00|zoff:12|Rn|Rs"},
|
||||
{"inst": "str Xs, [Xn|SP, #zoff*8]" , "op": "11111001|00|zoff:12|Rn|Rs"},
|
||||
{"inst": "str Ws, [Xn|SP, #soff*4]@" , "op": "10111000|000|soff:9|01|Rn|Rs"},
|
||||
{"inst": "str Xs, [Xn|SP, #soff*8]@" , "op": "11111000|000|soff:9|01|Rn|Rs"},
|
||||
{"inst": "str Ws, [Xn|SP, #soff*4]!" , "op": "10111000|000|soff:9|11|Rn|Rs"},
|
||||
{"inst": "str Xs, [Xn|SP, #soff*8]!" , "op": "11111000|000|soff:9|11|Rn|Rs"},
|
||||
{"inst": "stnp Ws, Ws2, [Xn|SP, #offS*4]" , "op": "00101000|00|offS:7|Rs2|Rn|Rs"},
|
||||
{"inst": "stnp Xs, Xs2, [Xn|SP, #offS*8]" , "op": "10101000|00|offS:7|Rs2|Rn|Rs"},
|
||||
{"inst": "stp Ws, Ws2, [Xn|SP, #offS*4]{@}{!}" , "op": "0010100|!post|W|0|offS:7|Rs2|Rn|Rs"},
|
||||
{"inst": "stp Xs, Xs2, [Xn|SP, #offS*8]{@}{!}" , "op": "1010100|!post|W|0|offS:7|Rs2|Rn|Rs"},
|
||||
{"inst": "str Ws, [Xn|SP, #offZ*4]" , "op": "10111001|00|offZ:12|Rn|Rs"},
|
||||
{"inst": "str Xs, [Xn|SP, #offZ*8]" , "op": "11111001|00|offZ:12|Rn|Rs"},
|
||||
{"inst": "str Ws, [Xn|SP, #offS*4]@" , "op": "10111000|000|offS:9|01|Rn|Rs"},
|
||||
{"inst": "str Xs, [Xn|SP, #offS*8]@" , "op": "11111000|000|offS:9|01|Rn|Rs"},
|
||||
{"inst": "str Ws, [Xn|SP, #offS*4]!" , "op": "10111000|000|offS:9|11|Rn|Rs"},
|
||||
{"inst": "str Xs, [Xn|SP, #offS*8]!" , "op": "11111000|000|offS:9|11|Rn|Rs"},
|
||||
{"inst": "str Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "10111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDR_STR(iop, n)"},
|
||||
{"inst": "str Xs, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "11111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDR_STR(iop, n)"},
|
||||
{"inst": "strb Ws, [Xn|SP, #zoff]" , "op": "00111001|00|zoff:12|Rn|Rs"},
|
||||
{"inst": "strb Ws, [Xn|SP, #soff]@" , "op": "00111000|000|soff:9|01|Rn|Rs"},
|
||||
{"inst": "strb Ws, [Xn|SP, #soff]!" , "op": "00111000|000|soff:9|11|Rn|Rs"},
|
||||
{"inst": "strb Ws, [Xn|SP, #offZ]" , "op": "00111001|00|offZ:12|Rn|Rs"},
|
||||
{"inst": "strb Ws, [Xn|SP, #offS]@" , "op": "00111000|000|offS:9|01|Rn|Rs"},
|
||||
{"inst": "strb Ws, [Xn|SP, #offS]!" , "op": "00111000|000|offS:9|11|Rn|Rs"},
|
||||
{"inst": "strb Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDRB_STRB(iop, n)"},
|
||||
{"inst": "strh Ws, [Xn|SP, #zoff*2]" , "op": "01111001|00|zoff:12|Rn|Rs"},
|
||||
{"inst": "strh Ws, [Xn|SP, #soff*2]@" , "op": "01111000|000|soff:9|01|Rn|Rs"},
|
||||
{"inst": "strh Ws, [Xn|SP, #soff*2]!" , "op": "01111000|000|soff:9|11|Rn|Rs"},
|
||||
{"inst": "strh Ws, [Xn|SP, #offZ*2]" , "op": "01111001|00|offZ:12|Rn|Rs"},
|
||||
{"inst": "strh Ws, [Xn|SP, #offS*2]@" , "op": "01111000|000|offS:9|01|Rn|Rs"},
|
||||
{"inst": "strh Ws, [Xn|SP, #offS*2]!" , "op": "01111000|000|offS:9|11|Rn|Rs"},
|
||||
{"inst": "strh Ws, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111000|001|Rm|option:3|s:1|10|Rn|Rs" , "imm": "ImmLDRH_STRH(iop, n)"},
|
||||
{"inst": "sttr Ws, [Xn|SP, #soff]" , "op": "10111000|000|soff:9|10|Rn|Rs"},
|
||||
{"inst": "sttr Xs, [Xn|SP, #soff]" , "op": "11111000|000|soff:9|10|Rn|Rs"},
|
||||
{"inst": "sttrb Ws, [Xn|SP, #soff]" , "op": "00111000|000|soff:9|10|Rn|Rs"},
|
||||
{"inst": "sttrh Ws, [Xn|SP, #soff]" , "op": "01111000|000|soff:9|10|Rn|Rs"},
|
||||
{"inst": "stur Ws, [Xn|SP, #soff]" , "op": "10111000|000|soff:9|00|Rn|Rs"},
|
||||
{"inst": "stur Xs, [Xn|SP, #soff]" , "op": "11111000|000|soff:9|00|Rn|Rs"},
|
||||
{"inst": "sturb Ws, [Xn|SP, #soff]" , "op": "00111000|000|soff:9|00|Rn|Rs"},
|
||||
{"inst": "sturh Ws, [Xn|SP, #soff]" , "op": "01111000|000|soff:9|00|Rn|Rs"},
|
||||
{"inst": "sttr Ws, [Xn|SP, #offS]" , "op": "10111000|000|offS:9|10|Rn|Rs"},
|
||||
{"inst": "sttr Xs, [Xn|SP, #offS]" , "op": "11111000|000|offS:9|10|Rn|Rs"},
|
||||
{"inst": "sttrb Ws, [Xn|SP, #offS]" , "op": "00111000|000|offS:9|10|Rn|Rs"},
|
||||
{"inst": "sttrh Ws, [Xn|SP, #offS]" , "op": "01111000|000|offS:9|10|Rn|Rs"},
|
||||
{"inst": "stur Ws, [Xn|SP, #offS]" , "op": "10111000|000|offS:9|00|Rn|Rs"},
|
||||
{"inst": "stur Xs, [Xn|SP, #offS]" , "op": "11111000|000|offS:9|00|Rn|Rs"},
|
||||
{"inst": "sturb Ws, [Xn|SP, #offS]" , "op": "00111000|000|offS:9|00|Rn|Rs"},
|
||||
{"inst": "sturh Ws, [Xn|SP, #offS]" , "op": "01111000|000|offS:9|00|Rn|Rs"},
|
||||
{"inst": "stxp Wd, Ws, Ws2, [Xn|SP]" , "op": "10001000|001|Rd|0|Rs2|Rn|Rs"},
|
||||
{"inst": "stxp Wd, Xs, Xs2, [Xn|SP]" , "op": "11001000|001|Rd|0|Rs2|Rn|Rs"},
|
||||
{"inst": "stxr Wd, Ws, [Xn|SP]" , "op": "10001000|000|Rd|0|11111|Rn|Rs"},
|
||||
@@ -353,7 +353,7 @@
|
||||
{"inst": "subs Xd, Xn|SP, Rm, {extend #n}" , "op": "11101011|00|1|Rm|option:3|n:3|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
|
||||
{"inst": "subs Wd|WSP, Wn|WSP, #immZ, {lsl #n=0|12}" , "op": "01110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
|
||||
{"inst": "subs Xd|SP, Xn|SP, #immZ, {lsl #n=0|12}" , "op": "11110001|0|n:1|immZ:12|Rn|Rd" , "io": "N=W Z=W C=W V=W"},
|
||||
{"inst": "svc #zimm" , "op": "11010100|000|zimm:16|00001"},
|
||||
{"inst": "svc #immZ" , "op": "11010100|000|immZ:16|00001"},
|
||||
{"inst": "sxtb Wd, Wn" , "op": "00010011|000|00000|0|00111|Rn|Rd"},
|
||||
{"inst": "sxtb Xd, Wn" , "op": "10010011|010|00000|0|00111|Rn|Rd"},
|
||||
{"inst": "sxth Wd, Wn" , "op": "00010011|000|00000|0|01111|Rn|Rd"},
|
||||
@@ -431,20 +431,20 @@
|
||||
{"inst": "ctz Xd, Xn" , "op": "11011010|110|00000|0|00110|Rn|Rd"},
|
||||
{"inst": "smax Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11000|Rn|Rd"},
|
||||
{"inst": "smax Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11000|Rn|Rd"},
|
||||
{"inst": "smax Wd, Wn, #simm" , "op": "00010001|110|000|simm:8|Rn|Rd"},
|
||||
{"inst": "smax Xd, Xn, #simm" , "op": "10010001|110|000|simm:8|Rn|Rd"},
|
||||
{"inst": "smax Wd, Wn, #immS" , "op": "00010001|110|000|immS:8|Rn|Rd"},
|
||||
{"inst": "smax Xd, Xn, #immS" , "op": "10010001|110|000|immS:8|Rn|Rd"},
|
||||
{"inst": "smin Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11010|Rn|Rd"},
|
||||
{"inst": "smin Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11010|Rn|Rd"},
|
||||
{"inst": "smin Wd, Wn, #simm" , "op": "00010001|110|010|simm:8|Rn|Rd"},
|
||||
{"inst": "smin Xd, Xn, #simm" , "op": "10010001|110|010|simm:8|Rn|Rd"},
|
||||
{"inst": "smin Wd, Wn, #immS" , "op": "00010001|110|010|immS:8|Rn|Rd"},
|
||||
{"inst": "smin Xd, Xn, #immS" , "op": "10010001|110|010|immS:8|Rn|Rd"},
|
||||
{"inst": "umax Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11001|Rn|Rd"},
|
||||
{"inst": "umax Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11001|Rn|Rd"},
|
||||
{"inst": "umax Wd, Wn, #simm" , "op": "00010001|110|001|simm:8|Rn|Rd"},
|
||||
{"inst": "umax Xd, Xn, #simm" , "op": "10010001|110|001|simm:8|Rn|Rd"},
|
||||
{"inst": "umax Wd, Wn, #immZ" , "op": "00010001|110|001|immZ:8|Rn|Rd"},
|
||||
{"inst": "umax Xd, Xn, #immZ" , "op": "10010001|110|001|immZ:8|Rn|Rd"},
|
||||
{"inst": "umin Wd, Wn, Wm" , "op": "00011010|110|Rm|0|11011|Rn|Rd"},
|
||||
{"inst": "umin Xd, Xn, Xm" , "op": "10011010|110|Rm|0|11011|Rn|Rd"},
|
||||
{"inst": "umin Wd, Wn, #simm" , "op": "00010001|110|011|simm:8|Rn|Rd"},
|
||||
{"inst": "umin Xd, Xn, #simm" , "op": "10010001|110|011|simm:8|Rn|Rd"}
|
||||
{"inst": "umin Wd, Wn, #immZ" , "op": "00010001|110|011|immZ:8|Rn|Rd"},
|
||||
{"inst": "umin Xd, Xn, #immZ" , "op": "10010001|110|011|immZ:8|Rn|Rd"}
|
||||
]},
|
||||
|
||||
{"category": "GP GP_EXT", "ext": "D128", "data": [
|
||||
@@ -510,21 +510,21 @@
|
||||
]},
|
||||
|
||||
{"category": "GP GP_EXT", "ext": "LRCPC2", "data": [
|
||||
{"inst": "ldapur Wd, [Xn|SP, #soff]" , "op": "10011001|010|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldapur Xd, [Xn|SP, #soff]" , "op": "11011001|010|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldapurb Wd, [Xn|SP, #soff]" , "op": "00011001|010|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldapurh Wd, [Xn|SP, #soff]" , "op": "01011001|010|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldapur Wd, [Xn|SP, #offS]" , "op": "10011001|010|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldapur Xd, [Xn|SP, #offS]" , "op": "11011001|010|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldapurb Wd, [Xn|SP, #offS]" , "op": "00011001|010|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldapurh Wd, [Xn|SP, #offS]" , "op": "01011001|010|offS:9|00|Rn|Rd"},
|
||||
|
||||
{"inst": "ldapursb Wd, [Xn|SP, #soff]" , "op": "00011001|110|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldapursb Xd, [Xn|SP, #soff]" , "op": "00011001|100|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldapursh Wd, [Xn|SP, #soff]" , "op": "01011001|110|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldapursh Xd, [Xn|SP, #soff]" , "op": "01011001|100|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldapursw Xd, [Xn|SP, #soff]" , "op": "10011001|100|soff:9|00|Rn|Rd"},
|
||||
{"inst": "ldapursb Wd, [Xn|SP, #offS]" , "op": "00011001|110|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldapursb Xd, [Xn|SP, #offS]" , "op": "00011001|100|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldapursh Wd, [Xn|SP, #offS]" , "op": "01011001|110|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldapursh Xd, [Xn|SP, #offS]" , "op": "01011001|100|offS:9|00|Rn|Rd"},
|
||||
{"inst": "ldapursw Xd, [Xn|SP, #offS]" , "op": "10011001|100|offS:9|00|Rn|Rd"},
|
||||
|
||||
{"inst": "stlur Ws, [Xn|SP, #soff]" , "op": "10011001|000|soff:9|00|Rn|Rs"},
|
||||
{"inst": "stlur Xs, [Xn|SP, #soff]" , "op": "11011001|000|soff:9|00|Rn|Rs"},
|
||||
{"inst": "stlurb Ws, [Xn|SP, #soff]" , "op": "00011001|000|soff:9|00|Rn|Rs"},
|
||||
{"inst": "stlurh Ws, [Xn|SP, #soff]" , "op": "01011001|000|soff:9|00|Rn|Rs"}
|
||||
{"inst": "stlur Ws, [Xn|SP, #offS]" , "op": "10011001|000|offS:9|00|Rn|Rs"},
|
||||
{"inst": "stlur Xs, [Xn|SP, #offS]" , "op": "11011001|000|offS:9|00|Rn|Rs"},
|
||||
{"inst": "stlurb Ws, [Xn|SP, #offS]" , "op": "00011001|000|offS:9|00|Rn|Rs"},
|
||||
{"inst": "stlurh Ws, [Xn|SP, #offS]" , "op": "01011001|000|offS:9|00|Rn|Rs"}
|
||||
]},
|
||||
|
||||
{"category": "GP GP_EXT", "ext": "LRCPC3", "data": [
|
||||
@@ -981,12 +981,12 @@
|
||||
{"inst": "cmpp Xn|SP, Xm|SP" , "op": "10111010|110|Rm|000000|Rn|11111"},
|
||||
{"inst": "gmi Xd, Xn|SP, Xm" , "op": "10011010|110|Rm|000101|Rn|Rd"},
|
||||
{"inst": "irg Xd, Xn|SP, Xm" , "op": "10011010|110|Rm|000100|Rn|Rd"},
|
||||
{"inst": "ldg Xd, [Xn|SP, #soff*16]" , "op": "11011001|011|soff:9|00|Rn|Rd"},
|
||||
{"inst": "st2g Xs|SP, [Xn|SP, #soff*16]{@}{!}" , "op": "11011001|101|soff:9|!post|W|Rn|Rs"},
|
||||
{"inst": "stg Xs|SP, [Xn|SP, #soff*16]{@}{!}" , "op": "11011001|001|soff:9|!post|W|Rn|Rs"},
|
||||
{"inst": "stgp Xs, Xs2, [Xn|SP, #soff*16]{@}{!}" , "op": "0110100|!post|W|0|soff:7|Rs2|Rn|Rs"},
|
||||
{"inst": "stz2g Xs|SP, [Xn|SP, #soff*16]{@}{!}" , "op": "11011001|111|soff:9|!post|W|Rn|Rs"},
|
||||
{"inst": "stzg Xs|SP, [Xn|SP, #soff*16]{@}{!}" , "op": "11011001|011|soff:9|!post|W|Rn|Rs"},
|
||||
{"inst": "ldg Xd, [Xn|SP, #offS*16]" , "op": "11011001|011|offS:9|00|Rn|Rd"},
|
||||
{"inst": "st2g Xs|SP, [Xn|SP, #offS*16]{@}{!}" , "op": "11011001|101|offS:9|!post|W|Rn|Rs"},
|
||||
{"inst": "stg Xs|SP, [Xn|SP, #offS*16]{@}{!}" , "op": "11011001|001|offS:9|!post|W|Rn|Rs"},
|
||||
{"inst": "stgp Xs, Xs2, [Xn|SP, #offS*16]{@}{!}" , "op": "0110100|!post|W|0|offS:7|Rs2|Rn|Rs"},
|
||||
{"inst": "stz2g Xs|SP, [Xn|SP, #offS*16]{@}{!}" , "op": "11011001|111|offS:9|!post|W|Rn|Rs"},
|
||||
{"inst": "stzg Xs|SP, [Xn|SP, #offS*16]{@}{!}" , "op": "11011001|011|offS:9|!post|W|Rn|Rs"},
|
||||
{"inst": "subg Xd|SP, Xn|SP, #imm1, #imm2" , "op": "11010001|10|imm1:6|00|imm2:4|Rn|Rd"},
|
||||
{"inst": "subp Xd, Xn|SP, Xm|SP" , "op": "10011010|110|Rm|0|00000|Rn|Rd"},
|
||||
{"inst": "subps Xd, Xn|SP, Xm|SP" , "op": "10011010|110|Rm|0|00000|Rn|Rd" , "io": "N=W Z=W C=W V=W"}
|
||||
@@ -1023,8 +1023,8 @@
|
||||
{"inst": "brabz Xn" , "op": "11010110|000|11111|0000|11|Rn|11111" , "control": "call"},
|
||||
{"inst": "eretaa" , "op": "11010110|100|11111|0000|10|11111|11111" , "control": "return"},
|
||||
{"inst": "eretab" , "op": "11010110|100|11111|0000|11|11111|11111" , "control": "return"},
|
||||
{"inst": "ldraa Xd, [Xn|SP, #soff]{!}" , "op": "11111000|0|soff:1|1|soff:9|W1|Rn|Rd"},
|
||||
{"inst": "ldrab Xd, [Xn|SP, #soff]{!}" , "op": "11111000|1|soff:1|1|soff:9|W1|Rn|Rd"},
|
||||
{"inst": "ldraa Xd, [Xn|SP, #offS]{!}" , "op": "11111000|0|offS:1|1|offS:9|W1|Rn|Rd"},
|
||||
{"inst": "ldrab Xd, [Xn|SP, #offS]{!}" , "op": "11111000|1|offS:1|1|offS:9|W1|Rn|Rd"},
|
||||
{"inst": "pacda Xd, Xn|SP" , "op": "11011010|110|00001|0|00010|Rn|Rd"},
|
||||
{"inst": "pacdb Xd, Xn|SP" , "op": "11011010|110|00001|0|00011|Rn|Rd"},
|
||||
{"inst": "pacdza Xd" , "op": "11011010|110|00001|0|01010|11111|Rd"},
|
||||
@@ -1768,40 +1768,40 @@
|
||||
{"inst": "ld4r 4x{Vd.t}, [Xn|SP, Xm]@" , "op": "01001101|111|Rm |1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||||
{"inst": "ld4r 4x{Vd.t}, [Xn|SP, #off==4<<sz]@" , "op": "00001101|111|11111|1110|sz|Rn|Vd" , "t": "8B 4H 2S 1D"},
|
||||
{"inst": "ld4r 4x{Vd.t}, [Xn|SP, #off==4<<sz]@" , "op": "01001101|111|11111|1110|sz|Rn|Vd" , "t": "16B 8H 4S 2D"},
|
||||
{"inst": "ldnp Sd, Sd2, [Xn|SP, #soff*4]" , "op": "00101100|01|soff:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldnp Dd, Dd2, [Xn|SP, #soff*8]" , "op": "01101100|01|soff:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldnp Qd, Qd2, [Xn|SP, #soff*16]" , "op": "10101100|01|soff:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldp Sd, Sd2, [Xn|SP, #soff*4]{@}{!}" , "op": "0010110|!post|W|1|soff:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldp Dd, Dd2, [Xn|SP, #soff*8]{@}{!}" , "op": "0110110|!post|W|1|soff:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldp Qd, Qd2, [Xn|SP, #soff*16]{@}{!}" , "op": "1010110|!post|W|1|soff:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldnp Sd, Sd2, [Xn|SP, #offS*4]" , "op": "00101100|01|offS:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldnp Dd, Dd2, [Xn|SP, #offS*8]" , "op": "01101100|01|offS:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldnp Qd, Qd2, [Xn|SP, #offS*16]" , "op": "10101100|01|offS:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldp Sd, Sd2, [Xn|SP, #offS*4]{@}{!}" , "op": "0010110|!post|W|1|offS:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldp Dd, Dd2, [Xn|SP, #offS*8]{@}{!}" , "op": "0110110|!post|W|1|offS:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldp Qd, Qd2, [Xn|SP, #offS*16]{@}{!}" , "op": "1010110|!post|W|1|offS:7|Vd2|Vn|Vd"},
|
||||
{"inst": "ldr Bd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111100|011|Rm|option:3|n:1|10|Rn|Vd"},
|
||||
{"inst": "ldr Hd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111100|011|Rm|option:3|n:1|10|Rn|Vd"},
|
||||
{"inst": "ldr Sd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*2}]" , "op": "10111100|011|Rm|option:3|n:1|10|Rn|Vd"},
|
||||
{"inst": "ldr Dd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*3}]" , "op": "11111100|011|Rm|option:3|n:1|10|Rn|Vd"},
|
||||
{"inst": "ldr Qd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*4}]" , "op": "00111100|111|Rm|option:3|n:1|10|Rn|Vd"},
|
||||
{"inst": "ldr Sd, [PC, #soff*4]" , "op": "00011100|soff:19|Vd"},
|
||||
{"inst": "ldr Dd, [PC, #soff*4]" , "op": "01011100|soff:19|Vd"},
|
||||
{"inst": "ldr Qd, [PC, #soff*4]" , "op": "10011100|soff:19|Vd"},
|
||||
{"inst": "ldr Bd, [Xn|SP, #zoff]" , "op": "00111101|01|zoff:12|Rn|Vd"},
|
||||
{"inst": "ldr Hd, [Xn|SP, #zoff*2]" , "op": "01111101|01|zoff:12|Rn|Vd"},
|
||||
{"inst": "ldr Sd, [Xn|SP, #zoff*4]" , "op": "10111101|01|zoff:12|Rn|Vd"},
|
||||
{"inst": "ldr Dd, [Xn|SP, #zoff*8]" , "op": "11111101|01|zoff:12|Rn|Vd"},
|
||||
{"inst": "ldr Qd, [Xn|SP, #zoff*16]" , "op": "00111101|11|zoff:12|Rn|Vd"},
|
||||
{"inst": "ldr Bd, [Xn|SP, #soff]!" , "op": "00111100|010|soff:9|11|Rn|Vd"},
|
||||
{"inst": "ldr Hd, [Xn|SP, #soff*2]!" , "op": "01111100|010|soff:9|11|Rn|Vd"},
|
||||
{"inst": "ldr Sd, [Xn|SP, #soff*4]!" , "op": "10111100|010|soff:9|11|Rn|Vd"},
|
||||
{"inst": "ldr Dd, [Xn|SP, #soff*8]!" , "op": "11111100|010|soff:9|11|Rn|Vd"},
|
||||
{"inst": "ldr Qd, [Xn|SP, #soff*16]!" , "op": "00111100|110|soff:9|11|Rn|Vd"},
|
||||
{"inst": "ldr Bd, [Xn|SP, #soff]@" , "op": "00111100|010|soff:9|01|Rn|Vd"},
|
||||
{"inst": "ldr Hd, [Xn|SP, #soff*2]@" , "op": "01111100|010|soff:9|01|Rn|Vd"},
|
||||
{"inst": "ldr Sd, [Xn|SP, #soff*4]@" , "op": "10111100|010|soff:9|01|Rn|Vd"},
|
||||
{"inst": "ldr Dd, [Xn|SP, #soff*8]@" , "op": "11111100|010|soff:9|01|Rn|Vd"},
|
||||
{"inst": "ldr Qd, [Xn|SP, #soff*16]@" , "op": "00111100|110|soff:9|01|Rn|Vd"},
|
||||
{"inst": "ldur Bd, [Xn|SP, #soff]" , "op": "00111100|010|soff:9|00|Rn|Vd"},
|
||||
{"inst": "ldur Hd, [Xn|SP, #soff]" , "op": "01111100|010|soff:9|00|Rn|Vd"},
|
||||
{"inst": "ldur Sd, [Xn|SP, #soff]" , "op": "10111100|010|soff:9|00|Rn|Vd"},
|
||||
{"inst": "ldur Dd, [Xn|SP, #soff]" , "op": "11111100|010|soff:9|00|Rn|Vd"},
|
||||
{"inst": "ldur Qd, [Xn|SP, #soff]" , "op": "00111100|110|soff:9|00|Rn|Vd"},
|
||||
{"inst": "ldr Sd, [PC, #offS*4]" , "op": "00011100|offS:19|Vd"},
|
||||
{"inst": "ldr Dd, [PC, #offS*4]" , "op": "01011100|offS:19|Vd"},
|
||||
{"inst": "ldr Qd, [PC, #offS*4]" , "op": "10011100|offS:19|Vd"},
|
||||
{"inst": "ldr Bd, [Xn|SP, #offZ]" , "op": "00111101|01|offZ:12|Rn|Vd"},
|
||||
{"inst": "ldr Hd, [Xn|SP, #offZ*2]" , "op": "01111101|01|offZ:12|Rn|Vd"},
|
||||
{"inst": "ldr Sd, [Xn|SP, #offZ*4]" , "op": "10111101|01|offZ:12|Rn|Vd"},
|
||||
{"inst": "ldr Dd, [Xn|SP, #offZ*8]" , "op": "11111101|01|offZ:12|Rn|Vd"},
|
||||
{"inst": "ldr Qd, [Xn|SP, #offZ*16]" , "op": "00111101|11|offZ:12|Rn|Vd"},
|
||||
{"inst": "ldr Bd, [Xn|SP, #offS]!" , "op": "00111100|010|offS:9|11|Rn|Vd"},
|
||||
{"inst": "ldr Hd, [Xn|SP, #offS*2]!" , "op": "01111100|010|offS:9|11|Rn|Vd"},
|
||||
{"inst": "ldr Sd, [Xn|SP, #offS*4]!" , "op": "10111100|010|offS:9|11|Rn|Vd"},
|
||||
{"inst": "ldr Dd, [Xn|SP, #offS*8]!" , "op": "11111100|010|offS:9|11|Rn|Vd"},
|
||||
{"inst": "ldr Qd, [Xn|SP, #offS*16]!" , "op": "00111100|110|offS:9|11|Rn|Vd"},
|
||||
{"inst": "ldr Bd, [Xn|SP, #offS]@" , "op": "00111100|010|offS:9|01|Rn|Vd"},
|
||||
{"inst": "ldr Hd, [Xn|SP, #offS*2]@" , "op": "01111100|010|offS:9|01|Rn|Vd"},
|
||||
{"inst": "ldr Sd, [Xn|SP, #offS*4]@" , "op": "10111100|010|offS:9|01|Rn|Vd"},
|
||||
{"inst": "ldr Dd, [Xn|SP, #offS*8]@" , "op": "11111100|010|offS:9|01|Rn|Vd"},
|
||||
{"inst": "ldr Qd, [Xn|SP, #offS*16]@" , "op": "00111100|110|offS:9|01|Rn|Vd"},
|
||||
{"inst": "ldur Bd, [Xn|SP, #offS]" , "op": "00111100|010|offS:9|00|Rn|Vd"},
|
||||
{"inst": "ldur Hd, [Xn|SP, #offS]" , "op": "01111100|010|offS:9|00|Rn|Vd"},
|
||||
{"inst": "ldur Sd, [Xn|SP, #offS]" , "op": "10111100|010|offS:9|00|Rn|Vd"},
|
||||
{"inst": "ldur Dd, [Xn|SP, #offS]" , "op": "11111100|010|offS:9|00|Rn|Vd"},
|
||||
{"inst": "ldur Qd, [Xn|SP, #offS]" , "op": "00111100|110|offS:9|00|Rn|Vd"},
|
||||
{"inst": "mla Vx.t, Vn.t, Vm.t" , "op": "00001110|sz|1|Vm|10010|1|Vn|Vx" , "t": "8B 4H 2S"},
|
||||
{"inst": "mla Vx.t, Vn.t, Vm.t" , "op": "01001110|sz|1|Vm|10010|1|Vn|Vx" , "t": "16B 8H 4S"},
|
||||
{"inst": "mla Vx.4H, Vn.4H, Vm.H[#idx]" , "op": "00101111|01|idx[1:0]|Vm:4|0000|idx[2]|0|Vn|Vx"},
|
||||
@@ -1934,18 +1934,18 @@
|
||||
{"inst": "sminv Hd, Vn.4H" , "op": "00001110|01|11000|11010|10|Vn|Vd"},
|
||||
{"inst": "sminv Hd, Vn.8H" , "op": "01001110|01|11000|11010|10|Vn|Vd"},
|
||||
{"inst": "sminv Sd, Vn.4S" , "op": "01001110|10|11000|11010|10|Vn|Vd"},
|
||||
{"inst": "smlal Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10000|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
|
||||
{"inst": "smlal2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10000|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
|
||||
{"inst": "smlal Vd.4S, Vn.4H, Vm.H[#dx]" , "op": "00001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vd"},
|
||||
{"inst": "smlal2 Vd.4S, Vn.8H, Vm.H[#dx]" , "op": "01001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vd"},
|
||||
{"inst": "smlal Vd.2D, Vn.2S, Vm.S[#dx]" , "op": "00001111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vd"},
|
||||
{"inst": "smlal2 Vd.2D, Vn.4S, Vm.S[#dx]" , "op": "01001111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vd"},
|
||||
{"inst": "smlsl Vd.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10100|0|Vn|Vd" , "t": "8H.8B 4S.4H 2D.2S"},
|
||||
{"inst": "smlsl2 Vd.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10100|0|Vn|Vd" , "t": "8H.16B 4S.8H 2D.4S"},
|
||||
{"inst": "smlsl Vd.4S, Vn.4H, Vm.H[#dx]" , "op": "00001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vd"},
|
||||
{"inst": "smlsl2 Vd.4S, Vn.8H, Vm.H[#dx]" , "op": "01001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vd"},
|
||||
{"inst": "smlsl Vd.2D, Vn.2S, Vm.S[#dx]" , "op": "00001111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vd"},
|
||||
{"inst": "smlsl2 Vd.2D, Vn.4S, Vm.S[#dx]" , "op": "01001111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vd"},
|
||||
{"inst": "smlal Vx.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10000|0|Vn|Vx" , "t": "8H.8B 4S.4H 2D.2S"},
|
||||
{"inst": "smlal2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10000|0|Vn|Vx" , "t": "8H.16B 4S.8H 2D.4S"},
|
||||
{"inst": "smlal Vx.4S, Vn.4H, Vm.H[#dx]" , "op": "00001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vx"},
|
||||
{"inst": "smlal2 Vx.4S, Vn.8H, Vm.H[#dx]" , "op": "01001111|01|idx[1:0]|Vm:4|0010|idx[2]|0|Vn|Vx"},
|
||||
{"inst": "smlal Vx.2D, Vn.2S, Vm.S[#dx]" , "op": "00001111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vx"},
|
||||
{"inst": "smlal2 Vx.2D, Vn.4S, Vm.S[#dx]" , "op": "01001111|10|idx[0] |Vm |0010|idx[1]|0|Vn|Vx"},
|
||||
{"inst": "smlsl Vx.ta, Vn.tb, Vm.tb" , "op": "00001110|sz|1|Vm|10100|0|Vn|Vx" , "t": "8H.8B 4S.4H 2D.2S"},
|
||||
{"inst": "smlsl2 Vx.ta, Vn.tb, Vm.tb" , "op": "01001110|sz|1|Vm|10100|0|Vn|Vx" , "t": "8H.16B 4S.8H 2D.4S"},
|
||||
{"inst": "smlsl Vx.4S, Vn.4H, Vm.H[#dx]" , "op": "00001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vx"},
|
||||
{"inst": "smlsl2 Vx.4S, Vn.8H, Vm.H[#dx]" , "op": "01001111|01|idx[1:0]|Vm:4|0110|idx[2]|0|Vn|Vx"},
|
||||
{"inst": "smlsl Vx.2D, Vn.2S, Vm.S[#dx]" , "op": "00001111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vx"},
|
||||
{"inst": "smlsl2 Vx.2D, Vn.4S, Vm.S[#dx]" , "op": "01001111|10|idx[0] |Vm |0110|idx[1]|0|Vn|Vx"},
|
||||
{"inst": "smov Wd, Vn.B[#idx]" , "op": "00001110|00|0|idx:4| 1|00101|1|Vn|Rd"},
|
||||
{"inst": "smov Wd, Vn.H[#idx]" , "op": "00001110|00|0|idx:3| 10|00101|1|Vn|Rd"},
|
||||
{"inst": "smov Xd, Vn.B[#idx]" , "op": "01001110|00|0|idx:4| 1|00101|1|Vn|Rd"},
|
||||
@@ -2216,37 +2216,37 @@
|
||||
{"inst": "st4 4x{Vs.t}+, [Xn|SP, Xm]@" , "op": "01001100|100|Rm |0000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||||
{"inst": "st4 4x{Vs.t}+, [Xn|SP, #off==32]@" , "op": "00001100|100|11111|0000|sz|Rn|Vs" , "t": "8B 4H 2S"},
|
||||
{"inst": "st4 4x{Vs.t}+, [Xn|SP, #off==64]@" , "op": "01001100|100|11111|0000|sz|Rn|Vs" , "t": "16B 8H 4S 2D"},
|
||||
{"inst": "stnp Sd, Sd2, [Xn|SP, #soff*4]" , "op": "00101100|00|soff:7|Vs2|Vn|Vs"},
|
||||
{"inst": "stnp Dd, Dd2, [Xn|SP, #soff*8]" , "op": "01101100|00|soff:7|Vs2|Vn|Vs"},
|
||||
{"inst": "stnp Qd, Qd2, [Xn|SP, #soff*16]" , "op": "10101100|00|soff:7|Vs2|Vn|Vs"},
|
||||
{"inst": "stp Sd, Sd2, [Xn|SP, #soff*4]{@}{!}" , "op": "0010110|!post|W|0|soff:7|Vs2|Vn|Vs"},
|
||||
{"inst": "stp Dd, Dd2, [Xn|SP, #soff*8]{@}{!}" , "op": "0110110|!post|W|0|soff:7|Vs2|Vn|Vs"},
|
||||
{"inst": "stp Qd, Qd2, [Xn|SP, #soff*16]{@}{!}" , "op": "1010110|!post|W|0|soff:7|Vs2|Vn|Vs"},
|
||||
{"inst": "stnp Sd, Sd2, [Xn|SP, #offS*4]" , "op": "00101100|00|offS:7|Vs2|Vn|Vs"},
|
||||
{"inst": "stnp Dd, Dd2, [Xn|SP, #offS*8]" , "op": "01101100|00|offS:7|Vs2|Vn|Vs"},
|
||||
{"inst": "stnp Qd, Qd2, [Xn|SP, #offS*16]" , "op": "10101100|00|offS:7|Vs2|Vn|Vs"},
|
||||
{"inst": "stp Sd, Sd2, [Xn|SP, #offS*4]{@}{!}" , "op": "0010110|!post|W|0|offS:7|Vs2|Vn|Vs"},
|
||||
{"inst": "stp Dd, Dd2, [Xn|SP, #offS*8]{@}{!}" , "op": "0110110|!post|W|0|offS:7|Vs2|Vn|Vs"},
|
||||
{"inst": "stp Qd, Qd2, [Xn|SP, #offS*16]{@}{!}" , "op": "1010110|!post|W|0|offS:7|Vs2|Vn|Vs"},
|
||||
{"inst": "str Bd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "00111100|001|Rm|option:3|n:1|10|Rn|Vs"},
|
||||
{"inst": "str Hd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n}]" , "op": "01111100|001|Rm|option:3|n:1|10|Rn|Vs"},
|
||||
{"inst": "str Sd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*2}]" , "op": "10111100|001|Rm|option:3|n:1|10|Rn|Vs"},
|
||||
{"inst": "str Dd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*3}]" , "op": "11111100|001|Rm|option:3|n:1|10|Rn|Vs"},
|
||||
{"inst": "str Qd, [Xn|SP, Rm, {uxtw|lsl|sxtw|sxtx #n*4}]" , "op": "00111100|101|Rm|option:3|n:1|10|Rn|Vs"},
|
||||
{"inst": "str Bd, [Xn|SP, #zoff]" , "op": "00111101|00|zoff:12|Rn|Vs"},
|
||||
{"inst": "str Hd, [Xn|SP, #zoff*2]" , "op": "01111101|00|zoff:12|Rn|Vs"},
|
||||
{"inst": "str Sd, [Xn|SP, #zoff*4]" , "op": "10111101|00|zoff:12|Rn|Vs"},
|
||||
{"inst": "str Dd, [Xn|SP, #zoff*8]" , "op": "11111101|00|zoff:12|Rn|Vs"},
|
||||
{"inst": "str Qd, [Xn|SP, #zoff*16]" , "op": "00111101|10|zoff:12|Rn|Vs"},
|
||||
{"inst": "str Bd, [Xn|SP, #soff]!" , "op": "00111100|000|soff:9|11|Rn|Vs"},
|
||||
{"inst": "str Hd, [Xn|SP, #soff*2]!" , "op": "01111100|000|soff:9|11|Rn|Vs"},
|
||||
{"inst": "str Sd, [Xn|SP, #soff*4]!" , "op": "10111100|000|soff:9|11|Rn|Vs"},
|
||||
{"inst": "str Dd, [Xn|SP, #soff*8]!" , "op": "11111100|000|soff:9|11|Rn|Vs"},
|
||||
{"inst": "str Qd, [Xn|SP, #soff*16]!" , "op": "00111100|100|soff:9|11|Rn|Vs"},
|
||||
{"inst": "str Bd, [Xn|SP, #soff]@" , "op": "00111100|000|soff:9|01|Rn|Vs"},
|
||||
{"inst": "str Hd, [Xn|SP, #soff*2]@" , "op": "01111100|000|soff:9|01|Rn|Vs"},
|
||||
{"inst": "str Sd, [Xn|SP, #soff*4]@" , "op": "10111100|000|soff:9|01|Rn|Vs"},
|
||||
{"inst": "str Dd, [Xn|SP, #soff*8]@" , "op": "11111100|000|soff:9|01|Rn|Vs"},
|
||||
{"inst": "str Qd, [Xn|SP, #soff*16]@" , "op": "00111100|100|soff:9|01|Rn|Vs"},
|
||||
{"inst": "stur Bd, [Xn|SP, #soff]" , "op": "00111100|000|soff:9|00|Rn|Vs"},
|
||||
{"inst": "stur Hd, [Xn|SP, #soff]" , "op": "01111100|000|soff:9|00|Rn|Vs"},
|
||||
{"inst": "stur Sd, [Xn|SP, #soff]" , "op": "10111100|000|soff:9|00|Rn|Vs"},
|
||||
{"inst": "stur Dd, [Xn|SP, #soff]" , "op": "11111100|000|soff:9|00|Rn|Vs"},
|
||||
{"inst": "stur Qd, [Xn|SP, #soff]" , "op": "00111100|100|soff:9|00|Rn|Vs"},
|
||||
{"inst": "str Bd, [Xn|SP, #offZ]" , "op": "00111101|00|offZ:12|Rn|Vs"},
|
||||
{"inst": "str Hd, [Xn|SP, #offZ*2]" , "op": "01111101|00|offZ:12|Rn|Vs"},
|
||||
{"inst": "str Sd, [Xn|SP, #offZ*4]" , "op": "10111101|00|offZ:12|Rn|Vs"},
|
||||
{"inst": "str Dd, [Xn|SP, #offZ*8]" , "op": "11111101|00|offZ:12|Rn|Vs"},
|
||||
{"inst": "str Qd, [Xn|SP, #offZ*16]" , "op": "00111101|10|offZ:12|Rn|Vs"},
|
||||
{"inst": "str Bd, [Xn|SP, #offS]!" , "op": "00111100|000|offS:9|11|Rn|Vs"},
|
||||
{"inst": "str Hd, [Xn|SP, #offS*2]!" , "op": "01111100|000|offS:9|11|Rn|Vs"},
|
||||
{"inst": "str Sd, [Xn|SP, #offS*4]!" , "op": "10111100|000|offS:9|11|Rn|Vs"},
|
||||
{"inst": "str Dd, [Xn|SP, #offS*8]!" , "op": "11111100|000|offS:9|11|Rn|Vs"},
|
||||
{"inst": "str Qd, [Xn|SP, #offS*16]!" , "op": "00111100|100|offS:9|11|Rn|Vs"},
|
||||
{"inst": "str Bd, [Xn|SP, #offS]@" , "op": "00111100|000|offS:9|01|Rn|Vs"},
|
||||
{"inst": "str Hd, [Xn|SP, #offS*2]@" , "op": "01111100|000|offS:9|01|Rn|Vs"},
|
||||
{"inst": "str Sd, [Xn|SP, #offS*4]@" , "op": "10111100|000|offS:9|01|Rn|Vs"},
|
||||
{"inst": "str Dd, [Xn|SP, #offS*8]@" , "op": "11111100|000|offS:9|01|Rn|Vs"},
|
||||
{"inst": "str Qd, [Xn|SP, #offS*16]@" , "op": "00111100|100|offS:9|01|Rn|Vs"},
|
||||
{"inst": "stur Bd, [Xn|SP, #offS]" , "op": "00111100|000|offS:9|00|Rn|Vs"},
|
||||
{"inst": "stur Hd, [Xn|SP, #offS]" , "op": "01111100|000|offS:9|00|Rn|Vs"},
|
||||
{"inst": "stur Sd, [Xn|SP, #offS]" , "op": "10111100|000|offS:9|00|Rn|Vs"},
|
||||
{"inst": "stur Dd, [Xn|SP, #offS]" , "op": "11111100|000|offS:9|00|Rn|Vs"},
|
||||
{"inst": "stur Qd, [Xn|SP, #offS]" , "op": "00111100|100|offS:9|00|Rn|Vs"},
|
||||
{"inst": "sub Dd, Dn, Dm" , "op": "01111110|11|1|Vm|10000|1|Vn|Vd"},
|
||||
{"inst": "sub Vd.t, Vn.t, Vm.t" , "op": "00101110|sz|1|Vm|10000|1|Vn|Vd" , "t": "8B 4H 2S"},
|
||||
{"inst": "sub Vd.t, Vn.t, Vm.t" , "op": "01101110|sz|1|Vm|10000|1|Vn|Vd" , "t": "16B 8H 4S 2D"},
|
||||
@@ -2810,17 +2810,17 @@
|
||||
|
||||
{"category": "ASIMD", "ext": "ASIMD LRCPC3", "data": [
|
||||
{"inst": "ldap1 Vd.D[#idx], [Xn|SP]" , "op": "0|idx:1|001101|010|00001|10000|1|Rn|Vd"},
|
||||
{"inst": "ldapur Bd, [Xn|SP, #soff]" , "op": "00011101|010|soff:9|10|Rn|Vd"},
|
||||
{"inst": "ldapur Hd, [Xn|SP, #soff]" , "op": "01011101|010|soff:9|10|Rn|Vd"},
|
||||
{"inst": "ldapur Sd, [Xn|SP, #soff]" , "op": "10011101|010|soff:9|10|Rn|Vd"},
|
||||
{"inst": "ldapur Dd, [Xn|SP, #soff]" , "op": "11011101|010|soff:9|10|Rn|Vd"},
|
||||
{"inst": "ldapur Qd, [Xn|SP, #soff]" , "op": "00011101|110|soff:9|10|Rn|Vd"},
|
||||
{"inst": "ldapur Bd, [Xn|SP, #offS]" , "op": "00011101|010|offS:9|10|Rn|Vd"},
|
||||
{"inst": "ldapur Hd, [Xn|SP, #offS]" , "op": "01011101|010|offS:9|10|Rn|Vd"},
|
||||
{"inst": "ldapur Sd, [Xn|SP, #offS]" , "op": "10011101|010|offS:9|10|Rn|Vd"},
|
||||
{"inst": "ldapur Dd, [Xn|SP, #offS]" , "op": "11011101|010|offS:9|10|Rn|Vd"},
|
||||
{"inst": "ldapur Qd, [Xn|SP, #offS]" , "op": "00011101|110|offS:9|10|Rn|Vd"},
|
||||
{"inst": "stl1 Vs.D[#idx], [Xn|SP]" , "op": "0|idx:1|001101|000|00001|10000|1|Rn|Vs"},
|
||||
{"inst": "stlur Bs, [Xn|SP, #soff]" , "op": "00011101|000|soff:9|10|Rn|Vs"},
|
||||
{"inst": "stlur Hs, [Xn|SP, #soff]" , "op": "01011101|000|soff:9|10|Rn|Vs"},
|
||||
{"inst": "stlur Ss, [Xn|SP, #soff]" , "op": "10011101|000|soff:9|10|Rn|Vs"},
|
||||
{"inst": "stlur Ds, [Xn|SP, #soff]" , "op": "11011101|000|soff:9|10|Rn|Vs"},
|
||||
{"inst": "stlur Qs, [Xn|SP, #soff]" , "op": "00011101|100|soff:9|10|Rn|Vs"}
|
||||
{"inst": "stlur Bs, [Xn|SP, #offS]" , "op": "00011101|000|offS:9|10|Rn|Vs"},
|
||||
{"inst": "stlur Hs, [Xn|SP, #offS]" , "op": "01011101|000|offS:9|10|Rn|Vs"},
|
||||
{"inst": "stlur Ss, [Xn|SP, #offS]" , "op": "10011101|000|offS:9|10|Rn|Vs"},
|
||||
{"inst": "stlur Ds, [Xn|SP, #offS]" , "op": "11011101|000|offS:9|10|Rn|Vs"},
|
||||
{"inst": "stlur Qs, [Xn|SP, #offS]" , "op": "00011101|100|offS:9|10|Rn|Vs"}
|
||||
]},
|
||||
|
||||
{"category": "ASIMD", "ext": "RDM", "data": [
|
||||
|
||||
@@ -2626,7 +2626,7 @@
|
||||
{"category": "AVX SIMD", "ext": "AVX SM3", "data": [
|
||||
{"inst": "vsm3msg1 X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.NP.0F38.W0 DA /r"},
|
||||
{"inst": "vsm3msg2 X:xmm, xmm, xmm/m128" , "op": "RVM: VEX.128.66.0F38.W0 DA /r"},
|
||||
{"inst": "vsm3rnds2 X:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.W0 DE /r /ib"}
|
||||
{"inst": "vsm3rnds2 X:xmm, xmm, xmm/m128, ib/ub" , "op": "RVM: VEX.128.66.0F3A.W0 DE /r ib"}
|
||||
]},
|
||||
|
||||
{"category": "AVX SIMD", "ext": "AVX SM4", "data": [
|
||||
|
||||
Reference in New Issue
Block a user