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Added more instructions (System, MPX, AVX512_VPOPCNTDQ, AVX512_4FMAPS, AVX512_4VNNIW)

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kobalicek
2017-02-21 01:55:07 +01:00
parent bb8b6d9fa2
commit aa154e3590
11 changed files with 5893 additions and 5573 deletions
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6
README.md
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@@ -1568,15 +1568,15 @@ int main(int argc, char* argv[]) {
### Error Handling
AsmJit uses error codes to represent and return errors. Every function where error can occur returns **Error**. Exceptions are never thrown by AsmJit even in extreme conditions like out-of-memory. Errors should never be ignored, however, checking errors after each asmjit API call would simply be overcomplicate the whole code generation. To handle these errors AsmJit provides **ErrorHandler**, which contains **handleError()**:
AsmJit uses error codes to represent and return errors. Every function where error can occur returns **Error**. Exceptions are never thrown by AsmJit even in extreme conditions like out-of-memory. Errors should never be ignored, however, checking errors after each asmjit API call would simply overcomplicate the whole code generation. To handle these errors AsmJit provides **ErrorHandler**, which contains **handleError()**:
`virtual bool handleError(Error err, const char* message, CodeEmitter* origin) = 0;`
That can be overridden by AsmJit users and do the following:
* 1. Return `true` or `false` from `handleError()`. If `true` is returned it means that error was handled and AsmJit can continue execution. The error code still be propagated to the caller, but won't put the origin into an error state (it won't set last-error). However, `false` reports to AsmJit that the error cannot be handled - in such case it stores the error, which can retrieved later by `getLastError()`. Returning `false` is the default behavior when no error handler is provided. To put the assembler into a non-error state again the `resetLastError()` must be called.
* 1. Return `true` or `false` from `handleError()`. If `true` is returned it means that error was handled and AsmJit can continue execution. The error code still be propagated to the caller, but the error origin (CodeEmitter) won't be put into an error state (last-error won't be set and `isInErrorState()` would return `true`). However, `false` reports to AsmJit that the error cannot be handled - in such case it stores the error, which can be retrieved later by `getLastError()`. Returning `false` is the default behavior when no error handler is provided. To put the assembler into a non-error state again `resetLastError()` must be called.
* 2. Throw an exception. AsmJit doesn't use exceptions and is completely exception-safe, but you can throw exception from the error handler if this way is easier / preferred by you. Throwing an exception acts virtually as returning `true` - AsmJit won't store the error.
* 3. Use plain old C's `setjmp()` and `longjmp()`. Asmjit always puts `Assembler` and `Compiler` to a consistent state before calling the `handleError()` so `longjmp()` can be used without issues to cancel the code-generation if an error occurred.
* 3. Use plain old C's `setjmp()` and `longjmp()`. Asmjit always puts `Assembler` and `Compiler` to a consistent state before calling the `handleError()` so `longjmp()` can be used without issues to cancel the code-generation if an error occurred. This method can be used if exception handling in your project is turned off and you still want some comfort. In most cases it should be safe as AsmJit is based on Zone memory, so no memory leaks will occur if you jump back to a location where `CodeHolder` still exist.
**ErrorHandler** is simply attached to **CodeHolder** and will be used by every emitter attached to it. The first example uses error handler that just prints the error, but lets AsmJit continue:

8
src/asmjit/base/codeholder.cpp
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@@ -194,11 +194,15 @@ Error CodeHolder::detach(CodeEmitter* emitter) noexcept {
// NOTE: We always detach if we were asked to, if error happens during
// `emitter->onDetach()` we just propagate it, but the CodeEmitter will
// be detached.
if (!emitter->_destroyed)
if (!emitter->_destroyed) {
if (type == CodeEmitter::kTypeAssembler)
static_cast<Assembler*>(emitter)->sync();
err = emitter->onDetach(this);
}
// Special case - detach `Assembler`.
if (type == CodeEmitter::kTypeAssembler) _cgAsm = nullptr;
if (type == CodeEmitter::kTypeAssembler)
_cgAsm = nullptr;
// Remove from a single-linked list of `CodeEmitter`s.
CodeEmitter** pPrev = &_emitters;

1
src/asmjit/base/globals.cpp
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@@ -67,6 +67,7 @@ static const char errorMessages[] =
"Invalid use of a low 8-bit GPB register\0"
"Invalid use of a 64-bit GPQ register in 32-bit mode\0"
"Invalid use of an 80-bit float\0"
"Not consecutive registers\0"
"No more physical registers\0"
"Overlapped registers\0"
"Overlapping register and arguments base-address register\0"

2
src/asmjit/base/globals.h
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@@ -215,6 +215,8 @@ ASMJIT_ENUM(ErrorCode) {
kErrorInvalidUseOfGpq,
//! Invalid use of an 80-bit float (TypeId::kF80).
kErrorInvalidUseOfF80,
//! Some registers in the instruction muse be consecutive (some ARM and AVX512 neural-net instructions).
kErrorNotConsecutiveRegs,
//! AsmJit requires a physical register, but no one is available.
kErrorNoMorePhysRegs,

72
src/asmjit/x86/x86assembler.cpp
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@@ -752,7 +752,9 @@ CaseX86M_GPB_MulDiv:
case X86Inst::kEncodingX86Rm:
ADD_PREFIX_BY_SIZE(o0.getSize());
ASMJIT_FALLTHROUGH;
case X86Inst::kEncodingX86Rm_NoRexW:
if (isign3 == ENC_OPS2(Reg, Reg)) {
opReg = o0.getId();
rbReg = o1.getId();
@@ -766,6 +768,24 @@ CaseX86M_GPB_MulDiv:
}
break;
case X86Inst::kEncodingX86Mr:
ADD_PREFIX_BY_SIZE(o0.getSize());
ASMJIT_FALLTHROUGH;
case X86Inst::kEncodingX86Mr_NoSize:
if (isign3 == ENC_OPS2(Reg, Reg)) {
rbReg = o0.getId();
opReg = o1.getId();
goto EmitX86R;
}
if (isign3 == ENC_OPS2(Mem, Reg)) {
rmRel = &o0;
opReg = o1.getId();
goto EmitX86M;
}
break;
case X86Inst::kEncodingX86Arith:
if (isign3 == ENC_OPS2(Reg, Reg)) {
if (o0.getSize() != o1.getSize())
@@ -1989,6 +2009,36 @@ CaseX86Pop_Gp:
rbReg = 0;
goto EmitX86R;
case X86Inst::kEncodingX86Bndmov:
if (isign3 == ENC_OPS2(Reg, Reg)) {
opReg = o0.getId();
rbReg = o1.getId();
// ModRM encoding:
if (!(options & X86Inst::kOptionModMR))
goto EmitX86R;
// ModMR encoding:
opCode = commonData->getAltOpCode();
std::swap(opReg, rbReg);
goto EmitX86R;
}
if (isign3 == ENC_OPS2(Reg, Mem)) {
opReg = o0.getId();
rmRel = &o1;
goto EmitX86M;
}
if (isign3 == ENC_OPS2(Mem, Reg)) {
opCode = commonData->getAltOpCode();
rmRel = &o0;
opReg = o1.getId();
goto EmitX86M;
}
break;
// ------------------------------------------------------------------------
// [FPU]
// ------------------------------------------------------------------------
@@ -2727,6 +2777,27 @@ CaseVexRm:
}
break;
case X86Inst::kEncodingVexRm_T1_4X: {
if (X86Reg::isZmm(o0 ) && X86Reg::isZmm(o1) &&
X86Reg::isZmm(o2 ) && X86Reg::isZmm(o3) &&
X86Reg::isZmm(_op4) && _op5.isMem()) {
// Registers [o1, o2, o3, _op4] must start aligned and must be consecutive.
uint32_t i1 = o1.getId();
uint32_t i2 = o2.getId();
uint32_t i3 = o3.getId();
uint32_t i4 = _op4.getId();
if (ASMJIT_UNLIKELY((i1 & 0x3) != 0 || i2 != i1 + 1 || i3 != i1 + 2 || i4 != i1 + 3))
goto NotConsecutiveRegs;
opReg = o0.getId();
rmRel = &_op5;
goto EmitVexEvexM;
}
break;
}
case X86Inst::kEncodingVexRmi_Wx:
ADD_REX_W(X86Reg::isGpq(o0) | X86Reg::isGpq(o1));
goto CaseVexRmi;
@@ -4331,6 +4402,7 @@ ERROR_HANDLER(InvalidDisplacement)
ERROR_HANDLER(InvalidSegment)
ERROR_HANDLER(OperandSizeMismatch)
ERROR_HANDLER(AmbiguousOperandSize)
ERROR_HANDLER(NotConsecutiveRegs)
Failed:
return _emitFailed(err, instId, options, o0, o1, o2, o3);

5238
src/asmjit/x86/x86emitter.h
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File diff suppressed because it is too large Load Diff

5713
src/asmjit/x86/x86inst.cpp
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File diff suppressed because it is too large Load Diff

139
src/asmjit/x86/x86inst.h
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@@ -61,6 +61,7 @@ struct X86Inst {
kIdAndnps, // [ANY] {SSE}
kIdAndpd, // [ANY] {SSE2}
kIdAndps, // [ANY] {SSE}
kIdArpl, // [X86]
kIdBextr, // [ANY] {BMI}
kIdBlcfill, // [ANY] {TBM}
kIdBlci, // [ANY] {TBM}
@@ -76,6 +77,14 @@ struct X86Inst {
kIdBlsic, // [ANY] {TBM}
kIdBlsmsk, // [ANY] {BMI}
kIdBlsr, // [ANY] {BMI}
kIdBndcl, // [ANY] {MPX}
kIdBndcn, // [ANY] {MPX}
kIdBndcu, // [ANY] {MPX}
kIdBndldx, // [ANY] {MPX}
kIdBndmk, // [ANY] {MPX}
kIdBndmov, // [ANY] {MPX}
kIdBndstx, // [ANY] {MPX}
kIdBound, // [X86]
kIdBsf, // [ANY]
kIdBsr, // [ANY]
kIdBswap, // [ANY]
@@ -93,6 +102,8 @@ struct X86Inst {
kIdCld, // [ANY]
kIdClflush, // [ANY] {CLFLUSH}
kIdClflushopt, // [ANY] {CLFLUSH_OPT}
kIdCli, // [ANY]
kIdClts, // [ANY]
kIdClwb, // [ANY] {CLWB}
kIdClzero, // [ANY] {CLZERO}
kIdCmc, // [ANY]
@@ -278,6 +289,7 @@ struct X86Inst {
kIdFyl2xp1, // [ANY]
kIdHaddpd, // [ANY] {SSE3}
kIdHaddps, // [ANY] {SSE3}
kIdHlt, // [ANY]
kIdHsubpd, // [ANY] {SSE3}
kIdHsubps, // [ANY] {SSE3}
kIdIdiv, // [ANY]
@@ -290,6 +302,9 @@ struct X86Inst {
kIdInt, // [ANY]
kIdInt3, // [ANY]
kIdInto, // [ANY]
kIdInvd, // [ANY] {I486}
kIdInvlpg, // [ANY] {I486}
kIdInvpcid, // [ANY] {I486}
kIdJa, // [ANY]
kIdJae, // [ANY]
kIdJb, // [ANY]
@@ -374,15 +389,22 @@ struct X86Inst {
kIdKxorq, // [ANY] {AVX512_BW}
kIdKxorw, // [ANY] {AVX512_F}
kIdLahf, // [ANY] {LAHFSAHF}
kIdLar, // [ANY]
kIdLddqu, // [ANY] {SSE3}
kIdLdmxcsr, // [ANY] {SSE}
kIdLea, // [ANY]
kIdLeave, // [ANY]
kIdLfence, // [ANY] {SSE2}
kIdLgdt, // [ANY]
kIdLidt, // [ANY]
kIdLldt, // [ANY]
kIdLmsw, // [ANY]
kIdLods, // [ANY]
kIdLoop, // [ANY]
kIdLoope, // [ANY]
kIdLoopne, // [ANY]
kIdLsl, // [ANY]
kIdLtr, // [ANY]
kIdLzcnt, // [ANY] {LZCNT}
kIdMaskmovdqu, // [ANY] {SSE2}
kIdMaskmovq, // [ANY] {MMX2}
@@ -395,7 +417,7 @@ struct X86Inst {
kIdMinps, // [ANY] {SSE}
kIdMinsd, // [ANY] {SSE2}
kIdMinss, // [ANY] {SSE}
kIdMonitor,
kIdMonitor, // [ANY] {MONITOR}
kIdMov, // [ANY]
kIdMovapd, // [ANY] {SSE2}
kIdMovaps, // [ANY] {SSE}
@@ -440,7 +462,7 @@ struct X86Inst {
kIdMulsd, // [ANY] {SSE2}
kIdMulss, // [ANY] {SSE}
kIdMulx, // [ANY] {BMI2}
kIdMwait,
kIdMwait, // [ANY] {MONITOR}
kIdNeg, // [ANY]
kIdNop, // [ANY]
kIdNot, // [ANY]
@@ -627,6 +649,8 @@ struct X86Inst {
kIdRcr, // [ANY]
kIdRdfsbase, // [X64] {FSGSBASE}
kIdRdgsbase, // [X64] {FSGSBASE}
kIdRdmsr, // [ANY] {MSR}
kIdRdpmc, // [ANY]
kIdRdrand, // [ANY] {RDRAND}
kIdRdseed, // [ANY] {RDSEED}
kIdRdtsc, // [ANY] {RDTSC}
@@ -678,6 +702,7 @@ struct X86Inst {
kIdSets, // [ANY]
kIdSetz, // [ANY]
kIdSfence, // [ANY] {MMX2}
kIdSgdt, // [ANY]
kIdSha1msg1, // [ANY] {SHA}
kIdSha1msg2, // [ANY] {SHA}
kIdSha1nexte, // [ANY] {SHA}
@@ -693,6 +718,9 @@ struct X86Inst {
kIdShrx, // [ANY] {BMI2}
kIdShufpd, // [ANY] {SSE2}
kIdShufps, // [ANY] {SSE}
kIdSidt, // [ANY]
kIdSldt, // [ANY]
kIdSmsw, // [ANY]
kIdSqrtpd, // [ANY] {SSE2}
kIdSqrtps, // [ANY] {SSE}
kIdSqrtsd, // [ANY] {SSE2}
@@ -703,12 +731,19 @@ struct X86Inst {
kIdSti, // [ANY]
kIdStmxcsr, // [ANY] {SSE}
kIdStos, // [ANY]
kIdStr, // [ANY]
kIdSub, // [ANY]
kIdSubpd, // [ANY] {SSE2}
kIdSubps, // [ANY] {SSE}
kIdSubsd, // [ANY] {SSE2}
kIdSubss, // [ANY] {SSE}
kIdSwapgs, // [X64]
kIdSyscall, // [X64]
kIdSysenter, // [ANY]
kIdSysexit, // [ANY]
kIdSysexit64, // [ANY]
kIdSysret, // [X64]
kIdSysret64, // [X64]
kIdT1mskc, // [ANY] {TBM}
kIdTest, // [ANY]
kIdTzcnt, // [ANY] {BMI}
@@ -720,6 +755,8 @@ struct X86Inst {
kIdUnpckhps, // [ANY] {SSE}
kIdUnpcklpd, // [ANY] {SSE2}
kIdUnpcklps, // [ANY] {SSE}
kIdV4fmaddps, // [ANY] {AVX512_4FMAPS}
kIdV4fnmaddps, // [ANY] {AVX512_4FMAPS}
kIdVaddpd, // [ANY] {AVX|AVX512_F (VL)}
kIdVaddps, // [ANY] {AVX|AVX512_F (VL)}
kIdVaddsd, // [ANY] {AVX|AVX512_F}
@@ -819,6 +856,8 @@ struct X86Inst {
kIdVdivss, // [ANY] {AVX|AVX512_F}
kIdVdppd, // [ANY] {AVX}
kIdVdpps, // [ANY] {AVX}
kIdVerr, // [ANY]
kIdVerw, // [ANY]
kIdVexp2pd, // [ANY] {AVX512_ERI}
kIdVexp2ps, // [ANY] {AVX512_ERI}
kIdVexpandpd, // [ANY] {AVX512_F (VL)}
@@ -1012,6 +1051,8 @@ struct X86Inst {
kIdVmulss, // [ANY] {AVX|AVX512_F}
kIdVorpd, // [ANY] {AVX|AVX512_DQ (VL)}
kIdVorps, // [ANY] {AVX|AVX512_F (VL)}
kIdVp4dpwssd, // [ANY] {AVX512_4VNNIW}
kIdVp4dpwssds, // [ANY] {AVX512_4VNNIW}
kIdVpabsb, // [ANY] {AVX|AVX2|AVX512_BW (VL)}
kIdVpabsd, // [ANY] {AVX|AVX2|AVX512_F (VL)}
kIdVpabsq, // [ANY] {AVX512_F (VL)}
@@ -1224,6 +1265,8 @@ struct X86Inst {
kIdVpmullw, // [ANY] {AVX|AVX2|AVX512_BW (VL)}
kIdVpmultishiftqb, // [ANY] {AVX512_VBMI (VL)}
kIdVpmuludq, // [ANY] {AVX|AVX2|AVX512_F (VL)}
kIdVpopcntd, // [ANY] {AVX512_VPOPCNTDQ}
kIdVpopcntq, // [ANY] {AVX512_VPOPCNTDQ}
kIdVpor, // [ANY] {AVX|AVX2}
kIdVpord, // [ANY] {AVX512_F (VL)}
kIdVporq, // [ANY] {AVX512_F (VL)}
@@ -1389,8 +1432,10 @@ struct X86Inst {
kIdVxorps, // [ANY] {AVX|AVX512_DQ (VL)}
kIdVzeroall, // [ANY] {AVX}
kIdVzeroupper, // [ANY] {AVX}
kIdWbinvd, // [ANY]
kIdWrfsbase, // [X64] {FSGSBASE}
kIdWrgsbase, // [X64] {FSGSBASE}
kIdWrmsr, // [ANY] {MSR}
kIdXadd, // [ANY] {I486}
kIdXchg, // [ANY]
kIdXgetbv, // [ANY] {XSAVE}
@@ -1428,6 +1473,9 @@ struct X86Inst {
kEncodingX86M_GPB_MulDiv, //!< X86 [M] (like GPB, handles implicit|explicit MUL|DIV|IDIV).
kEncodingX86M_Only, //!< X86 [M] (restricted to memory operand of any size).
kEncodingX86Rm, //!< X86 [RM] (doesn't handle single-byte size).
kEncodingX86Rm_NoRexW, //!< X86 [RM] (doesn't add REX.W prefix if 64-bit reg is used).
kEncodingX86Mr, //!< X86 [MR] (doesn't handle single-byte size).
kEncodingX86Mr_NoSize, //!< X86 [MR] (doesn't handle any size).
kEncodingX86Arith, //!< X86 adc, add, and, cmp, or, sbb, sub, xor.
kEncodingX86Bswap, //!< X86 bswap.
kEncodingX86Bt, //!< X86 bt, btc, btr, bts.
@@ -1461,6 +1509,7 @@ struct X86Inst {
kEncodingX86Xadd, //!< X86 xadd.
kEncodingX86Xchg, //!< X86 xchg.
kEncodingX86Fence, //!< X86 lfence, mfence, sfence.
kEncodingX86Bndmov, //!< X86 [RM|MR] (used by BNDMOV).
kEncodingFpuOp, //!< FPU [OP].
kEncodingFpuArith, //!< FPU fadd, fdiv, fdivr, fmul, fsub, fsubr.
kEncodingFpuCom, //!< FPU fcom, fcomp.
@@ -1500,6 +1549,7 @@ struct X86Inst {
kEncodingVexRm_ZDI, //!< VEX|EVEX [RM<ZDI>].
kEncodingVexRm_Lx, //!< VEX|EVEX [RM] (propagates VEX|EVEX.L if YMM used).
kEncodingVexRm_VM, //!< VEX|EVEX [RM] (propagates VEX|EVEX.L, VSIB support).
kEncodingVexRm_T1_4X, //!< EVEX [RM] (used by NN instructions that use RM-T1_4X encoding).
kEncodingVexRmi, //!< VEX|EVEX [RMI].
kEncodingVexRmi_Wx, //!< VEX|EVEX [RMI] (propagates VEX|EVEX.W if GPQ used).
kEncodingVexRmi_Lx, //!< VEX|EVEX [RMI] (propagates VEX|EVEX.L if YMM used).
@@ -1769,6 +1819,7 @@ struct X86Inst {
kOpCode_CDTT_FVM = kOpCode_CDTT_ByLL,
kOpCode_CDTT_T1S = kOpCode_CDTT_None,
kOpCode_CDTT_T1F = kOpCode_CDTT_None,
kOpCode_CDTT_T1_4X = kOpCode_CDTT_None,
kOpCode_CDTT_T2 = kOpCode_CDTT_None,
kOpCode_CDTT_T4 = kOpCode_CDTT_None,
kOpCode_CDTT_T8 = kOpCode_CDTT_None,
@@ -1970,6 +2021,29 @@ struct X86Inst {
kMemOpAny = 0x8000U //!< Operand can be any scalar memory pointer.
};
//! Instruction signature.
//!
//! Contains a sequence of operands' combinations and other metadata that defines
//! a single instruction. This data is used by instruction validator.
struct ISignature {
uint8_t opCount : 3; //!< Count of operands in `opIndex` (0..6).
uint8_t archMask : 2; //!< Architecture mask of this record.
uint8_t implicit : 3; //!< Number of implicit operands.
uint8_t reserved; //!< Reserved for future use.
uint8_t operands[6]; //!< Indexes to `OSignature` table.
};
//! Operand signature, used by \ref ISignature.
//!
//! Contains all possible operand combinations, memory size information,
//! and register index (or \ref Globals::kInvalidRegId if not mandatory).
struct OSignature {
uint32_t flags; //!< Operand flags.
uint16_t memFlags; //!< Memory flags.
uint8_t extFlags; //!< Extra flags.
uint8_t regMask; //!< Mask of possible register IDs.
};
//! Common data - aggregated data that is shared across many instructions.
struct CommonData {
//! Get all instruction flags, see \ref InstFlags.
@@ -2033,6 +2107,12 @@ struct X86Inst {
//! Get alternative opcode, see \ref OpCodeBits.
ASMJIT_INLINE uint32_t getAltOpCode() const noexcept;
ASMJIT_INLINE uint32_t getISignatureIndex() const noexcept { return _iSignatureIndex; }
ASMJIT_INLINE uint32_t getISignatureCount() const noexcept { return _iSignatureCount; }
ASMJIT_INLINE const ISignature* getISignatureData() const noexcept;
ASMJIT_INLINE const ISignature* getISignatureEnd() const noexcept;
ASMJIT_INLINE uint32_t getJumpType() const noexcept { return _jumpType; }
ASMJIT_INLINE uint32_t getSingleRegCase() const noexcept { return _singleRegCase; }
@@ -2109,7 +2189,10 @@ struct X86Inst {
kFeatureAVX512_DQ = 0x00020000U, //!< Supported by AVX512-DQ (dword/qword).
kFeatureAVX512_BW = 0x00040000U, //!< Supported by AVX512-BW (byte/word).
kFeatureAVX512_IFMA = 0x00080000U, //!< Supported by AVX512-IFMA (integer fused-multiply-add).
kFeatureAVX512_VBMI = 0x00100000U //!< Supported by AVX512-VBMI (vector byte manipulation).
kFeatureAVX512_VBMI = 0x00100000U, //!< Supported by AVX512-VBMI (vector byte manipulation).
kFeatureAVX512_4FMAPS = 0x00200000U, //!< Supported by AVX512-4FMAPS (NN floating-point single precision).
kFeatureAVX512_4VNNIW = 0x00400000U, //!< Supported by AVX512-4VNNIW (NN enhanced word variable precision).
kFeatureAVX512_VPOPCNTDQ= 0x00800000U //!< Supported by AVX512-VPOPCNTDQ (vector population count).
};
//!< Additional flags (AVX512).
@@ -2138,29 +2221,6 @@ struct X86Inst {
uint32_t flags; //!< Flags (AVX-512).
};
//! Instruction signature.
//!
//! Contains a sequence of operands' combinations and other metadata that defines
//! a single instruction. This data is used by instruction validator.
struct ISignature {
uint8_t opCount : 3; //!< Count of operands in `opIndex` (0..6).
uint8_t archMask : 2; //!< Architecture mask of this record.
uint8_t implicit : 3; //!< Number of implicit operands.
uint8_t reserved; //!< Reserved for future use.
uint8_t operands[6]; //!< Indexes to `OSignature` table.
};
//! Operand signature, used by \ref ISignature.
//!
//! Contains all possible operand combinations, memory size information,
//! and register index (or \ref Globals::kInvalidRegId if not mandatory).
struct OSignature {
uint32_t flags; //!< Operand flags.
uint16_t memFlags; //!< Memory flags.
uint8_t extFlags; //!< Extra flags.
uint8_t regMask; //!< Mask of possible register IDs.
};
//! Data that is not related to a specific X86 instruction (not referenced by
//! any tables).
struct MiscData {
@@ -2230,6 +2290,12 @@ struct X86Inst {
//! Get instruction flags, see \ref InstFlags.
ASMJIT_INLINE uint32_t getFlags() const noexcept { return getCommonData().getFlags(); }
ASMJIT_INLINE uint32_t getISignatureIndex() const noexcept { return getCommonData().getISignatureIndex(); }
ASMJIT_INLINE uint32_t getISignatureCount() const noexcept { return getCommonData().getISignatureCount(); }
ASMJIT_INLINE const ISignature* getISignatureData() const noexcept { return getCommonData().getISignatureData(); }
ASMJIT_INLINE const ISignature* getISignatureEnd() const noexcept { return getCommonData().getISignatureEnd(); }
// --------------------------------------------------------------------------
// [Get]
// --------------------------------------------------------------------------
@@ -2338,6 +2404,11 @@ struct X86InstDB {
ASMJIT_API static const uint32_t altOpCodeData[];
ASMJIT_API static const char nameData[];
ASMJIT_API static const X86Inst::MiscData miscData;
#if !defined(ASMJIT_DISABLE_VALIDATION)
ASMJIT_API static const X86Inst::ISignature iSignatureData[];
ASMJIT_API static const X86Inst::OSignature oSignatureData[];
#endif // ASMJIT_DISABLE_VALIDATION
};
ASMJIT_INLINE const X86Inst& X86Inst::getInst(uint32_t instId) noexcept {
@@ -2371,6 +2442,22 @@ ASMJIT_INLINE const X86Inst::MiscData& X86Inst::getMiscData() noexcept {
return X86InstDB::miscData;
}
#if !defined(ASMJIT_DISABLE_VALIDATION)
ASMJIT_INLINE const X86Inst::ISignature* X86Inst::CommonData::getISignatureData() const noexcept {
return X86InstDB::iSignatureData + _iSignatureIndex;
}
ASMJIT_INLINE const X86Inst::ISignature* X86Inst::CommonData::getISignatureEnd() const noexcept {
return X86InstDB::iSignatureData + _iSignatureIndex + _iSignatureCount;
}
#else
ASMJIT_INLINE const X86Inst::ISignature* X86Inst::CommonData::getISignatureData() const noexcept {
return static_cast<const X86Inst::ISignature*>(nullptr);
}
ASMJIT_INLINE const X86Inst::ISignature* X86Inst::CommonData::getISignatureEnd() const noexcept {
return static_cast<const X86Inst::ISignature*>(nullptr);
}
#endif // ASMJIT_DISABLE_VALIDATION
//! \}
} // asmjit namespace

112
src/asmjit/x86/x86operand.h
View File

@@ -811,22 +811,22 @@ ASMJIT_X86_PHYS_REG(X86Xmm , xmm12, xmm[12]); //!< 128-bit XMM register (X64).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm13, xmm[13]); //!< 128-bit XMM register (X64).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm14, xmm[14]); //!< 128-bit XMM register (X64).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm15, xmm[15]); //!< 128-bit XMM register (X64).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm16, xmm[16]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm17, xmm[17]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm18, xmm[18]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm19, xmm[19]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm20, xmm[20]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm21, xmm[21]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm22, xmm[22]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm23, xmm[23]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm24, xmm[24]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm25, xmm[25]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm26, xmm[26]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm27, xmm[27]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm28, xmm[28]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm29, xmm[29]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm30, xmm[30]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm31, xmm[31]); //!< 128-bit XMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm16, xmm[16]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm17, xmm[17]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm18, xmm[18]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm19, xmm[19]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm20, xmm[20]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm21, xmm[21]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm22, xmm[22]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm23, xmm[23]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm24, xmm[24]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm25, xmm[25]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm26, xmm[26]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm27, xmm[27]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm28, xmm[28]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm29, xmm[29]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm30, xmm[30]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Xmm , xmm31, xmm[31]); //!< 128-bit XMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm0 , ymm[0]); //!< 256-bit YMM register.
ASMJIT_X86_PHYS_REG(X86Ymm , ymm1 , ymm[1]); //!< 256-bit YMM register.
@@ -844,22 +844,22 @@ ASMJIT_X86_PHYS_REG(X86Ymm , ymm12, ymm[12]); //!< 256-bit YMM register (X64).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm13, ymm[13]); //!< 256-bit YMM register (X64).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm14, ymm[14]); //!< 256-bit YMM register (X64).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm15, ymm[15]); //!< 256-bit YMM register (X64).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm16, ymm[16]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm17, ymm[17]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm18, ymm[18]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm19, ymm[19]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm20, ymm[20]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm21, ymm[21]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm22, ymm[22]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm23, ymm[23]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm24, ymm[24]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm25, ymm[25]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm26, ymm[26]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm27, ymm[27]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm28, ymm[28]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm29, ymm[29]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm30, ymm[30]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm31, ymm[31]); //!< 256-bit YMM register (X64 & AVX512VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm16, ymm[16]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm17, ymm[17]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm18, ymm[18]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm19, ymm[19]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm20, ymm[20]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm21, ymm[21]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm22, ymm[22]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm23, ymm[23]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm24, ymm[24]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm25, ymm[25]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm26, ymm[26]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm27, ymm[27]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm28, ymm[28]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm29, ymm[29]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm30, ymm[30]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Ymm , ymm31, ymm[31]); //!< 256-bit YMM register (X64 & AVX512_VL+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm0 , zmm[0]); //!< 512-bit ZMM register.
ASMJIT_X86_PHYS_REG(X86Zmm , zmm1 , zmm[1]); //!< 512-bit ZMM register.
@@ -877,22 +877,22 @@ ASMJIT_X86_PHYS_REG(X86Zmm , zmm12, zmm[12]); //!< 512-bit ZMM register (X64).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm13, zmm[13]); //!< 512-bit ZMM register (X64).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm14, zmm[14]); //!< 512-bit ZMM register (X64).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm15, zmm[15]); //!< 512-bit ZMM register (X64).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm16, zmm[16]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm17, zmm[17]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm18, zmm[18]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm19, zmm[19]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm20, zmm[20]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm21, zmm[21]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm22, zmm[22]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm23, zmm[23]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm24, zmm[24]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm25, zmm[25]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm26, zmm[26]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm27, zmm[27]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm28, zmm[28]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm29, zmm[29]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm30, zmm[30]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm31, zmm[31]); //!< 512-bit ZMM register (X64 & AVX512F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm16, zmm[16]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm17, zmm[17]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm18, zmm[18]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm19, zmm[19]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm20, zmm[20]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm21, zmm[21]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm22, zmm[22]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm23, zmm[23]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm24, zmm[24]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm25, zmm[25]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm26, zmm[26]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm27, zmm[27]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm28, zmm[28]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm29, zmm[29]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm30, zmm[30]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Zmm , zmm31, zmm[31]); //!< 512-bit ZMM register (X64 & AVX512_F+).
ASMJIT_X86_PHYS_REG(X86Bnd , bnd0 , bnd[0]); //!< 128-bit bound register.
ASMJIT_X86_PHYS_REG(X86Bnd , bnd1 , bnd[1]); //!< 128-bit bound register.
@@ -1068,14 +1068,14 @@ static ASMJIT_INLINE X86Mem ptr(uint64_t base, const X86Vec& index, uint32_t shi
}
// Define memory operand constructors that use platform independent naming.
ASMJIT_X86_PTR_FN(ptr8, 1)
ASMJIT_X86_PTR_FN(ptr16, 2)
ASMJIT_X86_PTR_FN(ptr32, 4)
ASMJIT_X86_PTR_FN(ptr64, 8)
ASMJIT_X86_PTR_FN(ptr80, 10)
ASMJIT_X86_PTR_FN(ptr128, 16)
ASMJIT_X86_PTR_FN(ptr256, 32)
ASMJIT_X86_PTR_FN(ptr512, 64)
ASMJIT_X86_PTR_FN(ptr_8, 1)
ASMJIT_X86_PTR_FN(ptr_16, 2)
ASMJIT_X86_PTR_FN(ptr_32, 4)
ASMJIT_X86_PTR_FN(ptr_64, 8)
ASMJIT_X86_PTR_FN(ptr_80, 10)
ASMJIT_X86_PTR_FN(ptr_128, 16)
ASMJIT_X86_PTR_FN(ptr_256, 32)
ASMJIT_X86_PTR_FN(ptr_512, 64)
// Define memory operand constructors that use X86/X64 specific naming.
ASMJIT_X86_PTR_FN(byte_ptr, 1)

4
test/asmjit_test_opcode.h
View File

@@ -5356,6 +5356,10 @@ static void generateOpcodes(asmjit::X86Assembler& a, bool useRex1 = false, bool
a.vpmuludq(ymmA, ymmB, anyptr_gpC);
a.vpmuludq(zmmA, zmmB, zmmC);
a.vpmuludq(zmmA, zmmB, anyptr_gpC);
a.vpopcntd(zmmA, zmmB);
a.vpopcntd(zmmA, anyptr_gpB);
a.vpopcntq(zmmA, zmmB);
a.vpopcntq(zmmA, anyptr_gpB);
a.vpord(xmmA, xmmB, xmmC);
a.vpord(xmmA, xmmB, anyptr_gpC);
a.vpord(ymmA, ymmB, ymmC);

135
tools/generate-x86.js
View File

@@ -1243,24 +1243,24 @@ class X86Generator extends base.BaseGenerator {
}
}
var s = "#define ISIGNATURE(count, x86, x64, implicit, o0, o1, o2, o3, o4, o5) \\\n" +
var s = "#define FLAG(flag) X86Inst::kOp##flag\n" +
"#define MEM(mem) X86Inst::kMemOp##mem\n" +
"#define OSIGNATURE(flags, memFlags, extFlags, regId) \\\n" +
" { uint32_t(flags), uint16_t(memFlags), uint8_t(extFlags), uint8_t(regId) }\n" +
StringUtils.makeCxxArray(opArr, "const X86Inst::OSignature X86InstDB::oSignatureData[]") +
"#undef OSIGNATURE\n" +
"#undef MEM\n" +
"#undef FLAG\n" +
"\n" +
"#define ISIGNATURE(count, x86, x64, implicit, o0, o1, o2, o3, o4, o5) \\\n" +
" { count, (x86 ? uint8_t(X86Inst::kArchMaskX86) : uint8_t(0)) | \\\n" +
" (x64 ? uint8_t(X86Inst::kArchMaskX64) : uint8_t(0)) , \\\n" +
" implicit, \\\n" +
" 0, \\\n" +
" { o0, o1, o2, o3, o4, o5 } \\\n" +
" }\n" +
StringUtils.makeCxxArrayWithComment(signatureArr, "static const X86Inst::ISignature _x86InstISignatureData[]") +
"#undef ISIGNATURE\n" +
"\n" +
"#define FLAG(flag) X86Inst::kOp##flag\n" +
"#define MEM(mem) X86Inst::kMemOp##mem\n" +
"#define OSIGNATURE(flags, memFlags, extFlags, regId) \\\n" +
" { uint32_t(flags), uint16_t(memFlags), uint8_t(extFlags), uint8_t(regId) }\n" +
StringUtils.makeCxxArray(opArr, "static const X86Inst::OSignature _x86InstOSignatureData[]") +
"#undef OSIGNATURE\n" +
"#undef MEM\n" +
"#undef FLAG\n";
StringUtils.makeCxxArrayWithComment(signatureArr, "const X86Inst::ISignature X86InstDB::iSignatureData[]") +
"#undef ISIGNATURE\n";
return this.inject("signatureData", StringUtils.disclaimer(s), opArr.length * 8 + signatureArr.length * 8);
}
@@ -1354,19 +1354,40 @@ class X86Generator extends base.BaseGenerator {
printMissing() {
var out = "";
function CPUFlags(insts) {
var flags = {};
for (var i = 0; i < insts.length; i++) {
var inst = insts[i];
for (var k in inst.extensions)
flags[k] = true;
}
return Object.getOwnPropertyNames(flags).join("|");
}
// These are supported as `insb`, `lods`, ...
const ignored = {
"cmpsb": true,
"cmpsw": true,
"cmpsd": true,
"cmpsq": true,
"insb" : true,
"insw" : true,
"insd" : true,
"insq" : true,
"lodsb": true,
"lodsw": true,
"lodsd": true,
"lodsq": true,
"movsb": true,
"movsw": true,
"movsd": true,
"movsq": true,
"outsb": true,
"outsw": true,
"outsd": true,
"scasb": true,
"scasw": true,
"scasd": true,
"scasq": true,
"stosb": true,
"stosw": true,
"stosd": true,
"stosq": true
};
isa.instructionNames.forEach(function(name) {
var insts = isa.query(name);
if (!this.instMap[name]) {
if (!this.instMap[name] && ignored[name] !== true) {
console.log(`MISSING INSTRUCTION '${name}'`);
var inst = this.newInstFromInsts(insts);
if (inst) {
@@ -1389,48 +1410,7 @@ class X86Generator extends base.BaseGenerator {
}, this);
console.log(out);
}
}
// ----------------------------------------------------------------------------
// [Main]
// ----------------------------------------------------------------------------
function main() {
const gen = new X86Generator();
gen.parse();
gen.generate();
// gen.printMissing();
gen.dumpTableSizes();
gen.save();
}
main();
/*
newInstFromInsts(insts) {
function GetAccess(inst) {
var operands = inst.operands;
@@ -1449,9 +1429,9 @@ main();
var id = this.instArray.length;
var name = inst.name;
var enum_ = kX86InstId + name[0].toUpperCase() + name.substr(1);
var enum_ = name[0].toUpperCase() + name.substr(1);
var opcode = inst.opcode;
var opcode = inst.opcodeHex;
var rm = inst.rm;
var mm = inst.mm;
var pp = inst.pp;
@@ -1496,13 +1476,6 @@ main();
if (access !== GetAccess(inst)) return null;
}
var obj = AVX512Flags(insts);
if (obj) {
vexL = obj.vexL;
vexW = obj.vexW;
evexW = obj.evexW;
}
var ppmm = StringUtils.padLeft(pp, 2).replace(/ /g, "0") +
StringUtils.padLeft(mm, 4).replace(/ /g, "0") ;
@@ -1541,7 +1514,7 @@ main();
commonIndex : -1
};
}
/*
function genAPI() {
var asm = fs.readFileSync("../src/asmjit/x86/x86assembler.h", "utf8");
var list = ["AVX512_F", "AVX512_DQ", "AVX512_BW", "AVX512_CD", "AVX512_ER", "AVX512_PF", "AVX512_IFMA", "AVX512_VBMI"];
@@ -1861,3 +1834,19 @@ main();
console.log(out);
}
*/
}
// ----------------------------------------------------------------------------
// [Main]
// ----------------------------------------------------------------------------
function main() {
const gen = new X86Generator();
gen.parse();
gen.generate();
// gen.printMissing();
gen.dumpTableSizes();
gen.save();
}
main();