From 75f2b69a260b5f0021cc9ebefb5cf6f9ad3e55b4 Mon Sep 17 00:00:00 2001 From: kobalicek Date: Sun, 5 Jul 2020 00:45:03 +0200 Subject: [PATCH] Added new instructions and removed deprecated PCOMMIT --- src/asmjit/x86/x86assembler.cpp | 35 +- src/asmjit/x86/x86emitter.h | 77 +- src/asmjit/x86/x86features.cpp | 119 +- src/asmjit/x86/x86features.h | 7 +- src/asmjit/x86/x86formatter.cpp | 19 +- src/asmjit/x86/x86globals.h | 19 +- src/asmjit/x86/x86instdb.cpp | 5593 ++++++++++++++++--------------- src/asmjit/x86/x86instdb_p.h | 4 +- src/asmjit/x86/x86opcode_p.h | 57 +- test/asmjit_test_opcode.h | 4 - tools/tablegen-x86.js | 10 +- 11 files changed, 3055 insertions(+), 2889 deletions(-) diff --git a/src/asmjit/x86/x86assembler.cpp b/src/asmjit/x86/x86assembler.cpp index 2f1dad8..fe2bcb9 100644 --- a/src/asmjit/x86/x86assembler.cpp +++ b/src/asmjit/x86/x86assembler.cpp @@ -662,7 +662,8 @@ ASMJIT_FAVOR_SPEED Error Assembler::_emit(uint32_t instId, const Operand_& o0, c // This sequence seems to be the fastest. opcode = InstDB::_mainOpcodeTable[instInfo->_mainOpcodeIndex]; - opReg = opcode.extractO(); + opReg = opcode.extractModO(); + rbReg = 0; opcode |= instInfo->_mainOpcodeValue; // -------------------------------------------------------------------------- @@ -687,16 +688,17 @@ ASMJIT_FAVOR_SPEED Error Assembler::_emit(uint32_t instId, const Operand_& o0, c case InstDB::kEncodingX86Op: goto EmitX86Op; - case InstDB::kEncodingX86Op_O_I8: + case InstDB::kEncodingX86Op_Mod11RM: + rbReg = opcode.extractModRM(); + goto EmitX86R; + + case InstDB::kEncodingX86Op_Mod11RM_I8: if (ASMJIT_UNLIKELY(isign3 != ENC_OPS1(Imm))) goto InvalidInstruction; + rbReg = opcode.extractModRM(); immValue = o0.as().valueAs(); immSize = 1; - ASMJIT_FALLTHROUGH; - - case InstDB::kEncodingX86Op_O: - rbReg = 0; goto EmitX86R; case InstDB::kEncodingX86Op_xAddr: @@ -1126,7 +1128,7 @@ CaseX86M_GPB_MulDiv: opcode = x86AltOpcodeOf(instInfo); opcode.addPrefixBySize(o0.size()); - opReg = opcode.extractO(); + opReg = opcode.extractModO(); if (isign3 == ENC_OPS2(Reg, Imm)) { rbReg = o0.id(); @@ -2093,7 +2095,7 @@ CaseX86PushPop_Gp: // The following instructions use the secondary opcode. opcode = x86AltOpcodeOf(instInfo); - opReg = opcode.extractO(); + opReg = opcode.extractModO(); if (isign3 == ENC_OPS2(Reg, Imm)) { opcode.addArithBySize(o0.size()); @@ -2294,7 +2296,7 @@ CaseFpuArith_Mem: if (o0.size() == 10 && commonInfo->hasFlag(InstDB::kFlagFpuM80)) { opcode = x86AltOpcodeOf(instInfo); - opReg = opcode.extractO(); + opReg = opcode.extractModO(); goto EmitX86M; } } @@ -2323,7 +2325,7 @@ CaseFpuArith_Mem: if (o0.size() == 8 && commonInfo->hasFlag(InstDB::kFlagFpuM64)) { opcode = x86AltOpcodeOf(instInfo) & ~uint32_t(Opcode::kCDSHL_Mask); - opReg = opcode.extractO(); + opReg = opcode.extractModO(); goto EmitX86M; } } @@ -2642,7 +2644,7 @@ CaseExtRm: // The following instruction uses the secondary opcode. opcode = x86AltOpcodeOf(instInfo); - opReg = opcode.extractO(); + opReg = opcode.extractModO(); if (isign3 == ENC_OPS2(Reg, Imm)) { immValue = o1.as().value(); @@ -2672,7 +2674,7 @@ CaseExtRm: // The following instruction uses the secondary opcode. opcode = x86AltOpcodeOf(instInfo); - opReg = opcode.extractO(); + opReg = opcode.extractModO(); if (isign3 == ENC_OPS2(Reg, Imm)) { opcode.add66hIf(Reg::isXmm(o0)); @@ -2742,7 +2744,7 @@ CaseExtRm: (uint32_t(o2.as().valueAs()) << 8) ; immSize = 2; - rbReg = opcode.extractO(); + rbReg = opcode.extractModO(); goto EmitX86R; } break; @@ -3065,7 +3067,6 @@ CaseVexRvm_R: if (o3.isMem()) { rmRel = &o3; goto EmitVexEvexM; - } } break; @@ -3454,7 +3455,7 @@ CaseVexRvm_R: // The following instruction uses the secondary opcode. opcode &= Opcode::kLL_Mask; opcode |= x86AltOpcodeOf(instInfo); - opReg = opcode.extractO(); + opReg = opcode.extractModO(); immValue = o2.as().value(); immSize = 1; @@ -3804,7 +3805,7 @@ EmitX86R: { uint32_t rex = opcode.extractRex(options) | ((opReg & 0x08) >> 1) | // REX.R (0x04). - ((rbReg ) >> 3) ; // REX.B (0x01). + ((rbReg & 0x08) >> 3) ; // REX.B (0x01). if (ASMJIT_UNLIKELY(x86IsRexInvalid(rex))) goto InvalidRexPrefix; @@ -3820,8 +3821,8 @@ EmitX86R: // Emit ModR. writer.emit8(x86EncodeMod(3, opReg, rbReg)); - // Emit immediate value. + // Emit immediate value. writer.emitImmediate(uint64_t(immValue), immSize); goto EmitDone; diff --git a/src/asmjit/x86/x86emitter.h b/src/asmjit/x86/x86emitter.h index e984244..37abd2c 100644 --- a/src/asmjit/x86/x86emitter.h +++ b/src/asmjit/x86/x86emitter.h @@ -178,9 +178,11 @@ ASMJIT_BEGIN_SUB_NAMESPACE(x86) // [asmjit::x86::EmitterExplicitT] // ============================================================================ +//! Emitter (X86 - explicit). template struct EmitterExplicitT { //! \cond + // These typedefs are used to describe implicit operands passed explicitly. typedef Gp AL; typedef Gp AH; @@ -721,6 +723,10 @@ public: ASMJIT_INST_2i(test, Test, Gp, Imm) // ANY ASMJIT_INST_2x(test, Test, Mem, Gp) // ANY ASMJIT_INST_2i(test, Test, Mem, Imm) // ANY + ASMJIT_INST_2x(ud0, Ud0, Reg, Reg) // ANY + ASMJIT_INST_2x(ud0, Ud0, Reg, Mem) // ANY + ASMJIT_INST_2x(ud1, Ud1, Reg, Reg) // ANY + ASMJIT_INST_2x(ud1, Ud1, Reg, Mem) // ANY ASMJIT_INST_0x(ud2, Ud2) // ANY ASMJIT_INST_2x(xadd, Xadd, Gp, Gp) // ANY ASMJIT_INST_2x(xadd, Xadd, Mem, Gp) // ANY @@ -755,9 +761,12 @@ public: //! \} - //! \name In/Out Instructions + //! \name IN/OUT Instructions //! \{ + // NOTE: For some reason Doxygen is messed up here and thinks we are in cond. + //! \endcond + ASMJIT_INST_2i(in, In, ZAX, Imm) // ANY ASMJIT_INST_2x(in, In, ZAX, DX) // ANY ASMJIT_INST_2x(ins, Ins, ES_ZDI, DX) // ANY @@ -767,7 +776,7 @@ public: //! \} - //! \name Clear/Set CL/DF Instructions + //! \name Clear/Set CF/DF Instructions //! \{ ASMJIT_INST_0x(clc, Clc) // ANY @@ -781,8 +790,8 @@ public: //! \name LAHF/SAHF Instructions //! \{ - ASMJIT_INST_1x(lahf, Lahf, AH) // LAHFSAHF [EXPLICIT] AH <- EFL - ASMJIT_INST_1x(sahf, Sahf, AH) // LAHFSAHF [EXPLICIT] EFL <- AH + ASMJIT_INST_1x(lahf, Lahf, AH) // LAHFSAHF [EXPLICIT] AH <- EFL + ASMJIT_INST_1x(sahf, Sahf, AH) // LAHFSAHF [EXPLICIT] EFL <- AH //! \} @@ -956,10 +965,11 @@ public: //! \} - //! \name RDPRU Instruction + //! \name RDPRU/RDPKRU Instructions //! \{ - ASMJIT_INST_3x(rdpru, Rdpru, ECX, EDX, EAX) // RDPRU [EXPLICIT] EDX:EAX <- PRU[ECX] + ASMJIT_INST_3x(rdpru, Rdpru, EDX, EAX, ECX) // RDPRU [EXPLICIT] EDX:EAX <- PRU[ECX] + ASMJIT_INST_3x(rdpkru, Rdpkru, EDX, EAX, ECX) // RDPKRU [EXPLICIT] EDX:EAX <- PKRU[ECX] //! \} @@ -1061,14 +1071,21 @@ public: //! \} - //! \name PCOMMIT/MCOMMIT Instructions + //! \name MCOMMIT Instruction //! \{ - ASMJIT_INST_0x(pcommit, Pcommit) // PCOMMIT ASMJIT_INST_0x(mcommit, Mcommit) // MCOMMIT //! \} + //! \name PTWRITE Instruction + //! \{ + + ASMJIT_INST_1x(ptwrite, Ptwrite, Gp) // PTWRITE + ASMJIT_INST_1x(ptwrite, Ptwrite, Mem) // PTWRITE + + //! \} + //! \name ENQCMD Instructions //! \{ @@ -1126,6 +1143,34 @@ public: //! \} + //! \name CET-IBT Instructions + //! \{ + + ASMJIT_INST_0x(endbr32, Endbr32) + ASMJIT_INST_0x(endbr64, Endbr64) + + //! \} + + //! \name CET-SS Instructions + //! \{ + + ASMJIT_INST_1x(clrssbsy, Clrssbsy, Mem) + ASMJIT_INST_0x(setssbsy, Setssbsy) + + ASMJIT_INST_1x(rstorssp, Rstorssp, Mem) + ASMJIT_INST_0x(saveprevssp, Saveprevssp) + + ASMJIT_INST_1x(incsspd, Incsspd, Gp) + ASMJIT_INST_1x(incsspq, Incsspq, Gp) + ASMJIT_INST_1x(rdsspd, Rdsspd, Gp) + ASMJIT_INST_1x(rdsspq, Rdsspq, Gp) + ASMJIT_INST_2x(wrssd, Wrssd, Mem, Gp) + ASMJIT_INST_2x(wrssq, Wrssq, Mem, Gp) + ASMJIT_INST_2x(wrussd, Wrussd, Mem, Gp) + ASMJIT_INST_2x(wrussq, Wrussq, Mem, Gp) + + //! \} + //! \name Core Privileged Instructions //! \{ @@ -1216,13 +1261,6 @@ public: //! \} - //! \name SYSCALL & SYSENTER Instructions - //! \{ - - //! \} - - - //! \name FPU Instructions //! \{ @@ -2127,6 +2165,9 @@ public: //! \name GFNI Instructions //! \{ + // NOTE: For some reason Doxygen is messed up here and thinks we are in cond. + //! \endcond + ASMJIT_INST_3i(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Xmm, Imm) // GFNI ASMJIT_INST_3i(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Mem, Imm) // GFNI ASMJIT_INST_3i(gf2p8affineqb, Gf2p8affineqb, Xmm, Xmm, Imm) // GFNI @@ -3707,6 +3748,7 @@ public: // [asmjit::x86::EmitterImplicitT] // ============================================================================ +//! Emitter (X86 - implicit). template struct EmitterImplicitT : public EmitterExplicitT { //! \cond @@ -3863,6 +3905,7 @@ struct EmitterImplicitT : public EmitterExplicitT { //! \} //! \name CPUID Instruction + //! \{ //! \cond using EmitterExplicitT::cpuid; @@ -3883,14 +3926,16 @@ struct EmitterImplicitT : public EmitterExplicitT { //! \} - //! \name RDPRU Instruction + //! \name RDPRU/RDPKRU Instructions //! \{ //! \cond using EmitterExplicitT::rdpru; + using EmitterExplicitT::rdpkru; //! \endcond ASMJIT_INST_0x(rdpru, Rdpru) // RDPRU [IMPLICIT] EDX:EAX <- PRU[ECX] + ASMJIT_INST_0x(rdpkru, Rdpkru) // RDPKRU [IMPLICIT] EDX:EAX <- PKRU[ECX] //! \} diff --git a/src/asmjit/x86/x86features.cpp b/src/asmjit/x86/x86features.cpp index 99f2444..5f851f3 100644 --- a/src/asmjit/x86/x86features.cpp +++ b/src/asmjit/x86/x86features.cpp @@ -146,17 +146,19 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept { features.add(Features::kI486); // -------------------------------------------------------------------------- - // [CPUID EAX=0x0] + // [CPUID EAX=0] // -------------------------------------------------------------------------- // Get vendor string/id. cpuidQuery(®s, 0x0); uint32_t maxId = regs.eax; + uint32_t maxSubLeafId_0x7 = 0; + simplifyCpuVendor(cpu, regs.ebx, regs.edx, regs.ecx); // -------------------------------------------------------------------------- - // [CPUID EAX=0x1] + // [CPUID EAX=1] // -------------------------------------------------------------------------- if (maxId >= 0x1) { @@ -205,12 +207,12 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept { if (bitTest(regs.edx, 19)) features.add(Features::kCLFLUSH); if (bitTest(regs.edx, 23)) features.add(Features::kMMX); if (bitTest(regs.edx, 24)) features.add(Features::kFXSR); - if (bitTest(regs.edx, 25)) features.add(Features::kSSE, Features::kMMX2); + if (bitTest(regs.edx, 25)) features.add(Features::kSSE); if (bitTest(regs.edx, 26)) features.add(Features::kSSE, Features::kSSE2); if (bitTest(regs.edx, 28)) features.add(Features::kMT); - // Get the content of XCR0 if supported by CPU and enabled by OS. - if ((regs.ecx & 0x0C000000u) == 0x0C000000u) { + // Get the content of XCR0 if supported by the CPU and enabled by the OS. + if (features.hasXSAVE() && features.hasOSXSAVE()) { xgetbvQuery(&xcr0, 0); } @@ -227,8 +229,23 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept { } } + constexpr uint32_t kXCR0_AMX_Bits = 0x3u << 17; + bool amxEnabledByOS = (xcr0.eax & kXCR0_AMX_Bits) == kXCR0_AMX_Bits; + +#if defined(__APPLE__) + // Apple platform provides on-demand AVX512 support. When an AVX512 instruction is used + // the first time it results in #UD, which would cause the thread being promoted to use + // AVX512 support by the OS in addition to enabling the necessary bits in XCR0 register. + bool avx512EnabledByOS = true; +#else + // - XCR0[2:1] == 11b - XMM/YMM states need to be enabled by OS. + // - XCR0[7:5] == 111b - Upper 256-bit of ZMM0-XMM15 and ZMM16-ZMM31 need to be enabled by OS. + constexpr uint32_t kXCR0_AVX512_Bits = (0x3u << 1) | (0x7u << 5); + bool avx512EnabledByOS = (xcr0.eax & kXCR0_AVX512_Bits) == kXCR0_AVX512_Bits; +#endif + // -------------------------------------------------------------------------- - // [CPUID EAX=0x7] + // [CPUID EAX=7 ECX=0] // -------------------------------------------------------------------------- // Detect new features if the processor supports CPUID-07. @@ -236,7 +253,9 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept { if (maxId >= 0x7) { cpuidQuery(®s, 0x7); - uint32_t maxSubLeafId = regs.eax; + + maybeMPX = bitTest(regs.ebx, 14); + maxSubLeafId_0x7 = regs.eax; if (bitTest(regs.ebx, 0)) features.add(Features::kFSGSBASE); if (bitTest(regs.ebx, 3)) features.add(Features::kBMI); @@ -245,15 +264,18 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept { if (bitTest(regs.ebx, 8)) features.add(Features::kBMI2); if (bitTest(regs.ebx, 9)) features.add(Features::kERMS); if (bitTest(regs.ebx, 11)) features.add(Features::kRTM); - if (bitTest(regs.ebx, 14)) maybeMPX = true; if (bitTest(regs.ebx, 18)) features.add(Features::kRDSEED); if (bitTest(regs.ebx, 19)) features.add(Features::kADX); if (bitTest(regs.ebx, 20)) features.add(Features::kSMAP); - if (bitTest(regs.ebx, 22)) features.add(Features::kPCOMMIT); if (bitTest(regs.ebx, 23)) features.add(Features::kCLFLUSHOPT); if (bitTest(regs.ebx, 24)) features.add(Features::kCLWB); if (bitTest(regs.ebx, 29)) features.add(Features::kSHA); if (bitTest(regs.ecx, 0)) features.add(Features::kPREFETCHWT1); + if (bitTest(regs.ecx, 4)) features.add(Features::kOSPKE); + if (bitTest(regs.ecx, 5)) features.add(Features::kWAITPKG); + if (bitTest(regs.ecx, 8)) features.add(Features::kGFNI); + if (bitTest(regs.ecx, 9)) features.add(Features::kVAES); + if (bitTest(regs.ecx, 10)) features.add(Features::kVPCLMULQDQ); if (bitTest(regs.ecx, 22)) features.add(Features::kRDPID); if (bitTest(regs.ecx, 25)) features.add(Features::kCLDEMOTE); if (bitTest(regs.ecx, 27)) features.add(Features::kMOVDIRI); @@ -262,9 +284,6 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept { if (bitTest(regs.edx, 14)) features.add(Features::kSERIALIZE); if (bitTest(regs.edx, 16)) features.add(Features::kTSXLDTRK); if (bitTest(regs.edx, 18)) features.add(Features::kPCONFIG); - if (bitTest(regs.edx, 22)) features.add(Features::kAMX_BF16); - if (bitTest(regs.edx, 24)) features.add(Features::kAMX_TILE); - if (bitTest(regs.edx, 25)) features.add(Features::kAMX_INT8); // Detect 'TSX' - Requires at least one of `HLE` and `RTM` features. if (features.hasHLE() || features.hasRTM()) @@ -274,44 +293,47 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept { if (bitTest(regs.ebx, 5) && features.hasAVX()) features.add(Features::kAVX2); - // Detect 'AVX_512'. - if (bitTest(regs.ebx, 16)) { - // - XCR0[2:1] == 11b - XMM/YMM states need to be enabled by OS. - // - XCR0[7:5] == 111b - Upper 256-bit of ZMM0-XMM15 and ZMM16-ZMM31 need to be enabled by OS. - if ((xcr0.eax & 0x000000E6u) == 0x000000E6u) { - features.add(Features::kAVX512_F); - - if (bitTest(regs.ebx, 17)) features.add(Features::kAVX512_DQ); - if (bitTest(regs.ebx, 21)) features.add(Features::kAVX512_IFMA); - if (bitTest(regs.ebx, 26)) features.add(Features::kAVX512_PFI); - if (bitTest(regs.ebx, 27)) features.add(Features::kAVX512_ERI); - if (bitTest(regs.ebx, 28)) features.add(Features::kAVX512_CDI); - if (bitTest(regs.ebx, 30)) features.add(Features::kAVX512_BW); - if (bitTest(regs.ebx, 31)) features.add(Features::kAVX512_VL); - if (bitTest(regs.ecx, 1)) features.add(Features::kAVX512_VBMI); - if (bitTest(regs.ecx, 5)) features.add(Features::kWAITPKG); - if (bitTest(regs.ecx, 6)) features.add(Features::kAVX512_VBMI2); - if (bitTest(regs.ecx, 8)) features.add(Features::kGFNI); - if (bitTest(regs.ecx, 9)) features.add(Features::kVAES); - if (bitTest(regs.ecx, 10)) features.add(Features::kVPCLMULQDQ); - if (bitTest(regs.ecx, 11)) features.add(Features::kAVX512_VNNI); - if (bitTest(regs.ecx, 12)) features.add(Features::kAVX512_BITALG); - if (bitTest(regs.ecx, 14)) features.add(Features::kAVX512_VPOPCNTDQ); - if (bitTest(regs.edx, 2)) features.add(Features::kAVX512_4VNNIW); - if (bitTest(regs.edx, 3)) features.add(Features::kAVX512_4FMAPS); - if (bitTest(regs.edx, 8)) features.add(Features::kAVX512_VP2INTERSECT); - } + // Detect 'AMX'. + if (amxEnabledByOS) { + if (bitTest(regs.edx, 22)) features.add(Features::kAMX_BF16); + if (bitTest(regs.edx, 24)) features.add(Features::kAMX_TILE); + if (bitTest(regs.edx, 25)) features.add(Features::kAMX_INT8); } - if (maxSubLeafId >= 1 && features.hasAVX512_F()) { - cpuidQuery(®s, 0x7, 1); + // Detect 'AVX_512'. + if (avx512EnabledByOS && bitTest(regs.ebx, 16)) { + features.add(Features::kAVX512_F); - if (bitTest(regs.eax, 5)) features.add(Features::kAVX512_BF16); + if (bitTest(regs.ebx, 17)) features.add(Features::kAVX512_DQ); + if (bitTest(regs.ebx, 21)) features.add(Features::kAVX512_IFMA); + if (bitTest(regs.ebx, 26)) features.add(Features::kAVX512_PFI); + if (bitTest(regs.ebx, 27)) features.add(Features::kAVX512_ERI); + if (bitTest(regs.ebx, 28)) features.add(Features::kAVX512_CDI); + if (bitTest(regs.ebx, 30)) features.add(Features::kAVX512_BW); + if (bitTest(regs.ebx, 31)) features.add(Features::kAVX512_VL); + if (bitTest(regs.ecx, 1)) features.add(Features::kAVX512_VBMI); + if (bitTest(regs.ecx, 6)) features.add(Features::kAVX512_VBMI2); + if (bitTest(regs.ecx, 11)) features.add(Features::kAVX512_VNNI); + if (bitTest(regs.ecx, 12)) features.add(Features::kAVX512_BITALG); + if (bitTest(regs.ecx, 14)) features.add(Features::kAVX512_VPOPCNTDQ); + if (bitTest(regs.edx, 2)) features.add(Features::kAVX512_4VNNIW); + if (bitTest(regs.edx, 3)) features.add(Features::kAVX512_4FMAPS); + if (bitTest(regs.edx, 8)) features.add(Features::kAVX512_VP2INTERSECT); } } // -------------------------------------------------------------------------- - // [CPUID EAX=0xD] + // [CPUID EAX=7 ECX=1] + // -------------------------------------------------------------------------- + + if (features.hasAVX512_F() && maxSubLeafId_0x7 >= 1) { + cpuidQuery(®s, 0x7, 1); + + if (bitTest(regs.eax, 5)) features.add(Features::kAVX512_BF16); + } + + // -------------------------------------------------------------------------- + // [CPUID EAX=13 ECX=0] // -------------------------------------------------------------------------- if (maxId >= 0xD) { @@ -322,11 +344,22 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept { features.add(Features::kMPX); cpuidQuery(®s, 0xD, 1); + if (bitTest(regs.eax, 0)) features.add(Features::kXSAVEOPT); if (bitTest(regs.eax, 1)) features.add(Features::kXSAVEC); if (bitTest(regs.eax, 3)) features.add(Features::kXSAVES); } + // -------------------------------------------------------------------------- + // [CPUID EAX=14 ECX=0] + // -------------------------------------------------------------------------- + + if (maxId >= 0xE) { + cpuidQuery(®s, 0xE, 0); + + if (bitTest(regs.ebx, 4)) features.add(Features::kPTWRITE); + } + // -------------------------------------------------------------------------- // [CPUID EAX=0x80000000...maxId] // -------------------------------------------------------------------------- diff --git a/src/asmjit/x86/x86features.h b/src/asmjit/x86/x86features.h index e8de8d8..24a73f5 100644 --- a/src/asmjit/x86/x86features.h +++ b/src/asmjit/x86/x86features.h @@ -76,6 +76,8 @@ public: kAVX512_VPOPCNTDQ, //!< CPU has AVX512_VPOPCNTDQ (VPOPCNT[D|Q] instructions). kBMI, //!< CPU has BMI (bit manipulation instructions #1). kBMI2, //!< CPU has BMI2 (bit manipulation instructions #2). + kCET_IBT, //!< CPU has CET-IBT. + kCET_SS, //!< CPU has CET-SS. kCLDEMOTE, //!< CPU has CLDEMOTE (cache line demote). kCLFLUSH, //!< CPU has CLFUSH (Cache Line flush). kCLFLUSHOPT, //!< CPU has CLFUSHOPT (Cache Line flush - optimized). @@ -113,12 +115,13 @@ public: kMSR, //!< CPU has MSR (RDMSR/WRMSR instructions). kMSSE, //!< CPU has MSSE (misaligned SSE support). kOSXSAVE, //!< CPU has OSXSAVE (XSAVE enabled by OS). + kOSPKE, //!< CPU has OSPKE (PKE enabled by OS). kPCLMULQDQ, //!< CPU has PCLMULQDQ (packed carry-less multiplication). - kPCOMMIT, //!< CPU has PCOMMIT (PCOMMIT instruction). kPCONFIG, //!< CPU has PCONFIG (PCONFIG instruction). kPOPCNT, //!< CPU has POPCNT (POPCNT instruction). kPREFETCHW, //!< CPU has PREFETCHW. kPREFETCHWT1, //!< CPU has PREFETCHWT1. + kPTWRITE, //!< CPU has PTWRITE. kRDPID, //!< CPU has RDPID. kRDPRU, //!< CPU has RDPRU. kRDRAND, //!< CPU has RDRAND. @@ -253,11 +256,11 @@ public: ASMJIT_X86_FEATURE(MSSE) ASMJIT_X86_FEATURE(OSXSAVE) ASMJIT_X86_FEATURE(PCLMULQDQ) - ASMJIT_X86_FEATURE(PCOMMIT) ASMJIT_X86_FEATURE(PCONFIG) ASMJIT_X86_FEATURE(POPCNT) ASMJIT_X86_FEATURE(PREFETCHW) ASMJIT_X86_FEATURE(PREFETCHWT1) + ASMJIT_X86_FEATURE(PTWRITE) ASMJIT_X86_FEATURE(RDPID) ASMJIT_X86_FEATURE(RDPRU) ASMJIT_X86_FEATURE(RDRAND) diff --git a/src/asmjit/x86/x86formatter.cpp b/src/asmjit/x86/x86formatter.cpp index a14d341..398a30c 100644 --- a/src/asmjit/x86/x86formatter.cpp +++ b/src/asmjit/x86/x86formatter.cpp @@ -240,6 +240,8 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept "AVX512_VPOPCNTDQ\0" "BMI\0" "BMI2\0" + "CET_IBT\0" + "CET_SS\0" "CLDEMOTE\0" "CLFLUSH\0" "CLFLUSHOPT\0" @@ -277,12 +279,13 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept "MSR\0" "MSSE\0" "OSXSAVE\0" + "OSPKE\0" "PCLMULQDQ\0" - "PCOMMIT\0" "PCONFIG\0" "POPCNT\0" "PREFETCHW\0" "PREFETCHWT1\0" + "PTWRITE\0" "RDPID\0" "RDPRU\0" "RDRAND\0" @@ -322,13 +325,13 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept static const uint16_t sFeatureIndex[] = { 0, 5, 8, 11, 17, 24, 28, 34, 44, 53, 62, 71, 75, 80, 94, 108, 120, 134, 144, - 155, 165, 176, 185, 197, 208, 220, 233, 243, 255, 275, 292, 296, 301, 310, - 318, 329, 334, 341, 346, 357, 367, 373, 380, 385, 390, 394, 399, 403, 412, - 417, 425, 431, 436, 440, 445, 454, 458, 464, 472, 476, 481, 489, 498, 504, - 514, 522, 526, 530, 535, 543, 553, 561, 569, 576, 586, 598, 604, 610, 617, - 624, 630, 637, 641, 651, 655, 662, 667, 672, 676, 680, 684, 689, 694, 701, - 708, 714, 720, 724, 728, 732, 741, 746, 750, 761, 769, 778, 782, 788, 795, - 804, 811 + 155, 165, 176, 185, 197, 208, 220, 233, 243, 255, 275, 292, 296, 301, 309, + 316, 325, 333, 344, 349, 356, 361, 372, 382, 388, 395, 400, 405, 409, 414, + 418, 427, 432, 440, 446, 451, 455, 460, 469, 473, 479, 487, 491, 496, 504, + 513, 519, 529, 537, 541, 545, 550, 558, 564, 574, 582, 589, 599, 611, 619, + 625, 631, 638, 645, 651, 658, 662, 672, 676, 683, 688, 693, 697, 701, 705, + 710, 715, 722, 729, 735, 741, 745, 749, 753, 762, 767, 771, 782, 790, 799, + 803, 809, 816, 825, 832 }; // @EnumStringEnd@ diff --git a/src/asmjit/x86/x86globals.h b/src/asmjit/x86/x86globals.h index 21da129..4e11565 100644 --- a/src/asmjit/x86/x86globals.h +++ b/src/asmjit/x86/x86globals.h @@ -119,6 +119,7 @@ struct Inst : public BaseInst { kIdClflushopt, //!< Instruction 'clflushopt' {CLFLUSHOPT}. kIdClgi, //!< Instruction 'clgi' {SVM}. kIdCli, //!< Instruction 'cli'. + kIdClrssbsy, //!< Instruction 'clrssbsy' {CET_SS}. kIdClts, //!< Instruction 'clts'. kIdClwb, //!< Instruction 'clwb' {CLWB}. kIdClzero, //!< Instruction 'clzero' {CLZERO}. @@ -202,6 +203,8 @@ struct Inst : public BaseInst { kIdDppd, //!< Instruction 'dppd' {SSE4_1}. kIdDpps, //!< Instruction 'dpps' {SSE4_1}. kIdEmms, //!< Instruction 'emms' {MMX}. + kIdEndbr32, //!< Instruction 'endbr32' {CET_IBT}. + kIdEndbr64, //!< Instruction 'endbr64' {CET_IBT}. kIdEnqcmd, //!< Instruction 'enqcmd' {ENQCMD}. kIdEnqcmds, //!< Instruction 'enqcmds' {ENQCMD}. kIdEnter, //!< Instruction 'enter'. @@ -318,6 +321,8 @@ struct Inst : public BaseInst { kIdImul, //!< Instruction 'imul'. kIdIn, //!< Instruction 'in'. kIdInc, //!< Instruction 'inc'. + kIdIncsspd, //!< Instruction 'incsspd' {CET_SS}. + kIdIncsspq, //!< Instruction 'incsspq' {CET_SS} (X64). kIdIns, //!< Instruction 'ins'. kIdInsertps, //!< Instruction 'insertps' {SSE4_1}. kIdInsertq, //!< Instruction 'insertq' {SSE4A}. @@ -551,7 +556,6 @@ struct Inst : public BaseInst { kIdPcmpgtw, //!< Instruction 'pcmpgtw' {MMX|SSE2}. kIdPcmpistri, //!< Instruction 'pcmpistri' {SSE4_2}. kIdPcmpistrm, //!< Instruction 'pcmpistrm' {SSE4_2}. - kIdPcommit, //!< Instruction 'pcommit' {PCOMMIT}. kIdPconfig, //!< Instruction 'pconfig' {PCONFIG}. kIdPdep, //!< Instruction 'pdep' {BMI2}. kIdPext, //!< Instruction 'pext' {BMI2}. @@ -673,6 +677,7 @@ struct Inst : public BaseInst { kIdPsubw, //!< Instruction 'psubw' {MMX|SSE2}. kIdPswapd, //!< Instruction 'pswapd' {3DNOW2}. kIdPtest, //!< Instruction 'ptest' {SSE4_1}. + kIdPtwrite, //!< Instruction 'ptwrite' {PTWRITE}. kIdPunpckhbw, //!< Instruction 'punpckhbw' {MMX|SSE2}. kIdPunpckhdq, //!< Instruction 'punpckhdq' {MMX|SSE2}. kIdPunpckhqdq, //!< Instruction 'punpckhqdq' {SSE2}. @@ -697,10 +702,13 @@ struct Inst : public BaseInst { kIdRdgsbase, //!< Instruction 'rdgsbase' {FSGSBASE} (X64). kIdRdmsr, //!< Instruction 'rdmsr' {MSR}. kIdRdpid, //!< Instruction 'rdpid' {RDPID}. + kIdRdpkru, //!< Instruction 'rdpkru' {OSPKE}. kIdRdpmc, //!< Instruction 'rdpmc'. kIdRdpru, //!< Instruction 'rdpru' {RDPRU}. kIdRdrand, //!< Instruction 'rdrand' {RDRAND}. kIdRdseed, //!< Instruction 'rdseed' {RDSEED}. + kIdRdsspd, //!< Instruction 'rdsspd' {CET_SS}. + kIdRdsspq, //!< Instruction 'rdsspq' {CET_SS} (X64). kIdRdtsc, //!< Instruction 'rdtsc' {RDTSC}. kIdRdtscp, //!< Instruction 'rdtscp' {RDTSCP}. kIdRet, //!< Instruction 'ret'. @@ -716,10 +724,12 @@ struct Inst : public BaseInst { kIdRsm, //!< Instruction 'rsm' (X86). kIdRsqrtps, //!< Instruction 'rsqrtps' {SSE}. kIdRsqrtss, //!< Instruction 'rsqrtss' {SSE}. + kIdRstorssp, //!< Instruction 'rstorssp' {CET_SS}. kIdSahf, //!< Instruction 'sahf' {LAHFSAHF}. kIdSal, //!< Instruction 'sal'. kIdSar, //!< Instruction 'sar'. kIdSarx, //!< Instruction 'sarx' {BMI2}. + kIdSaveprevssp, //!< Instruction 'saveprevssp' {CET_SS}. kIdSbb, //!< Instruction 'sbb'. kIdScas, //!< Instruction 'scas'. kIdSerialize, //!< Instruction 'serialize' {SERIALIZE}. @@ -752,6 +762,7 @@ struct Inst : public BaseInst { kIdSetpe, //!< Instruction 'setpe'. kIdSetpo, //!< Instruction 'setpo'. kIdSets, //!< Instruction 'sets'. + kIdSetssbsy, //!< Instruction 'setssbsy' {CET_SS}. kIdSetz, //!< Instruction 'setz'. kIdSfence, //!< Instruction 'sfence' {MMX2}. kIdSgdt, //!< Instruction 'sgdt'. @@ -817,6 +828,8 @@ struct Inst : public BaseInst { kIdTzmsk, //!< Instruction 'tzmsk' {TBM}. kIdUcomisd, //!< Instruction 'ucomisd' {SSE2}. kIdUcomiss, //!< Instruction 'ucomiss' {SSE}. + kIdUd0, //!< Instruction 'ud0'. + kIdUd1, //!< Instruction 'ud1'. kIdUd2, //!< Instruction 'ud2'. kIdUmonitor, //!< Instruction 'umonitor' {WAITPKG}. kIdUmwait, //!< Instruction 'umwait' {WAITPKG}. @@ -1553,6 +1566,10 @@ struct Inst : public BaseInst { kIdWrfsbase, //!< Instruction 'wrfsbase' {FSGSBASE} (X64). kIdWrgsbase, //!< Instruction 'wrgsbase' {FSGSBASE} (X64). kIdWrmsr, //!< Instruction 'wrmsr' {MSR}. + kIdWrssd, //!< Instruction 'wrssd' {CET_SS}. + kIdWrssq, //!< Instruction 'wrssq' {CET_SS} (X64). + kIdWrussd, //!< Instruction 'wrussd' {CET_SS}. + kIdWrussq, //!< Instruction 'wrussq' {CET_SS} (X64). kIdXabort, //!< Instruction 'xabort' {RTM}. kIdXadd, //!< Instruction 'xadd' {I486}. kIdXbegin, //!< Instruction 'xbegin' {RTM}. diff --git a/src/asmjit/x86/x86instdb.cpp b/src/asmjit/x86/x86instdb.cpp index 4ec5ea2..267bf40 100644 --- a/src/asmjit/x86/x86instdb.cpp +++ b/src/asmjit/x86/x86instdb.cpp @@ -64,17 +64,17 @@ ASMJIT_BEGIN_SUB_NAMESPACE(x86) ((PREFIX) | (OPCODE) | (O) | (L) | (W) | (EvexW) | (N) | (TT) | \ (VEX && ((PREFIX) & Opcode::kMM_Mask) != Opcode::kMM_0F ? int(Opcode::kMM_ForceVex3) : 0)) -#define O(PREFIX, OPCODE, O, LL, W, EvexW, N, TT) (O_ENCODE(0, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kO_##O, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kCDTT_##TT)) -#define V(PREFIX, OPCODE, O, LL, W, EvexW, N, TT) (O_ENCODE(1, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kO_##O, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kCDTT_##TT)) -#define E(PREFIX, OPCODE, O, LL, W, EvexW, N, TT) (O_ENCODE(1, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kO_##O, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kCDTT_##TT) | Opcode::kMM_ForceEvex) -#define O_FPU(PREFIX, OPCODE, O) (Opcode::kFPU_##PREFIX | (0x##OPCODE & 0xFFu) | ((0x##OPCODE >> 8) << Opcode::kFPU_2B_Shift) | Opcode::kO_##O) +#define O(PREFIX, OPCODE, ModO, LL, W, EvexW, N, ModRM) (O_ENCODE(0, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kModO_##ModO, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kModRM_##ModRM)) +#define V(PREFIX, OPCODE, ModO, LL, W, EvexW, N, TT) (O_ENCODE(1, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kModO_##ModO, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kCDTT_##TT)) +#define E(PREFIX, OPCODE, ModO, LL, W, EvexW, N, TT) (O_ENCODE(1, Opcode::k##PREFIX, 0x##OPCODE, Opcode::kModO_##ModO, Opcode::kLL_##LL, Opcode::kW_##W, Opcode::kEvex_W_##EvexW, Opcode::kCDSHL_##N, Opcode::kCDTT_##TT) | Opcode::kMM_ForceEvex) +#define O_FPU(PREFIX, OPCODE, ModO) (Opcode::kFPU_##PREFIX | (0x##OPCODE & 0xFFu) | ((0x##OPCODE >> 8) << Opcode::kFPU_2B_Shift) | Opcode::kModO_##ModO) // Don't store `_nameDataIndex` if instruction names are disabled. Since some // APIs can use `_nameDataIndex` it's much safer if it's zero if it's not defined. #ifndef ASMJIT_NO_TEXT - #define NAME_DATA_INDEX(X) X + #define NAME_DATA_INDEX(Index) Index #else - #define NAME_DATA_INDEX(X) 0 + #define NAME_DATA_INDEX(Index) 0 #endif // Defines an X86 instruction. @@ -101,26 +101,26 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Aas , X86Op_xAX , O(000000,3F,_,_,_,_,_,_ ), 0 , 0 , 0 , 13 , 1 , 1 ), // #4 INST(Adc , X86Arith , O(000000,10,2,_,x,_,_,_ ), 0 , 1 , 0 , 17 , 3 , 2 ), // #5 INST(Adcx , X86Rm , O(660F38,F6,_,_,x,_,_,_ ), 0 , 2 , 0 , 21 , 4 , 3 ), // #6 - INST(Add , X86Arith , O(000000,00,0,_,x,_,_,_ ), 0 , 0 , 0 , 3020 , 3 , 1 ), // #7 - INST(Addpd , ExtRm , O(660F00,58,_,_,_,_,_,_ ), 0 , 3 , 0 , 5002 , 5 , 4 ), // #8 - INST(Addps , ExtRm , O(000F00,58,_,_,_,_,_,_ ), 0 , 4 , 0 , 5014 , 5 , 5 ), // #9 - INST(Addsd , ExtRm , O(F20F00,58,_,_,_,_,_,_ ), 0 , 5 , 0 , 5236 , 6 , 4 ), // #10 - INST(Addss , ExtRm , O(F30F00,58,_,_,_,_,_,_ ), 0 , 6 , 0 , 3143 , 7 , 5 ), // #11 - INST(Addsubpd , ExtRm , O(660F00,D0,_,_,_,_,_,_ ), 0 , 3 , 0 , 4741 , 5 , 6 ), // #12 - INST(Addsubps , ExtRm , O(F20F00,D0,_,_,_,_,_,_ ), 0 , 5 , 0 , 4753 , 5 , 6 ), // #13 + INST(Add , X86Arith , O(000000,00,0,_,x,_,_,_ ), 0 , 0 , 0 , 3112 , 3 , 1 ), // #7 + INST(Addpd , ExtRm , O(660F00,58,_,_,_,_,_,_ ), 0 , 3 , 0 , 5102 , 5 , 4 ), // #8 + INST(Addps , ExtRm , O(000F00,58,_,_,_,_,_,_ ), 0 , 4 , 0 , 5114 , 5 , 5 ), // #9 + INST(Addsd , ExtRm , O(F20F00,58,_,_,_,_,_,_ ), 0 , 5 , 0 , 5336 , 6 , 4 ), // #10 + INST(Addss , ExtRm , O(F30F00,58,_,_,_,_,_,_ ), 0 , 6 , 0 , 3243 , 7 , 5 ), // #11 + INST(Addsubpd , ExtRm , O(660F00,D0,_,_,_,_,_,_ ), 0 , 3 , 0 , 4841 , 5 , 6 ), // #12 + INST(Addsubps , ExtRm , O(F20F00,D0,_,_,_,_,_,_ ), 0 , 5 , 0 , 4853 , 5 , 6 ), // #13 INST(Adox , X86Rm , O(F30F38,F6,_,_,x,_,_,_ ), 0 , 7 , 0 , 26 , 4 , 7 ), // #14 - INST(Aesdec , ExtRm , O(660F38,DE,_,_,_,_,_,_ ), 0 , 2 , 0 , 3198 , 5 , 8 ), // #15 - INST(Aesdeclast , ExtRm , O(660F38,DF,_,_,_,_,_,_ ), 0 , 2 , 0 , 3206 , 5 , 8 ), // #16 - INST(Aesenc , ExtRm , O(660F38,DC,_,_,_,_,_,_ ), 0 , 2 , 0 , 3218 , 5 , 8 ), // #17 - INST(Aesenclast , ExtRm , O(660F38,DD,_,_,_,_,_,_ ), 0 , 2 , 0 , 3226 , 5 , 8 ), // #18 - INST(Aesimc , ExtRm , O(660F38,DB,_,_,_,_,_,_ ), 0 , 2 , 0 , 3238 , 5 , 8 ), // #19 - INST(Aeskeygenassist , ExtRmi , O(660F3A,DF,_,_,_,_,_,_ ), 0 , 8 , 0 , 3246 , 8 , 8 ), // #20 - INST(And , X86Arith , O(000000,20,4,_,x,_,_,_ ), 0 , 9 , 0 , 2462 , 9 , 1 ), // #21 - INST(Andn , VexRvm_Wx , V(000F38,F2,_,0,x,_,_,_ ), 0 , 10 , 0 , 6710 , 10 , 9 ), // #22 - INST(Andnpd , ExtRm , O(660F00,55,_,_,_,_,_,_ ), 0 , 3 , 0 , 3279 , 5 , 4 ), // #23 - INST(Andnps , ExtRm , O(000F00,55,_,_,_,_,_,_ ), 0 , 4 , 0 , 3287 , 5 , 5 ), // #24 - INST(Andpd , ExtRm , O(660F00,54,_,_,_,_,_,_ ), 0 , 3 , 0 , 4255 , 11 , 4 ), // #25 - INST(Andps , ExtRm , O(000F00,54,_,_,_,_,_,_ ), 0 , 4 , 0 , 4265 , 11 , 5 ), // #26 + INST(Aesdec , ExtRm , O(660F38,DE,_,_,_,_,_,_ ), 0 , 2 , 0 , 3298 , 5 , 8 ), // #15 + INST(Aesdeclast , ExtRm , O(660F38,DF,_,_,_,_,_,_ ), 0 , 2 , 0 , 3306 , 5 , 8 ), // #16 + INST(Aesenc , ExtRm , O(660F38,DC,_,_,_,_,_,_ ), 0 , 2 , 0 , 3318 , 5 , 8 ), // #17 + INST(Aesenclast , ExtRm , O(660F38,DD,_,_,_,_,_,_ ), 0 , 2 , 0 , 3326 , 5 , 8 ), // #18 + INST(Aesimc , ExtRm , O(660F38,DB,_,_,_,_,_,_ ), 0 , 2 , 0 , 3338 , 5 , 8 ), // #19 + INST(Aeskeygenassist , ExtRmi , O(660F3A,DF,_,_,_,_,_,_ ), 0 , 8 , 0 , 3346 , 8 , 8 ), // #20 + INST(And , X86Arith , O(000000,20,4,_,x,_,_,_ ), 0 , 9 , 0 , 2510 , 9 , 1 ), // #21 + INST(Andn , VexRvm_Wx , V(000F38,F2,_,0,x,_,_,_ ), 0 , 10 , 0 , 6810 , 10 , 9 ), // #22 + INST(Andnpd , ExtRm , O(660F00,55,_,_,_,_,_,_ ), 0 , 3 , 0 , 3379 , 5 , 4 ), // #23 + INST(Andnps , ExtRm , O(000F00,55,_,_,_,_,_,_ ), 0 , 4 , 0 , 3387 , 5 , 5 ), // #24 + INST(Andpd , ExtRm , O(660F00,54,_,_,_,_,_,_ ), 0 , 3 , 0 , 4355 , 11 , 4 ), // #25 + INST(Andps , ExtRm , O(000F00,54,_,_,_,_,_,_ ), 0 , 4 , 0 , 4365 , 11 , 5 ), // #26 INST(Arpl , X86Mr_NoSize , O(000000,63,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 12 , 10 ), // #27 INST(Bextr , VexRmv_Wx , V(000F38,F7,_,0,x,_,_,_ ), 0 , 10 , 0 , 36 , 13 , 9 ), // #28 INST(Blcfill , VexVm_Wx , V(XOP_M9,01,1,0,x,_,_,_ ), 0 , 11 , 0 , 42 , 14 , 11 ), // #29 @@ -128,10 +128,10 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Blcic , VexVm_Wx , V(XOP_M9,01,5,0,x,_,_,_ ), 0 , 13 , 0 , 55 , 14 , 11 ), // #31 INST(Blcmsk , VexVm_Wx , V(XOP_M9,02,1,0,x,_,_,_ ), 0 , 11 , 0 , 61 , 14 , 11 ), // #32 INST(Blcs , VexVm_Wx , V(XOP_M9,01,3,0,x,_,_,_ ), 0 , 14 , 0 , 68 , 14 , 11 ), // #33 - INST(Blendpd , ExtRmi , O(660F3A,0D,_,_,_,_,_,_ ), 0 , 8 , 0 , 3365 , 8 , 12 ), // #34 - INST(Blendps , ExtRmi , O(660F3A,0C,_,_,_,_,_,_ ), 0 , 8 , 0 , 3374 , 8 , 12 ), // #35 - INST(Blendvpd , ExtRm_XMM0 , O(660F38,15,_,_,_,_,_,_ ), 0 , 2 , 0 , 3383 , 15 , 12 ), // #36 - INST(Blendvps , ExtRm_XMM0 , O(660F38,14,_,_,_,_,_,_ ), 0 , 2 , 0 , 3393 , 15 , 12 ), // #37 + INST(Blendpd , ExtRmi , O(660F3A,0D,_,_,_,_,_,_ ), 0 , 8 , 0 , 3465 , 8 , 12 ), // #34 + INST(Blendps , ExtRmi , O(660F3A,0C,_,_,_,_,_,_ ), 0 , 8 , 0 , 3474 , 8 , 12 ), // #35 + INST(Blendvpd , ExtRm_XMM0 , O(660F38,15,_,_,_,_,_,_ ), 0 , 2 , 0 , 3483 , 15 , 12 ), // #36 + INST(Blendvps , ExtRm_XMM0 , O(660F38,14,_,_,_,_,_,_ ), 0 , 2 , 0 , 3493 , 15 , 12 ), // #37 INST(Blsfill , VexVm_Wx , V(XOP_M9,01,2,0,x,_,_,_ ), 0 , 15 , 0 , 73 , 14 , 11 ), // #38 INST(Blsi , VexVm_Wx , V(000F38,F3,3,0,x,_,_,_ ), 0 , 16 , 0 , 81 , 14 , 9 ), // #39 INST(Blsic , VexVm_Wx , V(XOP_M9,01,6,0,x,_,_,_ ), 0 , 12 , 0 , 86 , 14 , 11 ), // #40 @@ -153,7 +153,7 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Btr , X86Bt , O(000F00,B3,_,_,x,_,_,_ ), O(000F00,BA,6,_,x,_,_,_ ), 4 , 4 , 176 , 25 , 14 ), // #56 INST(Bts , X86Bt , O(000F00,AB,_,_,x,_,_,_ ), O(000F00,BA,5,_,x,_,_,_ ), 4 , 5 , 180 , 25 , 14 ), // #57 INST(Bzhi , VexRmv_Wx , V(000F38,F5,_,0,x,_,_,_ ), 0 , 10 , 0 , 184 , 13 , 15 ), // #58 - INST(Call , X86Call , O(000000,FF,2,_,_,_,_,_ ), 0 , 1 , 0 , 2917 , 26 , 1 ), // #59 + INST(Call , X86Call , O(000000,FF,2,_,_,_,_,_ ), 0 , 1 , 0 , 3009 , 26 , 1 ), // #59 INST(Cbw , X86Op_xAX , O(660000,98,_,_,_,_,_,_ ), 0 , 19 , 0 , 189 , 27 , 0 ), // #60 INST(Cdq , X86Op_xDX_xAX , O(000000,99,_,_,_,_,_,_ ), 0 , 0 , 0 , 193 , 28 , 0 ), // #61 INST(Cdqe , X86Op_xAX , O(000000,98,_,_,1,_,_,_ ), 0 , 20 , 0 , 197 , 29 , 0 ), // #62 @@ -165,1466 +165,1483 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Clflushopt , X86M_Only , O(660F00,AE,7,_,_,_,_,_ ), 0 , 23 , 0 , 232 , 31 , 21 ), // #68 INST(Clgi , X86Op , O(000F01,DD,_,_,_,_,_,_ ), 0 , 21 , 0 , 243 , 30 , 22 ), // #69 INST(Cli , X86Op , O(000000,FA,_,_,_,_,_,_ ), 0 , 0 , 0 , 248 , 30 , 23 ), // #70 - INST(Clts , X86Op , O(000F00,06,_,_,_,_,_,_ ), 0 , 4 , 0 , 252 , 30 , 0 ), // #71 - INST(Clwb , X86M_Only , O(660F00,AE,6,_,_,_,_,_ ), 0 , 24 , 0 , 257 , 31 , 24 ), // #72 - INST(Clzero , X86Op_MemZAX , O(000F01,FC,_,_,_,_,_,_ ), 0 , 21 , 0 , 262 , 32 , 25 ), // #73 - INST(Cmc , X86Op , O(000000,F5,_,_,_,_,_,_ ), 0 , 0 , 0 , 269 , 30 , 26 ), // #74 - INST(Cmova , X86Rm , O(000F00,47,_,_,x,_,_,_ ), 0 , 4 , 0 , 273 , 22 , 27 ), // #75 - INST(Cmovae , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 4 , 0 , 279 , 22 , 28 ), // #76 - INST(Cmovb , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 4 , 0 , 618 , 22 , 28 ), // #77 - INST(Cmovbe , X86Rm , O(000F00,46,_,_,x,_,_,_ ), 0 , 4 , 0 , 625 , 22 , 27 ), // #78 - INST(Cmovc , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 4 , 0 , 286 , 22 , 28 ), // #79 - INST(Cmove , X86Rm , O(000F00,44,_,_,x,_,_,_ ), 0 , 4 , 0 , 633 , 22 , 29 ), // #80 - INST(Cmovg , X86Rm , O(000F00,4F,_,_,x,_,_,_ ), 0 , 4 , 0 , 292 , 22 , 30 ), // #81 - INST(Cmovge , X86Rm , O(000F00,4D,_,_,x,_,_,_ ), 0 , 4 , 0 , 298 , 22 , 31 ), // #82 - INST(Cmovl , X86Rm , O(000F00,4C,_,_,x,_,_,_ ), 0 , 4 , 0 , 305 , 22 , 31 ), // #83 - INST(Cmovle , X86Rm , O(000F00,4E,_,_,x,_,_,_ ), 0 , 4 , 0 , 311 , 22 , 30 ), // #84 - INST(Cmovna , X86Rm , O(000F00,46,_,_,x,_,_,_ ), 0 , 4 , 0 , 318 , 22 , 27 ), // #85 - INST(Cmovnae , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 4 , 0 , 325 , 22 , 28 ), // #86 - INST(Cmovnb , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 4 , 0 , 640 , 22 , 28 ), // #87 - INST(Cmovnbe , X86Rm , O(000F00,47,_,_,x,_,_,_ ), 0 , 4 , 0 , 648 , 22 , 27 ), // #88 - INST(Cmovnc , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 4 , 0 , 333 , 22 , 28 ), // #89 - INST(Cmovne , X86Rm , O(000F00,45,_,_,x,_,_,_ ), 0 , 4 , 0 , 657 , 22 , 29 ), // #90 - INST(Cmovng , X86Rm , O(000F00,4E,_,_,x,_,_,_ ), 0 , 4 , 0 , 340 , 22 , 30 ), // #91 - INST(Cmovnge , X86Rm , O(000F00,4C,_,_,x,_,_,_ ), 0 , 4 , 0 , 347 , 22 , 31 ), // #92 - INST(Cmovnl , X86Rm , O(000F00,4D,_,_,x,_,_,_ ), 0 , 4 , 0 , 355 , 22 , 31 ), // #93 - INST(Cmovnle , X86Rm , O(000F00,4F,_,_,x,_,_,_ ), 0 , 4 , 0 , 362 , 22 , 30 ), // #94 - INST(Cmovno , X86Rm , O(000F00,41,_,_,x,_,_,_ ), 0 , 4 , 0 , 370 , 22 , 32 ), // #95 - INST(Cmovnp , X86Rm , O(000F00,4B,_,_,x,_,_,_ ), 0 , 4 , 0 , 377 , 22 , 33 ), // #96 - INST(Cmovns , X86Rm , O(000F00,49,_,_,x,_,_,_ ), 0 , 4 , 0 , 384 , 22 , 34 ), // #97 - INST(Cmovnz , X86Rm , O(000F00,45,_,_,x,_,_,_ ), 0 , 4 , 0 , 391 , 22 , 29 ), // #98 - INST(Cmovo , X86Rm , O(000F00,40,_,_,x,_,_,_ ), 0 , 4 , 0 , 398 , 22 , 32 ), // #99 - INST(Cmovp , X86Rm , O(000F00,4A,_,_,x,_,_,_ ), 0 , 4 , 0 , 404 , 22 , 33 ), // #100 - INST(Cmovpe , X86Rm , O(000F00,4A,_,_,x,_,_,_ ), 0 , 4 , 0 , 410 , 22 , 33 ), // #101 - INST(Cmovpo , X86Rm , O(000F00,4B,_,_,x,_,_,_ ), 0 , 4 , 0 , 417 , 22 , 33 ), // #102 - INST(Cmovs , X86Rm , O(000F00,48,_,_,x,_,_,_ ), 0 , 4 , 0 , 424 , 22 , 34 ), // #103 - INST(Cmovz , X86Rm , O(000F00,44,_,_,x,_,_,_ ), 0 , 4 , 0 , 430 , 22 , 29 ), // #104 - INST(Cmp , X86Arith , O(000000,38,7,_,x,_,_,_ ), 0 , 25 , 0 , 436 , 33 , 1 ), // #105 - INST(Cmppd , ExtRmi , O(660F00,C2,_,_,_,_,_,_ ), 0 , 3 , 0 , 3619 , 8 , 4 ), // #106 - INST(Cmpps , ExtRmi , O(000F00,C2,_,_,_,_,_,_ ), 0 , 4 , 0 , 3626 , 8 , 5 ), // #107 - INST(Cmps , X86StrMm , O(000000,A6,_,_,_,_,_,_ ), 0 , 0 , 0 , 440 , 34 , 35 ), // #108 - INST(Cmpsd , ExtRmi , O(F20F00,C2,_,_,_,_,_,_ ), 0 , 5 , 0 , 3633 , 35 , 4 ), // #109 - INST(Cmpss , ExtRmi , O(F30F00,C2,_,_,_,_,_,_ ), 0 , 6 , 0 , 3640 , 36 , 5 ), // #110 - INST(Cmpxchg , X86Cmpxchg , O(000F00,B0,_,_,x,_,_,_ ), 0 , 4 , 0 , 445 , 37 , 36 ), // #111 - INST(Cmpxchg16b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,1,_,_,_ ), 0 , 26 , 0 , 453 , 38 , 37 ), // #112 - INST(Cmpxchg8b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,_,_,_,_ ), 0 , 27 , 0 , 464 , 39 , 38 ), // #113 - INST(Comisd , ExtRm , O(660F00,2F,_,_,_,_,_,_ ), 0 , 3 , 0 , 10146, 6 , 39 ), // #114 - INST(Comiss , ExtRm , O(000F00,2F,_,_,_,_,_,_ ), 0 , 4 , 0 , 10155, 7 , 40 ), // #115 - INST(Cpuid , X86Op , O(000F00,A2,_,_,_,_,_,_ ), 0 , 4 , 0 , 474 , 40 , 41 ), // #116 - INST(Cqo , X86Op_xDX_xAX , O(000000,99,_,_,1,_,_,_ ), 0 , 20 , 0 , 480 , 41 , 0 ), // #117 - INST(Crc32 , X86Crc , O(F20F38,F0,_,_,x,_,_,_ ), 0 , 28 , 0 , 484 , 42 , 42 ), // #118 - INST(Cvtdq2pd , ExtRm , O(F30F00,E6,_,_,_,_,_,_ ), 0 , 6 , 0 , 3687 , 6 , 4 ), // #119 - INST(Cvtdq2ps , ExtRm , O(000F00,5B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3697 , 5 , 4 ), // #120 - INST(Cvtpd2dq , ExtRm , O(F20F00,E6,_,_,_,_,_,_ ), 0 , 5 , 0 , 3736 , 5 , 4 ), // #121 - INST(Cvtpd2pi , ExtRm , O(660F00,2D,_,_,_,_,_,_ ), 0 , 3 , 0 , 490 , 43 , 4 ), // #122 - INST(Cvtpd2ps , ExtRm , O(660F00,5A,_,_,_,_,_,_ ), 0 , 3 , 0 , 3746 , 5 , 4 ), // #123 - INST(Cvtpi2pd , ExtRm , O(660F00,2A,_,_,_,_,_,_ ), 0 , 3 , 0 , 499 , 44 , 4 ), // #124 - INST(Cvtpi2ps , ExtRm , O(000F00,2A,_,_,_,_,_,_ ), 0 , 4 , 0 , 508 , 44 , 5 ), // #125 - INST(Cvtps2dq , ExtRm , O(660F00,5B,_,_,_,_,_,_ ), 0 , 3 , 0 , 3798 , 5 , 4 ), // #126 - INST(Cvtps2pd , ExtRm , O(000F00,5A,_,_,_,_,_,_ ), 0 , 4 , 0 , 3808 , 6 , 4 ), // #127 - INST(Cvtps2pi , ExtRm , O(000F00,2D,_,_,_,_,_,_ ), 0 , 4 , 0 , 517 , 45 , 5 ), // #128 - INST(Cvtsd2si , ExtRm_Wx , O(F20F00,2D,_,_,x,_,_,_ ), 0 , 5 , 0 , 3880 , 46 , 4 ), // #129 - INST(Cvtsd2ss , ExtRm , O(F20F00,5A,_,_,_,_,_,_ ), 0 , 5 , 0 , 3890 , 6 , 4 ), // #130 - INST(Cvtsi2sd , ExtRm_Wx , O(F20F00,2A,_,_,x,_,_,_ ), 0 , 5 , 0 , 3911 , 47 , 4 ), // #131 - INST(Cvtsi2ss , ExtRm_Wx , O(F30F00,2A,_,_,x,_,_,_ ), 0 , 6 , 0 , 3921 , 47 , 5 ), // #132 - INST(Cvtss2sd , ExtRm , O(F30F00,5A,_,_,_,_,_,_ ), 0 , 6 , 0 , 3931 , 7 , 4 ), // #133 - INST(Cvtss2si , ExtRm_Wx , O(F30F00,2D,_,_,x,_,_,_ ), 0 , 6 , 0 , 3941 , 48 , 5 ), // #134 - INST(Cvttpd2dq , ExtRm , O(660F00,E6,_,_,_,_,_,_ ), 0 , 3 , 0 , 3962 , 5 , 4 ), // #135 - INST(Cvttpd2pi , ExtRm , O(660F00,2C,_,_,_,_,_,_ ), 0 , 3 , 0 , 526 , 43 , 4 ), // #136 - INST(Cvttps2dq , ExtRm , O(F30F00,5B,_,_,_,_,_,_ ), 0 , 6 , 0 , 4008 , 5 , 4 ), // #137 - INST(Cvttps2pi , ExtRm , O(000F00,2C,_,_,_,_,_,_ ), 0 , 4 , 0 , 536 , 45 , 5 ), // #138 - INST(Cvttsd2si , ExtRm_Wx , O(F20F00,2C,_,_,x,_,_,_ ), 0 , 5 , 0 , 4054 , 46 , 4 ), // #139 - INST(Cvttss2si , ExtRm_Wx , O(F30F00,2C,_,_,x,_,_,_ ), 0 , 6 , 0 , 4077 , 48 , 5 ), // #140 - INST(Cwd , X86Op_xDX_xAX , O(660000,99,_,_,_,_,_,_ ), 0 , 19 , 0 , 546 , 49 , 0 ), // #141 - INST(Cwde , X86Op_xAX , O(000000,98,_,_,_,_,_,_ ), 0 , 0 , 0 , 550 , 50 , 0 ), // #142 - INST(Daa , X86Op , O(000000,27,_,_,_,_,_,_ ), 0 , 0 , 0 , 555 , 1 , 1 ), // #143 - INST(Das , X86Op , O(000000,2F,_,_,_,_,_,_ ), 0 , 0 , 0 , 559 , 1 , 1 ), // #144 - INST(Dec , X86IncDec , O(000000,FE,1,_,x,_,_,_ ), O(000000,48,_,_,x,_,_,_ ), 29 , 6 , 3201 , 51 , 43 ), // #145 - INST(Div , X86M_GPB_MulDiv , O(000000,F6,6,_,x,_,_,_ ), 0 , 30 , 0 , 780 , 52 , 1 ), // #146 - INST(Divpd , ExtRm , O(660F00,5E,_,_,_,_,_,_ ), 0 , 3 , 0 , 4176 , 5 , 4 ), // #147 - INST(Divps , ExtRm , O(000F00,5E,_,_,_,_,_,_ ), 0 , 4 , 0 , 4183 , 5 , 5 ), // #148 - INST(Divsd , ExtRm , O(F20F00,5E,_,_,_,_,_,_ ), 0 , 5 , 0 , 4190 , 6 , 4 ), // #149 - INST(Divss , ExtRm , O(F30F00,5E,_,_,_,_,_,_ ), 0 , 6 , 0 , 4197 , 7 , 5 ), // #150 - INST(Dppd , ExtRmi , O(660F3A,41,_,_,_,_,_,_ ), 0 , 8 , 0 , 4214 , 8 , 12 ), // #151 - INST(Dpps , ExtRmi , O(660F3A,40,_,_,_,_,_,_ ), 0 , 8 , 0 , 4220 , 8 , 12 ), // #152 - INST(Emms , X86Op , O(000F00,77,_,_,_,_,_,_ ), 0 , 4 , 0 , 748 , 53 , 44 ), // #153 - INST(Enqcmd , X86EnqcmdMovdir64b , O(F20F38,F8,_,_,_,_,_,_ ), 0 , 28 , 0 , 563 , 54 , 45 ), // #154 - INST(Enqcmds , X86EnqcmdMovdir64b , O(F30F38,F8,_,_,_,_,_,_ ), 0 , 7 , 0 , 570 , 54 , 45 ), // #155 - INST(Enter , X86Enter , O(000000,C8,_,_,_,_,_,_ ), 0 , 0 , 0 , 2925 , 55 , 0 ), // #156 - INST(Extractps , ExtExtract , O(660F3A,17,_,_,_,_,_,_ ), 0 , 8 , 0 , 4410 , 56 , 12 ), // #157 - INST(Extrq , ExtExtrq , O(660F00,79,_,_,_,_,_,_ ), O(660F00,78,0,_,_,_,_,_ ), 3 , 7 , 7506 , 57 , 46 ), // #158 - INST(F2xm1 , FpuOp , O_FPU(00,D9F0,_) , 0 , 31 , 0 , 578 , 30 , 0 ), // #159 - INST(Fabs , FpuOp , O_FPU(00,D9E1,_) , 0 , 31 , 0 , 584 , 30 , 0 ), // #160 - INST(Fadd , FpuArith , O_FPU(00,C0C0,0) , 0 , 32 , 0 , 2073 , 58 , 0 ), // #161 - INST(Faddp , FpuRDef , O_FPU(00,DEC0,_) , 0 , 33 , 0 , 589 , 59 , 0 ), // #162 - INST(Fbld , X86M_Only , O_FPU(00,00DF,4) , 0 , 34 , 0 , 595 , 60 , 0 ), // #163 - INST(Fbstp , X86M_Only , O_FPU(00,00DF,6) , 0 , 35 , 0 , 600 , 60 , 0 ), // #164 - INST(Fchs , FpuOp , O_FPU(00,D9E0,_) , 0 , 31 , 0 , 606 , 30 , 0 ), // #165 - INST(Fclex , FpuOp , O_FPU(9B,DBE2,_) , 0 , 36 , 0 , 611 , 30 , 0 ), // #166 - INST(Fcmovb , FpuR , O_FPU(00,DAC0,_) , 0 , 37 , 0 , 617 , 61 , 28 ), // #167 - INST(Fcmovbe , FpuR , O_FPU(00,DAD0,_) , 0 , 37 , 0 , 624 , 61 , 27 ), // #168 - INST(Fcmove , FpuR , O_FPU(00,DAC8,_) , 0 , 37 , 0 , 632 , 61 , 29 ), // #169 - INST(Fcmovnb , FpuR , O_FPU(00,DBC0,_) , 0 , 38 , 0 , 639 , 61 , 28 ), // #170 - INST(Fcmovnbe , FpuR , O_FPU(00,DBD0,_) , 0 , 38 , 0 , 647 , 61 , 27 ), // #171 - INST(Fcmovne , FpuR , O_FPU(00,DBC8,_) , 0 , 38 , 0 , 656 , 61 , 29 ), // #172 - INST(Fcmovnu , FpuR , O_FPU(00,DBD8,_) , 0 , 38 , 0 , 664 , 61 , 33 ), // #173 - INST(Fcmovu , FpuR , O_FPU(00,DAD8,_) , 0 , 37 , 0 , 672 , 61 , 33 ), // #174 - INST(Fcom , FpuCom , O_FPU(00,D0D0,2) , 0 , 39 , 0 , 679 , 62 , 0 ), // #175 - INST(Fcomi , FpuR , O_FPU(00,DBF0,_) , 0 , 38 , 0 , 684 , 61 , 47 ), // #176 - INST(Fcomip , FpuR , O_FPU(00,DFF0,_) , 0 , 40 , 0 , 690 , 61 , 47 ), // #177 - INST(Fcomp , FpuCom , O_FPU(00,D8D8,3) , 0 , 41 , 0 , 697 , 62 , 0 ), // #178 - INST(Fcompp , FpuOp , O_FPU(00,DED9,_) , 0 , 33 , 0 , 703 , 30 , 0 ), // #179 - INST(Fcos , FpuOp , O_FPU(00,D9FF,_) , 0 , 31 , 0 , 710 , 30 , 0 ), // #180 - INST(Fdecstp , FpuOp , O_FPU(00,D9F6,_) , 0 , 31 , 0 , 715 , 30 , 0 ), // #181 - INST(Fdiv , FpuArith , O_FPU(00,F0F8,6) , 0 , 42 , 0 , 723 , 58 , 0 ), // #182 - INST(Fdivp , FpuRDef , O_FPU(00,DEF8,_) , 0 , 33 , 0 , 728 , 59 , 0 ), // #183 - INST(Fdivr , FpuArith , O_FPU(00,F8F0,7) , 0 , 43 , 0 , 734 , 58 , 0 ), // #184 - INST(Fdivrp , FpuRDef , O_FPU(00,DEF0,_) , 0 , 33 , 0 , 740 , 59 , 0 ), // #185 - INST(Femms , X86Op , O(000F00,0E,_,_,_,_,_,_ ), 0 , 4 , 0 , 747 , 30 , 48 ), // #186 - INST(Ffree , FpuR , O_FPU(00,DDC0,_) , 0 , 44 , 0 , 753 , 61 , 0 ), // #187 - INST(Fiadd , FpuM , O_FPU(00,00DA,0) , 0 , 45 , 0 , 759 , 63 , 0 ), // #188 - INST(Ficom , FpuM , O_FPU(00,00DA,2) , 0 , 46 , 0 , 765 , 63 , 0 ), // #189 - INST(Ficomp , FpuM , O_FPU(00,00DA,3) , 0 , 47 , 0 , 771 , 63 , 0 ), // #190 - INST(Fidiv , FpuM , O_FPU(00,00DA,6) , 0 , 35 , 0 , 778 , 63 , 0 ), // #191 - INST(Fidivr , FpuM , O_FPU(00,00DA,7) , 0 , 48 , 0 , 784 , 63 , 0 ), // #192 - INST(Fild , FpuM , O_FPU(00,00DB,0) , O_FPU(00,00DF,5) , 45 , 8 , 791 , 64 , 0 ), // #193 - INST(Fimul , FpuM , O_FPU(00,00DA,1) , 0 , 49 , 0 , 796 , 63 , 0 ), // #194 - INST(Fincstp , FpuOp , O_FPU(00,D9F7,_) , 0 , 31 , 0 , 802 , 30 , 0 ), // #195 - INST(Finit , FpuOp , O_FPU(9B,DBE3,_) , 0 , 36 , 0 , 810 , 30 , 0 ), // #196 - INST(Fist , FpuM , O_FPU(00,00DB,2) , 0 , 46 , 0 , 816 , 63 , 0 ), // #197 - INST(Fistp , FpuM , O_FPU(00,00DB,3) , O_FPU(00,00DF,7) , 47 , 9 , 821 , 64 , 0 ), // #198 - INST(Fisttp , FpuM , O_FPU(00,00DB,1) , O_FPU(00,00DD,1) , 49 , 10 , 827 , 64 , 6 ), // #199 - INST(Fisub , FpuM , O_FPU(00,00DA,4) , 0 , 34 , 0 , 834 , 63 , 0 ), // #200 - INST(Fisubr , FpuM , O_FPU(00,00DA,5) , 0 , 50 , 0 , 840 , 63 , 0 ), // #201 - INST(Fld , FpuFldFst , O_FPU(00,00D9,0) , O_FPU(00,00DB,5) , 45 , 11 , 847 , 65 , 0 ), // #202 - INST(Fld1 , FpuOp , O_FPU(00,D9E8,_) , 0 , 31 , 0 , 851 , 30 , 0 ), // #203 - INST(Fldcw , X86M_Only , O_FPU(00,00D9,5) , 0 , 50 , 0 , 856 , 66 , 0 ), // #204 - INST(Fldenv , X86M_Only , O_FPU(00,00D9,4) , 0 , 34 , 0 , 862 , 31 , 0 ), // #205 - INST(Fldl2e , FpuOp , O_FPU(00,D9EA,_) , 0 , 31 , 0 , 869 , 30 , 0 ), // #206 - INST(Fldl2t , FpuOp , O_FPU(00,D9E9,_) , 0 , 31 , 0 , 876 , 30 , 0 ), // #207 - INST(Fldlg2 , FpuOp , O_FPU(00,D9EC,_) , 0 , 31 , 0 , 883 , 30 , 0 ), // #208 - INST(Fldln2 , FpuOp , O_FPU(00,D9ED,_) , 0 , 31 , 0 , 890 , 30 , 0 ), // #209 - INST(Fldpi , FpuOp , O_FPU(00,D9EB,_) , 0 , 31 , 0 , 897 , 30 , 0 ), // #210 - INST(Fldz , FpuOp , O_FPU(00,D9EE,_) , 0 , 31 , 0 , 903 , 30 , 0 ), // #211 - INST(Fmul , FpuArith , O_FPU(00,C8C8,1) , 0 , 51 , 0 , 2115 , 58 , 0 ), // #212 - INST(Fmulp , FpuRDef , O_FPU(00,DEC8,_) , 0 , 33 , 0 , 908 , 59 , 0 ), // #213 - INST(Fnclex , FpuOp , O_FPU(00,DBE2,_) , 0 , 38 , 0 , 914 , 30 , 0 ), // #214 - INST(Fninit , FpuOp , O_FPU(00,DBE3,_) , 0 , 38 , 0 , 921 , 30 , 0 ), // #215 - INST(Fnop , FpuOp , O_FPU(00,D9D0,_) , 0 , 31 , 0 , 928 , 30 , 0 ), // #216 - INST(Fnsave , X86M_Only , O_FPU(00,00DD,6) , 0 , 35 , 0 , 933 , 31 , 0 ), // #217 - INST(Fnstcw , X86M_Only , O_FPU(00,00D9,7) , 0 , 48 , 0 , 940 , 66 , 0 ), // #218 - INST(Fnstenv , X86M_Only , O_FPU(00,00D9,6) , 0 , 35 , 0 , 947 , 31 , 0 ), // #219 - INST(Fnstsw , FpuStsw , O_FPU(00,00DD,7) , O_FPU(00,DFE0,_) , 48 , 12 , 955 , 67 , 0 ), // #220 - INST(Fpatan , FpuOp , O_FPU(00,D9F3,_) , 0 , 31 , 0 , 962 , 30 , 0 ), // #221 - INST(Fprem , FpuOp , O_FPU(00,D9F8,_) , 0 , 31 , 0 , 969 , 30 , 0 ), // #222 - INST(Fprem1 , FpuOp , O_FPU(00,D9F5,_) , 0 , 31 , 0 , 975 , 30 , 0 ), // #223 - INST(Fptan , FpuOp , O_FPU(00,D9F2,_) , 0 , 31 , 0 , 982 , 30 , 0 ), // #224 - INST(Frndint , FpuOp , O_FPU(00,D9FC,_) , 0 , 31 , 0 , 988 , 30 , 0 ), // #225 - INST(Frstor , X86M_Only , O_FPU(00,00DD,4) , 0 , 34 , 0 , 996 , 31 , 0 ), // #226 - INST(Fsave , X86M_Only , O_FPU(9B,00DD,6) , 0 , 52 , 0 , 1003 , 31 , 0 ), // #227 - INST(Fscale , FpuOp , O_FPU(00,D9FD,_) , 0 , 31 , 0 , 1009 , 30 , 0 ), // #228 - INST(Fsin , FpuOp , O_FPU(00,D9FE,_) , 0 , 31 , 0 , 1016 , 30 , 0 ), // #229 - INST(Fsincos , FpuOp , O_FPU(00,D9FB,_) , 0 , 31 , 0 , 1021 , 30 , 0 ), // #230 - INST(Fsqrt , FpuOp , O_FPU(00,D9FA,_) , 0 , 31 , 0 , 1029 , 30 , 0 ), // #231 - INST(Fst , FpuFldFst , O_FPU(00,00D9,2) , 0 , 46 , 0 , 1035 , 68 , 0 ), // #232 - INST(Fstcw , X86M_Only , O_FPU(9B,00D9,7) , 0 , 53 , 0 , 1039 , 66 , 0 ), // #233 - INST(Fstenv , X86M_Only , O_FPU(9B,00D9,6) , 0 , 52 , 0 , 1045 , 31 , 0 ), // #234 - INST(Fstp , FpuFldFst , O_FPU(00,00D9,3) , O(000000,DB,7,_,_,_,_,_ ), 47 , 13 , 1052 , 65 , 0 ), // #235 - INST(Fstsw , FpuStsw , O_FPU(9B,00DD,7) , O_FPU(9B,DFE0,_) , 53 , 14 , 1057 , 67 , 0 ), // #236 - INST(Fsub , FpuArith , O_FPU(00,E0E8,4) , 0 , 54 , 0 , 2193 , 58 , 0 ), // #237 - INST(Fsubp , FpuRDef , O_FPU(00,DEE8,_) , 0 , 33 , 0 , 1063 , 59 , 0 ), // #238 - INST(Fsubr , FpuArith , O_FPU(00,E8E0,5) , 0 , 55 , 0 , 2199 , 58 , 0 ), // #239 - INST(Fsubrp , FpuRDef , O_FPU(00,DEE0,_) , 0 , 33 , 0 , 1069 , 59 , 0 ), // #240 - INST(Ftst , FpuOp , O_FPU(00,D9E4,_) , 0 , 31 , 0 , 1076 , 30 , 0 ), // #241 - INST(Fucom , FpuRDef , O_FPU(00,DDE0,_) , 0 , 44 , 0 , 1081 , 59 , 0 ), // #242 - INST(Fucomi , FpuR , O_FPU(00,DBE8,_) , 0 , 38 , 0 , 1087 , 61 , 47 ), // #243 - INST(Fucomip , FpuR , O_FPU(00,DFE8,_) , 0 , 40 , 0 , 1094 , 61 , 47 ), // #244 - INST(Fucomp , FpuRDef , O_FPU(00,DDE8,_) , 0 , 44 , 0 , 1102 , 59 , 0 ), // #245 - INST(Fucompp , FpuOp , O_FPU(00,DAE9,_) , 0 , 37 , 0 , 1109 , 30 , 0 ), // #246 - INST(Fwait , X86Op , O_FPU(00,009B,_) , 0 , 56 , 0 , 1117 , 30 , 0 ), // #247 - INST(Fxam , FpuOp , O_FPU(00,D9E5,_) , 0 , 31 , 0 , 1123 , 30 , 0 ), // #248 - INST(Fxch , FpuR , O_FPU(00,D9C8,_) , 0 , 31 , 0 , 1128 , 59 , 0 ), // #249 - INST(Fxrstor , X86M_Only , O(000F00,AE,1,_,_,_,_,_ ), 0 , 27 , 0 , 1133 , 31 , 49 ), // #250 - INST(Fxrstor64 , X86M_Only , O(000F00,AE,1,_,1,_,_,_ ), 0 , 26 , 0 , 1141 , 69 , 49 ), // #251 - INST(Fxsave , X86M_Only , O(000F00,AE,0,_,_,_,_,_ ), 0 , 4 , 0 , 1151 , 31 , 49 ), // #252 - INST(Fxsave64 , X86M_Only , O(000F00,AE,0,_,1,_,_,_ ), 0 , 57 , 0 , 1158 , 69 , 49 ), // #253 - INST(Fxtract , FpuOp , O_FPU(00,D9F4,_) , 0 , 31 , 0 , 1167 , 30 , 0 ), // #254 - INST(Fyl2x , FpuOp , O_FPU(00,D9F1,_) , 0 , 31 , 0 , 1175 , 30 , 0 ), // #255 - INST(Fyl2xp1 , FpuOp , O_FPU(00,D9F9,_) , 0 , 31 , 0 , 1181 , 30 , 0 ), // #256 - INST(Getsec , X86Op , O(000F00,37,_,_,_,_,_,_ ), 0 , 4 , 0 , 1189 , 30 , 50 ), // #257 - INST(Gf2p8affineinvqb , ExtRmi , O(660F3A,CF,_,_,_,_,_,_ ), 0 , 8 , 0 , 5765 , 8 , 51 ), // #258 - INST(Gf2p8affineqb , ExtRmi , O(660F3A,CE,_,_,_,_,_,_ ), 0 , 8 , 0 , 5783 , 8 , 51 ), // #259 - INST(Gf2p8mulb , ExtRm , O(660F38,CF,_,_,_,_,_,_ ), 0 , 2 , 0 , 5798 , 5 , 51 ), // #260 - INST(Haddpd , ExtRm , O(660F00,7C,_,_,_,_,_,_ ), 0 , 3 , 0 , 5809 , 5 , 6 ), // #261 - INST(Haddps , ExtRm , O(F20F00,7C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5817 , 5 , 6 ), // #262 - INST(Hlt , X86Op , O(000000,F4,_,_,_,_,_,_ ), 0 , 0 , 0 , 1196 , 30 , 0 ), // #263 - INST(Hsubpd , ExtRm , O(660F00,7D,_,_,_,_,_,_ ), 0 , 3 , 0 , 5825 , 5 , 6 ), // #264 - INST(Hsubps , ExtRm , O(F20F00,7D,_,_,_,_,_,_ ), 0 , 5 , 0 , 5833 , 5 , 6 ), // #265 - INST(Idiv , X86M_GPB_MulDiv , O(000000,F6,7,_,x,_,_,_ ), 0 , 25 , 0 , 779 , 52 , 1 ), // #266 - INST(Imul , X86Imul , O(000000,F6,5,_,x,_,_,_ ), 0 , 58 , 0 , 797 , 70 , 1 ), // #267 - INST(In , X86In , O(000000,EC,_,_,_,_,_,_ ), O(000000,E4,_,_,_,_,_,_ ), 0 , 15 , 10292, 71 , 0 ), // #268 - INST(Inc , X86IncDec , O(000000,FE,0,_,x,_,_,_ ), O(000000,40,_,_,x,_,_,_ ), 0 , 16 , 1200 , 51 , 43 ), // #269 - INST(Ins , X86Ins , O(000000,6C,_,_,_,_,_,_ ), 0 , 0 , 0 , 1867 , 72 , 0 ), // #270 - INST(Insertps , ExtRmi , O(660F3A,21,_,_,_,_,_,_ ), 0 , 8 , 0 , 5969 , 36 , 12 ), // #271 - INST(Insertq , ExtInsertq , O(F20F00,79,_,_,_,_,_,_ ), O(F20F00,78,_,_,_,_,_,_ ), 5 , 17 , 1204 , 73 , 46 ), // #272 - INST(Int , X86Int , O(000000,CD,_,_,_,_,_,_ ), 0 , 0 , 0 , 992 , 74 , 0 ), // #273 - INST(Int3 , X86Op , O(000000,CC,_,_,_,_,_,_ ), 0 , 0 , 0 , 1212 , 30 , 0 ), // #274 - INST(Into , X86Op , O(000000,CE,_,_,_,_,_,_ ), 0 , 0 , 0 , 1217 , 75 , 52 ), // #275 - INST(Invd , X86Op , O(000F00,08,_,_,_,_,_,_ ), 0 , 4 , 0 , 10247, 30 , 41 ), // #276 - INST(Invept , X86Rm_NoSize , O(660F38,80,_,_,_,_,_,_ ), 0 , 2 , 0 , 1222 , 76 , 53 ), // #277 - INST(Invlpg , X86M_Only , O(000F00,01,7,_,_,_,_,_ ), 0 , 22 , 0 , 1229 , 31 , 41 ), // #278 - INST(Invlpga , X86Op_xAddr , O(000F01,DF,_,_,_,_,_,_ ), 0 , 21 , 0 , 1236 , 77 , 22 ), // #279 - INST(Invpcid , X86Rm_NoSize , O(660F38,82,_,_,_,_,_,_ ), 0 , 2 , 0 , 1244 , 76 , 41 ), // #280 - INST(Invvpid , X86Rm_NoSize , O(660F38,81,_,_,_,_,_,_ ), 0 , 2 , 0 , 1252 , 76 , 53 ), // #281 - INST(Iret , X86Op , O(000000,CF,_,_,_,_,_,_ ), 0 , 0 , 0 , 1260 , 78 , 1 ), // #282 - INST(Iretd , X86Op , O(000000,CF,_,_,_,_,_,_ ), 0 , 0 , 0 , 1265 , 78 , 1 ), // #283 - INST(Iretq , X86Op , O(000000,CF,_,_,1,_,_,_ ), 0 , 20 , 0 , 1271 , 79 , 1 ), // #284 - INST(Iretw , X86Op , O(660000,CF,_,_,_,_,_,_ ), 0 , 19 , 0 , 1277 , 78 , 1 ), // #285 - INST(Ja , X86Jcc , O(000F00,87,_,_,_,_,_,_ ), O(000000,77,_,_,_,_,_,_ ), 4 , 18 , 1283 , 80 , 54 ), // #286 - INST(Jae , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 4 , 19 , 1286 , 80 , 55 ), // #287 - INST(Jb , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 4 , 20 , 1290 , 80 , 55 ), // #288 - INST(Jbe , X86Jcc , O(000F00,86,_,_,_,_,_,_ ), O(000000,76,_,_,_,_,_,_ ), 4 , 21 , 1293 , 80 , 54 ), // #289 - INST(Jc , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 4 , 20 , 1297 , 80 , 55 ), // #290 - INST(Je , X86Jcc , O(000F00,84,_,_,_,_,_,_ ), O(000000,74,_,_,_,_,_,_ ), 4 , 22 , 1300 , 80 , 56 ), // #291 - INST(Jecxz , X86JecxzLoop , 0 , O(000000,E3,_,_,_,_,_,_ ), 0 , 23 , 1303 , 81 , 0 ), // #292 - INST(Jg , X86Jcc , O(000F00,8F,_,_,_,_,_,_ ), O(000000,7F,_,_,_,_,_,_ ), 4 , 24 , 1309 , 80 , 57 ), // #293 - INST(Jge , X86Jcc , O(000F00,8D,_,_,_,_,_,_ ), O(000000,7D,_,_,_,_,_,_ ), 4 , 25 , 1312 , 80 , 58 ), // #294 - INST(Jl , X86Jcc , O(000F00,8C,_,_,_,_,_,_ ), O(000000,7C,_,_,_,_,_,_ ), 4 , 26 , 1316 , 80 , 58 ), // #295 - INST(Jle , X86Jcc , O(000F00,8E,_,_,_,_,_,_ ), O(000000,7E,_,_,_,_,_,_ ), 4 , 27 , 1319 , 80 , 57 ), // #296 - INST(Jmp , X86Jmp , O(000000,FF,4,_,_,_,_,_ ), O(000000,EB,_,_,_,_,_,_ ), 9 , 28 , 1323 , 82 , 0 ), // #297 - INST(Jna , X86Jcc , O(000F00,86,_,_,_,_,_,_ ), O(000000,76,_,_,_,_,_,_ ), 4 , 21 , 1327 , 80 , 54 ), // #298 - INST(Jnae , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 4 , 20 , 1331 , 80 , 55 ), // #299 - INST(Jnb , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 4 , 19 , 1336 , 80 , 55 ), // #300 - INST(Jnbe , X86Jcc , O(000F00,87,_,_,_,_,_,_ ), O(000000,77,_,_,_,_,_,_ ), 4 , 18 , 1340 , 80 , 54 ), // #301 - INST(Jnc , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 4 , 19 , 1345 , 80 , 55 ), // #302 - INST(Jne , X86Jcc , O(000F00,85,_,_,_,_,_,_ ), O(000000,75,_,_,_,_,_,_ ), 4 , 29 , 1349 , 80 , 56 ), // #303 - INST(Jng , X86Jcc , O(000F00,8E,_,_,_,_,_,_ ), O(000000,7E,_,_,_,_,_,_ ), 4 , 27 , 1353 , 80 , 57 ), // #304 - INST(Jnge , X86Jcc , O(000F00,8C,_,_,_,_,_,_ ), O(000000,7C,_,_,_,_,_,_ ), 4 , 26 , 1357 , 80 , 58 ), // #305 - INST(Jnl , X86Jcc , O(000F00,8D,_,_,_,_,_,_ ), O(000000,7D,_,_,_,_,_,_ ), 4 , 25 , 1362 , 80 , 58 ), // #306 - INST(Jnle , X86Jcc , O(000F00,8F,_,_,_,_,_,_ ), O(000000,7F,_,_,_,_,_,_ ), 4 , 24 , 1366 , 80 , 57 ), // #307 - INST(Jno , X86Jcc , O(000F00,81,_,_,_,_,_,_ ), O(000000,71,_,_,_,_,_,_ ), 4 , 30 , 1371 , 80 , 52 ), // #308 - INST(Jnp , X86Jcc , O(000F00,8B,_,_,_,_,_,_ ), O(000000,7B,_,_,_,_,_,_ ), 4 , 31 , 1375 , 80 , 59 ), // #309 - INST(Jns , X86Jcc , O(000F00,89,_,_,_,_,_,_ ), O(000000,79,_,_,_,_,_,_ ), 4 , 32 , 1379 , 80 , 60 ), // #310 - INST(Jnz , X86Jcc , O(000F00,85,_,_,_,_,_,_ ), O(000000,75,_,_,_,_,_,_ ), 4 , 29 , 1383 , 80 , 56 ), // #311 - INST(Jo , X86Jcc , O(000F00,80,_,_,_,_,_,_ ), O(000000,70,_,_,_,_,_,_ ), 4 , 33 , 1387 , 80 , 52 ), // #312 - INST(Jp , X86Jcc , O(000F00,8A,_,_,_,_,_,_ ), O(000000,7A,_,_,_,_,_,_ ), 4 , 34 , 1390 , 80 , 59 ), // #313 - INST(Jpe , X86Jcc , O(000F00,8A,_,_,_,_,_,_ ), O(000000,7A,_,_,_,_,_,_ ), 4 , 34 , 1393 , 80 , 59 ), // #314 - INST(Jpo , X86Jcc , O(000F00,8B,_,_,_,_,_,_ ), O(000000,7B,_,_,_,_,_,_ ), 4 , 31 , 1397 , 80 , 59 ), // #315 - INST(Js , X86Jcc , O(000F00,88,_,_,_,_,_,_ ), O(000000,78,_,_,_,_,_,_ ), 4 , 35 , 1401 , 80 , 60 ), // #316 - INST(Jz , X86Jcc , O(000F00,84,_,_,_,_,_,_ ), O(000000,74,_,_,_,_,_,_ ), 4 , 22 , 1404 , 80 , 56 ), // #317 - INST(Kaddb , VexRvm , V(660F00,4A,_,1,0,_,_,_ ), 0 , 59 , 0 , 1407 , 83 , 61 ), // #318 - INST(Kaddd , VexRvm , V(660F00,4A,_,1,1,_,_,_ ), 0 , 60 , 0 , 1413 , 83 , 62 ), // #319 - INST(Kaddq , VexRvm , V(000F00,4A,_,1,1,_,_,_ ), 0 , 61 , 0 , 1419 , 83 , 62 ), // #320 - INST(Kaddw , VexRvm , V(000F00,4A,_,1,0,_,_,_ ), 0 , 62 , 0 , 1425 , 83 , 61 ), // #321 - INST(Kandb , VexRvm , V(660F00,41,_,1,0,_,_,_ ), 0 , 59 , 0 , 1431 , 83 , 61 ), // #322 - INST(Kandd , VexRvm , V(660F00,41,_,1,1,_,_,_ ), 0 , 60 , 0 , 1437 , 83 , 62 ), // #323 - INST(Kandnb , VexRvm , V(660F00,42,_,1,0,_,_,_ ), 0 , 59 , 0 , 1443 , 83 , 61 ), // #324 - INST(Kandnd , VexRvm , V(660F00,42,_,1,1,_,_,_ ), 0 , 60 , 0 , 1450 , 83 , 62 ), // #325 - INST(Kandnq , VexRvm , V(000F00,42,_,1,1,_,_,_ ), 0 , 61 , 0 , 1457 , 83 , 62 ), // #326 - INST(Kandnw , VexRvm , V(000F00,42,_,1,0,_,_,_ ), 0 , 62 , 0 , 1464 , 83 , 63 ), // #327 - INST(Kandq , VexRvm , V(000F00,41,_,1,1,_,_,_ ), 0 , 61 , 0 , 1471 , 83 , 62 ), // #328 - INST(Kandw , VexRvm , V(000F00,41,_,1,0,_,_,_ ), 0 , 62 , 0 , 1477 , 83 , 63 ), // #329 - INST(Kmovb , VexKmov , V(660F00,90,_,0,0,_,_,_ ), V(660F00,92,_,0,0,_,_,_ ), 63 , 36 , 1483 , 84 , 61 ), // #330 - INST(Kmovd , VexKmov , V(660F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,0,_,_,_ ), 64 , 37 , 7986 , 85 , 62 ), // #331 - INST(Kmovq , VexKmov , V(000F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,1,_,_,_ ), 65 , 38 , 7997 , 86 , 62 ), // #332 - INST(Kmovw , VexKmov , V(000F00,90,_,0,0,_,_,_ ), V(000F00,92,_,0,0,_,_,_ ), 66 , 39 , 1489 , 87 , 63 ), // #333 - INST(Knotb , VexRm , V(660F00,44,_,0,0,_,_,_ ), 0 , 63 , 0 , 1495 , 88 , 61 ), // #334 - INST(Knotd , VexRm , V(660F00,44,_,0,1,_,_,_ ), 0 , 64 , 0 , 1501 , 88 , 62 ), // #335 - INST(Knotq , VexRm , V(000F00,44,_,0,1,_,_,_ ), 0 , 65 , 0 , 1507 , 88 , 62 ), // #336 - INST(Knotw , VexRm , V(000F00,44,_,0,0,_,_,_ ), 0 , 66 , 0 , 1513 , 88 , 63 ), // #337 - INST(Korb , VexRvm , V(660F00,45,_,1,0,_,_,_ ), 0 , 59 , 0 , 1519 , 83 , 61 ), // #338 - INST(Kord , VexRvm , V(660F00,45,_,1,1,_,_,_ ), 0 , 60 , 0 , 1524 , 83 , 62 ), // #339 - INST(Korq , VexRvm , V(000F00,45,_,1,1,_,_,_ ), 0 , 61 , 0 , 1529 , 83 , 62 ), // #340 - INST(Kortestb , VexRm , V(660F00,98,_,0,0,_,_,_ ), 0 , 63 , 0 , 1534 , 88 , 64 ), // #341 - INST(Kortestd , VexRm , V(660F00,98,_,0,1,_,_,_ ), 0 , 64 , 0 , 1543 , 88 , 65 ), // #342 - INST(Kortestq , VexRm , V(000F00,98,_,0,1,_,_,_ ), 0 , 65 , 0 , 1552 , 88 , 65 ), // #343 - INST(Kortestw , VexRm , V(000F00,98,_,0,0,_,_,_ ), 0 , 66 , 0 , 1561 , 88 , 66 ), // #344 - INST(Korw , VexRvm , V(000F00,45,_,1,0,_,_,_ ), 0 , 62 , 0 , 1570 , 83 , 63 ), // #345 - INST(Kshiftlb , VexRmi , V(660F3A,32,_,0,0,_,_,_ ), 0 , 67 , 0 , 1575 , 89 , 61 ), // #346 - INST(Kshiftld , VexRmi , V(660F3A,33,_,0,0,_,_,_ ), 0 , 67 , 0 , 1584 , 89 , 62 ), // #347 - INST(Kshiftlq , VexRmi , V(660F3A,33,_,0,1,_,_,_ ), 0 , 68 , 0 , 1593 , 89 , 62 ), // #348 - INST(Kshiftlw , VexRmi , V(660F3A,32,_,0,1,_,_,_ ), 0 , 68 , 0 , 1602 , 89 , 63 ), // #349 - INST(Kshiftrb , VexRmi , V(660F3A,30,_,0,0,_,_,_ ), 0 , 67 , 0 , 1611 , 89 , 61 ), // #350 - INST(Kshiftrd , VexRmi , V(660F3A,31,_,0,0,_,_,_ ), 0 , 67 , 0 , 1620 , 89 , 62 ), // #351 - INST(Kshiftrq , VexRmi , V(660F3A,31,_,0,1,_,_,_ ), 0 , 68 , 0 , 1629 , 89 , 62 ), // #352 - INST(Kshiftrw , VexRmi , V(660F3A,30,_,0,1,_,_,_ ), 0 , 68 , 0 , 1638 , 89 , 63 ), // #353 - INST(Ktestb , VexRm , V(660F00,99,_,0,0,_,_,_ ), 0 , 63 , 0 , 1647 , 88 , 64 ), // #354 - INST(Ktestd , VexRm , V(660F00,99,_,0,1,_,_,_ ), 0 , 64 , 0 , 1654 , 88 , 65 ), // #355 - INST(Ktestq , VexRm , V(000F00,99,_,0,1,_,_,_ ), 0 , 65 , 0 , 1661 , 88 , 65 ), // #356 - INST(Ktestw , VexRm , V(000F00,99,_,0,0,_,_,_ ), 0 , 66 , 0 , 1668 , 88 , 64 ), // #357 - INST(Kunpckbw , VexRvm , V(660F00,4B,_,1,0,_,_,_ ), 0 , 59 , 0 , 1675 , 83 , 63 ), // #358 - INST(Kunpckdq , VexRvm , V(000F00,4B,_,1,1,_,_,_ ), 0 , 61 , 0 , 1684 , 83 , 62 ), // #359 - INST(Kunpckwd , VexRvm , V(000F00,4B,_,1,0,_,_,_ ), 0 , 62 , 0 , 1693 , 83 , 62 ), // #360 - INST(Kxnorb , VexRvm , V(660F00,46,_,1,0,_,_,_ ), 0 , 59 , 0 , 1702 , 83 , 61 ), // #361 - INST(Kxnord , VexRvm , V(660F00,46,_,1,1,_,_,_ ), 0 , 60 , 0 , 1709 , 83 , 62 ), // #362 - INST(Kxnorq , VexRvm , V(000F00,46,_,1,1,_,_,_ ), 0 , 61 , 0 , 1716 , 83 , 62 ), // #363 - INST(Kxnorw , VexRvm , V(000F00,46,_,1,0,_,_,_ ), 0 , 62 , 0 , 1723 , 83 , 63 ), // #364 - INST(Kxorb , VexRvm , V(660F00,47,_,1,0,_,_,_ ), 0 , 59 , 0 , 1730 , 83 , 61 ), // #365 - INST(Kxord , VexRvm , V(660F00,47,_,1,1,_,_,_ ), 0 , 60 , 0 , 1736 , 83 , 62 ), // #366 - INST(Kxorq , VexRvm , V(000F00,47,_,1,1,_,_,_ ), 0 , 61 , 0 , 1742 , 83 , 62 ), // #367 - INST(Kxorw , VexRvm , V(000F00,47,_,1,0,_,_,_ ), 0 , 62 , 0 , 1748 , 83 , 63 ), // #368 - INST(Lahf , X86Op , O(000000,9F,_,_,_,_,_,_ ), 0 , 0 , 0 , 1754 , 90 , 67 ), // #369 - INST(Lar , X86Rm , O(000F00,02,_,_,_,_,_,_ ), 0 , 4 , 0 , 1759 , 91 , 10 ), // #370 - INST(Lddqu , ExtRm , O(F20F00,F0,_,_,_,_,_,_ ), 0 , 5 , 0 , 5979 , 92 , 6 ), // #371 - INST(Ldmxcsr , X86M_Only , O(000F00,AE,2,_,_,_,_,_ ), 0 , 69 , 0 , 5986 , 93 , 5 ), // #372 - INST(Lds , X86Rm , O(000000,C5,_,_,_,_,_,_ ), 0 , 0 , 0 , 1763 , 94 , 0 ), // #373 - INST(Ldtilecfg , AmxCfg , V(000F38,49,_,0,0,_,_,_ ), 0 , 10 , 0 , 1767 , 95 , 68 ), // #374 - INST(Lea , X86Lea , O(000000,8D,_,_,x,_,_,_ ), 0 , 0 , 0 , 1777 , 96 , 0 ), // #375 - INST(Leave , X86Op , O(000000,C9,_,_,_,_,_,_ ), 0 , 0 , 0 , 1781 , 30 , 0 ), // #376 - INST(Les , X86Rm , O(000000,C4,_,_,_,_,_,_ ), 0 , 0 , 0 , 1787 , 94 , 0 ), // #377 - INST(Lfence , X86Fence , O(000F00,AE,5,_,_,_,_,_ ), 0 , 70 , 0 , 1791 , 30 , 4 ), // #378 - INST(Lfs , X86Rm , O(000F00,B4,_,_,_,_,_,_ ), 0 , 4 , 0 , 1798 , 97 , 0 ), // #379 - INST(Lgdt , X86M_Only , O(000F00,01,2,_,_,_,_,_ ), 0 , 69 , 0 , 1802 , 31 , 0 ), // #380 - INST(Lgs , X86Rm , O(000F00,B5,_,_,_,_,_,_ ), 0 , 4 , 0 , 1807 , 97 , 0 ), // #381 - INST(Lidt , X86M_Only , O(000F00,01,3,_,_,_,_,_ ), 0 , 71 , 0 , 1811 , 31 , 0 ), // #382 - INST(Lldt , X86M_NoSize , O(000F00,00,2,_,_,_,_,_ ), 0 , 69 , 0 , 1816 , 98 , 0 ), // #383 - INST(Llwpcb , VexR_Wx , V(XOP_M9,12,0,0,x,_,_,_ ), 0 , 72 , 0 , 1821 , 99 , 69 ), // #384 - INST(Lmsw , X86M_NoSize , O(000F00,01,6,_,_,_,_,_ ), 0 , 73 , 0 , 1828 , 98 , 0 ), // #385 - INST(Lods , X86StrRm , O(000000,AC,_,_,_,_,_,_ ), 0 , 0 , 0 , 1833 , 100, 70 ), // #386 - INST(Loop , X86JecxzLoop , 0 , O(000000,E2,_,_,_,_,_,_ ), 0 , 40 , 1838 , 101, 0 ), // #387 - INST(Loope , X86JecxzLoop , 0 , O(000000,E1,_,_,_,_,_,_ ), 0 , 41 , 1843 , 101, 56 ), // #388 - INST(Loopne , X86JecxzLoop , 0 , O(000000,E0,_,_,_,_,_,_ ), 0 , 42 , 1849 , 101, 56 ), // #389 - INST(Lsl , X86Rm , O(000F00,03,_,_,_,_,_,_ ), 0 , 4 , 0 , 1856 , 102, 10 ), // #390 - INST(Lss , X86Rm , O(000F00,B2,_,_,_,_,_,_ ), 0 , 4 , 0 , 6477 , 97 , 0 ), // #391 - INST(Ltr , X86M_NoSize , O(000F00,00,3,_,_,_,_,_ ), 0 , 71 , 0 , 1860 , 98 , 0 ), // #392 - INST(Lwpins , VexVmi4_Wx , V(XOP_MA,12,0,0,x,_,_,_ ), 0 , 74 , 0 , 1864 , 103, 69 ), // #393 - INST(Lwpval , VexVmi4_Wx , V(XOP_MA,12,1,0,x,_,_,_ ), 0 , 75 , 0 , 1871 , 103, 69 ), // #394 - INST(Lzcnt , X86Rm_Raw66H , O(F30F00,BD,_,_,x,_,_,_ ), 0 , 6 , 0 , 1878 , 22 , 71 ), // #395 - INST(Maskmovdqu , ExtRm_ZDI , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 5995 , 104, 4 ), // #396 - INST(Maskmovq , ExtRm_ZDI , O(000F00,F7,_,_,_,_,_,_ ), 0 , 4 , 0 , 7994 , 105, 72 ), // #397 - INST(Maxpd , ExtRm , O(660F00,5F,_,_,_,_,_,_ ), 0 , 3 , 0 , 6029 , 5 , 4 ), // #398 - INST(Maxps , ExtRm , O(000F00,5F,_,_,_,_,_,_ ), 0 , 4 , 0 , 6036 , 5 , 5 ), // #399 - INST(Maxsd , ExtRm , O(F20F00,5F,_,_,_,_,_,_ ), 0 , 5 , 0 , 8013 , 6 , 4 ), // #400 - INST(Maxss , ExtRm , O(F30F00,5F,_,_,_,_,_,_ ), 0 , 6 , 0 , 6050 , 7 , 5 ), // #401 - INST(Mcommit , X86Op , O(F30F01,FA,_,_,_,_,_,_ ), 0 , 76 , 0 , 1884 , 30 , 73 ), // #402 - INST(Mfence , X86Fence , O(000F00,AE,6,_,_,_,_,_ ), 0 , 73 , 0 , 1892 , 30 , 4 ), // #403 - INST(Minpd , ExtRm , O(660F00,5D,_,_,_,_,_,_ ), 0 , 3 , 0 , 6079 , 5 , 4 ), // #404 - INST(Minps , ExtRm , O(000F00,5D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6086 , 5 , 5 ), // #405 - INST(Minsd , ExtRm , O(F20F00,5D,_,_,_,_,_,_ ), 0 , 5 , 0 , 8077 , 6 , 4 ), // #406 - INST(Minss , ExtRm , O(F30F00,5D,_,_,_,_,_,_ ), 0 , 6 , 0 , 6100 , 7 , 5 ), // #407 - INST(Monitor , X86Op , O(000F01,C8,_,_,_,_,_,_ ), 0 , 21 , 0 , 3092 , 106, 74 ), // #408 - INST(Monitorx , X86Op , O(000F01,FA,_,_,_,_,_,_ ), 0 , 21 , 0 , 1899 , 106, 75 ), // #409 - INST(Mov , X86Mov , 0 , 0 , 0 , 0 , 138 , 107, 0 ), // #410 - INST(Movapd , ExtMov , O(660F00,28,_,_,_,_,_,_ ), O(660F00,29,_,_,_,_,_,_ ), 3 , 43 , 6131 , 108, 4 ), // #411 - INST(Movaps , ExtMov , O(000F00,28,_,_,_,_,_,_ ), O(000F00,29,_,_,_,_,_,_ ), 4 , 44 , 6139 , 108, 5 ), // #412 - INST(Movbe , ExtMovbe , O(000F38,F0,_,_,x,_,_,_ ), O(000F38,F1,_,_,x,_,_,_ ), 77 , 45 , 626 , 109, 76 ), // #413 - INST(Movd , ExtMovd , O(000F00,6E,_,_,_,_,_,_ ), O(000F00,7E,_,_,_,_,_,_ ), 4 , 46 , 7987 , 110, 77 ), // #414 - INST(Movddup , ExtMov , O(F20F00,12,_,_,_,_,_,_ ), 0 , 5 , 0 , 6153 , 6 , 6 ), // #415 - INST(Movdir64b , X86EnqcmdMovdir64b , O(660F38,F8,_,_,_,_,_,_ ), 0 , 2 , 0 , 1908 , 111, 78 ), // #416 - INST(Movdiri , X86MovntiMovdiri , O(000F38,F9,_,_,_,_,_,_ ), 0 , 77 , 0 , 1918 , 112, 79 ), // #417 - INST(Movdq2q , ExtMov , O(F20F00,D6,_,_,_,_,_,_ ), 0 , 5 , 0 , 1926 , 113, 4 ), // #418 - INST(Movdqa , ExtMov , O(660F00,6F,_,_,_,_,_,_ ), O(660F00,7F,_,_,_,_,_,_ ), 3 , 47 , 6162 , 108, 4 ), // #419 - INST(Movdqu , ExtMov , O(F30F00,6F,_,_,_,_,_,_ ), O(F30F00,7F,_,_,_,_,_,_ ), 6 , 48 , 5999 , 108, 4 ), // #420 - INST(Movhlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), 0 , 4 , 0 , 6237 , 114, 5 ), // #421 - INST(Movhpd , ExtMov , O(660F00,16,_,_,_,_,_,_ ), O(660F00,17,_,_,_,_,_,_ ), 3 , 49 , 6246 , 115, 4 ), // #422 - INST(Movhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), O(000F00,17,_,_,_,_,_,_ ), 4 , 50 , 6254 , 115, 5 ), // #423 - INST(Movlhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), 0 , 4 , 0 , 6262 , 114, 5 ), // #424 - INST(Movlpd , ExtMov , O(660F00,12,_,_,_,_,_,_ ), O(660F00,13,_,_,_,_,_,_ ), 3 , 51 , 6271 , 115, 4 ), // #425 - INST(Movlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), O(000F00,13,_,_,_,_,_,_ ), 4 , 52 , 6279 , 115, 5 ), // #426 - INST(Movmskpd , ExtMov , O(660F00,50,_,_,_,_,_,_ ), 0 , 3 , 0 , 6287 , 116, 4 ), // #427 - INST(Movmskps , ExtMov , O(000F00,50,_,_,_,_,_,_ ), 0 , 4 , 0 , 6297 , 116, 5 ), // #428 - INST(Movntdq , ExtMov , 0 , O(660F00,E7,_,_,_,_,_,_ ), 0 , 53 , 6307 , 117, 4 ), // #429 - INST(Movntdqa , ExtMov , O(660F38,2A,_,_,_,_,_,_ ), 0 , 2 , 0 , 6316 , 92 , 12 ), // #430 - INST(Movnti , X86MovntiMovdiri , O(000F00,C3,_,_,x,_,_,_ ), 0 , 4 , 0 , 1934 , 112, 4 ), // #431 - INST(Movntpd , ExtMov , 0 , O(660F00,2B,_,_,_,_,_,_ ), 0 , 54 , 6326 , 117, 4 ), // #432 - INST(Movntps , ExtMov , 0 , O(000F00,2B,_,_,_,_,_,_ ), 0 , 55 , 6335 , 117, 5 ), // #433 - INST(Movntq , ExtMov , 0 , O(000F00,E7,_,_,_,_,_,_ ), 0 , 56 , 1941 , 118, 72 ), // #434 - INST(Movntsd , ExtMov , 0 , O(F20F00,2B,_,_,_,_,_,_ ), 0 , 57 , 1948 , 119, 46 ), // #435 - INST(Movntss , ExtMov , 0 , O(F30F00,2B,_,_,_,_,_,_ ), 0 , 58 , 1956 , 120, 46 ), // #436 - INST(Movq , ExtMovq , O(000F00,6E,_,_,x,_,_,_ ), O(000F00,7E,_,_,x,_,_,_ ), 4 , 59 , 7998 , 121, 77 ), // #437 - INST(Movq2dq , ExtRm , O(F30F00,D6,_,_,_,_,_,_ ), 0 , 6 , 0 , 1964 , 122, 4 ), // #438 - INST(Movs , X86StrMm , O(000000,A4,_,_,_,_,_,_ ), 0 , 0 , 0 , 425 , 123, 70 ), // #439 - INST(Movsd , ExtMov , O(F20F00,10,_,_,_,_,_,_ ), O(F20F00,11,_,_,_,_,_,_ ), 5 , 60 , 6350 , 124, 4 ), // #440 - INST(Movshdup , ExtRm , O(F30F00,16,_,_,_,_,_,_ ), 0 , 6 , 0 , 6357 , 5 , 6 ), // #441 - INST(Movsldup , ExtRm , O(F30F00,12,_,_,_,_,_,_ ), 0 , 6 , 0 , 6367 , 5 , 6 ), // #442 - INST(Movss , ExtMov , O(F30F00,10,_,_,_,_,_,_ ), O(F30F00,11,_,_,_,_,_,_ ), 6 , 61 , 6377 , 125, 5 ), // #443 - INST(Movsx , X86MovsxMovzx , O(000F00,BE,_,_,x,_,_,_ ), 0 , 4 , 0 , 1972 , 126, 0 ), // #444 - INST(Movsxd , X86Rm , O(000000,63,_,_,x,_,_,_ ), 0 , 0 , 0 , 1978 , 127, 0 ), // #445 - INST(Movupd , ExtMov , O(660F00,10,_,_,_,_,_,_ ), O(660F00,11,_,_,_,_,_,_ ), 3 , 62 , 6384 , 108, 4 ), // #446 - INST(Movups , ExtMov , O(000F00,10,_,_,_,_,_,_ ), O(000F00,11,_,_,_,_,_,_ ), 4 , 63 , 6392 , 108, 5 ), // #447 - INST(Movzx , X86MovsxMovzx , O(000F00,B6,_,_,x,_,_,_ ), 0 , 4 , 0 , 1985 , 126, 0 ), // #448 - INST(Mpsadbw , ExtRmi , O(660F3A,42,_,_,_,_,_,_ ), 0 , 8 , 0 , 6400 , 8 , 12 ), // #449 - INST(Mul , X86M_GPB_MulDiv , O(000000,F6,4,_,x,_,_,_ ), 0 , 9 , 0 , 798 , 52 , 1 ), // #450 - INST(Mulpd , ExtRm , O(660F00,59,_,_,_,_,_,_ ), 0 , 3 , 0 , 6454 , 5 , 4 ), // #451 - INST(Mulps , ExtRm , O(000F00,59,_,_,_,_,_,_ ), 0 , 4 , 0 , 6461 , 5 , 5 ), // #452 - INST(Mulsd , ExtRm , O(F20F00,59,_,_,_,_,_,_ ), 0 , 5 , 0 , 6468 , 6 , 4 ), // #453 - INST(Mulss , ExtRm , O(F30F00,59,_,_,_,_,_,_ ), 0 , 6 , 0 , 6475 , 7 , 5 ), // #454 - INST(Mulx , VexRvm_ZDX_Wx , V(F20F38,F6,_,0,x,_,_,_ ), 0 , 78 , 0 , 1991 , 128, 80 ), // #455 - INST(Mwait , X86Op , O(000F01,C9,_,_,_,_,_,_ ), 0 , 21 , 0 , 3101 , 129, 74 ), // #456 - INST(Mwaitx , X86Op , O(000F01,FB,_,_,_,_,_,_ ), 0 , 21 , 0 , 1996 , 130, 75 ), // #457 - INST(Neg , X86M_GPB , O(000000,F6,3,_,x,_,_,_ ), 0 , 79 , 0 , 2003 , 131, 1 ), // #458 - INST(Nop , X86M_Nop , O(000000,90,_,_,_,_,_,_ ), 0 , 0 , 0 , 929 , 132, 0 ), // #459 - INST(Not , X86M_GPB , O(000000,F6,2,_,x,_,_,_ ), 0 , 1 , 0 , 2007 , 131, 0 ), // #460 - INST(Or , X86Arith , O(000000,08,1,_,x,_,_,_ ), 0 , 29 , 0 , 3097 , 133, 1 ), // #461 - INST(Orpd , ExtRm , O(660F00,56,_,_,_,_,_,_ ), 0 , 3 , 0 , 10204, 11 , 4 ), // #462 - INST(Orps , ExtRm , O(000F00,56,_,_,_,_,_,_ ), 0 , 4 , 0 , 10211, 11 , 5 ), // #463 - INST(Out , X86Out , O(000000,EE,_,_,_,_,_,_ ), O(000000,E6,_,_,_,_,_,_ ), 0 , 64 , 2011 , 134, 0 ), // #464 - INST(Outs , X86Outs , O(000000,6E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2015 , 135, 0 ), // #465 - INST(Pabsb , ExtRm_P , O(000F38,1C,_,_,_,_,_,_ ), 0 , 77 , 0 , 6557 , 136, 81 ), // #466 - INST(Pabsd , ExtRm_P , O(000F38,1E,_,_,_,_,_,_ ), 0 , 77 , 0 , 6564 , 136, 81 ), // #467 - INST(Pabsw , ExtRm_P , O(000F38,1D,_,_,_,_,_,_ ), 0 , 77 , 0 , 6578 , 136, 81 ), // #468 - INST(Packssdw , ExtRm_P , O(000F00,6B,_,_,_,_,_,_ ), 0 , 4 , 0 , 6585 , 136, 77 ), // #469 - INST(Packsswb , ExtRm_P , O(000F00,63,_,_,_,_,_,_ ), 0 , 4 , 0 , 6595 , 136, 77 ), // #470 - INST(Packusdw , ExtRm , O(660F38,2B,_,_,_,_,_,_ ), 0 , 2 , 0 , 6605 , 5 , 12 ), // #471 - INST(Packuswb , ExtRm_P , O(000F00,67,_,_,_,_,_,_ ), 0 , 4 , 0 , 6615 , 136, 77 ), // #472 - INST(Paddb , ExtRm_P , O(000F00,FC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6625 , 136, 77 ), // #473 - INST(Paddd , ExtRm_P , O(000F00,FE,_,_,_,_,_,_ ), 0 , 4 , 0 , 6632 , 136, 77 ), // #474 - INST(Paddq , ExtRm_P , O(000F00,D4,_,_,_,_,_,_ ), 0 , 4 , 0 , 6639 , 136, 4 ), // #475 - INST(Paddsb , ExtRm_P , O(000F00,EC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6646 , 136, 77 ), // #476 - INST(Paddsw , ExtRm_P , O(000F00,ED,_,_,_,_,_,_ ), 0 , 4 , 0 , 6654 , 136, 77 ), // #477 - INST(Paddusb , ExtRm_P , O(000F00,DC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6662 , 136, 77 ), // #478 - INST(Paddusw , ExtRm_P , O(000F00,DD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6671 , 136, 77 ), // #479 - INST(Paddw , ExtRm_P , O(000F00,FD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6680 , 136, 77 ), // #480 - INST(Palignr , ExtRmi_P , O(000F3A,0F,_,_,_,_,_,_ ), 0 , 80 , 0 , 6687 , 137, 6 ), // #481 - INST(Pand , ExtRm_P , O(000F00,DB,_,_,_,_,_,_ ), 0 , 4 , 0 , 6696 , 138, 77 ), // #482 - INST(Pandn , ExtRm_P , O(000F00,DF,_,_,_,_,_,_ ), 0 , 4 , 0 , 6709 , 139, 77 ), // #483 - INST(Pause , X86Op , O(F30000,90,_,_,_,_,_,_ ), 0 , 81 , 0 , 3069 , 30 , 0 ), // #484 - INST(Pavgb , ExtRm_P , O(000F00,E0,_,_,_,_,_,_ ), 0 , 4 , 0 , 6739 , 136, 82 ), // #485 - INST(Pavgusb , Ext3dNow , O(000F0F,BF,_,_,_,_,_,_ ), 0 , 82 , 0 , 2020 , 140, 48 ), // #486 - INST(Pavgw , ExtRm_P , O(000F00,E3,_,_,_,_,_,_ ), 0 , 4 , 0 , 6746 , 136, 82 ), // #487 - INST(Pblendvb , ExtRm_XMM0 , O(660F38,10,_,_,_,_,_,_ ), 0 , 2 , 0 , 6762 , 15 , 12 ), // #488 - INST(Pblendw , ExtRmi , O(660F3A,0E,_,_,_,_,_,_ ), 0 , 8 , 0 , 6772 , 8 , 12 ), // #489 - INST(Pclmulqdq , ExtRmi , O(660F3A,44,_,_,_,_,_,_ ), 0 , 8 , 0 , 6865 , 8 , 83 ), // #490 - INST(Pcmpeqb , ExtRm_P , O(000F00,74,_,_,_,_,_,_ ), 0 , 4 , 0 , 6897 , 139, 77 ), // #491 - INST(Pcmpeqd , ExtRm_P , O(000F00,76,_,_,_,_,_,_ ), 0 , 4 , 0 , 6906 , 139, 77 ), // #492 - INST(Pcmpeqq , ExtRm , O(660F38,29,_,_,_,_,_,_ ), 0 , 2 , 0 , 6915 , 141, 12 ), // #493 - INST(Pcmpeqw , ExtRm_P , O(000F00,75,_,_,_,_,_,_ ), 0 , 4 , 0 , 6924 , 139, 77 ), // #494 - INST(Pcmpestri , ExtRmi , O(660F3A,61,_,_,_,_,_,_ ), 0 , 8 , 0 , 6933 , 142, 84 ), // #495 - INST(Pcmpestrm , ExtRmi , O(660F3A,60,_,_,_,_,_,_ ), 0 , 8 , 0 , 6944 , 143, 84 ), // #496 - INST(Pcmpgtb , ExtRm_P , O(000F00,64,_,_,_,_,_,_ ), 0 , 4 , 0 , 6955 , 139, 77 ), // #497 - INST(Pcmpgtd , ExtRm_P , O(000F00,66,_,_,_,_,_,_ ), 0 , 4 , 0 , 6964 , 139, 77 ), // #498 - INST(Pcmpgtq , ExtRm , O(660F38,37,_,_,_,_,_,_ ), 0 , 2 , 0 , 6973 , 141, 42 ), // #499 - INST(Pcmpgtw , ExtRm_P , O(000F00,65,_,_,_,_,_,_ ), 0 , 4 , 0 , 6982 , 139, 77 ), // #500 - INST(Pcmpistri , ExtRmi , O(660F3A,63,_,_,_,_,_,_ ), 0 , 8 , 0 , 6991 , 144, 84 ), // #501 - INST(Pcmpistrm , ExtRmi , O(660F3A,62,_,_,_,_,_,_ ), 0 , 8 , 0 , 7002 , 145, 84 ), // #502 - INST(Pcommit , X86Op_O , O(660F00,AE,7,_,_,_,_,_ ), 0 , 23 , 0 , 2028 , 30 , 85 ), // #503 - INST(Pconfig , X86Op , O(000F01,C5,_,_,_,_,_,_ ), 0 , 21 , 0 , 2036 , 30 , 86 ), // #504 - INST(Pdep , VexRvm_Wx , V(F20F38,F5,_,0,x,_,_,_ ), 0 , 78 , 0 , 2044 , 10 , 80 ), // #505 - INST(Pext , VexRvm_Wx , V(F30F38,F5,_,0,x,_,_,_ ), 0 , 83 , 0 , 2049 , 10 , 80 ), // #506 - INST(Pextrb , ExtExtract , O(000F3A,14,_,_,_,_,_,_ ), 0 , 80 , 0 , 7489 , 146, 12 ), // #507 - INST(Pextrd , ExtExtract , O(000F3A,16,_,_,_,_,_,_ ), 0 , 80 , 0 , 7497 , 56 , 12 ), // #508 - INST(Pextrq , ExtExtract , O(000F3A,16,_,_,1,_,_,_ ), 0 , 84 , 0 , 7505 , 147, 12 ), // #509 - INST(Pextrw , ExtPextrw , O(000F00,C5,_,_,_,_,_,_ ), O(000F3A,15,_,_,_,_,_,_ ), 4 , 65 , 7513 , 148, 87 ), // #510 - INST(Pf2id , Ext3dNow , O(000F0F,1D,_,_,_,_,_,_ ), 0 , 82 , 0 , 2054 , 140, 48 ), // #511 - INST(Pf2iw , Ext3dNow , O(000F0F,1C,_,_,_,_,_,_ ), 0 , 82 , 0 , 2060 , 140, 88 ), // #512 - INST(Pfacc , Ext3dNow , O(000F0F,AE,_,_,_,_,_,_ ), 0 , 82 , 0 , 2066 , 140, 48 ), // #513 - INST(Pfadd , Ext3dNow , O(000F0F,9E,_,_,_,_,_,_ ), 0 , 82 , 0 , 2072 , 140, 48 ), // #514 - INST(Pfcmpeq , Ext3dNow , O(000F0F,B0,_,_,_,_,_,_ ), 0 , 82 , 0 , 2078 , 140, 48 ), // #515 - INST(Pfcmpge , Ext3dNow , O(000F0F,90,_,_,_,_,_,_ ), 0 , 82 , 0 , 2086 , 140, 48 ), // #516 - INST(Pfcmpgt , Ext3dNow , O(000F0F,A0,_,_,_,_,_,_ ), 0 , 82 , 0 , 2094 , 140, 48 ), // #517 - INST(Pfmax , Ext3dNow , O(000F0F,A4,_,_,_,_,_,_ ), 0 , 82 , 0 , 2102 , 140, 48 ), // #518 - INST(Pfmin , Ext3dNow , O(000F0F,94,_,_,_,_,_,_ ), 0 , 82 , 0 , 2108 , 140, 48 ), // #519 - INST(Pfmul , Ext3dNow , O(000F0F,B4,_,_,_,_,_,_ ), 0 , 82 , 0 , 2114 , 140, 48 ), // #520 - INST(Pfnacc , Ext3dNow , O(000F0F,8A,_,_,_,_,_,_ ), 0 , 82 , 0 , 2120 , 140, 88 ), // #521 - INST(Pfpnacc , Ext3dNow , O(000F0F,8E,_,_,_,_,_,_ ), 0 , 82 , 0 , 2127 , 140, 88 ), // #522 - INST(Pfrcp , Ext3dNow , O(000F0F,96,_,_,_,_,_,_ ), 0 , 82 , 0 , 2135 , 140, 48 ), // #523 - INST(Pfrcpit1 , Ext3dNow , O(000F0F,A6,_,_,_,_,_,_ ), 0 , 82 , 0 , 2141 , 140, 48 ), // #524 - INST(Pfrcpit2 , Ext3dNow , O(000F0F,B6,_,_,_,_,_,_ ), 0 , 82 , 0 , 2150 , 140, 48 ), // #525 - INST(Pfrcpv , Ext3dNow , O(000F0F,86,_,_,_,_,_,_ ), 0 , 82 , 0 , 2159 , 140, 89 ), // #526 - INST(Pfrsqit1 , Ext3dNow , O(000F0F,A7,_,_,_,_,_,_ ), 0 , 82 , 0 , 2166 , 140, 48 ), // #527 - INST(Pfrsqrt , Ext3dNow , O(000F0F,97,_,_,_,_,_,_ ), 0 , 82 , 0 , 2175 , 140, 48 ), // #528 - INST(Pfrsqrtv , Ext3dNow , O(000F0F,87,_,_,_,_,_,_ ), 0 , 82 , 0 , 2183 , 140, 89 ), // #529 - INST(Pfsub , Ext3dNow , O(000F0F,9A,_,_,_,_,_,_ ), 0 , 82 , 0 , 2192 , 140, 48 ), // #530 - INST(Pfsubr , Ext3dNow , O(000F0F,AA,_,_,_,_,_,_ ), 0 , 82 , 0 , 2198 , 140, 48 ), // #531 - INST(Phaddd , ExtRm_P , O(000F38,02,_,_,_,_,_,_ ), 0 , 77 , 0 , 7592 , 136, 81 ), // #532 - INST(Phaddsw , ExtRm_P , O(000F38,03,_,_,_,_,_,_ ), 0 , 77 , 0 , 7609 , 136, 81 ), // #533 - INST(Phaddw , ExtRm_P , O(000F38,01,_,_,_,_,_,_ ), 0 , 77 , 0 , 7678 , 136, 81 ), // #534 - INST(Phminposuw , ExtRm , O(660F38,41,_,_,_,_,_,_ ), 0 , 2 , 0 , 7704 , 5 , 12 ), // #535 - INST(Phsubd , ExtRm_P , O(000F38,06,_,_,_,_,_,_ ), 0 , 77 , 0 , 7725 , 136, 81 ), // #536 - INST(Phsubsw , ExtRm_P , O(000F38,07,_,_,_,_,_,_ ), 0 , 77 , 0 , 7742 , 136, 81 ), // #537 - INST(Phsubw , ExtRm_P , O(000F38,05,_,_,_,_,_,_ ), 0 , 77 , 0 , 7751 , 136, 81 ), // #538 - INST(Pi2fd , Ext3dNow , O(000F0F,0D,_,_,_,_,_,_ ), 0 , 82 , 0 , 2205 , 140, 48 ), // #539 - INST(Pi2fw , Ext3dNow , O(000F0F,0C,_,_,_,_,_,_ ), 0 , 82 , 0 , 2211 , 140, 88 ), // #540 - INST(Pinsrb , ExtRmi , O(660F3A,20,_,_,_,_,_,_ ), 0 , 8 , 0 , 7768 , 149, 12 ), // #541 - INST(Pinsrd , ExtRmi , O(660F3A,22,_,_,_,_,_,_ ), 0 , 8 , 0 , 7776 , 150, 12 ), // #542 - INST(Pinsrq , ExtRmi , O(660F3A,22,_,_,1,_,_,_ ), 0 , 85 , 0 , 7784 , 151, 12 ), // #543 - INST(Pinsrw , ExtRmi_P , O(000F00,C4,_,_,_,_,_,_ ), 0 , 4 , 0 , 7792 , 152, 82 ), // #544 - INST(Pmaddubsw , ExtRm_P , O(000F38,04,_,_,_,_,_,_ ), 0 , 77 , 0 , 7962 , 136, 81 ), // #545 - INST(Pmaddwd , ExtRm_P , O(000F00,F5,_,_,_,_,_,_ ), 0 , 4 , 0 , 7973 , 136, 77 ), // #546 - INST(Pmaxsb , ExtRm , O(660F38,3C,_,_,_,_,_,_ ), 0 , 2 , 0 , 8004 , 11 , 12 ), // #547 - INST(Pmaxsd , ExtRm , O(660F38,3D,_,_,_,_,_,_ ), 0 , 2 , 0 , 8012 , 11 , 12 ), // #548 - INST(Pmaxsw , ExtRm_P , O(000F00,EE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8028 , 138, 82 ), // #549 - INST(Pmaxub , ExtRm_P , O(000F00,DE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8036 , 138, 82 ), // #550 - INST(Pmaxud , ExtRm , O(660F38,3F,_,_,_,_,_,_ ), 0 , 2 , 0 , 8044 , 11 , 12 ), // #551 - INST(Pmaxuw , ExtRm , O(660F38,3E,_,_,_,_,_,_ ), 0 , 2 , 0 , 8060 , 11 , 12 ), // #552 - INST(Pminsb , ExtRm , O(660F38,38,_,_,_,_,_,_ ), 0 , 2 , 0 , 8068 , 11 , 12 ), // #553 - INST(Pminsd , ExtRm , O(660F38,39,_,_,_,_,_,_ ), 0 , 2 , 0 , 8076 , 11 , 12 ), // #554 - INST(Pminsw , ExtRm_P , O(000F00,EA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8092 , 138, 82 ), // #555 - INST(Pminub , ExtRm_P , O(000F00,DA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8100 , 138, 82 ), // #556 - INST(Pminud , ExtRm , O(660F38,3B,_,_,_,_,_,_ ), 0 , 2 , 0 , 8108 , 11 , 12 ), // #557 - INST(Pminuw , ExtRm , O(660F38,3A,_,_,_,_,_,_ ), 0 , 2 , 0 , 8124 , 11 , 12 ), // #558 - INST(Pmovmskb , ExtRm_P , O(000F00,D7,_,_,_,_,_,_ ), 0 , 4 , 0 , 8202 , 153, 82 ), // #559 - INST(Pmovsxbd , ExtRm , O(660F38,21,_,_,_,_,_,_ ), 0 , 2 , 0 , 8299 , 7 , 12 ), // #560 - INST(Pmovsxbq , ExtRm , O(660F38,22,_,_,_,_,_,_ ), 0 , 2 , 0 , 8309 , 154, 12 ), // #561 - INST(Pmovsxbw , ExtRm , O(660F38,20,_,_,_,_,_,_ ), 0 , 2 , 0 , 8319 , 6 , 12 ), // #562 - INST(Pmovsxdq , ExtRm , O(660F38,25,_,_,_,_,_,_ ), 0 , 2 , 0 , 8329 , 6 , 12 ), // #563 - INST(Pmovsxwd , ExtRm , O(660F38,23,_,_,_,_,_,_ ), 0 , 2 , 0 , 8339 , 6 , 12 ), // #564 - INST(Pmovsxwq , ExtRm , O(660F38,24,_,_,_,_,_,_ ), 0 , 2 , 0 , 8349 , 7 , 12 ), // #565 - INST(Pmovzxbd , ExtRm , O(660F38,31,_,_,_,_,_,_ ), 0 , 2 , 0 , 8436 , 7 , 12 ), // #566 - INST(Pmovzxbq , ExtRm , O(660F38,32,_,_,_,_,_,_ ), 0 , 2 , 0 , 8446 , 154, 12 ), // #567 - INST(Pmovzxbw , ExtRm , O(660F38,30,_,_,_,_,_,_ ), 0 , 2 , 0 , 8456 , 6 , 12 ), // #568 - INST(Pmovzxdq , ExtRm , O(660F38,35,_,_,_,_,_,_ ), 0 , 2 , 0 , 8466 , 6 , 12 ), // #569 - INST(Pmovzxwd , ExtRm , O(660F38,33,_,_,_,_,_,_ ), 0 , 2 , 0 , 8476 , 6 , 12 ), // #570 - INST(Pmovzxwq , ExtRm , O(660F38,34,_,_,_,_,_,_ ), 0 , 2 , 0 , 8486 , 7 , 12 ), // #571 - INST(Pmuldq , ExtRm , O(660F38,28,_,_,_,_,_,_ ), 0 , 2 , 0 , 8496 , 5 , 12 ), // #572 - INST(Pmulhrsw , ExtRm_P , O(000F38,0B,_,_,_,_,_,_ ), 0 , 77 , 0 , 8504 , 136, 81 ), // #573 - INST(Pmulhrw , Ext3dNow , O(000F0F,B7,_,_,_,_,_,_ ), 0 , 82 , 0 , 2217 , 140, 48 ), // #574 - INST(Pmulhuw , ExtRm_P , O(000F00,E4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8514 , 136, 82 ), // #575 - INST(Pmulhw , ExtRm_P , O(000F00,E5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8523 , 136, 77 ), // #576 - INST(Pmulld , ExtRm , O(660F38,40,_,_,_,_,_,_ ), 0 , 2 , 0 , 8531 , 5 , 12 ), // #577 - INST(Pmullw , ExtRm_P , O(000F00,D5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8547 , 136, 77 ), // #578 - INST(Pmuludq , ExtRm_P , O(000F00,F4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8570 , 136, 4 ), // #579 - INST(Pop , X86Pop , O(000000,8F,0,_,_,_,_,_ ), O(000000,58,_,_,_,_,_,_ ), 0 , 66 , 2225 , 155, 0 ), // #580 - INST(Popa , X86Op , O(660000,61,_,_,_,_,_,_ ), 0 , 19 , 0 , 2229 , 75 , 0 ), // #581 - INST(Popad , X86Op , O(000000,61,_,_,_,_,_,_ ), 0 , 0 , 0 , 2234 , 75 , 0 ), // #582 - INST(Popcnt , X86Rm_Raw66H , O(F30F00,B8,_,_,x,_,_,_ ), 0 , 6 , 0 , 2240 , 22 , 90 ), // #583 - INST(Popf , X86Op , O(660000,9D,_,_,_,_,_,_ ), 0 , 19 , 0 , 2247 , 30 , 91 ), // #584 - INST(Popfd , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2252 , 75 , 91 ), // #585 - INST(Popfq , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2258 , 156, 91 ), // #586 - INST(Por , ExtRm_P , O(000F00,EB,_,_,_,_,_,_ ), 0 , 4 , 0 , 8615 , 138, 77 ), // #587 - INST(Prefetch , X86M_Only , O(000F00,0D,0,_,_,_,_,_ ), 0 , 4 , 0 , 2264 , 31 , 48 ), // #588 - INST(Prefetchnta , X86M_Only , O(000F00,18,0,_,_,_,_,_ ), 0 , 4 , 0 , 2273 , 31 , 72 ), // #589 - INST(Prefetcht0 , X86M_Only , O(000F00,18,1,_,_,_,_,_ ), 0 , 27 , 0 , 2285 , 31 , 72 ), // #590 - INST(Prefetcht1 , X86M_Only , O(000F00,18,2,_,_,_,_,_ ), 0 , 69 , 0 , 2296 , 31 , 72 ), // #591 - INST(Prefetcht2 , X86M_Only , O(000F00,18,3,_,_,_,_,_ ), 0 , 71 , 0 , 2307 , 31 , 72 ), // #592 - INST(Prefetchw , X86M_Only , O(000F00,0D,1,_,_,_,_,_ ), 0 , 27 , 0 , 2318 , 31 , 92 ), // #593 - INST(Prefetchwt1 , X86M_Only , O(000F00,0D,2,_,_,_,_,_ ), 0 , 69 , 0 , 2328 , 31 , 93 ), // #594 - INST(Psadbw , ExtRm_P , O(000F00,F6,_,_,_,_,_,_ ), 0 , 4 , 0 , 4168 , 136, 82 ), // #595 - INST(Pshufb , ExtRm_P , O(000F38,00,_,_,_,_,_,_ ), 0 , 77 , 0 , 8941 , 136, 81 ), // #596 - INST(Pshufd , ExtRmi , O(660F00,70,_,_,_,_,_,_ ), 0 , 3 , 0 , 8962 , 8 , 4 ), // #597 - INST(Pshufhw , ExtRmi , O(F30F00,70,_,_,_,_,_,_ ), 0 , 6 , 0 , 8970 , 8 , 4 ), // #598 - INST(Pshuflw , ExtRmi , O(F20F00,70,_,_,_,_,_,_ ), 0 , 5 , 0 , 8979 , 8 , 4 ), // #599 - INST(Pshufw , ExtRmi_P , O(000F00,70,_,_,_,_,_,_ ), 0 , 4 , 0 , 2340 , 157, 72 ), // #600 - INST(Psignb , ExtRm_P , O(000F38,08,_,_,_,_,_,_ ), 0 , 77 , 0 , 8988 , 136, 81 ), // #601 - INST(Psignd , ExtRm_P , O(000F38,0A,_,_,_,_,_,_ ), 0 , 77 , 0 , 8996 , 136, 81 ), // #602 - INST(Psignw , ExtRm_P , O(000F38,09,_,_,_,_,_,_ ), 0 , 77 , 0 , 9004 , 136, 81 ), // #603 - INST(Pslld , ExtRmRi_P , O(000F00,F2,_,_,_,_,_,_ ), O(000F00,72,6,_,_,_,_,_ ), 4 , 67 , 9012 , 158, 77 ), // #604 - INST(Pslldq , ExtRmRi , 0 , O(660F00,73,7,_,_,_,_,_ ), 0 , 68 , 9019 , 159, 4 ), // #605 - INST(Psllq , ExtRmRi_P , O(000F00,F3,_,_,_,_,_,_ ), O(000F00,73,6,_,_,_,_,_ ), 4 , 69 , 9027 , 158, 77 ), // #606 - INST(Psllw , ExtRmRi_P , O(000F00,F1,_,_,_,_,_,_ ), O(000F00,71,6,_,_,_,_,_ ), 4 , 70 , 9058 , 158, 77 ), // #607 - INST(Psmash , X86Op , O(F30F01,FF,_,_,_,_,_,_ ), 0 , 76 , 0 , 2347 , 156, 94 ), // #608 - INST(Psrad , ExtRmRi_P , O(000F00,E2,_,_,_,_,_,_ ), O(000F00,72,4,_,_,_,_,_ ), 4 , 71 , 9065 , 158, 77 ), // #609 - INST(Psraw , ExtRmRi_P , O(000F00,E1,_,_,_,_,_,_ ), O(000F00,71,4,_,_,_,_,_ ), 4 , 72 , 9103 , 158, 77 ), // #610 - INST(Psrld , ExtRmRi_P , O(000F00,D2,_,_,_,_,_,_ ), O(000F00,72,2,_,_,_,_,_ ), 4 , 73 , 9110 , 158, 77 ), // #611 - INST(Psrldq , ExtRmRi , 0 , O(660F00,73,3,_,_,_,_,_ ), 0 , 74 , 9117 , 159, 4 ), // #612 - INST(Psrlq , ExtRmRi_P , O(000F00,D3,_,_,_,_,_,_ ), O(000F00,73,2,_,_,_,_,_ ), 4 , 75 , 9125 , 158, 77 ), // #613 - INST(Psrlw , ExtRmRi_P , O(000F00,D1,_,_,_,_,_,_ ), O(000F00,71,2,_,_,_,_,_ ), 4 , 76 , 9156 , 158, 77 ), // #614 - INST(Psubb , ExtRm_P , O(000F00,F8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9163 , 139, 77 ), // #615 - INST(Psubd , ExtRm_P , O(000F00,FA,_,_,_,_,_,_ ), 0 , 4 , 0 , 9170 , 139, 77 ), // #616 - INST(Psubq , ExtRm_P , O(000F00,FB,_,_,_,_,_,_ ), 0 , 4 , 0 , 9177 , 139, 4 ), // #617 - INST(Psubsb , ExtRm_P , O(000F00,E8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9184 , 139, 77 ), // #618 - INST(Psubsw , ExtRm_P , O(000F00,E9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9192 , 139, 77 ), // #619 - INST(Psubusb , ExtRm_P , O(000F00,D8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9200 , 139, 77 ), // #620 - INST(Psubusw , ExtRm_P , O(000F00,D9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9209 , 139, 77 ), // #621 - INST(Psubw , ExtRm_P , O(000F00,F9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9218 , 139, 77 ), // #622 - INST(Pswapd , Ext3dNow , O(000F0F,BB,_,_,_,_,_,_ ), 0 , 82 , 0 , 2354 , 140, 88 ), // #623 - INST(Ptest , ExtRm , O(660F38,17,_,_,_,_,_,_ ), 0 , 2 , 0 , 9247 , 5 , 95 ), // #624 - INST(Punpckhbw , ExtRm_P , O(000F00,68,_,_,_,_,_,_ ), 0 , 4 , 0 , 9330 , 136, 77 ), // #625 - INST(Punpckhdq , ExtRm_P , O(000F00,6A,_,_,_,_,_,_ ), 0 , 4 , 0 , 9341 , 136, 77 ), // #626 - INST(Punpckhqdq , ExtRm , O(660F00,6D,_,_,_,_,_,_ ), 0 , 3 , 0 , 9352 , 5 , 4 ), // #627 - INST(Punpckhwd , ExtRm_P , O(000F00,69,_,_,_,_,_,_ ), 0 , 4 , 0 , 9364 , 136, 77 ), // #628 - INST(Punpcklbw , ExtRm_P , O(000F00,60,_,_,_,_,_,_ ), 0 , 4 , 0 , 9375 , 136, 77 ), // #629 - INST(Punpckldq , ExtRm_P , O(000F00,62,_,_,_,_,_,_ ), 0 , 4 , 0 , 9386 , 136, 77 ), // #630 - INST(Punpcklqdq , ExtRm , O(660F00,6C,_,_,_,_,_,_ ), 0 , 3 , 0 , 9397 , 5 , 4 ), // #631 - INST(Punpcklwd , ExtRm_P , O(000F00,61,_,_,_,_,_,_ ), 0 , 4 , 0 , 9409 , 136, 77 ), // #632 - INST(Push , X86Push , O(000000,FF,6,_,_,_,_,_ ), O(000000,50,_,_,_,_,_,_ ), 30 , 77 , 2361 , 160, 0 ), // #633 - INST(Pusha , X86Op , O(660000,60,_,_,_,_,_,_ ), 0 , 19 , 0 , 2366 , 75 , 0 ), // #634 - INST(Pushad , X86Op , O(000000,60,_,_,_,_,_,_ ), 0 , 0 , 0 , 2372 , 75 , 0 ), // #635 - INST(Pushf , X86Op , O(660000,9C,_,_,_,_,_,_ ), 0 , 19 , 0 , 2379 , 30 , 96 ), // #636 - INST(Pushfd , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2385 , 75 , 96 ), // #637 - INST(Pushfq , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2392 , 156, 96 ), // #638 - INST(Pvalidate , X86Op , O(F20F01,FF,_,_,_,_,_,_ ), 0 , 86 , 0 , 2399 , 30 , 97 ), // #639 - INST(Pxor , ExtRm_P , O(000F00,EF,_,_,_,_,_,_ ), 0 , 4 , 0 , 9420 , 139, 77 ), // #640 - INST(Rcl , X86Rot , O(000000,D0,2,_,x,_,_,_ ), 0 , 1 , 0 , 2409 , 161, 98 ), // #641 - INST(Rcpps , ExtRm , O(000F00,53,_,_,_,_,_,_ ), 0 , 4 , 0 , 9548 , 5 , 5 ), // #642 - INST(Rcpss , ExtRm , O(F30F00,53,_,_,_,_,_,_ ), 0 , 6 , 0 , 9555 , 7 , 5 ), // #643 - INST(Rcr , X86Rot , O(000000,D0,3,_,x,_,_,_ ), 0 , 79 , 0 , 2413 , 161, 98 ), // #644 - INST(Rdfsbase , X86M , O(F30F00,AE,0,_,x,_,_,_ ), 0 , 6 , 0 , 2417 , 162, 99 ), // #645 - INST(Rdgsbase , X86M , O(F30F00,AE,1,_,x,_,_,_ ), 0 , 87 , 0 , 2426 , 162, 99 ), // #646 - INST(Rdmsr , X86Op , O(000F00,32,_,_,_,_,_,_ ), 0 , 4 , 0 , 2435 , 163, 100), // #647 - INST(Rdpid , X86R_Native , O(F30F00,C7,7,_,_,_,_,_ ), 0 , 88 , 0 , 2441 , 164, 101), // #648 - INST(Rdpmc , X86Op , O(000F00,33,_,_,_,_,_,_ ), 0 , 4 , 0 , 2447 , 163, 0 ), // #649 - INST(Rdpru , X86Op , O(000F01,FD,_,_,_,_,_,_ ), 0 , 21 , 0 , 2453 , 165, 102), // #650 - INST(Rdrand , X86M , O(000F00,C7,6,_,x,_,_,_ ), 0 , 73 , 0 , 2459 , 23 , 103), // #651 - INST(Rdseed , X86M , O(000F00,C7,7,_,x,_,_,_ ), 0 , 22 , 0 , 2466 , 23 , 104), // #652 - INST(Rdtsc , X86Op , O(000F00,31,_,_,_,_,_,_ ), 0 , 4 , 0 , 2473 , 28 , 105), // #653 - INST(Rdtscp , X86Op , O(000F01,F9,_,_,_,_,_,_ ), 0 , 21 , 0 , 2479 , 163, 106), // #654 - INST(Ret , X86Ret , O(000000,C2,_,_,_,_,_,_ ), 0 , 0 , 0 , 2952 , 166, 0 ), // #655 - INST(Rmpadjust , X86Op , O(F30F01,FE,_,_,_,_,_,_ ), 0 , 76 , 0 , 2486 , 156, 94 ), // #656 - INST(Rmpupdate , X86Op , O(F20F01,FE,_,_,_,_,_,_ ), 0 , 86 , 0 , 2496 , 156, 94 ), // #657 - INST(Rol , X86Rot , O(000000,D0,0,_,x,_,_,_ ), 0 , 0 , 0 , 2506 , 161, 107), // #658 - INST(Ror , X86Rot , O(000000,D0,1,_,x,_,_,_ ), 0 , 29 , 0 , 2510 , 161, 107), // #659 - INST(Rorx , VexRmi_Wx , V(F20F3A,F0,_,0,x,_,_,_ ), 0 , 89 , 0 , 2514 , 167, 80 ), // #660 - INST(Roundpd , ExtRmi , O(660F3A,09,_,_,_,_,_,_ ), 0 , 8 , 0 , 9650 , 8 , 12 ), // #661 - INST(Roundps , ExtRmi , O(660F3A,08,_,_,_,_,_,_ ), 0 , 8 , 0 , 9659 , 8 , 12 ), // #662 - INST(Roundsd , ExtRmi , O(660F3A,0B,_,_,_,_,_,_ ), 0 , 8 , 0 , 9668 , 35 , 12 ), // #663 - INST(Roundss , ExtRmi , O(660F3A,0A,_,_,_,_,_,_ ), 0 , 8 , 0 , 9677 , 36 , 12 ), // #664 - INST(Rsm , X86Op , O(000F00,AA,_,_,_,_,_,_ ), 0 , 4 , 0 , 2519 , 75 , 1 ), // #665 - INST(Rsqrtps , ExtRm , O(000F00,52,_,_,_,_,_,_ ), 0 , 4 , 0 , 9774 , 5 , 5 ), // #666 - INST(Rsqrtss , ExtRm , O(F30F00,52,_,_,_,_,_,_ ), 0 , 6 , 0 , 9783 , 7 , 5 ), // #667 - INST(Sahf , X86Op , O(000000,9E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2523 , 90 , 108), // #668 - INST(Sal , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2528 , 161, 1 ), // #669 - INST(Sar , X86Rot , O(000000,D0,7,_,x,_,_,_ ), 0 , 25 , 0 , 2532 , 161, 1 ), // #670 - INST(Sarx , VexRmv_Wx , V(F30F38,F7,_,0,x,_,_,_ ), 0 , 83 , 0 , 2536 , 13 , 80 ), // #671 - INST(Sbb , X86Arith , O(000000,18,3,_,x,_,_,_ ), 0 , 79 , 0 , 2541 , 168, 2 ), // #672 - INST(Scas , X86StrRm , O(000000,AE,_,_,_,_,_,_ ), 0 , 0 , 0 , 2545 , 169, 35 ), // #673 - INST(Serialize , X86Op , O(000F01,E8,_,_,_,_,_,_ ), 0 , 21 , 0 , 2550 , 30 , 109), // #674 - INST(Seta , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2560 , 170, 54 ), // #675 - INST(Setae , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2565 , 170, 55 ), // #676 - INST(Setb , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2571 , 170, 55 ), // #677 - INST(Setbe , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2576 , 170, 54 ), // #678 - INST(Setc , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2582 , 170, 55 ), // #679 - INST(Sete , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2587 , 170, 56 ), // #680 - INST(Setg , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2592 , 170, 57 ), // #681 - INST(Setge , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2597 , 170, 58 ), // #682 - INST(Setl , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2603 , 170, 58 ), // #683 - INST(Setle , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2608 , 170, 57 ), // #684 - INST(Setna , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2614 , 170, 54 ), // #685 - INST(Setnae , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2620 , 170, 55 ), // #686 - INST(Setnb , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2627 , 170, 55 ), // #687 - INST(Setnbe , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2633 , 170, 54 ), // #688 - INST(Setnc , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2640 , 170, 55 ), // #689 - INST(Setne , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2646 , 170, 56 ), // #690 - INST(Setng , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2652 , 170, 57 ), // #691 - INST(Setnge , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2658 , 170, 58 ), // #692 - INST(Setnl , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2665 , 170, 58 ), // #693 - INST(Setnle , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2671 , 170, 57 ), // #694 - INST(Setno , X86Set , O(000F00,91,_,_,_,_,_,_ ), 0 , 4 , 0 , 2678 , 170, 52 ), // #695 - INST(Setnp , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2684 , 170, 59 ), // #696 - INST(Setns , X86Set , O(000F00,99,_,_,_,_,_,_ ), 0 , 4 , 0 , 2690 , 170, 60 ), // #697 - INST(Setnz , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2696 , 170, 56 ), // #698 - INST(Seto , X86Set , O(000F00,90,_,_,_,_,_,_ ), 0 , 4 , 0 , 2702 , 170, 52 ), // #699 - INST(Setp , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2707 , 170, 59 ), // #700 - INST(Setpe , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2712 , 170, 59 ), // #701 - INST(Setpo , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2718 , 170, 59 ), // #702 - INST(Sets , X86Set , O(000F00,98,_,_,_,_,_,_ ), 0 , 4 , 0 , 2724 , 170, 60 ), // #703 - INST(Setz , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2729 , 170, 56 ), // #704 - INST(Sfence , X86Fence , O(000F00,AE,7,_,_,_,_,_ ), 0 , 22 , 0 , 2734 , 30 , 72 ), // #705 - INST(Sgdt , X86M_Only , O(000F00,01,0,_,_,_,_,_ ), 0 , 4 , 0 , 2741 , 31 , 0 ), // #706 - INST(Sha1msg1 , ExtRm , O(000F38,C9,_,_,_,_,_,_ ), 0 , 77 , 0 , 2746 , 5 , 110), // #707 - INST(Sha1msg2 , ExtRm , O(000F38,CA,_,_,_,_,_,_ ), 0 , 77 , 0 , 2755 , 5 , 110), // #708 - INST(Sha1nexte , ExtRm , O(000F38,C8,_,_,_,_,_,_ ), 0 , 77 , 0 , 2764 , 5 , 110), // #709 - INST(Sha1rnds4 , ExtRmi , O(000F3A,CC,_,_,_,_,_,_ ), 0 , 80 , 0 , 2774 , 8 , 110), // #710 - INST(Sha256msg1 , ExtRm , O(000F38,CC,_,_,_,_,_,_ ), 0 , 77 , 0 , 2784 , 5 , 110), // #711 - INST(Sha256msg2 , ExtRm , O(000F38,CD,_,_,_,_,_,_ ), 0 , 77 , 0 , 2795 , 5 , 110), // #712 - INST(Sha256rnds2 , ExtRm_XMM0 , O(000F38,CB,_,_,_,_,_,_ ), 0 , 77 , 0 , 2806 , 15 , 110), // #713 - INST(Shl , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2818 , 161, 1 ), // #714 - INST(Shld , X86ShldShrd , O(000F00,A4,_,_,x,_,_,_ ), 0 , 4 , 0 , 8819 , 171, 1 ), // #715 - INST(Shlx , VexRmv_Wx , V(660F38,F7,_,0,x,_,_,_ ), 0 , 90 , 0 , 2822 , 13 , 80 ), // #716 - INST(Shr , X86Rot , O(000000,D0,5,_,x,_,_,_ ), 0 , 58 , 0 , 2827 , 161, 1 ), // #717 - INST(Shrd , X86ShldShrd , O(000F00,AC,_,_,x,_,_,_ ), 0 , 4 , 0 , 2831 , 171, 1 ), // #718 - INST(Shrx , VexRmv_Wx , V(F20F38,F7,_,0,x,_,_,_ ), 0 , 78 , 0 , 2836 , 13 , 80 ), // #719 - INST(Shufpd , ExtRmi , O(660F00,C6,_,_,_,_,_,_ ), 0 , 3 , 0 , 10044, 8 , 4 ), // #720 - INST(Shufps , ExtRmi , O(000F00,C6,_,_,_,_,_,_ ), 0 , 4 , 0 , 10052, 8 , 5 ), // #721 - INST(Sidt , X86M_Only , O(000F00,01,1,_,_,_,_,_ ), 0 , 27 , 0 , 2841 , 31 , 0 ), // #722 - INST(Skinit , X86Op_xAX , O(000F01,DE,_,_,_,_,_,_ ), 0 , 21 , 0 , 2846 , 50 , 111), // #723 - INST(Sldt , X86M , O(000F00,00,0,_,_,_,_,_ ), 0 , 4 , 0 , 2853 , 172, 0 ), // #724 - INST(Slwpcb , VexR_Wx , V(XOP_M9,12,1,0,x,_,_,_ ), 0 , 11 , 0 , 2858 , 99 , 69 ), // #725 - INST(Smsw , X86M , O(000F00,01,4,_,_,_,_,_ ), 0 , 91 , 0 , 2865 , 172, 0 ), // #726 - INST(Sqrtpd , ExtRm , O(660F00,51,_,_,_,_,_,_ ), 0 , 3 , 0 , 10060, 5 , 4 ), // #727 - INST(Sqrtps , ExtRm , O(000F00,51,_,_,_,_,_,_ ), 0 , 4 , 0 , 9775 , 5 , 5 ), // #728 - INST(Sqrtsd , ExtRm , O(F20F00,51,_,_,_,_,_,_ ), 0 , 5 , 0 , 10076, 6 , 4 ), // #729 - INST(Sqrtss , ExtRm , O(F30F00,51,_,_,_,_,_,_ ), 0 , 6 , 0 , 9784 , 7 , 5 ), // #730 - INST(Stac , X86Op , O(000F01,CB,_,_,_,_,_,_ ), 0 , 21 , 0 , 2870 , 30 , 16 ), // #731 - INST(Stc , X86Op , O(000000,F9,_,_,_,_,_,_ ), 0 , 0 , 0 , 2875 , 30 , 17 ), // #732 - INST(Std , X86Op , O(000000,FD,_,_,_,_,_,_ ), 0 , 0 , 0 , 6802 , 30 , 18 ), // #733 - INST(Stgi , X86Op , O(000F01,DC,_,_,_,_,_,_ ), 0 , 21 , 0 , 2879 , 30 , 111), // #734 - INST(Sti , X86Op , O(000000,FB,_,_,_,_,_,_ ), 0 , 0 , 0 , 2884 , 30 , 23 ), // #735 - INST(Stmxcsr , X86M_Only , O(000F00,AE,3,_,_,_,_,_ ), 0 , 71 , 0 , 10092, 93 , 5 ), // #736 - INST(Stos , X86StrMr , O(000000,AA,_,_,_,_,_,_ ), 0 , 0 , 0 , 2888 , 173, 70 ), // #737 - INST(Str , X86M , O(000F00,00,1,_,_,_,_,_ ), 0 , 27 , 0 , 2893 , 172, 0 ), // #738 - INST(Sttilecfg , AmxCfg , V(660F38,49,_,0,0,_,_,_ ), 0 , 90 , 0 , 2897 , 95 , 68 ), // #739 - INST(Sub , X86Arith , O(000000,28,5,_,x,_,_,_ ), 0 , 58 , 0 , 836 , 168, 1 ), // #740 - INST(Subpd , ExtRm , O(660F00,5C,_,_,_,_,_,_ ), 0 , 3 , 0 , 4744 , 5 , 4 ), // #741 - INST(Subps , ExtRm , O(000F00,5C,_,_,_,_,_,_ ), 0 , 4 , 0 , 4756 , 5 , 5 ), // #742 - INST(Subsd , ExtRm , O(F20F00,5C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5432 , 6 , 4 ), // #743 - INST(Subss , ExtRm , O(F30F00,5C,_,_,_,_,_,_ ), 0 , 6 , 0 , 5442 , 7 , 5 ), // #744 - INST(Swapgs , X86Op , O(000F01,F8,_,_,_,_,_,_ ), 0 , 21 , 0 , 2907 , 156, 0 ), // #745 - INST(Syscall , X86Op , O(000F00,05,_,_,_,_,_,_ ), 0 , 4 , 0 , 2914 , 156, 0 ), // #746 - INST(Sysenter , X86Op , O(000F00,34,_,_,_,_,_,_ ), 0 , 4 , 0 , 2922 , 30 , 0 ), // #747 - INST(Sysexit , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 2931 , 30 , 0 ), // #748 - INST(Sysexit64 , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 2939 , 30 , 0 ), // #749 - INST(Sysret , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 2949 , 156, 0 ), // #750 - INST(Sysret64 , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 2956 , 156, 0 ), // #751 - INST(T1mskc , VexVm_Wx , V(XOP_M9,01,7,0,x,_,_,_ ), 0 , 92 , 0 , 2965 , 14 , 11 ), // #752 - INST(Tdpbf16ps , AmxRmv , V(F30F38,5C,_,0,0,_,_,_ ), 0 , 83 , 0 , 2972 , 174, 112), // #753 - INST(Tdpbssd , AmxRmv , V(F20F38,5E,_,0,0,_,_,_ ), 0 , 78 , 0 , 2982 , 174, 113), // #754 - INST(Tdpbsud , AmxRmv , V(F30F38,5E,_,0,0,_,_,_ ), 0 , 83 , 0 , 2990 , 174, 113), // #755 - INST(Tdpbusd , AmxRmv , V(660F38,5E,_,0,0,_,_,_ ), 0 , 90 , 0 , 2998 , 174, 113), // #756 - INST(Tdpbuud , AmxRmv , V(000F38,5E,_,0,0,_,_,_ ), 0 , 10 , 0 , 3006 , 174, 113), // #757 - INST(Test , X86Test , O(000000,84,_,_,x,_,_,_ ), O(000000,F6,_,_,x,_,_,_ ), 0 , 78 , 9248 , 175, 1 ), // #758 - INST(Tileloadd , AmxRm , V(F20F38,4B,_,0,0,_,_,_ ), 0 , 78 , 0 , 3014 , 176, 68 ), // #759 - INST(Tileloaddt1 , AmxRm , V(660F38,4B,_,0,0,_,_,_ ), 0 , 90 , 0 , 3024 , 176, 68 ), // #760 - INST(Tilerelease , VexOpMod , V(000F38,49,0,0,0,_,_,_ ), 0 , 10 , 0 , 3036 , 177, 68 ), // #761 - INST(Tilestored , AmxMr , V(F30F38,4B,_,0,0,_,_,_ ), 0 , 83 , 0 , 3048 , 178, 68 ), // #762 - INST(Tilezero , AmxR , V(F20F38,49,_,0,0,_,_,_ ), 0 , 78 , 0 , 3059 , 179, 68 ), // #763 - INST(Tpause , X86R32_EDX_EAX , O(660F00,AE,6,_,_,_,_,_ ), 0 , 24 , 0 , 3068 , 180, 114), // #764 - INST(Tzcnt , X86Rm_Raw66H , O(F30F00,BC,_,_,x,_,_,_ ), 0 , 6 , 0 , 3075 , 22 , 9 ), // #765 - INST(Tzmsk , VexVm_Wx , V(XOP_M9,01,4,0,x,_,_,_ ), 0 , 93 , 0 , 3081 , 14 , 11 ), // #766 - INST(Ucomisd , ExtRm , O(660F00,2E,_,_,_,_,_,_ ), 0 , 3 , 0 , 10145, 6 , 39 ), // #767 - INST(Ucomiss , ExtRm , O(000F00,2E,_,_,_,_,_,_ ), 0 , 4 , 0 , 10154, 7 , 40 ), // #768 - INST(Ud2 , X86Op , O(000F00,0B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3087 , 30 , 0 ), // #769 - INST(Umonitor , X86R_FromM , O(F30F00,AE,6,_,_,_,_,_ ), 0 , 94 , 0 , 3091 , 181, 115), // #770 - INST(Umwait , X86R32_EDX_EAX , O(F20F00,AE,6,_,_,_,_,_ ), 0 , 95 , 0 , 3100 , 180, 114), // #771 - INST(Unpckhpd , ExtRm , O(660F00,15,_,_,_,_,_,_ ), 0 , 3 , 0 , 10163, 5 , 4 ), // #772 - INST(Unpckhps , ExtRm , O(000F00,15,_,_,_,_,_,_ ), 0 , 4 , 0 , 10173, 5 , 5 ), // #773 - INST(Unpcklpd , ExtRm , O(660F00,14,_,_,_,_,_,_ ), 0 , 3 , 0 , 10183, 5 , 4 ), // #774 - INST(Unpcklps , ExtRm , O(000F00,14,_,_,_,_,_,_ ), 0 , 4 , 0 , 10193, 5 , 5 ), // #775 - INST(V4fmaddps , VexRm_T1_4X , E(F20F38,9A,_,2,_,0,2,T4X), 0 , 96 , 0 , 3107 , 182, 116), // #776 - INST(V4fmaddss , VexRm_T1_4X , E(F20F38,9B,_,2,_,0,2,T4X), 0 , 96 , 0 , 3117 , 183, 116), // #777 - INST(V4fnmaddps , VexRm_T1_4X , E(F20F38,AA,_,2,_,0,2,T4X), 0 , 96 , 0 , 3127 , 182, 116), // #778 - INST(V4fnmaddss , VexRm_T1_4X , E(F20F38,AB,_,2,_,0,2,T4X), 0 , 96 , 0 , 3138 , 183, 116), // #779 - INST(Vaddpd , VexRvm_Lx , V(660F00,58,_,x,I,1,4,FV ), 0 , 97 , 0 , 3149 , 184, 117), // #780 - INST(Vaddps , VexRvm_Lx , V(000F00,58,_,x,I,0,4,FV ), 0 , 98 , 0 , 3156 , 185, 117), // #781 - INST(Vaddsd , VexRvm , V(F20F00,58,_,I,I,1,3,T1S), 0 , 99 , 0 , 3163 , 186, 118), // #782 - INST(Vaddss , VexRvm , V(F30F00,58,_,I,I,0,2,T1S), 0 , 100, 0 , 3170 , 187, 118), // #783 - INST(Vaddsubpd , VexRvm_Lx , V(660F00,D0,_,x,I,_,_,_ ), 0 , 63 , 0 , 3177 , 188, 119), // #784 - INST(Vaddsubps , VexRvm_Lx , V(F20F00,D0,_,x,I,_,_,_ ), 0 , 101, 0 , 3187 , 188, 119), // #785 - INST(Vaesdec , VexRvm_Lx , V(660F38,DE,_,x,I,_,4,FVM), 0 , 102, 0 , 3197 , 189, 120), // #786 - INST(Vaesdeclast , VexRvm_Lx , V(660F38,DF,_,x,I,_,4,FVM), 0 , 102, 0 , 3205 , 189, 120), // #787 - INST(Vaesenc , VexRvm_Lx , V(660F38,DC,_,x,I,_,4,FVM), 0 , 102, 0 , 3217 , 189, 120), // #788 - INST(Vaesenclast , VexRvm_Lx , V(660F38,DD,_,x,I,_,4,FVM), 0 , 102, 0 , 3225 , 189, 120), // #789 - INST(Vaesimc , VexRm , V(660F38,DB,_,0,I,_,_,_ ), 0 , 90 , 0 , 3237 , 190, 121), // #790 - INST(Vaeskeygenassist , VexRmi , V(660F3A,DF,_,0,I,_,_,_ ), 0 , 67 , 0 , 3245 , 191, 121), // #791 - INST(Valignd , VexRvmi_Lx , E(660F3A,03,_,x,_,0,4,FV ), 0 , 103, 0 , 3262 , 192, 122), // #792 - INST(Valignq , VexRvmi_Lx , E(660F3A,03,_,x,_,1,4,FV ), 0 , 104, 0 , 3270 , 193, 122), // #793 - INST(Vandnpd , VexRvm_Lx , V(660F00,55,_,x,I,1,4,FV ), 0 , 97 , 0 , 3278 , 194, 123), // #794 - INST(Vandnps , VexRvm_Lx , V(000F00,55,_,x,I,0,4,FV ), 0 , 98 , 0 , 3286 , 195, 123), // #795 - INST(Vandpd , VexRvm_Lx , V(660F00,54,_,x,I,1,4,FV ), 0 , 97 , 0 , 3294 , 196, 123), // #796 - INST(Vandps , VexRvm_Lx , V(000F00,54,_,x,I,0,4,FV ), 0 , 98 , 0 , 3301 , 197, 123), // #797 - INST(Vblendmb , VexRvm_Lx , E(660F38,66,_,x,_,0,4,FVM), 0 , 105, 0 , 3308 , 198, 124), // #798 - INST(Vblendmd , VexRvm_Lx , E(660F38,64,_,x,_,0,4,FV ), 0 , 106, 0 , 3317 , 199, 122), // #799 - INST(Vblendmpd , VexRvm_Lx , E(660F38,65,_,x,_,1,4,FV ), 0 , 107, 0 , 3326 , 200, 122), // #800 - INST(Vblendmps , VexRvm_Lx , E(660F38,65,_,x,_,0,4,FV ), 0 , 106, 0 , 3336 , 199, 122), // #801 - INST(Vblendmq , VexRvm_Lx , E(660F38,64,_,x,_,1,4,FV ), 0 , 107, 0 , 3346 , 200, 122), // #802 - INST(Vblendmw , VexRvm_Lx , E(660F38,66,_,x,_,1,4,FVM), 0 , 108, 0 , 3355 , 198, 124), // #803 - INST(Vblendpd , VexRvmi_Lx , V(660F3A,0D,_,x,I,_,_,_ ), 0 , 67 , 0 , 3364 , 201, 119), // #804 - INST(Vblendps , VexRvmi_Lx , V(660F3A,0C,_,x,I,_,_,_ ), 0 , 67 , 0 , 3373 , 201, 119), // #805 - INST(Vblendvpd , VexRvmr_Lx , V(660F3A,4B,_,x,0,_,_,_ ), 0 , 67 , 0 , 3382 , 202, 119), // #806 - INST(Vblendvps , VexRvmr_Lx , V(660F3A,4A,_,x,0,_,_,_ ), 0 , 67 , 0 , 3392 , 202, 119), // #807 - INST(Vbroadcastf128 , VexRm , V(660F38,1A,_,1,0,_,_,_ ), 0 , 109, 0 , 3402 , 203, 119), // #808 - INST(Vbroadcastf32x2 , VexRm_Lx , E(660F38,19,_,x,_,0,3,T2 ), 0 , 110, 0 , 3417 , 204, 125), // #809 - INST(Vbroadcastf32x4 , VexRm_Lx , E(660F38,1A,_,x,_,0,4,T4 ), 0 , 111, 0 , 3433 , 205, 63 ), // #810 - INST(Vbroadcastf32x8 , VexRm , E(660F38,1B,_,2,_,0,5,T8 ), 0 , 112, 0 , 3449 , 206, 61 ), // #811 - INST(Vbroadcastf64x2 , VexRm_Lx , E(660F38,1A,_,x,_,1,4,T2 ), 0 , 113, 0 , 3465 , 205, 125), // #812 - INST(Vbroadcastf64x4 , VexRm , E(660F38,1B,_,2,_,1,5,T4 ), 0 , 114, 0 , 3481 , 206, 63 ), // #813 - INST(Vbroadcasti128 , VexRm , V(660F38,5A,_,1,0,_,_,_ ), 0 , 109, 0 , 3497 , 203, 126), // #814 - INST(Vbroadcasti32x2 , VexRm_Lx , E(660F38,59,_,x,_,0,3,T2 ), 0 , 110, 0 , 3512 , 207, 125), // #815 - INST(Vbroadcasti32x4 , VexRm_Lx , E(660F38,5A,_,x,_,0,4,T4 ), 0 , 111, 0 , 3528 , 205, 122), // #816 - INST(Vbroadcasti32x8 , VexRm , E(660F38,5B,_,2,_,0,5,T8 ), 0 , 112, 0 , 3544 , 206, 61 ), // #817 - INST(Vbroadcasti64x2 , VexRm_Lx , E(660F38,5A,_,x,_,1,4,T2 ), 0 , 113, 0 , 3560 , 205, 125), // #818 - INST(Vbroadcasti64x4 , VexRm , E(660F38,5B,_,2,_,1,5,T4 ), 0 , 114, 0 , 3576 , 206, 63 ), // #819 - INST(Vbroadcastsd , VexRm_Lx , V(660F38,19,_,x,0,1,3,T1S), 0 , 115, 0 , 3592 , 208, 127), // #820 - INST(Vbroadcastss , VexRm_Lx , V(660F38,18,_,x,0,0,2,T1S), 0 , 116, 0 , 3605 , 209, 127), // #821 - INST(Vcmppd , VexRvmi_Lx , V(660F00,C2,_,x,I,1,4,FV ), 0 , 97 , 0 , 3618 , 210, 117), // #822 - INST(Vcmpps , VexRvmi_Lx , V(000F00,C2,_,x,I,0,4,FV ), 0 , 98 , 0 , 3625 , 211, 117), // #823 - INST(Vcmpsd , VexRvmi , V(F20F00,C2,_,I,I,1,3,T1S), 0 , 99 , 0 , 3632 , 212, 118), // #824 - INST(Vcmpss , VexRvmi , V(F30F00,C2,_,I,I,0,2,T1S), 0 , 100, 0 , 3639 , 213, 118), // #825 - INST(Vcomisd , VexRm , V(660F00,2F,_,I,I,1,3,T1S), 0 , 117, 0 , 3646 , 214, 128), // #826 - INST(Vcomiss , VexRm , V(000F00,2F,_,I,I,0,2,T1S), 0 , 118, 0 , 3654 , 215, 128), // #827 - INST(Vcompresspd , VexMr_Lx , E(660F38,8A,_,x,_,1,3,T1S), 0 , 119, 0 , 3662 , 216, 122), // #828 - INST(Vcompressps , VexMr_Lx , E(660F38,8A,_,x,_,0,2,T1S), 0 , 120, 0 , 3674 , 216, 122), // #829 - INST(Vcvtdq2pd , VexRm_Lx , V(F30F00,E6,_,x,I,0,3,HV ), 0 , 121, 0 , 3686 , 217, 117), // #830 - INST(Vcvtdq2ps , VexRm_Lx , V(000F00,5B,_,x,I,0,4,FV ), 0 , 98 , 0 , 3696 , 218, 117), // #831 - INST(Vcvtne2ps2bf16 , VexRvm , E(F20F38,72,_,_,_,0,_,_ ), 0 , 122, 0 , 3706 , 199, 129), // #832 - INST(Vcvtneps2bf16 , VexRm , E(F30F38,72,_,_,_,0,_,_ ), 0 , 123, 0 , 3721 , 219, 129), // #833 - INST(Vcvtpd2dq , VexRm_Lx , V(F20F00,E6,_,x,I,1,4,FV ), 0 , 124, 0 , 3735 , 220, 117), // #834 - INST(Vcvtpd2ps , VexRm_Lx , V(660F00,5A,_,x,I,1,4,FV ), 0 , 97 , 0 , 3745 , 220, 117), // #835 - INST(Vcvtpd2qq , VexRm_Lx , E(660F00,7B,_,x,_,1,4,FV ), 0 , 125, 0 , 3755 , 221, 125), // #836 - INST(Vcvtpd2udq , VexRm_Lx , E(000F00,79,_,x,_,1,4,FV ), 0 , 126, 0 , 3765 , 222, 122), // #837 - INST(Vcvtpd2uqq , VexRm_Lx , E(660F00,79,_,x,_,1,4,FV ), 0 , 125, 0 , 3776 , 221, 125), // #838 - INST(Vcvtph2ps , VexRm_Lx , V(660F38,13,_,x,0,0,3,HVM), 0 , 127, 0 , 3787 , 223, 130), // #839 - INST(Vcvtps2dq , VexRm_Lx , V(660F00,5B,_,x,I,0,4,FV ), 0 , 128, 0 , 3797 , 218, 117), // #840 - INST(Vcvtps2pd , VexRm_Lx , V(000F00,5A,_,x,I,0,4,HV ), 0 , 129, 0 , 3807 , 224, 117), // #841 - INST(Vcvtps2ph , VexMri_Lx , V(660F3A,1D,_,x,0,0,3,HVM), 0 , 130, 0 , 3817 , 225, 130), // #842 - INST(Vcvtps2qq , VexRm_Lx , E(660F00,7B,_,x,_,0,3,HV ), 0 , 131, 0 , 3827 , 226, 125), // #843 - INST(Vcvtps2udq , VexRm_Lx , E(000F00,79,_,x,_,0,4,FV ), 0 , 132, 0 , 3837 , 227, 122), // #844 - INST(Vcvtps2uqq , VexRm_Lx , E(660F00,79,_,x,_,0,3,HV ), 0 , 131, 0 , 3848 , 226, 125), // #845 - INST(Vcvtqq2pd , VexRm_Lx , E(F30F00,E6,_,x,_,1,4,FV ), 0 , 133, 0 , 3859 , 221, 125), // #846 - INST(Vcvtqq2ps , VexRm_Lx , E(000F00,5B,_,x,_,1,4,FV ), 0 , 126, 0 , 3869 , 222, 125), // #847 - INST(Vcvtsd2si , VexRm_Wx , V(F20F00,2D,_,I,x,x,3,T1F), 0 , 134, 0 , 3879 , 228, 118), // #848 - INST(Vcvtsd2ss , VexRvm , V(F20F00,5A,_,I,I,1,3,T1S), 0 , 99 , 0 , 3889 , 186, 118), // #849 - INST(Vcvtsd2usi , VexRm_Wx , E(F20F00,79,_,I,_,x,3,T1F), 0 , 135, 0 , 3899 , 229, 63 ), // #850 - INST(Vcvtsi2sd , VexRvm_Wx , V(F20F00,2A,_,I,x,x,2,T1W), 0 , 136, 0 , 3910 , 230, 118), // #851 - INST(Vcvtsi2ss , VexRvm_Wx , V(F30F00,2A,_,I,x,x,2,T1W), 0 , 137, 0 , 3920 , 230, 118), // #852 - INST(Vcvtss2sd , VexRvm , V(F30F00,5A,_,I,I,0,2,T1S), 0 , 100, 0 , 3930 , 231, 118), // #853 - INST(Vcvtss2si , VexRm_Wx , V(F30F00,2D,_,I,x,x,2,T1F), 0 , 138, 0 , 3940 , 232, 118), // #854 - INST(Vcvtss2usi , VexRm_Wx , E(F30F00,79,_,I,_,x,2,T1F), 0 , 139, 0 , 3950 , 233, 63 ), // #855 - INST(Vcvttpd2dq , VexRm_Lx , V(660F00,E6,_,x,I,1,4,FV ), 0 , 97 , 0 , 3961 , 234, 117), // #856 - INST(Vcvttpd2qq , VexRm_Lx , E(660F00,7A,_,x,_,1,4,FV ), 0 , 125, 0 , 3972 , 235, 122), // #857 - INST(Vcvttpd2udq , VexRm_Lx , E(000F00,78,_,x,_,1,4,FV ), 0 , 126, 0 , 3983 , 236, 122), // #858 - INST(Vcvttpd2uqq , VexRm_Lx , E(660F00,78,_,x,_,1,4,FV ), 0 , 125, 0 , 3995 , 235, 125), // #859 - INST(Vcvttps2dq , VexRm_Lx , V(F30F00,5B,_,x,I,0,4,FV ), 0 , 140, 0 , 4007 , 237, 117), // #860 - INST(Vcvttps2qq , VexRm_Lx , E(660F00,7A,_,x,_,0,3,HV ), 0 , 131, 0 , 4018 , 238, 125), // #861 - INST(Vcvttps2udq , VexRm_Lx , E(000F00,78,_,x,_,0,4,FV ), 0 , 132, 0 , 4029 , 239, 122), // #862 - INST(Vcvttps2uqq , VexRm_Lx , E(660F00,78,_,x,_,0,3,HV ), 0 , 131, 0 , 4041 , 238, 125), // #863 - INST(Vcvttsd2si , VexRm_Wx , V(F20F00,2C,_,I,x,x,3,T1F), 0 , 134, 0 , 4053 , 240, 118), // #864 - INST(Vcvttsd2usi , VexRm_Wx , E(F20F00,78,_,I,_,x,3,T1F), 0 , 135, 0 , 4064 , 241, 63 ), // #865 - INST(Vcvttss2si , VexRm_Wx , V(F30F00,2C,_,I,x,x,2,T1F), 0 , 138, 0 , 4076 , 242, 118), // #866 - INST(Vcvttss2usi , VexRm_Wx , E(F30F00,78,_,I,_,x,2,T1F), 0 , 139, 0 , 4087 , 243, 63 ), // #867 - INST(Vcvtudq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,0,3,HV ), 0 , 141, 0 , 4099 , 244, 122), // #868 - INST(Vcvtudq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,0,4,FV ), 0 , 142, 0 , 4110 , 227, 122), // #869 - INST(Vcvtuqq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,1,4,FV ), 0 , 133, 0 , 4121 , 221, 125), // #870 - INST(Vcvtuqq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,1,4,FV ), 0 , 143, 0 , 4132 , 222, 125), // #871 - INST(Vcvtusi2sd , VexRvm_Wx , E(F20F00,7B,_,I,_,x,2,T1W), 0 , 144, 0 , 4143 , 245, 63 ), // #872 - INST(Vcvtusi2ss , VexRvm_Wx , E(F30F00,7B,_,I,_,x,2,T1W), 0 , 145, 0 , 4154 , 245, 63 ), // #873 - INST(Vdbpsadbw , VexRvmi_Lx , E(660F3A,42,_,x,_,0,4,FVM), 0 , 146, 0 , 4165 , 246, 124), // #874 - INST(Vdivpd , VexRvm_Lx , V(660F00,5E,_,x,I,1,4,FV ), 0 , 97 , 0 , 4175 , 184, 117), // #875 - INST(Vdivps , VexRvm_Lx , V(000F00,5E,_,x,I,0,4,FV ), 0 , 98 , 0 , 4182 , 185, 117), // #876 - INST(Vdivsd , VexRvm , V(F20F00,5E,_,I,I,1,3,T1S), 0 , 99 , 0 , 4189 , 186, 118), // #877 - INST(Vdivss , VexRvm , V(F30F00,5E,_,I,I,0,2,T1S), 0 , 100, 0 , 4196 , 187, 118), // #878 - INST(Vdpbf16ps , VexRvm , E(F30F38,52,_,_,_,0,_,_ ), 0 , 123, 0 , 4203 , 199, 129), // #879 - INST(Vdppd , VexRvmi_Lx , V(660F3A,41,_,x,I,_,_,_ ), 0 , 67 , 0 , 4213 , 247, 119), // #880 - INST(Vdpps , VexRvmi_Lx , V(660F3A,40,_,x,I,_,_,_ ), 0 , 67 , 0 , 4219 , 201, 119), // #881 - INST(Verr , X86M_NoSize , O(000F00,00,4,_,_,_,_,_ ), 0 , 91 , 0 , 4225 , 98 , 10 ), // #882 - INST(Verw , X86M_NoSize , O(000F00,00,5,_,_,_,_,_ ), 0 , 70 , 0 , 4230 , 98 , 10 ), // #883 - INST(Vexp2pd , VexRm , E(660F38,C8,_,2,_,1,4,FV ), 0 , 147, 0 , 4235 , 248, 131), // #884 - INST(Vexp2ps , VexRm , E(660F38,C8,_,2,_,0,4,FV ), 0 , 148, 0 , 4243 , 249, 131), // #885 - INST(Vexpandpd , VexRm_Lx , E(660F38,88,_,x,_,1,3,T1S), 0 , 119, 0 , 4251 , 250, 122), // #886 - INST(Vexpandps , VexRm_Lx , E(660F38,88,_,x,_,0,2,T1S), 0 , 120, 0 , 4261 , 250, 122), // #887 - INST(Vextractf128 , VexMri , V(660F3A,19,_,1,0,_,_,_ ), 0 , 149, 0 , 4271 , 251, 119), // #888 - INST(Vextractf32x4 , VexMri_Lx , E(660F3A,19,_,x,_,0,4,T4 ), 0 , 150, 0 , 4284 , 252, 122), // #889 - INST(Vextractf32x8 , VexMri , E(660F3A,1B,_,2,_,0,5,T8 ), 0 , 151, 0 , 4298 , 253, 61 ), // #890 - INST(Vextractf64x2 , VexMri_Lx , E(660F3A,19,_,x,_,1,4,T2 ), 0 , 152, 0 , 4312 , 252, 125), // #891 - INST(Vextractf64x4 , VexMri , E(660F3A,1B,_,2,_,1,5,T4 ), 0 , 153, 0 , 4326 , 253, 63 ), // #892 - INST(Vextracti128 , VexMri , V(660F3A,39,_,1,0,_,_,_ ), 0 , 149, 0 , 4340 , 251, 126), // #893 - INST(Vextracti32x4 , VexMri_Lx , E(660F3A,39,_,x,_,0,4,T4 ), 0 , 150, 0 , 4353 , 252, 122), // #894 - INST(Vextracti32x8 , VexMri , E(660F3A,3B,_,2,_,0,5,T8 ), 0 , 151, 0 , 4367 , 253, 61 ), // #895 - INST(Vextracti64x2 , VexMri_Lx , E(660F3A,39,_,x,_,1,4,T2 ), 0 , 152, 0 , 4381 , 252, 125), // #896 - INST(Vextracti64x4 , VexMri , E(660F3A,3B,_,2,_,1,5,T4 ), 0 , 153, 0 , 4395 , 253, 63 ), // #897 - INST(Vextractps , VexMri , V(660F3A,17,_,0,I,I,2,T1S), 0 , 154, 0 , 4409 , 254, 118), // #898 - INST(Vfixupimmpd , VexRvmi_Lx , E(660F3A,54,_,x,_,1,4,FV ), 0 , 104, 0 , 4420 , 255, 122), // #899 - INST(Vfixupimmps , VexRvmi_Lx , E(660F3A,54,_,x,_,0,4,FV ), 0 , 103, 0 , 4432 , 256, 122), // #900 - INST(Vfixupimmsd , VexRvmi , E(660F3A,55,_,I,_,1,3,T1S), 0 , 155, 0 , 4444 , 257, 63 ), // #901 - INST(Vfixupimmss , VexRvmi , E(660F3A,55,_,I,_,0,2,T1S), 0 , 156, 0 , 4456 , 258, 63 ), // #902 - INST(Vfmadd132pd , VexRvm_Lx , V(660F38,98,_,x,1,1,4,FV ), 0 , 157, 0 , 4468 , 184, 132), // #903 - INST(Vfmadd132ps , VexRvm_Lx , V(660F38,98,_,x,0,0,4,FV ), 0 , 158, 0 , 4480 , 185, 132), // #904 - INST(Vfmadd132sd , VexRvm , V(660F38,99,_,I,1,1,3,T1S), 0 , 159, 0 , 4492 , 186, 133), // #905 - INST(Vfmadd132ss , VexRvm , V(660F38,99,_,I,0,0,2,T1S), 0 , 116, 0 , 4504 , 187, 133), // #906 - INST(Vfmadd213pd , VexRvm_Lx , V(660F38,A8,_,x,1,1,4,FV ), 0 , 157, 0 , 4516 , 184, 132), // #907 - INST(Vfmadd213ps , VexRvm_Lx , V(660F38,A8,_,x,0,0,4,FV ), 0 , 158, 0 , 4528 , 185, 132), // #908 - INST(Vfmadd213sd , VexRvm , V(660F38,A9,_,I,1,1,3,T1S), 0 , 159, 0 , 4540 , 186, 133), // #909 - INST(Vfmadd213ss , VexRvm , V(660F38,A9,_,I,0,0,2,T1S), 0 , 116, 0 , 4552 , 187, 133), // #910 - INST(Vfmadd231pd , VexRvm_Lx , V(660F38,B8,_,x,1,1,4,FV ), 0 , 157, 0 , 4564 , 184, 132), // #911 - INST(Vfmadd231ps , VexRvm_Lx , V(660F38,B8,_,x,0,0,4,FV ), 0 , 158, 0 , 4576 , 185, 132), // #912 - INST(Vfmadd231sd , VexRvm , V(660F38,B9,_,I,1,1,3,T1S), 0 , 159, 0 , 4588 , 186, 133), // #913 - INST(Vfmadd231ss , VexRvm , V(660F38,B9,_,I,0,0,2,T1S), 0 , 116, 0 , 4600 , 187, 133), // #914 - INST(Vfmaddpd , Fma4_Lx , V(660F3A,69,_,x,x,_,_,_ ), 0 , 67 , 0 , 4612 , 259, 134), // #915 - INST(Vfmaddps , Fma4_Lx , V(660F3A,68,_,x,x,_,_,_ ), 0 , 67 , 0 , 4621 , 259, 134), // #916 - INST(Vfmaddsd , Fma4 , V(660F3A,6B,_,0,x,_,_,_ ), 0 , 67 , 0 , 4630 , 260, 134), // #917 - INST(Vfmaddss , Fma4 , V(660F3A,6A,_,0,x,_,_,_ ), 0 , 67 , 0 , 4639 , 261, 134), // #918 - INST(Vfmaddsub132pd , VexRvm_Lx , V(660F38,96,_,x,1,1,4,FV ), 0 , 157, 0 , 4648 , 184, 132), // #919 - INST(Vfmaddsub132ps , VexRvm_Lx , V(660F38,96,_,x,0,0,4,FV ), 0 , 158, 0 , 4663 , 185, 132), // #920 - INST(Vfmaddsub213pd , VexRvm_Lx , V(660F38,A6,_,x,1,1,4,FV ), 0 , 157, 0 , 4678 , 184, 132), // #921 - INST(Vfmaddsub213ps , VexRvm_Lx , V(660F38,A6,_,x,0,0,4,FV ), 0 , 158, 0 , 4693 , 185, 132), // #922 - INST(Vfmaddsub231pd , VexRvm_Lx , V(660F38,B6,_,x,1,1,4,FV ), 0 , 157, 0 , 4708 , 184, 132), // #923 - INST(Vfmaddsub231ps , VexRvm_Lx , V(660F38,B6,_,x,0,0,4,FV ), 0 , 158, 0 , 4723 , 185, 132), // #924 - INST(Vfmaddsubpd , Fma4_Lx , V(660F3A,5D,_,x,x,_,_,_ ), 0 , 67 , 0 , 4738 , 259, 134), // #925 - INST(Vfmaddsubps , Fma4_Lx , V(660F3A,5C,_,x,x,_,_,_ ), 0 , 67 , 0 , 4750 , 259, 134), // #926 - INST(Vfmsub132pd , VexRvm_Lx , V(660F38,9A,_,x,1,1,4,FV ), 0 , 157, 0 , 4762 , 184, 132), // #927 - INST(Vfmsub132ps , VexRvm_Lx , V(660F38,9A,_,x,0,0,4,FV ), 0 , 158, 0 , 4774 , 185, 132), // #928 - INST(Vfmsub132sd , VexRvm , V(660F38,9B,_,I,1,1,3,T1S), 0 , 159, 0 , 4786 , 186, 133), // #929 - INST(Vfmsub132ss , VexRvm , V(660F38,9B,_,I,0,0,2,T1S), 0 , 116, 0 , 4798 , 187, 133), // #930 - INST(Vfmsub213pd , VexRvm_Lx , V(660F38,AA,_,x,1,1,4,FV ), 0 , 157, 0 , 4810 , 184, 132), // #931 - INST(Vfmsub213ps , VexRvm_Lx , V(660F38,AA,_,x,0,0,4,FV ), 0 , 158, 0 , 4822 , 185, 132), // #932 - INST(Vfmsub213sd , VexRvm , V(660F38,AB,_,I,1,1,3,T1S), 0 , 159, 0 , 4834 , 186, 133), // #933 - INST(Vfmsub213ss , VexRvm , V(660F38,AB,_,I,0,0,2,T1S), 0 , 116, 0 , 4846 , 187, 133), // #934 - INST(Vfmsub231pd , VexRvm_Lx , V(660F38,BA,_,x,1,1,4,FV ), 0 , 157, 0 , 4858 , 184, 132), // #935 - INST(Vfmsub231ps , VexRvm_Lx , V(660F38,BA,_,x,0,0,4,FV ), 0 , 158, 0 , 4870 , 185, 132), // #936 - INST(Vfmsub231sd , VexRvm , V(660F38,BB,_,I,1,1,3,T1S), 0 , 159, 0 , 4882 , 186, 133), // #937 - INST(Vfmsub231ss , VexRvm , V(660F38,BB,_,I,0,0,2,T1S), 0 , 116, 0 , 4894 , 187, 133), // #938 - INST(Vfmsubadd132pd , VexRvm_Lx , V(660F38,97,_,x,1,1,4,FV ), 0 , 157, 0 , 4906 , 184, 132), // #939 - INST(Vfmsubadd132ps , VexRvm_Lx , V(660F38,97,_,x,0,0,4,FV ), 0 , 158, 0 , 4921 , 185, 132), // #940 - INST(Vfmsubadd213pd , VexRvm_Lx , V(660F38,A7,_,x,1,1,4,FV ), 0 , 157, 0 , 4936 , 184, 132), // #941 - INST(Vfmsubadd213ps , VexRvm_Lx , V(660F38,A7,_,x,0,0,4,FV ), 0 , 158, 0 , 4951 , 185, 132), // #942 - INST(Vfmsubadd231pd , VexRvm_Lx , V(660F38,B7,_,x,1,1,4,FV ), 0 , 157, 0 , 4966 , 184, 132), // #943 - INST(Vfmsubadd231ps , VexRvm_Lx , V(660F38,B7,_,x,0,0,4,FV ), 0 , 158, 0 , 4981 , 185, 132), // #944 - INST(Vfmsubaddpd , Fma4_Lx , V(660F3A,5F,_,x,x,_,_,_ ), 0 , 67 , 0 , 4996 , 259, 134), // #945 - INST(Vfmsubaddps , Fma4_Lx , V(660F3A,5E,_,x,x,_,_,_ ), 0 , 67 , 0 , 5008 , 259, 134), // #946 - INST(Vfmsubpd , Fma4_Lx , V(660F3A,6D,_,x,x,_,_,_ ), 0 , 67 , 0 , 5020 , 259, 134), // #947 - INST(Vfmsubps , Fma4_Lx , V(660F3A,6C,_,x,x,_,_,_ ), 0 , 67 , 0 , 5029 , 259, 134), // #948 - INST(Vfmsubsd , Fma4 , V(660F3A,6F,_,0,x,_,_,_ ), 0 , 67 , 0 , 5038 , 260, 134), // #949 - INST(Vfmsubss , Fma4 , V(660F3A,6E,_,0,x,_,_,_ ), 0 , 67 , 0 , 5047 , 261, 134), // #950 - INST(Vfnmadd132pd , VexRvm_Lx , V(660F38,9C,_,x,1,1,4,FV ), 0 , 157, 0 , 5056 , 184, 132), // #951 - INST(Vfnmadd132ps , VexRvm_Lx , V(660F38,9C,_,x,0,0,4,FV ), 0 , 158, 0 , 5069 , 185, 132), // #952 - INST(Vfnmadd132sd , VexRvm , V(660F38,9D,_,I,1,1,3,T1S), 0 , 159, 0 , 5082 , 186, 133), // #953 - INST(Vfnmadd132ss , VexRvm , V(660F38,9D,_,I,0,0,2,T1S), 0 , 116, 0 , 5095 , 187, 133), // #954 - INST(Vfnmadd213pd , VexRvm_Lx , V(660F38,AC,_,x,1,1,4,FV ), 0 , 157, 0 , 5108 , 184, 132), // #955 - INST(Vfnmadd213ps , VexRvm_Lx , V(660F38,AC,_,x,0,0,4,FV ), 0 , 158, 0 , 5121 , 185, 132), // #956 - INST(Vfnmadd213sd , VexRvm , V(660F38,AD,_,I,1,1,3,T1S), 0 , 159, 0 , 5134 , 186, 133), // #957 - INST(Vfnmadd213ss , VexRvm , V(660F38,AD,_,I,0,0,2,T1S), 0 , 116, 0 , 5147 , 187, 133), // #958 - INST(Vfnmadd231pd , VexRvm_Lx , V(660F38,BC,_,x,1,1,4,FV ), 0 , 157, 0 , 5160 , 184, 132), // #959 - INST(Vfnmadd231ps , VexRvm_Lx , V(660F38,BC,_,x,0,0,4,FV ), 0 , 158, 0 , 5173 , 185, 132), // #960 - INST(Vfnmadd231sd , VexRvm , V(660F38,BC,_,I,1,1,3,T1S), 0 , 159, 0 , 5186 , 186, 133), // #961 - INST(Vfnmadd231ss , VexRvm , V(660F38,BC,_,I,0,0,2,T1S), 0 , 116, 0 , 5199 , 187, 133), // #962 - INST(Vfnmaddpd , Fma4_Lx , V(660F3A,79,_,x,x,_,_,_ ), 0 , 67 , 0 , 5212 , 259, 134), // #963 - INST(Vfnmaddps , Fma4_Lx , V(660F3A,78,_,x,x,_,_,_ ), 0 , 67 , 0 , 5222 , 259, 134), // #964 - INST(Vfnmaddsd , Fma4 , V(660F3A,7B,_,0,x,_,_,_ ), 0 , 67 , 0 , 5232 , 260, 134), // #965 - INST(Vfnmaddss , Fma4 , V(660F3A,7A,_,0,x,_,_,_ ), 0 , 67 , 0 , 5242 , 261, 134), // #966 - INST(Vfnmsub132pd , VexRvm_Lx , V(660F38,9E,_,x,1,1,4,FV ), 0 , 157, 0 , 5252 , 184, 132), // #967 - INST(Vfnmsub132ps , VexRvm_Lx , V(660F38,9E,_,x,0,0,4,FV ), 0 , 158, 0 , 5265 , 185, 132), // #968 - INST(Vfnmsub132sd , VexRvm , V(660F38,9F,_,I,1,1,3,T1S), 0 , 159, 0 , 5278 , 186, 133), // #969 - INST(Vfnmsub132ss , VexRvm , V(660F38,9F,_,I,0,0,2,T1S), 0 , 116, 0 , 5291 , 187, 133), // #970 - INST(Vfnmsub213pd , VexRvm_Lx , V(660F38,AE,_,x,1,1,4,FV ), 0 , 157, 0 , 5304 , 184, 132), // #971 - INST(Vfnmsub213ps , VexRvm_Lx , V(660F38,AE,_,x,0,0,4,FV ), 0 , 158, 0 , 5317 , 185, 132), // #972 - INST(Vfnmsub213sd , VexRvm , V(660F38,AF,_,I,1,1,3,T1S), 0 , 159, 0 , 5330 , 186, 133), // #973 - INST(Vfnmsub213ss , VexRvm , V(660F38,AF,_,I,0,0,2,T1S), 0 , 116, 0 , 5343 , 187, 133), // #974 - INST(Vfnmsub231pd , VexRvm_Lx , V(660F38,BE,_,x,1,1,4,FV ), 0 , 157, 0 , 5356 , 184, 132), // #975 - INST(Vfnmsub231ps , VexRvm_Lx , V(660F38,BE,_,x,0,0,4,FV ), 0 , 158, 0 , 5369 , 185, 132), // #976 - INST(Vfnmsub231sd , VexRvm , V(660F38,BF,_,I,1,1,3,T1S), 0 , 159, 0 , 5382 , 186, 133), // #977 - INST(Vfnmsub231ss , VexRvm , V(660F38,BF,_,I,0,0,2,T1S), 0 , 116, 0 , 5395 , 187, 133), // #978 - INST(Vfnmsubpd , Fma4_Lx , V(660F3A,7D,_,x,x,_,_,_ ), 0 , 67 , 0 , 5408 , 259, 134), // #979 - INST(Vfnmsubps , Fma4_Lx , V(660F3A,7C,_,x,x,_,_,_ ), 0 , 67 , 0 , 5418 , 259, 134), // #980 - INST(Vfnmsubsd , Fma4 , V(660F3A,7F,_,0,x,_,_,_ ), 0 , 67 , 0 , 5428 , 260, 134), // #981 - INST(Vfnmsubss , Fma4 , V(660F3A,7E,_,0,x,_,_,_ ), 0 , 67 , 0 , 5438 , 261, 134), // #982 - INST(Vfpclasspd , VexRmi_Lx , E(660F3A,66,_,x,_,1,4,FV ), 0 , 104, 0 , 5448 , 262, 125), // #983 - INST(Vfpclassps , VexRmi_Lx , E(660F3A,66,_,x,_,0,4,FV ), 0 , 103, 0 , 5459 , 263, 125), // #984 - INST(Vfpclasssd , VexRmi_Lx , E(660F3A,67,_,I,_,1,3,T1S), 0 , 155, 0 , 5470 , 264, 61 ), // #985 - INST(Vfpclassss , VexRmi_Lx , E(660F3A,67,_,I,_,0,2,T1S), 0 , 156, 0 , 5481 , 265, 61 ), // #986 - INST(Vfrczpd , VexRm_Lx , V(XOP_M9,81,_,x,0,_,_,_ ), 0 , 72 , 0 , 5492 , 266, 135), // #987 - INST(Vfrczps , VexRm_Lx , V(XOP_M9,80,_,x,0,_,_,_ ), 0 , 72 , 0 , 5500 , 266, 135), // #988 - INST(Vfrczsd , VexRm , V(XOP_M9,83,_,0,0,_,_,_ ), 0 , 72 , 0 , 5508 , 267, 135), // #989 - INST(Vfrczss , VexRm , V(XOP_M9,82,_,0,0,_,_,_ ), 0 , 72 , 0 , 5516 , 268, 135), // #990 - INST(Vgatherdpd , VexRmvRm_VM , V(660F38,92,_,x,1,_,_,_ ), V(660F38,92,_,x,_,1,3,T1S), 160, 79 , 5524 , 269, 136), // #991 - INST(Vgatherdps , VexRmvRm_VM , V(660F38,92,_,x,0,_,_,_ ), V(660F38,92,_,x,_,0,2,T1S), 90 , 80 , 5535 , 270, 136), // #992 - INST(Vgatherpf0dpd , VexM_VM , E(660F38,C6,1,2,_,1,3,T1S), 0 , 161, 0 , 5546 , 271, 137), // #993 - INST(Vgatherpf0dps , VexM_VM , E(660F38,C6,1,2,_,0,2,T1S), 0 , 162, 0 , 5560 , 272, 137), // #994 - INST(Vgatherpf0qpd , VexM_VM , E(660F38,C7,1,2,_,1,3,T1S), 0 , 161, 0 , 5574 , 273, 137), // #995 - INST(Vgatherpf0qps , VexM_VM , E(660F38,C7,1,2,_,0,2,T1S), 0 , 162, 0 , 5588 , 273, 137), // #996 - INST(Vgatherpf1dpd , VexM_VM , E(660F38,C6,2,2,_,1,3,T1S), 0 , 163, 0 , 5602 , 271, 137), // #997 - INST(Vgatherpf1dps , VexM_VM , E(660F38,C6,2,2,_,0,2,T1S), 0 , 164, 0 , 5616 , 272, 137), // #998 - INST(Vgatherpf1qpd , VexM_VM , E(660F38,C7,2,2,_,1,3,T1S), 0 , 163, 0 , 5630 , 273, 137), // #999 - INST(Vgatherpf1qps , VexM_VM , E(660F38,C7,2,2,_,0,2,T1S), 0 , 164, 0 , 5644 , 273, 137), // #1000 - INST(Vgatherqpd , VexRmvRm_VM , V(660F38,93,_,x,1,_,_,_ ), V(660F38,93,_,x,_,1,3,T1S), 160, 81 , 5658 , 274, 136), // #1001 - INST(Vgatherqps , VexRmvRm_VM , V(660F38,93,_,x,0,_,_,_ ), V(660F38,93,_,x,_,0,2,T1S), 90 , 82 , 5669 , 275, 136), // #1002 - INST(Vgetexppd , VexRm_Lx , E(660F38,42,_,x,_,1,4,FV ), 0 , 107, 0 , 5680 , 235, 122), // #1003 - INST(Vgetexpps , VexRm_Lx , E(660F38,42,_,x,_,0,4,FV ), 0 , 106, 0 , 5690 , 239, 122), // #1004 - INST(Vgetexpsd , VexRvm , E(660F38,43,_,I,_,1,3,T1S), 0 , 119, 0 , 5700 , 276, 63 ), // #1005 - INST(Vgetexpss , VexRvm , E(660F38,43,_,I,_,0,2,T1S), 0 , 120, 0 , 5710 , 277, 63 ), // #1006 - INST(Vgetmantpd , VexRmi_Lx , E(660F3A,26,_,x,_,1,4,FV ), 0 , 104, 0 , 5720 , 278, 122), // #1007 - INST(Vgetmantps , VexRmi_Lx , E(660F3A,26,_,x,_,0,4,FV ), 0 , 103, 0 , 5731 , 279, 122), // #1008 - INST(Vgetmantsd , VexRvmi , E(660F3A,27,_,I,_,1,3,T1S), 0 , 155, 0 , 5742 , 257, 63 ), // #1009 - INST(Vgetmantss , VexRvmi , E(660F3A,27,_,I,_,0,2,T1S), 0 , 156, 0 , 5753 , 258, 63 ), // #1010 - INST(Vgf2p8affineinvqb, VexRvmi_Lx , V(660F3A,CF,_,x,1,1,4,FV ), 0 , 165, 0 , 5764 , 280, 138), // #1011 - INST(Vgf2p8affineqb , VexRvmi_Lx , V(660F3A,CE,_,x,1,1,4,FV ), 0 , 165, 0 , 5782 , 280, 138), // #1012 - INST(Vgf2p8mulb , VexRvm_Lx , V(660F38,CF,_,x,0,0,4,FV ), 0 , 158, 0 , 5797 , 281, 138), // #1013 - INST(Vhaddpd , VexRvm_Lx , V(660F00,7C,_,x,I,_,_,_ ), 0 , 63 , 0 , 5808 , 188, 119), // #1014 - INST(Vhaddps , VexRvm_Lx , V(F20F00,7C,_,x,I,_,_,_ ), 0 , 101, 0 , 5816 , 188, 119), // #1015 - INST(Vhsubpd , VexRvm_Lx , V(660F00,7D,_,x,I,_,_,_ ), 0 , 63 , 0 , 5824 , 188, 119), // #1016 - INST(Vhsubps , VexRvm_Lx , V(F20F00,7D,_,x,I,_,_,_ ), 0 , 101, 0 , 5832 , 188, 119), // #1017 - INST(Vinsertf128 , VexRvmi , V(660F3A,18,_,1,0,_,_,_ ), 0 , 149, 0 , 5840 , 282, 119), // #1018 - INST(Vinsertf32x4 , VexRvmi_Lx , E(660F3A,18,_,x,_,0,4,T4 ), 0 , 150, 0 , 5852 , 283, 122), // #1019 - INST(Vinsertf32x8 , VexRvmi , E(660F3A,1A,_,2,_,0,5,T8 ), 0 , 151, 0 , 5865 , 284, 61 ), // #1020 - INST(Vinsertf64x2 , VexRvmi_Lx , E(660F3A,18,_,x,_,1,4,T2 ), 0 , 152, 0 , 5878 , 283, 125), // #1021 - INST(Vinsertf64x4 , VexRvmi , E(660F3A,1A,_,2,_,1,5,T4 ), 0 , 153, 0 , 5891 , 284, 63 ), // #1022 - INST(Vinserti128 , VexRvmi , V(660F3A,38,_,1,0,_,_,_ ), 0 , 149, 0 , 5904 , 282, 126), // #1023 - INST(Vinserti32x4 , VexRvmi_Lx , E(660F3A,38,_,x,_,0,4,T4 ), 0 , 150, 0 , 5916 , 283, 122), // #1024 - INST(Vinserti32x8 , VexRvmi , E(660F3A,3A,_,2,_,0,5,T8 ), 0 , 151, 0 , 5929 , 284, 61 ), // #1025 - INST(Vinserti64x2 , VexRvmi_Lx , E(660F3A,38,_,x,_,1,4,T2 ), 0 , 152, 0 , 5942 , 283, 125), // #1026 - INST(Vinserti64x4 , VexRvmi , E(660F3A,3A,_,2,_,1,5,T4 ), 0 , 153, 0 , 5955 , 284, 63 ), // #1027 - INST(Vinsertps , VexRvmi , V(660F3A,21,_,0,I,0,2,T1S), 0 , 154, 0 , 5968 , 285, 118), // #1028 - INST(Vlddqu , VexRm_Lx , V(F20F00,F0,_,x,I,_,_,_ ), 0 , 101, 0 , 5978 , 286, 119), // #1029 - INST(Vldmxcsr , VexM , V(000F00,AE,2,0,I,_,_,_ ), 0 , 166, 0 , 5985 , 287, 119), // #1030 - INST(Vmaskmovdqu , VexRm_ZDI , V(660F00,F7,_,0,I,_,_,_ ), 0 , 63 , 0 , 5994 , 288, 119), // #1031 - INST(Vmaskmovpd , VexRvmMvr_Lx , V(660F38,2D,_,x,0,_,_,_ ), V(660F38,2F,_,x,0,_,_,_ ), 90 , 83 , 6006 , 289, 119), // #1032 - INST(Vmaskmovps , VexRvmMvr_Lx , V(660F38,2C,_,x,0,_,_,_ ), V(660F38,2E,_,x,0,_,_,_ ), 90 , 84 , 6017 , 289, 119), // #1033 - INST(Vmaxpd , VexRvm_Lx , V(660F00,5F,_,x,I,1,4,FV ), 0 , 97 , 0 , 6028 , 290, 117), // #1034 - INST(Vmaxps , VexRvm_Lx , V(000F00,5F,_,x,I,0,4,FV ), 0 , 98 , 0 , 6035 , 291, 117), // #1035 - INST(Vmaxsd , VexRvm , V(F20F00,5F,_,I,I,1,3,T1S), 0 , 99 , 0 , 6042 , 292, 117), // #1036 - INST(Vmaxss , VexRvm , V(F30F00,5F,_,I,I,0,2,T1S), 0 , 100, 0 , 6049 , 231, 117), // #1037 - INST(Vmcall , X86Op , O(000F01,C1,_,_,_,_,_,_ ), 0 , 21 , 0 , 6056 , 30 , 53 ), // #1038 - INST(Vmclear , X86M_Only , O(660F00,C7,6,_,_,_,_,_ ), 0 , 24 , 0 , 6063 , 293, 53 ), // #1039 - INST(Vmfunc , X86Op , O(000F01,D4,_,_,_,_,_,_ ), 0 , 21 , 0 , 6071 , 30 , 53 ), // #1040 - INST(Vminpd , VexRvm_Lx , V(660F00,5D,_,x,I,1,4,FV ), 0 , 97 , 0 , 6078 , 290, 117), // #1041 - INST(Vminps , VexRvm_Lx , V(000F00,5D,_,x,I,0,4,FV ), 0 , 98 , 0 , 6085 , 291, 117), // #1042 - INST(Vminsd , VexRvm , V(F20F00,5D,_,I,I,1,3,T1S), 0 , 99 , 0 , 6092 , 292, 117), // #1043 - INST(Vminss , VexRvm , V(F30F00,5D,_,I,I,0,2,T1S), 0 , 100, 0 , 6099 , 231, 117), // #1044 - INST(Vmlaunch , X86Op , O(000F01,C2,_,_,_,_,_,_ ), 0 , 21 , 0 , 6106 , 30 , 53 ), // #1045 - INST(Vmload , X86Op_xAX , O(000F01,DA,_,_,_,_,_,_ ), 0 , 21 , 0 , 6115 , 294, 22 ), // #1046 - INST(Vmmcall , X86Op , O(000F01,D9,_,_,_,_,_,_ ), 0 , 21 , 0 , 6122 , 30 , 22 ), // #1047 - INST(Vmovapd , VexRmMr_Lx , V(660F00,28,_,x,I,1,4,FVM), V(660F00,29,_,x,I,1,4,FVM), 167, 85 , 6130 , 295, 117), // #1048 - INST(Vmovaps , VexRmMr_Lx , V(000F00,28,_,x,I,0,4,FVM), V(000F00,29,_,x,I,0,4,FVM), 168, 86 , 6138 , 295, 117), // #1049 - INST(Vmovd , VexMovdMovq , V(660F00,6E,_,0,0,0,2,T1S), V(660F00,7E,_,0,0,0,2,T1S), 169, 87 , 6146 , 296, 118), // #1050 - INST(Vmovddup , VexRm_Lx , V(F20F00,12,_,x,I,1,3,DUP), 0 , 170, 0 , 6152 , 297, 117), // #1051 - INST(Vmovdqa , VexRmMr_Lx , V(660F00,6F,_,x,I,_,_,_ ), V(660F00,7F,_,x,I,_,_,_ ), 63 , 88 , 6161 , 298, 119), // #1052 - INST(Vmovdqa32 , VexRmMr_Lx , E(660F00,6F,_,x,_,0,4,FVM), E(660F00,7F,_,x,_,0,4,FVM), 171, 89 , 6169 , 299, 122), // #1053 - INST(Vmovdqa64 , VexRmMr_Lx , E(660F00,6F,_,x,_,1,4,FVM), E(660F00,7F,_,x,_,1,4,FVM), 172, 90 , 6179 , 299, 122), // #1054 - INST(Vmovdqu , VexRmMr_Lx , V(F30F00,6F,_,x,I,_,_,_ ), V(F30F00,7F,_,x,I,_,_,_ ), 173, 91 , 6189 , 298, 119), // #1055 - INST(Vmovdqu16 , VexRmMr_Lx , E(F20F00,6F,_,x,_,1,4,FVM), E(F20F00,7F,_,x,_,1,4,FVM), 174, 92 , 6197 , 299, 124), // #1056 - INST(Vmovdqu32 , VexRmMr_Lx , E(F30F00,6F,_,x,_,0,4,FVM), E(F30F00,7F,_,x,_,0,4,FVM), 175, 93 , 6207 , 299, 122), // #1057 - INST(Vmovdqu64 , VexRmMr_Lx , E(F30F00,6F,_,x,_,1,4,FVM), E(F30F00,7F,_,x,_,1,4,FVM), 176, 94 , 6217 , 299, 122), // #1058 - INST(Vmovdqu8 , VexRmMr_Lx , E(F20F00,6F,_,x,_,0,4,FVM), E(F20F00,7F,_,x,_,0,4,FVM), 177, 95 , 6227 , 299, 124), // #1059 - INST(Vmovhlps , VexRvm , V(000F00,12,_,0,I,0,_,_ ), 0 , 66 , 0 , 6236 , 300, 118), // #1060 - INST(Vmovhpd , VexRvmMr , V(660F00,16,_,0,I,1,3,T1S), V(660F00,17,_,0,I,1,3,T1S), 117, 96 , 6245 , 301, 118), // #1061 - INST(Vmovhps , VexRvmMr , V(000F00,16,_,0,I,0,3,T2 ), V(000F00,17,_,0,I,0,3,T2 ), 178, 97 , 6253 , 301, 118), // #1062 - INST(Vmovlhps , VexRvm , V(000F00,16,_,0,I,0,_,_ ), 0 , 66 , 0 , 6261 , 300, 118), // #1063 - INST(Vmovlpd , VexRvmMr , V(660F00,12,_,0,I,1,3,T1S), V(660F00,13,_,0,I,1,3,T1S), 117, 98 , 6270 , 301, 118), // #1064 - INST(Vmovlps , VexRvmMr , V(000F00,12,_,0,I,0,3,T2 ), V(000F00,13,_,0,I,0,3,T2 ), 178, 99 , 6278 , 301, 118), // #1065 - INST(Vmovmskpd , VexRm_Lx , V(660F00,50,_,x,I,_,_,_ ), 0 , 63 , 0 , 6286 , 302, 119), // #1066 - INST(Vmovmskps , VexRm_Lx , V(000F00,50,_,x,I,_,_,_ ), 0 , 66 , 0 , 6296 , 302, 119), // #1067 - INST(Vmovntdq , VexMr_Lx , V(660F00,E7,_,x,I,0,4,FVM), 0 , 179, 0 , 6306 , 303, 117), // #1068 - INST(Vmovntdqa , VexRm_Lx , V(660F38,2A,_,x,I,0,4,FVM), 0 , 102, 0 , 6315 , 304, 127), // #1069 - INST(Vmovntpd , VexMr_Lx , V(660F00,2B,_,x,I,1,4,FVM), 0 , 167, 0 , 6325 , 303, 117), // #1070 - INST(Vmovntps , VexMr_Lx , V(000F00,2B,_,x,I,0,4,FVM), 0 , 168, 0 , 6334 , 303, 117), // #1071 - INST(Vmovq , VexMovdMovq , V(660F00,6E,_,0,I,1,3,T1S), V(660F00,7E,_,0,I,1,3,T1S), 117, 100, 6343 , 305, 118), // #1072 - INST(Vmovsd , VexMovssMovsd , V(F20F00,10,_,I,I,1,3,T1S), V(F20F00,11,_,I,I,1,3,T1S), 99 , 101, 6349 , 306, 118), // #1073 - INST(Vmovshdup , VexRm_Lx , V(F30F00,16,_,x,I,0,4,FVM), 0 , 180, 0 , 6356 , 307, 117), // #1074 - INST(Vmovsldup , VexRm_Lx , V(F30F00,12,_,x,I,0,4,FVM), 0 , 180, 0 , 6366 , 307, 117), // #1075 - INST(Vmovss , VexMovssMovsd , V(F30F00,10,_,I,I,0,2,T1S), V(F30F00,11,_,I,I,0,2,T1S), 100, 102, 6376 , 308, 118), // #1076 - INST(Vmovupd , VexRmMr_Lx , V(660F00,10,_,x,I,1,4,FVM), V(660F00,11,_,x,I,1,4,FVM), 167, 103, 6383 , 295, 117), // #1077 - INST(Vmovups , VexRmMr_Lx , V(000F00,10,_,x,I,0,4,FVM), V(000F00,11,_,x,I,0,4,FVM), 168, 104, 6391 , 295, 117), // #1078 - INST(Vmpsadbw , VexRvmi_Lx , V(660F3A,42,_,x,I,_,_,_ ), 0 , 67 , 0 , 6399 , 201, 139), // #1079 - INST(Vmptrld , X86M_Only , O(000F00,C7,6,_,_,_,_,_ ), 0 , 73 , 0 , 6408 , 293, 53 ), // #1080 - INST(Vmptrst , X86M_Only , O(000F00,C7,7,_,_,_,_,_ ), 0 , 22 , 0 , 6416 , 293, 53 ), // #1081 - INST(Vmread , X86Mr_NoSize , O(000F00,78,_,_,_,_,_,_ ), 0 , 4 , 0 , 6424 , 309, 53 ), // #1082 - INST(Vmresume , X86Op , O(000F01,C3,_,_,_,_,_,_ ), 0 , 21 , 0 , 6431 , 30 , 53 ), // #1083 - INST(Vmrun , X86Op_xAX , O(000F01,D8,_,_,_,_,_,_ ), 0 , 21 , 0 , 6440 , 294, 22 ), // #1084 - INST(Vmsave , X86Op_xAX , O(000F01,DB,_,_,_,_,_,_ ), 0 , 21 , 0 , 6446 , 294, 22 ), // #1085 - INST(Vmulpd , VexRvm_Lx , V(660F00,59,_,x,I,1,4,FV ), 0 , 97 , 0 , 6453 , 184, 117), // #1086 - INST(Vmulps , VexRvm_Lx , V(000F00,59,_,x,I,0,4,FV ), 0 , 98 , 0 , 6460 , 185, 117), // #1087 - INST(Vmulsd , VexRvm_Lx , V(F20F00,59,_,I,I,1,3,T1S), 0 , 99 , 0 , 6467 , 186, 118), // #1088 - INST(Vmulss , VexRvm_Lx , V(F30F00,59,_,I,I,0,2,T1S), 0 , 100, 0 , 6474 , 187, 118), // #1089 - INST(Vmwrite , X86Rm_NoSize , O(000F00,79,_,_,_,_,_,_ ), 0 , 4 , 0 , 6481 , 310, 53 ), // #1090 - INST(Vmxon , X86M_Only , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 94 , 0 , 6489 , 293, 53 ), // #1091 - INST(Vorpd , VexRvm_Lx , V(660F00,56,_,x,I,1,4,FV ), 0 , 97 , 0 , 6495 , 196, 123), // #1092 - INST(Vorps , VexRvm_Lx , V(000F00,56,_,x,I,0,4,FV ), 0 , 98 , 0 , 6501 , 197, 123), // #1093 - INST(Vp2intersectd , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,0,4,FV ), 0 , 181, 0 , 6507 , 311, 140), // #1094 - INST(Vp2intersectq , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,1,4,FV ), 0 , 182, 0 , 6521 , 312, 140), // #1095 - INST(Vp4dpwssd , VexRm_T1_4X , E(F20F38,52,_,2,_,0,2,T4X), 0 , 96 , 0 , 6535 , 182, 141), // #1096 - INST(Vp4dpwssds , VexRm_T1_4X , E(F20F38,53,_,2,_,0,2,T4X), 0 , 96 , 0 , 6545 , 182, 141), // #1097 - INST(Vpabsb , VexRm_Lx , V(660F38,1C,_,x,I,_,4,FVM), 0 , 102, 0 , 6556 , 307, 142), // #1098 - INST(Vpabsd , VexRm_Lx , V(660F38,1E,_,x,I,0,4,FV ), 0 , 158, 0 , 6563 , 307, 127), // #1099 - INST(Vpabsq , VexRm_Lx , E(660F38,1F,_,x,_,1,4,FV ), 0 , 107, 0 , 6570 , 250, 122), // #1100 - INST(Vpabsw , VexRm_Lx , V(660F38,1D,_,x,I,_,4,FVM), 0 , 102, 0 , 6577 , 307, 142), // #1101 - INST(Vpackssdw , VexRvm_Lx , V(660F00,6B,_,x,I,0,4,FV ), 0 , 128, 0 , 6584 , 195, 142), // #1102 - INST(Vpacksswb , VexRvm_Lx , V(660F00,63,_,x,I,I,4,FVM), 0 , 179, 0 , 6594 , 281, 142), // #1103 - INST(Vpackusdw , VexRvm_Lx , V(660F38,2B,_,x,I,0,4,FV ), 0 , 158, 0 , 6604 , 195, 142), // #1104 - INST(Vpackuswb , VexRvm_Lx , V(660F00,67,_,x,I,I,4,FVM), 0 , 179, 0 , 6614 , 281, 142), // #1105 - INST(Vpaddb , VexRvm_Lx , V(660F00,FC,_,x,I,I,4,FVM), 0 , 179, 0 , 6624 , 281, 142), // #1106 - INST(Vpaddd , VexRvm_Lx , V(660F00,FE,_,x,I,0,4,FV ), 0 , 128, 0 , 6631 , 195, 127), // #1107 - INST(Vpaddq , VexRvm_Lx , V(660F00,D4,_,x,I,1,4,FV ), 0 , 97 , 0 , 6638 , 194, 127), // #1108 - INST(Vpaddsb , VexRvm_Lx , V(660F00,EC,_,x,I,I,4,FVM), 0 , 179, 0 , 6645 , 281, 142), // #1109 - INST(Vpaddsw , VexRvm_Lx , V(660F00,ED,_,x,I,I,4,FVM), 0 , 179, 0 , 6653 , 281, 142), // #1110 - INST(Vpaddusb , VexRvm_Lx , V(660F00,DC,_,x,I,I,4,FVM), 0 , 179, 0 , 6661 , 281, 142), // #1111 - INST(Vpaddusw , VexRvm_Lx , V(660F00,DD,_,x,I,I,4,FVM), 0 , 179, 0 , 6670 , 281, 142), // #1112 - INST(Vpaddw , VexRvm_Lx , V(660F00,FD,_,x,I,I,4,FVM), 0 , 179, 0 , 6679 , 281, 142), // #1113 - INST(Vpalignr , VexRvmi_Lx , V(660F3A,0F,_,x,I,I,4,FVM), 0 , 183, 0 , 6686 , 280, 142), // #1114 - INST(Vpand , VexRvm_Lx , V(660F00,DB,_,x,I,_,_,_ ), 0 , 63 , 0 , 6695 , 313, 139), // #1115 - INST(Vpandd , VexRvm_Lx , E(660F00,DB,_,x,_,0,4,FV ), 0 , 184, 0 , 6701 , 314, 122), // #1116 - INST(Vpandn , VexRvm_Lx , V(660F00,DF,_,x,I,_,_,_ ), 0 , 63 , 0 , 6708 , 315, 139), // #1117 - INST(Vpandnd , VexRvm_Lx , E(660F00,DF,_,x,_,0,4,FV ), 0 , 184, 0 , 6715 , 316, 122), // #1118 - INST(Vpandnq , VexRvm_Lx , E(660F00,DF,_,x,_,1,4,FV ), 0 , 125, 0 , 6723 , 317, 122), // #1119 - INST(Vpandq , VexRvm_Lx , E(660F00,DB,_,x,_,1,4,FV ), 0 , 125, 0 , 6731 , 318, 122), // #1120 - INST(Vpavgb , VexRvm_Lx , V(660F00,E0,_,x,I,I,4,FVM), 0 , 179, 0 , 6738 , 281, 142), // #1121 - INST(Vpavgw , VexRvm_Lx , V(660F00,E3,_,x,I,I,4,FVM), 0 , 179, 0 , 6745 , 281, 142), // #1122 - INST(Vpblendd , VexRvmi_Lx , V(660F3A,02,_,x,0,_,_,_ ), 0 , 67 , 0 , 6752 , 201, 126), // #1123 - INST(Vpblendvb , VexRvmr , V(660F3A,4C,_,x,0,_,_,_ ), 0 , 67 , 0 , 6761 , 202, 139), // #1124 - INST(Vpblendw , VexRvmi_Lx , V(660F3A,0E,_,x,I,_,_,_ ), 0 , 67 , 0 , 6771 , 201, 139), // #1125 - INST(Vpbroadcastb , VexRm_Lx_Bcst , V(660F38,78,_,x,0,0,0,T1S), E(660F38,7A,_,x,0,0,0,T1S), 185, 105, 6780 , 319, 143), // #1126 - INST(Vpbroadcastd , VexRm_Lx_Bcst , V(660F38,58,_,x,0,0,2,T1S), E(660F38,7C,_,x,0,0,0,T1S), 116, 106, 6793 , 320, 136), // #1127 - INST(Vpbroadcastmb2d , VexRm_Lx , E(F30F38,3A,_,x,_,0,_,_ ), 0 , 123, 0 , 6806 , 321, 144), // #1128 - INST(Vpbroadcastmb2q , VexRm_Lx , E(F30F38,2A,_,x,_,1,_,_ ), 0 , 186, 0 , 6822 , 321, 144), // #1129 - INST(Vpbroadcastq , VexRm_Lx_Bcst , V(660F38,59,_,x,0,1,3,T1S), E(660F38,7C,_,x,0,1,0,T1S), 115, 107, 6838 , 322, 136), // #1130 - INST(Vpbroadcastw , VexRm_Lx_Bcst , V(660F38,79,_,x,0,0,1,T1S), E(660F38,7B,_,x,0,0,0,T1S), 187, 108, 6851 , 323, 143), // #1131 - INST(Vpclmulqdq , VexRvmi_Lx , V(660F3A,44,_,x,I,_,4,FVM), 0 , 183, 0 , 6864 , 324, 145), // #1132 - INST(Vpcmov , VexRvrmRvmr_Lx , V(XOP_M8,A2,_,x,x,_,_,_ ), 0 , 188, 0 , 6875 , 259, 135), // #1133 - INST(Vpcmpb , VexRvmi_Lx , E(660F3A,3F,_,x,_,0,4,FVM), 0 , 146, 0 , 6882 , 325, 124), // #1134 - INST(Vpcmpd , VexRvmi_Lx , E(660F3A,1F,_,x,_,0,4,FV ), 0 , 103, 0 , 6889 , 326, 122), // #1135 - INST(Vpcmpeqb , VexRvm_Lx , V(660F00,74,_,x,I,I,4,FV ), 0 , 128, 0 , 6896 , 327, 142), // #1136 - INST(Vpcmpeqd , VexRvm_Lx , V(660F00,76,_,x,I,0,4,FVM), 0 , 179, 0 , 6905 , 328, 127), // #1137 - INST(Vpcmpeqq , VexRvm_Lx , V(660F38,29,_,x,I,1,4,FVM), 0 , 189, 0 , 6914 , 329, 127), // #1138 - INST(Vpcmpeqw , VexRvm_Lx , V(660F00,75,_,x,I,I,4,FV ), 0 , 128, 0 , 6923 , 327, 142), // #1139 - INST(Vpcmpestri , VexRmi , V(660F3A,61,_,0,I,_,_,_ ), 0 , 67 , 0 , 6932 , 330, 146), // #1140 - INST(Vpcmpestrm , VexRmi , V(660F3A,60,_,0,I,_,_,_ ), 0 , 67 , 0 , 6943 , 331, 146), // #1141 - INST(Vpcmpgtb , VexRvm_Lx , V(660F00,64,_,x,I,I,4,FV ), 0 , 128, 0 , 6954 , 327, 142), // #1142 - INST(Vpcmpgtd , VexRvm_Lx , V(660F00,66,_,x,I,0,4,FVM), 0 , 179, 0 , 6963 , 328, 127), // #1143 - INST(Vpcmpgtq , VexRvm_Lx , V(660F38,37,_,x,I,1,4,FVM), 0 , 189, 0 , 6972 , 329, 127), // #1144 - INST(Vpcmpgtw , VexRvm_Lx , V(660F00,65,_,x,I,I,4,FV ), 0 , 128, 0 , 6981 , 327, 142), // #1145 - INST(Vpcmpistri , VexRmi , V(660F3A,63,_,0,I,_,_,_ ), 0 , 67 , 0 , 6990 , 332, 146), // #1146 - INST(Vpcmpistrm , VexRmi , V(660F3A,62,_,0,I,_,_,_ ), 0 , 67 , 0 , 7001 , 333, 146), // #1147 - INST(Vpcmpq , VexRvmi_Lx , E(660F3A,1F,_,x,_,1,4,FV ), 0 , 104, 0 , 7012 , 334, 122), // #1148 - INST(Vpcmpub , VexRvmi_Lx , E(660F3A,3E,_,x,_,0,4,FVM), 0 , 146, 0 , 7019 , 325, 124), // #1149 - INST(Vpcmpud , VexRvmi_Lx , E(660F3A,1E,_,x,_,0,4,FV ), 0 , 103, 0 , 7027 , 326, 122), // #1150 - INST(Vpcmpuq , VexRvmi_Lx , E(660F3A,1E,_,x,_,1,4,FV ), 0 , 104, 0 , 7035 , 334, 122), // #1151 - INST(Vpcmpuw , VexRvmi_Lx , E(660F3A,3E,_,x,_,1,4,FVM), 0 , 190, 0 , 7043 , 334, 124), // #1152 - INST(Vpcmpw , VexRvmi_Lx , E(660F3A,3F,_,x,_,1,4,FVM), 0 , 190, 0 , 7051 , 334, 124), // #1153 - INST(Vpcomb , VexRvmi , V(XOP_M8,CC,_,0,0,_,_,_ ), 0 , 188, 0 , 7058 , 247, 135), // #1154 - INST(Vpcomd , VexRvmi , V(XOP_M8,CE,_,0,0,_,_,_ ), 0 , 188, 0 , 7065 , 247, 135), // #1155 - INST(Vpcompressb , VexMr_Lx , E(660F38,63,_,x,_,0,0,T1S), 0 , 191, 0 , 7072 , 216, 147), // #1156 - INST(Vpcompressd , VexMr_Lx , E(660F38,8B,_,x,_,0,2,T1S), 0 , 120, 0 , 7084 , 216, 122), // #1157 - INST(Vpcompressq , VexMr_Lx , E(660F38,8B,_,x,_,1,3,T1S), 0 , 119, 0 , 7096 , 216, 122), // #1158 - INST(Vpcompressw , VexMr_Lx , E(660F38,63,_,x,_,1,1,T1S), 0 , 192, 0 , 7108 , 216, 147), // #1159 - INST(Vpcomq , VexRvmi , V(XOP_M8,CF,_,0,0,_,_,_ ), 0 , 188, 0 , 7120 , 247, 135), // #1160 - INST(Vpcomub , VexRvmi , V(XOP_M8,EC,_,0,0,_,_,_ ), 0 , 188, 0 , 7127 , 247, 135), // #1161 - INST(Vpcomud , VexRvmi , V(XOP_M8,EE,_,0,0,_,_,_ ), 0 , 188, 0 , 7135 , 247, 135), // #1162 - INST(Vpcomuq , VexRvmi , V(XOP_M8,EF,_,0,0,_,_,_ ), 0 , 188, 0 , 7143 , 247, 135), // #1163 - INST(Vpcomuw , VexRvmi , V(XOP_M8,ED,_,0,0,_,_,_ ), 0 , 188, 0 , 7151 , 247, 135), // #1164 - INST(Vpcomw , VexRvmi , V(XOP_M8,CD,_,0,0,_,_,_ ), 0 , 188, 0 , 7159 , 247, 135), // #1165 - INST(Vpconflictd , VexRm_Lx , E(660F38,C4,_,x,_,0,4,FV ), 0 , 106, 0 , 7166 , 335, 144), // #1166 - INST(Vpconflictq , VexRm_Lx , E(660F38,C4,_,x,_,1,4,FV ), 0 , 107, 0 , 7178 , 335, 144), // #1167 - INST(Vpdpbusd , VexRvm_Lx , E(660F38,50,_,x,_,0,4,FV ), 0 , 106, 0 , 7190 , 199, 148), // #1168 - INST(Vpdpbusds , VexRvm_Lx , E(660F38,51,_,x,_,0,4,FV ), 0 , 106, 0 , 7199 , 199, 148), // #1169 - INST(Vpdpwssd , VexRvm_Lx , E(660F38,52,_,x,_,0,4,FV ), 0 , 106, 0 , 7209 , 199, 148), // #1170 - INST(Vpdpwssds , VexRvm_Lx , E(660F38,53,_,x,_,0,4,FV ), 0 , 106, 0 , 7218 , 199, 148), // #1171 - INST(Vperm2f128 , VexRvmi , V(660F3A,06,_,1,0,_,_,_ ), 0 , 149, 0 , 7228 , 336, 119), // #1172 - INST(Vperm2i128 , VexRvmi , V(660F3A,46,_,1,0,_,_,_ ), 0 , 149, 0 , 7239 , 336, 126), // #1173 - INST(Vpermb , VexRvm_Lx , E(660F38,8D,_,x,_,0,4,FVM), 0 , 105, 0 , 7250 , 198, 149), // #1174 - INST(Vpermd , VexRvm_Lx , V(660F38,36,_,x,0,0,4,FV ), 0 , 158, 0 , 7257 , 337, 136), // #1175 - INST(Vpermi2b , VexRvm_Lx , E(660F38,75,_,x,_,0,4,FVM), 0 , 105, 0 , 7264 , 198, 149), // #1176 - INST(Vpermi2d , VexRvm_Lx , E(660F38,76,_,x,_,0,4,FV ), 0 , 106, 0 , 7273 , 199, 122), // #1177 - INST(Vpermi2pd , VexRvm_Lx , E(660F38,77,_,x,_,1,4,FV ), 0 , 107, 0 , 7282 , 200, 122), // #1178 - INST(Vpermi2ps , VexRvm_Lx , E(660F38,77,_,x,_,0,4,FV ), 0 , 106, 0 , 7292 , 199, 122), // #1179 - INST(Vpermi2q , VexRvm_Lx , E(660F38,76,_,x,_,1,4,FV ), 0 , 107, 0 , 7302 , 200, 122), // #1180 - INST(Vpermi2w , VexRvm_Lx , E(660F38,75,_,x,_,1,4,FVM), 0 , 108, 0 , 7311 , 198, 124), // #1181 - INST(Vpermil2pd , VexRvrmiRvmri_Lx , V(660F3A,49,_,x,x,_,_,_ ), 0 , 67 , 0 , 7320 , 338, 135), // #1182 - INST(Vpermil2ps , VexRvrmiRvmri_Lx , V(660F3A,48,_,x,x,_,_,_ ), 0 , 67 , 0 , 7331 , 338, 135), // #1183 - INST(Vpermilpd , VexRvmRmi_Lx , V(660F38,0D,_,x,0,1,4,FV ), V(660F3A,05,_,x,0,1,4,FV ), 193, 109, 7342 , 339, 117), // #1184 - INST(Vpermilps , VexRvmRmi_Lx , V(660F38,0C,_,x,0,0,4,FV ), V(660F3A,04,_,x,0,0,4,FV ), 158, 110, 7352 , 339, 117), // #1185 - INST(Vpermpd , VexRvmRmi_Lx , E(660F38,16,_,x,1,1,4,FV ), V(660F3A,01,_,x,1,1,4,FV ), 194, 111, 7362 , 340, 136), // #1186 - INST(Vpermps , VexRvm_Lx , V(660F38,16,_,x,0,0,4,FV ), 0 , 158, 0 , 7370 , 337, 136), // #1187 - INST(Vpermq , VexRvmRmi_Lx , V(660F38,36,_,x,_,1,4,FV ), V(660F3A,00,_,x,1,1,4,FV ), 193, 112, 7378 , 340, 136), // #1188 - INST(Vpermt2b , VexRvm_Lx , E(660F38,7D,_,x,_,0,4,FVM), 0 , 105, 0 , 7385 , 198, 149), // #1189 - INST(Vpermt2d , VexRvm_Lx , E(660F38,7E,_,x,_,0,4,FV ), 0 , 106, 0 , 7394 , 199, 122), // #1190 - INST(Vpermt2pd , VexRvm_Lx , E(660F38,7F,_,x,_,1,4,FV ), 0 , 107, 0 , 7403 , 200, 122), // #1191 - INST(Vpermt2ps , VexRvm_Lx , E(660F38,7F,_,x,_,0,4,FV ), 0 , 106, 0 , 7413 , 199, 122), // #1192 - INST(Vpermt2q , VexRvm_Lx , E(660F38,7E,_,x,_,1,4,FV ), 0 , 107, 0 , 7423 , 200, 122), // #1193 - INST(Vpermt2w , VexRvm_Lx , E(660F38,7D,_,x,_,1,4,FVM), 0 , 108, 0 , 7432 , 198, 124), // #1194 - INST(Vpermw , VexRvm_Lx , E(660F38,8D,_,x,_,1,4,FVM), 0 , 108, 0 , 7441 , 198, 124), // #1195 - INST(Vpexpandb , VexRm_Lx , E(660F38,62,_,x,_,0,0,T1S), 0 , 191, 0 , 7448 , 250, 147), // #1196 - INST(Vpexpandd , VexRm_Lx , E(660F38,89,_,x,_,0,2,T1S), 0 , 120, 0 , 7458 , 250, 122), // #1197 - INST(Vpexpandq , VexRm_Lx , E(660F38,89,_,x,_,1,3,T1S), 0 , 119, 0 , 7468 , 250, 122), // #1198 - INST(Vpexpandw , VexRm_Lx , E(660F38,62,_,x,_,1,1,T1S), 0 , 192, 0 , 7478 , 250, 147), // #1199 - INST(Vpextrb , VexMri , V(660F3A,14,_,0,0,I,0,T1S), 0 , 195, 0 , 7488 , 341, 150), // #1200 - INST(Vpextrd , VexMri , V(660F3A,16,_,0,0,0,2,T1S), 0 , 154, 0 , 7496 , 254, 151), // #1201 - INST(Vpextrq , VexMri , V(660F3A,16,_,0,1,1,3,T1S), 0 , 196, 0 , 7504 , 342, 151), // #1202 - INST(Vpextrw , VexMri , V(660F3A,15,_,0,0,I,1,T1S), 0 , 197, 0 , 7512 , 343, 150), // #1203 - INST(Vpgatherdd , VexRmvRm_VM , V(660F38,90,_,x,0,_,_,_ ), V(660F38,90,_,x,_,0,2,T1S), 90 , 113, 7520 , 270, 136), // #1204 - INST(Vpgatherdq , VexRmvRm_VM , V(660F38,90,_,x,1,_,_,_ ), V(660F38,90,_,x,_,1,3,T1S), 160, 114, 7531 , 269, 136), // #1205 - INST(Vpgatherqd , VexRmvRm_VM , V(660F38,91,_,x,0,_,_,_ ), V(660F38,91,_,x,_,0,2,T1S), 90 , 115, 7542 , 275, 136), // #1206 - INST(Vpgatherqq , VexRmvRm_VM , V(660F38,91,_,x,1,_,_,_ ), V(660F38,91,_,x,_,1,3,T1S), 160, 116, 7553 , 274, 136), // #1207 - INST(Vphaddbd , VexRm , V(XOP_M9,C2,_,0,0,_,_,_ ), 0 , 72 , 0 , 7564 , 190, 135), // #1208 - INST(Vphaddbq , VexRm , V(XOP_M9,C3,_,0,0,_,_,_ ), 0 , 72 , 0 , 7573 , 190, 135), // #1209 - INST(Vphaddbw , VexRm , V(XOP_M9,C1,_,0,0,_,_,_ ), 0 , 72 , 0 , 7582 , 190, 135), // #1210 - INST(Vphaddd , VexRvm_Lx , V(660F38,02,_,x,I,_,_,_ ), 0 , 90 , 0 , 7591 , 188, 139), // #1211 - INST(Vphadddq , VexRm , V(XOP_M9,CB,_,0,0,_,_,_ ), 0 , 72 , 0 , 7599 , 190, 135), // #1212 - INST(Vphaddsw , VexRvm_Lx , V(660F38,03,_,x,I,_,_,_ ), 0 , 90 , 0 , 7608 , 188, 139), // #1213 - INST(Vphaddubd , VexRm , V(XOP_M9,D2,_,0,0,_,_,_ ), 0 , 72 , 0 , 7617 , 190, 135), // #1214 - INST(Vphaddubq , VexRm , V(XOP_M9,D3,_,0,0,_,_,_ ), 0 , 72 , 0 , 7627 , 190, 135), // #1215 - INST(Vphaddubw , VexRm , V(XOP_M9,D1,_,0,0,_,_,_ ), 0 , 72 , 0 , 7637 , 190, 135), // #1216 - INST(Vphaddudq , VexRm , V(XOP_M9,DB,_,0,0,_,_,_ ), 0 , 72 , 0 , 7647 , 190, 135), // #1217 - INST(Vphadduwd , VexRm , V(XOP_M9,D6,_,0,0,_,_,_ ), 0 , 72 , 0 , 7657 , 190, 135), // #1218 - INST(Vphadduwq , VexRm , V(XOP_M9,D7,_,0,0,_,_,_ ), 0 , 72 , 0 , 7667 , 190, 135), // #1219 - INST(Vphaddw , VexRvm_Lx , V(660F38,01,_,x,I,_,_,_ ), 0 , 90 , 0 , 7677 , 188, 139), // #1220 - INST(Vphaddwd , VexRm , V(XOP_M9,C6,_,0,0,_,_,_ ), 0 , 72 , 0 , 7685 , 190, 135), // #1221 - INST(Vphaddwq , VexRm , V(XOP_M9,C7,_,0,0,_,_,_ ), 0 , 72 , 0 , 7694 , 190, 135), // #1222 - INST(Vphminposuw , VexRm , V(660F38,41,_,0,I,_,_,_ ), 0 , 90 , 0 , 7703 , 190, 119), // #1223 - INST(Vphsubbw , VexRm , V(XOP_M9,E1,_,0,0,_,_,_ ), 0 , 72 , 0 , 7715 , 190, 135), // #1224 - INST(Vphsubd , VexRvm_Lx , V(660F38,06,_,x,I,_,_,_ ), 0 , 90 , 0 , 7724 , 188, 139), // #1225 - INST(Vphsubdq , VexRm , V(XOP_M9,E3,_,0,0,_,_,_ ), 0 , 72 , 0 , 7732 , 190, 135), // #1226 - INST(Vphsubsw , VexRvm_Lx , V(660F38,07,_,x,I,_,_,_ ), 0 , 90 , 0 , 7741 , 188, 139), // #1227 - INST(Vphsubw , VexRvm_Lx , V(660F38,05,_,x,I,_,_,_ ), 0 , 90 , 0 , 7750 , 188, 139), // #1228 - INST(Vphsubwd , VexRm , V(XOP_M9,E2,_,0,0,_,_,_ ), 0 , 72 , 0 , 7758 , 190, 135), // #1229 - INST(Vpinsrb , VexRvmi , V(660F3A,20,_,0,0,I,0,T1S), 0 , 195, 0 , 7767 , 344, 150), // #1230 - INST(Vpinsrd , VexRvmi , V(660F3A,22,_,0,0,0,2,T1S), 0 , 154, 0 , 7775 , 345, 151), // #1231 - INST(Vpinsrq , VexRvmi , V(660F3A,22,_,0,1,1,3,T1S), 0 , 196, 0 , 7783 , 346, 151), // #1232 - INST(Vpinsrw , VexRvmi , V(660F00,C4,_,0,0,I,1,T1S), 0 , 198, 0 , 7791 , 347, 150), // #1233 - INST(Vplzcntd , VexRm_Lx , E(660F38,44,_,x,_,0,4,FV ), 0 , 106, 0 , 7799 , 335, 144), // #1234 - INST(Vplzcntq , VexRm_Lx , E(660F38,44,_,x,_,1,4,FV ), 0 , 107, 0 , 7808 , 348, 144), // #1235 - INST(Vpmacsdd , VexRvmr , V(XOP_M8,9E,_,0,0,_,_,_ ), 0 , 188, 0 , 7817 , 349, 135), // #1236 - INST(Vpmacsdqh , VexRvmr , V(XOP_M8,9F,_,0,0,_,_,_ ), 0 , 188, 0 , 7826 , 349, 135), // #1237 - INST(Vpmacsdql , VexRvmr , V(XOP_M8,97,_,0,0,_,_,_ ), 0 , 188, 0 , 7836 , 349, 135), // #1238 - INST(Vpmacssdd , VexRvmr , V(XOP_M8,8E,_,0,0,_,_,_ ), 0 , 188, 0 , 7846 , 349, 135), // #1239 - INST(Vpmacssdqh , VexRvmr , V(XOP_M8,8F,_,0,0,_,_,_ ), 0 , 188, 0 , 7856 , 349, 135), // #1240 - INST(Vpmacssdql , VexRvmr , V(XOP_M8,87,_,0,0,_,_,_ ), 0 , 188, 0 , 7867 , 349, 135), // #1241 - INST(Vpmacsswd , VexRvmr , V(XOP_M8,86,_,0,0,_,_,_ ), 0 , 188, 0 , 7878 , 349, 135), // #1242 - INST(Vpmacssww , VexRvmr , V(XOP_M8,85,_,0,0,_,_,_ ), 0 , 188, 0 , 7888 , 349, 135), // #1243 - INST(Vpmacswd , VexRvmr , V(XOP_M8,96,_,0,0,_,_,_ ), 0 , 188, 0 , 7898 , 349, 135), // #1244 - INST(Vpmacsww , VexRvmr , V(XOP_M8,95,_,0,0,_,_,_ ), 0 , 188, 0 , 7907 , 349, 135), // #1245 - INST(Vpmadcsswd , VexRvmr , V(XOP_M8,A6,_,0,0,_,_,_ ), 0 , 188, 0 , 7916 , 349, 135), // #1246 - INST(Vpmadcswd , VexRvmr , V(XOP_M8,B6,_,0,0,_,_,_ ), 0 , 188, 0 , 7927 , 349, 135), // #1247 - INST(Vpmadd52huq , VexRvm_Lx , E(660F38,B5,_,x,_,1,4,FV ), 0 , 107, 0 , 7937 , 200, 152), // #1248 - INST(Vpmadd52luq , VexRvm_Lx , E(660F38,B4,_,x,_,1,4,FV ), 0 , 107, 0 , 7949 , 200, 152), // #1249 - INST(Vpmaddubsw , VexRvm_Lx , V(660F38,04,_,x,I,I,4,FVM), 0 , 102, 0 , 7961 , 281, 142), // #1250 - INST(Vpmaddwd , VexRvm_Lx , V(660F00,F5,_,x,I,I,4,FVM), 0 , 179, 0 , 7972 , 281, 142), // #1251 - INST(Vpmaskmovd , VexRvmMvr_Lx , V(660F38,8C,_,x,0,_,_,_ ), V(660F38,8E,_,x,0,_,_,_ ), 90 , 117, 7981 , 289, 126), // #1252 - INST(Vpmaskmovq , VexRvmMvr_Lx , V(660F38,8C,_,x,1,_,_,_ ), V(660F38,8E,_,x,1,_,_,_ ), 160, 118, 7992 , 289, 126), // #1253 - INST(Vpmaxsb , VexRvm_Lx , V(660F38,3C,_,x,I,I,4,FVM), 0 , 102, 0 , 8003 , 350, 142), // #1254 - INST(Vpmaxsd , VexRvm_Lx , V(660F38,3D,_,x,I,0,4,FV ), 0 , 158, 0 , 8011 , 197, 127), // #1255 - INST(Vpmaxsq , VexRvm_Lx , E(660F38,3D,_,x,_,1,4,FV ), 0 , 107, 0 , 8019 , 200, 122), // #1256 - INST(Vpmaxsw , VexRvm_Lx , V(660F00,EE,_,x,I,I,4,FVM), 0 , 179, 0 , 8027 , 350, 142), // #1257 - INST(Vpmaxub , VexRvm_Lx , V(660F00,DE,_,x,I,I,4,FVM), 0 , 179, 0 , 8035 , 350, 142), // #1258 - INST(Vpmaxud , VexRvm_Lx , V(660F38,3F,_,x,I,0,4,FV ), 0 , 158, 0 , 8043 , 197, 127), // #1259 - INST(Vpmaxuq , VexRvm_Lx , E(660F38,3F,_,x,_,1,4,FV ), 0 , 107, 0 , 8051 , 200, 122), // #1260 - INST(Vpmaxuw , VexRvm_Lx , V(660F38,3E,_,x,I,I,4,FVM), 0 , 102, 0 , 8059 , 350, 142), // #1261 - INST(Vpminsb , VexRvm_Lx , V(660F38,38,_,x,I,I,4,FVM), 0 , 102, 0 , 8067 , 350, 142), // #1262 - INST(Vpminsd , VexRvm_Lx , V(660F38,39,_,x,I,0,4,FV ), 0 , 158, 0 , 8075 , 197, 127), // #1263 - INST(Vpminsq , VexRvm_Lx , E(660F38,39,_,x,_,1,4,FV ), 0 , 107, 0 , 8083 , 200, 122), // #1264 - INST(Vpminsw , VexRvm_Lx , V(660F00,EA,_,x,I,I,4,FVM), 0 , 179, 0 , 8091 , 350, 142), // #1265 - INST(Vpminub , VexRvm_Lx , V(660F00,DA,_,x,I,_,4,FVM), 0 , 179, 0 , 8099 , 350, 142), // #1266 - INST(Vpminud , VexRvm_Lx , V(660F38,3B,_,x,I,0,4,FV ), 0 , 158, 0 , 8107 , 197, 127), // #1267 - INST(Vpminuq , VexRvm_Lx , E(660F38,3B,_,x,_,1,4,FV ), 0 , 107, 0 , 8115 , 200, 122), // #1268 - INST(Vpminuw , VexRvm_Lx , V(660F38,3A,_,x,I,_,4,FVM), 0 , 102, 0 , 8123 , 350, 142), // #1269 - INST(Vpmovb2m , VexRm_Lx , E(F30F38,29,_,x,_,0,_,_ ), 0 , 123, 0 , 8131 , 351, 124), // #1270 - INST(Vpmovd2m , VexRm_Lx , E(F30F38,39,_,x,_,0,_,_ ), 0 , 123, 0 , 8140 , 351, 125), // #1271 - INST(Vpmovdb , VexMr_Lx , E(F30F38,31,_,x,_,0,2,QVM), 0 , 199, 0 , 8149 , 352, 122), // #1272 - INST(Vpmovdw , VexMr_Lx , E(F30F38,33,_,x,_,0,3,HVM), 0 , 200, 0 , 8157 , 353, 122), // #1273 - INST(Vpmovm2b , VexRm_Lx , E(F30F38,28,_,x,_,0,_,_ ), 0 , 123, 0 , 8165 , 321, 124), // #1274 - INST(Vpmovm2d , VexRm_Lx , E(F30F38,38,_,x,_,0,_,_ ), 0 , 123, 0 , 8174 , 321, 125), // #1275 - INST(Vpmovm2q , VexRm_Lx , E(F30F38,38,_,x,_,1,_,_ ), 0 , 186, 0 , 8183 , 321, 125), // #1276 - INST(Vpmovm2w , VexRm_Lx , E(F30F38,28,_,x,_,1,_,_ ), 0 , 186, 0 , 8192 , 321, 124), // #1277 - INST(Vpmovmskb , VexRm_Lx , V(660F00,D7,_,x,I,_,_,_ ), 0 , 63 , 0 , 8201 , 302, 139), // #1278 - INST(Vpmovq2m , VexRm_Lx , E(F30F38,39,_,x,_,1,_,_ ), 0 , 186, 0 , 8211 , 351, 125), // #1279 - INST(Vpmovqb , VexMr_Lx , E(F30F38,32,_,x,_,0,1,OVM), 0 , 201, 0 , 8220 , 354, 122), // #1280 - INST(Vpmovqd , VexMr_Lx , E(F30F38,35,_,x,_,0,3,HVM), 0 , 200, 0 , 8228 , 353, 122), // #1281 - INST(Vpmovqw , VexMr_Lx , E(F30F38,34,_,x,_,0,2,QVM), 0 , 199, 0 , 8236 , 352, 122), // #1282 - INST(Vpmovsdb , VexMr_Lx , E(F30F38,21,_,x,_,0,2,QVM), 0 , 199, 0 , 8244 , 352, 122), // #1283 - INST(Vpmovsdw , VexMr_Lx , E(F30F38,23,_,x,_,0,3,HVM), 0 , 200, 0 , 8253 , 353, 122), // #1284 - INST(Vpmovsqb , VexMr_Lx , E(F30F38,22,_,x,_,0,1,OVM), 0 , 201, 0 , 8262 , 354, 122), // #1285 - INST(Vpmovsqd , VexMr_Lx , E(F30F38,25,_,x,_,0,3,HVM), 0 , 200, 0 , 8271 , 353, 122), // #1286 - INST(Vpmovsqw , VexMr_Lx , E(F30F38,24,_,x,_,0,2,QVM), 0 , 199, 0 , 8280 , 352, 122), // #1287 - INST(Vpmovswb , VexMr_Lx , E(F30F38,20,_,x,_,0,3,HVM), 0 , 200, 0 , 8289 , 353, 124), // #1288 - INST(Vpmovsxbd , VexRm_Lx , V(660F38,21,_,x,I,I,2,QVM), 0 , 202, 0 , 8298 , 355, 127), // #1289 - INST(Vpmovsxbq , VexRm_Lx , V(660F38,22,_,x,I,I,1,OVM), 0 , 203, 0 , 8308 , 356, 127), // #1290 - INST(Vpmovsxbw , VexRm_Lx , V(660F38,20,_,x,I,I,3,HVM), 0 , 127, 0 , 8318 , 357, 142), // #1291 - INST(Vpmovsxdq , VexRm_Lx , V(660F38,25,_,x,I,0,3,HVM), 0 , 127, 0 , 8328 , 357, 127), // #1292 - INST(Vpmovsxwd , VexRm_Lx , V(660F38,23,_,x,I,I,3,HVM), 0 , 127, 0 , 8338 , 357, 127), // #1293 - INST(Vpmovsxwq , VexRm_Lx , V(660F38,24,_,x,I,I,2,QVM), 0 , 202, 0 , 8348 , 355, 127), // #1294 - INST(Vpmovusdb , VexMr_Lx , E(F30F38,11,_,x,_,0,2,QVM), 0 , 199, 0 , 8358 , 352, 122), // #1295 - INST(Vpmovusdw , VexMr_Lx , E(F30F38,13,_,x,_,0,3,HVM), 0 , 200, 0 , 8368 , 353, 122), // #1296 - INST(Vpmovusqb , VexMr_Lx , E(F30F38,12,_,x,_,0,1,OVM), 0 , 201, 0 , 8378 , 354, 122), // #1297 - INST(Vpmovusqd , VexMr_Lx , E(F30F38,15,_,x,_,0,3,HVM), 0 , 200, 0 , 8388 , 353, 122), // #1298 - INST(Vpmovusqw , VexMr_Lx , E(F30F38,14,_,x,_,0,2,QVM), 0 , 199, 0 , 8398 , 352, 122), // #1299 - INST(Vpmovuswb , VexMr_Lx , E(F30F38,10,_,x,_,0,3,HVM), 0 , 200, 0 , 8408 , 353, 124), // #1300 - INST(Vpmovw2m , VexRm_Lx , E(F30F38,29,_,x,_,1,_,_ ), 0 , 186, 0 , 8418 , 351, 124), // #1301 - INST(Vpmovwb , VexMr_Lx , E(F30F38,30,_,x,_,0,3,HVM), 0 , 200, 0 , 8427 , 353, 124), // #1302 - INST(Vpmovzxbd , VexRm_Lx , V(660F38,31,_,x,I,I,2,QVM), 0 , 202, 0 , 8435 , 355, 127), // #1303 - INST(Vpmovzxbq , VexRm_Lx , V(660F38,32,_,x,I,I,1,OVM), 0 , 203, 0 , 8445 , 356, 127), // #1304 - INST(Vpmovzxbw , VexRm_Lx , V(660F38,30,_,x,I,I,3,HVM), 0 , 127, 0 , 8455 , 357, 142), // #1305 - INST(Vpmovzxdq , VexRm_Lx , V(660F38,35,_,x,I,0,3,HVM), 0 , 127, 0 , 8465 , 357, 127), // #1306 - INST(Vpmovzxwd , VexRm_Lx , V(660F38,33,_,x,I,I,3,HVM), 0 , 127, 0 , 8475 , 357, 127), // #1307 - INST(Vpmovzxwq , VexRm_Lx , V(660F38,34,_,x,I,I,2,QVM), 0 , 202, 0 , 8485 , 355, 127), // #1308 - INST(Vpmuldq , VexRvm_Lx , V(660F38,28,_,x,I,1,4,FV ), 0 , 193, 0 , 8495 , 194, 127), // #1309 - INST(Vpmulhrsw , VexRvm_Lx , V(660F38,0B,_,x,I,I,4,FVM), 0 , 102, 0 , 8503 , 281, 142), // #1310 - INST(Vpmulhuw , VexRvm_Lx , V(660F00,E4,_,x,I,I,4,FVM), 0 , 179, 0 , 8513 , 281, 142), // #1311 - INST(Vpmulhw , VexRvm_Lx , V(660F00,E5,_,x,I,I,4,FVM), 0 , 179, 0 , 8522 , 281, 142), // #1312 - INST(Vpmulld , VexRvm_Lx , V(660F38,40,_,x,I,0,4,FV ), 0 , 158, 0 , 8530 , 195, 127), // #1313 - INST(Vpmullq , VexRvm_Lx , E(660F38,40,_,x,_,1,4,FV ), 0 , 107, 0 , 8538 , 200, 125), // #1314 - INST(Vpmullw , VexRvm_Lx , V(660F00,D5,_,x,I,I,4,FVM), 0 , 179, 0 , 8546 , 281, 142), // #1315 - INST(Vpmultishiftqb , VexRvm_Lx , E(660F38,83,_,x,_,1,4,FV ), 0 , 107, 0 , 8554 , 200, 149), // #1316 - INST(Vpmuludq , VexRvm_Lx , V(660F00,F4,_,x,I,1,4,FV ), 0 , 97 , 0 , 8569 , 194, 127), // #1317 - INST(Vpopcntb , VexRm_Lx , E(660F38,54,_,x,_,0,4,FV ), 0 , 106, 0 , 8578 , 250, 153), // #1318 - INST(Vpopcntd , VexRm_Lx , E(660F38,55,_,x,_,0,4,FVM), 0 , 105, 0 , 8587 , 335, 154), // #1319 - INST(Vpopcntq , VexRm_Lx , E(660F38,55,_,x,_,1,4,FVM), 0 , 108, 0 , 8596 , 348, 154), // #1320 - INST(Vpopcntw , VexRm_Lx , E(660F38,54,_,x,_,1,4,FV ), 0 , 107, 0 , 8605 , 250, 153), // #1321 - INST(Vpor , VexRvm_Lx , V(660F00,EB,_,x,I,_,_,_ ), 0 , 63 , 0 , 8614 , 313, 139), // #1322 - INST(Vpord , VexRvm_Lx , E(660F00,EB,_,x,_,0,4,FV ), 0 , 184, 0 , 8619 , 314, 122), // #1323 - INST(Vporq , VexRvm_Lx , E(660F00,EB,_,x,_,1,4,FV ), 0 , 125, 0 , 8625 , 318, 122), // #1324 - INST(Vpperm , VexRvrmRvmr , V(XOP_M8,A3,_,0,x,_,_,_ ), 0 , 188, 0 , 8631 , 358, 135), // #1325 - INST(Vprold , VexVmi_Lx , E(660F00,72,1,x,_,0,4,FV ), 0 , 204, 0 , 8638 , 359, 122), // #1326 - INST(Vprolq , VexVmi_Lx , E(660F00,72,1,x,_,1,4,FV ), 0 , 205, 0 , 8645 , 360, 122), // #1327 - INST(Vprolvd , VexRvm_Lx , E(660F38,15,_,x,_,0,4,FV ), 0 , 106, 0 , 8652 , 199, 122), // #1328 - INST(Vprolvq , VexRvm_Lx , E(660F38,15,_,x,_,1,4,FV ), 0 , 107, 0 , 8660 , 200, 122), // #1329 - INST(Vprord , VexVmi_Lx , E(660F00,72,0,x,_,0,4,FV ), 0 , 184, 0 , 8668 , 359, 122), // #1330 - INST(Vprorq , VexVmi_Lx , E(660F00,72,0,x,_,1,4,FV ), 0 , 125, 0 , 8675 , 360, 122), // #1331 - INST(Vprorvd , VexRvm_Lx , E(660F38,14,_,x,_,0,4,FV ), 0 , 106, 0 , 8682 , 199, 122), // #1332 - INST(Vprorvq , VexRvm_Lx , E(660F38,14,_,x,_,1,4,FV ), 0 , 107, 0 , 8690 , 200, 122), // #1333 - INST(Vprotb , VexRvmRmvRmi , V(XOP_M9,90,_,0,x,_,_,_ ), V(XOP_M8,C0,_,0,x,_,_,_ ), 72 , 119, 8698 , 361, 135), // #1334 - INST(Vprotd , VexRvmRmvRmi , V(XOP_M9,92,_,0,x,_,_,_ ), V(XOP_M8,C2,_,0,x,_,_,_ ), 72 , 120, 8705 , 361, 135), // #1335 - INST(Vprotq , VexRvmRmvRmi , V(XOP_M9,93,_,0,x,_,_,_ ), V(XOP_M8,C3,_,0,x,_,_,_ ), 72 , 121, 8712 , 361, 135), // #1336 - INST(Vprotw , VexRvmRmvRmi , V(XOP_M9,91,_,0,x,_,_,_ ), V(XOP_M8,C1,_,0,x,_,_,_ ), 72 , 122, 8719 , 361, 135), // #1337 - INST(Vpsadbw , VexRvm_Lx , V(660F00,F6,_,x,I,I,4,FVM), 0 , 179, 0 , 8726 , 189, 142), // #1338 - INST(Vpscatterdd , VexMr_VM , E(660F38,A0,_,x,_,0,2,T1S), 0 , 120, 0 , 8734 , 362, 122), // #1339 - INST(Vpscatterdq , VexMr_VM , E(660F38,A0,_,x,_,1,3,T1S), 0 , 119, 0 , 8746 , 362, 122), // #1340 - INST(Vpscatterqd , VexMr_VM , E(660F38,A1,_,x,_,0,2,T1S), 0 , 120, 0 , 8758 , 363, 122), // #1341 - INST(Vpscatterqq , VexMr_VM , E(660F38,A1,_,x,_,1,3,T1S), 0 , 119, 0 , 8770 , 364, 122), // #1342 - INST(Vpshab , VexRvmRmv , V(XOP_M9,98,_,0,x,_,_,_ ), 0 , 72 , 0 , 8782 , 365, 135), // #1343 - INST(Vpshad , VexRvmRmv , V(XOP_M9,9A,_,0,x,_,_,_ ), 0 , 72 , 0 , 8789 , 365, 135), // #1344 - INST(Vpshaq , VexRvmRmv , V(XOP_M9,9B,_,0,x,_,_,_ ), 0 , 72 , 0 , 8796 , 365, 135), // #1345 - INST(Vpshaw , VexRvmRmv , V(XOP_M9,99,_,0,x,_,_,_ ), 0 , 72 , 0 , 8803 , 365, 135), // #1346 - INST(Vpshlb , VexRvmRmv , V(XOP_M9,94,_,0,x,_,_,_ ), 0 , 72 , 0 , 8810 , 365, 135), // #1347 - INST(Vpshld , VexRvmRmv , V(XOP_M9,96,_,0,x,_,_,_ ), 0 , 72 , 0 , 8817 , 365, 135), // #1348 - INST(Vpshldd , VexRvmi_Lx , E(660F3A,71,_,x,_,0,4,FV ), 0 , 103, 0 , 8824 , 192, 147), // #1349 - INST(Vpshldq , VexRvmi_Lx , E(660F3A,71,_,x,_,1,4,FV ), 0 , 104, 0 , 8832 , 193, 147), // #1350 - INST(Vpshldvd , VexRvm_Lx , E(660F38,71,_,x,_,0,4,FV ), 0 , 106, 0 , 8840 , 199, 147), // #1351 - INST(Vpshldvq , VexRvm_Lx , E(660F38,71,_,x,_,1,4,FV ), 0 , 107, 0 , 8849 , 200, 147), // #1352 - INST(Vpshldvw , VexRvm_Lx , E(660F38,70,_,x,_,0,4,FVM), 0 , 105, 0 , 8858 , 198, 147), // #1353 - INST(Vpshldw , VexRvmi_Lx , E(660F3A,70,_,x,_,0,4,FVM), 0 , 146, 0 , 8867 , 246, 147), // #1354 - INST(Vpshlq , VexRvmRmv , V(XOP_M9,97,_,0,x,_,_,_ ), 0 , 72 , 0 , 8875 , 365, 135), // #1355 - INST(Vpshlw , VexRvmRmv , V(XOP_M9,95,_,0,x,_,_,_ ), 0 , 72 , 0 , 8882 , 365, 135), // #1356 - INST(Vpshrdd , VexRvmi_Lx , E(660F3A,73,_,x,_,0,4,FV ), 0 , 103, 0 , 8889 , 192, 147), // #1357 - INST(Vpshrdq , VexRvmi_Lx , E(660F3A,73,_,x,_,1,4,FV ), 0 , 104, 0 , 8897 , 193, 147), // #1358 - INST(Vpshrdvd , VexRvm_Lx , E(660F38,73,_,x,_,0,4,FV ), 0 , 106, 0 , 8905 , 199, 147), // #1359 - INST(Vpshrdvq , VexRvm_Lx , E(660F38,73,_,x,_,1,4,FV ), 0 , 107, 0 , 8914 , 200, 147), // #1360 - INST(Vpshrdvw , VexRvm_Lx , E(660F38,72,_,x,_,0,4,FVM), 0 , 105, 0 , 8923 , 198, 147), // #1361 - INST(Vpshrdw , VexRvmi_Lx , E(660F3A,72,_,x,_,0,4,FVM), 0 , 146, 0 , 8932 , 246, 147), // #1362 - INST(Vpshufb , VexRvm_Lx , V(660F38,00,_,x,I,I,4,FVM), 0 , 102, 0 , 8940 , 281, 142), // #1363 - INST(Vpshufbitqmb , VexRvm_Lx , E(660F38,8F,_,x,0,0,4,FVM), 0 , 105, 0 , 8948 , 366, 153), // #1364 - INST(Vpshufd , VexRmi_Lx , V(660F00,70,_,x,I,0,4,FV ), 0 , 128, 0 , 8961 , 367, 127), // #1365 - INST(Vpshufhw , VexRmi_Lx , V(F30F00,70,_,x,I,I,4,FVM), 0 , 180, 0 , 8969 , 368, 142), // #1366 - INST(Vpshuflw , VexRmi_Lx , V(F20F00,70,_,x,I,I,4,FVM), 0 , 206, 0 , 8978 , 368, 142), // #1367 - INST(Vpsignb , VexRvm_Lx , V(660F38,08,_,x,I,_,_,_ ), 0 , 90 , 0 , 8987 , 188, 139), // #1368 - INST(Vpsignd , VexRvm_Lx , V(660F38,0A,_,x,I,_,_,_ ), 0 , 90 , 0 , 8995 , 188, 139), // #1369 - INST(Vpsignw , VexRvm_Lx , V(660F38,09,_,x,I,_,_,_ ), 0 , 90 , 0 , 9003 , 188, 139), // #1370 - INST(Vpslld , VexRvmVmi_Lx , V(660F00,F2,_,x,I,0,4,128), V(660F00,72,6,x,I,0,4,FV ), 207, 123, 9011 , 369, 127), // #1371 - INST(Vpslldq , VexEvexVmi_Lx , V(660F00,73,7,x,I,I,4,FVM), 0 , 208, 0 , 9018 , 370, 142), // #1372 - INST(Vpsllq , VexRvmVmi_Lx , V(660F00,F3,_,x,I,1,4,128), V(660F00,73,6,x,I,1,4,FV ), 209, 124, 9026 , 371, 127), // #1373 - INST(Vpsllvd , VexRvm_Lx , V(660F38,47,_,x,0,0,4,FV ), 0 , 158, 0 , 9033 , 195, 136), // #1374 - INST(Vpsllvq , VexRvm_Lx , V(660F38,47,_,x,1,1,4,FV ), 0 , 157, 0 , 9041 , 194, 136), // #1375 - INST(Vpsllvw , VexRvm_Lx , E(660F38,12,_,x,_,1,4,FVM), 0 , 108, 0 , 9049 , 198, 124), // #1376 - INST(Vpsllw , VexRvmVmi_Lx , V(660F00,F1,_,x,I,I,4,FVM), V(660F00,71,6,x,I,I,4,FVM), 179, 125, 9057 , 372, 142), // #1377 - INST(Vpsrad , VexRvmVmi_Lx , V(660F00,E2,_,x,I,0,4,128), V(660F00,72,4,x,I,0,4,FV ), 207, 126, 9064 , 369, 127), // #1378 - INST(Vpsraq , VexRvmVmi_Lx , E(660F00,E2,_,x,_,1,4,128), E(660F00,72,4,x,_,1,4,FV ), 210, 127, 9071 , 373, 122), // #1379 - INST(Vpsravd , VexRvm_Lx , V(660F38,46,_,x,0,0,4,FV ), 0 , 158, 0 , 9078 , 195, 136), // #1380 - INST(Vpsravq , VexRvm_Lx , E(660F38,46,_,x,_,1,4,FV ), 0 , 107, 0 , 9086 , 200, 122), // #1381 - INST(Vpsravw , VexRvm_Lx , E(660F38,11,_,x,_,1,4,FVM), 0 , 108, 0 , 9094 , 198, 124), // #1382 - INST(Vpsraw , VexRvmVmi_Lx , V(660F00,E1,_,x,I,I,4,128), V(660F00,71,4,x,I,I,4,FVM), 207, 128, 9102 , 372, 142), // #1383 - INST(Vpsrld , VexRvmVmi_Lx , V(660F00,D2,_,x,I,0,4,128), V(660F00,72,2,x,I,0,4,FV ), 207, 129, 9109 , 369, 127), // #1384 - INST(Vpsrldq , VexEvexVmi_Lx , V(660F00,73,3,x,I,I,4,FVM), 0 , 211, 0 , 9116 , 370, 142), // #1385 - INST(Vpsrlq , VexRvmVmi_Lx , V(660F00,D3,_,x,I,1,4,128), V(660F00,73,2,x,I,1,4,FV ), 209, 130, 9124 , 371, 127), // #1386 - INST(Vpsrlvd , VexRvm_Lx , V(660F38,45,_,x,0,0,4,FV ), 0 , 158, 0 , 9131 , 195, 136), // #1387 - INST(Vpsrlvq , VexRvm_Lx , V(660F38,45,_,x,1,1,4,FV ), 0 , 157, 0 , 9139 , 194, 136), // #1388 - INST(Vpsrlvw , VexRvm_Lx , E(660F38,10,_,x,_,1,4,FVM), 0 , 108, 0 , 9147 , 198, 124), // #1389 - INST(Vpsrlw , VexRvmVmi_Lx , V(660F00,D1,_,x,I,I,4,128), V(660F00,71,2,x,I,I,4,FVM), 207, 131, 9155 , 372, 142), // #1390 - INST(Vpsubb , VexRvm_Lx , V(660F00,F8,_,x,I,I,4,FVM), 0 , 179, 0 , 9162 , 374, 142), // #1391 - INST(Vpsubd , VexRvm_Lx , V(660F00,FA,_,x,I,0,4,FV ), 0 , 128, 0 , 9169 , 375, 127), // #1392 - INST(Vpsubq , VexRvm_Lx , V(660F00,FB,_,x,I,1,4,FV ), 0 , 97 , 0 , 9176 , 376, 127), // #1393 - INST(Vpsubsb , VexRvm_Lx , V(660F00,E8,_,x,I,I,4,FVM), 0 , 179, 0 , 9183 , 374, 142), // #1394 - INST(Vpsubsw , VexRvm_Lx , V(660F00,E9,_,x,I,I,4,FVM), 0 , 179, 0 , 9191 , 374, 142), // #1395 - INST(Vpsubusb , VexRvm_Lx , V(660F00,D8,_,x,I,I,4,FVM), 0 , 179, 0 , 9199 , 374, 142), // #1396 - INST(Vpsubusw , VexRvm_Lx , V(660F00,D9,_,x,I,I,4,FVM), 0 , 179, 0 , 9208 , 374, 142), // #1397 - INST(Vpsubw , VexRvm_Lx , V(660F00,F9,_,x,I,I,4,FVM), 0 , 179, 0 , 9217 , 374, 142), // #1398 - INST(Vpternlogd , VexRvmi_Lx , E(660F3A,25,_,x,_,0,4,FV ), 0 , 103, 0 , 9224 , 192, 122), // #1399 - INST(Vpternlogq , VexRvmi_Lx , E(660F3A,25,_,x,_,1,4,FV ), 0 , 104, 0 , 9235 , 193, 122), // #1400 - INST(Vptest , VexRm_Lx , V(660F38,17,_,x,I,_,_,_ ), 0 , 90 , 0 , 9246 , 266, 146), // #1401 - INST(Vptestmb , VexRvm_Lx , E(660F38,26,_,x,_,0,4,FVM), 0 , 105, 0 , 9253 , 366, 124), // #1402 - INST(Vptestmd , VexRvm_Lx , E(660F38,27,_,x,_,0,4,FV ), 0 , 106, 0 , 9262 , 377, 122), // #1403 - INST(Vptestmq , VexRvm_Lx , E(660F38,27,_,x,_,1,4,FV ), 0 , 107, 0 , 9271 , 378, 122), // #1404 - INST(Vptestmw , VexRvm_Lx , E(660F38,26,_,x,_,1,4,FVM), 0 , 108, 0 , 9280 , 366, 124), // #1405 - INST(Vptestnmb , VexRvm_Lx , E(F30F38,26,_,x,_,0,4,FVM), 0 , 212, 0 , 9289 , 366, 124), // #1406 - INST(Vptestnmd , VexRvm_Lx , E(F30F38,27,_,x,_,0,4,FV ), 0 , 213, 0 , 9299 , 377, 122), // #1407 - INST(Vptestnmq , VexRvm_Lx , E(F30F38,27,_,x,_,1,4,FV ), 0 , 214, 0 , 9309 , 378, 122), // #1408 - INST(Vptestnmw , VexRvm_Lx , E(F30F38,26,_,x,_,1,4,FVM), 0 , 215, 0 , 9319 , 366, 124), // #1409 - INST(Vpunpckhbw , VexRvm_Lx , V(660F00,68,_,x,I,I,4,FVM), 0 , 179, 0 , 9329 , 281, 142), // #1410 - INST(Vpunpckhdq , VexRvm_Lx , V(660F00,6A,_,x,I,0,4,FV ), 0 , 128, 0 , 9340 , 195, 127), // #1411 - INST(Vpunpckhqdq , VexRvm_Lx , V(660F00,6D,_,x,I,1,4,FV ), 0 , 97 , 0 , 9351 , 194, 127), // #1412 - INST(Vpunpckhwd , VexRvm_Lx , V(660F00,69,_,x,I,I,4,FVM), 0 , 179, 0 , 9363 , 281, 142), // #1413 - INST(Vpunpcklbw , VexRvm_Lx , V(660F00,60,_,x,I,I,4,FVM), 0 , 179, 0 , 9374 , 281, 142), // #1414 - INST(Vpunpckldq , VexRvm_Lx , V(660F00,62,_,x,I,0,4,FV ), 0 , 128, 0 , 9385 , 195, 127), // #1415 - INST(Vpunpcklqdq , VexRvm_Lx , V(660F00,6C,_,x,I,1,4,FV ), 0 , 97 , 0 , 9396 , 194, 127), // #1416 - INST(Vpunpcklwd , VexRvm_Lx , V(660F00,61,_,x,I,I,4,FVM), 0 , 179, 0 , 9408 , 281, 142), // #1417 - INST(Vpxor , VexRvm_Lx , V(660F00,EF,_,x,I,_,_,_ ), 0 , 63 , 0 , 9419 , 315, 139), // #1418 - INST(Vpxord , VexRvm_Lx , E(660F00,EF,_,x,_,0,4,FV ), 0 , 184, 0 , 9425 , 316, 122), // #1419 - INST(Vpxorq , VexRvm_Lx , E(660F00,EF,_,x,_,1,4,FV ), 0 , 125, 0 , 9432 , 317, 122), // #1420 - INST(Vrangepd , VexRvmi_Lx , E(660F3A,50,_,x,_,1,4,FV ), 0 , 104, 0 , 9439 , 255, 125), // #1421 - INST(Vrangeps , VexRvmi_Lx , E(660F3A,50,_,x,_,0,4,FV ), 0 , 103, 0 , 9448 , 256, 125), // #1422 - INST(Vrangesd , VexRvmi , E(660F3A,51,_,I,_,1,3,T1S), 0 , 155, 0 , 9457 , 257, 61 ), // #1423 - INST(Vrangess , VexRvmi , E(660F3A,51,_,I,_,0,2,T1S), 0 , 156, 0 , 9466 , 258, 61 ), // #1424 - INST(Vrcp14pd , VexRm_Lx , E(660F38,4C,_,x,_,1,4,FV ), 0 , 107, 0 , 9475 , 348, 122), // #1425 - INST(Vrcp14ps , VexRm_Lx , E(660F38,4C,_,x,_,0,4,FV ), 0 , 106, 0 , 9484 , 335, 122), // #1426 - INST(Vrcp14sd , VexRvm , E(660F38,4D,_,I,_,1,3,T1S), 0 , 119, 0 , 9493 , 379, 63 ), // #1427 - INST(Vrcp14ss , VexRvm , E(660F38,4D,_,I,_,0,2,T1S), 0 , 120, 0 , 9502 , 380, 63 ), // #1428 - INST(Vrcp28pd , VexRm , E(660F38,CA,_,2,_,1,4,FV ), 0 , 147, 0 , 9511 , 248, 131), // #1429 - INST(Vrcp28ps , VexRm , E(660F38,CA,_,2,_,0,4,FV ), 0 , 148, 0 , 9520 , 249, 131), // #1430 - INST(Vrcp28sd , VexRvm , E(660F38,CB,_,I,_,1,3,T1S), 0 , 119, 0 , 9529 , 276, 131), // #1431 - INST(Vrcp28ss , VexRvm , E(660F38,CB,_,I,_,0,2,T1S), 0 , 120, 0 , 9538 , 277, 131), // #1432 - INST(Vrcpps , VexRm_Lx , V(000F00,53,_,x,I,_,_,_ ), 0 , 66 , 0 , 9547 , 266, 119), // #1433 - INST(Vrcpss , VexRvm , V(F30F00,53,_,I,I,_,_,_ ), 0 , 173, 0 , 9554 , 381, 119), // #1434 - INST(Vreducepd , VexRmi_Lx , E(660F3A,56,_,x,_,1,4,FV ), 0 , 104, 0 , 9561 , 360, 125), // #1435 - INST(Vreduceps , VexRmi_Lx , E(660F3A,56,_,x,_,0,4,FV ), 0 , 103, 0 , 9571 , 359, 125), // #1436 - INST(Vreducesd , VexRvmi , E(660F3A,57,_,I,_,1,3,T1S), 0 , 155, 0 , 9581 , 382, 61 ), // #1437 - INST(Vreducess , VexRvmi , E(660F3A,57,_,I,_,0,2,T1S), 0 , 156, 0 , 9591 , 383, 61 ), // #1438 - INST(Vrndscalepd , VexRmi_Lx , E(660F3A,09,_,x,_,1,4,FV ), 0 , 104, 0 , 9601 , 278, 122), // #1439 - INST(Vrndscaleps , VexRmi_Lx , E(660F3A,08,_,x,_,0,4,FV ), 0 , 103, 0 , 9613 , 279, 122), // #1440 - INST(Vrndscalesd , VexRvmi , E(660F3A,0B,_,I,_,1,3,T1S), 0 , 155, 0 , 9625 , 257, 63 ), // #1441 - INST(Vrndscaless , VexRvmi , E(660F3A,0A,_,I,_,0,2,T1S), 0 , 156, 0 , 9637 , 258, 63 ), // #1442 - INST(Vroundpd , VexRmi_Lx , V(660F3A,09,_,x,I,_,_,_ ), 0 , 67 , 0 , 9649 , 384, 119), // #1443 - INST(Vroundps , VexRmi_Lx , V(660F3A,08,_,x,I,_,_,_ ), 0 , 67 , 0 , 9658 , 384, 119), // #1444 - INST(Vroundsd , VexRvmi , V(660F3A,0B,_,I,I,_,_,_ ), 0 , 67 , 0 , 9667 , 385, 119), // #1445 - INST(Vroundss , VexRvmi , V(660F3A,0A,_,I,I,_,_,_ ), 0 , 67 , 0 , 9676 , 386, 119), // #1446 - INST(Vrsqrt14pd , VexRm_Lx , E(660F38,4E,_,x,_,1,4,FV ), 0 , 107, 0 , 9685 , 348, 122), // #1447 - INST(Vrsqrt14ps , VexRm_Lx , E(660F38,4E,_,x,_,0,4,FV ), 0 , 106, 0 , 9696 , 335, 122), // #1448 - INST(Vrsqrt14sd , VexRvm , E(660F38,4F,_,I,_,1,3,T1S), 0 , 119, 0 , 9707 , 379, 63 ), // #1449 - INST(Vrsqrt14ss , VexRvm , E(660F38,4F,_,I,_,0,2,T1S), 0 , 120, 0 , 9718 , 380, 63 ), // #1450 - INST(Vrsqrt28pd , VexRm , E(660F38,CC,_,2,_,1,4,FV ), 0 , 147, 0 , 9729 , 248, 131), // #1451 - INST(Vrsqrt28ps , VexRm , E(660F38,CC,_,2,_,0,4,FV ), 0 , 148, 0 , 9740 , 249, 131), // #1452 - INST(Vrsqrt28sd , VexRvm , E(660F38,CD,_,I,_,1,3,T1S), 0 , 119, 0 , 9751 , 276, 131), // #1453 - INST(Vrsqrt28ss , VexRvm , E(660F38,CD,_,I,_,0,2,T1S), 0 , 120, 0 , 9762 , 277, 131), // #1454 - INST(Vrsqrtps , VexRm_Lx , V(000F00,52,_,x,I,_,_,_ ), 0 , 66 , 0 , 9773 , 266, 119), // #1455 - INST(Vrsqrtss , VexRvm , V(F30F00,52,_,I,I,_,_,_ ), 0 , 173, 0 , 9782 , 381, 119), // #1456 - INST(Vscalefpd , VexRvm_Lx , E(660F38,2C,_,x,_,1,4,FV ), 0 , 107, 0 , 9791 , 387, 122), // #1457 - INST(Vscalefps , VexRvm_Lx , E(660F38,2C,_,x,_,0,4,FV ), 0 , 106, 0 , 9801 , 388, 122), // #1458 - INST(Vscalefsd , VexRvm , E(660F38,2D,_,I,_,1,3,T1S), 0 , 119, 0 , 9811 , 389, 63 ), // #1459 - INST(Vscalefss , VexRvm , E(660F38,2D,_,I,_,0,2,T1S), 0 , 120, 0 , 9821 , 390, 63 ), // #1460 - INST(Vscatterdpd , VexMr_Lx , E(660F38,A2,_,x,_,1,3,T1S), 0 , 119, 0 , 9831 , 391, 122), // #1461 - INST(Vscatterdps , VexMr_Lx , E(660F38,A2,_,x,_,0,2,T1S), 0 , 120, 0 , 9843 , 362, 122), // #1462 - INST(Vscatterpf0dpd , VexM_VM , E(660F38,C6,5,2,_,1,3,T1S), 0 , 216, 0 , 9855 , 271, 137), // #1463 - INST(Vscatterpf0dps , VexM_VM , E(660F38,C6,5,2,_,0,2,T1S), 0 , 217, 0 , 9870 , 272, 137), // #1464 - INST(Vscatterpf0qpd , VexM_VM , E(660F38,C7,5,2,_,1,3,T1S), 0 , 216, 0 , 9885 , 273, 137), // #1465 - INST(Vscatterpf0qps , VexM_VM , E(660F38,C7,5,2,_,0,2,T1S), 0 , 217, 0 , 9900 , 273, 137), // #1466 - INST(Vscatterpf1dpd , VexM_VM , E(660F38,C6,6,2,_,1,3,T1S), 0 , 218, 0 , 9915 , 271, 137), // #1467 - INST(Vscatterpf1dps , VexM_VM , E(660F38,C6,6,2,_,0,2,T1S), 0 , 219, 0 , 9930 , 272, 137), // #1468 - INST(Vscatterpf1qpd , VexM_VM , E(660F38,C7,6,2,_,1,3,T1S), 0 , 218, 0 , 9945 , 273, 137), // #1469 - INST(Vscatterpf1qps , VexM_VM , E(660F38,C7,6,2,_,0,2,T1S), 0 , 219, 0 , 9960 , 273, 137), // #1470 - INST(Vscatterqpd , VexMr_Lx , E(660F38,A3,_,x,_,1,3,T1S), 0 , 119, 0 , 9975 , 364, 122), // #1471 - INST(Vscatterqps , VexMr_Lx , E(660F38,A3,_,x,_,0,2,T1S), 0 , 120, 0 , 9987 , 363, 122), // #1472 - INST(Vshuff32x4 , VexRvmi_Lx , E(660F3A,23,_,x,_,0,4,FV ), 0 , 103, 0 , 9999 , 392, 122), // #1473 - INST(Vshuff64x2 , VexRvmi_Lx , E(660F3A,23,_,x,_,1,4,FV ), 0 , 104, 0 , 10010, 393, 122), // #1474 - INST(Vshufi32x4 , VexRvmi_Lx , E(660F3A,43,_,x,_,0,4,FV ), 0 , 103, 0 , 10021, 392, 122), // #1475 - INST(Vshufi64x2 , VexRvmi_Lx , E(660F3A,43,_,x,_,1,4,FV ), 0 , 104, 0 , 10032, 393, 122), // #1476 - INST(Vshufpd , VexRvmi_Lx , V(660F00,C6,_,x,I,1,4,FV ), 0 , 97 , 0 , 10043, 394, 117), // #1477 - INST(Vshufps , VexRvmi_Lx , V(000F00,C6,_,x,I,0,4,FV ), 0 , 98 , 0 , 10051, 395, 117), // #1478 - INST(Vsqrtpd , VexRm_Lx , V(660F00,51,_,x,I,1,4,FV ), 0 , 97 , 0 , 10059, 396, 117), // #1479 - INST(Vsqrtps , VexRm_Lx , V(000F00,51,_,x,I,0,4,FV ), 0 , 98 , 0 , 10067, 218, 117), // #1480 - INST(Vsqrtsd , VexRvm , V(F20F00,51,_,I,I,1,3,T1S), 0 , 99 , 0 , 10075, 186, 118), // #1481 - INST(Vsqrtss , VexRvm , V(F30F00,51,_,I,I,0,2,T1S), 0 , 100, 0 , 10083, 187, 118), // #1482 - INST(Vstmxcsr , VexM , V(000F00,AE,3,0,I,_,_,_ ), 0 , 220, 0 , 10091, 287, 119), // #1483 - INST(Vsubpd , VexRvm_Lx , V(660F00,5C,_,x,I,1,4,FV ), 0 , 97 , 0 , 10100, 184, 117), // #1484 - INST(Vsubps , VexRvm_Lx , V(000F00,5C,_,x,I,0,4,FV ), 0 , 98 , 0 , 10107, 185, 117), // #1485 - INST(Vsubsd , VexRvm , V(F20F00,5C,_,I,I,1,3,T1S), 0 , 99 , 0 , 10114, 186, 118), // #1486 - INST(Vsubss , VexRvm , V(F30F00,5C,_,I,I,0,2,T1S), 0 , 100, 0 , 10121, 187, 118), // #1487 - INST(Vtestpd , VexRm_Lx , V(660F38,0F,_,x,0,_,_,_ ), 0 , 90 , 0 , 10128, 266, 146), // #1488 - INST(Vtestps , VexRm_Lx , V(660F38,0E,_,x,0,_,_,_ ), 0 , 90 , 0 , 10136, 266, 146), // #1489 - INST(Vucomisd , VexRm , V(660F00,2E,_,I,I,1,3,T1S), 0 , 117, 0 , 10144, 214, 128), // #1490 - INST(Vucomiss , VexRm , V(000F00,2E,_,I,I,0,2,T1S), 0 , 118, 0 , 10153, 215, 128), // #1491 - INST(Vunpckhpd , VexRvm_Lx , V(660F00,15,_,x,I,1,4,FV ), 0 , 97 , 0 , 10162, 194, 117), // #1492 - INST(Vunpckhps , VexRvm_Lx , V(000F00,15,_,x,I,0,4,FV ), 0 , 98 , 0 , 10172, 195, 117), // #1493 - INST(Vunpcklpd , VexRvm_Lx , V(660F00,14,_,x,I,1,4,FV ), 0 , 97 , 0 , 10182, 194, 117), // #1494 - INST(Vunpcklps , VexRvm_Lx , V(000F00,14,_,x,I,0,4,FV ), 0 , 98 , 0 , 10192, 195, 117), // #1495 - INST(Vxorpd , VexRvm_Lx , V(660F00,57,_,x,I,1,4,FV ), 0 , 97 , 0 , 10202, 376, 123), // #1496 - INST(Vxorps , VexRvm_Lx , V(000F00,57,_,x,I,0,4,FV ), 0 , 98 , 0 , 10209, 375, 123), // #1497 - INST(Vzeroall , VexOp , V(000F00,77,_,1,I,_,_,_ ), 0 , 62 , 0 , 10216, 397, 119), // #1498 - INST(Vzeroupper , VexOp , V(000F00,77,_,0,I,_,_,_ ), 0 , 66 , 0 , 10225, 397, 119), // #1499 - INST(Wbinvd , X86Op , O(000F00,09,_,_,_,_,_,_ ), 0 , 4 , 0 , 10236, 30 , 0 ), // #1500 - INST(Wbnoinvd , X86Op , O(F30F00,09,_,_,_,_,_,_ ), 0 , 6 , 0 , 10243, 30 , 155), // #1501 - INST(Wrfsbase , X86M , O(F30F00,AE,2,_,x,_,_,_ ), 0 , 221, 0 , 10252, 162, 99 ), // #1502 - INST(Wrgsbase , X86M , O(F30F00,AE,3,_,x,_,_,_ ), 0 , 222, 0 , 10261, 162, 99 ), // #1503 - INST(Wrmsr , X86Op , O(000F00,30,_,_,_,_,_,_ ), 0 , 4 , 0 , 10270, 163, 100), // #1504 - INST(Xabort , X86Op_O_I8 , O(000000,C6,7,_,_,_,_,_ ), 0 , 25 , 0 , 10276, 74 , 156), // #1505 - INST(Xadd , X86Xadd , O(000F00,C0,_,_,x,_,_,_ ), 0 , 4 , 0 , 10283, 398, 36 ), // #1506 - INST(Xbegin , X86JmpRel , O(000000,C7,7,_,_,_,_,_ ), 0 , 25 , 0 , 10288, 399, 156), // #1507 - INST(Xchg , X86Xchg , O(000000,86,_,_,x,_,_,_ ), 0 , 0 , 0 , 448 , 400, 0 ), // #1508 - INST(Xend , X86Op , O(000F01,D5,_,_,_,_,_,_ ), 0 , 21 , 0 , 10295, 30 , 156), // #1509 - INST(Xgetbv , X86Op , O(000F01,D0,_,_,_,_,_,_ ), 0 , 21 , 0 , 10300, 163, 157), // #1510 - INST(Xlatb , X86Op , O(000000,D7,_,_,_,_,_,_ ), 0 , 0 , 0 , 10307, 30 , 0 ), // #1511 - INST(Xor , X86Arith , O(000000,30,6,_,x,_,_,_ ), 0 , 30 , 0 , 9421 , 168, 1 ), // #1512 - INST(Xorpd , ExtRm , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 10203, 141, 4 ), // #1513 - INST(Xorps , ExtRm , O(000F00,57,_,_,_,_,_,_ ), 0 , 4 , 0 , 10210, 141, 5 ), // #1514 - INST(Xresldtrk , X86Op , O(F20F01,E9,_,_,_,_,_,_ ), 0 , 86 , 0 , 10313, 30 , 158), // #1515 - INST(Xrstor , X86M_Only , O(000F00,AE,5,_,_,_,_,_ ), 0 , 70 , 0 , 1134 , 401, 157), // #1516 - INST(Xrstor64 , X86M_Only , O(000F00,AE,5,_,1,_,_,_ ), 0 , 223, 0 , 1142 , 402, 157), // #1517 - INST(Xrstors , X86M_Only , O(000F00,C7,3,_,_,_,_,_ ), 0 , 71 , 0 , 10323, 401, 159), // #1518 - INST(Xrstors64 , X86M_Only , O(000F00,C7,3,_,1,_,_,_ ), 0 , 224, 0 , 10331, 402, 159), // #1519 - INST(Xsave , X86M_Only , O(000F00,AE,4,_,_,_,_,_ ), 0 , 91 , 0 , 1152 , 401, 157), // #1520 - INST(Xsave64 , X86M_Only , O(000F00,AE,4,_,1,_,_,_ ), 0 , 225, 0 , 1159 , 402, 157), // #1521 - INST(Xsavec , X86M_Only , O(000F00,C7,4,_,_,_,_,_ ), 0 , 91 , 0 , 10341, 401, 160), // #1522 - INST(Xsavec64 , X86M_Only , O(000F00,C7,4,_,1,_,_,_ ), 0 , 225, 0 , 10348, 402, 160), // #1523 - INST(Xsaveopt , X86M_Only , O(000F00,AE,6,_,_,_,_,_ ), 0 , 73 , 0 , 10357, 401, 161), // #1524 - INST(Xsaveopt64 , X86M_Only , O(000F00,AE,6,_,1,_,_,_ ), 0 , 226, 0 , 10366, 402, 161), // #1525 - INST(Xsaves , X86M_Only , O(000F00,C7,5,_,_,_,_,_ ), 0 , 70 , 0 , 10377, 401, 159), // #1526 - INST(Xsaves64 , X86M_Only , O(000F00,C7,5,_,1,_,_,_ ), 0 , 223, 0 , 10384, 402, 159), // #1527 - INST(Xsetbv , X86Op , O(000F01,D1,_,_,_,_,_,_ ), 0 , 21 , 0 , 10393, 163, 157), // #1528 - INST(Xsusldtrk , X86Op , O(F20F01,E8,_,_,_,_,_,_ ), 0 , 86 , 0 , 10400, 30 , 158), // #1529 - INST(Xtest , X86Op , O(000F01,D6,_,_,_,_,_,_ ), 0 , 21 , 0 , 10410, 30 , 162) // #1530 + INST(Clrssbsy , X86M , O(F30F00,AE,6,_,_,_,_,_ ), 0 , 24 , 0 , 252 , 32 , 24 ), // #71 + INST(Clts , X86Op , O(000F00,06,_,_,_,_,_,_ ), 0 , 4 , 0 , 261 , 30 , 0 ), // #72 + INST(Clwb , X86M_Only , O(660F00,AE,6,_,_,_,_,_ ), 0 , 25 , 0 , 266 , 31 , 25 ), // #73 + INST(Clzero , X86Op_MemZAX , O(000F01,FC,_,_,_,_,_,_ ), 0 , 21 , 0 , 271 , 33 , 26 ), // #74 + INST(Cmc , X86Op , O(000000,F5,_,_,_,_,_,_ ), 0 , 0 , 0 , 278 , 30 , 27 ), // #75 + INST(Cmova , X86Rm , O(000F00,47,_,_,x,_,_,_ ), 0 , 4 , 0 , 282 , 22 , 28 ), // #76 + INST(Cmovae , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 4 , 0 , 288 , 22 , 29 ), // #77 + INST(Cmovb , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 4 , 0 , 643 , 22 , 29 ), // #78 + INST(Cmovbe , X86Rm , O(000F00,46,_,_,x,_,_,_ ), 0 , 4 , 0 , 650 , 22 , 28 ), // #79 + INST(Cmovc , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 4 , 0 , 295 , 22 , 29 ), // #80 + INST(Cmove , X86Rm , O(000F00,44,_,_,x,_,_,_ ), 0 , 4 , 0 , 658 , 22 , 30 ), // #81 + INST(Cmovg , X86Rm , O(000F00,4F,_,_,x,_,_,_ ), 0 , 4 , 0 , 301 , 22 , 31 ), // #82 + INST(Cmovge , X86Rm , O(000F00,4D,_,_,x,_,_,_ ), 0 , 4 , 0 , 307 , 22 , 32 ), // #83 + INST(Cmovl , X86Rm , O(000F00,4C,_,_,x,_,_,_ ), 0 , 4 , 0 , 314 , 22 , 32 ), // #84 + INST(Cmovle , X86Rm , O(000F00,4E,_,_,x,_,_,_ ), 0 , 4 , 0 , 320 , 22 , 31 ), // #85 + INST(Cmovna , X86Rm , O(000F00,46,_,_,x,_,_,_ ), 0 , 4 , 0 , 327 , 22 , 28 ), // #86 + INST(Cmovnae , X86Rm , O(000F00,42,_,_,x,_,_,_ ), 0 , 4 , 0 , 334 , 22 , 29 ), // #87 + INST(Cmovnb , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 4 , 0 , 665 , 22 , 29 ), // #88 + INST(Cmovnbe , X86Rm , O(000F00,47,_,_,x,_,_,_ ), 0 , 4 , 0 , 673 , 22 , 28 ), // #89 + INST(Cmovnc , X86Rm , O(000F00,43,_,_,x,_,_,_ ), 0 , 4 , 0 , 342 , 22 , 29 ), // #90 + INST(Cmovne , X86Rm , O(000F00,45,_,_,x,_,_,_ ), 0 , 4 , 0 , 682 , 22 , 30 ), // #91 + INST(Cmovng , X86Rm , O(000F00,4E,_,_,x,_,_,_ ), 0 , 4 , 0 , 349 , 22 , 31 ), // #92 + INST(Cmovnge , X86Rm , O(000F00,4C,_,_,x,_,_,_ ), 0 , 4 , 0 , 356 , 22 , 32 ), // #93 + INST(Cmovnl , X86Rm , O(000F00,4D,_,_,x,_,_,_ ), 0 , 4 , 0 , 364 , 22 , 32 ), // #94 + INST(Cmovnle , X86Rm , O(000F00,4F,_,_,x,_,_,_ ), 0 , 4 , 0 , 371 , 22 , 31 ), // #95 + INST(Cmovno , X86Rm , O(000F00,41,_,_,x,_,_,_ ), 0 , 4 , 0 , 379 , 22 , 33 ), // #96 + INST(Cmovnp , X86Rm , O(000F00,4B,_,_,x,_,_,_ ), 0 , 4 , 0 , 386 , 22 , 34 ), // #97 + INST(Cmovns , X86Rm , O(000F00,49,_,_,x,_,_,_ ), 0 , 4 , 0 , 393 , 22 , 35 ), // #98 + INST(Cmovnz , X86Rm , O(000F00,45,_,_,x,_,_,_ ), 0 , 4 , 0 , 400 , 22 , 30 ), // #99 + INST(Cmovo , X86Rm , O(000F00,40,_,_,x,_,_,_ ), 0 , 4 , 0 , 407 , 22 , 33 ), // #100 + INST(Cmovp , X86Rm , O(000F00,4A,_,_,x,_,_,_ ), 0 , 4 , 0 , 413 , 22 , 34 ), // #101 + INST(Cmovpe , X86Rm , O(000F00,4A,_,_,x,_,_,_ ), 0 , 4 , 0 , 419 , 22 , 34 ), // #102 + INST(Cmovpo , X86Rm , O(000F00,4B,_,_,x,_,_,_ ), 0 , 4 , 0 , 426 , 22 , 34 ), // #103 + INST(Cmovs , X86Rm , O(000F00,48,_,_,x,_,_,_ ), 0 , 4 , 0 , 433 , 22 , 35 ), // #104 + INST(Cmovz , X86Rm , O(000F00,44,_,_,x,_,_,_ ), 0 , 4 , 0 , 439 , 22 , 30 ), // #105 + INST(Cmp , X86Arith , O(000000,38,7,_,x,_,_,_ ), 0 , 26 , 0 , 445 , 34 , 1 ), // #106 + INST(Cmppd , ExtRmi , O(660F00,C2,_,_,_,_,_,_ ), 0 , 3 , 0 , 3719 , 8 , 4 ), // #107 + INST(Cmpps , ExtRmi , O(000F00,C2,_,_,_,_,_,_ ), 0 , 4 , 0 , 3726 , 8 , 5 ), // #108 + INST(Cmps , X86StrMm , O(000000,A6,_,_,_,_,_,_ ), 0 , 0 , 0 , 449 , 35 , 36 ), // #109 + INST(Cmpsd , ExtRmi , O(F20F00,C2,_,_,_,_,_,_ ), 0 , 5 , 0 , 3733 , 36 , 4 ), // #110 + INST(Cmpss , ExtRmi , O(F30F00,C2,_,_,_,_,_,_ ), 0 , 6 , 0 , 3740 , 37 , 5 ), // #111 + INST(Cmpxchg , X86Cmpxchg , O(000F00,B0,_,_,x,_,_,_ ), 0 , 4 , 0 , 454 , 38 , 37 ), // #112 + INST(Cmpxchg16b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,1,_,_,_ ), 0 , 27 , 0 , 462 , 39 , 38 ), // #113 + INST(Cmpxchg8b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,_,_,_,_ ), 0 , 28 , 0 , 473 , 40 , 39 ), // #114 + INST(Comisd , ExtRm , O(660F00,2F,_,_,_,_,_,_ ), 0 , 3 , 0 , 10246, 6 , 40 ), // #115 + INST(Comiss , ExtRm , O(000F00,2F,_,_,_,_,_,_ ), 0 , 4 , 0 , 10255, 7 , 41 ), // #116 + INST(Cpuid , X86Op , O(000F00,A2,_,_,_,_,_,_ ), 0 , 4 , 0 , 483 , 41 , 42 ), // #117 + INST(Cqo , X86Op_xDX_xAX , O(000000,99,_,_,1,_,_,_ ), 0 , 20 , 0 , 489 , 42 , 0 ), // #118 + INST(Crc32 , X86Crc , O(F20F38,F0,_,_,x,_,_,_ ), 0 , 29 , 0 , 493 , 43 , 43 ), // #119 + INST(Cvtdq2pd , ExtRm , O(F30F00,E6,_,_,_,_,_,_ ), 0 , 6 , 0 , 3787 , 6 , 4 ), // #120 + INST(Cvtdq2ps , ExtRm , O(000F00,5B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3797 , 5 , 4 ), // #121 + INST(Cvtpd2dq , ExtRm , O(F20F00,E6,_,_,_,_,_,_ ), 0 , 5 , 0 , 3836 , 5 , 4 ), // #122 + INST(Cvtpd2pi , ExtRm , O(660F00,2D,_,_,_,_,_,_ ), 0 , 3 , 0 , 499 , 44 , 4 ), // #123 + INST(Cvtpd2ps , ExtRm , O(660F00,5A,_,_,_,_,_,_ ), 0 , 3 , 0 , 3846 , 5 , 4 ), // #124 + INST(Cvtpi2pd , ExtRm , O(660F00,2A,_,_,_,_,_,_ ), 0 , 3 , 0 , 508 , 45 , 4 ), // #125 + INST(Cvtpi2ps , ExtRm , O(000F00,2A,_,_,_,_,_,_ ), 0 , 4 , 0 , 517 , 45 , 5 ), // #126 + INST(Cvtps2dq , ExtRm , O(660F00,5B,_,_,_,_,_,_ ), 0 , 3 , 0 , 3898 , 5 , 4 ), // #127 + INST(Cvtps2pd , ExtRm , O(000F00,5A,_,_,_,_,_,_ ), 0 , 4 , 0 , 3908 , 6 , 4 ), // #128 + INST(Cvtps2pi , ExtRm , O(000F00,2D,_,_,_,_,_,_ ), 0 , 4 , 0 , 526 , 46 , 5 ), // #129 + INST(Cvtsd2si , ExtRm_Wx , O(F20F00,2D,_,_,x,_,_,_ ), 0 , 5 , 0 , 3980 , 47 , 4 ), // #130 + INST(Cvtsd2ss , ExtRm , O(F20F00,5A,_,_,_,_,_,_ ), 0 , 5 , 0 , 3990 , 6 , 4 ), // #131 + INST(Cvtsi2sd , ExtRm_Wx , O(F20F00,2A,_,_,x,_,_,_ ), 0 , 5 , 0 , 4011 , 48 , 4 ), // #132 + INST(Cvtsi2ss , ExtRm_Wx , O(F30F00,2A,_,_,x,_,_,_ ), 0 , 6 , 0 , 4021 , 48 , 5 ), // #133 + INST(Cvtss2sd , ExtRm , O(F30F00,5A,_,_,_,_,_,_ ), 0 , 6 , 0 , 4031 , 7 , 4 ), // #134 + INST(Cvtss2si , ExtRm_Wx , O(F30F00,2D,_,_,x,_,_,_ ), 0 , 6 , 0 , 4041 , 49 , 5 ), // #135 + INST(Cvttpd2dq , ExtRm , O(660F00,E6,_,_,_,_,_,_ ), 0 , 3 , 0 , 4062 , 5 , 4 ), // #136 + INST(Cvttpd2pi , ExtRm , O(660F00,2C,_,_,_,_,_,_ ), 0 , 3 , 0 , 535 , 44 , 4 ), // #137 + INST(Cvttps2dq , ExtRm , O(F30F00,5B,_,_,_,_,_,_ ), 0 , 6 , 0 , 4108 , 5 , 4 ), // #138 + INST(Cvttps2pi , ExtRm , O(000F00,2C,_,_,_,_,_,_ ), 0 , 4 , 0 , 545 , 46 , 5 ), // #139 + INST(Cvttsd2si , ExtRm_Wx , O(F20F00,2C,_,_,x,_,_,_ ), 0 , 5 , 0 , 4154 , 47 , 4 ), // #140 + INST(Cvttss2si , ExtRm_Wx , O(F30F00,2C,_,_,x,_,_,_ ), 0 , 6 , 0 , 4177 , 49 , 5 ), // #141 + INST(Cwd , X86Op_xDX_xAX , O(660000,99,_,_,_,_,_,_ ), 0 , 19 , 0 , 555 , 50 , 0 ), // #142 + INST(Cwde , X86Op_xAX , O(000000,98,_,_,_,_,_,_ ), 0 , 0 , 0 , 559 , 51 , 0 ), // #143 + INST(Daa , X86Op , O(000000,27,_,_,_,_,_,_ ), 0 , 0 , 0 , 564 , 1 , 1 ), // #144 + INST(Das , X86Op , O(000000,2F,_,_,_,_,_,_ ), 0 , 0 , 0 , 568 , 1 , 1 ), // #145 + INST(Dec , X86IncDec , O(000000,FE,1,_,x,_,_,_ ), O(000000,48,_,_,x,_,_,_ ), 30 , 6 , 3301 , 52 , 44 ), // #146 + INST(Div , X86M_GPB_MulDiv , O(000000,F6,6,_,x,_,_,_ ), 0 , 31 , 0 , 805 , 53 , 1 ), // #147 + INST(Divpd , ExtRm , O(660F00,5E,_,_,_,_,_,_ ), 0 , 3 , 0 , 4276 , 5 , 4 ), // #148 + INST(Divps , ExtRm , O(000F00,5E,_,_,_,_,_,_ ), 0 , 4 , 0 , 4283 , 5 , 5 ), // #149 + INST(Divsd , ExtRm , O(F20F00,5E,_,_,_,_,_,_ ), 0 , 5 , 0 , 4290 , 6 , 4 ), // #150 + INST(Divss , ExtRm , O(F30F00,5E,_,_,_,_,_,_ ), 0 , 6 , 0 , 4297 , 7 , 5 ), // #151 + INST(Dppd , ExtRmi , O(660F3A,41,_,_,_,_,_,_ ), 0 , 8 , 0 , 4314 , 8 , 12 ), // #152 + INST(Dpps , ExtRmi , O(660F3A,40,_,_,_,_,_,_ ), 0 , 8 , 0 , 4320 , 8 , 12 ), // #153 + INST(Emms , X86Op , O(000F00,77,_,_,_,_,_,_ ), 0 , 4 , 0 , 773 , 54 , 45 ), // #154 + INST(Endbr32 , X86Op_Mod11RM , O(F30F00,FB,7,_,_,_,_,3 ), 0 , 32 , 0 , 572 , 30 , 46 ), // #155 + INST(Endbr64 , X86Op_Mod11RM , O(F30F00,FA,7,_,_,_,_,2 ), 0 , 33 , 0 , 580 , 30 , 46 ), // #156 + INST(Enqcmd , X86EnqcmdMovdir64b , O(F20F38,F8,_,_,_,_,_,_ ), 0 , 29 , 0 , 588 , 55 , 47 ), // #157 + INST(Enqcmds , X86EnqcmdMovdir64b , O(F30F38,F8,_,_,_,_,_,_ ), 0 , 7 , 0 , 595 , 55 , 47 ), // #158 + INST(Enter , X86Enter , O(000000,C8,_,_,_,_,_,_ ), 0 , 0 , 0 , 3017 , 56 , 0 ), // #159 + INST(Extractps , ExtExtract , O(660F3A,17,_,_,_,_,_,_ ), 0 , 8 , 0 , 4510 , 57 , 12 ), // #160 + INST(Extrq , ExtExtrq , O(660F00,79,_,_,_,_,_,_ ), O(660F00,78,0,_,_,_,_,_ ), 3 , 7 , 7606 , 58 , 48 ), // #161 + INST(F2xm1 , FpuOp , O_FPU(00,D9F0,_) , 0 , 34 , 0 , 603 , 30 , 0 ), // #162 + INST(Fabs , FpuOp , O_FPU(00,D9E1,_) , 0 , 34 , 0 , 609 , 30 , 0 ), // #163 + INST(Fadd , FpuArith , O_FPU(00,C0C0,0) , 0 , 35 , 0 , 2106 , 59 , 0 ), // #164 + INST(Faddp , FpuRDef , O_FPU(00,DEC0,_) , 0 , 36 , 0 , 614 , 60 , 0 ), // #165 + INST(Fbld , X86M_Only , O_FPU(00,00DF,4) , 0 , 37 , 0 , 620 , 61 , 0 ), // #166 + INST(Fbstp , X86M_Only , O_FPU(00,00DF,6) , 0 , 38 , 0 , 625 , 61 , 0 ), // #167 + INST(Fchs , FpuOp , O_FPU(00,D9E0,_) , 0 , 34 , 0 , 631 , 30 , 0 ), // #168 + INST(Fclex , FpuOp , O_FPU(9B,DBE2,_) , 0 , 39 , 0 , 636 , 30 , 0 ), // #169 + INST(Fcmovb , FpuR , O_FPU(00,DAC0,_) , 0 , 40 , 0 , 642 , 62 , 29 ), // #170 + INST(Fcmovbe , FpuR , O_FPU(00,DAD0,_) , 0 , 40 , 0 , 649 , 62 , 28 ), // #171 + INST(Fcmove , FpuR , O_FPU(00,DAC8,_) , 0 , 40 , 0 , 657 , 62 , 30 ), // #172 + INST(Fcmovnb , FpuR , O_FPU(00,DBC0,_) , 0 , 41 , 0 , 664 , 62 , 29 ), // #173 + INST(Fcmovnbe , FpuR , O_FPU(00,DBD0,_) , 0 , 41 , 0 , 672 , 62 , 28 ), // #174 + INST(Fcmovne , FpuR , O_FPU(00,DBC8,_) , 0 , 41 , 0 , 681 , 62 , 30 ), // #175 + INST(Fcmovnu , FpuR , O_FPU(00,DBD8,_) , 0 , 41 , 0 , 689 , 62 , 34 ), // #176 + INST(Fcmovu , FpuR , O_FPU(00,DAD8,_) , 0 , 40 , 0 , 697 , 62 , 34 ), // #177 + INST(Fcom , FpuCom , O_FPU(00,D0D0,2) , 0 , 42 , 0 , 704 , 63 , 0 ), // #178 + INST(Fcomi , FpuR , O_FPU(00,DBF0,_) , 0 , 41 , 0 , 709 , 62 , 49 ), // #179 + INST(Fcomip , FpuR , O_FPU(00,DFF0,_) , 0 , 43 , 0 , 715 , 62 , 49 ), // #180 + INST(Fcomp , FpuCom , O_FPU(00,D8D8,3) , 0 , 44 , 0 , 722 , 63 , 0 ), // #181 + INST(Fcompp , FpuOp , O_FPU(00,DED9,_) , 0 , 36 , 0 , 728 , 30 , 0 ), // #182 + INST(Fcos , FpuOp , O_FPU(00,D9FF,_) , 0 , 34 , 0 , 735 , 30 , 0 ), // #183 + INST(Fdecstp , FpuOp , O_FPU(00,D9F6,_) , 0 , 34 , 0 , 740 , 30 , 0 ), // #184 + INST(Fdiv , FpuArith , O_FPU(00,F0F8,6) , 0 , 45 , 0 , 748 , 59 , 0 ), // #185 + INST(Fdivp , FpuRDef , O_FPU(00,DEF8,_) , 0 , 36 , 0 , 753 , 60 , 0 ), // #186 + INST(Fdivr , FpuArith , O_FPU(00,F8F0,7) , 0 , 46 , 0 , 759 , 59 , 0 ), // #187 + INST(Fdivrp , FpuRDef , O_FPU(00,DEF0,_) , 0 , 36 , 0 , 765 , 60 , 0 ), // #188 + INST(Femms , X86Op , O(000F00,0E,_,_,_,_,_,_ ), 0 , 4 , 0 , 772 , 30 , 50 ), // #189 + INST(Ffree , FpuR , O_FPU(00,DDC0,_) , 0 , 47 , 0 , 778 , 62 , 0 ), // #190 + INST(Fiadd , FpuM , O_FPU(00,00DA,0) , 0 , 48 , 0 , 784 , 64 , 0 ), // #191 + INST(Ficom , FpuM , O_FPU(00,00DA,2) , 0 , 49 , 0 , 790 , 64 , 0 ), // #192 + INST(Ficomp , FpuM , O_FPU(00,00DA,3) , 0 , 50 , 0 , 796 , 64 , 0 ), // #193 + INST(Fidiv , FpuM , O_FPU(00,00DA,6) , 0 , 38 , 0 , 803 , 64 , 0 ), // #194 + INST(Fidivr , FpuM , O_FPU(00,00DA,7) , 0 , 51 , 0 , 809 , 64 , 0 ), // #195 + INST(Fild , FpuM , O_FPU(00,00DB,0) , O_FPU(00,00DF,5) , 48 , 8 , 816 , 65 , 0 ), // #196 + INST(Fimul , FpuM , O_FPU(00,00DA,1) , 0 , 52 , 0 , 821 , 64 , 0 ), // #197 + INST(Fincstp , FpuOp , O_FPU(00,D9F7,_) , 0 , 34 , 0 , 827 , 30 , 0 ), // #198 + INST(Finit , FpuOp , O_FPU(9B,DBE3,_) , 0 , 39 , 0 , 835 , 30 , 0 ), // #199 + INST(Fist , FpuM , O_FPU(00,00DB,2) , 0 , 49 , 0 , 841 , 64 , 0 ), // #200 + INST(Fistp , FpuM , O_FPU(00,00DB,3) , O_FPU(00,00DF,7) , 50 , 9 , 846 , 65 , 0 ), // #201 + INST(Fisttp , FpuM , O_FPU(00,00DB,1) , O_FPU(00,00DD,1) , 52 , 10 , 852 , 65 , 6 ), // #202 + INST(Fisub , FpuM , O_FPU(00,00DA,4) , 0 , 37 , 0 , 859 , 64 , 0 ), // #203 + INST(Fisubr , FpuM , O_FPU(00,00DA,5) , 0 , 53 , 0 , 865 , 64 , 0 ), // #204 + INST(Fld , FpuFldFst , O_FPU(00,00D9,0) , O_FPU(00,00DB,5) , 48 , 11 , 872 , 66 , 0 ), // #205 + INST(Fld1 , FpuOp , O_FPU(00,D9E8,_) , 0 , 34 , 0 , 876 , 30 , 0 ), // #206 + INST(Fldcw , X86M_Only , O_FPU(00,00D9,5) , 0 , 53 , 0 , 881 , 67 , 0 ), // #207 + INST(Fldenv , X86M_Only , O_FPU(00,00D9,4) , 0 , 37 , 0 , 887 , 31 , 0 ), // #208 + INST(Fldl2e , FpuOp , O_FPU(00,D9EA,_) , 0 , 34 , 0 , 894 , 30 , 0 ), // #209 + INST(Fldl2t , FpuOp , O_FPU(00,D9E9,_) , 0 , 34 , 0 , 901 , 30 , 0 ), // #210 + INST(Fldlg2 , FpuOp , O_FPU(00,D9EC,_) , 0 , 34 , 0 , 908 , 30 , 0 ), // #211 + INST(Fldln2 , FpuOp , O_FPU(00,D9ED,_) , 0 , 34 , 0 , 915 , 30 , 0 ), // #212 + INST(Fldpi , FpuOp , O_FPU(00,D9EB,_) , 0 , 34 , 0 , 922 , 30 , 0 ), // #213 + INST(Fldz , FpuOp , O_FPU(00,D9EE,_) , 0 , 34 , 0 , 928 , 30 , 0 ), // #214 + INST(Fmul , FpuArith , O_FPU(00,C8C8,1) , 0 , 54 , 0 , 2148 , 59 , 0 ), // #215 + INST(Fmulp , FpuRDef , O_FPU(00,DEC8,_) , 0 , 36 , 0 , 933 , 60 , 0 ), // #216 + INST(Fnclex , FpuOp , O_FPU(00,DBE2,_) , 0 , 41 , 0 , 939 , 30 , 0 ), // #217 + INST(Fninit , FpuOp , O_FPU(00,DBE3,_) , 0 , 41 , 0 , 946 , 30 , 0 ), // #218 + INST(Fnop , FpuOp , O_FPU(00,D9D0,_) , 0 , 34 , 0 , 953 , 30 , 0 ), // #219 + INST(Fnsave , X86M_Only , O_FPU(00,00DD,6) , 0 , 38 , 0 , 958 , 31 , 0 ), // #220 + INST(Fnstcw , X86M_Only , O_FPU(00,00D9,7) , 0 , 51 , 0 , 965 , 67 , 0 ), // #221 + INST(Fnstenv , X86M_Only , O_FPU(00,00D9,6) , 0 , 38 , 0 , 972 , 31 , 0 ), // #222 + INST(Fnstsw , FpuStsw , O_FPU(00,00DD,7) , O_FPU(00,DFE0,_) , 51 , 12 , 980 , 68 , 0 ), // #223 + INST(Fpatan , FpuOp , O_FPU(00,D9F3,_) , 0 , 34 , 0 , 987 , 30 , 0 ), // #224 + INST(Fprem , FpuOp , O_FPU(00,D9F8,_) , 0 , 34 , 0 , 994 , 30 , 0 ), // #225 + INST(Fprem1 , FpuOp , O_FPU(00,D9F5,_) , 0 , 34 , 0 , 1000 , 30 , 0 ), // #226 + INST(Fptan , FpuOp , O_FPU(00,D9F2,_) , 0 , 34 , 0 , 1007 , 30 , 0 ), // #227 + INST(Frndint , FpuOp , O_FPU(00,D9FC,_) , 0 , 34 , 0 , 1013 , 30 , 0 ), // #228 + INST(Frstor , X86M_Only , O_FPU(00,00DD,4) , 0 , 37 , 0 , 1021 , 31 , 0 ), // #229 + INST(Fsave , X86M_Only , O_FPU(9B,00DD,6) , 0 , 55 , 0 , 1028 , 31 , 0 ), // #230 + INST(Fscale , FpuOp , O_FPU(00,D9FD,_) , 0 , 34 , 0 , 1034 , 30 , 0 ), // #231 + INST(Fsin , FpuOp , O_FPU(00,D9FE,_) , 0 , 34 , 0 , 1041 , 30 , 0 ), // #232 + INST(Fsincos , FpuOp , O_FPU(00,D9FB,_) , 0 , 34 , 0 , 1046 , 30 , 0 ), // #233 + INST(Fsqrt , FpuOp , O_FPU(00,D9FA,_) , 0 , 34 , 0 , 1054 , 30 , 0 ), // #234 + INST(Fst , FpuFldFst , O_FPU(00,00D9,2) , 0 , 49 , 0 , 1060 , 69 , 0 ), // #235 + INST(Fstcw , X86M_Only , O_FPU(9B,00D9,7) , 0 , 56 , 0 , 1064 , 67 , 0 ), // #236 + INST(Fstenv , X86M_Only , O_FPU(9B,00D9,6) , 0 , 55 , 0 , 1070 , 31 , 0 ), // #237 + INST(Fstp , FpuFldFst , O_FPU(00,00D9,3) , O(000000,DB,7,_,_,_,_,_ ), 50 , 13 , 1077 , 66 , 0 ), // #238 + INST(Fstsw , FpuStsw , O_FPU(9B,00DD,7) , O_FPU(9B,DFE0,_) , 56 , 14 , 1082 , 68 , 0 ), // #239 + INST(Fsub , FpuArith , O_FPU(00,E0E8,4) , 0 , 57 , 0 , 2226 , 59 , 0 ), // #240 + INST(Fsubp , FpuRDef , O_FPU(00,DEE8,_) , 0 , 36 , 0 , 1088 , 60 , 0 ), // #241 + INST(Fsubr , FpuArith , O_FPU(00,E8E0,5) , 0 , 58 , 0 , 2232 , 59 , 0 ), // #242 + INST(Fsubrp , FpuRDef , O_FPU(00,DEE0,_) , 0 , 36 , 0 , 1094 , 60 , 0 ), // #243 + INST(Ftst , FpuOp , O_FPU(00,D9E4,_) , 0 , 34 , 0 , 1101 , 30 , 0 ), // #244 + INST(Fucom , FpuRDef , O_FPU(00,DDE0,_) , 0 , 47 , 0 , 1106 , 60 , 0 ), // #245 + INST(Fucomi , FpuR , O_FPU(00,DBE8,_) , 0 , 41 , 0 , 1112 , 62 , 49 ), // #246 + INST(Fucomip , FpuR , O_FPU(00,DFE8,_) , 0 , 43 , 0 , 1119 , 62 , 49 ), // #247 + INST(Fucomp , FpuRDef , O_FPU(00,DDE8,_) , 0 , 47 , 0 , 1127 , 60 , 0 ), // #248 + INST(Fucompp , FpuOp , O_FPU(00,DAE9,_) , 0 , 40 , 0 , 1134 , 30 , 0 ), // #249 + INST(Fwait , X86Op , O_FPU(00,009B,_) , 0 , 59 , 0 , 1142 , 30 , 0 ), // #250 + INST(Fxam , FpuOp , O_FPU(00,D9E5,_) , 0 , 34 , 0 , 1148 , 30 , 0 ), // #251 + INST(Fxch , FpuR , O_FPU(00,D9C8,_) , 0 , 34 , 0 , 1153 , 60 , 0 ), // #252 + INST(Fxrstor , X86M_Only , O(000F00,AE,1,_,_,_,_,_ ), 0 , 28 , 0 , 1158 , 31 , 51 ), // #253 + INST(Fxrstor64 , X86M_Only , O(000F00,AE,1,_,1,_,_,_ ), 0 , 27 , 0 , 1166 , 70 , 51 ), // #254 + INST(Fxsave , X86M_Only , O(000F00,AE,0,_,_,_,_,_ ), 0 , 4 , 0 , 1176 , 31 , 51 ), // #255 + INST(Fxsave64 , X86M_Only , O(000F00,AE,0,_,1,_,_,_ ), 0 , 60 , 0 , 1183 , 70 , 51 ), // #256 + INST(Fxtract , FpuOp , O_FPU(00,D9F4,_) , 0 , 34 , 0 , 1192 , 30 , 0 ), // #257 + INST(Fyl2x , FpuOp , O_FPU(00,D9F1,_) , 0 , 34 , 0 , 1200 , 30 , 0 ), // #258 + INST(Fyl2xp1 , FpuOp , O_FPU(00,D9F9,_) , 0 , 34 , 0 , 1206 , 30 , 0 ), // #259 + INST(Getsec , X86Op , O(000F00,37,_,_,_,_,_,_ ), 0 , 4 , 0 , 1214 , 30 , 52 ), // #260 + INST(Gf2p8affineinvqb , ExtRmi , O(660F3A,CF,_,_,_,_,_,_ ), 0 , 8 , 0 , 5865 , 8 , 53 ), // #261 + INST(Gf2p8affineqb , ExtRmi , O(660F3A,CE,_,_,_,_,_,_ ), 0 , 8 , 0 , 5883 , 8 , 53 ), // #262 + INST(Gf2p8mulb , ExtRm , O(660F38,CF,_,_,_,_,_,_ ), 0 , 2 , 0 , 5898 , 5 , 53 ), // #263 + INST(Haddpd , ExtRm , O(660F00,7C,_,_,_,_,_,_ ), 0 , 3 , 0 , 5909 , 5 , 6 ), // #264 + INST(Haddps , ExtRm , O(F20F00,7C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5917 , 5 , 6 ), // #265 + INST(Hlt , X86Op , O(000000,F4,_,_,_,_,_,_ ), 0 , 0 , 0 , 1221 , 30 , 0 ), // #266 + INST(Hsubpd , ExtRm , O(660F00,7D,_,_,_,_,_,_ ), 0 , 3 , 0 , 5925 , 5 , 6 ), // #267 + INST(Hsubps , ExtRm , O(F20F00,7D,_,_,_,_,_,_ ), 0 , 5 , 0 , 5933 , 5 , 6 ), // #268 + INST(Idiv , X86M_GPB_MulDiv , O(000000,F6,7,_,x,_,_,_ ), 0 , 26 , 0 , 804 , 53 , 1 ), // #269 + INST(Imul , X86Imul , O(000000,F6,5,_,x,_,_,_ ), 0 , 61 , 0 , 822 , 71 , 1 ), // #270 + INST(In , X86In , O(000000,EC,_,_,_,_,_,_ ), O(000000,E4,_,_,_,_,_,_ ), 0 , 15 , 10418, 72 , 0 ), // #271 + INST(Inc , X86IncDec , O(000000,FE,0,_,x,_,_,_ ), O(000000,40,_,_,x,_,_,_ ), 0 , 16 , 1225 , 52 , 44 ), // #272 + INST(Incsspd , X86M , O(F30F00,AE,5,_,0,_,_,_ ), 0 , 62 , 0 , 1229 , 73 , 54 ), // #273 + INST(Incsspq , X86M , O(F30F00,AE,5,_,1,_,_,_ ), 0 , 63 , 0 , 1237 , 74 , 54 ), // #274 + INST(Ins , X86Ins , O(000000,6C,_,_,_,_,_,_ ), 0 , 0 , 0 , 1908 , 75 , 0 ), // #275 + INST(Insertps , ExtRmi , O(660F3A,21,_,_,_,_,_,_ ), 0 , 8 , 0 , 6069 , 37 , 12 ), // #276 + INST(Insertq , ExtInsertq , O(F20F00,79,_,_,_,_,_,_ ), O(F20F00,78,_,_,_,_,_,_ ), 5 , 17 , 1245 , 76 , 48 ), // #277 + INST(Int , X86Int , O(000000,CD,_,_,_,_,_,_ ), 0 , 0 , 0 , 1017 , 77 , 0 ), // #278 + INST(Int3 , X86Op , O(000000,CC,_,_,_,_,_,_ ), 0 , 0 , 0 , 1253 , 30 , 0 ), // #279 + INST(Into , X86Op , O(000000,CE,_,_,_,_,_,_ ), 0 , 0 , 0 , 1258 , 78 , 55 ), // #280 + INST(Invd , X86Op , O(000F00,08,_,_,_,_,_,_ ), 0 , 4 , 0 , 10347, 30 , 42 ), // #281 + INST(Invept , X86Rm_NoSize , O(660F38,80,_,_,_,_,_,_ ), 0 , 2 , 0 , 1263 , 79 , 56 ), // #282 + INST(Invlpg , X86M_Only , O(000F00,01,7,_,_,_,_,_ ), 0 , 22 , 0 , 1270 , 31 , 42 ), // #283 + INST(Invlpga , X86Op_xAddr , O(000F01,DF,_,_,_,_,_,_ ), 0 , 21 , 0 , 1277 , 80 , 22 ), // #284 + INST(Invpcid , X86Rm_NoSize , O(660F38,82,_,_,_,_,_,_ ), 0 , 2 , 0 , 1285 , 79 , 42 ), // #285 + INST(Invvpid , X86Rm_NoSize , O(660F38,81,_,_,_,_,_,_ ), 0 , 2 , 0 , 1293 , 79 , 56 ), // #286 + INST(Iret , X86Op , O(000000,CF,_,_,_,_,_,_ ), 0 , 0 , 0 , 1301 , 81 , 1 ), // #287 + INST(Iretd , X86Op , O(000000,CF,_,_,_,_,_,_ ), 0 , 0 , 0 , 1306 , 81 , 1 ), // #288 + INST(Iretq , X86Op , O(000000,CF,_,_,1,_,_,_ ), 0 , 20 , 0 , 1312 , 82 , 1 ), // #289 + INST(Iretw , X86Op , O(660000,CF,_,_,_,_,_,_ ), 0 , 19 , 0 , 1318 , 81 , 1 ), // #290 + INST(Ja , X86Jcc , O(000F00,87,_,_,_,_,_,_ ), O(000000,77,_,_,_,_,_,_ ), 4 , 18 , 1324 , 83 , 57 ), // #291 + INST(Jae , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 4 , 19 , 1327 , 83 , 58 ), // #292 + INST(Jb , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 4 , 20 , 1331 , 83 , 58 ), // #293 + INST(Jbe , X86Jcc , O(000F00,86,_,_,_,_,_,_ ), O(000000,76,_,_,_,_,_,_ ), 4 , 21 , 1334 , 83 , 57 ), // #294 + INST(Jc , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 4 , 20 , 1338 , 83 , 58 ), // #295 + INST(Je , X86Jcc , O(000F00,84,_,_,_,_,_,_ ), O(000000,74,_,_,_,_,_,_ ), 4 , 22 , 1341 , 83 , 59 ), // #296 + INST(Jecxz , X86JecxzLoop , 0 , O(000000,E3,_,_,_,_,_,_ ), 0 , 23 , 1344 , 84 , 0 ), // #297 + INST(Jg , X86Jcc , O(000F00,8F,_,_,_,_,_,_ ), O(000000,7F,_,_,_,_,_,_ ), 4 , 24 , 1350 , 83 , 60 ), // #298 + INST(Jge , X86Jcc , O(000F00,8D,_,_,_,_,_,_ ), O(000000,7D,_,_,_,_,_,_ ), 4 , 25 , 1353 , 83 , 61 ), // #299 + INST(Jl , X86Jcc , O(000F00,8C,_,_,_,_,_,_ ), O(000000,7C,_,_,_,_,_,_ ), 4 , 26 , 1357 , 83 , 61 ), // #300 + INST(Jle , X86Jcc , O(000F00,8E,_,_,_,_,_,_ ), O(000000,7E,_,_,_,_,_,_ ), 4 , 27 , 1360 , 83 , 60 ), // #301 + INST(Jmp , X86Jmp , O(000000,FF,4,_,_,_,_,_ ), O(000000,EB,_,_,_,_,_,_ ), 9 , 28 , 1364 , 85 , 0 ), // #302 + INST(Jna , X86Jcc , O(000F00,86,_,_,_,_,_,_ ), O(000000,76,_,_,_,_,_,_ ), 4 , 21 , 1368 , 83 , 57 ), // #303 + INST(Jnae , X86Jcc , O(000F00,82,_,_,_,_,_,_ ), O(000000,72,_,_,_,_,_,_ ), 4 , 20 , 1372 , 83 , 58 ), // #304 + INST(Jnb , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 4 , 19 , 1377 , 83 , 58 ), // #305 + INST(Jnbe , X86Jcc , O(000F00,87,_,_,_,_,_,_ ), O(000000,77,_,_,_,_,_,_ ), 4 , 18 , 1381 , 83 , 57 ), // #306 + INST(Jnc , X86Jcc , O(000F00,83,_,_,_,_,_,_ ), O(000000,73,_,_,_,_,_,_ ), 4 , 19 , 1386 , 83 , 58 ), // #307 + INST(Jne , X86Jcc , O(000F00,85,_,_,_,_,_,_ ), O(000000,75,_,_,_,_,_,_ ), 4 , 29 , 1390 , 83 , 59 ), // #308 + INST(Jng , X86Jcc , O(000F00,8E,_,_,_,_,_,_ ), O(000000,7E,_,_,_,_,_,_ ), 4 , 27 , 1394 , 83 , 60 ), // #309 + INST(Jnge , X86Jcc , O(000F00,8C,_,_,_,_,_,_ ), O(000000,7C,_,_,_,_,_,_ ), 4 , 26 , 1398 , 83 , 61 ), // #310 + INST(Jnl , X86Jcc , O(000F00,8D,_,_,_,_,_,_ ), O(000000,7D,_,_,_,_,_,_ ), 4 , 25 , 1403 , 83 , 61 ), // #311 + INST(Jnle , X86Jcc , O(000F00,8F,_,_,_,_,_,_ ), O(000000,7F,_,_,_,_,_,_ ), 4 , 24 , 1407 , 83 , 60 ), // #312 + INST(Jno , X86Jcc , O(000F00,81,_,_,_,_,_,_ ), O(000000,71,_,_,_,_,_,_ ), 4 , 30 , 1412 , 83 , 55 ), // #313 + INST(Jnp , X86Jcc , O(000F00,8B,_,_,_,_,_,_ ), O(000000,7B,_,_,_,_,_,_ ), 4 , 31 , 1416 , 83 , 62 ), // #314 + INST(Jns , X86Jcc , O(000F00,89,_,_,_,_,_,_ ), O(000000,79,_,_,_,_,_,_ ), 4 , 32 , 1420 , 83 , 63 ), // #315 + INST(Jnz , X86Jcc , O(000F00,85,_,_,_,_,_,_ ), O(000000,75,_,_,_,_,_,_ ), 4 , 29 , 1424 , 83 , 59 ), // #316 + INST(Jo , X86Jcc , O(000F00,80,_,_,_,_,_,_ ), O(000000,70,_,_,_,_,_,_ ), 4 , 33 , 1428 , 83 , 55 ), // #317 + INST(Jp , X86Jcc , O(000F00,8A,_,_,_,_,_,_ ), O(000000,7A,_,_,_,_,_,_ ), 4 , 34 , 1431 , 83 , 62 ), // #318 + INST(Jpe , X86Jcc , O(000F00,8A,_,_,_,_,_,_ ), O(000000,7A,_,_,_,_,_,_ ), 4 , 34 , 1434 , 83 , 62 ), // #319 + INST(Jpo , X86Jcc , O(000F00,8B,_,_,_,_,_,_ ), O(000000,7B,_,_,_,_,_,_ ), 4 , 31 , 1438 , 83 , 62 ), // #320 + INST(Js , X86Jcc , O(000F00,88,_,_,_,_,_,_ ), O(000000,78,_,_,_,_,_,_ ), 4 , 35 , 1442 , 83 , 63 ), // #321 + INST(Jz , X86Jcc , O(000F00,84,_,_,_,_,_,_ ), O(000000,74,_,_,_,_,_,_ ), 4 , 22 , 1445 , 83 , 59 ), // #322 + INST(Kaddb , VexRvm , V(660F00,4A,_,1,0,_,_,_ ), 0 , 64 , 0 , 1448 , 86 , 64 ), // #323 + INST(Kaddd , VexRvm , V(660F00,4A,_,1,1,_,_,_ ), 0 , 65 , 0 , 1454 , 86 , 65 ), // #324 + INST(Kaddq , VexRvm , V(000F00,4A,_,1,1,_,_,_ ), 0 , 66 , 0 , 1460 , 86 , 65 ), // #325 + INST(Kaddw , VexRvm , V(000F00,4A,_,1,0,_,_,_ ), 0 , 67 , 0 , 1466 , 86 , 64 ), // #326 + INST(Kandb , VexRvm , V(660F00,41,_,1,0,_,_,_ ), 0 , 64 , 0 , 1472 , 86 , 64 ), // #327 + INST(Kandd , VexRvm , V(660F00,41,_,1,1,_,_,_ ), 0 , 65 , 0 , 1478 , 86 , 65 ), // #328 + INST(Kandnb , VexRvm , V(660F00,42,_,1,0,_,_,_ ), 0 , 64 , 0 , 1484 , 86 , 64 ), // #329 + INST(Kandnd , VexRvm , V(660F00,42,_,1,1,_,_,_ ), 0 , 65 , 0 , 1491 , 86 , 65 ), // #330 + INST(Kandnq , VexRvm , V(000F00,42,_,1,1,_,_,_ ), 0 , 66 , 0 , 1498 , 86 , 65 ), // #331 + INST(Kandnw , VexRvm , V(000F00,42,_,1,0,_,_,_ ), 0 , 67 , 0 , 1505 , 86 , 66 ), // #332 + INST(Kandq , VexRvm , V(000F00,41,_,1,1,_,_,_ ), 0 , 66 , 0 , 1512 , 86 , 65 ), // #333 + INST(Kandw , VexRvm , V(000F00,41,_,1,0,_,_,_ ), 0 , 67 , 0 , 1518 , 86 , 66 ), // #334 + INST(Kmovb , VexKmov , V(660F00,90,_,0,0,_,_,_ ), V(660F00,92,_,0,0,_,_,_ ), 68 , 36 , 1524 , 87 , 64 ), // #335 + INST(Kmovd , VexKmov , V(660F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,0,_,_,_ ), 69 , 37 , 8086 , 88 , 65 ), // #336 + INST(Kmovq , VexKmov , V(000F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,1,_,_,_ ), 70 , 38 , 8097 , 89 , 65 ), // #337 + INST(Kmovw , VexKmov , V(000F00,90,_,0,0,_,_,_ ), V(000F00,92,_,0,0,_,_,_ ), 71 , 39 , 1530 , 90 , 66 ), // #338 + INST(Knotb , VexRm , V(660F00,44,_,0,0,_,_,_ ), 0 , 68 , 0 , 1536 , 91 , 64 ), // #339 + INST(Knotd , VexRm , V(660F00,44,_,0,1,_,_,_ ), 0 , 69 , 0 , 1542 , 91 , 65 ), // #340 + INST(Knotq , VexRm , V(000F00,44,_,0,1,_,_,_ ), 0 , 70 , 0 , 1548 , 91 , 65 ), // #341 + INST(Knotw , VexRm , V(000F00,44,_,0,0,_,_,_ ), 0 , 71 , 0 , 1554 , 91 , 66 ), // #342 + INST(Korb , VexRvm , V(660F00,45,_,1,0,_,_,_ ), 0 , 64 , 0 , 1560 , 86 , 64 ), // #343 + INST(Kord , VexRvm , V(660F00,45,_,1,1,_,_,_ ), 0 , 65 , 0 , 1565 , 86 , 65 ), // #344 + INST(Korq , VexRvm , V(000F00,45,_,1,1,_,_,_ ), 0 , 66 , 0 , 1570 , 86 , 65 ), // #345 + INST(Kortestb , VexRm , V(660F00,98,_,0,0,_,_,_ ), 0 , 68 , 0 , 1575 , 91 , 67 ), // #346 + INST(Kortestd , VexRm , V(660F00,98,_,0,1,_,_,_ ), 0 , 69 , 0 , 1584 , 91 , 68 ), // #347 + INST(Kortestq , VexRm , V(000F00,98,_,0,1,_,_,_ ), 0 , 70 , 0 , 1593 , 91 , 68 ), // #348 + INST(Kortestw , VexRm , V(000F00,98,_,0,0,_,_,_ ), 0 , 71 , 0 , 1602 , 91 , 69 ), // #349 + INST(Korw , VexRvm , V(000F00,45,_,1,0,_,_,_ ), 0 , 67 , 0 , 1611 , 86 , 66 ), // #350 + INST(Kshiftlb , VexRmi , V(660F3A,32,_,0,0,_,_,_ ), 0 , 72 , 0 , 1616 , 92 , 64 ), // #351 + INST(Kshiftld , VexRmi , V(660F3A,33,_,0,0,_,_,_ ), 0 , 72 , 0 , 1625 , 92 , 65 ), // #352 + INST(Kshiftlq , VexRmi , V(660F3A,33,_,0,1,_,_,_ ), 0 , 73 , 0 , 1634 , 92 , 65 ), // #353 + INST(Kshiftlw , VexRmi , V(660F3A,32,_,0,1,_,_,_ ), 0 , 73 , 0 , 1643 , 92 , 66 ), // #354 + INST(Kshiftrb , VexRmi , V(660F3A,30,_,0,0,_,_,_ ), 0 , 72 , 0 , 1652 , 92 , 64 ), // #355 + INST(Kshiftrd , VexRmi , V(660F3A,31,_,0,0,_,_,_ ), 0 , 72 , 0 , 1661 , 92 , 65 ), // #356 + INST(Kshiftrq , VexRmi , V(660F3A,31,_,0,1,_,_,_ ), 0 , 73 , 0 , 1670 , 92 , 65 ), // #357 + INST(Kshiftrw , VexRmi , V(660F3A,30,_,0,1,_,_,_ ), 0 , 73 , 0 , 1679 , 92 , 66 ), // #358 + INST(Ktestb , VexRm , V(660F00,99,_,0,0,_,_,_ ), 0 , 68 , 0 , 1688 , 91 , 67 ), // #359 + INST(Ktestd , VexRm , V(660F00,99,_,0,1,_,_,_ ), 0 , 69 , 0 , 1695 , 91 , 68 ), // #360 + INST(Ktestq , VexRm , V(000F00,99,_,0,1,_,_,_ ), 0 , 70 , 0 , 1702 , 91 , 68 ), // #361 + INST(Ktestw , VexRm , V(000F00,99,_,0,0,_,_,_ ), 0 , 71 , 0 , 1709 , 91 , 67 ), // #362 + INST(Kunpckbw , VexRvm , V(660F00,4B,_,1,0,_,_,_ ), 0 , 64 , 0 , 1716 , 86 , 66 ), // #363 + INST(Kunpckdq , VexRvm , V(000F00,4B,_,1,1,_,_,_ ), 0 , 66 , 0 , 1725 , 86 , 65 ), // #364 + INST(Kunpckwd , VexRvm , V(000F00,4B,_,1,0,_,_,_ ), 0 , 67 , 0 , 1734 , 86 , 65 ), // #365 + INST(Kxnorb , VexRvm , V(660F00,46,_,1,0,_,_,_ ), 0 , 64 , 0 , 1743 , 86 , 64 ), // #366 + INST(Kxnord , VexRvm , V(660F00,46,_,1,1,_,_,_ ), 0 , 65 , 0 , 1750 , 86 , 65 ), // #367 + INST(Kxnorq , VexRvm , V(000F00,46,_,1,1,_,_,_ ), 0 , 66 , 0 , 1757 , 86 , 65 ), // #368 + INST(Kxnorw , VexRvm , V(000F00,46,_,1,0,_,_,_ ), 0 , 67 , 0 , 1764 , 86 , 66 ), // #369 + INST(Kxorb , VexRvm , V(660F00,47,_,1,0,_,_,_ ), 0 , 64 , 0 , 1771 , 86 , 64 ), // #370 + INST(Kxord , VexRvm , V(660F00,47,_,1,1,_,_,_ ), 0 , 65 , 0 , 1777 , 86 , 65 ), // #371 + INST(Kxorq , VexRvm , V(000F00,47,_,1,1,_,_,_ ), 0 , 66 , 0 , 1783 , 86 , 65 ), // #372 + INST(Kxorw , VexRvm , V(000F00,47,_,1,0,_,_,_ ), 0 , 67 , 0 , 1789 , 86 , 66 ), // #373 + INST(Lahf , X86Op , O(000000,9F,_,_,_,_,_,_ ), 0 , 0 , 0 , 1795 , 93 , 70 ), // #374 + INST(Lar , X86Rm , O(000F00,02,_,_,_,_,_,_ ), 0 , 4 , 0 , 1800 , 94 , 10 ), // #375 + INST(Lddqu , ExtRm , O(F20F00,F0,_,_,_,_,_,_ ), 0 , 5 , 0 , 6079 , 95 , 6 ), // #376 + INST(Ldmxcsr , X86M_Only , O(000F00,AE,2,_,_,_,_,_ ), 0 , 74 , 0 , 6086 , 96 , 5 ), // #377 + INST(Lds , X86Rm , O(000000,C5,_,_,_,_,_,_ ), 0 , 0 , 0 , 1804 , 97 , 0 ), // #378 + INST(Ldtilecfg , AmxCfg , V(000F38,49,_,0,0,_,_,_ ), 0 , 10 , 0 , 1808 , 98 , 71 ), // #379 + INST(Lea , X86Lea , O(000000,8D,_,_,x,_,_,_ ), 0 , 0 , 0 , 1818 , 99 , 0 ), // #380 + INST(Leave , X86Op , O(000000,C9,_,_,_,_,_,_ ), 0 , 0 , 0 , 1822 , 30 , 0 ), // #381 + INST(Les , X86Rm , O(000000,C4,_,_,_,_,_,_ ), 0 , 0 , 0 , 1828 , 97 , 0 ), // #382 + INST(Lfence , X86Fence , O(000F00,AE,5,_,_,_,_,_ ), 0 , 75 , 0 , 1832 , 30 , 4 ), // #383 + INST(Lfs , X86Rm , O(000F00,B4,_,_,_,_,_,_ ), 0 , 4 , 0 , 1839 , 100, 0 ), // #384 + INST(Lgdt , X86M_Only , O(000F00,01,2,_,_,_,_,_ ), 0 , 74 , 0 , 1843 , 31 , 0 ), // #385 + INST(Lgs , X86Rm , O(000F00,B5,_,_,_,_,_,_ ), 0 , 4 , 0 , 1848 , 100, 0 ), // #386 + INST(Lidt , X86M_Only , O(000F00,01,3,_,_,_,_,_ ), 0 , 76 , 0 , 1852 , 31 , 0 ), // #387 + INST(Lldt , X86M_NoSize , O(000F00,00,2,_,_,_,_,_ ), 0 , 74 , 0 , 1857 , 101, 0 ), // #388 + INST(Llwpcb , VexR_Wx , V(XOP_M9,12,0,0,x,_,_,_ ), 0 , 77 , 0 , 1862 , 102, 72 ), // #389 + INST(Lmsw , X86M_NoSize , O(000F00,01,6,_,_,_,_,_ ), 0 , 78 , 0 , 1869 , 101, 0 ), // #390 + INST(Lods , X86StrRm , O(000000,AC,_,_,_,_,_,_ ), 0 , 0 , 0 , 1874 , 103, 73 ), // #391 + INST(Loop , X86JecxzLoop , 0 , O(000000,E2,_,_,_,_,_,_ ), 0 , 40 , 1879 , 104, 0 ), // #392 + INST(Loope , X86JecxzLoop , 0 , O(000000,E1,_,_,_,_,_,_ ), 0 , 41 , 1884 , 104, 59 ), // #393 + INST(Loopne , X86JecxzLoop , 0 , O(000000,E0,_,_,_,_,_,_ ), 0 , 42 , 1890 , 104, 59 ), // #394 + INST(Lsl , X86Rm , O(000F00,03,_,_,_,_,_,_ ), 0 , 4 , 0 , 1897 , 105, 10 ), // #395 + INST(Lss , X86Rm , O(000F00,B2,_,_,_,_,_,_ ), 0 , 4 , 0 , 6577 , 100, 0 ), // #396 + INST(Ltr , X86M_NoSize , O(000F00,00,3,_,_,_,_,_ ), 0 , 76 , 0 , 1901 , 101, 0 ), // #397 + INST(Lwpins , VexVmi4_Wx , V(XOP_MA,12,0,0,x,_,_,_ ), 0 , 79 , 0 , 1905 , 106, 72 ), // #398 + INST(Lwpval , VexVmi4_Wx , V(XOP_MA,12,1,0,x,_,_,_ ), 0 , 80 , 0 , 1912 , 106, 72 ), // #399 + INST(Lzcnt , X86Rm_Raw66H , O(F30F00,BD,_,_,x,_,_,_ ), 0 , 6 , 0 , 1919 , 22 , 74 ), // #400 + INST(Maskmovdqu , ExtRm_ZDI , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 6095 , 107, 4 ), // #401 + INST(Maskmovq , ExtRm_ZDI , O(000F00,F7,_,_,_,_,_,_ ), 0 , 4 , 0 , 8094 , 108, 75 ), // #402 + INST(Maxpd , ExtRm , O(660F00,5F,_,_,_,_,_,_ ), 0 , 3 , 0 , 6129 , 5 , 4 ), // #403 + INST(Maxps , ExtRm , O(000F00,5F,_,_,_,_,_,_ ), 0 , 4 , 0 , 6136 , 5 , 5 ), // #404 + INST(Maxsd , ExtRm , O(F20F00,5F,_,_,_,_,_,_ ), 0 , 5 , 0 , 8113 , 6 , 4 ), // #405 + INST(Maxss , ExtRm , O(F30F00,5F,_,_,_,_,_,_ ), 0 , 6 , 0 , 6150 , 7 , 5 ), // #406 + INST(Mcommit , X86Op , O(F30F01,FA,_,_,_,_,_,_ ), 0 , 81 , 0 , 1925 , 30 , 76 ), // #407 + INST(Mfence , X86Fence , O(000F00,AE,6,_,_,_,_,_ ), 0 , 78 , 0 , 1933 , 30 , 4 ), // #408 + INST(Minpd , ExtRm , O(660F00,5D,_,_,_,_,_,_ ), 0 , 3 , 0 , 6179 , 5 , 4 ), // #409 + INST(Minps , ExtRm , O(000F00,5D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6186 , 5 , 5 ), // #410 + INST(Minsd , ExtRm , O(F20F00,5D,_,_,_,_,_,_ ), 0 , 5 , 0 , 8177 , 6 , 4 ), // #411 + INST(Minss , ExtRm , O(F30F00,5D,_,_,_,_,_,_ ), 0 , 6 , 0 , 6200 , 7 , 5 ), // #412 + INST(Monitor , X86Op , O(000F01,C8,_,_,_,_,_,_ ), 0 , 21 , 0 , 3192 , 109, 77 ), // #413 + INST(Monitorx , X86Op , O(000F01,FA,_,_,_,_,_,_ ), 0 , 21 , 0 , 1940 , 109, 78 ), // #414 + INST(Mov , X86Mov , 0 , 0 , 0 , 0 , 138 , 110, 0 ), // #415 + INST(Movapd , ExtMov , O(660F00,28,_,_,_,_,_,_ ), O(660F00,29,_,_,_,_,_,_ ), 3 , 43 , 6231 , 111, 4 ), // #416 + INST(Movaps , ExtMov , O(000F00,28,_,_,_,_,_,_ ), O(000F00,29,_,_,_,_,_,_ ), 4 , 44 , 6239 , 111, 5 ), // #417 + INST(Movbe , ExtMovbe , O(000F38,F0,_,_,x,_,_,_ ), O(000F38,F1,_,_,x,_,_,_ ), 82 , 45 , 651 , 112, 79 ), // #418 + INST(Movd , ExtMovd , O(000F00,6E,_,_,_,_,_,_ ), O(000F00,7E,_,_,_,_,_,_ ), 4 , 46 , 8087 , 113, 80 ), // #419 + INST(Movddup , ExtMov , O(F20F00,12,_,_,_,_,_,_ ), 0 , 5 , 0 , 6253 , 6 , 6 ), // #420 + INST(Movdir64b , X86EnqcmdMovdir64b , O(660F38,F8,_,_,_,_,_,_ ), 0 , 2 , 0 , 1949 , 114, 81 ), // #421 + INST(Movdiri , X86MovntiMovdiri , O(000F38,F9,_,_,_,_,_,_ ), 0 , 82 , 0 , 1959 , 115, 82 ), // #422 + INST(Movdq2q , ExtMov , O(F20F00,D6,_,_,_,_,_,_ ), 0 , 5 , 0 , 1967 , 116, 4 ), // #423 + INST(Movdqa , ExtMov , O(660F00,6F,_,_,_,_,_,_ ), O(660F00,7F,_,_,_,_,_,_ ), 3 , 47 , 6262 , 111, 4 ), // #424 + INST(Movdqu , ExtMov , O(F30F00,6F,_,_,_,_,_,_ ), O(F30F00,7F,_,_,_,_,_,_ ), 6 , 48 , 6099 , 111, 4 ), // #425 + INST(Movhlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), 0 , 4 , 0 , 6337 , 117, 5 ), // #426 + INST(Movhpd , ExtMov , O(660F00,16,_,_,_,_,_,_ ), O(660F00,17,_,_,_,_,_,_ ), 3 , 49 , 6346 , 118, 4 ), // #427 + INST(Movhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), O(000F00,17,_,_,_,_,_,_ ), 4 , 50 , 6354 , 118, 5 ), // #428 + INST(Movlhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), 0 , 4 , 0 , 6362 , 117, 5 ), // #429 + INST(Movlpd , ExtMov , O(660F00,12,_,_,_,_,_,_ ), O(660F00,13,_,_,_,_,_,_ ), 3 , 51 , 6371 , 118, 4 ), // #430 + INST(Movlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), O(000F00,13,_,_,_,_,_,_ ), 4 , 52 , 6379 , 118, 5 ), // #431 + INST(Movmskpd , ExtMov , O(660F00,50,_,_,_,_,_,_ ), 0 , 3 , 0 , 6387 , 119, 4 ), // #432 + INST(Movmskps , ExtMov , O(000F00,50,_,_,_,_,_,_ ), 0 , 4 , 0 , 6397 , 119, 5 ), // #433 + INST(Movntdq , ExtMov , 0 , O(660F00,E7,_,_,_,_,_,_ ), 0 , 53 , 6407 , 120, 4 ), // #434 + INST(Movntdqa , ExtMov , O(660F38,2A,_,_,_,_,_,_ ), 0 , 2 , 0 , 6416 , 95 , 12 ), // #435 + INST(Movnti , X86MovntiMovdiri , O(000F00,C3,_,_,x,_,_,_ ), 0 , 4 , 0 , 1975 , 115, 4 ), // #436 + INST(Movntpd , ExtMov , 0 , O(660F00,2B,_,_,_,_,_,_ ), 0 , 54 , 6426 , 120, 4 ), // #437 + INST(Movntps , ExtMov , 0 , O(000F00,2B,_,_,_,_,_,_ ), 0 , 55 , 6435 , 120, 5 ), // #438 + INST(Movntq , ExtMov , 0 , O(000F00,E7,_,_,_,_,_,_ ), 0 , 56 , 1982 , 121, 75 ), // #439 + INST(Movntsd , ExtMov , 0 , O(F20F00,2B,_,_,_,_,_,_ ), 0 , 57 , 1989 , 122, 48 ), // #440 + INST(Movntss , ExtMov , 0 , O(F30F00,2B,_,_,_,_,_,_ ), 0 , 58 , 1997 , 123, 48 ), // #441 + INST(Movq , ExtMovq , O(000F00,6E,_,_,x,_,_,_ ), O(000F00,7E,_,_,x,_,_,_ ), 4 , 59 , 8098 , 124, 80 ), // #442 + INST(Movq2dq , ExtRm , O(F30F00,D6,_,_,_,_,_,_ ), 0 , 6 , 0 , 2005 , 125, 4 ), // #443 + INST(Movs , X86StrMm , O(000000,A4,_,_,_,_,_,_ ), 0 , 0 , 0 , 434 , 126, 73 ), // #444 + INST(Movsd , ExtMov , O(F20F00,10,_,_,_,_,_,_ ), O(F20F00,11,_,_,_,_,_,_ ), 5 , 60 , 6450 , 127, 4 ), // #445 + INST(Movshdup , ExtRm , O(F30F00,16,_,_,_,_,_,_ ), 0 , 6 , 0 , 6457 , 5 , 6 ), // #446 + INST(Movsldup , ExtRm , O(F30F00,12,_,_,_,_,_,_ ), 0 , 6 , 0 , 6467 , 5 , 6 ), // #447 + INST(Movss , ExtMov , O(F30F00,10,_,_,_,_,_,_ ), O(F30F00,11,_,_,_,_,_,_ ), 6 , 61 , 6477 , 128, 5 ), // #448 + INST(Movsx , X86MovsxMovzx , O(000F00,BE,_,_,x,_,_,_ ), 0 , 4 , 0 , 2013 , 129, 0 ), // #449 + INST(Movsxd , X86Rm , O(000000,63,_,_,x,_,_,_ ), 0 , 0 , 0 , 2019 , 130, 0 ), // #450 + INST(Movupd , ExtMov , O(660F00,10,_,_,_,_,_,_ ), O(660F00,11,_,_,_,_,_,_ ), 3 , 62 , 6484 , 111, 4 ), // #451 + INST(Movups , ExtMov , O(000F00,10,_,_,_,_,_,_ ), O(000F00,11,_,_,_,_,_,_ ), 4 , 63 , 6492 , 111, 5 ), // #452 + INST(Movzx , X86MovsxMovzx , O(000F00,B6,_,_,x,_,_,_ ), 0 , 4 , 0 , 2026 , 129, 0 ), // #453 + INST(Mpsadbw , ExtRmi , O(660F3A,42,_,_,_,_,_,_ ), 0 , 8 , 0 , 6500 , 8 , 12 ), // #454 + INST(Mul , X86M_GPB_MulDiv , O(000000,F6,4,_,x,_,_,_ ), 0 , 9 , 0 , 823 , 53 , 1 ), // #455 + INST(Mulpd , ExtRm , O(660F00,59,_,_,_,_,_,_ ), 0 , 3 , 0 , 6554 , 5 , 4 ), // #456 + INST(Mulps , ExtRm , O(000F00,59,_,_,_,_,_,_ ), 0 , 4 , 0 , 6561 , 5 , 5 ), // #457 + INST(Mulsd , ExtRm , O(F20F00,59,_,_,_,_,_,_ ), 0 , 5 , 0 , 6568 , 6 , 4 ), // #458 + INST(Mulss , ExtRm , O(F30F00,59,_,_,_,_,_,_ ), 0 , 6 , 0 , 6575 , 7 , 5 ), // #459 + INST(Mulx , VexRvm_ZDX_Wx , V(F20F38,F6,_,0,x,_,_,_ ), 0 , 83 , 0 , 2032 , 131, 83 ), // #460 + INST(Mwait , X86Op , O(000F01,C9,_,_,_,_,_,_ ), 0 , 21 , 0 , 3201 , 132, 77 ), // #461 + INST(Mwaitx , X86Op , O(000F01,FB,_,_,_,_,_,_ ), 0 , 21 , 0 , 2037 , 133, 78 ), // #462 + INST(Neg , X86M_GPB , O(000000,F6,3,_,x,_,_,_ ), 0 , 84 , 0 , 2044 , 134, 1 ), // #463 + INST(Nop , X86M_Nop , O(000000,90,_,_,_,_,_,_ ), 0 , 0 , 0 , 954 , 135, 0 ), // #464 + INST(Not , X86M_GPB , O(000000,F6,2,_,x,_,_,_ ), 0 , 1 , 0 , 2048 , 134, 0 ), // #465 + INST(Or , X86Arith , O(000000,08,1,_,x,_,_,_ ), 0 , 30 , 0 , 3197 , 136, 1 ), // #466 + INST(Orpd , ExtRm , O(660F00,56,_,_,_,_,_,_ ), 0 , 3 , 0 , 10304, 11 , 4 ), // #467 + INST(Orps , ExtRm , O(000F00,56,_,_,_,_,_,_ ), 0 , 4 , 0 , 10311, 11 , 5 ), // #468 + INST(Out , X86Out , O(000000,EE,_,_,_,_,_,_ ), O(000000,E6,_,_,_,_,_,_ ), 0 , 64 , 2052 , 137, 0 ), // #469 + INST(Outs , X86Outs , O(000000,6E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2056 , 138, 0 ), // #470 + INST(Pabsb , ExtRm_P , O(000F38,1C,_,_,_,_,_,_ ), 0 , 82 , 0 , 6657 , 139, 84 ), // #471 + INST(Pabsd , ExtRm_P , O(000F38,1E,_,_,_,_,_,_ ), 0 , 82 , 0 , 6664 , 139, 84 ), // #472 + INST(Pabsw , ExtRm_P , O(000F38,1D,_,_,_,_,_,_ ), 0 , 82 , 0 , 6678 , 139, 84 ), // #473 + INST(Packssdw , ExtRm_P , O(000F00,6B,_,_,_,_,_,_ ), 0 , 4 , 0 , 6685 , 139, 80 ), // #474 + INST(Packsswb , ExtRm_P , O(000F00,63,_,_,_,_,_,_ ), 0 , 4 , 0 , 6695 , 139, 80 ), // #475 + INST(Packusdw , ExtRm , O(660F38,2B,_,_,_,_,_,_ ), 0 , 2 , 0 , 6705 , 5 , 12 ), // #476 + INST(Packuswb , ExtRm_P , O(000F00,67,_,_,_,_,_,_ ), 0 , 4 , 0 , 6715 , 139, 80 ), // #477 + INST(Paddb , ExtRm_P , O(000F00,FC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6725 , 139, 80 ), // #478 + INST(Paddd , ExtRm_P , O(000F00,FE,_,_,_,_,_,_ ), 0 , 4 , 0 , 6732 , 139, 80 ), // #479 + INST(Paddq , ExtRm_P , O(000F00,D4,_,_,_,_,_,_ ), 0 , 4 , 0 , 6739 , 139, 4 ), // #480 + INST(Paddsb , ExtRm_P , O(000F00,EC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6746 , 139, 80 ), // #481 + INST(Paddsw , ExtRm_P , O(000F00,ED,_,_,_,_,_,_ ), 0 , 4 , 0 , 6754 , 139, 80 ), // #482 + INST(Paddusb , ExtRm_P , O(000F00,DC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6762 , 139, 80 ), // #483 + INST(Paddusw , ExtRm_P , O(000F00,DD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6771 , 139, 80 ), // #484 + INST(Paddw , ExtRm_P , O(000F00,FD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6780 , 139, 80 ), // #485 + INST(Palignr , ExtRmi_P , O(000F3A,0F,_,_,_,_,_,_ ), 0 , 85 , 0 , 6787 , 140, 6 ), // #486 + INST(Pand , ExtRm_P , O(000F00,DB,_,_,_,_,_,_ ), 0 , 4 , 0 , 6796 , 141, 80 ), // #487 + INST(Pandn , ExtRm_P , O(000F00,DF,_,_,_,_,_,_ ), 0 , 4 , 0 , 6809 , 142, 80 ), // #488 + INST(Pause , X86Op , O(F30000,90,_,_,_,_,_,_ ), 0 , 86 , 0 , 3161 , 30 , 0 ), // #489 + INST(Pavgb , ExtRm_P , O(000F00,E0,_,_,_,_,_,_ ), 0 , 4 , 0 , 6839 , 139, 85 ), // #490 + INST(Pavgusb , Ext3dNow , O(000F0F,BF,_,_,_,_,_,_ ), 0 , 87 , 0 , 2061 , 143, 50 ), // #491 + INST(Pavgw , ExtRm_P , O(000F00,E3,_,_,_,_,_,_ ), 0 , 4 , 0 , 6846 , 139, 85 ), // #492 + INST(Pblendvb , ExtRm_XMM0 , O(660F38,10,_,_,_,_,_,_ ), 0 , 2 , 0 , 6862 , 15 , 12 ), // #493 + INST(Pblendw , ExtRmi , O(660F3A,0E,_,_,_,_,_,_ ), 0 , 8 , 0 , 6872 , 8 , 12 ), // #494 + INST(Pclmulqdq , ExtRmi , O(660F3A,44,_,_,_,_,_,_ ), 0 , 8 , 0 , 6965 , 8 , 86 ), // #495 + INST(Pcmpeqb , ExtRm_P , O(000F00,74,_,_,_,_,_,_ ), 0 , 4 , 0 , 6997 , 142, 80 ), // #496 + INST(Pcmpeqd , ExtRm_P , O(000F00,76,_,_,_,_,_,_ ), 0 , 4 , 0 , 7006 , 142, 80 ), // #497 + INST(Pcmpeqq , ExtRm , O(660F38,29,_,_,_,_,_,_ ), 0 , 2 , 0 , 7015 , 144, 12 ), // #498 + INST(Pcmpeqw , ExtRm_P , O(000F00,75,_,_,_,_,_,_ ), 0 , 4 , 0 , 7024 , 142, 80 ), // #499 + INST(Pcmpestri , ExtRmi , O(660F3A,61,_,_,_,_,_,_ ), 0 , 8 , 0 , 7033 , 145, 87 ), // #500 + INST(Pcmpestrm , ExtRmi , O(660F3A,60,_,_,_,_,_,_ ), 0 , 8 , 0 , 7044 , 146, 87 ), // #501 + INST(Pcmpgtb , ExtRm_P , O(000F00,64,_,_,_,_,_,_ ), 0 , 4 , 0 , 7055 , 142, 80 ), // #502 + INST(Pcmpgtd , ExtRm_P , O(000F00,66,_,_,_,_,_,_ ), 0 , 4 , 0 , 7064 , 142, 80 ), // #503 + INST(Pcmpgtq , ExtRm , O(660F38,37,_,_,_,_,_,_ ), 0 , 2 , 0 , 7073 , 144, 43 ), // #504 + INST(Pcmpgtw , ExtRm_P , O(000F00,65,_,_,_,_,_,_ ), 0 , 4 , 0 , 7082 , 142, 80 ), // #505 + INST(Pcmpistri , ExtRmi , O(660F3A,63,_,_,_,_,_,_ ), 0 , 8 , 0 , 7091 , 147, 87 ), // #506 + INST(Pcmpistrm , ExtRmi , O(660F3A,62,_,_,_,_,_,_ ), 0 , 8 , 0 , 7102 , 148, 87 ), // #507 + INST(Pconfig , X86Op , O(000F01,C5,_,_,_,_,_,_ ), 0 , 21 , 0 , 2069 , 30 , 88 ), // #508 + INST(Pdep , VexRvm_Wx , V(F20F38,F5,_,0,x,_,_,_ ), 0 , 83 , 0 , 2077 , 10 , 83 ), // #509 + INST(Pext , VexRvm_Wx , V(F30F38,F5,_,0,x,_,_,_ ), 0 , 88 , 0 , 2082 , 10 , 83 ), // #510 + INST(Pextrb , ExtExtract , O(000F3A,14,_,_,_,_,_,_ ), 0 , 85 , 0 , 7589 , 149, 12 ), // #511 + INST(Pextrd , ExtExtract , O(000F3A,16,_,_,_,_,_,_ ), 0 , 85 , 0 , 7597 , 57 , 12 ), // #512 + INST(Pextrq , ExtExtract , O(000F3A,16,_,_,1,_,_,_ ), 0 , 89 , 0 , 7605 , 150, 12 ), // #513 + INST(Pextrw , ExtPextrw , O(000F00,C5,_,_,_,_,_,_ ), O(000F3A,15,_,_,_,_,_,_ ), 4 , 65 , 7613 , 151, 89 ), // #514 + INST(Pf2id , Ext3dNow , O(000F0F,1D,_,_,_,_,_,_ ), 0 , 87 , 0 , 2087 , 143, 50 ), // #515 + INST(Pf2iw , Ext3dNow , O(000F0F,1C,_,_,_,_,_,_ ), 0 , 87 , 0 , 2093 , 143, 90 ), // #516 + INST(Pfacc , Ext3dNow , O(000F0F,AE,_,_,_,_,_,_ ), 0 , 87 , 0 , 2099 , 143, 50 ), // #517 + INST(Pfadd , Ext3dNow , O(000F0F,9E,_,_,_,_,_,_ ), 0 , 87 , 0 , 2105 , 143, 50 ), // #518 + INST(Pfcmpeq , Ext3dNow , O(000F0F,B0,_,_,_,_,_,_ ), 0 , 87 , 0 , 2111 , 143, 50 ), // #519 + INST(Pfcmpge , Ext3dNow , O(000F0F,90,_,_,_,_,_,_ ), 0 , 87 , 0 , 2119 , 143, 50 ), // #520 + INST(Pfcmpgt , Ext3dNow , O(000F0F,A0,_,_,_,_,_,_ ), 0 , 87 , 0 , 2127 , 143, 50 ), // #521 + INST(Pfmax , Ext3dNow , O(000F0F,A4,_,_,_,_,_,_ ), 0 , 87 , 0 , 2135 , 143, 50 ), // #522 + INST(Pfmin , Ext3dNow , O(000F0F,94,_,_,_,_,_,_ ), 0 , 87 , 0 , 2141 , 143, 50 ), // #523 + INST(Pfmul , Ext3dNow , O(000F0F,B4,_,_,_,_,_,_ ), 0 , 87 , 0 , 2147 , 143, 50 ), // #524 + INST(Pfnacc , Ext3dNow , O(000F0F,8A,_,_,_,_,_,_ ), 0 , 87 , 0 , 2153 , 143, 90 ), // #525 + INST(Pfpnacc , Ext3dNow , O(000F0F,8E,_,_,_,_,_,_ ), 0 , 87 , 0 , 2160 , 143, 90 ), // #526 + INST(Pfrcp , Ext3dNow , O(000F0F,96,_,_,_,_,_,_ ), 0 , 87 , 0 , 2168 , 143, 50 ), // #527 + INST(Pfrcpit1 , Ext3dNow , O(000F0F,A6,_,_,_,_,_,_ ), 0 , 87 , 0 , 2174 , 143, 50 ), // #528 + INST(Pfrcpit2 , Ext3dNow , O(000F0F,B6,_,_,_,_,_,_ ), 0 , 87 , 0 , 2183 , 143, 50 ), // #529 + INST(Pfrcpv , Ext3dNow , O(000F0F,86,_,_,_,_,_,_ ), 0 , 87 , 0 , 2192 , 143, 91 ), // #530 + INST(Pfrsqit1 , Ext3dNow , O(000F0F,A7,_,_,_,_,_,_ ), 0 , 87 , 0 , 2199 , 143, 50 ), // #531 + INST(Pfrsqrt , Ext3dNow , O(000F0F,97,_,_,_,_,_,_ ), 0 , 87 , 0 , 2208 , 143, 50 ), // #532 + INST(Pfrsqrtv , Ext3dNow , O(000F0F,87,_,_,_,_,_,_ ), 0 , 87 , 0 , 2216 , 143, 91 ), // #533 + INST(Pfsub , Ext3dNow , O(000F0F,9A,_,_,_,_,_,_ ), 0 , 87 , 0 , 2225 , 143, 50 ), // #534 + INST(Pfsubr , Ext3dNow , O(000F0F,AA,_,_,_,_,_,_ ), 0 , 87 , 0 , 2231 , 143, 50 ), // #535 + INST(Phaddd , ExtRm_P , O(000F38,02,_,_,_,_,_,_ ), 0 , 82 , 0 , 7692 , 139, 84 ), // #536 + INST(Phaddsw , ExtRm_P , O(000F38,03,_,_,_,_,_,_ ), 0 , 82 , 0 , 7709 , 139, 84 ), // #537 + INST(Phaddw , ExtRm_P , O(000F38,01,_,_,_,_,_,_ ), 0 , 82 , 0 , 7778 , 139, 84 ), // #538 + INST(Phminposuw , ExtRm , O(660F38,41,_,_,_,_,_,_ ), 0 , 2 , 0 , 7804 , 5 , 12 ), // #539 + INST(Phsubd , ExtRm_P , O(000F38,06,_,_,_,_,_,_ ), 0 , 82 , 0 , 7825 , 139, 84 ), // #540 + INST(Phsubsw , ExtRm_P , O(000F38,07,_,_,_,_,_,_ ), 0 , 82 , 0 , 7842 , 139, 84 ), // #541 + INST(Phsubw , ExtRm_P , O(000F38,05,_,_,_,_,_,_ ), 0 , 82 , 0 , 7851 , 139, 84 ), // #542 + INST(Pi2fd , Ext3dNow , O(000F0F,0D,_,_,_,_,_,_ ), 0 , 87 , 0 , 2238 , 143, 50 ), // #543 + INST(Pi2fw , Ext3dNow , O(000F0F,0C,_,_,_,_,_,_ ), 0 , 87 , 0 , 2244 , 143, 90 ), // #544 + INST(Pinsrb , ExtRmi , O(660F3A,20,_,_,_,_,_,_ ), 0 , 8 , 0 , 7868 , 152, 12 ), // #545 + INST(Pinsrd , ExtRmi , O(660F3A,22,_,_,_,_,_,_ ), 0 , 8 , 0 , 7876 , 153, 12 ), // #546 + INST(Pinsrq , ExtRmi , O(660F3A,22,_,_,1,_,_,_ ), 0 , 90 , 0 , 7884 , 154, 12 ), // #547 + INST(Pinsrw , ExtRmi_P , O(000F00,C4,_,_,_,_,_,_ ), 0 , 4 , 0 , 7892 , 155, 85 ), // #548 + INST(Pmaddubsw , ExtRm_P , O(000F38,04,_,_,_,_,_,_ ), 0 , 82 , 0 , 8062 , 139, 84 ), // #549 + INST(Pmaddwd , ExtRm_P , O(000F00,F5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8073 , 139, 80 ), // #550 + INST(Pmaxsb , ExtRm , O(660F38,3C,_,_,_,_,_,_ ), 0 , 2 , 0 , 8104 , 11 , 12 ), // #551 + INST(Pmaxsd , ExtRm , O(660F38,3D,_,_,_,_,_,_ ), 0 , 2 , 0 , 8112 , 11 , 12 ), // #552 + INST(Pmaxsw , ExtRm_P , O(000F00,EE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8128 , 141, 85 ), // #553 + INST(Pmaxub , ExtRm_P , O(000F00,DE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8136 , 141, 85 ), // #554 + INST(Pmaxud , ExtRm , O(660F38,3F,_,_,_,_,_,_ ), 0 , 2 , 0 , 8144 , 11 , 12 ), // #555 + INST(Pmaxuw , ExtRm , O(660F38,3E,_,_,_,_,_,_ ), 0 , 2 , 0 , 8160 , 11 , 12 ), // #556 + INST(Pminsb , ExtRm , O(660F38,38,_,_,_,_,_,_ ), 0 , 2 , 0 , 8168 , 11 , 12 ), // #557 + INST(Pminsd , ExtRm , O(660F38,39,_,_,_,_,_,_ ), 0 , 2 , 0 , 8176 , 11 , 12 ), // #558 + INST(Pminsw , ExtRm_P , O(000F00,EA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8192 , 141, 85 ), // #559 + INST(Pminub , ExtRm_P , O(000F00,DA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8200 , 141, 85 ), // #560 + INST(Pminud , ExtRm , O(660F38,3B,_,_,_,_,_,_ ), 0 , 2 , 0 , 8208 , 11 , 12 ), // #561 + INST(Pminuw , ExtRm , O(660F38,3A,_,_,_,_,_,_ ), 0 , 2 , 0 , 8224 , 11 , 12 ), // #562 + INST(Pmovmskb , ExtRm_P , O(000F00,D7,_,_,_,_,_,_ ), 0 , 4 , 0 , 8302 , 156, 85 ), // #563 + INST(Pmovsxbd , ExtRm , O(660F38,21,_,_,_,_,_,_ ), 0 , 2 , 0 , 8399 , 7 , 12 ), // #564 + INST(Pmovsxbq , ExtRm , O(660F38,22,_,_,_,_,_,_ ), 0 , 2 , 0 , 8409 , 157, 12 ), // #565 + INST(Pmovsxbw , ExtRm , O(660F38,20,_,_,_,_,_,_ ), 0 , 2 , 0 , 8419 , 6 , 12 ), // #566 + INST(Pmovsxdq , ExtRm , O(660F38,25,_,_,_,_,_,_ ), 0 , 2 , 0 , 8429 , 6 , 12 ), // #567 + INST(Pmovsxwd , ExtRm , O(660F38,23,_,_,_,_,_,_ ), 0 , 2 , 0 , 8439 , 6 , 12 ), // #568 + INST(Pmovsxwq , ExtRm , O(660F38,24,_,_,_,_,_,_ ), 0 , 2 , 0 , 8449 , 7 , 12 ), // #569 + INST(Pmovzxbd , ExtRm , O(660F38,31,_,_,_,_,_,_ ), 0 , 2 , 0 , 8536 , 7 , 12 ), // #570 + INST(Pmovzxbq , ExtRm , O(660F38,32,_,_,_,_,_,_ ), 0 , 2 , 0 , 8546 , 157, 12 ), // #571 + INST(Pmovzxbw , ExtRm , O(660F38,30,_,_,_,_,_,_ ), 0 , 2 , 0 , 8556 , 6 , 12 ), // #572 + INST(Pmovzxdq , ExtRm , O(660F38,35,_,_,_,_,_,_ ), 0 , 2 , 0 , 8566 , 6 , 12 ), // #573 + INST(Pmovzxwd , ExtRm , O(660F38,33,_,_,_,_,_,_ ), 0 , 2 , 0 , 8576 , 6 , 12 ), // #574 + INST(Pmovzxwq , ExtRm , O(660F38,34,_,_,_,_,_,_ ), 0 , 2 , 0 , 8586 , 7 , 12 ), // #575 + INST(Pmuldq , ExtRm , O(660F38,28,_,_,_,_,_,_ ), 0 , 2 , 0 , 8596 , 5 , 12 ), // #576 + INST(Pmulhrsw , ExtRm_P , O(000F38,0B,_,_,_,_,_,_ ), 0 , 82 , 0 , 8604 , 139, 84 ), // #577 + INST(Pmulhrw , Ext3dNow , O(000F0F,B7,_,_,_,_,_,_ ), 0 , 87 , 0 , 2250 , 143, 50 ), // #578 + INST(Pmulhuw , ExtRm_P , O(000F00,E4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8614 , 139, 85 ), // #579 + INST(Pmulhw , ExtRm_P , O(000F00,E5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8623 , 139, 80 ), // #580 + INST(Pmulld , ExtRm , O(660F38,40,_,_,_,_,_,_ ), 0 , 2 , 0 , 8631 , 5 , 12 ), // #581 + INST(Pmullw , ExtRm_P , O(000F00,D5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8647 , 139, 80 ), // #582 + INST(Pmuludq , ExtRm_P , O(000F00,F4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8670 , 139, 4 ), // #583 + INST(Pop , X86Pop , O(000000,8F,0,_,_,_,_,_ ), O(000000,58,_,_,_,_,_,_ ), 0 , 66 , 2258 , 158, 0 ), // #584 + INST(Popa , X86Op , O(660000,61,_,_,_,_,_,_ ), 0 , 19 , 0 , 2262 , 78 , 0 ), // #585 + INST(Popad , X86Op , O(000000,61,_,_,_,_,_,_ ), 0 , 0 , 0 , 2267 , 78 , 0 ), // #586 + INST(Popcnt , X86Rm_Raw66H , O(F30F00,B8,_,_,x,_,_,_ ), 0 , 6 , 0 , 2273 , 22 , 92 ), // #587 + INST(Popf , X86Op , O(660000,9D,_,_,_,_,_,_ ), 0 , 19 , 0 , 2280 , 30 , 93 ), // #588 + INST(Popfd , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2285 , 78 , 93 ), // #589 + INST(Popfq , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2291 , 159, 93 ), // #590 + INST(Por , ExtRm_P , O(000F00,EB,_,_,_,_,_,_ ), 0 , 4 , 0 , 8715 , 141, 80 ), // #591 + INST(Prefetch , X86M_Only , O(000F00,0D,0,_,_,_,_,_ ), 0 , 4 , 0 , 2297 , 31 , 50 ), // #592 + INST(Prefetchnta , X86M_Only , O(000F00,18,0,_,_,_,_,_ ), 0 , 4 , 0 , 2306 , 31 , 75 ), // #593 + INST(Prefetcht0 , X86M_Only , O(000F00,18,1,_,_,_,_,_ ), 0 , 28 , 0 , 2318 , 31 , 75 ), // #594 + INST(Prefetcht1 , X86M_Only , O(000F00,18,2,_,_,_,_,_ ), 0 , 74 , 0 , 2329 , 31 , 75 ), // #595 + INST(Prefetcht2 , X86M_Only , O(000F00,18,3,_,_,_,_,_ ), 0 , 76 , 0 , 2340 , 31 , 75 ), // #596 + INST(Prefetchw , X86M_Only , O(000F00,0D,1,_,_,_,_,_ ), 0 , 28 , 0 , 2351 , 31 , 94 ), // #597 + INST(Prefetchwt1 , X86M_Only , O(000F00,0D,2,_,_,_,_,_ ), 0 , 74 , 0 , 2361 , 31 , 95 ), // #598 + INST(Psadbw , ExtRm_P , O(000F00,F6,_,_,_,_,_,_ ), 0 , 4 , 0 , 4268 , 139, 85 ), // #599 + INST(Pshufb , ExtRm_P , O(000F38,00,_,_,_,_,_,_ ), 0 , 82 , 0 , 9041 , 139, 84 ), // #600 + INST(Pshufd , ExtRmi , O(660F00,70,_,_,_,_,_,_ ), 0 , 3 , 0 , 9062 , 8 , 4 ), // #601 + INST(Pshufhw , ExtRmi , O(F30F00,70,_,_,_,_,_,_ ), 0 , 6 , 0 , 9070 , 8 , 4 ), // #602 + INST(Pshuflw , ExtRmi , O(F20F00,70,_,_,_,_,_,_ ), 0 , 5 , 0 , 9079 , 8 , 4 ), // #603 + INST(Pshufw , ExtRmi_P , O(000F00,70,_,_,_,_,_,_ ), 0 , 4 , 0 , 2373 , 160, 75 ), // #604 + INST(Psignb , ExtRm_P , O(000F38,08,_,_,_,_,_,_ ), 0 , 82 , 0 , 9088 , 139, 84 ), // #605 + INST(Psignd , ExtRm_P , O(000F38,0A,_,_,_,_,_,_ ), 0 , 82 , 0 , 9096 , 139, 84 ), // #606 + INST(Psignw , ExtRm_P , O(000F38,09,_,_,_,_,_,_ ), 0 , 82 , 0 , 9104 , 139, 84 ), // #607 + INST(Pslld , ExtRmRi_P , O(000F00,F2,_,_,_,_,_,_ ), O(000F00,72,6,_,_,_,_,_ ), 4 , 67 , 9112 , 161, 80 ), // #608 + INST(Pslldq , ExtRmRi , 0 , O(660F00,73,7,_,_,_,_,_ ), 0 , 68 , 9119 , 162, 4 ), // #609 + INST(Psllq , ExtRmRi_P , O(000F00,F3,_,_,_,_,_,_ ), O(000F00,73,6,_,_,_,_,_ ), 4 , 69 , 9127 , 161, 80 ), // #610 + INST(Psllw , ExtRmRi_P , O(000F00,F1,_,_,_,_,_,_ ), O(000F00,71,6,_,_,_,_,_ ), 4 , 70 , 9158 , 161, 80 ), // #611 + INST(Psmash , X86Op , O(F30F01,FF,_,_,_,_,_,_ ), 0 , 81 , 0 , 2380 , 159, 96 ), // #612 + INST(Psrad , ExtRmRi_P , O(000F00,E2,_,_,_,_,_,_ ), O(000F00,72,4,_,_,_,_,_ ), 4 , 71 , 9165 , 161, 80 ), // #613 + INST(Psraw , ExtRmRi_P , O(000F00,E1,_,_,_,_,_,_ ), O(000F00,71,4,_,_,_,_,_ ), 4 , 72 , 9203 , 161, 80 ), // #614 + INST(Psrld , ExtRmRi_P , O(000F00,D2,_,_,_,_,_,_ ), O(000F00,72,2,_,_,_,_,_ ), 4 , 73 , 9210 , 161, 80 ), // #615 + INST(Psrldq , ExtRmRi , 0 , O(660F00,73,3,_,_,_,_,_ ), 0 , 74 , 9217 , 162, 4 ), // #616 + INST(Psrlq , ExtRmRi_P , O(000F00,D3,_,_,_,_,_,_ ), O(000F00,73,2,_,_,_,_,_ ), 4 , 75 , 9225 , 161, 80 ), // #617 + INST(Psrlw , ExtRmRi_P , O(000F00,D1,_,_,_,_,_,_ ), O(000F00,71,2,_,_,_,_,_ ), 4 , 76 , 9256 , 161, 80 ), // #618 + INST(Psubb , ExtRm_P , O(000F00,F8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9263 , 142, 80 ), // #619 + INST(Psubd , ExtRm_P , O(000F00,FA,_,_,_,_,_,_ ), 0 , 4 , 0 , 9270 , 142, 80 ), // #620 + INST(Psubq , ExtRm_P , O(000F00,FB,_,_,_,_,_,_ ), 0 , 4 , 0 , 9277 , 142, 4 ), // #621 + INST(Psubsb , ExtRm_P , O(000F00,E8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9284 , 142, 80 ), // #622 + INST(Psubsw , ExtRm_P , O(000F00,E9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9292 , 142, 80 ), // #623 + INST(Psubusb , ExtRm_P , O(000F00,D8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9300 , 142, 80 ), // #624 + INST(Psubusw , ExtRm_P , O(000F00,D9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9309 , 142, 80 ), // #625 + INST(Psubw , ExtRm_P , O(000F00,F9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9318 , 142, 80 ), // #626 + INST(Pswapd , Ext3dNow , O(000F0F,BB,_,_,_,_,_,_ ), 0 , 87 , 0 , 2387 , 143, 90 ), // #627 + INST(Ptest , ExtRm , O(660F38,17,_,_,_,_,_,_ ), 0 , 2 , 0 , 9347 , 5 , 97 ), // #628 + INST(Ptwrite , X86M , O(F30F00,AE,4,_,_,_,_,_ ), 0 , 91 , 0 , 2394 , 163, 98 ), // #629 + INST(Punpckhbw , ExtRm_P , O(000F00,68,_,_,_,_,_,_ ), 0 , 4 , 0 , 9430 , 139, 80 ), // #630 + INST(Punpckhdq , ExtRm_P , O(000F00,6A,_,_,_,_,_,_ ), 0 , 4 , 0 , 9441 , 139, 80 ), // #631 + INST(Punpckhqdq , ExtRm , O(660F00,6D,_,_,_,_,_,_ ), 0 , 3 , 0 , 9452 , 5 , 4 ), // #632 + INST(Punpckhwd , ExtRm_P , O(000F00,69,_,_,_,_,_,_ ), 0 , 4 , 0 , 9464 , 139, 80 ), // #633 + INST(Punpcklbw , ExtRm_P , O(000F00,60,_,_,_,_,_,_ ), 0 , 4 , 0 , 9475 , 139, 80 ), // #634 + INST(Punpckldq , ExtRm_P , O(000F00,62,_,_,_,_,_,_ ), 0 , 4 , 0 , 9486 , 139, 80 ), // #635 + INST(Punpcklqdq , ExtRm , O(660F00,6C,_,_,_,_,_,_ ), 0 , 3 , 0 , 9497 , 5 , 4 ), // #636 + INST(Punpcklwd , ExtRm_P , O(000F00,61,_,_,_,_,_,_ ), 0 , 4 , 0 , 9509 , 139, 80 ), // #637 + INST(Push , X86Push , O(000000,FF,6,_,_,_,_,_ ), O(000000,50,_,_,_,_,_,_ ), 31 , 77 , 2402 , 164, 0 ), // #638 + INST(Pusha , X86Op , O(660000,60,_,_,_,_,_,_ ), 0 , 19 , 0 , 2407 , 78 , 0 ), // #639 + INST(Pushad , X86Op , O(000000,60,_,_,_,_,_,_ ), 0 , 0 , 0 , 2413 , 78 , 0 ), // #640 + INST(Pushf , X86Op , O(660000,9C,_,_,_,_,_,_ ), 0 , 19 , 0 , 2420 , 30 , 99 ), // #641 + INST(Pushfd , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2426 , 78 , 99 ), // #642 + INST(Pushfq , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2433 , 159, 99 ), // #643 + INST(Pvalidate , X86Op , O(F20F01,FF,_,_,_,_,_,_ ), 0 , 92 , 0 , 2440 , 30 , 100), // #644 + INST(Pxor , ExtRm_P , O(000F00,EF,_,_,_,_,_,_ ), 0 , 4 , 0 , 9520 , 142, 80 ), // #645 + INST(Rcl , X86Rot , O(000000,D0,2,_,x,_,_,_ ), 0 , 1 , 0 , 2450 , 165, 101), // #646 + INST(Rcpps , ExtRm , O(000F00,53,_,_,_,_,_,_ ), 0 , 4 , 0 , 9648 , 5 , 5 ), // #647 + INST(Rcpss , ExtRm , O(F30F00,53,_,_,_,_,_,_ ), 0 , 6 , 0 , 9655 , 7 , 5 ), // #648 + INST(Rcr , X86Rot , O(000000,D0,3,_,x,_,_,_ ), 0 , 84 , 0 , 2454 , 165, 101), // #649 + INST(Rdfsbase , X86M , O(F30F00,AE,0,_,x,_,_,_ ), 0 , 6 , 0 , 2458 , 166, 102), // #650 + INST(Rdgsbase , X86M , O(F30F00,AE,1,_,x,_,_,_ ), 0 , 93 , 0 , 2467 , 166, 102), // #651 + INST(Rdmsr , X86Op , O(000F00,32,_,_,_,_,_,_ ), 0 , 4 , 0 , 2476 , 167, 103), // #652 + INST(Rdpid , X86R_Native , O(F30F00,C7,7,_,_,_,_,_ ), 0 , 94 , 0 , 2482 , 168, 104), // #653 + INST(Rdpkru , X86Op , O(000F01,EE,_,_,_,_,_,_ ), 0 , 21 , 0 , 2488 , 167, 105), // #654 + INST(Rdpmc , X86Op , O(000F00,33,_,_,_,_,_,_ ), 0 , 4 , 0 , 2495 , 167, 0 ), // #655 + INST(Rdpru , X86Op , O(000F01,FD,_,_,_,_,_,_ ), 0 , 21 , 0 , 2501 , 167, 106), // #656 + INST(Rdrand , X86M , O(000F00,C7,6,_,x,_,_,_ ), 0 , 78 , 0 , 2507 , 23 , 107), // #657 + INST(Rdseed , X86M , O(000F00,C7,7,_,x,_,_,_ ), 0 , 22 , 0 , 2514 , 23 , 108), // #658 + INST(Rdsspd , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 93 , 0 , 2521 , 73 , 54 ), // #659 + INST(Rdsspq , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 93 , 0 , 2528 , 74 , 54 ), // #660 + INST(Rdtsc , X86Op , O(000F00,31,_,_,_,_,_,_ ), 0 , 4 , 0 , 2535 , 28 , 109), // #661 + INST(Rdtscp , X86Op , O(000F01,F9,_,_,_,_,_,_ ), 0 , 21 , 0 , 2541 , 167, 110), // #662 + INST(Ret , X86Ret , O(000000,C2,_,_,_,_,_,_ ), 0 , 0 , 0 , 3044 , 169, 0 ), // #663 + INST(Rmpadjust , X86Op , O(F30F01,FE,_,_,_,_,_,_ ), 0 , 81 , 0 , 2548 , 159, 96 ), // #664 + INST(Rmpupdate , X86Op , O(F20F01,FE,_,_,_,_,_,_ ), 0 , 92 , 0 , 2558 , 159, 96 ), // #665 + INST(Rol , X86Rot , O(000000,D0,0,_,x,_,_,_ ), 0 , 0 , 0 , 2568 , 165, 111), // #666 + INST(Ror , X86Rot , O(000000,D0,1,_,x,_,_,_ ), 0 , 30 , 0 , 2572 , 165, 111), // #667 + INST(Rorx , VexRmi_Wx , V(F20F3A,F0,_,0,x,_,_,_ ), 0 , 95 , 0 , 2576 , 170, 83 ), // #668 + INST(Roundpd , ExtRmi , O(660F3A,09,_,_,_,_,_,_ ), 0 , 8 , 0 , 9750 , 8 , 12 ), // #669 + INST(Roundps , ExtRmi , O(660F3A,08,_,_,_,_,_,_ ), 0 , 8 , 0 , 9759 , 8 , 12 ), // #670 + INST(Roundsd , ExtRmi , O(660F3A,0B,_,_,_,_,_,_ ), 0 , 8 , 0 , 9768 , 36 , 12 ), // #671 + INST(Roundss , ExtRmi , O(660F3A,0A,_,_,_,_,_,_ ), 0 , 8 , 0 , 9777 , 37 , 12 ), // #672 + INST(Rsm , X86Op , O(000F00,AA,_,_,_,_,_,_ ), 0 , 4 , 0 , 2581 , 78 , 1 ), // #673 + INST(Rsqrtps , ExtRm , O(000F00,52,_,_,_,_,_,_ ), 0 , 4 , 0 , 9874 , 5 , 5 ), // #674 + INST(Rsqrtss , ExtRm , O(F30F00,52,_,_,_,_,_,_ ), 0 , 6 , 0 , 9883 , 7 , 5 ), // #675 + INST(Rstorssp , X86M , O(F30F00,01,5,_,_,_,_,_ ), 0 , 62 , 0 , 2585 , 32 , 24 ), // #676 + INST(Sahf , X86Op , O(000000,9E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2594 , 93 , 112), // #677 + INST(Sal , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2599 , 165, 1 ), // #678 + INST(Sar , X86Rot , O(000000,D0,7,_,x,_,_,_ ), 0 , 26 , 0 , 2603 , 165, 1 ), // #679 + INST(Sarx , VexRmv_Wx , V(F30F38,F7,_,0,x,_,_,_ ), 0 , 88 , 0 , 2607 , 13 , 83 ), // #680 + INST(Saveprevssp , X86Op , O(F30F01,EA,_,_,_,_,_,_ ), 0 , 81 , 0 , 2612 , 30 , 24 ), // #681 + INST(Sbb , X86Arith , O(000000,18,3,_,x,_,_,_ ), 0 , 84 , 0 , 2624 , 171, 2 ), // #682 + INST(Scas , X86StrRm , O(000000,AE,_,_,_,_,_,_ ), 0 , 0 , 0 , 2628 , 172, 36 ), // #683 + INST(Serialize , X86Op , O(000F01,E8,_,_,_,_,_,_ ), 0 , 21 , 0 , 2633 , 30 , 113), // #684 + INST(Seta , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2643 , 173, 57 ), // #685 + INST(Setae , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2648 , 173, 58 ), // #686 + INST(Setb , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2654 , 173, 58 ), // #687 + INST(Setbe , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2659 , 173, 57 ), // #688 + INST(Setc , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2665 , 173, 58 ), // #689 + INST(Sete , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2670 , 173, 59 ), // #690 + INST(Setg , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2675 , 173, 60 ), // #691 + INST(Setge , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2680 , 173, 61 ), // #692 + INST(Setl , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2686 , 173, 61 ), // #693 + INST(Setle , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2691 , 173, 60 ), // #694 + INST(Setna , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2697 , 173, 57 ), // #695 + INST(Setnae , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2703 , 173, 58 ), // #696 + INST(Setnb , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2710 , 173, 58 ), // #697 + INST(Setnbe , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2716 , 173, 57 ), // #698 + INST(Setnc , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2723 , 173, 58 ), // #699 + INST(Setne , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2729 , 173, 59 ), // #700 + INST(Setng , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2735 , 173, 60 ), // #701 + INST(Setnge , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2741 , 173, 61 ), // #702 + INST(Setnl , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2748 , 173, 61 ), // #703 + INST(Setnle , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2754 , 173, 60 ), // #704 + INST(Setno , X86Set , O(000F00,91,_,_,_,_,_,_ ), 0 , 4 , 0 , 2761 , 173, 55 ), // #705 + INST(Setnp , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2767 , 173, 62 ), // #706 + INST(Setns , X86Set , O(000F00,99,_,_,_,_,_,_ ), 0 , 4 , 0 , 2773 , 173, 63 ), // #707 + INST(Setnz , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2779 , 173, 59 ), // #708 + INST(Seto , X86Set , O(000F00,90,_,_,_,_,_,_ ), 0 , 4 , 0 , 2785 , 173, 55 ), // #709 + INST(Setp , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2790 , 173, 62 ), // #710 + INST(Setpe , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2795 , 173, 62 ), // #711 + INST(Setpo , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2801 , 173, 62 ), // #712 + INST(Sets , X86Set , O(000F00,98,_,_,_,_,_,_ ), 0 , 4 , 0 , 2807 , 173, 63 ), // #713 + INST(Setssbsy , X86Op , O(F30F01,E8,_,_,_,_,_,_ ), 0 , 81 , 0 , 2812 , 30 , 54 ), // #714 + INST(Setz , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2821 , 173, 59 ), // #715 + INST(Sfence , X86Fence , O(000F00,AE,7,_,_,_,_,_ ), 0 , 22 , 0 , 2826 , 30 , 75 ), // #716 + INST(Sgdt , X86M_Only , O(000F00,01,0,_,_,_,_,_ ), 0 , 4 , 0 , 2833 , 31 , 0 ), // #717 + INST(Sha1msg1 , ExtRm , O(000F38,C9,_,_,_,_,_,_ ), 0 , 82 , 0 , 2838 , 5 , 114), // #718 + INST(Sha1msg2 , ExtRm , O(000F38,CA,_,_,_,_,_,_ ), 0 , 82 , 0 , 2847 , 5 , 114), // #719 + INST(Sha1nexte , ExtRm , O(000F38,C8,_,_,_,_,_,_ ), 0 , 82 , 0 , 2856 , 5 , 114), // #720 + INST(Sha1rnds4 , ExtRmi , O(000F3A,CC,_,_,_,_,_,_ ), 0 , 85 , 0 , 2866 , 8 , 114), // #721 + INST(Sha256msg1 , ExtRm , O(000F38,CC,_,_,_,_,_,_ ), 0 , 82 , 0 , 2876 , 5 , 114), // #722 + INST(Sha256msg2 , ExtRm , O(000F38,CD,_,_,_,_,_,_ ), 0 , 82 , 0 , 2887 , 5 , 114), // #723 + INST(Sha256rnds2 , ExtRm_XMM0 , O(000F38,CB,_,_,_,_,_,_ ), 0 , 82 , 0 , 2898 , 15 , 114), // #724 + INST(Shl , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2910 , 165, 1 ), // #725 + INST(Shld , X86ShldShrd , O(000F00,A4,_,_,x,_,_,_ ), 0 , 4 , 0 , 8919 , 174, 1 ), // #726 + INST(Shlx , VexRmv_Wx , V(660F38,F7,_,0,x,_,_,_ ), 0 , 96 , 0 , 2914 , 13 , 83 ), // #727 + INST(Shr , X86Rot , O(000000,D0,5,_,x,_,_,_ ), 0 , 61 , 0 , 2919 , 165, 1 ), // #728 + INST(Shrd , X86ShldShrd , O(000F00,AC,_,_,x,_,_,_ ), 0 , 4 , 0 , 2923 , 174, 1 ), // #729 + INST(Shrx , VexRmv_Wx , V(F20F38,F7,_,0,x,_,_,_ ), 0 , 83 , 0 , 2928 , 13 , 83 ), // #730 + INST(Shufpd , ExtRmi , O(660F00,C6,_,_,_,_,_,_ ), 0 , 3 , 0 , 10144, 8 , 4 ), // #731 + INST(Shufps , ExtRmi , O(000F00,C6,_,_,_,_,_,_ ), 0 , 4 , 0 , 10152, 8 , 5 ), // #732 + INST(Sidt , X86M_Only , O(000F00,01,1,_,_,_,_,_ ), 0 , 28 , 0 , 2933 , 31 , 0 ), // #733 + INST(Skinit , X86Op_xAX , O(000F01,DE,_,_,_,_,_,_ ), 0 , 21 , 0 , 2938 , 51 , 115), // #734 + INST(Sldt , X86M , O(000F00,00,0,_,_,_,_,_ ), 0 , 4 , 0 , 2945 , 175, 0 ), // #735 + INST(Slwpcb , VexR_Wx , V(XOP_M9,12,1,0,x,_,_,_ ), 0 , 11 , 0 , 2950 , 102, 72 ), // #736 + INST(Smsw , X86M , O(000F00,01,4,_,_,_,_,_ ), 0 , 97 , 0 , 2957 , 175, 0 ), // #737 + INST(Sqrtpd , ExtRm , O(660F00,51,_,_,_,_,_,_ ), 0 , 3 , 0 , 10160, 5 , 4 ), // #738 + INST(Sqrtps , ExtRm , O(000F00,51,_,_,_,_,_,_ ), 0 , 4 , 0 , 9875 , 5 , 5 ), // #739 + INST(Sqrtsd , ExtRm , O(F20F00,51,_,_,_,_,_,_ ), 0 , 5 , 0 , 10176, 6 , 4 ), // #740 + INST(Sqrtss , ExtRm , O(F30F00,51,_,_,_,_,_,_ ), 0 , 6 , 0 , 9884 , 7 , 5 ), // #741 + INST(Stac , X86Op , O(000F01,CB,_,_,_,_,_,_ ), 0 , 21 , 0 , 2962 , 30 , 16 ), // #742 + INST(Stc , X86Op , O(000000,F9,_,_,_,_,_,_ ), 0 , 0 , 0 , 2967 , 30 , 17 ), // #743 + INST(Std , X86Op , O(000000,FD,_,_,_,_,_,_ ), 0 , 0 , 0 , 6902 , 30 , 18 ), // #744 + INST(Stgi , X86Op , O(000F01,DC,_,_,_,_,_,_ ), 0 , 21 , 0 , 2971 , 30 , 115), // #745 + INST(Sti , X86Op , O(000000,FB,_,_,_,_,_,_ ), 0 , 0 , 0 , 2976 , 30 , 23 ), // #746 + INST(Stmxcsr , X86M_Only , O(000F00,AE,3,_,_,_,_,_ ), 0 , 76 , 0 , 10192, 96 , 5 ), // #747 + INST(Stos , X86StrMr , O(000000,AA,_,_,_,_,_,_ ), 0 , 0 , 0 , 2980 , 176, 73 ), // #748 + INST(Str , X86M , O(000F00,00,1,_,_,_,_,_ ), 0 , 28 , 0 , 2985 , 175, 0 ), // #749 + INST(Sttilecfg , AmxCfg , V(660F38,49,_,0,0,_,_,_ ), 0 , 96 , 0 , 2989 , 98 , 71 ), // #750 + INST(Sub , X86Arith , O(000000,28,5,_,x,_,_,_ ), 0 , 61 , 0 , 861 , 171, 1 ), // #751 + INST(Subpd , ExtRm , O(660F00,5C,_,_,_,_,_,_ ), 0 , 3 , 0 , 4844 , 5 , 4 ), // #752 + INST(Subps , ExtRm , O(000F00,5C,_,_,_,_,_,_ ), 0 , 4 , 0 , 4856 , 5 , 5 ), // #753 + INST(Subsd , ExtRm , O(F20F00,5C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5532 , 6 , 4 ), // #754 + INST(Subss , ExtRm , O(F30F00,5C,_,_,_,_,_,_ ), 0 , 6 , 0 , 5542 , 7 , 5 ), // #755 + INST(Swapgs , X86Op , O(000F01,F8,_,_,_,_,_,_ ), 0 , 21 , 0 , 2999 , 159, 0 ), // #756 + INST(Syscall , X86Op , O(000F00,05,_,_,_,_,_,_ ), 0 , 4 , 0 , 3006 , 159, 0 ), // #757 + INST(Sysenter , X86Op , O(000F00,34,_,_,_,_,_,_ ), 0 , 4 , 0 , 3014 , 30 , 0 ), // #758 + INST(Sysexit , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 3023 , 30 , 0 ), // #759 + INST(Sysexit64 , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 3031 , 30 , 0 ), // #760 + INST(Sysret , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 3041 , 159, 0 ), // #761 + INST(Sysret64 , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 3048 , 159, 0 ), // #762 + INST(T1mskc , VexVm_Wx , V(XOP_M9,01,7,0,x,_,_,_ ), 0 , 98 , 0 , 3057 , 14 , 11 ), // #763 + INST(Tdpbf16ps , AmxRmv , V(F30F38,5C,_,0,0,_,_,_ ), 0 , 88 , 0 , 3064 , 177, 116), // #764 + INST(Tdpbssd , AmxRmv , V(F20F38,5E,_,0,0,_,_,_ ), 0 , 83 , 0 , 3074 , 177, 117), // #765 + INST(Tdpbsud , AmxRmv , V(F30F38,5E,_,0,0,_,_,_ ), 0 , 88 , 0 , 3082 , 177, 117), // #766 + INST(Tdpbusd , AmxRmv , V(660F38,5E,_,0,0,_,_,_ ), 0 , 96 , 0 , 3090 , 177, 117), // #767 + INST(Tdpbuud , AmxRmv , V(000F38,5E,_,0,0,_,_,_ ), 0 , 10 , 0 , 3098 , 177, 117), // #768 + INST(Test , X86Test , O(000000,84,_,_,x,_,_,_ ), O(000000,F6,_,_,x,_,_,_ ), 0 , 78 , 9348 , 178, 1 ), // #769 + INST(Tileloadd , AmxRm , V(F20F38,4B,_,0,0,_,_,_ ), 0 , 83 , 0 , 3106 , 179, 71 ), // #770 + INST(Tileloaddt1 , AmxRm , V(660F38,4B,_,0,0,_,_,_ ), 0 , 96 , 0 , 3116 , 179, 71 ), // #771 + INST(Tilerelease , VexOpMod , V(000F38,49,0,0,0,_,_,_ ), 0 , 10 , 0 , 3128 , 180, 71 ), // #772 + INST(Tilestored , AmxMr , V(F30F38,4B,_,0,0,_,_,_ ), 0 , 88 , 0 , 3140 , 181, 71 ), // #773 + INST(Tilezero , AmxR , V(F20F38,49,_,0,0,_,_,_ ), 0 , 83 , 0 , 3151 , 182, 71 ), // #774 + INST(Tpause , X86R32_EDX_EAX , O(660F00,AE,6,_,_,_,_,_ ), 0 , 25 , 0 , 3160 , 183, 118), // #775 + INST(Tzcnt , X86Rm_Raw66H , O(F30F00,BC,_,_,x,_,_,_ ), 0 , 6 , 0 , 3167 , 22 , 9 ), // #776 + INST(Tzmsk , VexVm_Wx , V(XOP_M9,01,4,0,x,_,_,_ ), 0 , 99 , 0 , 3173 , 14 , 11 ), // #777 + INST(Ucomisd , ExtRm , O(660F00,2E,_,_,_,_,_,_ ), 0 , 3 , 0 , 10245, 6 , 40 ), // #778 + INST(Ucomiss , ExtRm , O(000F00,2E,_,_,_,_,_,_ ), 0 , 4 , 0 , 10254, 7 , 41 ), // #779 + INST(Ud0 , X86M , O(000F00,FF,_,_,_,_,_,_ ), 0 , 4 , 0 , 3179 , 184, 0 ), // #780 + INST(Ud1 , X86M , O(000F00,B9,_,_,_,_,_,_ ), 0 , 4 , 0 , 3183 , 184, 0 ), // #781 + INST(Ud2 , X86Op , O(000F00,0B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3187 , 30 , 0 ), // #782 + INST(Umonitor , X86R_FromM , O(F30F00,AE,6,_,_,_,_,_ ), 0 , 24 , 0 , 3191 , 185, 119), // #783 + INST(Umwait , X86R32_EDX_EAX , O(F20F00,AE,6,_,_,_,_,_ ), 0 , 100, 0 , 3200 , 183, 118), // #784 + INST(Unpckhpd , ExtRm , O(660F00,15,_,_,_,_,_,_ ), 0 , 3 , 0 , 10263, 5 , 4 ), // #785 + INST(Unpckhps , ExtRm , O(000F00,15,_,_,_,_,_,_ ), 0 , 4 , 0 , 10273, 5 , 5 ), // #786 + INST(Unpcklpd , ExtRm , O(660F00,14,_,_,_,_,_,_ ), 0 , 3 , 0 , 10283, 5 , 4 ), // #787 + INST(Unpcklps , ExtRm , O(000F00,14,_,_,_,_,_,_ ), 0 , 4 , 0 , 10293, 5 , 5 ), // #788 + INST(V4fmaddps , VexRm_T1_4X , E(F20F38,9A,_,2,_,0,2,T4X), 0 , 101, 0 , 3207 , 186, 120), // #789 + INST(V4fmaddss , VexRm_T1_4X , E(F20F38,9B,_,2,_,0,2,T4X), 0 , 101, 0 , 3217 , 187, 120), // #790 + INST(V4fnmaddps , VexRm_T1_4X , E(F20F38,AA,_,2,_,0,2,T4X), 0 , 101, 0 , 3227 , 186, 120), // #791 + INST(V4fnmaddss , VexRm_T1_4X , E(F20F38,AB,_,2,_,0,2,T4X), 0 , 101, 0 , 3238 , 187, 120), // #792 + INST(Vaddpd , VexRvm_Lx , V(660F00,58,_,x,I,1,4,FV ), 0 , 102, 0 , 3249 , 188, 121), // #793 + INST(Vaddps , VexRvm_Lx , V(000F00,58,_,x,I,0,4,FV ), 0 , 103, 0 , 3256 , 189, 121), // #794 + INST(Vaddsd , VexRvm , V(F20F00,58,_,I,I,1,3,T1S), 0 , 104, 0 , 3263 , 190, 122), // #795 + INST(Vaddss , VexRvm , V(F30F00,58,_,I,I,0,2,T1S), 0 , 105, 0 , 3270 , 191, 122), // #796 + INST(Vaddsubpd , VexRvm_Lx , V(660F00,D0,_,x,I,_,_,_ ), 0 , 68 , 0 , 3277 , 192, 123), // #797 + INST(Vaddsubps , VexRvm_Lx , V(F20F00,D0,_,x,I,_,_,_ ), 0 , 106, 0 , 3287 , 192, 123), // #798 + INST(Vaesdec , VexRvm_Lx , V(660F38,DE,_,x,I,_,4,FVM), 0 , 107, 0 , 3297 , 193, 124), // #799 + INST(Vaesdeclast , VexRvm_Lx , V(660F38,DF,_,x,I,_,4,FVM), 0 , 107, 0 , 3305 , 193, 124), // #800 + INST(Vaesenc , VexRvm_Lx , V(660F38,DC,_,x,I,_,4,FVM), 0 , 107, 0 , 3317 , 193, 124), // #801 + INST(Vaesenclast , VexRvm_Lx , V(660F38,DD,_,x,I,_,4,FVM), 0 , 107, 0 , 3325 , 193, 124), // #802 + INST(Vaesimc , VexRm , V(660F38,DB,_,0,I,_,_,_ ), 0 , 96 , 0 , 3337 , 194, 125), // #803 + INST(Vaeskeygenassist , VexRmi , V(660F3A,DF,_,0,I,_,_,_ ), 0 , 72 , 0 , 3345 , 195, 125), // #804 + INST(Valignd , VexRvmi_Lx , E(660F3A,03,_,x,_,0,4,FV ), 0 , 108, 0 , 3362 , 196, 126), // #805 + INST(Valignq , VexRvmi_Lx , E(660F3A,03,_,x,_,1,4,FV ), 0 , 109, 0 , 3370 , 197, 126), // #806 + INST(Vandnpd , VexRvm_Lx , V(660F00,55,_,x,I,1,4,FV ), 0 , 102, 0 , 3378 , 198, 127), // #807 + INST(Vandnps , VexRvm_Lx , V(000F00,55,_,x,I,0,4,FV ), 0 , 103, 0 , 3386 , 199, 127), // #808 + INST(Vandpd , VexRvm_Lx , V(660F00,54,_,x,I,1,4,FV ), 0 , 102, 0 , 3394 , 200, 127), // #809 + INST(Vandps , VexRvm_Lx , V(000F00,54,_,x,I,0,4,FV ), 0 , 103, 0 , 3401 , 201, 127), // #810 + INST(Vblendmb , VexRvm_Lx , E(660F38,66,_,x,_,0,4,FVM), 0 , 110, 0 , 3408 , 202, 128), // #811 + INST(Vblendmd , VexRvm_Lx , E(660F38,64,_,x,_,0,4,FV ), 0 , 111, 0 , 3417 , 203, 126), // #812 + INST(Vblendmpd , VexRvm_Lx , E(660F38,65,_,x,_,1,4,FV ), 0 , 112, 0 , 3426 , 204, 126), // #813 + INST(Vblendmps , VexRvm_Lx , E(660F38,65,_,x,_,0,4,FV ), 0 , 111, 0 , 3436 , 203, 126), // #814 + INST(Vblendmq , VexRvm_Lx , E(660F38,64,_,x,_,1,4,FV ), 0 , 112, 0 , 3446 , 204, 126), // #815 + INST(Vblendmw , VexRvm_Lx , E(660F38,66,_,x,_,1,4,FVM), 0 , 113, 0 , 3455 , 202, 128), // #816 + INST(Vblendpd , VexRvmi_Lx , V(660F3A,0D,_,x,I,_,_,_ ), 0 , 72 , 0 , 3464 , 205, 123), // #817 + INST(Vblendps , VexRvmi_Lx , V(660F3A,0C,_,x,I,_,_,_ ), 0 , 72 , 0 , 3473 , 205, 123), // #818 + INST(Vblendvpd , VexRvmr_Lx , V(660F3A,4B,_,x,0,_,_,_ ), 0 , 72 , 0 , 3482 , 206, 123), // #819 + INST(Vblendvps , VexRvmr_Lx , V(660F3A,4A,_,x,0,_,_,_ ), 0 , 72 , 0 , 3492 , 206, 123), // #820 + INST(Vbroadcastf128 , VexRm , V(660F38,1A,_,1,0,_,_,_ ), 0 , 114, 0 , 3502 , 207, 123), // #821 + INST(Vbroadcastf32x2 , VexRm_Lx , E(660F38,19,_,x,_,0,3,T2 ), 0 , 115, 0 , 3517 , 208, 129), // #822 + INST(Vbroadcastf32x4 , VexRm_Lx , E(660F38,1A,_,x,_,0,4,T4 ), 0 , 116, 0 , 3533 , 209, 66 ), // #823 + INST(Vbroadcastf32x8 , VexRm , E(660F38,1B,_,2,_,0,5,T8 ), 0 , 117, 0 , 3549 , 210, 64 ), // #824 + INST(Vbroadcastf64x2 , VexRm_Lx , E(660F38,1A,_,x,_,1,4,T2 ), 0 , 118, 0 , 3565 , 209, 129), // #825 + INST(Vbroadcastf64x4 , VexRm , E(660F38,1B,_,2,_,1,5,T4 ), 0 , 119, 0 , 3581 , 210, 66 ), // #826 + INST(Vbroadcasti128 , VexRm , V(660F38,5A,_,1,0,_,_,_ ), 0 , 114, 0 , 3597 , 207, 130), // #827 + INST(Vbroadcasti32x2 , VexRm_Lx , E(660F38,59,_,x,_,0,3,T2 ), 0 , 115, 0 , 3612 , 211, 129), // #828 + INST(Vbroadcasti32x4 , VexRm_Lx , E(660F38,5A,_,x,_,0,4,T4 ), 0 , 116, 0 , 3628 , 209, 126), // #829 + INST(Vbroadcasti32x8 , VexRm , E(660F38,5B,_,2,_,0,5,T8 ), 0 , 117, 0 , 3644 , 210, 64 ), // #830 + INST(Vbroadcasti64x2 , VexRm_Lx , E(660F38,5A,_,x,_,1,4,T2 ), 0 , 118, 0 , 3660 , 209, 129), // #831 + INST(Vbroadcasti64x4 , VexRm , E(660F38,5B,_,2,_,1,5,T4 ), 0 , 119, 0 , 3676 , 210, 66 ), // #832 + INST(Vbroadcastsd , VexRm_Lx , V(660F38,19,_,x,0,1,3,T1S), 0 , 120, 0 , 3692 , 212, 131), // #833 + INST(Vbroadcastss , VexRm_Lx , V(660F38,18,_,x,0,0,2,T1S), 0 , 121, 0 , 3705 , 213, 131), // #834 + INST(Vcmppd , VexRvmi_Lx , V(660F00,C2,_,x,I,1,4,FV ), 0 , 102, 0 , 3718 , 214, 121), // #835 + INST(Vcmpps , VexRvmi_Lx , V(000F00,C2,_,x,I,0,4,FV ), 0 , 103, 0 , 3725 , 215, 121), // #836 + INST(Vcmpsd , VexRvmi , V(F20F00,C2,_,I,I,1,3,T1S), 0 , 104, 0 , 3732 , 216, 122), // #837 + INST(Vcmpss , VexRvmi , V(F30F00,C2,_,I,I,0,2,T1S), 0 , 105, 0 , 3739 , 217, 122), // #838 + INST(Vcomisd , VexRm , V(660F00,2F,_,I,I,1,3,T1S), 0 , 122, 0 , 3746 , 218, 132), // #839 + INST(Vcomiss , VexRm , V(000F00,2F,_,I,I,0,2,T1S), 0 , 123, 0 , 3754 , 219, 132), // #840 + INST(Vcompresspd , VexMr_Lx , E(660F38,8A,_,x,_,1,3,T1S), 0 , 124, 0 , 3762 , 220, 126), // #841 + INST(Vcompressps , VexMr_Lx , E(660F38,8A,_,x,_,0,2,T1S), 0 , 125, 0 , 3774 , 220, 126), // #842 + INST(Vcvtdq2pd , VexRm_Lx , V(F30F00,E6,_,x,I,0,3,HV ), 0 , 126, 0 , 3786 , 221, 121), // #843 + INST(Vcvtdq2ps , VexRm_Lx , V(000F00,5B,_,x,I,0,4,FV ), 0 , 103, 0 , 3796 , 222, 121), // #844 + INST(Vcvtne2ps2bf16 , VexRvm , E(F20F38,72,_,_,_,0,_,_ ), 0 , 127, 0 , 3806 , 203, 133), // #845 + INST(Vcvtneps2bf16 , VexRm , E(F30F38,72,_,_,_,0,_,_ ), 0 , 128, 0 , 3821 , 223, 133), // #846 + INST(Vcvtpd2dq , VexRm_Lx , V(F20F00,E6,_,x,I,1,4,FV ), 0 , 129, 0 , 3835 , 224, 121), // #847 + INST(Vcvtpd2ps , VexRm_Lx , V(660F00,5A,_,x,I,1,4,FV ), 0 , 102, 0 , 3845 , 224, 121), // #848 + INST(Vcvtpd2qq , VexRm_Lx , E(660F00,7B,_,x,_,1,4,FV ), 0 , 130, 0 , 3855 , 225, 129), // #849 + INST(Vcvtpd2udq , VexRm_Lx , E(000F00,79,_,x,_,1,4,FV ), 0 , 131, 0 , 3865 , 226, 126), // #850 + INST(Vcvtpd2uqq , VexRm_Lx , E(660F00,79,_,x,_,1,4,FV ), 0 , 130, 0 , 3876 , 225, 129), // #851 + INST(Vcvtph2ps , VexRm_Lx , V(660F38,13,_,x,0,0,3,HVM), 0 , 132, 0 , 3887 , 227, 134), // #852 + INST(Vcvtps2dq , VexRm_Lx , V(660F00,5B,_,x,I,0,4,FV ), 0 , 133, 0 , 3897 , 222, 121), // #853 + INST(Vcvtps2pd , VexRm_Lx , V(000F00,5A,_,x,I,0,4,HV ), 0 , 134, 0 , 3907 , 228, 121), // #854 + INST(Vcvtps2ph , VexMri_Lx , V(660F3A,1D,_,x,0,0,3,HVM), 0 , 135, 0 , 3917 , 229, 134), // #855 + INST(Vcvtps2qq , VexRm_Lx , E(660F00,7B,_,x,_,0,3,HV ), 0 , 136, 0 , 3927 , 230, 129), // #856 + INST(Vcvtps2udq , VexRm_Lx , E(000F00,79,_,x,_,0,4,FV ), 0 , 137, 0 , 3937 , 231, 126), // #857 + INST(Vcvtps2uqq , VexRm_Lx , E(660F00,79,_,x,_,0,3,HV ), 0 , 136, 0 , 3948 , 230, 129), // #858 + INST(Vcvtqq2pd , VexRm_Lx , E(F30F00,E6,_,x,_,1,4,FV ), 0 , 138, 0 , 3959 , 225, 129), // #859 + INST(Vcvtqq2ps , VexRm_Lx , E(000F00,5B,_,x,_,1,4,FV ), 0 , 131, 0 , 3969 , 226, 129), // #860 + INST(Vcvtsd2si , VexRm_Wx , V(F20F00,2D,_,I,x,x,3,T1F), 0 , 139, 0 , 3979 , 232, 122), // #861 + INST(Vcvtsd2ss , VexRvm , V(F20F00,5A,_,I,I,1,3,T1S), 0 , 104, 0 , 3989 , 190, 122), // #862 + INST(Vcvtsd2usi , VexRm_Wx , E(F20F00,79,_,I,_,x,3,T1F), 0 , 140, 0 , 3999 , 233, 66 ), // #863 + INST(Vcvtsi2sd , VexRvm_Wx , V(F20F00,2A,_,I,x,x,2,T1W), 0 , 141, 0 , 4010 , 234, 122), // #864 + INST(Vcvtsi2ss , VexRvm_Wx , V(F30F00,2A,_,I,x,x,2,T1W), 0 , 142, 0 , 4020 , 234, 122), // #865 + INST(Vcvtss2sd , VexRvm , V(F30F00,5A,_,I,I,0,2,T1S), 0 , 105, 0 , 4030 , 235, 122), // #866 + INST(Vcvtss2si , VexRm_Wx , V(F30F00,2D,_,I,x,x,2,T1F), 0 , 143, 0 , 4040 , 236, 122), // #867 + INST(Vcvtss2usi , VexRm_Wx , E(F30F00,79,_,I,_,x,2,T1F), 0 , 144, 0 , 4050 , 237, 66 ), // #868 + INST(Vcvttpd2dq , VexRm_Lx , V(660F00,E6,_,x,I,1,4,FV ), 0 , 102, 0 , 4061 , 238, 121), // #869 + INST(Vcvttpd2qq , VexRm_Lx , E(660F00,7A,_,x,_,1,4,FV ), 0 , 130, 0 , 4072 , 239, 126), // #870 + INST(Vcvttpd2udq , VexRm_Lx , E(000F00,78,_,x,_,1,4,FV ), 0 , 131, 0 , 4083 , 240, 126), // #871 + INST(Vcvttpd2uqq , VexRm_Lx , E(660F00,78,_,x,_,1,4,FV ), 0 , 130, 0 , 4095 , 239, 129), // #872 + INST(Vcvttps2dq , VexRm_Lx , V(F30F00,5B,_,x,I,0,4,FV ), 0 , 145, 0 , 4107 , 241, 121), // #873 + INST(Vcvttps2qq , VexRm_Lx , E(660F00,7A,_,x,_,0,3,HV ), 0 , 136, 0 , 4118 , 242, 129), // #874 + INST(Vcvttps2udq , VexRm_Lx , E(000F00,78,_,x,_,0,4,FV ), 0 , 137, 0 , 4129 , 243, 126), // #875 + INST(Vcvttps2uqq , VexRm_Lx , E(660F00,78,_,x,_,0,3,HV ), 0 , 136, 0 , 4141 , 242, 129), // #876 + INST(Vcvttsd2si , VexRm_Wx , V(F20F00,2C,_,I,x,x,3,T1F), 0 , 139, 0 , 4153 , 244, 122), // #877 + INST(Vcvttsd2usi , VexRm_Wx , E(F20F00,78,_,I,_,x,3,T1F), 0 , 140, 0 , 4164 , 245, 66 ), // #878 + INST(Vcvttss2si , VexRm_Wx , V(F30F00,2C,_,I,x,x,2,T1F), 0 , 143, 0 , 4176 , 246, 122), // #879 + INST(Vcvttss2usi , VexRm_Wx , E(F30F00,78,_,I,_,x,2,T1F), 0 , 144, 0 , 4187 , 247, 66 ), // #880 + INST(Vcvtudq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,0,3,HV ), 0 , 146, 0 , 4199 , 248, 126), // #881 + INST(Vcvtudq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,0,4,FV ), 0 , 147, 0 , 4210 , 231, 126), // #882 + INST(Vcvtuqq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,1,4,FV ), 0 , 138, 0 , 4221 , 225, 129), // #883 + INST(Vcvtuqq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,1,4,FV ), 0 , 148, 0 , 4232 , 226, 129), // #884 + INST(Vcvtusi2sd , VexRvm_Wx , E(F20F00,7B,_,I,_,x,2,T1W), 0 , 149, 0 , 4243 , 249, 66 ), // #885 + INST(Vcvtusi2ss , VexRvm_Wx , E(F30F00,7B,_,I,_,x,2,T1W), 0 , 150, 0 , 4254 , 249, 66 ), // #886 + INST(Vdbpsadbw , VexRvmi_Lx , E(660F3A,42,_,x,_,0,4,FVM), 0 , 151, 0 , 4265 , 250, 128), // #887 + INST(Vdivpd , VexRvm_Lx , V(660F00,5E,_,x,I,1,4,FV ), 0 , 102, 0 , 4275 , 188, 121), // #888 + INST(Vdivps , VexRvm_Lx , V(000F00,5E,_,x,I,0,4,FV ), 0 , 103, 0 , 4282 , 189, 121), // #889 + INST(Vdivsd , VexRvm , V(F20F00,5E,_,I,I,1,3,T1S), 0 , 104, 0 , 4289 , 190, 122), // #890 + INST(Vdivss , VexRvm , V(F30F00,5E,_,I,I,0,2,T1S), 0 , 105, 0 , 4296 , 191, 122), // #891 + INST(Vdpbf16ps , VexRvm , E(F30F38,52,_,_,_,0,_,_ ), 0 , 128, 0 , 4303 , 203, 133), // #892 + INST(Vdppd , VexRvmi_Lx , V(660F3A,41,_,x,I,_,_,_ ), 0 , 72 , 0 , 4313 , 251, 123), // #893 + INST(Vdpps , VexRvmi_Lx , V(660F3A,40,_,x,I,_,_,_ ), 0 , 72 , 0 , 4319 , 205, 123), // #894 + INST(Verr , X86M_NoSize , O(000F00,00,4,_,_,_,_,_ ), 0 , 97 , 0 , 4325 , 101, 10 ), // #895 + INST(Verw , X86M_NoSize , O(000F00,00,5,_,_,_,_,_ ), 0 , 75 , 0 , 4330 , 101, 10 ), // #896 + INST(Vexp2pd , VexRm , E(660F38,C8,_,2,_,1,4,FV ), 0 , 152, 0 , 4335 , 252, 135), // #897 + INST(Vexp2ps , VexRm , E(660F38,C8,_,2,_,0,4,FV ), 0 , 153, 0 , 4343 , 253, 135), // #898 + INST(Vexpandpd , VexRm_Lx , E(660F38,88,_,x,_,1,3,T1S), 0 , 124, 0 , 4351 , 254, 126), // #899 + INST(Vexpandps , VexRm_Lx , E(660F38,88,_,x,_,0,2,T1S), 0 , 125, 0 , 4361 , 254, 126), // #900 + INST(Vextractf128 , VexMri , V(660F3A,19,_,1,0,_,_,_ ), 0 , 154, 0 , 4371 , 255, 123), // #901 + INST(Vextractf32x4 , VexMri_Lx , E(660F3A,19,_,x,_,0,4,T4 ), 0 , 155, 0 , 4384 , 256, 126), // #902 + INST(Vextractf32x8 , VexMri , E(660F3A,1B,_,2,_,0,5,T8 ), 0 , 156, 0 , 4398 , 257, 64 ), // #903 + INST(Vextractf64x2 , VexMri_Lx , E(660F3A,19,_,x,_,1,4,T2 ), 0 , 157, 0 , 4412 , 256, 129), // #904 + INST(Vextractf64x4 , VexMri , E(660F3A,1B,_,2,_,1,5,T4 ), 0 , 158, 0 , 4426 , 257, 66 ), // #905 + INST(Vextracti128 , VexMri , V(660F3A,39,_,1,0,_,_,_ ), 0 , 154, 0 , 4440 , 255, 130), // #906 + INST(Vextracti32x4 , VexMri_Lx , E(660F3A,39,_,x,_,0,4,T4 ), 0 , 155, 0 , 4453 , 256, 126), // #907 + INST(Vextracti32x8 , VexMri , E(660F3A,3B,_,2,_,0,5,T8 ), 0 , 156, 0 , 4467 , 257, 64 ), // #908 + INST(Vextracti64x2 , VexMri_Lx , E(660F3A,39,_,x,_,1,4,T2 ), 0 , 157, 0 , 4481 , 256, 129), // #909 + INST(Vextracti64x4 , VexMri , E(660F3A,3B,_,2,_,1,5,T4 ), 0 , 158, 0 , 4495 , 257, 66 ), // #910 + INST(Vextractps , VexMri , V(660F3A,17,_,0,I,I,2,T1S), 0 , 159, 0 , 4509 , 258, 122), // #911 + INST(Vfixupimmpd , VexRvmi_Lx , E(660F3A,54,_,x,_,1,4,FV ), 0 , 109, 0 , 4520 , 259, 126), // #912 + INST(Vfixupimmps , VexRvmi_Lx , E(660F3A,54,_,x,_,0,4,FV ), 0 , 108, 0 , 4532 , 260, 126), // #913 + INST(Vfixupimmsd , VexRvmi , E(660F3A,55,_,I,_,1,3,T1S), 0 , 160, 0 , 4544 , 261, 66 ), // #914 + INST(Vfixupimmss , VexRvmi , E(660F3A,55,_,I,_,0,2,T1S), 0 , 161, 0 , 4556 , 262, 66 ), // #915 + INST(Vfmadd132pd , VexRvm_Lx , V(660F38,98,_,x,1,1,4,FV ), 0 , 162, 0 , 4568 , 188, 136), // #916 + INST(Vfmadd132ps , VexRvm_Lx , V(660F38,98,_,x,0,0,4,FV ), 0 , 163, 0 , 4580 , 189, 136), // #917 + INST(Vfmadd132sd , VexRvm , V(660F38,99,_,I,1,1,3,T1S), 0 , 164, 0 , 4592 , 190, 137), // #918 + INST(Vfmadd132ss , VexRvm , V(660F38,99,_,I,0,0,2,T1S), 0 , 121, 0 , 4604 , 191, 137), // #919 + INST(Vfmadd213pd , VexRvm_Lx , V(660F38,A8,_,x,1,1,4,FV ), 0 , 162, 0 , 4616 , 188, 136), // #920 + INST(Vfmadd213ps , VexRvm_Lx , V(660F38,A8,_,x,0,0,4,FV ), 0 , 163, 0 , 4628 , 189, 136), // #921 + INST(Vfmadd213sd , VexRvm , V(660F38,A9,_,I,1,1,3,T1S), 0 , 164, 0 , 4640 , 190, 137), // #922 + INST(Vfmadd213ss , VexRvm , V(660F38,A9,_,I,0,0,2,T1S), 0 , 121, 0 , 4652 , 191, 137), // #923 + INST(Vfmadd231pd , VexRvm_Lx , V(660F38,B8,_,x,1,1,4,FV ), 0 , 162, 0 , 4664 , 188, 136), // #924 + INST(Vfmadd231ps , VexRvm_Lx , V(660F38,B8,_,x,0,0,4,FV ), 0 , 163, 0 , 4676 , 189, 136), // #925 + INST(Vfmadd231sd , VexRvm , V(660F38,B9,_,I,1,1,3,T1S), 0 , 164, 0 , 4688 , 190, 137), // #926 + INST(Vfmadd231ss , VexRvm , V(660F38,B9,_,I,0,0,2,T1S), 0 , 121, 0 , 4700 , 191, 137), // #927 + INST(Vfmaddpd , Fma4_Lx , V(660F3A,69,_,x,x,_,_,_ ), 0 , 72 , 0 , 4712 , 263, 138), // #928 + INST(Vfmaddps , Fma4_Lx , V(660F3A,68,_,x,x,_,_,_ ), 0 , 72 , 0 , 4721 , 263, 138), // #929 + INST(Vfmaddsd , Fma4 , V(660F3A,6B,_,0,x,_,_,_ ), 0 , 72 , 0 , 4730 , 264, 138), // #930 + INST(Vfmaddss , Fma4 , V(660F3A,6A,_,0,x,_,_,_ ), 0 , 72 , 0 , 4739 , 265, 138), // #931 + INST(Vfmaddsub132pd , VexRvm_Lx , V(660F38,96,_,x,1,1,4,FV ), 0 , 162, 0 , 4748 , 188, 136), // #932 + INST(Vfmaddsub132ps , VexRvm_Lx , V(660F38,96,_,x,0,0,4,FV ), 0 , 163, 0 , 4763 , 189, 136), // #933 + INST(Vfmaddsub213pd , VexRvm_Lx , V(660F38,A6,_,x,1,1,4,FV ), 0 , 162, 0 , 4778 , 188, 136), // #934 + INST(Vfmaddsub213ps , VexRvm_Lx , V(660F38,A6,_,x,0,0,4,FV ), 0 , 163, 0 , 4793 , 189, 136), // #935 + INST(Vfmaddsub231pd , VexRvm_Lx , V(660F38,B6,_,x,1,1,4,FV ), 0 , 162, 0 , 4808 , 188, 136), // #936 + INST(Vfmaddsub231ps , VexRvm_Lx , V(660F38,B6,_,x,0,0,4,FV ), 0 , 163, 0 , 4823 , 189, 136), // #937 + INST(Vfmaddsubpd , Fma4_Lx , V(660F3A,5D,_,x,x,_,_,_ ), 0 , 72 , 0 , 4838 , 263, 138), // #938 + INST(Vfmaddsubps , Fma4_Lx , V(660F3A,5C,_,x,x,_,_,_ ), 0 , 72 , 0 , 4850 , 263, 138), // #939 + INST(Vfmsub132pd , VexRvm_Lx , V(660F38,9A,_,x,1,1,4,FV ), 0 , 162, 0 , 4862 , 188, 136), // #940 + INST(Vfmsub132ps , VexRvm_Lx , V(660F38,9A,_,x,0,0,4,FV ), 0 , 163, 0 , 4874 , 189, 136), // #941 + INST(Vfmsub132sd , VexRvm , V(660F38,9B,_,I,1,1,3,T1S), 0 , 164, 0 , 4886 , 190, 137), // #942 + INST(Vfmsub132ss , VexRvm , V(660F38,9B,_,I,0,0,2,T1S), 0 , 121, 0 , 4898 , 191, 137), // #943 + INST(Vfmsub213pd , VexRvm_Lx , V(660F38,AA,_,x,1,1,4,FV ), 0 , 162, 0 , 4910 , 188, 136), // #944 + INST(Vfmsub213ps , VexRvm_Lx , V(660F38,AA,_,x,0,0,4,FV ), 0 , 163, 0 , 4922 , 189, 136), // #945 + INST(Vfmsub213sd , VexRvm , V(660F38,AB,_,I,1,1,3,T1S), 0 , 164, 0 , 4934 , 190, 137), // #946 + INST(Vfmsub213ss , VexRvm , V(660F38,AB,_,I,0,0,2,T1S), 0 , 121, 0 , 4946 , 191, 137), // #947 + INST(Vfmsub231pd , VexRvm_Lx , V(660F38,BA,_,x,1,1,4,FV ), 0 , 162, 0 , 4958 , 188, 136), // #948 + INST(Vfmsub231ps , VexRvm_Lx , V(660F38,BA,_,x,0,0,4,FV ), 0 , 163, 0 , 4970 , 189, 136), // #949 + INST(Vfmsub231sd , VexRvm , V(660F38,BB,_,I,1,1,3,T1S), 0 , 164, 0 , 4982 , 190, 137), // #950 + INST(Vfmsub231ss , VexRvm , V(660F38,BB,_,I,0,0,2,T1S), 0 , 121, 0 , 4994 , 191, 137), // #951 + INST(Vfmsubadd132pd , VexRvm_Lx , V(660F38,97,_,x,1,1,4,FV ), 0 , 162, 0 , 5006 , 188, 136), // #952 + INST(Vfmsubadd132ps , VexRvm_Lx , V(660F38,97,_,x,0,0,4,FV ), 0 , 163, 0 , 5021 , 189, 136), // #953 + INST(Vfmsubadd213pd , VexRvm_Lx , V(660F38,A7,_,x,1,1,4,FV ), 0 , 162, 0 , 5036 , 188, 136), // #954 + INST(Vfmsubadd213ps , VexRvm_Lx , V(660F38,A7,_,x,0,0,4,FV ), 0 , 163, 0 , 5051 , 189, 136), // #955 + INST(Vfmsubadd231pd , VexRvm_Lx , V(660F38,B7,_,x,1,1,4,FV ), 0 , 162, 0 , 5066 , 188, 136), // #956 + INST(Vfmsubadd231ps , VexRvm_Lx , V(660F38,B7,_,x,0,0,4,FV ), 0 , 163, 0 , 5081 , 189, 136), // #957 + INST(Vfmsubaddpd , Fma4_Lx , V(660F3A,5F,_,x,x,_,_,_ ), 0 , 72 , 0 , 5096 , 263, 138), // #958 + INST(Vfmsubaddps , Fma4_Lx , V(660F3A,5E,_,x,x,_,_,_ ), 0 , 72 , 0 , 5108 , 263, 138), // #959 + INST(Vfmsubpd , Fma4_Lx , V(660F3A,6D,_,x,x,_,_,_ ), 0 , 72 , 0 , 5120 , 263, 138), // #960 + INST(Vfmsubps , Fma4_Lx , V(660F3A,6C,_,x,x,_,_,_ ), 0 , 72 , 0 , 5129 , 263, 138), // #961 + INST(Vfmsubsd , Fma4 , V(660F3A,6F,_,0,x,_,_,_ ), 0 , 72 , 0 , 5138 , 264, 138), // #962 + INST(Vfmsubss , Fma4 , V(660F3A,6E,_,0,x,_,_,_ ), 0 , 72 , 0 , 5147 , 265, 138), // #963 + INST(Vfnmadd132pd , VexRvm_Lx , V(660F38,9C,_,x,1,1,4,FV ), 0 , 162, 0 , 5156 , 188, 136), // #964 + INST(Vfnmadd132ps , VexRvm_Lx , V(660F38,9C,_,x,0,0,4,FV ), 0 , 163, 0 , 5169 , 189, 136), // #965 + INST(Vfnmadd132sd , VexRvm , V(660F38,9D,_,I,1,1,3,T1S), 0 , 164, 0 , 5182 , 190, 137), // #966 + INST(Vfnmadd132ss , VexRvm , V(660F38,9D,_,I,0,0,2,T1S), 0 , 121, 0 , 5195 , 191, 137), // #967 + INST(Vfnmadd213pd , VexRvm_Lx , V(660F38,AC,_,x,1,1,4,FV ), 0 , 162, 0 , 5208 , 188, 136), // #968 + INST(Vfnmadd213ps , VexRvm_Lx , V(660F38,AC,_,x,0,0,4,FV ), 0 , 163, 0 , 5221 , 189, 136), // #969 + INST(Vfnmadd213sd , VexRvm , V(660F38,AD,_,I,1,1,3,T1S), 0 , 164, 0 , 5234 , 190, 137), // #970 + INST(Vfnmadd213ss , VexRvm , V(660F38,AD,_,I,0,0,2,T1S), 0 , 121, 0 , 5247 , 191, 137), // #971 + INST(Vfnmadd231pd , VexRvm_Lx , V(660F38,BC,_,x,1,1,4,FV ), 0 , 162, 0 , 5260 , 188, 136), // #972 + INST(Vfnmadd231ps , VexRvm_Lx , V(660F38,BC,_,x,0,0,4,FV ), 0 , 163, 0 , 5273 , 189, 136), // #973 + INST(Vfnmadd231sd , VexRvm , V(660F38,BC,_,I,1,1,3,T1S), 0 , 164, 0 , 5286 , 190, 137), // #974 + INST(Vfnmadd231ss , VexRvm , V(660F38,BC,_,I,0,0,2,T1S), 0 , 121, 0 , 5299 , 191, 137), // #975 + INST(Vfnmaddpd , Fma4_Lx , V(660F3A,79,_,x,x,_,_,_ ), 0 , 72 , 0 , 5312 , 263, 138), // #976 + INST(Vfnmaddps , Fma4_Lx , V(660F3A,78,_,x,x,_,_,_ ), 0 , 72 , 0 , 5322 , 263, 138), // #977 + INST(Vfnmaddsd , Fma4 , V(660F3A,7B,_,0,x,_,_,_ ), 0 , 72 , 0 , 5332 , 264, 138), // #978 + INST(Vfnmaddss , Fma4 , V(660F3A,7A,_,0,x,_,_,_ ), 0 , 72 , 0 , 5342 , 265, 138), // #979 + INST(Vfnmsub132pd , VexRvm_Lx , V(660F38,9E,_,x,1,1,4,FV ), 0 , 162, 0 , 5352 , 188, 136), // #980 + INST(Vfnmsub132ps , VexRvm_Lx , V(660F38,9E,_,x,0,0,4,FV ), 0 , 163, 0 , 5365 , 189, 136), // #981 + INST(Vfnmsub132sd , VexRvm , V(660F38,9F,_,I,1,1,3,T1S), 0 , 164, 0 , 5378 , 190, 137), // #982 + INST(Vfnmsub132ss , VexRvm , V(660F38,9F,_,I,0,0,2,T1S), 0 , 121, 0 , 5391 , 191, 137), // #983 + INST(Vfnmsub213pd , VexRvm_Lx , V(660F38,AE,_,x,1,1,4,FV ), 0 , 162, 0 , 5404 , 188, 136), // #984 + INST(Vfnmsub213ps , VexRvm_Lx , V(660F38,AE,_,x,0,0,4,FV ), 0 , 163, 0 , 5417 , 189, 136), // #985 + INST(Vfnmsub213sd , VexRvm , V(660F38,AF,_,I,1,1,3,T1S), 0 , 164, 0 , 5430 , 190, 137), // #986 + INST(Vfnmsub213ss , VexRvm , V(660F38,AF,_,I,0,0,2,T1S), 0 , 121, 0 , 5443 , 191, 137), // #987 + INST(Vfnmsub231pd , VexRvm_Lx , V(660F38,BE,_,x,1,1,4,FV ), 0 , 162, 0 , 5456 , 188, 136), // #988 + INST(Vfnmsub231ps , VexRvm_Lx , V(660F38,BE,_,x,0,0,4,FV ), 0 , 163, 0 , 5469 , 189, 136), // #989 + INST(Vfnmsub231sd , VexRvm , V(660F38,BF,_,I,1,1,3,T1S), 0 , 164, 0 , 5482 , 190, 137), // #990 + INST(Vfnmsub231ss , VexRvm , V(660F38,BF,_,I,0,0,2,T1S), 0 , 121, 0 , 5495 , 191, 137), // #991 + INST(Vfnmsubpd , Fma4_Lx , V(660F3A,7D,_,x,x,_,_,_ ), 0 , 72 , 0 , 5508 , 263, 138), // #992 + INST(Vfnmsubps , Fma4_Lx , V(660F3A,7C,_,x,x,_,_,_ ), 0 , 72 , 0 , 5518 , 263, 138), // #993 + INST(Vfnmsubsd , Fma4 , V(660F3A,7F,_,0,x,_,_,_ ), 0 , 72 , 0 , 5528 , 264, 138), // #994 + INST(Vfnmsubss , Fma4 , V(660F3A,7E,_,0,x,_,_,_ ), 0 , 72 , 0 , 5538 , 265, 138), // #995 + INST(Vfpclasspd , VexRmi_Lx , E(660F3A,66,_,x,_,1,4,FV ), 0 , 109, 0 , 5548 , 266, 129), // #996 + INST(Vfpclassps , VexRmi_Lx , E(660F3A,66,_,x,_,0,4,FV ), 0 , 108, 0 , 5559 , 267, 129), // #997 + INST(Vfpclasssd , VexRmi_Lx , E(660F3A,67,_,I,_,1,3,T1S), 0 , 160, 0 , 5570 , 268, 64 ), // #998 + INST(Vfpclassss , VexRmi_Lx , E(660F3A,67,_,I,_,0,2,T1S), 0 , 161, 0 , 5581 , 269, 64 ), // #999 + INST(Vfrczpd , VexRm_Lx , V(XOP_M9,81,_,x,0,_,_,_ ), 0 , 77 , 0 , 5592 , 270, 139), // #1000 + INST(Vfrczps , VexRm_Lx , V(XOP_M9,80,_,x,0,_,_,_ ), 0 , 77 , 0 , 5600 , 270, 139), // #1001 + INST(Vfrczsd , VexRm , V(XOP_M9,83,_,0,0,_,_,_ ), 0 , 77 , 0 , 5608 , 271, 139), // #1002 + INST(Vfrczss , VexRm , V(XOP_M9,82,_,0,0,_,_,_ ), 0 , 77 , 0 , 5616 , 272, 139), // #1003 + INST(Vgatherdpd , VexRmvRm_VM , V(660F38,92,_,x,1,_,_,_ ), V(660F38,92,_,x,_,1,3,T1S), 165, 79 , 5624 , 273, 140), // #1004 + INST(Vgatherdps , VexRmvRm_VM , V(660F38,92,_,x,0,_,_,_ ), V(660F38,92,_,x,_,0,2,T1S), 96 , 80 , 5635 , 274, 140), // #1005 + INST(Vgatherpf0dpd , VexM_VM , E(660F38,C6,1,2,_,1,3,T1S), 0 , 166, 0 , 5646 , 275, 141), // #1006 + INST(Vgatherpf0dps , VexM_VM , E(660F38,C6,1,2,_,0,2,T1S), 0 , 167, 0 , 5660 , 276, 141), // #1007 + INST(Vgatherpf0qpd , VexM_VM , E(660F38,C7,1,2,_,1,3,T1S), 0 , 166, 0 , 5674 , 277, 141), // #1008 + INST(Vgatherpf0qps , VexM_VM , E(660F38,C7,1,2,_,0,2,T1S), 0 , 167, 0 , 5688 , 277, 141), // #1009 + INST(Vgatherpf1dpd , VexM_VM , E(660F38,C6,2,2,_,1,3,T1S), 0 , 168, 0 , 5702 , 275, 141), // #1010 + INST(Vgatherpf1dps , VexM_VM , E(660F38,C6,2,2,_,0,2,T1S), 0 , 169, 0 , 5716 , 276, 141), // #1011 + INST(Vgatherpf1qpd , VexM_VM , E(660F38,C7,2,2,_,1,3,T1S), 0 , 168, 0 , 5730 , 277, 141), // #1012 + INST(Vgatherpf1qps , VexM_VM , E(660F38,C7,2,2,_,0,2,T1S), 0 , 169, 0 , 5744 , 277, 141), // #1013 + INST(Vgatherqpd , VexRmvRm_VM , V(660F38,93,_,x,1,_,_,_ ), V(660F38,93,_,x,_,1,3,T1S), 165, 81 , 5758 , 278, 140), // #1014 + INST(Vgatherqps , VexRmvRm_VM , V(660F38,93,_,x,0,_,_,_ ), V(660F38,93,_,x,_,0,2,T1S), 96 , 82 , 5769 , 279, 140), // #1015 + INST(Vgetexppd , VexRm_Lx , E(660F38,42,_,x,_,1,4,FV ), 0 , 112, 0 , 5780 , 239, 126), // #1016 + INST(Vgetexpps , VexRm_Lx , E(660F38,42,_,x,_,0,4,FV ), 0 , 111, 0 , 5790 , 243, 126), // #1017 + INST(Vgetexpsd , VexRvm , E(660F38,43,_,I,_,1,3,T1S), 0 , 124, 0 , 5800 , 280, 66 ), // #1018 + INST(Vgetexpss , VexRvm , E(660F38,43,_,I,_,0,2,T1S), 0 , 125, 0 , 5810 , 281, 66 ), // #1019 + INST(Vgetmantpd , VexRmi_Lx , E(660F3A,26,_,x,_,1,4,FV ), 0 , 109, 0 , 5820 , 282, 126), // #1020 + INST(Vgetmantps , VexRmi_Lx , E(660F3A,26,_,x,_,0,4,FV ), 0 , 108, 0 , 5831 , 283, 126), // #1021 + INST(Vgetmantsd , VexRvmi , E(660F3A,27,_,I,_,1,3,T1S), 0 , 160, 0 , 5842 , 261, 66 ), // #1022 + INST(Vgetmantss , VexRvmi , E(660F3A,27,_,I,_,0,2,T1S), 0 , 161, 0 , 5853 , 262, 66 ), // #1023 + INST(Vgf2p8affineinvqb, VexRvmi_Lx , V(660F3A,CF,_,x,1,1,4,FV ), 0 , 170, 0 , 5864 , 284, 142), // #1024 + INST(Vgf2p8affineqb , VexRvmi_Lx , V(660F3A,CE,_,x,1,1,4,FV ), 0 , 170, 0 , 5882 , 284, 142), // #1025 + INST(Vgf2p8mulb , VexRvm_Lx , V(660F38,CF,_,x,0,0,4,FV ), 0 , 163, 0 , 5897 , 285, 142), // #1026 + INST(Vhaddpd , VexRvm_Lx , V(660F00,7C,_,x,I,_,_,_ ), 0 , 68 , 0 , 5908 , 192, 123), // #1027 + INST(Vhaddps , VexRvm_Lx , V(F20F00,7C,_,x,I,_,_,_ ), 0 , 106, 0 , 5916 , 192, 123), // #1028 + INST(Vhsubpd , VexRvm_Lx , V(660F00,7D,_,x,I,_,_,_ ), 0 , 68 , 0 , 5924 , 192, 123), // #1029 + INST(Vhsubps , VexRvm_Lx , V(F20F00,7D,_,x,I,_,_,_ ), 0 , 106, 0 , 5932 , 192, 123), // #1030 + INST(Vinsertf128 , VexRvmi , V(660F3A,18,_,1,0,_,_,_ ), 0 , 154, 0 , 5940 , 286, 123), // #1031 + INST(Vinsertf32x4 , VexRvmi_Lx , E(660F3A,18,_,x,_,0,4,T4 ), 0 , 155, 0 , 5952 , 287, 126), // #1032 + INST(Vinsertf32x8 , VexRvmi , E(660F3A,1A,_,2,_,0,5,T8 ), 0 , 156, 0 , 5965 , 288, 64 ), // #1033 + INST(Vinsertf64x2 , VexRvmi_Lx , E(660F3A,18,_,x,_,1,4,T2 ), 0 , 157, 0 , 5978 , 287, 129), // #1034 + INST(Vinsertf64x4 , VexRvmi , E(660F3A,1A,_,2,_,1,5,T4 ), 0 , 158, 0 , 5991 , 288, 66 ), // #1035 + INST(Vinserti128 , VexRvmi , V(660F3A,38,_,1,0,_,_,_ ), 0 , 154, 0 , 6004 , 286, 130), // #1036 + INST(Vinserti32x4 , VexRvmi_Lx , E(660F3A,38,_,x,_,0,4,T4 ), 0 , 155, 0 , 6016 , 287, 126), // #1037 + INST(Vinserti32x8 , VexRvmi , E(660F3A,3A,_,2,_,0,5,T8 ), 0 , 156, 0 , 6029 , 288, 64 ), // #1038 + INST(Vinserti64x2 , VexRvmi_Lx , E(660F3A,38,_,x,_,1,4,T2 ), 0 , 157, 0 , 6042 , 287, 129), // #1039 + INST(Vinserti64x4 , VexRvmi , E(660F3A,3A,_,2,_,1,5,T4 ), 0 , 158, 0 , 6055 , 288, 66 ), // #1040 + INST(Vinsertps , VexRvmi , V(660F3A,21,_,0,I,0,2,T1S), 0 , 159, 0 , 6068 , 289, 122), // #1041 + INST(Vlddqu , VexRm_Lx , V(F20F00,F0,_,x,I,_,_,_ ), 0 , 106, 0 , 6078 , 290, 123), // #1042 + INST(Vldmxcsr , VexM , V(000F00,AE,2,0,I,_,_,_ ), 0 , 171, 0 , 6085 , 291, 123), // #1043 + INST(Vmaskmovdqu , VexRm_ZDI , V(660F00,F7,_,0,I,_,_,_ ), 0 , 68 , 0 , 6094 , 292, 123), // #1044 + INST(Vmaskmovpd , VexRvmMvr_Lx , V(660F38,2D,_,x,0,_,_,_ ), V(660F38,2F,_,x,0,_,_,_ ), 96 , 83 , 6106 , 293, 123), // #1045 + INST(Vmaskmovps , VexRvmMvr_Lx , V(660F38,2C,_,x,0,_,_,_ ), V(660F38,2E,_,x,0,_,_,_ ), 96 , 84 , 6117 , 293, 123), // #1046 + INST(Vmaxpd , VexRvm_Lx , V(660F00,5F,_,x,I,1,4,FV ), 0 , 102, 0 , 6128 , 294, 121), // #1047 + INST(Vmaxps , VexRvm_Lx , V(000F00,5F,_,x,I,0,4,FV ), 0 , 103, 0 , 6135 , 295, 121), // #1048 + INST(Vmaxsd , VexRvm , V(F20F00,5F,_,I,I,1,3,T1S), 0 , 104, 0 , 6142 , 296, 121), // #1049 + INST(Vmaxss , VexRvm , V(F30F00,5F,_,I,I,0,2,T1S), 0 , 105, 0 , 6149 , 235, 121), // #1050 + INST(Vmcall , X86Op , O(000F01,C1,_,_,_,_,_,_ ), 0 , 21 , 0 , 6156 , 30 , 56 ), // #1051 + INST(Vmclear , X86M_Only , O(660F00,C7,6,_,_,_,_,_ ), 0 , 25 , 0 , 6163 , 32 , 56 ), // #1052 + INST(Vmfunc , X86Op , O(000F01,D4,_,_,_,_,_,_ ), 0 , 21 , 0 , 6171 , 30 , 56 ), // #1053 + INST(Vminpd , VexRvm_Lx , V(660F00,5D,_,x,I,1,4,FV ), 0 , 102, 0 , 6178 , 294, 121), // #1054 + INST(Vminps , VexRvm_Lx , V(000F00,5D,_,x,I,0,4,FV ), 0 , 103, 0 , 6185 , 295, 121), // #1055 + INST(Vminsd , VexRvm , V(F20F00,5D,_,I,I,1,3,T1S), 0 , 104, 0 , 6192 , 296, 121), // #1056 + INST(Vminss , VexRvm , V(F30F00,5D,_,I,I,0,2,T1S), 0 , 105, 0 , 6199 , 235, 121), // #1057 + INST(Vmlaunch , X86Op , O(000F01,C2,_,_,_,_,_,_ ), 0 , 21 , 0 , 6206 , 30 , 56 ), // #1058 + INST(Vmload , X86Op_xAX , O(000F01,DA,_,_,_,_,_,_ ), 0 , 21 , 0 , 6215 , 297, 22 ), // #1059 + INST(Vmmcall , X86Op , O(000F01,D9,_,_,_,_,_,_ ), 0 , 21 , 0 , 6222 , 30 , 22 ), // #1060 + INST(Vmovapd , VexRmMr_Lx , V(660F00,28,_,x,I,1,4,FVM), V(660F00,29,_,x,I,1,4,FVM), 172, 85 , 6230 , 298, 121), // #1061 + INST(Vmovaps , VexRmMr_Lx , V(000F00,28,_,x,I,0,4,FVM), V(000F00,29,_,x,I,0,4,FVM), 173, 86 , 6238 , 298, 121), // #1062 + INST(Vmovd , VexMovdMovq , V(660F00,6E,_,0,0,0,2,T1S), V(660F00,7E,_,0,0,0,2,T1S), 174, 87 , 6246 , 299, 122), // #1063 + INST(Vmovddup , VexRm_Lx , V(F20F00,12,_,x,I,1,3,DUP), 0 , 175, 0 , 6252 , 300, 121), // #1064 + INST(Vmovdqa , VexRmMr_Lx , V(660F00,6F,_,x,I,_,_,_ ), V(660F00,7F,_,x,I,_,_,_ ), 68 , 88 , 6261 , 301, 123), // #1065 + INST(Vmovdqa32 , VexRmMr_Lx , E(660F00,6F,_,x,_,0,4,FVM), E(660F00,7F,_,x,_,0,4,FVM), 176, 89 , 6269 , 302, 126), // #1066 + INST(Vmovdqa64 , VexRmMr_Lx , E(660F00,6F,_,x,_,1,4,FVM), E(660F00,7F,_,x,_,1,4,FVM), 177, 90 , 6279 , 302, 126), // #1067 + INST(Vmovdqu , VexRmMr_Lx , V(F30F00,6F,_,x,I,_,_,_ ), V(F30F00,7F,_,x,I,_,_,_ ), 178, 91 , 6289 , 301, 123), // #1068 + INST(Vmovdqu16 , VexRmMr_Lx , E(F20F00,6F,_,x,_,1,4,FVM), E(F20F00,7F,_,x,_,1,4,FVM), 179, 92 , 6297 , 302, 128), // #1069 + INST(Vmovdqu32 , VexRmMr_Lx , E(F30F00,6F,_,x,_,0,4,FVM), E(F30F00,7F,_,x,_,0,4,FVM), 180, 93 , 6307 , 302, 126), // #1070 + INST(Vmovdqu64 , VexRmMr_Lx , E(F30F00,6F,_,x,_,1,4,FVM), E(F30F00,7F,_,x,_,1,4,FVM), 181, 94 , 6317 , 302, 126), // #1071 + INST(Vmovdqu8 , VexRmMr_Lx , E(F20F00,6F,_,x,_,0,4,FVM), E(F20F00,7F,_,x,_,0,4,FVM), 182, 95 , 6327 , 302, 128), // #1072 + INST(Vmovhlps , VexRvm , V(000F00,12,_,0,I,0,_,_ ), 0 , 71 , 0 , 6336 , 303, 122), // #1073 + INST(Vmovhpd , VexRvmMr , V(660F00,16,_,0,I,1,3,T1S), V(660F00,17,_,0,I,1,3,T1S), 122, 96 , 6345 , 304, 122), // #1074 + INST(Vmovhps , VexRvmMr , V(000F00,16,_,0,I,0,3,T2 ), V(000F00,17,_,0,I,0,3,T2 ), 183, 97 , 6353 , 304, 122), // #1075 + INST(Vmovlhps , VexRvm , V(000F00,16,_,0,I,0,_,_ ), 0 , 71 , 0 , 6361 , 303, 122), // #1076 + INST(Vmovlpd , VexRvmMr , V(660F00,12,_,0,I,1,3,T1S), V(660F00,13,_,0,I,1,3,T1S), 122, 98 , 6370 , 304, 122), // #1077 + INST(Vmovlps , VexRvmMr , V(000F00,12,_,0,I,0,3,T2 ), V(000F00,13,_,0,I,0,3,T2 ), 183, 99 , 6378 , 304, 122), // #1078 + INST(Vmovmskpd , VexRm_Lx , V(660F00,50,_,x,I,_,_,_ ), 0 , 68 , 0 , 6386 , 305, 123), // #1079 + INST(Vmovmskps , VexRm_Lx , V(000F00,50,_,x,I,_,_,_ ), 0 , 71 , 0 , 6396 , 305, 123), // #1080 + INST(Vmovntdq , VexMr_Lx , V(660F00,E7,_,x,I,0,4,FVM), 0 , 184, 0 , 6406 , 306, 121), // #1081 + INST(Vmovntdqa , VexRm_Lx , V(660F38,2A,_,x,I,0,4,FVM), 0 , 107, 0 , 6415 , 307, 131), // #1082 + INST(Vmovntpd , VexMr_Lx , V(660F00,2B,_,x,I,1,4,FVM), 0 , 172, 0 , 6425 , 306, 121), // #1083 + INST(Vmovntps , VexMr_Lx , V(000F00,2B,_,x,I,0,4,FVM), 0 , 173, 0 , 6434 , 306, 121), // #1084 + INST(Vmovq , VexMovdMovq , V(660F00,6E,_,0,I,1,3,T1S), V(660F00,7E,_,0,I,1,3,T1S), 122, 100, 6443 , 308, 122), // #1085 + INST(Vmovsd , VexMovssMovsd , V(F20F00,10,_,I,I,1,3,T1S), V(F20F00,11,_,I,I,1,3,T1S), 104, 101, 6449 , 309, 122), // #1086 + INST(Vmovshdup , VexRm_Lx , V(F30F00,16,_,x,I,0,4,FVM), 0 , 185, 0 , 6456 , 310, 121), // #1087 + INST(Vmovsldup , VexRm_Lx , V(F30F00,12,_,x,I,0,4,FVM), 0 , 185, 0 , 6466 , 310, 121), // #1088 + INST(Vmovss , VexMovssMovsd , V(F30F00,10,_,I,I,0,2,T1S), V(F30F00,11,_,I,I,0,2,T1S), 105, 102, 6476 , 311, 122), // #1089 + INST(Vmovupd , VexRmMr_Lx , V(660F00,10,_,x,I,1,4,FVM), V(660F00,11,_,x,I,1,4,FVM), 172, 103, 6483 , 298, 121), // #1090 + INST(Vmovups , VexRmMr_Lx , V(000F00,10,_,x,I,0,4,FVM), V(000F00,11,_,x,I,0,4,FVM), 173, 104, 6491 , 298, 121), // #1091 + INST(Vmpsadbw , VexRvmi_Lx , V(660F3A,42,_,x,I,_,_,_ ), 0 , 72 , 0 , 6499 , 205, 143), // #1092 + INST(Vmptrld , X86M_Only , O(000F00,C7,6,_,_,_,_,_ ), 0 , 78 , 0 , 6508 , 32 , 56 ), // #1093 + INST(Vmptrst , X86M_Only , O(000F00,C7,7,_,_,_,_,_ ), 0 , 22 , 0 , 6516 , 32 , 56 ), // #1094 + INST(Vmread , X86Mr_NoSize , O(000F00,78,_,_,_,_,_,_ ), 0 , 4 , 0 , 6524 , 312, 56 ), // #1095 + INST(Vmresume , X86Op , O(000F01,C3,_,_,_,_,_,_ ), 0 , 21 , 0 , 6531 , 30 , 56 ), // #1096 + INST(Vmrun , X86Op_xAX , O(000F01,D8,_,_,_,_,_,_ ), 0 , 21 , 0 , 6540 , 297, 22 ), // #1097 + INST(Vmsave , X86Op_xAX , O(000F01,DB,_,_,_,_,_,_ ), 0 , 21 , 0 , 6546 , 297, 22 ), // #1098 + INST(Vmulpd , VexRvm_Lx , V(660F00,59,_,x,I,1,4,FV ), 0 , 102, 0 , 6553 , 188, 121), // #1099 + INST(Vmulps , VexRvm_Lx , V(000F00,59,_,x,I,0,4,FV ), 0 , 103, 0 , 6560 , 189, 121), // #1100 + INST(Vmulsd , VexRvm_Lx , V(F20F00,59,_,I,I,1,3,T1S), 0 , 104, 0 , 6567 , 190, 122), // #1101 + INST(Vmulss , VexRvm_Lx , V(F30F00,59,_,I,I,0,2,T1S), 0 , 105, 0 , 6574 , 191, 122), // #1102 + INST(Vmwrite , X86Rm_NoSize , O(000F00,79,_,_,_,_,_,_ ), 0 , 4 , 0 , 6581 , 313, 56 ), // #1103 + INST(Vmxon , X86M_Only , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 24 , 0 , 6589 , 32 , 56 ), // #1104 + INST(Vorpd , VexRvm_Lx , V(660F00,56,_,x,I,1,4,FV ), 0 , 102, 0 , 6595 , 200, 127), // #1105 + INST(Vorps , VexRvm_Lx , V(000F00,56,_,x,I,0,4,FV ), 0 , 103, 0 , 6601 , 201, 127), // #1106 + INST(Vp2intersectd , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,0,4,FV ), 0 , 186, 0 , 6607 , 314, 144), // #1107 + INST(Vp2intersectq , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,1,4,FV ), 0 , 187, 0 , 6621 , 315, 144), // #1108 + INST(Vp4dpwssd , VexRm_T1_4X , E(F20F38,52,_,2,_,0,2,T4X), 0 , 101, 0 , 6635 , 186, 145), // #1109 + INST(Vp4dpwssds , VexRm_T1_4X , E(F20F38,53,_,2,_,0,2,T4X), 0 , 101, 0 , 6645 , 186, 145), // #1110 + INST(Vpabsb , VexRm_Lx , V(660F38,1C,_,x,I,_,4,FVM), 0 , 107, 0 , 6656 , 310, 146), // #1111 + INST(Vpabsd , VexRm_Lx , V(660F38,1E,_,x,I,0,4,FV ), 0 , 163, 0 , 6663 , 310, 131), // #1112 + INST(Vpabsq , VexRm_Lx , E(660F38,1F,_,x,_,1,4,FV ), 0 , 112, 0 , 6670 , 254, 126), // #1113 + INST(Vpabsw , VexRm_Lx , V(660F38,1D,_,x,I,_,4,FVM), 0 , 107, 0 , 6677 , 310, 146), // #1114 + INST(Vpackssdw , VexRvm_Lx , V(660F00,6B,_,x,I,0,4,FV ), 0 , 133, 0 , 6684 , 199, 146), // #1115 + INST(Vpacksswb , VexRvm_Lx , V(660F00,63,_,x,I,I,4,FVM), 0 , 184, 0 , 6694 , 285, 146), // #1116 + INST(Vpackusdw , VexRvm_Lx , V(660F38,2B,_,x,I,0,4,FV ), 0 , 163, 0 , 6704 , 199, 146), // #1117 + INST(Vpackuswb , VexRvm_Lx , V(660F00,67,_,x,I,I,4,FVM), 0 , 184, 0 , 6714 , 285, 146), // #1118 + INST(Vpaddb , VexRvm_Lx , V(660F00,FC,_,x,I,I,4,FVM), 0 , 184, 0 , 6724 , 285, 146), // #1119 + INST(Vpaddd , VexRvm_Lx , V(660F00,FE,_,x,I,0,4,FV ), 0 , 133, 0 , 6731 , 199, 131), // #1120 + INST(Vpaddq , VexRvm_Lx , V(660F00,D4,_,x,I,1,4,FV ), 0 , 102, 0 , 6738 , 198, 131), // #1121 + INST(Vpaddsb , VexRvm_Lx , V(660F00,EC,_,x,I,I,4,FVM), 0 , 184, 0 , 6745 , 285, 146), // #1122 + INST(Vpaddsw , VexRvm_Lx , V(660F00,ED,_,x,I,I,4,FVM), 0 , 184, 0 , 6753 , 285, 146), // #1123 + INST(Vpaddusb , VexRvm_Lx , V(660F00,DC,_,x,I,I,4,FVM), 0 , 184, 0 , 6761 , 285, 146), // #1124 + INST(Vpaddusw , VexRvm_Lx , V(660F00,DD,_,x,I,I,4,FVM), 0 , 184, 0 , 6770 , 285, 146), // #1125 + INST(Vpaddw , VexRvm_Lx , V(660F00,FD,_,x,I,I,4,FVM), 0 , 184, 0 , 6779 , 285, 146), // #1126 + INST(Vpalignr , VexRvmi_Lx , V(660F3A,0F,_,x,I,I,4,FVM), 0 , 188, 0 , 6786 , 284, 146), // #1127 + INST(Vpand , VexRvm_Lx , V(660F00,DB,_,x,I,_,_,_ ), 0 , 68 , 0 , 6795 , 316, 143), // #1128 + INST(Vpandd , VexRvm_Lx , E(660F00,DB,_,x,_,0,4,FV ), 0 , 189, 0 , 6801 , 317, 126), // #1129 + INST(Vpandn , VexRvm_Lx , V(660F00,DF,_,x,I,_,_,_ ), 0 , 68 , 0 , 6808 , 318, 143), // #1130 + INST(Vpandnd , VexRvm_Lx , E(660F00,DF,_,x,_,0,4,FV ), 0 , 189, 0 , 6815 , 319, 126), // #1131 + INST(Vpandnq , VexRvm_Lx , E(660F00,DF,_,x,_,1,4,FV ), 0 , 130, 0 , 6823 , 320, 126), // #1132 + INST(Vpandq , VexRvm_Lx , E(660F00,DB,_,x,_,1,4,FV ), 0 , 130, 0 , 6831 , 321, 126), // #1133 + INST(Vpavgb , VexRvm_Lx , V(660F00,E0,_,x,I,I,4,FVM), 0 , 184, 0 , 6838 , 285, 146), // #1134 + INST(Vpavgw , VexRvm_Lx , V(660F00,E3,_,x,I,I,4,FVM), 0 , 184, 0 , 6845 , 285, 146), // #1135 + INST(Vpblendd , VexRvmi_Lx , V(660F3A,02,_,x,0,_,_,_ ), 0 , 72 , 0 , 6852 , 205, 130), // #1136 + INST(Vpblendvb , VexRvmr , V(660F3A,4C,_,x,0,_,_,_ ), 0 , 72 , 0 , 6861 , 206, 143), // #1137 + INST(Vpblendw , VexRvmi_Lx , V(660F3A,0E,_,x,I,_,_,_ ), 0 , 72 , 0 , 6871 , 205, 143), // #1138 + INST(Vpbroadcastb , VexRm_Lx_Bcst , V(660F38,78,_,x,0,0,0,T1S), E(660F38,7A,_,x,0,0,0,T1S), 190, 105, 6880 , 322, 147), // #1139 + INST(Vpbroadcastd , VexRm_Lx_Bcst , V(660F38,58,_,x,0,0,2,T1S), E(660F38,7C,_,x,0,0,0,T1S), 121, 106, 6893 , 323, 140), // #1140 + INST(Vpbroadcastmb2d , VexRm_Lx , E(F30F38,3A,_,x,_,0,_,_ ), 0 , 128, 0 , 6906 , 324, 148), // #1141 + INST(Vpbroadcastmb2q , VexRm_Lx , E(F30F38,2A,_,x,_,1,_,_ ), 0 , 191, 0 , 6922 , 324, 148), // #1142 + INST(Vpbroadcastq , VexRm_Lx_Bcst , V(660F38,59,_,x,0,1,3,T1S), E(660F38,7C,_,x,0,1,0,T1S), 120, 107, 6938 , 325, 140), // #1143 + INST(Vpbroadcastw , VexRm_Lx_Bcst , V(660F38,79,_,x,0,0,1,T1S), E(660F38,7B,_,x,0,0,0,T1S), 192, 108, 6951 , 326, 147), // #1144 + INST(Vpclmulqdq , VexRvmi_Lx , V(660F3A,44,_,x,I,_,4,FVM), 0 , 188, 0 , 6964 , 327, 149), // #1145 + INST(Vpcmov , VexRvrmRvmr_Lx , V(XOP_M8,A2,_,x,x,_,_,_ ), 0 , 193, 0 , 6975 , 263, 139), // #1146 + INST(Vpcmpb , VexRvmi_Lx , E(660F3A,3F,_,x,_,0,4,FVM), 0 , 151, 0 , 6982 , 328, 128), // #1147 + INST(Vpcmpd , VexRvmi_Lx , E(660F3A,1F,_,x,_,0,4,FV ), 0 , 108, 0 , 6989 , 329, 126), // #1148 + INST(Vpcmpeqb , VexRvm_Lx , V(660F00,74,_,x,I,I,4,FV ), 0 , 133, 0 , 6996 , 330, 146), // #1149 + INST(Vpcmpeqd , VexRvm_Lx , V(660F00,76,_,x,I,0,4,FVM), 0 , 184, 0 , 7005 , 331, 131), // #1150 + INST(Vpcmpeqq , VexRvm_Lx , V(660F38,29,_,x,I,1,4,FVM), 0 , 194, 0 , 7014 , 332, 131), // #1151 + INST(Vpcmpeqw , VexRvm_Lx , V(660F00,75,_,x,I,I,4,FV ), 0 , 133, 0 , 7023 , 330, 146), // #1152 + INST(Vpcmpestri , VexRmi , V(660F3A,61,_,0,I,_,_,_ ), 0 , 72 , 0 , 7032 , 333, 150), // #1153 + INST(Vpcmpestrm , VexRmi , V(660F3A,60,_,0,I,_,_,_ ), 0 , 72 , 0 , 7043 , 334, 150), // #1154 + INST(Vpcmpgtb , VexRvm_Lx , V(660F00,64,_,x,I,I,4,FV ), 0 , 133, 0 , 7054 , 330, 146), // #1155 + INST(Vpcmpgtd , VexRvm_Lx , V(660F00,66,_,x,I,0,4,FVM), 0 , 184, 0 , 7063 , 331, 131), // #1156 + INST(Vpcmpgtq , VexRvm_Lx , V(660F38,37,_,x,I,1,4,FVM), 0 , 194, 0 , 7072 , 332, 131), // #1157 + INST(Vpcmpgtw , VexRvm_Lx , V(660F00,65,_,x,I,I,4,FV ), 0 , 133, 0 , 7081 , 330, 146), // #1158 + INST(Vpcmpistri , VexRmi , V(660F3A,63,_,0,I,_,_,_ ), 0 , 72 , 0 , 7090 , 335, 150), // #1159 + INST(Vpcmpistrm , VexRmi , V(660F3A,62,_,0,I,_,_,_ ), 0 , 72 , 0 , 7101 , 336, 150), // #1160 + INST(Vpcmpq , VexRvmi_Lx , E(660F3A,1F,_,x,_,1,4,FV ), 0 , 109, 0 , 7112 , 337, 126), // #1161 + INST(Vpcmpub , VexRvmi_Lx , E(660F3A,3E,_,x,_,0,4,FVM), 0 , 151, 0 , 7119 , 328, 128), // #1162 + INST(Vpcmpud , VexRvmi_Lx , E(660F3A,1E,_,x,_,0,4,FV ), 0 , 108, 0 , 7127 , 329, 126), // #1163 + INST(Vpcmpuq , VexRvmi_Lx , E(660F3A,1E,_,x,_,1,4,FV ), 0 , 109, 0 , 7135 , 337, 126), // #1164 + INST(Vpcmpuw , VexRvmi_Lx , E(660F3A,3E,_,x,_,1,4,FVM), 0 , 195, 0 , 7143 , 337, 128), // #1165 + INST(Vpcmpw , VexRvmi_Lx , E(660F3A,3F,_,x,_,1,4,FVM), 0 , 195, 0 , 7151 , 337, 128), // #1166 + INST(Vpcomb , VexRvmi , V(XOP_M8,CC,_,0,0,_,_,_ ), 0 , 193, 0 , 7158 , 251, 139), // #1167 + INST(Vpcomd , VexRvmi , V(XOP_M8,CE,_,0,0,_,_,_ ), 0 , 193, 0 , 7165 , 251, 139), // #1168 + INST(Vpcompressb , VexMr_Lx , E(660F38,63,_,x,_,0,0,T1S), 0 , 196, 0 , 7172 , 220, 151), // #1169 + INST(Vpcompressd , VexMr_Lx , E(660F38,8B,_,x,_,0,2,T1S), 0 , 125, 0 , 7184 , 220, 126), // #1170 + INST(Vpcompressq , VexMr_Lx , E(660F38,8B,_,x,_,1,3,T1S), 0 , 124, 0 , 7196 , 220, 126), // #1171 + INST(Vpcompressw , VexMr_Lx , E(660F38,63,_,x,_,1,1,T1S), 0 , 197, 0 , 7208 , 220, 151), // #1172 + INST(Vpcomq , VexRvmi , V(XOP_M8,CF,_,0,0,_,_,_ ), 0 , 193, 0 , 7220 , 251, 139), // #1173 + INST(Vpcomub , VexRvmi , V(XOP_M8,EC,_,0,0,_,_,_ ), 0 , 193, 0 , 7227 , 251, 139), // #1174 + INST(Vpcomud , VexRvmi , V(XOP_M8,EE,_,0,0,_,_,_ ), 0 , 193, 0 , 7235 , 251, 139), // #1175 + INST(Vpcomuq , VexRvmi , V(XOP_M8,EF,_,0,0,_,_,_ ), 0 , 193, 0 , 7243 , 251, 139), // #1176 + INST(Vpcomuw , VexRvmi , V(XOP_M8,ED,_,0,0,_,_,_ ), 0 , 193, 0 , 7251 , 251, 139), // #1177 + INST(Vpcomw , VexRvmi , V(XOP_M8,CD,_,0,0,_,_,_ ), 0 , 193, 0 , 7259 , 251, 139), // #1178 + INST(Vpconflictd , VexRm_Lx , E(660F38,C4,_,x,_,0,4,FV ), 0 , 111, 0 , 7266 , 338, 148), // #1179 + INST(Vpconflictq , VexRm_Lx , E(660F38,C4,_,x,_,1,4,FV ), 0 , 112, 0 , 7278 , 338, 148), // #1180 + INST(Vpdpbusd , VexRvm_Lx , E(660F38,50,_,x,_,0,4,FV ), 0 , 111, 0 , 7290 , 203, 152), // #1181 + INST(Vpdpbusds , VexRvm_Lx , E(660F38,51,_,x,_,0,4,FV ), 0 , 111, 0 , 7299 , 203, 152), // #1182 + INST(Vpdpwssd , VexRvm_Lx , E(660F38,52,_,x,_,0,4,FV ), 0 , 111, 0 , 7309 , 203, 152), // #1183 + INST(Vpdpwssds , VexRvm_Lx , E(660F38,53,_,x,_,0,4,FV ), 0 , 111, 0 , 7318 , 203, 152), // #1184 + INST(Vperm2f128 , VexRvmi , V(660F3A,06,_,1,0,_,_,_ ), 0 , 154, 0 , 7328 , 339, 123), // #1185 + INST(Vperm2i128 , VexRvmi , V(660F3A,46,_,1,0,_,_,_ ), 0 , 154, 0 , 7339 , 339, 130), // #1186 + INST(Vpermb , VexRvm_Lx , E(660F38,8D,_,x,_,0,4,FVM), 0 , 110, 0 , 7350 , 202, 153), // #1187 + INST(Vpermd , VexRvm_Lx , V(660F38,36,_,x,0,0,4,FV ), 0 , 163, 0 , 7357 , 340, 140), // #1188 + INST(Vpermi2b , VexRvm_Lx , E(660F38,75,_,x,_,0,4,FVM), 0 , 110, 0 , 7364 , 202, 153), // #1189 + INST(Vpermi2d , VexRvm_Lx , E(660F38,76,_,x,_,0,4,FV ), 0 , 111, 0 , 7373 , 203, 126), // #1190 + INST(Vpermi2pd , VexRvm_Lx , E(660F38,77,_,x,_,1,4,FV ), 0 , 112, 0 , 7382 , 204, 126), // #1191 + INST(Vpermi2ps , VexRvm_Lx , E(660F38,77,_,x,_,0,4,FV ), 0 , 111, 0 , 7392 , 203, 126), // #1192 + INST(Vpermi2q , VexRvm_Lx , E(660F38,76,_,x,_,1,4,FV ), 0 , 112, 0 , 7402 , 204, 126), // #1193 + INST(Vpermi2w , VexRvm_Lx , E(660F38,75,_,x,_,1,4,FVM), 0 , 113, 0 , 7411 , 202, 128), // #1194 + INST(Vpermil2pd , VexRvrmiRvmri_Lx , V(660F3A,49,_,x,x,_,_,_ ), 0 , 72 , 0 , 7420 , 341, 139), // #1195 + INST(Vpermil2ps , VexRvrmiRvmri_Lx , V(660F3A,48,_,x,x,_,_,_ ), 0 , 72 , 0 , 7431 , 341, 139), // #1196 + INST(Vpermilpd , VexRvmRmi_Lx , V(660F38,0D,_,x,0,1,4,FV ), V(660F3A,05,_,x,0,1,4,FV ), 198, 109, 7442 , 342, 121), // #1197 + INST(Vpermilps , VexRvmRmi_Lx , V(660F38,0C,_,x,0,0,4,FV ), V(660F3A,04,_,x,0,0,4,FV ), 163, 110, 7452 , 342, 121), // #1198 + INST(Vpermpd , VexRvmRmi_Lx , E(660F38,16,_,x,1,1,4,FV ), V(660F3A,01,_,x,1,1,4,FV ), 199, 111, 7462 , 343, 140), // #1199 + INST(Vpermps , VexRvm_Lx , V(660F38,16,_,x,0,0,4,FV ), 0 , 163, 0 , 7470 , 340, 140), // #1200 + INST(Vpermq , VexRvmRmi_Lx , V(660F38,36,_,x,_,1,4,FV ), V(660F3A,00,_,x,1,1,4,FV ), 198, 112, 7478 , 343, 140), // #1201 + INST(Vpermt2b , VexRvm_Lx , E(660F38,7D,_,x,_,0,4,FVM), 0 , 110, 0 , 7485 , 202, 153), // #1202 + INST(Vpermt2d , VexRvm_Lx , E(660F38,7E,_,x,_,0,4,FV ), 0 , 111, 0 , 7494 , 203, 126), // #1203 + INST(Vpermt2pd , VexRvm_Lx , E(660F38,7F,_,x,_,1,4,FV ), 0 , 112, 0 , 7503 , 204, 126), // #1204 + INST(Vpermt2ps , VexRvm_Lx , E(660F38,7F,_,x,_,0,4,FV ), 0 , 111, 0 , 7513 , 203, 126), // #1205 + INST(Vpermt2q , VexRvm_Lx , E(660F38,7E,_,x,_,1,4,FV ), 0 , 112, 0 , 7523 , 204, 126), // #1206 + INST(Vpermt2w , VexRvm_Lx , E(660F38,7D,_,x,_,1,4,FVM), 0 , 113, 0 , 7532 , 202, 128), // #1207 + INST(Vpermw , VexRvm_Lx , E(660F38,8D,_,x,_,1,4,FVM), 0 , 113, 0 , 7541 , 202, 128), // #1208 + INST(Vpexpandb , VexRm_Lx , E(660F38,62,_,x,_,0,0,T1S), 0 , 196, 0 , 7548 , 254, 151), // #1209 + INST(Vpexpandd , VexRm_Lx , E(660F38,89,_,x,_,0,2,T1S), 0 , 125, 0 , 7558 , 254, 126), // #1210 + INST(Vpexpandq , VexRm_Lx , E(660F38,89,_,x,_,1,3,T1S), 0 , 124, 0 , 7568 , 254, 126), // #1211 + INST(Vpexpandw , VexRm_Lx , E(660F38,62,_,x,_,1,1,T1S), 0 , 197, 0 , 7578 , 254, 151), // #1212 + INST(Vpextrb , VexMri , V(660F3A,14,_,0,0,I,0,T1S), 0 , 200, 0 , 7588 , 344, 154), // #1213 + INST(Vpextrd , VexMri , V(660F3A,16,_,0,0,0,2,T1S), 0 , 159, 0 , 7596 , 258, 155), // #1214 + INST(Vpextrq , VexMri , V(660F3A,16,_,0,1,1,3,T1S), 0 , 201, 0 , 7604 , 345, 155), // #1215 + INST(Vpextrw , VexMri , V(660F3A,15,_,0,0,I,1,T1S), 0 , 202, 0 , 7612 , 346, 154), // #1216 + INST(Vpgatherdd , VexRmvRm_VM , V(660F38,90,_,x,0,_,_,_ ), V(660F38,90,_,x,_,0,2,T1S), 96 , 113, 7620 , 274, 140), // #1217 + INST(Vpgatherdq , VexRmvRm_VM , V(660F38,90,_,x,1,_,_,_ ), V(660F38,90,_,x,_,1,3,T1S), 165, 114, 7631 , 273, 140), // #1218 + INST(Vpgatherqd , VexRmvRm_VM , V(660F38,91,_,x,0,_,_,_ ), V(660F38,91,_,x,_,0,2,T1S), 96 , 115, 7642 , 279, 140), // #1219 + INST(Vpgatherqq , VexRmvRm_VM , V(660F38,91,_,x,1,_,_,_ ), V(660F38,91,_,x,_,1,3,T1S), 165, 116, 7653 , 278, 140), // #1220 + INST(Vphaddbd , VexRm , V(XOP_M9,C2,_,0,0,_,_,_ ), 0 , 77 , 0 , 7664 , 194, 139), // #1221 + INST(Vphaddbq , VexRm , V(XOP_M9,C3,_,0,0,_,_,_ ), 0 , 77 , 0 , 7673 , 194, 139), // #1222 + INST(Vphaddbw , VexRm , V(XOP_M9,C1,_,0,0,_,_,_ ), 0 , 77 , 0 , 7682 , 194, 139), // #1223 + INST(Vphaddd , VexRvm_Lx , V(660F38,02,_,x,I,_,_,_ ), 0 , 96 , 0 , 7691 , 192, 143), // #1224 + INST(Vphadddq , VexRm , V(XOP_M9,CB,_,0,0,_,_,_ ), 0 , 77 , 0 , 7699 , 194, 139), // #1225 + INST(Vphaddsw , VexRvm_Lx , V(660F38,03,_,x,I,_,_,_ ), 0 , 96 , 0 , 7708 , 192, 143), // #1226 + INST(Vphaddubd , VexRm , V(XOP_M9,D2,_,0,0,_,_,_ ), 0 , 77 , 0 , 7717 , 194, 139), // #1227 + INST(Vphaddubq , VexRm , V(XOP_M9,D3,_,0,0,_,_,_ ), 0 , 77 , 0 , 7727 , 194, 139), // #1228 + INST(Vphaddubw , VexRm , V(XOP_M9,D1,_,0,0,_,_,_ ), 0 , 77 , 0 , 7737 , 194, 139), // #1229 + INST(Vphaddudq , VexRm , V(XOP_M9,DB,_,0,0,_,_,_ ), 0 , 77 , 0 , 7747 , 194, 139), // #1230 + INST(Vphadduwd , VexRm , V(XOP_M9,D6,_,0,0,_,_,_ ), 0 , 77 , 0 , 7757 , 194, 139), // #1231 + INST(Vphadduwq , VexRm , V(XOP_M9,D7,_,0,0,_,_,_ ), 0 , 77 , 0 , 7767 , 194, 139), // #1232 + INST(Vphaddw , VexRvm_Lx , V(660F38,01,_,x,I,_,_,_ ), 0 , 96 , 0 , 7777 , 192, 143), // #1233 + INST(Vphaddwd , VexRm , V(XOP_M9,C6,_,0,0,_,_,_ ), 0 , 77 , 0 , 7785 , 194, 139), // #1234 + INST(Vphaddwq , VexRm , V(XOP_M9,C7,_,0,0,_,_,_ ), 0 , 77 , 0 , 7794 , 194, 139), // #1235 + INST(Vphminposuw , VexRm , V(660F38,41,_,0,I,_,_,_ ), 0 , 96 , 0 , 7803 , 194, 123), // #1236 + INST(Vphsubbw , VexRm , V(XOP_M9,E1,_,0,0,_,_,_ ), 0 , 77 , 0 , 7815 , 194, 139), // #1237 + INST(Vphsubd , VexRvm_Lx , V(660F38,06,_,x,I,_,_,_ ), 0 , 96 , 0 , 7824 , 192, 143), // #1238 + INST(Vphsubdq , VexRm , V(XOP_M9,E3,_,0,0,_,_,_ ), 0 , 77 , 0 , 7832 , 194, 139), // #1239 + INST(Vphsubsw , VexRvm_Lx , V(660F38,07,_,x,I,_,_,_ ), 0 , 96 , 0 , 7841 , 192, 143), // #1240 + INST(Vphsubw , VexRvm_Lx , V(660F38,05,_,x,I,_,_,_ ), 0 , 96 , 0 , 7850 , 192, 143), // #1241 + INST(Vphsubwd , VexRm , V(XOP_M9,E2,_,0,0,_,_,_ ), 0 , 77 , 0 , 7858 , 194, 139), // #1242 + INST(Vpinsrb , VexRvmi , V(660F3A,20,_,0,0,I,0,T1S), 0 , 200, 0 , 7867 , 347, 154), // #1243 + INST(Vpinsrd , VexRvmi , V(660F3A,22,_,0,0,0,2,T1S), 0 , 159, 0 , 7875 , 348, 155), // #1244 + INST(Vpinsrq , VexRvmi , V(660F3A,22,_,0,1,1,3,T1S), 0 , 201, 0 , 7883 , 349, 155), // #1245 + INST(Vpinsrw , VexRvmi , V(660F00,C4,_,0,0,I,1,T1S), 0 , 203, 0 , 7891 , 350, 154), // #1246 + INST(Vplzcntd , VexRm_Lx , E(660F38,44,_,x,_,0,4,FV ), 0 , 111, 0 , 7899 , 338, 148), // #1247 + INST(Vplzcntq , VexRm_Lx , E(660F38,44,_,x,_,1,4,FV ), 0 , 112, 0 , 7908 , 351, 148), // #1248 + INST(Vpmacsdd , VexRvmr , V(XOP_M8,9E,_,0,0,_,_,_ ), 0 , 193, 0 , 7917 , 352, 139), // #1249 + INST(Vpmacsdqh , VexRvmr , V(XOP_M8,9F,_,0,0,_,_,_ ), 0 , 193, 0 , 7926 , 352, 139), // #1250 + INST(Vpmacsdql , VexRvmr , V(XOP_M8,97,_,0,0,_,_,_ ), 0 , 193, 0 , 7936 , 352, 139), // #1251 + INST(Vpmacssdd , VexRvmr , V(XOP_M8,8E,_,0,0,_,_,_ ), 0 , 193, 0 , 7946 , 352, 139), // #1252 + INST(Vpmacssdqh , VexRvmr , V(XOP_M8,8F,_,0,0,_,_,_ ), 0 , 193, 0 , 7956 , 352, 139), // #1253 + INST(Vpmacssdql , VexRvmr , V(XOP_M8,87,_,0,0,_,_,_ ), 0 , 193, 0 , 7967 , 352, 139), // #1254 + INST(Vpmacsswd , VexRvmr , V(XOP_M8,86,_,0,0,_,_,_ ), 0 , 193, 0 , 7978 , 352, 139), // #1255 + INST(Vpmacssww , VexRvmr , V(XOP_M8,85,_,0,0,_,_,_ ), 0 , 193, 0 , 7988 , 352, 139), // #1256 + INST(Vpmacswd , VexRvmr , V(XOP_M8,96,_,0,0,_,_,_ ), 0 , 193, 0 , 7998 , 352, 139), // #1257 + INST(Vpmacsww , VexRvmr , V(XOP_M8,95,_,0,0,_,_,_ ), 0 , 193, 0 , 8007 , 352, 139), // #1258 + INST(Vpmadcsswd , VexRvmr , V(XOP_M8,A6,_,0,0,_,_,_ ), 0 , 193, 0 , 8016 , 352, 139), // #1259 + INST(Vpmadcswd , VexRvmr , V(XOP_M8,B6,_,0,0,_,_,_ ), 0 , 193, 0 , 8027 , 352, 139), // #1260 + INST(Vpmadd52huq , VexRvm_Lx , E(660F38,B5,_,x,_,1,4,FV ), 0 , 112, 0 , 8037 , 204, 156), // #1261 + INST(Vpmadd52luq , VexRvm_Lx , E(660F38,B4,_,x,_,1,4,FV ), 0 , 112, 0 , 8049 , 204, 156), // #1262 + INST(Vpmaddubsw , VexRvm_Lx , V(660F38,04,_,x,I,I,4,FVM), 0 , 107, 0 , 8061 , 285, 146), // #1263 + INST(Vpmaddwd , VexRvm_Lx , V(660F00,F5,_,x,I,I,4,FVM), 0 , 184, 0 , 8072 , 285, 146), // #1264 + INST(Vpmaskmovd , VexRvmMvr_Lx , V(660F38,8C,_,x,0,_,_,_ ), V(660F38,8E,_,x,0,_,_,_ ), 96 , 117, 8081 , 293, 130), // #1265 + INST(Vpmaskmovq , VexRvmMvr_Lx , V(660F38,8C,_,x,1,_,_,_ ), V(660F38,8E,_,x,1,_,_,_ ), 165, 118, 8092 , 293, 130), // #1266 + INST(Vpmaxsb , VexRvm_Lx , V(660F38,3C,_,x,I,I,4,FVM), 0 , 107, 0 , 8103 , 353, 146), // #1267 + INST(Vpmaxsd , VexRvm_Lx , V(660F38,3D,_,x,I,0,4,FV ), 0 , 163, 0 , 8111 , 201, 131), // #1268 + INST(Vpmaxsq , VexRvm_Lx , E(660F38,3D,_,x,_,1,4,FV ), 0 , 112, 0 , 8119 , 204, 126), // #1269 + INST(Vpmaxsw , VexRvm_Lx , V(660F00,EE,_,x,I,I,4,FVM), 0 , 184, 0 , 8127 , 353, 146), // #1270 + INST(Vpmaxub , VexRvm_Lx , V(660F00,DE,_,x,I,I,4,FVM), 0 , 184, 0 , 8135 , 353, 146), // #1271 + INST(Vpmaxud , VexRvm_Lx , V(660F38,3F,_,x,I,0,4,FV ), 0 , 163, 0 , 8143 , 201, 131), // #1272 + INST(Vpmaxuq , VexRvm_Lx , E(660F38,3F,_,x,_,1,4,FV ), 0 , 112, 0 , 8151 , 204, 126), // #1273 + INST(Vpmaxuw , VexRvm_Lx , V(660F38,3E,_,x,I,I,4,FVM), 0 , 107, 0 , 8159 , 353, 146), // #1274 + INST(Vpminsb , VexRvm_Lx , V(660F38,38,_,x,I,I,4,FVM), 0 , 107, 0 , 8167 , 353, 146), // #1275 + INST(Vpminsd , VexRvm_Lx , V(660F38,39,_,x,I,0,4,FV ), 0 , 163, 0 , 8175 , 201, 131), // #1276 + INST(Vpminsq , VexRvm_Lx , E(660F38,39,_,x,_,1,4,FV ), 0 , 112, 0 , 8183 , 204, 126), // #1277 + INST(Vpminsw , VexRvm_Lx , V(660F00,EA,_,x,I,I,4,FVM), 0 , 184, 0 , 8191 , 353, 146), // #1278 + INST(Vpminub , VexRvm_Lx , V(660F00,DA,_,x,I,_,4,FVM), 0 , 184, 0 , 8199 , 353, 146), // #1279 + INST(Vpminud , VexRvm_Lx , V(660F38,3B,_,x,I,0,4,FV ), 0 , 163, 0 , 8207 , 201, 131), // #1280 + INST(Vpminuq , VexRvm_Lx , E(660F38,3B,_,x,_,1,4,FV ), 0 , 112, 0 , 8215 , 204, 126), // #1281 + INST(Vpminuw , VexRvm_Lx , V(660F38,3A,_,x,I,_,4,FVM), 0 , 107, 0 , 8223 , 353, 146), // #1282 + INST(Vpmovb2m , VexRm_Lx , E(F30F38,29,_,x,_,0,_,_ ), 0 , 128, 0 , 8231 , 354, 128), // #1283 + INST(Vpmovd2m , VexRm_Lx , E(F30F38,39,_,x,_,0,_,_ ), 0 , 128, 0 , 8240 , 354, 129), // #1284 + INST(Vpmovdb , VexMr_Lx , E(F30F38,31,_,x,_,0,2,QVM), 0 , 204, 0 , 8249 , 355, 126), // #1285 + INST(Vpmovdw , VexMr_Lx , E(F30F38,33,_,x,_,0,3,HVM), 0 , 205, 0 , 8257 , 356, 126), // #1286 + INST(Vpmovm2b , VexRm_Lx , E(F30F38,28,_,x,_,0,_,_ ), 0 , 128, 0 , 8265 , 324, 128), // #1287 + INST(Vpmovm2d , VexRm_Lx , E(F30F38,38,_,x,_,0,_,_ ), 0 , 128, 0 , 8274 , 324, 129), // #1288 + INST(Vpmovm2q , VexRm_Lx , E(F30F38,38,_,x,_,1,_,_ ), 0 , 191, 0 , 8283 , 324, 129), // #1289 + INST(Vpmovm2w , VexRm_Lx , E(F30F38,28,_,x,_,1,_,_ ), 0 , 191, 0 , 8292 , 324, 128), // #1290 + INST(Vpmovmskb , VexRm_Lx , V(660F00,D7,_,x,I,_,_,_ ), 0 , 68 , 0 , 8301 , 305, 143), // #1291 + INST(Vpmovq2m , VexRm_Lx , E(F30F38,39,_,x,_,1,_,_ ), 0 , 191, 0 , 8311 , 354, 129), // #1292 + INST(Vpmovqb , VexMr_Lx , E(F30F38,32,_,x,_,0,1,OVM), 0 , 206, 0 , 8320 , 357, 126), // #1293 + INST(Vpmovqd , VexMr_Lx , E(F30F38,35,_,x,_,0,3,HVM), 0 , 205, 0 , 8328 , 356, 126), // #1294 + INST(Vpmovqw , VexMr_Lx , E(F30F38,34,_,x,_,0,2,QVM), 0 , 204, 0 , 8336 , 355, 126), // #1295 + INST(Vpmovsdb , VexMr_Lx , E(F30F38,21,_,x,_,0,2,QVM), 0 , 204, 0 , 8344 , 355, 126), // #1296 + INST(Vpmovsdw , VexMr_Lx , E(F30F38,23,_,x,_,0,3,HVM), 0 , 205, 0 , 8353 , 356, 126), // #1297 + INST(Vpmovsqb , VexMr_Lx , E(F30F38,22,_,x,_,0,1,OVM), 0 , 206, 0 , 8362 , 357, 126), // #1298 + INST(Vpmovsqd , VexMr_Lx , E(F30F38,25,_,x,_,0,3,HVM), 0 , 205, 0 , 8371 , 356, 126), // #1299 + INST(Vpmovsqw , VexMr_Lx , E(F30F38,24,_,x,_,0,2,QVM), 0 , 204, 0 , 8380 , 355, 126), // #1300 + INST(Vpmovswb , VexMr_Lx , E(F30F38,20,_,x,_,0,3,HVM), 0 , 205, 0 , 8389 , 356, 128), // #1301 + INST(Vpmovsxbd , VexRm_Lx , V(660F38,21,_,x,I,I,2,QVM), 0 , 207, 0 , 8398 , 358, 131), // #1302 + INST(Vpmovsxbq , VexRm_Lx , V(660F38,22,_,x,I,I,1,OVM), 0 , 208, 0 , 8408 , 359, 131), // #1303 + INST(Vpmovsxbw , VexRm_Lx , V(660F38,20,_,x,I,I,3,HVM), 0 , 132, 0 , 8418 , 360, 146), // #1304 + INST(Vpmovsxdq , VexRm_Lx , V(660F38,25,_,x,I,0,3,HVM), 0 , 132, 0 , 8428 , 360, 131), // #1305 + INST(Vpmovsxwd , VexRm_Lx , V(660F38,23,_,x,I,I,3,HVM), 0 , 132, 0 , 8438 , 360, 131), // #1306 + INST(Vpmovsxwq , VexRm_Lx , V(660F38,24,_,x,I,I,2,QVM), 0 , 207, 0 , 8448 , 358, 131), // #1307 + INST(Vpmovusdb , VexMr_Lx , E(F30F38,11,_,x,_,0,2,QVM), 0 , 204, 0 , 8458 , 355, 126), // #1308 + INST(Vpmovusdw , VexMr_Lx , E(F30F38,13,_,x,_,0,3,HVM), 0 , 205, 0 , 8468 , 356, 126), // #1309 + INST(Vpmovusqb , VexMr_Lx , E(F30F38,12,_,x,_,0,1,OVM), 0 , 206, 0 , 8478 , 357, 126), // #1310 + INST(Vpmovusqd , VexMr_Lx , E(F30F38,15,_,x,_,0,3,HVM), 0 , 205, 0 , 8488 , 356, 126), // #1311 + INST(Vpmovusqw , VexMr_Lx , E(F30F38,14,_,x,_,0,2,QVM), 0 , 204, 0 , 8498 , 355, 126), // #1312 + INST(Vpmovuswb , VexMr_Lx , E(F30F38,10,_,x,_,0,3,HVM), 0 , 205, 0 , 8508 , 356, 128), // #1313 + INST(Vpmovw2m , VexRm_Lx , E(F30F38,29,_,x,_,1,_,_ ), 0 , 191, 0 , 8518 , 354, 128), // #1314 + INST(Vpmovwb , VexMr_Lx , E(F30F38,30,_,x,_,0,3,HVM), 0 , 205, 0 , 8527 , 356, 128), // #1315 + INST(Vpmovzxbd , VexRm_Lx , V(660F38,31,_,x,I,I,2,QVM), 0 , 207, 0 , 8535 , 358, 131), // #1316 + INST(Vpmovzxbq , VexRm_Lx , V(660F38,32,_,x,I,I,1,OVM), 0 , 208, 0 , 8545 , 359, 131), // #1317 + INST(Vpmovzxbw , VexRm_Lx , V(660F38,30,_,x,I,I,3,HVM), 0 , 132, 0 , 8555 , 360, 146), // #1318 + INST(Vpmovzxdq , VexRm_Lx , V(660F38,35,_,x,I,0,3,HVM), 0 , 132, 0 , 8565 , 360, 131), // #1319 + INST(Vpmovzxwd , VexRm_Lx , V(660F38,33,_,x,I,I,3,HVM), 0 , 132, 0 , 8575 , 360, 131), // #1320 + INST(Vpmovzxwq , VexRm_Lx , V(660F38,34,_,x,I,I,2,QVM), 0 , 207, 0 , 8585 , 358, 131), // #1321 + INST(Vpmuldq , VexRvm_Lx , V(660F38,28,_,x,I,1,4,FV ), 0 , 198, 0 , 8595 , 198, 131), // #1322 + INST(Vpmulhrsw , VexRvm_Lx , V(660F38,0B,_,x,I,I,4,FVM), 0 , 107, 0 , 8603 , 285, 146), // #1323 + INST(Vpmulhuw , VexRvm_Lx , V(660F00,E4,_,x,I,I,4,FVM), 0 , 184, 0 , 8613 , 285, 146), // #1324 + INST(Vpmulhw , VexRvm_Lx , V(660F00,E5,_,x,I,I,4,FVM), 0 , 184, 0 , 8622 , 285, 146), // #1325 + INST(Vpmulld , VexRvm_Lx , V(660F38,40,_,x,I,0,4,FV ), 0 , 163, 0 , 8630 , 199, 131), // #1326 + INST(Vpmullq , VexRvm_Lx , E(660F38,40,_,x,_,1,4,FV ), 0 , 112, 0 , 8638 , 204, 129), // #1327 + INST(Vpmullw , VexRvm_Lx , V(660F00,D5,_,x,I,I,4,FVM), 0 , 184, 0 , 8646 , 285, 146), // #1328 + INST(Vpmultishiftqb , VexRvm_Lx , E(660F38,83,_,x,_,1,4,FV ), 0 , 112, 0 , 8654 , 204, 153), // #1329 + INST(Vpmuludq , VexRvm_Lx , V(660F00,F4,_,x,I,1,4,FV ), 0 , 102, 0 , 8669 , 198, 131), // #1330 + INST(Vpopcntb , VexRm_Lx , E(660F38,54,_,x,_,0,4,FV ), 0 , 111, 0 , 8678 , 254, 157), // #1331 + INST(Vpopcntd , VexRm_Lx , E(660F38,55,_,x,_,0,4,FVM), 0 , 110, 0 , 8687 , 338, 158), // #1332 + INST(Vpopcntq , VexRm_Lx , E(660F38,55,_,x,_,1,4,FVM), 0 , 113, 0 , 8696 , 351, 158), // #1333 + INST(Vpopcntw , VexRm_Lx , E(660F38,54,_,x,_,1,4,FV ), 0 , 112, 0 , 8705 , 254, 157), // #1334 + INST(Vpor , VexRvm_Lx , V(660F00,EB,_,x,I,_,_,_ ), 0 , 68 , 0 , 8714 , 316, 143), // #1335 + INST(Vpord , VexRvm_Lx , E(660F00,EB,_,x,_,0,4,FV ), 0 , 189, 0 , 8719 , 317, 126), // #1336 + INST(Vporq , VexRvm_Lx , E(660F00,EB,_,x,_,1,4,FV ), 0 , 130, 0 , 8725 , 321, 126), // #1337 + INST(Vpperm , VexRvrmRvmr , V(XOP_M8,A3,_,0,x,_,_,_ ), 0 , 193, 0 , 8731 , 361, 139), // #1338 + INST(Vprold , VexVmi_Lx , E(660F00,72,1,x,_,0,4,FV ), 0 , 209, 0 , 8738 , 362, 126), // #1339 + INST(Vprolq , VexVmi_Lx , E(660F00,72,1,x,_,1,4,FV ), 0 , 210, 0 , 8745 , 363, 126), // #1340 + INST(Vprolvd , VexRvm_Lx , E(660F38,15,_,x,_,0,4,FV ), 0 , 111, 0 , 8752 , 203, 126), // #1341 + INST(Vprolvq , VexRvm_Lx , E(660F38,15,_,x,_,1,4,FV ), 0 , 112, 0 , 8760 , 204, 126), // #1342 + INST(Vprord , VexVmi_Lx , E(660F00,72,0,x,_,0,4,FV ), 0 , 189, 0 , 8768 , 362, 126), // #1343 + INST(Vprorq , VexVmi_Lx , E(660F00,72,0,x,_,1,4,FV ), 0 , 130, 0 , 8775 , 363, 126), // #1344 + INST(Vprorvd , VexRvm_Lx , E(660F38,14,_,x,_,0,4,FV ), 0 , 111, 0 , 8782 , 203, 126), // #1345 + INST(Vprorvq , VexRvm_Lx , E(660F38,14,_,x,_,1,4,FV ), 0 , 112, 0 , 8790 , 204, 126), // #1346 + INST(Vprotb , VexRvmRmvRmi , V(XOP_M9,90,_,0,x,_,_,_ ), V(XOP_M8,C0,_,0,x,_,_,_ ), 77 , 119, 8798 , 364, 139), // #1347 + INST(Vprotd , VexRvmRmvRmi , V(XOP_M9,92,_,0,x,_,_,_ ), V(XOP_M8,C2,_,0,x,_,_,_ ), 77 , 120, 8805 , 364, 139), // #1348 + INST(Vprotq , VexRvmRmvRmi , V(XOP_M9,93,_,0,x,_,_,_ ), V(XOP_M8,C3,_,0,x,_,_,_ ), 77 , 121, 8812 , 364, 139), // #1349 + INST(Vprotw , VexRvmRmvRmi , V(XOP_M9,91,_,0,x,_,_,_ ), V(XOP_M8,C1,_,0,x,_,_,_ ), 77 , 122, 8819 , 364, 139), // #1350 + INST(Vpsadbw , VexRvm_Lx , V(660F00,F6,_,x,I,I,4,FVM), 0 , 184, 0 , 8826 , 193, 146), // #1351 + INST(Vpscatterdd , VexMr_VM , E(660F38,A0,_,x,_,0,2,T1S), 0 , 125, 0 , 8834 , 365, 126), // #1352 + INST(Vpscatterdq , VexMr_VM , E(660F38,A0,_,x,_,1,3,T1S), 0 , 124, 0 , 8846 , 365, 126), // #1353 + INST(Vpscatterqd , VexMr_VM , E(660F38,A1,_,x,_,0,2,T1S), 0 , 125, 0 , 8858 , 366, 126), // #1354 + INST(Vpscatterqq , VexMr_VM , E(660F38,A1,_,x,_,1,3,T1S), 0 , 124, 0 , 8870 , 367, 126), // #1355 + INST(Vpshab , VexRvmRmv , V(XOP_M9,98,_,0,x,_,_,_ ), 0 , 77 , 0 , 8882 , 368, 139), // #1356 + INST(Vpshad , VexRvmRmv , V(XOP_M9,9A,_,0,x,_,_,_ ), 0 , 77 , 0 , 8889 , 368, 139), // #1357 + INST(Vpshaq , VexRvmRmv , V(XOP_M9,9B,_,0,x,_,_,_ ), 0 , 77 , 0 , 8896 , 368, 139), // #1358 + INST(Vpshaw , VexRvmRmv , V(XOP_M9,99,_,0,x,_,_,_ ), 0 , 77 , 0 , 8903 , 368, 139), // #1359 + INST(Vpshlb , VexRvmRmv , V(XOP_M9,94,_,0,x,_,_,_ ), 0 , 77 , 0 , 8910 , 368, 139), // #1360 + INST(Vpshld , VexRvmRmv , V(XOP_M9,96,_,0,x,_,_,_ ), 0 , 77 , 0 , 8917 , 368, 139), // #1361 + INST(Vpshldd , VexRvmi_Lx , E(660F3A,71,_,x,_,0,4,FV ), 0 , 108, 0 , 8924 , 196, 151), // #1362 + INST(Vpshldq , VexRvmi_Lx , E(660F3A,71,_,x,_,1,4,FV ), 0 , 109, 0 , 8932 , 197, 151), // #1363 + INST(Vpshldvd , VexRvm_Lx , E(660F38,71,_,x,_,0,4,FV ), 0 , 111, 0 , 8940 , 203, 151), // #1364 + INST(Vpshldvq , VexRvm_Lx , E(660F38,71,_,x,_,1,4,FV ), 0 , 112, 0 , 8949 , 204, 151), // #1365 + INST(Vpshldvw , VexRvm_Lx , E(660F38,70,_,x,_,0,4,FVM), 0 , 110, 0 , 8958 , 202, 151), // #1366 + INST(Vpshldw , VexRvmi_Lx , E(660F3A,70,_,x,_,0,4,FVM), 0 , 151, 0 , 8967 , 250, 151), // #1367 + INST(Vpshlq , VexRvmRmv , V(XOP_M9,97,_,0,x,_,_,_ ), 0 , 77 , 0 , 8975 , 368, 139), // #1368 + INST(Vpshlw , VexRvmRmv , V(XOP_M9,95,_,0,x,_,_,_ ), 0 , 77 , 0 , 8982 , 368, 139), // #1369 + INST(Vpshrdd , VexRvmi_Lx , E(660F3A,73,_,x,_,0,4,FV ), 0 , 108, 0 , 8989 , 196, 151), // #1370 + INST(Vpshrdq , VexRvmi_Lx , E(660F3A,73,_,x,_,1,4,FV ), 0 , 109, 0 , 8997 , 197, 151), // #1371 + INST(Vpshrdvd , VexRvm_Lx , E(660F38,73,_,x,_,0,4,FV ), 0 , 111, 0 , 9005 , 203, 151), // #1372 + INST(Vpshrdvq , VexRvm_Lx , E(660F38,73,_,x,_,1,4,FV ), 0 , 112, 0 , 9014 , 204, 151), // #1373 + INST(Vpshrdvw , VexRvm_Lx , E(660F38,72,_,x,_,0,4,FVM), 0 , 110, 0 , 9023 , 202, 151), // #1374 + INST(Vpshrdw , VexRvmi_Lx , E(660F3A,72,_,x,_,0,4,FVM), 0 , 151, 0 , 9032 , 250, 151), // #1375 + INST(Vpshufb , VexRvm_Lx , V(660F38,00,_,x,I,I,4,FVM), 0 , 107, 0 , 9040 , 285, 146), // #1376 + INST(Vpshufbitqmb , VexRvm_Lx , E(660F38,8F,_,x,0,0,4,FVM), 0 , 110, 0 , 9048 , 369, 157), // #1377 + INST(Vpshufd , VexRmi_Lx , V(660F00,70,_,x,I,0,4,FV ), 0 , 133, 0 , 9061 , 370, 131), // #1378 + INST(Vpshufhw , VexRmi_Lx , V(F30F00,70,_,x,I,I,4,FVM), 0 , 185, 0 , 9069 , 371, 146), // #1379 + INST(Vpshuflw , VexRmi_Lx , V(F20F00,70,_,x,I,I,4,FVM), 0 , 211, 0 , 9078 , 371, 146), // #1380 + INST(Vpsignb , VexRvm_Lx , V(660F38,08,_,x,I,_,_,_ ), 0 , 96 , 0 , 9087 , 192, 143), // #1381 + INST(Vpsignd , VexRvm_Lx , V(660F38,0A,_,x,I,_,_,_ ), 0 , 96 , 0 , 9095 , 192, 143), // #1382 + INST(Vpsignw , VexRvm_Lx , V(660F38,09,_,x,I,_,_,_ ), 0 , 96 , 0 , 9103 , 192, 143), // #1383 + INST(Vpslld , VexRvmVmi_Lx , V(660F00,F2,_,x,I,0,4,128), V(660F00,72,6,x,I,0,4,FV ), 212, 123, 9111 , 372, 131), // #1384 + INST(Vpslldq , VexEvexVmi_Lx , V(660F00,73,7,x,I,I,4,FVM), 0 , 213, 0 , 9118 , 373, 146), // #1385 + INST(Vpsllq , VexRvmVmi_Lx , V(660F00,F3,_,x,I,1,4,128), V(660F00,73,6,x,I,1,4,FV ), 214, 124, 9126 , 374, 131), // #1386 + INST(Vpsllvd , VexRvm_Lx , V(660F38,47,_,x,0,0,4,FV ), 0 , 163, 0 , 9133 , 199, 140), // #1387 + INST(Vpsllvq , VexRvm_Lx , V(660F38,47,_,x,1,1,4,FV ), 0 , 162, 0 , 9141 , 198, 140), // #1388 + INST(Vpsllvw , VexRvm_Lx , E(660F38,12,_,x,_,1,4,FVM), 0 , 113, 0 , 9149 , 202, 128), // #1389 + INST(Vpsllw , VexRvmVmi_Lx , V(660F00,F1,_,x,I,I,4,FVM), V(660F00,71,6,x,I,I,4,FVM), 184, 125, 9157 , 375, 146), // #1390 + INST(Vpsrad , VexRvmVmi_Lx , V(660F00,E2,_,x,I,0,4,128), V(660F00,72,4,x,I,0,4,FV ), 212, 126, 9164 , 372, 131), // #1391 + INST(Vpsraq , VexRvmVmi_Lx , E(660F00,E2,_,x,_,1,4,128), E(660F00,72,4,x,_,1,4,FV ), 215, 127, 9171 , 376, 126), // #1392 + INST(Vpsravd , VexRvm_Lx , V(660F38,46,_,x,0,0,4,FV ), 0 , 163, 0 , 9178 , 199, 140), // #1393 + INST(Vpsravq , VexRvm_Lx , E(660F38,46,_,x,_,1,4,FV ), 0 , 112, 0 , 9186 , 204, 126), // #1394 + INST(Vpsravw , VexRvm_Lx , E(660F38,11,_,x,_,1,4,FVM), 0 , 113, 0 , 9194 , 202, 128), // #1395 + INST(Vpsraw , VexRvmVmi_Lx , V(660F00,E1,_,x,I,I,4,128), V(660F00,71,4,x,I,I,4,FVM), 212, 128, 9202 , 375, 146), // #1396 + INST(Vpsrld , VexRvmVmi_Lx , V(660F00,D2,_,x,I,0,4,128), V(660F00,72,2,x,I,0,4,FV ), 212, 129, 9209 , 372, 131), // #1397 + INST(Vpsrldq , VexEvexVmi_Lx , V(660F00,73,3,x,I,I,4,FVM), 0 , 216, 0 , 9216 , 373, 146), // #1398 + INST(Vpsrlq , VexRvmVmi_Lx , V(660F00,D3,_,x,I,1,4,128), V(660F00,73,2,x,I,1,4,FV ), 214, 130, 9224 , 374, 131), // #1399 + INST(Vpsrlvd , VexRvm_Lx , V(660F38,45,_,x,0,0,4,FV ), 0 , 163, 0 , 9231 , 199, 140), // #1400 + INST(Vpsrlvq , VexRvm_Lx , V(660F38,45,_,x,1,1,4,FV ), 0 , 162, 0 , 9239 , 198, 140), // #1401 + INST(Vpsrlvw , VexRvm_Lx , E(660F38,10,_,x,_,1,4,FVM), 0 , 113, 0 , 9247 , 202, 128), // #1402 + INST(Vpsrlw , VexRvmVmi_Lx , V(660F00,D1,_,x,I,I,4,128), V(660F00,71,2,x,I,I,4,FVM), 212, 131, 9255 , 375, 146), // #1403 + INST(Vpsubb , VexRvm_Lx , V(660F00,F8,_,x,I,I,4,FVM), 0 , 184, 0 , 9262 , 377, 146), // #1404 + INST(Vpsubd , VexRvm_Lx , V(660F00,FA,_,x,I,0,4,FV ), 0 , 133, 0 , 9269 , 378, 131), // #1405 + INST(Vpsubq , VexRvm_Lx , V(660F00,FB,_,x,I,1,4,FV ), 0 , 102, 0 , 9276 , 379, 131), // #1406 + INST(Vpsubsb , VexRvm_Lx , V(660F00,E8,_,x,I,I,4,FVM), 0 , 184, 0 , 9283 , 377, 146), // #1407 + INST(Vpsubsw , VexRvm_Lx , V(660F00,E9,_,x,I,I,4,FVM), 0 , 184, 0 , 9291 , 377, 146), // #1408 + INST(Vpsubusb , VexRvm_Lx , V(660F00,D8,_,x,I,I,4,FVM), 0 , 184, 0 , 9299 , 377, 146), // #1409 + INST(Vpsubusw , VexRvm_Lx , V(660F00,D9,_,x,I,I,4,FVM), 0 , 184, 0 , 9308 , 377, 146), // #1410 + INST(Vpsubw , VexRvm_Lx , V(660F00,F9,_,x,I,I,4,FVM), 0 , 184, 0 , 9317 , 377, 146), // #1411 + INST(Vpternlogd , VexRvmi_Lx , E(660F3A,25,_,x,_,0,4,FV ), 0 , 108, 0 , 9324 , 196, 126), // #1412 + INST(Vpternlogq , VexRvmi_Lx , E(660F3A,25,_,x,_,1,4,FV ), 0 , 109, 0 , 9335 , 197, 126), // #1413 + INST(Vptest , VexRm_Lx , V(660F38,17,_,x,I,_,_,_ ), 0 , 96 , 0 , 9346 , 270, 150), // #1414 + INST(Vptestmb , VexRvm_Lx , E(660F38,26,_,x,_,0,4,FVM), 0 , 110, 0 , 9353 , 369, 128), // #1415 + INST(Vptestmd , VexRvm_Lx , E(660F38,27,_,x,_,0,4,FV ), 0 , 111, 0 , 9362 , 380, 126), // #1416 + INST(Vptestmq , VexRvm_Lx , E(660F38,27,_,x,_,1,4,FV ), 0 , 112, 0 , 9371 , 381, 126), // #1417 + INST(Vptestmw , VexRvm_Lx , E(660F38,26,_,x,_,1,4,FVM), 0 , 113, 0 , 9380 , 369, 128), // #1418 + INST(Vptestnmb , VexRvm_Lx , E(F30F38,26,_,x,_,0,4,FVM), 0 , 217, 0 , 9389 , 369, 128), // #1419 + INST(Vptestnmd , VexRvm_Lx , E(F30F38,27,_,x,_,0,4,FV ), 0 , 218, 0 , 9399 , 380, 126), // #1420 + INST(Vptestnmq , VexRvm_Lx , E(F30F38,27,_,x,_,1,4,FV ), 0 , 219, 0 , 9409 , 381, 126), // #1421 + INST(Vptestnmw , VexRvm_Lx , E(F30F38,26,_,x,_,1,4,FVM), 0 , 220, 0 , 9419 , 369, 128), // #1422 + INST(Vpunpckhbw , VexRvm_Lx , V(660F00,68,_,x,I,I,4,FVM), 0 , 184, 0 , 9429 , 285, 146), // #1423 + INST(Vpunpckhdq , VexRvm_Lx , V(660F00,6A,_,x,I,0,4,FV ), 0 , 133, 0 , 9440 , 199, 131), // #1424 + INST(Vpunpckhqdq , VexRvm_Lx , V(660F00,6D,_,x,I,1,4,FV ), 0 , 102, 0 , 9451 , 198, 131), // #1425 + INST(Vpunpckhwd , VexRvm_Lx , V(660F00,69,_,x,I,I,4,FVM), 0 , 184, 0 , 9463 , 285, 146), // #1426 + INST(Vpunpcklbw , VexRvm_Lx , V(660F00,60,_,x,I,I,4,FVM), 0 , 184, 0 , 9474 , 285, 146), // #1427 + INST(Vpunpckldq , VexRvm_Lx , V(660F00,62,_,x,I,0,4,FV ), 0 , 133, 0 , 9485 , 199, 131), // #1428 + INST(Vpunpcklqdq , VexRvm_Lx , V(660F00,6C,_,x,I,1,4,FV ), 0 , 102, 0 , 9496 , 198, 131), // #1429 + INST(Vpunpcklwd , VexRvm_Lx , V(660F00,61,_,x,I,I,4,FVM), 0 , 184, 0 , 9508 , 285, 146), // #1430 + INST(Vpxor , VexRvm_Lx , V(660F00,EF,_,x,I,_,_,_ ), 0 , 68 , 0 , 9519 , 318, 143), // #1431 + INST(Vpxord , VexRvm_Lx , E(660F00,EF,_,x,_,0,4,FV ), 0 , 189, 0 , 9525 , 319, 126), // #1432 + INST(Vpxorq , VexRvm_Lx , E(660F00,EF,_,x,_,1,4,FV ), 0 , 130, 0 , 9532 , 320, 126), // #1433 + INST(Vrangepd , VexRvmi_Lx , E(660F3A,50,_,x,_,1,4,FV ), 0 , 109, 0 , 9539 , 259, 129), // #1434 + INST(Vrangeps , VexRvmi_Lx , E(660F3A,50,_,x,_,0,4,FV ), 0 , 108, 0 , 9548 , 260, 129), // #1435 + INST(Vrangesd , VexRvmi , E(660F3A,51,_,I,_,1,3,T1S), 0 , 160, 0 , 9557 , 261, 64 ), // #1436 + INST(Vrangess , VexRvmi , E(660F3A,51,_,I,_,0,2,T1S), 0 , 161, 0 , 9566 , 262, 64 ), // #1437 + INST(Vrcp14pd , VexRm_Lx , E(660F38,4C,_,x,_,1,4,FV ), 0 , 112, 0 , 9575 , 351, 126), // #1438 + INST(Vrcp14ps , VexRm_Lx , E(660F38,4C,_,x,_,0,4,FV ), 0 , 111, 0 , 9584 , 338, 126), // #1439 + INST(Vrcp14sd , VexRvm , E(660F38,4D,_,I,_,1,3,T1S), 0 , 124, 0 , 9593 , 382, 66 ), // #1440 + INST(Vrcp14ss , VexRvm , E(660F38,4D,_,I,_,0,2,T1S), 0 , 125, 0 , 9602 , 383, 66 ), // #1441 + INST(Vrcp28pd , VexRm , E(660F38,CA,_,2,_,1,4,FV ), 0 , 152, 0 , 9611 , 252, 135), // #1442 + INST(Vrcp28ps , VexRm , E(660F38,CA,_,2,_,0,4,FV ), 0 , 153, 0 , 9620 , 253, 135), // #1443 + INST(Vrcp28sd , VexRvm , E(660F38,CB,_,I,_,1,3,T1S), 0 , 124, 0 , 9629 , 280, 135), // #1444 + INST(Vrcp28ss , VexRvm , E(660F38,CB,_,I,_,0,2,T1S), 0 , 125, 0 , 9638 , 281, 135), // #1445 + INST(Vrcpps , VexRm_Lx , V(000F00,53,_,x,I,_,_,_ ), 0 , 71 , 0 , 9647 , 270, 123), // #1446 + INST(Vrcpss , VexRvm , V(F30F00,53,_,I,I,_,_,_ ), 0 , 178, 0 , 9654 , 384, 123), // #1447 + INST(Vreducepd , VexRmi_Lx , E(660F3A,56,_,x,_,1,4,FV ), 0 , 109, 0 , 9661 , 363, 129), // #1448 + INST(Vreduceps , VexRmi_Lx , E(660F3A,56,_,x,_,0,4,FV ), 0 , 108, 0 , 9671 , 362, 129), // #1449 + INST(Vreducesd , VexRvmi , E(660F3A,57,_,I,_,1,3,T1S), 0 , 160, 0 , 9681 , 385, 64 ), // #1450 + INST(Vreducess , VexRvmi , E(660F3A,57,_,I,_,0,2,T1S), 0 , 161, 0 , 9691 , 386, 64 ), // #1451 + INST(Vrndscalepd , VexRmi_Lx , E(660F3A,09,_,x,_,1,4,FV ), 0 , 109, 0 , 9701 , 282, 126), // #1452 + INST(Vrndscaleps , VexRmi_Lx , E(660F3A,08,_,x,_,0,4,FV ), 0 , 108, 0 , 9713 , 283, 126), // #1453 + INST(Vrndscalesd , VexRvmi , E(660F3A,0B,_,I,_,1,3,T1S), 0 , 160, 0 , 9725 , 261, 66 ), // #1454 + INST(Vrndscaless , VexRvmi , E(660F3A,0A,_,I,_,0,2,T1S), 0 , 161, 0 , 9737 , 262, 66 ), // #1455 + INST(Vroundpd , VexRmi_Lx , V(660F3A,09,_,x,I,_,_,_ ), 0 , 72 , 0 , 9749 , 387, 123), // #1456 + INST(Vroundps , VexRmi_Lx , V(660F3A,08,_,x,I,_,_,_ ), 0 , 72 , 0 , 9758 , 387, 123), // #1457 + INST(Vroundsd , VexRvmi , V(660F3A,0B,_,I,I,_,_,_ ), 0 , 72 , 0 , 9767 , 388, 123), // #1458 + INST(Vroundss , VexRvmi , V(660F3A,0A,_,I,I,_,_,_ ), 0 , 72 , 0 , 9776 , 389, 123), // #1459 + INST(Vrsqrt14pd , VexRm_Lx , E(660F38,4E,_,x,_,1,4,FV ), 0 , 112, 0 , 9785 , 351, 126), // #1460 + INST(Vrsqrt14ps , VexRm_Lx , E(660F38,4E,_,x,_,0,4,FV ), 0 , 111, 0 , 9796 , 338, 126), // #1461 + INST(Vrsqrt14sd , VexRvm , E(660F38,4F,_,I,_,1,3,T1S), 0 , 124, 0 , 9807 , 382, 66 ), // #1462 + INST(Vrsqrt14ss , VexRvm , E(660F38,4F,_,I,_,0,2,T1S), 0 , 125, 0 , 9818 , 383, 66 ), // #1463 + INST(Vrsqrt28pd , VexRm , E(660F38,CC,_,2,_,1,4,FV ), 0 , 152, 0 , 9829 , 252, 135), // #1464 + INST(Vrsqrt28ps , VexRm , E(660F38,CC,_,2,_,0,4,FV ), 0 , 153, 0 , 9840 , 253, 135), // #1465 + INST(Vrsqrt28sd , VexRvm , E(660F38,CD,_,I,_,1,3,T1S), 0 , 124, 0 , 9851 , 280, 135), // #1466 + INST(Vrsqrt28ss , VexRvm , E(660F38,CD,_,I,_,0,2,T1S), 0 , 125, 0 , 9862 , 281, 135), // #1467 + INST(Vrsqrtps , VexRm_Lx , V(000F00,52,_,x,I,_,_,_ ), 0 , 71 , 0 , 9873 , 270, 123), // #1468 + INST(Vrsqrtss , VexRvm , V(F30F00,52,_,I,I,_,_,_ ), 0 , 178, 0 , 9882 , 384, 123), // #1469 + INST(Vscalefpd , VexRvm_Lx , E(660F38,2C,_,x,_,1,4,FV ), 0 , 112, 0 , 9891 , 390, 126), // #1470 + INST(Vscalefps , VexRvm_Lx , E(660F38,2C,_,x,_,0,4,FV ), 0 , 111, 0 , 9901 , 391, 126), // #1471 + INST(Vscalefsd , VexRvm , E(660F38,2D,_,I,_,1,3,T1S), 0 , 124, 0 , 9911 , 392, 66 ), // #1472 + INST(Vscalefss , VexRvm , E(660F38,2D,_,I,_,0,2,T1S), 0 , 125, 0 , 9921 , 393, 66 ), // #1473 + INST(Vscatterdpd , VexMr_Lx , E(660F38,A2,_,x,_,1,3,T1S), 0 , 124, 0 , 9931 , 394, 126), // #1474 + INST(Vscatterdps , VexMr_Lx , E(660F38,A2,_,x,_,0,2,T1S), 0 , 125, 0 , 9943 , 365, 126), // #1475 + INST(Vscatterpf0dpd , VexM_VM , E(660F38,C6,5,2,_,1,3,T1S), 0 , 221, 0 , 9955 , 275, 141), // #1476 + INST(Vscatterpf0dps , VexM_VM , E(660F38,C6,5,2,_,0,2,T1S), 0 , 222, 0 , 9970 , 276, 141), // #1477 + INST(Vscatterpf0qpd , VexM_VM , E(660F38,C7,5,2,_,1,3,T1S), 0 , 221, 0 , 9985 , 277, 141), // #1478 + INST(Vscatterpf0qps , VexM_VM , E(660F38,C7,5,2,_,0,2,T1S), 0 , 222, 0 , 10000, 277, 141), // #1479 + INST(Vscatterpf1dpd , VexM_VM , E(660F38,C6,6,2,_,1,3,T1S), 0 , 223, 0 , 10015, 275, 141), // #1480 + INST(Vscatterpf1dps , VexM_VM , E(660F38,C6,6,2,_,0,2,T1S), 0 , 224, 0 , 10030, 276, 141), // #1481 + INST(Vscatterpf1qpd , VexM_VM , E(660F38,C7,6,2,_,1,3,T1S), 0 , 223, 0 , 10045, 277, 141), // #1482 + INST(Vscatterpf1qps , VexM_VM , E(660F38,C7,6,2,_,0,2,T1S), 0 , 224, 0 , 10060, 277, 141), // #1483 + INST(Vscatterqpd , VexMr_Lx , E(660F38,A3,_,x,_,1,3,T1S), 0 , 124, 0 , 10075, 367, 126), // #1484 + INST(Vscatterqps , VexMr_Lx , E(660F38,A3,_,x,_,0,2,T1S), 0 , 125, 0 , 10087, 366, 126), // #1485 + INST(Vshuff32x4 , VexRvmi_Lx , E(660F3A,23,_,x,_,0,4,FV ), 0 , 108, 0 , 10099, 395, 126), // #1486 + INST(Vshuff64x2 , VexRvmi_Lx , E(660F3A,23,_,x,_,1,4,FV ), 0 , 109, 0 , 10110, 396, 126), // #1487 + INST(Vshufi32x4 , VexRvmi_Lx , E(660F3A,43,_,x,_,0,4,FV ), 0 , 108, 0 , 10121, 395, 126), // #1488 + INST(Vshufi64x2 , VexRvmi_Lx , E(660F3A,43,_,x,_,1,4,FV ), 0 , 109, 0 , 10132, 396, 126), // #1489 + INST(Vshufpd , VexRvmi_Lx , V(660F00,C6,_,x,I,1,4,FV ), 0 , 102, 0 , 10143, 397, 121), // #1490 + INST(Vshufps , VexRvmi_Lx , V(000F00,C6,_,x,I,0,4,FV ), 0 , 103, 0 , 10151, 398, 121), // #1491 + INST(Vsqrtpd , VexRm_Lx , V(660F00,51,_,x,I,1,4,FV ), 0 , 102, 0 , 10159, 399, 121), // #1492 + INST(Vsqrtps , VexRm_Lx , V(000F00,51,_,x,I,0,4,FV ), 0 , 103, 0 , 10167, 222, 121), // #1493 + INST(Vsqrtsd , VexRvm , V(F20F00,51,_,I,I,1,3,T1S), 0 , 104, 0 , 10175, 190, 122), // #1494 + INST(Vsqrtss , VexRvm , V(F30F00,51,_,I,I,0,2,T1S), 0 , 105, 0 , 10183, 191, 122), // #1495 + INST(Vstmxcsr , VexM , V(000F00,AE,3,0,I,_,_,_ ), 0 , 225, 0 , 10191, 291, 123), // #1496 + INST(Vsubpd , VexRvm_Lx , V(660F00,5C,_,x,I,1,4,FV ), 0 , 102, 0 , 10200, 188, 121), // #1497 + INST(Vsubps , VexRvm_Lx , V(000F00,5C,_,x,I,0,4,FV ), 0 , 103, 0 , 10207, 189, 121), // #1498 + INST(Vsubsd , VexRvm , V(F20F00,5C,_,I,I,1,3,T1S), 0 , 104, 0 , 10214, 190, 122), // #1499 + INST(Vsubss , VexRvm , V(F30F00,5C,_,I,I,0,2,T1S), 0 , 105, 0 , 10221, 191, 122), // #1500 + INST(Vtestpd , VexRm_Lx , V(660F38,0F,_,x,0,_,_,_ ), 0 , 96 , 0 , 10228, 270, 150), // #1501 + INST(Vtestps , VexRm_Lx , V(660F38,0E,_,x,0,_,_,_ ), 0 , 96 , 0 , 10236, 270, 150), // #1502 + INST(Vucomisd , VexRm , V(660F00,2E,_,I,I,1,3,T1S), 0 , 122, 0 , 10244, 218, 132), // #1503 + INST(Vucomiss , VexRm , V(000F00,2E,_,I,I,0,2,T1S), 0 , 123, 0 , 10253, 219, 132), // #1504 + INST(Vunpckhpd , VexRvm_Lx , V(660F00,15,_,x,I,1,4,FV ), 0 , 102, 0 , 10262, 198, 121), // #1505 + INST(Vunpckhps , VexRvm_Lx , V(000F00,15,_,x,I,0,4,FV ), 0 , 103, 0 , 10272, 199, 121), // #1506 + INST(Vunpcklpd , VexRvm_Lx , V(660F00,14,_,x,I,1,4,FV ), 0 , 102, 0 , 10282, 198, 121), // #1507 + INST(Vunpcklps , VexRvm_Lx , V(000F00,14,_,x,I,0,4,FV ), 0 , 103, 0 , 10292, 199, 121), // #1508 + INST(Vxorpd , VexRvm_Lx , V(660F00,57,_,x,I,1,4,FV ), 0 , 102, 0 , 10302, 379, 127), // #1509 + INST(Vxorps , VexRvm_Lx , V(000F00,57,_,x,I,0,4,FV ), 0 , 103, 0 , 10309, 378, 127), // #1510 + INST(Vzeroall , VexOp , V(000F00,77,_,1,I,_,_,_ ), 0 , 67 , 0 , 10316, 400, 123), // #1511 + INST(Vzeroupper , VexOp , V(000F00,77,_,0,I,_,_,_ ), 0 , 71 , 0 , 10325, 400, 123), // #1512 + INST(Wbinvd , X86Op , O(000F00,09,_,_,_,_,_,_ ), 0 , 4 , 0 , 10336, 30 , 0 ), // #1513 + INST(Wbnoinvd , X86Op , O(F30F00,09,_,_,_,_,_,_ ), 0 , 6 , 0 , 10343, 30 , 159), // #1514 + INST(Wrfsbase , X86M , O(F30F00,AE,2,_,x,_,_,_ ), 0 , 226, 0 , 10352, 166, 102), // #1515 + INST(Wrgsbase , X86M , O(F30F00,AE,3,_,x,_,_,_ ), 0 , 227, 0 , 10361, 166, 102), // #1516 + INST(Wrmsr , X86Op , O(000F00,30,_,_,_,_,_,_ ), 0 , 4 , 0 , 10370, 167, 103), // #1517 + INST(Wrssd , X86Mr , O(000F38,F6,_,_,_,_,_,_ ), 0 , 82 , 0 , 10376, 401, 54 ), // #1518 + INST(Wrssq , X86Mr , O(000F38,F6,_,_,1,_,_,_ ), 0 , 228, 0 , 10382, 402, 54 ), // #1519 + INST(Wrussd , X86Mr , O(660F38,F5,_,_,_,_,_,_ ), 0 , 2 , 0 , 10388, 401, 54 ), // #1520 + INST(Wrussq , X86Mr , O(660F38,F5,_,_,1,_,_,_ ), 0 , 229, 0 , 10395, 402, 54 ), // #1521 + INST(Xabort , X86Op_Mod11RM_I8 , O(000000,C6,7,_,_,_,_,_ ), 0 , 26 , 0 , 10402, 77 , 160), // #1522 + INST(Xadd , X86Xadd , O(000F00,C0,_,_,x,_,_,_ ), 0 , 4 , 0 , 10409, 403, 37 ), // #1523 + INST(Xbegin , X86JmpRel , O(000000,C7,7,_,_,_,_,_ ), 0 , 26 , 0 , 10414, 404, 160), // #1524 + INST(Xchg , X86Xchg , O(000000,86,_,_,x,_,_,_ ), 0 , 0 , 0 , 457 , 405, 0 ), // #1525 + INST(Xend , X86Op , O(000F01,D5,_,_,_,_,_,_ ), 0 , 21 , 0 , 10421, 30 , 160), // #1526 + INST(Xgetbv , X86Op , O(000F01,D0,_,_,_,_,_,_ ), 0 , 21 , 0 , 10426, 167, 161), // #1527 + INST(Xlatb , X86Op , O(000000,D7,_,_,_,_,_,_ ), 0 , 0 , 0 , 10433, 30 , 0 ), // #1528 + INST(Xor , X86Arith , O(000000,30,6,_,x,_,_,_ ), 0 , 31 , 0 , 9521 , 171, 1 ), // #1529 + INST(Xorpd , ExtRm , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 10303, 144, 4 ), // #1530 + INST(Xorps , ExtRm , O(000F00,57,_,_,_,_,_,_ ), 0 , 4 , 0 , 10310, 144, 5 ), // #1531 + INST(Xresldtrk , X86Op , O(F20F01,E9,_,_,_,_,_,_ ), 0 , 92 , 0 , 10439, 30 , 162), // #1532 + INST(Xrstor , X86M_Only , O(000F00,AE,5,_,_,_,_,_ ), 0 , 75 , 0 , 1159 , 406, 161), // #1533 + INST(Xrstor64 , X86M_Only , O(000F00,AE,5,_,1,_,_,_ ), 0 , 230, 0 , 1167 , 407, 161), // #1534 + INST(Xrstors , X86M_Only , O(000F00,C7,3,_,_,_,_,_ ), 0 , 76 , 0 , 10449, 406, 163), // #1535 + INST(Xrstors64 , X86M_Only , O(000F00,C7,3,_,1,_,_,_ ), 0 , 231, 0 , 10457, 407, 163), // #1536 + INST(Xsave , X86M_Only , O(000F00,AE,4,_,_,_,_,_ ), 0 , 97 , 0 , 1177 , 406, 161), // #1537 + INST(Xsave64 , X86M_Only , O(000F00,AE,4,_,1,_,_,_ ), 0 , 232, 0 , 1184 , 407, 161), // #1538 + INST(Xsavec , X86M_Only , O(000F00,C7,4,_,_,_,_,_ ), 0 , 97 , 0 , 10467, 406, 164), // #1539 + INST(Xsavec64 , X86M_Only , O(000F00,C7,4,_,1,_,_,_ ), 0 , 232, 0 , 10474, 407, 164), // #1540 + INST(Xsaveopt , X86M_Only , O(000F00,AE,6,_,_,_,_,_ ), 0 , 78 , 0 , 10483, 406, 165), // #1541 + INST(Xsaveopt64 , X86M_Only , O(000F00,AE,6,_,1,_,_,_ ), 0 , 233, 0 , 10492, 407, 165), // #1542 + INST(Xsaves , X86M_Only , O(000F00,C7,5,_,_,_,_,_ ), 0 , 75 , 0 , 10503, 406, 163), // #1543 + INST(Xsaves64 , X86M_Only , O(000F00,C7,5,_,1,_,_,_ ), 0 , 230, 0 , 10510, 407, 163), // #1544 + INST(Xsetbv , X86Op , O(000F01,D1,_,_,_,_,_,_ ), 0 , 21 , 0 , 10519, 167, 161), // #1545 + INST(Xsusldtrk , X86Op , O(F20F01,E8,_,_,_,_,_,_ ), 0 , 92 , 0 , 10526, 30 , 162), // #1546 + INST(Xtest , X86Op , O(000F01,D6,_,_,_,_,_,_ ), 0 , 21 , 0 , 10536, 30 , 166) // #1547 // ${InstInfo:End} }; #undef NAME_DATA_INDEX @@ -1639,9 +1656,9 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { const uint32_t InstDB::_mainOpcodeTable[] = { O(000000,00,0,0,0,0,0,_ ), // #0 [ref=56x] O(000000,00,2,0,0,0,0,_ ), // #1 [ref=4x] - O(660F38,00,0,0,0,0,0,_ ), // #2 [ref=42x] + O(660F38,00,0,0,0,0,0,_ ), // #2 [ref=43x] O(660F00,00,0,0,0,0,0,_ ), // #3 [ref=38x] - O(000F00,00,0,0,0,0,0,_ ), // #4 [ref=231x] + O(000F00,00,0,0,0,0,0,_ ), // #4 [ref=233x] O(F20F00,00,0,0,0,0,0,_ ), // #5 [ref=24x] O(F30F00,00,0,0,0,0,0,_ ), // #6 [ref=29x] O(F30F38,00,0,0,0,0,0,_ ), // #7 [ref=2x] @@ -1658,212 +1675,219 @@ const uint32_t InstDB::_mainOpcodeTable[] = { V(000F38,00,1,0,0,0,0,_ ), // #18 [ref=1x] O(660000,00,0,0,0,0,0,_ ), // #19 [ref=7x] O(000000,00,0,0,1,0,0,_ ), // #20 [ref=3x] - O(000F01,00,0,0,0,0,0,_ ), // #21 [ref=28x] + O(000F01,00,0,0,0,0,0,_ ), // #21 [ref=29x] O(000F00,00,7,0,0,0,0,_ ), // #22 [ref=5x] - O(660F00,00,7,0,0,0,0,_ ), // #23 [ref=2x] - O(660F00,00,6,0,0,0,0,_ ), // #24 [ref=3x] - O(000000,00,7,0,0,0,0,_ ), // #25 [ref=5x] - O(000F00,00,1,0,1,0,0,_ ), // #26 [ref=2x] - O(000F00,00,1,0,0,0,0,_ ), // #27 [ref=6x] - O(F20F38,00,0,0,0,0,0,_ ), // #28 [ref=2x] - O(000000,00,1,0,0,0,0,_ ), // #29 [ref=3x] - O(000000,00,6,0,0,0,0,_ ), // #30 [ref=3x] - O_FPU(00,D900,_) , // #31 [ref=29x] - O_FPU(00,C000,0) , // #32 [ref=1x] - O_FPU(00,DE00,_) , // #33 [ref=7x] - O_FPU(00,0000,4) , // #34 [ref=4x] - O_FPU(00,0000,6) , // #35 [ref=4x] - O_FPU(9B,DB00,_) , // #36 [ref=2x] - O_FPU(00,DA00,_) , // #37 [ref=5x] - O_FPU(00,DB00,_) , // #38 [ref=8x] - O_FPU(00,D000,2) , // #39 [ref=1x] - O_FPU(00,DF00,_) , // #40 [ref=2x] - O_FPU(00,D800,3) , // #41 [ref=1x] - O_FPU(00,F000,6) , // #42 [ref=1x] - O_FPU(00,F800,7) , // #43 [ref=1x] - O_FPU(00,DD00,_) , // #44 [ref=3x] - O_FPU(00,0000,0) , // #45 [ref=3x] - O_FPU(00,0000,2) , // #46 [ref=3x] - O_FPU(00,0000,3) , // #47 [ref=3x] - O_FPU(00,0000,7) , // #48 [ref=3x] - O_FPU(00,0000,1) , // #49 [ref=2x] - O_FPU(00,0000,5) , // #50 [ref=2x] - O_FPU(00,C800,1) , // #51 [ref=1x] - O_FPU(9B,0000,6) , // #52 [ref=2x] - O_FPU(9B,0000,7) , // #53 [ref=2x] - O_FPU(00,E000,4) , // #54 [ref=1x] - O_FPU(00,E800,5) , // #55 [ref=1x] - O_FPU(00,0000,_) , // #56 [ref=1x] - O(000F00,00,0,0,1,0,0,_ ), // #57 [ref=1x] - O(000000,00,5,0,0,0,0,_ ), // #58 [ref=3x] - V(660F00,00,0,1,0,0,0,_ ), // #59 [ref=7x] - V(660F00,00,0,1,1,0,0,_ ), // #60 [ref=6x] - V(000F00,00,0,1,1,0,0,_ ), // #61 [ref=7x] - V(000F00,00,0,1,0,0,0,_ ), // #62 [ref=8x] - V(660F00,00,0,0,0,0,0,_ ), // #63 [ref=15x] - V(660F00,00,0,0,1,0,0,_ ), // #64 [ref=4x] - V(000F00,00,0,0,1,0,0,_ ), // #65 [ref=4x] - V(000F00,00,0,0,0,0,0,_ ), // #66 [ref=10x] - V(660F3A,00,0,0,0,0,0,_ ), // #67 [ref=45x] - V(660F3A,00,0,0,1,0,0,_ ), // #68 [ref=4x] - O(000F00,00,2,0,0,0,0,_ ), // #69 [ref=5x] - O(000F00,00,5,0,0,0,0,_ ), // #70 [ref=4x] - O(000F00,00,3,0,0,0,0,_ ), // #71 [ref=5x] - V(XOP_M9,00,0,0,0,0,0,_ ), // #72 [ref=32x] - O(000F00,00,6,0,0,0,0,_ ), // #73 [ref=5x] - V(XOP_MA,00,0,0,0,0,0,_ ), // #74 [ref=1x] - V(XOP_MA,00,1,0,0,0,0,_ ), // #75 [ref=1x] - O(F30F01,00,0,0,0,0,0,_ ), // #76 [ref=3x] - O(000F38,00,0,0,0,0,0,_ ), // #77 [ref=23x] - V(F20F38,00,0,0,0,0,0,_ ), // #78 [ref=6x] - O(000000,00,3,0,0,0,0,_ ), // #79 [ref=3x] - O(000F3A,00,0,0,0,0,0,_ ), // #80 [ref=4x] - O(F30000,00,0,0,0,0,0,_ ), // #81 [ref=1x] - O(000F0F,00,0,0,0,0,0,_ ), // #82 [ref=26x] - V(F30F38,00,0,0,0,0,0,_ ), // #83 [ref=5x] - O(000F3A,00,0,0,1,0,0,_ ), // #84 [ref=1x] - O(660F3A,00,0,0,1,0,0,_ ), // #85 [ref=1x] - O(F20F01,00,0,0,0,0,0,_ ), // #86 [ref=4x] - O(F30F00,00,1,0,0,0,0,_ ), // #87 [ref=1x] - O(F30F00,00,7,0,0,0,0,_ ), // #88 [ref=1x] - V(F20F3A,00,0,0,0,0,0,_ ), // #89 [ref=1x] - V(660F38,00,0,0,0,0,0,_ ), // #90 [ref=25x] - O(000F00,00,4,0,0,0,0,_ ), // #91 [ref=4x] - V(XOP_M9,00,7,0,0,0,0,_ ), // #92 [ref=1x] - V(XOP_M9,00,4,0,0,0,0,_ ), // #93 [ref=1x] - O(F30F00,00,6,0,0,0,0,_ ), // #94 [ref=2x] - O(F20F00,00,6,0,0,0,0,_ ), // #95 [ref=1x] - E(F20F38,00,0,2,0,0,2,T4X), // #96 [ref=6x] - V(660F00,00,0,0,0,1,4,FV ), // #97 [ref=22x] - V(000F00,00,0,0,0,0,4,FV ), // #98 [ref=16x] - V(F20F00,00,0,0,0,1,3,T1S), // #99 [ref=10x] - V(F30F00,00,0,0,0,0,2,T1S), // #100 [ref=10x] - V(F20F00,00,0,0,0,0,0,_ ), // #101 [ref=4x] - V(660F38,00,0,0,0,0,4,FVM), // #102 [ref=14x] - E(660F3A,00,0,0,0,0,4,FV ), // #103 [ref=14x] - E(660F3A,00,0,0,0,1,4,FV ), // #104 [ref=14x] - E(660F38,00,0,0,0,0,4,FVM), // #105 [ref=9x] - E(660F38,00,0,0,0,0,4,FV ), // #106 [ref=22x] - E(660F38,00,0,0,0,1,4,FV ), // #107 [ref=28x] - E(660F38,00,0,0,0,1,4,FVM), // #108 [ref=9x] - V(660F38,00,0,1,0,0,0,_ ), // #109 [ref=2x] - E(660F38,00,0,0,0,0,3,T2 ), // #110 [ref=2x] - E(660F38,00,0,0,0,0,4,T4 ), // #111 [ref=2x] - E(660F38,00,0,2,0,0,5,T8 ), // #112 [ref=2x] - E(660F38,00,0,0,0,1,4,T2 ), // #113 [ref=2x] - E(660F38,00,0,2,0,1,5,T4 ), // #114 [ref=2x] - V(660F38,00,0,0,0,1,3,T1S), // #115 [ref=2x] - V(660F38,00,0,0,0,0,2,T1S), // #116 [ref=14x] - V(660F00,00,0,0,0,1,3,T1S), // #117 [ref=5x] - V(000F00,00,0,0,0,0,2,T1S), // #118 [ref=2x] - E(660F38,00,0,0,0,1,3,T1S), // #119 [ref=14x] - E(660F38,00,0,0,0,0,2,T1S), // #120 [ref=14x] - V(F30F00,00,0,0,0,0,3,HV ), // #121 [ref=1x] - E(F20F38,00,0,0,0,0,0,_ ), // #122 [ref=1x] - E(F30F38,00,0,0,0,0,0,_ ), // #123 [ref=7x] - V(F20F00,00,0,0,0,1,4,FV ), // #124 [ref=1x] - E(660F00,00,0,0,0,1,4,FV ), // #125 [ref=9x] - E(000F00,00,0,0,0,1,4,FV ), // #126 [ref=3x] - V(660F38,00,0,0,0,0,3,HVM), // #127 [ref=7x] - V(660F00,00,0,0,0,0,4,FV ), // #128 [ref=11x] - V(000F00,00,0,0,0,0,4,HV ), // #129 [ref=1x] - V(660F3A,00,0,0,0,0,3,HVM), // #130 [ref=1x] - E(660F00,00,0,0,0,0,3,HV ), // #131 [ref=4x] - E(000F00,00,0,0,0,0,4,FV ), // #132 [ref=2x] - E(F30F00,00,0,0,0,1,4,FV ), // #133 [ref=2x] - V(F20F00,00,0,0,0,0,3,T1F), // #134 [ref=2x] - E(F20F00,00,0,0,0,0,3,T1F), // #135 [ref=2x] - V(F20F00,00,0,0,0,0,2,T1W), // #136 [ref=1x] - V(F30F00,00,0,0,0,0,2,T1W), // #137 [ref=1x] - V(F30F00,00,0,0,0,0,2,T1F), // #138 [ref=2x] - E(F30F00,00,0,0,0,0,2,T1F), // #139 [ref=2x] - V(F30F00,00,0,0,0,0,4,FV ), // #140 [ref=1x] - E(F30F00,00,0,0,0,0,3,HV ), // #141 [ref=1x] - E(F20F00,00,0,0,0,0,4,FV ), // #142 [ref=1x] - E(F20F00,00,0,0,0,1,4,FV ), // #143 [ref=1x] - E(F20F00,00,0,0,0,0,2,T1W), // #144 [ref=1x] - E(F30F00,00,0,0,0,0,2,T1W), // #145 [ref=1x] - E(660F3A,00,0,0,0,0,4,FVM), // #146 [ref=5x] - E(660F38,00,0,2,0,1,4,FV ), // #147 [ref=3x] - E(660F38,00,0,2,0,0,4,FV ), // #148 [ref=3x] - V(660F3A,00,0,1,0,0,0,_ ), // #149 [ref=6x] - E(660F3A,00,0,0,0,0,4,T4 ), // #150 [ref=4x] - E(660F3A,00,0,2,0,0,5,T8 ), // #151 [ref=4x] - E(660F3A,00,0,0,0,1,4,T2 ), // #152 [ref=4x] - E(660F3A,00,0,2,0,1,5,T4 ), // #153 [ref=4x] - V(660F3A,00,0,0,0,0,2,T1S), // #154 [ref=4x] - E(660F3A,00,0,0,0,1,3,T1S), // #155 [ref=6x] - E(660F3A,00,0,0,0,0,2,T1S), // #156 [ref=6x] - V(660F38,00,0,0,1,1,4,FV ), // #157 [ref=20x] - V(660F38,00,0,0,0,0,4,FV ), // #158 [ref=32x] - V(660F38,00,0,0,1,1,3,T1S), // #159 [ref=12x] - V(660F38,00,0,0,1,0,0,_ ), // #160 [ref=5x] - E(660F38,00,1,2,0,1,3,T1S), // #161 [ref=2x] - E(660F38,00,1,2,0,0,2,T1S), // #162 [ref=2x] - E(660F38,00,2,2,0,1,3,T1S), // #163 [ref=2x] - E(660F38,00,2,2,0,0,2,T1S), // #164 [ref=2x] - V(660F3A,00,0,0,1,1,4,FV ), // #165 [ref=2x] - V(000F00,00,2,0,0,0,0,_ ), // #166 [ref=1x] - V(660F00,00,0,0,0,1,4,FVM), // #167 [ref=3x] - V(000F00,00,0,0,0,0,4,FVM), // #168 [ref=3x] - V(660F00,00,0,0,0,0,2,T1S), // #169 [ref=1x] - V(F20F00,00,0,0,0,1,3,DUP), // #170 [ref=1x] - E(660F00,00,0,0,0,0,4,FVM), // #171 [ref=1x] - E(660F00,00,0,0,0,1,4,FVM), // #172 [ref=1x] - V(F30F00,00,0,0,0,0,0,_ ), // #173 [ref=3x] - E(F20F00,00,0,0,0,1,4,FVM), // #174 [ref=1x] - E(F30F00,00,0,0,0,0,4,FVM), // #175 [ref=1x] - E(F30F00,00,0,0,0,1,4,FVM), // #176 [ref=1x] - E(F20F00,00,0,0,0,0,4,FVM), // #177 [ref=1x] - V(000F00,00,0,0,0,0,3,T2 ), // #178 [ref=2x] - V(660F00,00,0,0,0,0,4,FVM), // #179 [ref=33x] - V(F30F00,00,0,0,0,0,4,FVM), // #180 [ref=3x] - E(F20F38,00,0,0,0,0,4,FV ), // #181 [ref=1x] - E(F20F38,00,0,0,0,1,4,FV ), // #182 [ref=1x] - V(660F3A,00,0,0,0,0,4,FVM), // #183 [ref=2x] - E(660F00,00,0,0,0,0,4,FV ), // #184 [ref=5x] - V(660F38,00,0,0,0,0,0,T1S), // #185 [ref=1x] - E(F30F38,00,0,0,0,1,0,_ ), // #186 [ref=5x] - V(660F38,00,0,0,0,0,1,T1S), // #187 [ref=1x] - V(XOP_M8,00,0,0,0,0,0,_ ), // #188 [ref=22x] - V(660F38,00,0,0,0,1,4,FVM), // #189 [ref=2x] - E(660F3A,00,0,0,0,1,4,FVM), // #190 [ref=2x] - E(660F38,00,0,0,0,0,0,T1S), // #191 [ref=2x] - E(660F38,00,0,0,0,1,1,T1S), // #192 [ref=2x] - V(660F38,00,0,0,0,1,4,FV ), // #193 [ref=3x] - E(660F38,00,0,0,1,1,4,FV ), // #194 [ref=1x] - V(660F3A,00,0,0,0,0,0,T1S), // #195 [ref=2x] - V(660F3A,00,0,0,1,1,3,T1S), // #196 [ref=2x] - V(660F3A,00,0,0,0,0,1,T1S), // #197 [ref=1x] - V(660F00,00,0,0,0,0,1,T1S), // #198 [ref=1x] - E(F30F38,00,0,0,0,0,2,QVM), // #199 [ref=6x] - E(F30F38,00,0,0,0,0,3,HVM), // #200 [ref=9x] - E(F30F38,00,0,0,0,0,1,OVM), // #201 [ref=3x] - V(660F38,00,0,0,0,0,2,QVM), // #202 [ref=4x] - V(660F38,00,0,0,0,0,1,OVM), // #203 [ref=2x] - E(660F00,00,1,0,0,0,4,FV ), // #204 [ref=1x] - E(660F00,00,1,0,0,1,4,FV ), // #205 [ref=1x] - V(F20F00,00,0,0,0,0,4,FVM), // #206 [ref=1x] - V(660F00,00,0,0,0,0,4,128), // #207 [ref=5x] - V(660F00,00,7,0,0,0,4,FVM), // #208 [ref=1x] - V(660F00,00,0,0,0,1,4,128), // #209 [ref=2x] - E(660F00,00,0,0,0,1,4,128), // #210 [ref=1x] - V(660F00,00,3,0,0,0,4,FVM), // #211 [ref=1x] - E(F30F38,00,0,0,0,0,4,FVM), // #212 [ref=1x] - E(F30F38,00,0,0,0,0,4,FV ), // #213 [ref=1x] - E(F30F38,00,0,0,0,1,4,FV ), // #214 [ref=1x] - E(F30F38,00,0,0,0,1,4,FVM), // #215 [ref=1x] - E(660F38,00,5,2,0,1,3,T1S), // #216 [ref=2x] - E(660F38,00,5,2,0,0,2,T1S), // #217 [ref=2x] - E(660F38,00,6,2,0,1,3,T1S), // #218 [ref=2x] - E(660F38,00,6,2,0,0,2,T1S), // #219 [ref=2x] - V(000F00,00,3,0,0,0,0,_ ), // #220 [ref=1x] - O(F30F00,00,2,0,0,0,0,_ ), // #221 [ref=1x] - O(F30F00,00,3,0,0,0,0,_ ), // #222 [ref=1x] - O(000F00,00,5,0,1,0,0,_ ), // #223 [ref=2x] - O(000F00,00,3,0,1,0,0,_ ), // #224 [ref=1x] - O(000F00,00,4,0,1,0,0,_ ), // #225 [ref=2x] - O(000F00,00,6,0,1,0,0,_ ) // #226 [ref=1x] + O(660F00,00,7,0,0,0,0,_ ), // #23 [ref=1x] + O(F30F00,00,6,0,0,0,0,_ ), // #24 [ref=3x] + O(660F00,00,6,0,0,0,0,_ ), // #25 [ref=3x] + O(000000,00,7,0,0,0,0,_ ), // #26 [ref=5x] + O(000F00,00,1,0,1,0,0,_ ), // #27 [ref=2x] + O(000F00,00,1,0,0,0,0,_ ), // #28 [ref=6x] + O(F20F38,00,0,0,0,0,0,_ ), // #29 [ref=2x] + O(000000,00,1,0,0,0,0,_ ), // #30 [ref=3x] + O(000000,00,6,0,0,0,0,_ ), // #31 [ref=3x] + O(F30F00,00,7,0,0,0,0,3 ), // #32 [ref=1x] + O(F30F00,00,7,0,0,0,0,2 ), // #33 [ref=1x] + O_FPU(00,D900,_) , // #34 [ref=29x] + O_FPU(00,C000,0) , // #35 [ref=1x] + O_FPU(00,DE00,_) , // #36 [ref=7x] + O_FPU(00,0000,4) , // #37 [ref=4x] + O_FPU(00,0000,6) , // #38 [ref=4x] + O_FPU(9B,DB00,_) , // #39 [ref=2x] + O_FPU(00,DA00,_) , // #40 [ref=5x] + O_FPU(00,DB00,_) , // #41 [ref=8x] + O_FPU(00,D000,2) , // #42 [ref=1x] + O_FPU(00,DF00,_) , // #43 [ref=2x] + O_FPU(00,D800,3) , // #44 [ref=1x] + O_FPU(00,F000,6) , // #45 [ref=1x] + O_FPU(00,F800,7) , // #46 [ref=1x] + O_FPU(00,DD00,_) , // #47 [ref=3x] + O_FPU(00,0000,0) , // #48 [ref=3x] + O_FPU(00,0000,2) , // #49 [ref=3x] + O_FPU(00,0000,3) , // #50 [ref=3x] + O_FPU(00,0000,7) , // #51 [ref=3x] + O_FPU(00,0000,1) , // #52 [ref=2x] + O_FPU(00,0000,5) , // #53 [ref=2x] + O_FPU(00,C800,1) , // #54 [ref=1x] + O_FPU(9B,0000,6) , // #55 [ref=2x] + O_FPU(9B,0000,7) , // #56 [ref=2x] + O_FPU(00,E000,4) , // #57 [ref=1x] + O_FPU(00,E800,5) , // #58 [ref=1x] + O_FPU(00,0000,_) , // #59 [ref=1x] + O(000F00,00,0,0,1,0,0,_ ), // #60 [ref=1x] + O(000000,00,5,0,0,0,0,_ ), // #61 [ref=3x] + O(F30F00,00,5,0,0,0,0,_ ), // #62 [ref=2x] + O(F30F00,00,5,0,1,0,0,_ ), // #63 [ref=1x] + V(660F00,00,0,1,0,0,0,_ ), // #64 [ref=7x] + V(660F00,00,0,1,1,0,0,_ ), // #65 [ref=6x] + V(000F00,00,0,1,1,0,0,_ ), // #66 [ref=7x] + V(000F00,00,0,1,0,0,0,_ ), // #67 [ref=8x] + V(660F00,00,0,0,0,0,0,_ ), // #68 [ref=15x] + V(660F00,00,0,0,1,0,0,_ ), // #69 [ref=4x] + V(000F00,00,0,0,1,0,0,_ ), // #70 [ref=4x] + V(000F00,00,0,0,0,0,0,_ ), // #71 [ref=10x] + V(660F3A,00,0,0,0,0,0,_ ), // #72 [ref=45x] + V(660F3A,00,0,0,1,0,0,_ ), // #73 [ref=4x] + O(000F00,00,2,0,0,0,0,_ ), // #74 [ref=5x] + O(000F00,00,5,0,0,0,0,_ ), // #75 [ref=4x] + O(000F00,00,3,0,0,0,0,_ ), // #76 [ref=5x] + V(XOP_M9,00,0,0,0,0,0,_ ), // #77 [ref=32x] + O(000F00,00,6,0,0,0,0,_ ), // #78 [ref=5x] + V(XOP_MA,00,0,0,0,0,0,_ ), // #79 [ref=1x] + V(XOP_MA,00,1,0,0,0,0,_ ), // #80 [ref=1x] + O(F30F01,00,0,0,0,0,0,_ ), // #81 [ref=5x] + O(000F38,00,0,0,0,0,0,_ ), // #82 [ref=24x] + V(F20F38,00,0,0,0,0,0,_ ), // #83 [ref=6x] + O(000000,00,3,0,0,0,0,_ ), // #84 [ref=3x] + O(000F3A,00,0,0,0,0,0,_ ), // #85 [ref=4x] + O(F30000,00,0,0,0,0,0,_ ), // #86 [ref=1x] + O(000F0F,00,0,0,0,0,0,_ ), // #87 [ref=26x] + V(F30F38,00,0,0,0,0,0,_ ), // #88 [ref=5x] + O(000F3A,00,0,0,1,0,0,_ ), // #89 [ref=1x] + O(660F3A,00,0,0,1,0,0,_ ), // #90 [ref=1x] + O(F30F00,00,4,0,0,0,0,_ ), // #91 [ref=1x] + O(F20F01,00,0,0,0,0,0,_ ), // #92 [ref=4x] + O(F30F00,00,1,0,0,0,0,_ ), // #93 [ref=3x] + O(F30F00,00,7,0,0,0,0,_ ), // #94 [ref=1x] + V(F20F3A,00,0,0,0,0,0,_ ), // #95 [ref=1x] + V(660F38,00,0,0,0,0,0,_ ), // #96 [ref=25x] + O(000F00,00,4,0,0,0,0,_ ), // #97 [ref=4x] + V(XOP_M9,00,7,0,0,0,0,_ ), // #98 [ref=1x] + V(XOP_M9,00,4,0,0,0,0,_ ), // #99 [ref=1x] + O(F20F00,00,6,0,0,0,0,_ ), // #100 [ref=1x] + E(F20F38,00,0,2,0,0,2,T4X), // #101 [ref=6x] + V(660F00,00,0,0,0,1,4,FV ), // #102 [ref=22x] + V(000F00,00,0,0,0,0,4,FV ), // #103 [ref=16x] + V(F20F00,00,0,0,0,1,3,T1S), // #104 [ref=10x] + V(F30F00,00,0,0,0,0,2,T1S), // #105 [ref=10x] + V(F20F00,00,0,0,0,0,0,_ ), // #106 [ref=4x] + V(660F38,00,0,0,0,0,4,FVM), // #107 [ref=14x] + E(660F3A,00,0,0,0,0,4,FV ), // #108 [ref=14x] + E(660F3A,00,0,0,0,1,4,FV ), // #109 [ref=14x] + E(660F38,00,0,0,0,0,4,FVM), // #110 [ref=9x] + E(660F38,00,0,0,0,0,4,FV ), // #111 [ref=22x] + E(660F38,00,0,0,0,1,4,FV ), // #112 [ref=28x] + E(660F38,00,0,0,0,1,4,FVM), // #113 [ref=9x] + V(660F38,00,0,1,0,0,0,_ ), // #114 [ref=2x] + E(660F38,00,0,0,0,0,3,T2 ), // #115 [ref=2x] + E(660F38,00,0,0,0,0,4,T4 ), // #116 [ref=2x] + E(660F38,00,0,2,0,0,5,T8 ), // #117 [ref=2x] + E(660F38,00,0,0,0,1,4,T2 ), // #118 [ref=2x] + E(660F38,00,0,2,0,1,5,T4 ), // #119 [ref=2x] + V(660F38,00,0,0,0,1,3,T1S), // #120 [ref=2x] + V(660F38,00,0,0,0,0,2,T1S), // #121 [ref=14x] + V(660F00,00,0,0,0,1,3,T1S), // #122 [ref=5x] + V(000F00,00,0,0,0,0,2,T1S), // #123 [ref=2x] + E(660F38,00,0,0,0,1,3,T1S), // #124 [ref=14x] + E(660F38,00,0,0,0,0,2,T1S), // #125 [ref=14x] + V(F30F00,00,0,0,0,0,3,HV ), // #126 [ref=1x] + E(F20F38,00,0,0,0,0,0,_ ), // #127 [ref=1x] + E(F30F38,00,0,0,0,0,0,_ ), // #128 [ref=7x] + V(F20F00,00,0,0,0,1,4,FV ), // #129 [ref=1x] + E(660F00,00,0,0,0,1,4,FV ), // #130 [ref=9x] + E(000F00,00,0,0,0,1,4,FV ), // #131 [ref=3x] + V(660F38,00,0,0,0,0,3,HVM), // #132 [ref=7x] + V(660F00,00,0,0,0,0,4,FV ), // #133 [ref=11x] + V(000F00,00,0,0,0,0,4,HV ), // #134 [ref=1x] + V(660F3A,00,0,0,0,0,3,HVM), // #135 [ref=1x] + E(660F00,00,0,0,0,0,3,HV ), // #136 [ref=4x] + E(000F00,00,0,0,0,0,4,FV ), // #137 [ref=2x] + E(F30F00,00,0,0,0,1,4,FV ), // #138 [ref=2x] + V(F20F00,00,0,0,0,0,3,T1F), // #139 [ref=2x] + E(F20F00,00,0,0,0,0,3,T1F), // #140 [ref=2x] + V(F20F00,00,0,0,0,0,2,T1W), // #141 [ref=1x] + V(F30F00,00,0,0,0,0,2,T1W), // #142 [ref=1x] + V(F30F00,00,0,0,0,0,2,T1F), // #143 [ref=2x] + E(F30F00,00,0,0,0,0,2,T1F), // #144 [ref=2x] + V(F30F00,00,0,0,0,0,4,FV ), // #145 [ref=1x] + E(F30F00,00,0,0,0,0,3,HV ), // #146 [ref=1x] + E(F20F00,00,0,0,0,0,4,FV ), // #147 [ref=1x] + E(F20F00,00,0,0,0,1,4,FV ), // #148 [ref=1x] + E(F20F00,00,0,0,0,0,2,T1W), // #149 [ref=1x] + E(F30F00,00,0,0,0,0,2,T1W), // #150 [ref=1x] + E(660F3A,00,0,0,0,0,4,FVM), // #151 [ref=5x] + E(660F38,00,0,2,0,1,4,FV ), // #152 [ref=3x] + E(660F38,00,0,2,0,0,4,FV ), // #153 [ref=3x] + V(660F3A,00,0,1,0,0,0,_ ), // #154 [ref=6x] + E(660F3A,00,0,0,0,0,4,T4 ), // #155 [ref=4x] + E(660F3A,00,0,2,0,0,5,T8 ), // #156 [ref=4x] + E(660F3A,00,0,0,0,1,4,T2 ), // #157 [ref=4x] + E(660F3A,00,0,2,0,1,5,T4 ), // #158 [ref=4x] + V(660F3A,00,0,0,0,0,2,T1S), // #159 [ref=4x] + E(660F3A,00,0,0,0,1,3,T1S), // #160 [ref=6x] + E(660F3A,00,0,0,0,0,2,T1S), // #161 [ref=6x] + V(660F38,00,0,0,1,1,4,FV ), // #162 [ref=20x] + V(660F38,00,0,0,0,0,4,FV ), // #163 [ref=32x] + V(660F38,00,0,0,1,1,3,T1S), // #164 [ref=12x] + V(660F38,00,0,0,1,0,0,_ ), // #165 [ref=5x] + E(660F38,00,1,2,0,1,3,T1S), // #166 [ref=2x] + E(660F38,00,1,2,0,0,2,T1S), // #167 [ref=2x] + E(660F38,00,2,2,0,1,3,T1S), // #168 [ref=2x] + E(660F38,00,2,2,0,0,2,T1S), // #169 [ref=2x] + V(660F3A,00,0,0,1,1,4,FV ), // #170 [ref=2x] + V(000F00,00,2,0,0,0,0,_ ), // #171 [ref=1x] + V(660F00,00,0,0,0,1,4,FVM), // #172 [ref=3x] + V(000F00,00,0,0,0,0,4,FVM), // #173 [ref=3x] + V(660F00,00,0,0,0,0,2,T1S), // #174 [ref=1x] + V(F20F00,00,0,0,0,1,3,DUP), // #175 [ref=1x] + E(660F00,00,0,0,0,0,4,FVM), // #176 [ref=1x] + E(660F00,00,0,0,0,1,4,FVM), // #177 [ref=1x] + V(F30F00,00,0,0,0,0,0,_ ), // #178 [ref=3x] + E(F20F00,00,0,0,0,1,4,FVM), // #179 [ref=1x] + E(F30F00,00,0,0,0,0,4,FVM), // #180 [ref=1x] + E(F30F00,00,0,0,0,1,4,FVM), // #181 [ref=1x] + E(F20F00,00,0,0,0,0,4,FVM), // #182 [ref=1x] + V(000F00,00,0,0,0,0,3,T2 ), // #183 [ref=2x] + V(660F00,00,0,0,0,0,4,FVM), // #184 [ref=33x] + V(F30F00,00,0,0,0,0,4,FVM), // #185 [ref=3x] + E(F20F38,00,0,0,0,0,4,FV ), // #186 [ref=1x] + E(F20F38,00,0,0,0,1,4,FV ), // #187 [ref=1x] + V(660F3A,00,0,0,0,0,4,FVM), // #188 [ref=2x] + E(660F00,00,0,0,0,0,4,FV ), // #189 [ref=5x] + V(660F38,00,0,0,0,0,0,T1S), // #190 [ref=1x] + E(F30F38,00,0,0,0,1,0,_ ), // #191 [ref=5x] + V(660F38,00,0,0,0,0,1,T1S), // #192 [ref=1x] + V(XOP_M8,00,0,0,0,0,0,_ ), // #193 [ref=22x] + V(660F38,00,0,0,0,1,4,FVM), // #194 [ref=2x] + E(660F3A,00,0,0,0,1,4,FVM), // #195 [ref=2x] + E(660F38,00,0,0,0,0,0,T1S), // #196 [ref=2x] + E(660F38,00,0,0,0,1,1,T1S), // #197 [ref=2x] + V(660F38,00,0,0,0,1,4,FV ), // #198 [ref=3x] + E(660F38,00,0,0,1,1,4,FV ), // #199 [ref=1x] + V(660F3A,00,0,0,0,0,0,T1S), // #200 [ref=2x] + V(660F3A,00,0,0,1,1,3,T1S), // #201 [ref=2x] + V(660F3A,00,0,0,0,0,1,T1S), // #202 [ref=1x] + V(660F00,00,0,0,0,0,1,T1S), // #203 [ref=1x] + E(F30F38,00,0,0,0,0,2,QVM), // #204 [ref=6x] + E(F30F38,00,0,0,0,0,3,HVM), // #205 [ref=9x] + E(F30F38,00,0,0,0,0,1,OVM), // #206 [ref=3x] + V(660F38,00,0,0,0,0,2,QVM), // #207 [ref=4x] + V(660F38,00,0,0,0,0,1,OVM), // #208 [ref=2x] + E(660F00,00,1,0,0,0,4,FV ), // #209 [ref=1x] + E(660F00,00,1,0,0,1,4,FV ), // #210 [ref=1x] + V(F20F00,00,0,0,0,0,4,FVM), // #211 [ref=1x] + V(660F00,00,0,0,0,0,4,128), // #212 [ref=5x] + V(660F00,00,7,0,0,0,4,FVM), // #213 [ref=1x] + V(660F00,00,0,0,0,1,4,128), // #214 [ref=2x] + E(660F00,00,0,0,0,1,4,128), // #215 [ref=1x] + V(660F00,00,3,0,0,0,4,FVM), // #216 [ref=1x] + E(F30F38,00,0,0,0,0,4,FVM), // #217 [ref=1x] + E(F30F38,00,0,0,0,0,4,FV ), // #218 [ref=1x] + E(F30F38,00,0,0,0,1,4,FV ), // #219 [ref=1x] + E(F30F38,00,0,0,0,1,4,FVM), // #220 [ref=1x] + E(660F38,00,5,2,0,1,3,T1S), // #221 [ref=2x] + E(660F38,00,5,2,0,0,2,T1S), // #222 [ref=2x] + E(660F38,00,6,2,0,1,3,T1S), // #223 [ref=2x] + E(660F38,00,6,2,0,0,2,T1S), // #224 [ref=2x] + V(000F00,00,3,0,0,0,0,_ ), // #225 [ref=1x] + O(F30F00,00,2,0,0,0,0,_ ), // #226 [ref=1x] + O(F30F00,00,3,0,0,0,0,_ ), // #227 [ref=1x] + O(000F38,00,0,0,1,0,0,_ ), // #228 [ref=1x] + O(660F38,00,0,0,1,0,0,_ ), // #229 [ref=1x] + O(000F00,00,5,0,1,0,0,_ ), // #230 [ref=2x] + O(000F00,00,3,0,1,0,0,_ ), // #231 [ref=1x] + O(000F00,00,4,0,1,0,0,_ ), // #232 [ref=2x] + O(000F00,00,6,0,1,0,0,_ ) // #233 [ref=1x] }; // ---------------------------------------------------------------------------- // ${MainOpcodeTable:End} @@ -1871,7 +1895,7 @@ const uint32_t InstDB::_mainOpcodeTable[] = { // ${AltOpcodeTable:Begin} // ------------------- Automatically generated, do not edit ------------------- const uint32_t InstDB::_altOpcodeTable[] = { - 0 , // #0 [ref=1386x] + 0 , // #0 [ref=1403x] O(660F00,1B,_,_,_,_,_,_ ), // #1 [ref=1x] O(000F00,BA,4,_,x,_,_,_ ), // #2 [ref=1x] O(000F00,BA,7,_,x,_,_,_ ), // #3 [ref=1x] @@ -2007,10 +2031,10 @@ const uint32_t InstDB::_altOpcodeTable[] = { // ---------------------------------------------------------------------------- // ${AltOpcodeTable:End} -#undef O_FPU #undef O #undef V #undef E +#undef O_FPU // ============================================================================ // [asmjit::x86::InstDB - CommonInfoTableA] @@ -2052,379 +2076,384 @@ const InstDB::CommonInfo InstDB::_commonInfoTable[] = { { 0 , 352, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #27 [ref=1x] { 0 , 353, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #28 [ref=2x] { 0 , 327, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #29 [ref=1x] - { 0 , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #30 [ref=80x] + { 0 , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #30 [ref=83x] { 0 , 354, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #31 [ref=24x] - { 0 , 355, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #32 [ref=1x] - { 0 , 16 , 12, CONTROL(None) , SINGLE_REG(None), 0 }, // #33 [ref=1x] - { F(Rep) , 356, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #34 [ref=1x] - { F(Vec) , 357, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #35 [ref=2x] - { F(Vec) , 358, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #36 [ref=3x] - { F(Lock)|F(XAcquire)|F(XRelease) , 118, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #37 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 359, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #38 [ref=1x] + { 0 , 355, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #32 [ref=6x] + { 0 , 356, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #33 [ref=1x] + { 0 , 16 , 12, CONTROL(None) , SINGLE_REG(None), 0 }, // #34 [ref=1x] + { F(Rep) , 357, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #35 [ref=1x] + { F(Vec) , 358, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #36 [ref=2x] + { F(Vec) , 359, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #37 [ref=3x] + { F(Lock)|F(XAcquire)|F(XRelease) , 118, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #38 [ref=1x] { F(Lock)|F(XAcquire)|F(XRelease) , 360, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #39 [ref=1x] - { 0 , 361, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #40 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 361, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #40 [ref=1x] { 0 , 362, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #41 [ref=1x] - { 0 , 252, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #42 [ref=1x] - { F(Mmx)|F(Vec) , 363, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #43 [ref=2x] + { 0 , 363, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #42 [ref=1x] + { 0 , 252, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #43 [ref=1x] { F(Mmx)|F(Vec) , 364, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #44 [ref=2x] { F(Mmx)|F(Vec) , 365, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #45 [ref=2x] - { F(Vec) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #46 [ref=2x] + { F(Mmx)|F(Vec) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #46 [ref=2x] { F(Vec) , 367, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #47 [ref=2x] { F(Vec) , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #48 [ref=2x] - { 0 , 369, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #49 [ref=1x] - { 0 , 370, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #50 [ref=2x] - { F(Lock)|F(XAcquire)|F(XRelease) , 254, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #51 [ref=2x] - { 0 , 39 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #52 [ref=3x] - { F(Mmx) , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #53 [ref=1x] - { 0 , 256, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #54 [ref=2x] - { 0 , 371, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #55 [ref=1x] - { F(Vec) , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #56 [ref=2x] - { F(Vec) , 258, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #57 [ref=1x] - { F(FpuM32)|F(FpuM64) , 153, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #58 [ref=6x] - { 0 , 260, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #59 [ref=9x] - { F(FpuM80) , 373, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #60 [ref=2x] - { 0 , 261, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #61 [ref=13x] - { F(FpuM32)|F(FpuM64) , 262, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #62 [ref=2x] - { F(FpuM16)|F(FpuM32) , 374, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #63 [ref=9x] - { F(FpuM16)|F(FpuM32)|F(FpuM64) , 375, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #64 [ref=3x] - { F(FpuM32)|F(FpuM64)|F(FpuM80) , 376, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #65 [ref=2x] - { F(FpuM16) , 377, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #66 [ref=3x] - { F(FpuM16) , 378, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #67 [ref=2x] - { F(FpuM32)|F(FpuM64) , 263, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #68 [ref=1x] - { 0 , 379, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #69 [ref=2x] - { 0 , 39 , 10, CONTROL(None) , SINGLE_REG(None), 0 }, // #70 [ref=1x] - { 0 , 380, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #71 [ref=1x] - { F(Rep) , 381, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #72 [ref=1x] - { F(Vec) , 264, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #73 [ref=1x] - { 0 , 382, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #74 [ref=2x] - { 0 , 383, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #75 [ref=8x] - { 0 , 266, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #76 [ref=3x] - { 0 , 268, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #77 [ref=1x] - { 0 , 260, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #78 [ref=3x] - { 0 , 384, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #79 [ref=1x] - { F(Rep)|F(RepIgnored) , 270, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #80 [ref=30x] - { F(Rep)|F(RepIgnored) , 272, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #81 [ref=1x] - { F(Rep)|F(RepIgnored) , 274, 2 , CONTROL(Jump) , SINGLE_REG(None), 0 }, // #82 [ref=1x] - { F(Vec)|F(Vex) , 385, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #83 [ref=27x] - { F(Vec)|F(Vex) , 276, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #84 [ref=1x] - { F(Vec)|F(Vex) , 278, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #85 [ref=1x] - { F(Vec)|F(Vex) , 280, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #86 [ref=1x] - { F(Vec)|F(Vex) , 282, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #87 [ref=1x] - { F(Vec)|F(Vex) , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #88 [ref=12x] - { F(Vec)|F(Vex) , 387, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #89 [ref=8x] - { 0 , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #90 [ref=2x] - { 0 , 284, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #91 [ref=1x] - { F(Vec) , 192, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #92 [ref=2x] - { 0 , 389, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #93 [ref=2x] - { 0 , 286, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #94 [ref=2x] - { F(Vex) , 390, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #95 [ref=2x] - { 0 , 391, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #96 [ref=1x] - { 0 , 156, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #97 [ref=3x] - { 0 , 392, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #98 [ref=5x] - { F(Vex) , 393, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #99 [ref=2x] - { F(Rep) , 394, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #100 [ref=1x] - { 0 , 272, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #101 [ref=3x] - { 0 , 288, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #102 [ref=1x] - { F(Vex) , 395, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #103 [ref=2x] - { F(Vec) , 396, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #104 [ref=1x] - { F(Mmx) , 397, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #105 [ref=1x] - { 0 , 398, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #106 [ref=2x] - { F(XRelease) , 0 , 16, CONTROL(None) , SINGLE_REG(None), 0 }, // #107 [ref=1x] - { F(Vec) , 70 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #108 [ref=6x] - { 0 , 64 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #109 [ref=1x] - { F(Mmx)|F(Vec) , 290, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #110 [ref=1x] - { 0 , 399, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #111 [ref=1x] - { 0 , 68 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #112 [ref=2x] - { F(Mmx)|F(Vec) , 400, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #113 [ref=1x] - { F(Vec) , 259, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #114 [ref=2x] - { F(Vec) , 198, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #115 [ref=4x] - { F(Vec) , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #116 [ref=2x] - { F(Vec) , 71 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #117 [ref=3x] - { F(Mmx) , 402, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #118 [ref=1x] - { F(Vec) , 98 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #119 [ref=1x] - { F(Vec) , 201, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #120 [ref=1x] - { F(Mmx)|F(Vec) , 94 , 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #121 [ref=1x] - { F(Mmx)|F(Vec) , 403, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #122 [ref=1x] - { F(Rep) , 404, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #123 [ref=1x] - { F(Vec) , 97 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #124 [ref=1x] - { F(Vec) , 292, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #125 [ref=1x] - { 0 , 294, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #126 [ref=2x] - { 0 , 296, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #127 [ref=1x] - { F(Vex) , 298, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #128 [ref=1x] - { 0 , 405, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #129 [ref=1x] - { 0 , 406, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #130 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 255, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #131 [ref=2x] - { 0 , 300, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #132 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(RO) , 0 }, // #133 [ref=1x] - { 0 , 407, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #134 [ref=1x] - { F(Rep) , 408, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #135 [ref=1x] - { F(Mmx)|F(Vec) , 302, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #136 [ref=40x] - { F(Mmx)|F(Vec) , 304, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #137 [ref=1x] - { F(Mmx)|F(Vec) , 302, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #138 [ref=6x] - { F(Mmx)|F(Vec) , 302, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #139 [ref=16x] - { F(Mmx) , 302, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #140 [ref=26x] - { F(Vec) , 70 , 1 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #141 [ref=4x] - { F(Vec) , 409, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #142 [ref=1x] - { F(Vec) , 410, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #143 [ref=1x] - { F(Vec) , 411, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #144 [ref=1x] - { F(Vec) , 412, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #145 [ref=1x] - { F(Vec) , 413, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #146 [ref=1x] - { F(Vec) , 414, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #147 [ref=1x] - { F(Mmx)|F(Vec) , 306, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #148 [ref=1x] + { F(Vec) , 369, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #49 [ref=2x] + { 0 , 370, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #50 [ref=1x] + { 0 , 371, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #51 [ref=2x] + { F(Lock)|F(XAcquire)|F(XRelease) , 254, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #52 [ref=2x] + { 0 , 39 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #53 [ref=3x] + { F(Mmx) , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #54 [ref=1x] + { 0 , 256, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #55 [ref=2x] + { 0 , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #56 [ref=1x] + { F(Vec) , 373, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #57 [ref=2x] + { F(Vec) , 258, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #58 [ref=1x] + { F(FpuM32)|F(FpuM64) , 153, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #59 [ref=6x] + { 0 , 260, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #60 [ref=9x] + { F(FpuM80) , 374, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #61 [ref=2x] + { 0 , 261, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #62 [ref=13x] + { F(FpuM32)|F(FpuM64) , 262, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #63 [ref=2x] + { F(FpuM16)|F(FpuM32) , 375, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #64 [ref=9x] + { F(FpuM16)|F(FpuM32)|F(FpuM64) , 376, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #65 [ref=3x] + { F(FpuM32)|F(FpuM64)|F(FpuM80) , 377, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #66 [ref=2x] + { F(FpuM16) , 378, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #67 [ref=3x] + { F(FpuM16) , 379, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #68 [ref=2x] + { F(FpuM32)|F(FpuM64) , 263, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #69 [ref=1x] + { 0 , 380, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #70 [ref=2x] + { 0 , 39 , 10, CONTROL(None) , SINGLE_REG(None), 0 }, // #71 [ref=1x] + { 0 , 381, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #72 [ref=1x] + { 0 , 382, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #73 [ref=2x] + { 0 , 311, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #74 [ref=2x] + { F(Rep) , 383, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #75 [ref=1x] + { F(Vec) , 264, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #76 [ref=1x] + { 0 , 384, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #77 [ref=2x] + { 0 , 385, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #78 [ref=8x] + { 0 , 266, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #79 [ref=3x] + { 0 , 268, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #80 [ref=1x] + { 0 , 260, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #81 [ref=3x] + { 0 , 386, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #82 [ref=1x] + { F(Rep)|F(RepIgnored) , 270, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #83 [ref=30x] + { F(Rep)|F(RepIgnored) , 272, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #84 [ref=1x] + { F(Rep)|F(RepIgnored) , 274, 2 , CONTROL(Jump) , SINGLE_REG(None), 0 }, // #85 [ref=1x] + { F(Vec)|F(Vex) , 387, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #86 [ref=27x] + { F(Vec)|F(Vex) , 276, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #87 [ref=1x] + { F(Vec)|F(Vex) , 278, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #88 [ref=1x] + { F(Vec)|F(Vex) , 280, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #89 [ref=1x] + { F(Vec)|F(Vex) , 282, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #90 [ref=1x] + { F(Vec)|F(Vex) , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #91 [ref=12x] + { F(Vec)|F(Vex) , 389, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #92 [ref=8x] + { 0 , 390, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #93 [ref=2x] + { 0 , 284, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #94 [ref=1x] + { F(Vec) , 192, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #95 [ref=2x] + { 0 , 391, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #96 [ref=2x] + { 0 , 286, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #97 [ref=2x] + { F(Vex) , 392, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #98 [ref=2x] + { 0 , 393, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #99 [ref=1x] + { 0 , 156, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #100 [ref=3x] + { 0 , 394, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #101 [ref=5x] + { F(Vex) , 395, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #102 [ref=2x] + { F(Rep) , 396, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #103 [ref=1x] + { 0 , 272, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #104 [ref=3x] + { 0 , 288, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #105 [ref=1x] + { F(Vex) , 397, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #106 [ref=2x] + { F(Vec) , 398, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #107 [ref=1x] + { F(Mmx) , 399, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #108 [ref=1x] + { 0 , 400, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #109 [ref=2x] + { F(XRelease) , 0 , 16, CONTROL(None) , SINGLE_REG(None), 0 }, // #110 [ref=1x] + { F(Vec) , 70 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #111 [ref=6x] + { 0 , 64 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #112 [ref=1x] + { F(Mmx)|F(Vec) , 290, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #113 [ref=1x] + { 0 , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #114 [ref=1x] + { 0 , 68 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #115 [ref=2x] + { F(Mmx)|F(Vec) , 402, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #116 [ref=1x] + { F(Vec) , 259, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #117 [ref=2x] + { F(Vec) , 198, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #118 [ref=4x] + { F(Vec) , 403, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #119 [ref=2x] + { F(Vec) , 71 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #120 [ref=3x] + { F(Mmx) , 404, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #121 [ref=1x] + { F(Vec) , 98 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #122 [ref=1x] + { F(Vec) , 201, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #123 [ref=1x] + { F(Mmx)|F(Vec) , 94 , 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #124 [ref=1x] + { F(Mmx)|F(Vec) , 405, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #125 [ref=1x] + { F(Rep) , 406, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #126 [ref=1x] + { F(Vec) , 97 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #127 [ref=1x] + { F(Vec) , 292, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #128 [ref=1x] + { 0 , 294, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #129 [ref=2x] + { 0 , 296, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #130 [ref=1x] + { F(Vex) , 298, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #131 [ref=1x] + { 0 , 407, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #132 [ref=1x] + { 0 , 408, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #133 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 255, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #134 [ref=2x] + { 0 , 300, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #135 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(RO) , 0 }, // #136 [ref=1x] + { 0 , 409, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #137 [ref=1x] + { F(Rep) , 410, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #138 [ref=1x] + { F(Mmx)|F(Vec) , 302, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #139 [ref=40x] + { F(Mmx)|F(Vec) , 304, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #140 [ref=1x] + { F(Mmx)|F(Vec) , 302, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #141 [ref=6x] + { F(Mmx)|F(Vec) , 302, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #142 [ref=16x] + { F(Mmx) , 302, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #143 [ref=26x] + { F(Vec) , 70 , 1 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #144 [ref=4x] + { F(Vec) , 411, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #145 [ref=1x] + { F(Vec) , 412, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #146 [ref=1x] + { F(Vec) , 413, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #147 [ref=1x] + { F(Vec) , 414, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #148 [ref=1x] { F(Vec) , 415, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #149 [ref=1x] { F(Vec) , 416, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #150 [ref=1x] - { F(Vec) , 417, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #151 [ref=1x] - { F(Mmx)|F(Vec) , 418, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #152 [ref=1x] - { F(Mmx)|F(Vec) , 419, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #153 [ref=1x] - { F(Vec) , 228, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #154 [ref=2x] - { 0 , 122, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #155 [ref=1x] - { 0 , 384, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #156 [ref=9x] - { F(Mmx) , 304, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #157 [ref=1x] - { F(Mmx)|F(Vec) , 308, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #158 [ref=8x] - { F(Vec) , 420, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #159 [ref=2x] - { 0 , 126, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #160 [ref=1x] - { 0 , 421, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #161 [ref=8x] - { 0 , 422, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #162 [ref=4x] - { 0 , 423, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #163 [ref=6x] - { 0 , 310, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #164 [ref=1x] - { 0 , 424, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #165 [ref=1x] - { F(Rep)|F(RepIgnored) , 312, 2 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #166 [ref=1x] - { F(Vex) , 314, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #167 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(WO) , 0 }, // #168 [ref=3x] - { F(Rep) , 425, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #169 [ref=1x] - { 0 , 426, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #170 [ref=30x] - { 0 , 159, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #171 [ref=2x] - { 0 , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #172 [ref=3x] - { F(Rep) , 428, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #173 [ref=1x] - { F(Vex) , 429, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #174 [ref=5x] - { 0 , 57 , 7 , CONTROL(None) , SINGLE_REG(None), 0 }, // #175 [ref=1x] - { F(Tsib)|F(Vex) , 430, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #176 [ref=2x] - { F(Vex) , 384, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #177 [ref=1x] - { F(Tsib)|F(Vex) , 431, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #178 [ref=1x] - { F(Vex) , 432, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #179 [ref=1x] - { 0 , 433, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #180 [ref=2x] - { 0 , 434, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #181 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 435, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #182 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 436, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #183 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #184 [ref=22x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #185 [ref=22x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #186 [ref=18x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #187 [ref=17x] - { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #188 [ref=15x] - { F(Vec)|F(Vex)|F(Evex) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #189 [ref=5x] - { F(Vec)|F(Vex) , 70 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #190 [ref=17x] - { F(Vec)|F(Vex) , 183, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #191 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #192 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #193 [ref=4x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #194 [ref=10x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #195 [ref=12x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #196 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #197 [ref=6x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #198 [ref=13x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #199 [ref=16x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #200 [ref=19x] - { F(Vec)|F(Vex) , 165, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #201 [ref=6x] - { F(Vec)|F(Vex) , 316, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #202 [ref=3x] - { F(Vec)|F(Vex) , 439, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #203 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #204 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #205 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 442, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #206 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #207 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #208 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #209 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 168, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #210 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 168, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #211 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 445, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #212 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 446, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #213 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #214 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 225, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #215 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 171, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #216 [ref=6x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #217 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #218 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #219 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #220 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #221 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #222 [ref=3x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #223 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #224 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 180, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #225 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #226 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #227 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #228 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #229 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 447, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #230 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #231 [ref=3x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #232 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #233 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #234 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #235 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #236 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #237 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #238 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #239 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #240 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512SAE) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #241 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #242 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512SAE) , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #243 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #244 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 447, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #245 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #246 [ref=3x] - { F(Vec)|F(Vex) , 165, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #247 [ref=9x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 74 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #248 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 74 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #249 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #250 [ref=9x] - { F(Vec)|F(Vex) , 181, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #251 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 448, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #252 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 182, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #253 [ref=4x] - { F(Vec)|F(Vex)|F(Evex) , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #254 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #255 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #256 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 449, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #257 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #258 [ref=4x] - { F(Vec)|F(Vex) , 130, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #259 [ref=13x] - { F(Vec)|F(Vex) , 320, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #260 [ref=4x] - { F(Vec)|F(Vex) , 322, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #261 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512K_B64) , 451, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #262 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512K_B32) , 451, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #263 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512K) , 452, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #264 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512K) , 453, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #265 [ref=1x] - { F(Vec)|F(Vex) , 177, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #266 [ref=7x] - { F(Vec)|F(Vex) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #267 [ref=1x] - { F(Vec)|F(Vex) , 225, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #268 [ref=1x] - { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 99 , 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #269 [ref=2x] - { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 104, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #270 [ref=2x] - { F(Vsib)|F(Evex)|F(Avx512K) , 454, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #271 [ref=4x] - { F(Vsib)|F(Evex)|F(Avx512K) , 455, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #272 [ref=4x] - { F(Vsib)|F(Evex)|F(Avx512K) , 456, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #273 [ref=8x] - { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 109, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #274 [ref=2x] - { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 134, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #275 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #276 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #277 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #278 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #279 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #280 [ref=3x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #281 [ref=22x] - { F(Vec)|F(Vex) , 324, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #282 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 324, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #283 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 457, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #284 [ref=4x] - { F(Vec)|F(Vex)|F(Evex) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #285 [ref=1x] - { F(Vec)|F(Vex) , 192, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #286 [ref=1x] - { F(Vex) , 389, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #287 [ref=2x] - { F(Vec)|F(Vex) , 396, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #288 [ref=1x] - { F(Vec)|F(Vex) , 138, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #289 [ref=4x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #290 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #291 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #292 [ref=2x] - { 0 , 458, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #293 [ref=4x] - { 0 , 326, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #294 [ref=3x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 70 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #295 [ref=4x] - { F(Vec)|F(Vex)|F(Evex) , 328, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #296 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #297 [ref=1x] - { F(Vec)|F(Vex) , 70 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #298 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 70 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #299 [ref=6x] - { F(Vec)|F(Vex)|F(Evex) , 200, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #300 [ref=2x] - { F(Vec)|F(Vex)|F(Evex) , 330, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #301 [ref=4x] - { F(Vec)|F(Vex) , 459, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #302 [ref=3x] - { F(Vec)|F(Vex)|F(Evex) , 189, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #303 [ref=3x] - { F(Vec)|F(Vex)|F(Evex) , 192, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #304 [ref=1x] - { F(Vec)|F(Vex)|F(Evex) , 195, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #305 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #306 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #307 [ref=5x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 201, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #308 [ref=1x] - { 0 , 332, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #309 [ref=1x] - { 0 , 334, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #310 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512B32) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #311 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512B64) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #312 [ref=1x] - { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #313 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #314 [ref=2x] - { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #315 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #316 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #317 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #318 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #319 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 461, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #320 [ref=1x] - { F(Vec)|F(Evex) , 462, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #321 [ref=6x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 207, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #322 [ref=1x] + { F(Mmx)|F(Vec) , 306, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #151 [ref=1x] + { F(Vec) , 417, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #152 [ref=1x] + { F(Vec) , 418, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #153 [ref=1x] + { F(Vec) , 419, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #154 [ref=1x] + { F(Mmx)|F(Vec) , 420, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #155 [ref=1x] + { F(Mmx)|F(Vec) , 421, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #156 [ref=1x] + { F(Vec) , 228, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #157 [ref=2x] + { 0 , 122, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #158 [ref=1x] + { 0 , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #159 [ref=9x] + { F(Mmx) , 304, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #160 [ref=1x] + { F(Mmx)|F(Vec) , 308, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #161 [ref=8x] + { F(Vec) , 422, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #162 [ref=2x] + { 0 , 423, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #163 [ref=1x] + { 0 , 126, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #164 [ref=1x] + { 0 , 424, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #165 [ref=8x] + { 0 , 425, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #166 [ref=4x] + { 0 , 426, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #167 [ref=8x] + { 0 , 310, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #168 [ref=1x] + { F(Rep)|F(RepIgnored) , 312, 2 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #169 [ref=1x] + { F(Vex) , 314, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #170 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(WO) , 0 }, // #171 [ref=3x] + { F(Rep) , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #172 [ref=1x] + { 0 , 428, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #173 [ref=30x] + { 0 , 159, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #174 [ref=2x] + { 0 , 429, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #175 [ref=3x] + { F(Rep) , 430, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #176 [ref=1x] + { F(Vex) , 431, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #177 [ref=5x] + { 0 , 57 , 7 , CONTROL(None) , SINGLE_REG(None), 0 }, // #178 [ref=1x] + { F(Tsib)|F(Vex) , 432, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #179 [ref=2x] + { F(Vex) , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #180 [ref=1x] + { F(Tsib)|F(Vex) , 433, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #181 [ref=1x] + { F(Vex) , 434, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #182 [ref=1x] + { 0 , 435, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #183 [ref=2x] + { 0 , 436, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #184 [ref=2x] + { 0 , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #185 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #186 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 439, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #187 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #188 [ref=22x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #189 [ref=22x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #190 [ref=18x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #191 [ref=17x] + { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #192 [ref=15x] + { F(Vec)|F(Vex)|F(Evex) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #193 [ref=5x] + { F(Vec)|F(Vex) , 70 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #194 [ref=17x] + { F(Vec)|F(Vex) , 183, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #195 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #196 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #197 [ref=4x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #198 [ref=10x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #199 [ref=12x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #200 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #201 [ref=6x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #202 [ref=13x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #203 [ref=16x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #204 [ref=19x] + { F(Vec)|F(Vex) , 165, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #205 [ref=6x] + { F(Vec)|F(Vex) , 316, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #206 [ref=3x] + { F(Vec)|F(Vex) , 442, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #207 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #208 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #209 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 445, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #210 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 446, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #211 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #212 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 447, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #213 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 168, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #214 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 168, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #215 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 448, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #216 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 449, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #217 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #218 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 225, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #219 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 171, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #220 [ref=6x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #221 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #222 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #223 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #224 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #225 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #226 [ref=3x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #227 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #228 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 180, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #229 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #230 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #231 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 367, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #232 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 367, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #233 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #234 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #235 [ref=3x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 369, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #236 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 369, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #237 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #238 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #239 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 318, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #240 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #241 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #242 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #243 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 367, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #244 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512SAE) , 367, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #245 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 369, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #246 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512SAE) , 369, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #247 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #248 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #249 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #250 [ref=3x] + { F(Vec)|F(Vex) , 165, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #251 [ref=9x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 74 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #252 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 74 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #253 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #254 [ref=9x] + { F(Vec)|F(Vex) , 181, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #255 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 451, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #256 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 182, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #257 [ref=4x] + { F(Vec)|F(Vex)|F(Evex) , 373, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #258 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #259 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #260 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 452, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #261 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 453, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #262 [ref=4x] + { F(Vec)|F(Vex) , 130, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #263 [ref=13x] + { F(Vec)|F(Vex) , 320, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #264 [ref=4x] + { F(Vec)|F(Vex) , 322, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #265 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512K_B64) , 454, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #266 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512K_B32) , 454, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #267 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512K) , 455, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #268 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512K) , 456, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #269 [ref=1x] + { F(Vec)|F(Vex) , 177, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #270 [ref=7x] + { F(Vec)|F(Vex) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #271 [ref=1x] + { F(Vec)|F(Vex) , 225, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #272 [ref=1x] + { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 99 , 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #273 [ref=2x] + { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 104, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #274 [ref=2x] + { F(Vsib)|F(Evex)|F(Avx512K) , 457, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #275 [ref=4x] + { F(Vsib)|F(Evex)|F(Avx512K) , 458, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #276 [ref=4x] + { F(Vsib)|F(Evex)|F(Avx512K) , 459, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #277 [ref=8x] + { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 109, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #278 [ref=2x] + { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 134, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #279 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #280 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #281 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #282 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #283 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #284 [ref=3x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #285 [ref=22x] + { F(Vec)|F(Vex) , 324, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #286 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 324, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #287 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #288 [ref=4x] + { F(Vec)|F(Vex)|F(Evex) , 453, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #289 [ref=1x] + { F(Vec)|F(Vex) , 192, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #290 [ref=1x] + { F(Vex) , 391, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #291 [ref=2x] + { F(Vec)|F(Vex) , 398, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #292 [ref=1x] + { F(Vec)|F(Vex) , 138, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #293 [ref=4x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #294 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #295 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #296 [ref=2x] + { 0 , 326, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #297 [ref=3x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 70 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #298 [ref=4x] + { F(Vec)|F(Vex)|F(Evex) , 328, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #299 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #300 [ref=1x] + { F(Vec)|F(Vex) , 70 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #301 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 70 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #302 [ref=6x] + { F(Vec)|F(Vex)|F(Evex) , 200, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #303 [ref=2x] + { F(Vec)|F(Vex)|F(Evex) , 330, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #304 [ref=4x] + { F(Vec)|F(Vex) , 461, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #305 [ref=3x] + { F(Vec)|F(Vex)|F(Evex) , 189, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #306 [ref=3x] + { F(Vec)|F(Vex)|F(Evex) , 192, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #307 [ref=1x] + { F(Vec)|F(Vex)|F(Evex) , 195, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #308 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #309 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #310 [ref=5x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 201, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #311 [ref=1x] + { 0 , 332, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #312 [ref=1x] + { 0 , 334, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #313 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512B32) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #314 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512B64) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #315 [ref=1x] + { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #316 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #317 [ref=2x] + { F(Vec)|F(Vex) , 162, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #318 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #319 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #320 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #321 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 462, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #322 [ref=1x] { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 463, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #323 [ref=1x] - { F(Vec)|F(Vex)|F(Evex) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #324 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512K) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #325 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512K_B32) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #326 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512K) , 213, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #327 [ref=4x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B32) , 213, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #328 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B64) , 213, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #329 [ref=2x] - { F(Vec)|F(Vex) , 409, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #330 [ref=1x] - { F(Vec)|F(Vex) , 410, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #331 [ref=1x] - { F(Vec)|F(Vex) , 411, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #332 [ref=1x] - { F(Vec)|F(Vex) , 412, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #333 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512K_B64) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #334 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #335 [ref=6x] - { F(Vec)|F(Vex) , 166, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #336 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 163, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #337 [ref=2x] - { F(Vec)|F(Vex) , 142, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #338 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 76 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #339 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 146, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #340 [ref=2x] - { F(Vec)|F(Vex)|F(Evex) , 413, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #341 [ref=1x] - { F(Vec)|F(Vex)|F(Evex) , 414, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #342 [ref=1x] - { F(Vec)|F(Vex)|F(Evex) , 464, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #343 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 465, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #344 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 466, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #345 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 467, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #346 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 468, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #347 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #348 [ref=4x] - { F(Vec)|F(Vex) , 316, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #349 [ref=12x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #350 [ref=8x] - { F(Vec)|F(Evex) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #351 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 216, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #352 [ref=6x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 219, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #353 [ref=9x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 222, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #354 [ref=3x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 225, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #355 [ref=4x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 228, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #356 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #357 [ref=6x] - { F(Vec)|F(Vex) , 130, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #358 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #359 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #360 [ref=3x] - { F(Vec)|F(Vex) , 336, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #361 [ref=4x] - { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 231, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #362 [ref=3x] - { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 338, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #363 [ref=2x] - { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 234, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #364 [ref=2x] - { F(Vec)|F(Vex) , 340, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #365 [ref=8x] - { F(Vec)|F(Evex)|F(Avx512K) , 237, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #366 [ref=5x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #367 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #368 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #369 [ref=3x] - { F(Vec)|F(Vex)|F(Evex) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #370 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #371 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #372 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 88 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #373 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #374 [ref=6x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #375 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #376 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512K_B32) , 237, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #377 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512K_B64) , 237, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #378 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #379 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #380 [ref=2x] - { F(Vec)|F(Vex) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #381 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 449, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #382 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #383 [ref=1x] - { F(Vec)|F(Vex) , 183, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #384 [ref=2x] - { F(Vec)|F(Vex) , 449, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #385 [ref=1x] - { F(Vec)|F(Vex) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #386 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #387 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #388 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #389 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #390 [ref=1x] - { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 342, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #391 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 166, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #392 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 166, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #393 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #394 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #395 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #396 [ref=1x] - { F(Vec)|F(Vex) , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #397 [ref=2x] - { F(Lock)|F(XAcquire)|F(XRelease) , 49 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #398 [ref=1x] - { 0 , 470, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #399 [ref=1x] - { F(Lock)|F(XAcquire) , 49 , 8 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #400 [ref=1x] - { 0 , 471, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #401 [ref=6x] - { 0 , 472, 1 , CONTROL(None) , SINGLE_REG(None), 0 } // #402 [ref=6x] + { F(Vec)|F(Evex) , 464, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #324 [ref=6x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 207, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #325 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 465, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #326 [ref=1x] + { F(Vec)|F(Vex)|F(Evex) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #327 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512K) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #328 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512K_B32) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #329 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512K) , 213, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #330 [ref=4x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B32) , 213, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #331 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B64) , 213, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #332 [ref=2x] + { F(Vec)|F(Vex) , 411, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #333 [ref=1x] + { F(Vec)|F(Vex) , 412, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #334 [ref=1x] + { F(Vec)|F(Vex) , 413, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #335 [ref=1x] + { F(Vec)|F(Vex) , 414, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #336 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512K_B64) , 210, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #337 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #338 [ref=6x] + { F(Vec)|F(Vex) , 166, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #339 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 163, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #340 [ref=2x] + { F(Vec)|F(Vex) , 142, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #341 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 76 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #342 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 146, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #343 [ref=2x] + { F(Vec)|F(Vex)|F(Evex) , 415, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #344 [ref=1x] + { F(Vec)|F(Vex)|F(Evex) , 416, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #345 [ref=1x] + { F(Vec)|F(Vex)|F(Evex) , 466, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #346 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 467, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #347 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 468, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #348 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #349 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 470, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #350 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #351 [ref=4x] + { F(Vec)|F(Vex) , 316, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #352 [ref=12x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #353 [ref=8x] + { F(Vec)|F(Evex) , 471, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #354 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 216, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #355 [ref=6x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 219, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #356 [ref=9x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 222, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #357 [ref=3x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 225, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #358 [ref=4x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 228, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #359 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #360 [ref=6x] + { F(Vec)|F(Vex) , 130, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #361 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #362 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #363 [ref=3x] + { F(Vec)|F(Vex) , 336, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #364 [ref=4x] + { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 231, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #365 [ref=3x] + { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 338, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #366 [ref=2x] + { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 234, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #367 [ref=2x] + { F(Vec)|F(Vex) , 340, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #368 [ref=8x] + { F(Vec)|F(Evex)|F(Avx512K) , 237, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #369 [ref=5x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #370 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #371 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #372 [ref=3x] + { F(Vec)|F(Vex)|F(Evex) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #373 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #374 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #375 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 88 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #376 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #377 [ref=6x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #378 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #379 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512K_B32) , 237, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #380 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512K_B64) , 237, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #381 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #382 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #383 [ref=2x] + { F(Vec)|F(Vex) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #384 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 452, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #385 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 453, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #386 [ref=1x] + { F(Vec)|F(Vex) , 183, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #387 [ref=2x] + { F(Vec)|F(Vex) , 452, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #388 [ref=1x] + { F(Vec)|F(Vex) , 453, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #389 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #390 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 162, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #391 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #392 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #393 [ref=1x] + { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 342, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #394 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 166, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #395 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 166, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #396 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #397 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 165, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #398 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #399 [ref=1x] + { F(Vec)|F(Vex) , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #400 [ref=2x] + { 0 , 23 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #401 [ref=2x] + { 0 , 52 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #402 [ref=2x] + { F(Lock)|F(XAcquire)|F(XRelease) , 49 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #403 [ref=1x] + { 0 , 472, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #404 [ref=1x] + { F(Lock)|F(XAcquire) , 49 , 8 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #405 [ref=1x] + { 0 , 473, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #406 [ref=6x] + { 0 , 474, 1 , CONTROL(None) , SINGLE_REG(None), 0 } // #407 [ref=6x] }; #undef SINGLE_REG #undef CONTROL @@ -2440,7 +2469,7 @@ const InstDB::CommonInfo InstDB::_commonInfoTable[] = { // ------------------- Automatically generated, do not edit ------------------- #define EXT(VAL) uint32_t(Features::k##VAL) const InstDB::CommonInfoTableB InstDB::_commonInfoTableB[] = { - { { 0 }, 0, 0 }, // #0 [ref=144x] + { { 0 }, 0, 0 }, // #0 [ref=146x] { { 0 }, 1, 0 }, // #1 [ref=32x] { { 0 }, 2, 0 }, // #2 [ref=2x] { { EXT(ADX) }, 3, 0 }, // #3 [ref=1x] @@ -2464,152 +2493,156 @@ const InstDB::CommonInfoTableB InstDB::_commonInfoTableB[] = { { { EXT(CLFLUSHOPT) }, 0, 0 }, // #21 [ref=1x] { { EXT(SVM) }, 0, 0 }, // #22 [ref=6x] { { 0 }, 10, 0 }, // #23 [ref=2x] - { { EXT(CLWB) }, 0, 0 }, // #24 [ref=1x] - { { EXT(CLZERO) }, 0, 0 }, // #25 [ref=1x] - { { 0 }, 3, 0 }, // #26 [ref=1x] - { { EXT(CMOV) }, 11, 0 }, // #27 [ref=6x] - { { EXT(CMOV) }, 12, 0 }, // #28 [ref=8x] - { { EXT(CMOV) }, 13, 0 }, // #29 [ref=6x] - { { EXT(CMOV) }, 14, 0 }, // #30 [ref=4x] - { { EXT(CMOV) }, 15, 0 }, // #31 [ref=4x] - { { EXT(CMOV) }, 16, 0 }, // #32 [ref=2x] - { { EXT(CMOV) }, 17, 0 }, // #33 [ref=6x] - { { EXT(CMOV) }, 18, 0 }, // #34 [ref=2x] - { { 0 }, 19, 0 }, // #35 [ref=2x] - { { EXT(I486) }, 1, 0 }, // #36 [ref=2x] - { { EXT(CMPXCHG16B) }, 5, 0 }, // #37 [ref=1x] - { { EXT(CMPXCHG8B) }, 5, 0 }, // #38 [ref=1x] - { { EXT(SSE2) }, 1, 0 }, // #39 [ref=2x] - { { EXT(SSE) }, 1, 0 }, // #40 [ref=2x] - { { EXT(I486) }, 0, 0 }, // #41 [ref=4x] - { { EXT(SSE4_2) }, 0, 0 }, // #42 [ref=2x] - { { 0 }, 20, 0 }, // #43 [ref=2x] - { { EXT(MMX) }, 0, 0 }, // #44 [ref=1x] - { { EXT(ENQCMD) }, 0, 0 }, // #45 [ref=2x] - { { EXT(SSE4A) }, 0, 0 }, // #46 [ref=4x] - { { 0 }, 21, 0 }, // #47 [ref=4x] - { { EXT(3DNOW) }, 0, 0 }, // #48 [ref=21x] - { { EXT(FXSR) }, 0, 0 }, // #49 [ref=4x] - { { EXT(SMX) }, 0, 0 }, // #50 [ref=1x] - { { EXT(GFNI) }, 0, 0 }, // #51 [ref=3x] - { { 0 }, 16, 0 }, // #52 [ref=5x] - { { EXT(VMX) }, 0, 0 }, // #53 [ref=12x] - { { 0 }, 11, 0 }, // #54 [ref=8x] - { { 0 }, 12, 0 }, // #55 [ref=12x] - { { 0 }, 13, 0 }, // #56 [ref=10x] - { { 0 }, 14, 0 }, // #57 [ref=8x] - { { 0 }, 15, 0 }, // #58 [ref=8x] - { { 0 }, 17, 0 }, // #59 [ref=8x] - { { 0 }, 18, 0 }, // #60 [ref=4x] - { { EXT(AVX512_DQ) }, 0, 0 }, // #61 [ref=23x] - { { EXT(AVX512_BW) }, 0, 0 }, // #62 [ref=22x] - { { EXT(AVX512_F) }, 0, 0 }, // #63 [ref=37x] - { { EXT(AVX512_DQ) }, 1, 0 }, // #64 [ref=3x] - { { EXT(AVX512_BW) }, 1, 0 }, // #65 [ref=4x] - { { EXT(AVX512_F) }, 1, 0 }, // #66 [ref=1x] - { { EXT(LAHFSAHF) }, 22, 0 }, // #67 [ref=1x] - { { EXT(AMX_TILE) }, 0, 0 }, // #68 [ref=7x] - { { EXT(LWP) }, 0, 0 }, // #69 [ref=4x] - { { 0 }, 23, 0 }, // #70 [ref=3x] - { { EXT(LZCNT) }, 1, 0 }, // #71 [ref=1x] - { { EXT(MMX2) }, 0, 0 }, // #72 [ref=8x] - { { EXT(MCOMMIT) }, 1, 0 }, // #73 [ref=1x] - { { EXT(MONITOR) }, 0, 0 }, // #74 [ref=2x] - { { EXT(MONITORX) }, 0, 0 }, // #75 [ref=2x] - { { EXT(MOVBE) }, 0, 0 }, // #76 [ref=1x] - { { EXT(MMX), EXT(SSE2) }, 0, 0 }, // #77 [ref=46x] - { { EXT(MOVDIR64B) }, 0, 0 }, // #78 [ref=1x] - { { EXT(MOVDIRI) }, 0, 0 }, // #79 [ref=1x] - { { EXT(BMI2) }, 0, 0 }, // #80 [ref=7x] - { { EXT(SSSE3) }, 0, 0 }, // #81 [ref=15x] - { { EXT(MMX2), EXT(SSE2) }, 0, 0 }, // #82 [ref=10x] - { { EXT(PCLMULQDQ) }, 0, 0 }, // #83 [ref=1x] - { { EXT(SSE4_2) }, 1, 0 }, // #84 [ref=4x] - { { EXT(PCOMMIT) }, 0, 0 }, // #85 [ref=1x] - { { EXT(PCONFIG) }, 0, 0 }, // #86 [ref=1x] - { { EXT(MMX2), EXT(SSE2), EXT(SSE4_1) }, 0, 0 }, // #87 [ref=1x] - { { EXT(3DNOW2) }, 0, 0 }, // #88 [ref=5x] - { { EXT(GEODE) }, 0, 0 }, // #89 [ref=2x] - { { EXT(POPCNT) }, 1, 0 }, // #90 [ref=1x] - { { 0 }, 24, 0 }, // #91 [ref=3x] - { { EXT(PREFETCHW) }, 1, 0 }, // #92 [ref=1x] - { { EXT(PREFETCHWT1) }, 1, 0 }, // #93 [ref=1x] - { { EXT(SNP) }, 20, 0 }, // #94 [ref=3x] - { { EXT(SSE4_1) }, 1, 0 }, // #95 [ref=1x] - { { 0 }, 25, 0 }, // #96 [ref=3x] - { { EXT(SNP) }, 1, 0 }, // #97 [ref=1x] - { { 0 }, 26, 0 }, // #98 [ref=2x] - { { EXT(FSGSBASE) }, 0, 0 }, // #99 [ref=4x] - { { EXT(MSR) }, 0, 0 }, // #100 [ref=2x] - { { EXT(RDPID) }, 0, 0 }, // #101 [ref=1x] - { { EXT(RDPRU) }, 0, 0 }, // #102 [ref=1x] - { { EXT(RDRAND) }, 1, 0 }, // #103 [ref=1x] - { { EXT(RDSEED) }, 1, 0 }, // #104 [ref=1x] - { { EXT(RDTSC) }, 0, 0 }, // #105 [ref=1x] - { { EXT(RDTSCP) }, 0, 0 }, // #106 [ref=1x] - { { 0 }, 27, 0 }, // #107 [ref=2x] - { { EXT(LAHFSAHF) }, 28, 0 }, // #108 [ref=1x] - { { EXT(SERIALIZE) }, 0, 0 }, // #109 [ref=1x] - { { EXT(SHA) }, 0, 0 }, // #110 [ref=7x] - { { EXT(SKINIT) }, 0, 0 }, // #111 [ref=2x] - { { EXT(AMX_BF16) }, 0, 0 }, // #112 [ref=1x] - { { EXT(AMX_INT8) }, 0, 0 }, // #113 [ref=4x] - { { EXT(WAITPKG) }, 1, 0 }, // #114 [ref=2x] - { { EXT(WAITPKG) }, 0, 0 }, // #115 [ref=1x] - { { EXT(AVX512_4FMAPS) }, 0, 0 }, // #116 [ref=4x] - { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #117 [ref=46x] - { { EXT(AVX), EXT(AVX512_F) }, 0, 0 }, // #118 [ref=32x] - { { EXT(AVX) }, 0, 0 }, // #119 [ref=37x] - { { EXT(AESNI), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(VAES) }, 0, 0 }, // #120 [ref=4x] - { { EXT(AESNI), EXT(AVX) }, 0, 0 }, // #121 [ref=2x] - { { EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #122 [ref=112x] - { { EXT(AVX), EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #123 [ref=8x] - { { EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #124 [ref=26x] - { { EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #125 [ref=30x] - { { EXT(AVX2) }, 0, 0 }, // #126 [ref=7x] - { { EXT(AVX), EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #127 [ref=39x] - { { EXT(AVX), EXT(AVX512_F) }, 1, 0 }, // #128 [ref=4x] - { { EXT(AVX512_BF16), EXT(AVX512_VL) }, 0, 0 }, // #129 [ref=3x] - { { EXT(AVX512_F), EXT(AVX512_VL), EXT(F16C) }, 0, 0 }, // #130 [ref=2x] - { { EXT(AVX512_ERI) }, 0, 0 }, // #131 [ref=10x] - { { EXT(AVX512_F), EXT(AVX512_VL), EXT(FMA) }, 0, 0 }, // #132 [ref=36x] - { { EXT(AVX512_F), EXT(FMA) }, 0, 0 }, // #133 [ref=24x] - { { EXT(FMA4) }, 0, 0 }, // #134 [ref=20x] - { { EXT(XOP) }, 0, 0 }, // #135 [ref=55x] - { { EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #136 [ref=19x] - { { EXT(AVX512_PFI) }, 0, 0 }, // #137 [ref=16x] - { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(GFNI) }, 0, 0 }, // #138 [ref=3x] - { { EXT(AVX), EXT(AVX2) }, 0, 0 }, // #139 [ref=17x] - { { EXT(AVX512_VP2INTERSECT) }, 0, 0 }, // #140 [ref=2x] - { { EXT(AVX512_4VNNIW) }, 0, 0 }, // #141 [ref=2x] - { { EXT(AVX), EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #142 [ref=54x] - { { EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #143 [ref=2x] - { { EXT(AVX512_CDI), EXT(AVX512_VL) }, 0, 0 }, // #144 [ref=6x] - { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(PCLMULQDQ), EXT(VPCLMULQDQ) }, 0, 0 }, // #145 [ref=1x] - { { EXT(AVX) }, 1, 0 }, // #146 [ref=7x] - { { EXT(AVX512_VBMI2), EXT(AVX512_VL) }, 0, 0 }, // #147 [ref=16x] - { { EXT(AVX512_VL), EXT(AVX512_VNNI) }, 0, 0 }, // #148 [ref=4x] - { { EXT(AVX512_VBMI), EXT(AVX512_VL) }, 0, 0 }, // #149 [ref=4x] - { { EXT(AVX), EXT(AVX512_BW) }, 0, 0 }, // #150 [ref=4x] - { { EXT(AVX), EXT(AVX512_DQ) }, 0, 0 }, // #151 [ref=4x] - { { EXT(AVX512_IFMA), EXT(AVX512_VL) }, 0, 0 }, // #152 [ref=2x] - { { EXT(AVX512_BITALG), EXT(AVX512_VL) }, 0, 0 }, // #153 [ref=3x] - { { EXT(AVX512_VL), EXT(AVX512_VPOPCNTDQ) }, 0, 0 }, // #154 [ref=2x] - { { EXT(WBNOINVD) }, 0, 0 }, // #155 [ref=1x] - { { EXT(RTM) }, 0, 0 }, // #156 [ref=3x] - { { EXT(XSAVE) }, 0, 0 }, // #157 [ref=6x] - { { EXT(TSXLDTRK) }, 0, 0 }, // #158 [ref=2x] - { { EXT(XSAVES) }, 0, 0 }, // #159 [ref=4x] - { { EXT(XSAVEC) }, 0, 0 }, // #160 [ref=2x] - { { EXT(XSAVEOPT) }, 0, 0 }, // #161 [ref=2x] - { { EXT(TSX) }, 1, 0 } // #162 [ref=1x] + { { EXT(CET_SS) }, 1, 0 }, // #24 [ref=3x] + { { EXT(CLWB) }, 0, 0 }, // #25 [ref=1x] + { { EXT(CLZERO) }, 0, 0 }, // #26 [ref=1x] + { { 0 }, 3, 0 }, // #27 [ref=1x] + { { EXT(CMOV) }, 11, 0 }, // #28 [ref=6x] + { { EXT(CMOV) }, 12, 0 }, // #29 [ref=8x] + { { EXT(CMOV) }, 13, 0 }, // #30 [ref=6x] + { { EXT(CMOV) }, 14, 0 }, // #31 [ref=4x] + { { EXT(CMOV) }, 15, 0 }, // #32 [ref=4x] + { { EXT(CMOV) }, 16, 0 }, // #33 [ref=2x] + { { EXT(CMOV) }, 17, 0 }, // #34 [ref=6x] + { { EXT(CMOV) }, 18, 0 }, // #35 [ref=2x] + { { 0 }, 19, 0 }, // #36 [ref=2x] + { { EXT(I486) }, 1, 0 }, // #37 [ref=2x] + { { EXT(CMPXCHG16B) }, 5, 0 }, // #38 [ref=1x] + { { EXT(CMPXCHG8B) }, 5, 0 }, // #39 [ref=1x] + { { EXT(SSE2) }, 1, 0 }, // #40 [ref=2x] + { { EXT(SSE) }, 1, 0 }, // #41 [ref=2x] + { { EXT(I486) }, 0, 0 }, // #42 [ref=4x] + { { EXT(SSE4_2) }, 0, 0 }, // #43 [ref=2x] + { { 0 }, 20, 0 }, // #44 [ref=2x] + { { EXT(MMX) }, 0, 0 }, // #45 [ref=1x] + { { EXT(CET_IBT) }, 0, 0 }, // #46 [ref=2x] + { { EXT(ENQCMD) }, 0, 0 }, // #47 [ref=2x] + { { EXT(SSE4A) }, 0, 0 }, // #48 [ref=4x] + { { 0 }, 21, 0 }, // #49 [ref=4x] + { { EXT(3DNOW) }, 0, 0 }, // #50 [ref=21x] + { { EXT(FXSR) }, 0, 0 }, // #51 [ref=4x] + { { EXT(SMX) }, 0, 0 }, // #52 [ref=1x] + { { EXT(GFNI) }, 0, 0 }, // #53 [ref=3x] + { { EXT(CET_SS) }, 0, 0 }, // #54 [ref=9x] + { { 0 }, 16, 0 }, // #55 [ref=5x] + { { EXT(VMX) }, 0, 0 }, // #56 [ref=12x] + { { 0 }, 11, 0 }, // #57 [ref=8x] + { { 0 }, 12, 0 }, // #58 [ref=12x] + { { 0 }, 13, 0 }, // #59 [ref=10x] + { { 0 }, 14, 0 }, // #60 [ref=8x] + { { 0 }, 15, 0 }, // #61 [ref=8x] + { { 0 }, 17, 0 }, // #62 [ref=8x] + { { 0 }, 18, 0 }, // #63 [ref=4x] + { { EXT(AVX512_DQ) }, 0, 0 }, // #64 [ref=23x] + { { EXT(AVX512_BW) }, 0, 0 }, // #65 [ref=22x] + { { EXT(AVX512_F) }, 0, 0 }, // #66 [ref=37x] + { { EXT(AVX512_DQ) }, 1, 0 }, // #67 [ref=3x] + { { EXT(AVX512_BW) }, 1, 0 }, // #68 [ref=4x] + { { EXT(AVX512_F) }, 1, 0 }, // #69 [ref=1x] + { { EXT(LAHFSAHF) }, 22, 0 }, // #70 [ref=1x] + { { EXT(AMX_TILE) }, 0, 0 }, // #71 [ref=7x] + { { EXT(LWP) }, 0, 0 }, // #72 [ref=4x] + { { 0 }, 23, 0 }, // #73 [ref=3x] + { { EXT(LZCNT) }, 1, 0 }, // #74 [ref=1x] + { { EXT(MMX2) }, 0, 0 }, // #75 [ref=8x] + { { EXT(MCOMMIT) }, 1, 0 }, // #76 [ref=1x] + { { EXT(MONITOR) }, 0, 0 }, // #77 [ref=2x] + { { EXT(MONITORX) }, 0, 0 }, // #78 [ref=2x] + { { EXT(MOVBE) }, 0, 0 }, // #79 [ref=1x] + { { EXT(MMX), EXT(SSE2) }, 0, 0 }, // #80 [ref=46x] + { { EXT(MOVDIR64B) }, 0, 0 }, // #81 [ref=1x] + { { EXT(MOVDIRI) }, 0, 0 }, // #82 [ref=1x] + { { EXT(BMI2) }, 0, 0 }, // #83 [ref=7x] + { { EXT(SSSE3) }, 0, 0 }, // #84 [ref=15x] + { { EXT(MMX2), EXT(SSE2) }, 0, 0 }, // #85 [ref=10x] + { { EXT(PCLMULQDQ) }, 0, 0 }, // #86 [ref=1x] + { { EXT(SSE4_2) }, 1, 0 }, // #87 [ref=4x] + { { EXT(PCONFIG) }, 0, 0 }, // #88 [ref=1x] + { { EXT(MMX2), EXT(SSE2), EXT(SSE4_1) }, 0, 0 }, // #89 [ref=1x] + { { EXT(3DNOW2) }, 0, 0 }, // #90 [ref=5x] + { { EXT(GEODE) }, 0, 0 }, // #91 [ref=2x] + { { EXT(POPCNT) }, 1, 0 }, // #92 [ref=1x] + { { 0 }, 24, 0 }, // #93 [ref=3x] + { { EXT(PREFETCHW) }, 1, 0 }, // #94 [ref=1x] + { { EXT(PREFETCHWT1) }, 1, 0 }, // #95 [ref=1x] + { { EXT(SNP) }, 20, 0 }, // #96 [ref=3x] + { { EXT(SSE4_1) }, 1, 0 }, // #97 [ref=1x] + { { EXT(PTWRITE) }, 0, 0 }, // #98 [ref=1x] + { { 0 }, 25, 0 }, // #99 [ref=3x] + { { EXT(SNP) }, 1, 0 }, // #100 [ref=1x] + { { 0 }, 26, 0 }, // #101 [ref=2x] + { { EXT(FSGSBASE) }, 0, 0 }, // #102 [ref=4x] + { { EXT(MSR) }, 0, 0 }, // #103 [ref=2x] + { { EXT(RDPID) }, 0, 0 }, // #104 [ref=1x] + { { EXT(OSPKE) }, 0, 0 }, // #105 [ref=1x] + { { EXT(RDPRU) }, 0, 0 }, // #106 [ref=1x] + { { EXT(RDRAND) }, 1, 0 }, // #107 [ref=1x] + { { EXT(RDSEED) }, 1, 0 }, // #108 [ref=1x] + { { EXT(RDTSC) }, 0, 0 }, // #109 [ref=1x] + { { EXT(RDTSCP) }, 0, 0 }, // #110 [ref=1x] + { { 0 }, 27, 0 }, // #111 [ref=2x] + { { EXT(LAHFSAHF) }, 28, 0 }, // #112 [ref=1x] + { { EXT(SERIALIZE) }, 0, 0 }, // #113 [ref=1x] + { { EXT(SHA) }, 0, 0 }, // #114 [ref=7x] + { { EXT(SKINIT) }, 0, 0 }, // #115 [ref=2x] + { { EXT(AMX_BF16) }, 0, 0 }, // #116 [ref=1x] + { { EXT(AMX_INT8) }, 0, 0 }, // #117 [ref=4x] + { { EXT(WAITPKG) }, 1, 0 }, // #118 [ref=2x] + { { EXT(WAITPKG) }, 0, 0 }, // #119 [ref=1x] + { { EXT(AVX512_4FMAPS) }, 0, 0 }, // #120 [ref=4x] + { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #121 [ref=46x] + { { EXT(AVX), EXT(AVX512_F) }, 0, 0 }, // #122 [ref=32x] + { { EXT(AVX) }, 0, 0 }, // #123 [ref=37x] + { { EXT(AESNI), EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(VAES) }, 0, 0 }, // #124 [ref=4x] + { { EXT(AESNI), EXT(AVX) }, 0, 0 }, // #125 [ref=2x] + { { EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #126 [ref=112x] + { { EXT(AVX), EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #127 [ref=8x] + { { EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #128 [ref=26x] + { { EXT(AVX512_DQ), EXT(AVX512_VL) }, 0, 0 }, // #129 [ref=30x] + { { EXT(AVX2) }, 0, 0 }, // #130 [ref=7x] + { { EXT(AVX), EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #131 [ref=39x] + { { EXT(AVX), EXT(AVX512_F) }, 1, 0 }, // #132 [ref=4x] + { { EXT(AVX512_BF16), EXT(AVX512_VL) }, 0, 0 }, // #133 [ref=3x] + { { EXT(AVX512_F), EXT(AVX512_VL), EXT(F16C) }, 0, 0 }, // #134 [ref=2x] + { { EXT(AVX512_ERI) }, 0, 0 }, // #135 [ref=10x] + { { EXT(AVX512_F), EXT(AVX512_VL), EXT(FMA) }, 0, 0 }, // #136 [ref=36x] + { { EXT(AVX512_F), EXT(FMA) }, 0, 0 }, // #137 [ref=24x] + { { EXT(FMA4) }, 0, 0 }, // #138 [ref=20x] + { { EXT(XOP) }, 0, 0 }, // #139 [ref=55x] + { { EXT(AVX2), EXT(AVX512_F), EXT(AVX512_VL) }, 0, 0 }, // #140 [ref=19x] + { { EXT(AVX512_PFI) }, 0, 0 }, // #141 [ref=16x] + { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(GFNI) }, 0, 0 }, // #142 [ref=3x] + { { EXT(AVX), EXT(AVX2) }, 0, 0 }, // #143 [ref=17x] + { { EXT(AVX512_VP2INTERSECT) }, 0, 0 }, // #144 [ref=2x] + { { EXT(AVX512_4VNNIW) }, 0, 0 }, // #145 [ref=2x] + { { EXT(AVX), EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #146 [ref=54x] + { { EXT(AVX2), EXT(AVX512_BW), EXT(AVX512_VL) }, 0, 0 }, // #147 [ref=2x] + { { EXT(AVX512_CDI), EXT(AVX512_VL) }, 0, 0 }, // #148 [ref=6x] + { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(PCLMULQDQ), EXT(VPCLMULQDQ) }, 0, 0 }, // #149 [ref=1x] + { { EXT(AVX) }, 1, 0 }, // #150 [ref=7x] + { { EXT(AVX512_VBMI2), EXT(AVX512_VL) }, 0, 0 }, // #151 [ref=16x] + { { EXT(AVX512_VL), EXT(AVX512_VNNI) }, 0, 0 }, // #152 [ref=4x] + { { EXT(AVX512_VBMI), EXT(AVX512_VL) }, 0, 0 }, // #153 [ref=4x] + { { EXT(AVX), EXT(AVX512_BW) }, 0, 0 }, // #154 [ref=4x] + { { EXT(AVX), EXT(AVX512_DQ) }, 0, 0 }, // #155 [ref=4x] + { { EXT(AVX512_IFMA), EXT(AVX512_VL) }, 0, 0 }, // #156 [ref=2x] + { { EXT(AVX512_BITALG), EXT(AVX512_VL) }, 0, 0 }, // #157 [ref=3x] + { { EXT(AVX512_VL), EXT(AVX512_VPOPCNTDQ) }, 0, 0 }, // #158 [ref=2x] + { { EXT(WBNOINVD) }, 0, 0 }, // #159 [ref=1x] + { { EXT(RTM) }, 0, 0 }, // #160 [ref=3x] + { { EXT(XSAVE) }, 0, 0 }, // #161 [ref=6x] + { { EXT(TSXLDTRK) }, 0, 0 }, // #162 [ref=2x] + { { EXT(XSAVES) }, 0, 0 }, // #163 [ref=4x] + { { EXT(XSAVEC) }, 0, 0 }, // #164 [ref=2x] + { { EXT(XSAVEOPT) }, 0, 0 }, // #165 [ref=2x] + { { EXT(TSX) }, 1, 0 } // #166 [ref=1x] }; #undef EXT #define FLAG(VAL) uint32_t(Status::k##VAL) const InstDB::RWFlagsInfoTable InstDB::_rwFlagsInfoTable[] = { - { 0, 0 }, // #0 [ref=1301x] - { 0, FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #1 [ref=80x] + { 0, 0 }, // #0 [ref=1315x] + { 0, FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #1 [ref=83x] { FLAG(CF), FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #2 [ref=2x] { FLAG(CF), FLAG(CF) }, // #3 [ref=2x] { FLAG(OF), FLAG(OF) }, // #4 [ref=1x] @@ -2653,119 +2686,120 @@ const char InstDB::_nameData[] = "\0" "aaa\0" "aad\0" "aam\0" "aas\0" "adc\0" "adcx\0" "adox\0" "arpl\0" "bextr\0" "blcfill\0" "blci\0" "blcic\0" "blcmsk\0" "blcs\0" "blsfill\0" "blsi\0" "blsic\0" "blsmsk\0" "blsr\0" "bndcl\0" "bndcn\0" "bndcu\0" "bndldx\0" "bndmk\0" "bndmov\0" "bndstx\0" "bound\0" "bsf\0" "bsr\0" "bswap\0" "bt\0" "btc\0" "btr\0" "bts\0" "bzhi\0" "cbw\0" - "cdq\0" "cdqe\0" "clac\0" "clc\0" "cld\0" "cldemote\0" "clflush\0" "clflushopt\0" "clgi\0" "cli\0" "clts\0" "clwb\0" - "clzero\0" "cmc\0" "cmova\0" "cmovae\0" "cmovc\0" "cmovg\0" "cmovge\0" "cmovl\0" "cmovle\0" "cmovna\0" "cmovnae\0" - "cmovnc\0" "cmovng\0" "cmovnge\0" "cmovnl\0" "cmovnle\0" "cmovno\0" "cmovnp\0" "cmovns\0" "cmovnz\0" "cmovo\0" - "cmovp\0" "cmovpe\0" "cmovpo\0" "cmovs\0" "cmovz\0" "cmp\0" "cmps\0" "cmpxchg\0" "cmpxchg16b\0" "cmpxchg8b\0" - "cpuid\0" "cqo\0" "crc32\0" "cvtpd2pi\0" "cvtpi2pd\0" "cvtpi2ps\0" "cvtps2pi\0" "cvttpd2pi\0" "cvttps2pi\0" "cwd\0" - "cwde\0" "daa\0" "das\0" "enqcmd\0" "enqcmds\0" "f2xm1\0" "fabs\0" "faddp\0" "fbld\0" "fbstp\0" "fchs\0" "fclex\0" - "fcmovb\0" "fcmovbe\0" "fcmove\0" "fcmovnb\0" "fcmovnbe\0" "fcmovne\0" "fcmovnu\0" "fcmovu\0" "fcom\0" "fcomi\0" - "fcomip\0" "fcomp\0" "fcompp\0" "fcos\0" "fdecstp\0" "fdiv\0" "fdivp\0" "fdivr\0" "fdivrp\0" "femms\0" "ffree\0" - "fiadd\0" "ficom\0" "ficomp\0" "fidiv\0" "fidivr\0" "fild\0" "fimul\0" "fincstp\0" "finit\0" "fist\0" "fistp\0" - "fisttp\0" "fisub\0" "fisubr\0" "fld\0" "fld1\0" "fldcw\0" "fldenv\0" "fldl2e\0" "fldl2t\0" "fldlg2\0" "fldln2\0" - "fldpi\0" "fldz\0" "fmulp\0" "fnclex\0" "fninit\0" "fnop\0" "fnsave\0" "fnstcw\0" "fnstenv\0" "fnstsw\0" "fpatan\0" - "fprem\0" "fprem1\0" "fptan\0" "frndint\0" "frstor\0" "fsave\0" "fscale\0" "fsin\0" "fsincos\0" "fsqrt\0" "fst\0" - "fstcw\0" "fstenv\0" "fstp\0" "fstsw\0" "fsubp\0" "fsubrp\0" "ftst\0" "fucom\0" "fucomi\0" "fucomip\0" "fucomp\0" - "fucompp\0" "fwait\0" "fxam\0" "fxch\0" "fxrstor\0" "fxrstor64\0" "fxsave\0" "fxsave64\0" "fxtract\0" "fyl2x\0" - "fyl2xp1\0" "getsec\0" "hlt\0" "inc\0" "insertq\0" "int3\0" "into\0" "invept\0" "invlpg\0" "invlpga\0" "invpcid\0" - "invvpid\0" "iret\0" "iretd\0" "iretq\0" "iretw\0" "ja\0" "jae\0" "jb\0" "jbe\0" "jc\0" "je\0" "jecxz\0" "jg\0" - "jge\0" "jl\0" "jle\0" "jmp\0" "jna\0" "jnae\0" "jnb\0" "jnbe\0" "jnc\0" "jne\0" "jng\0" "jnge\0" "jnl\0" "jnle\0" - "jno\0" "jnp\0" "jns\0" "jnz\0" "jo\0" "jp\0" "jpe\0" "jpo\0" "js\0" "jz\0" "kaddb\0" "kaddd\0" "kaddq\0" "kaddw\0" - "kandb\0" "kandd\0" "kandnb\0" "kandnd\0" "kandnq\0" "kandnw\0" "kandq\0" "kandw\0" "kmovb\0" "kmovw\0" "knotb\0" - "knotd\0" "knotq\0" "knotw\0" "korb\0" "kord\0" "korq\0" "kortestb\0" "kortestd\0" "kortestq\0" "kortestw\0" "korw\0" - "kshiftlb\0" "kshiftld\0" "kshiftlq\0" "kshiftlw\0" "kshiftrb\0" "kshiftrd\0" "kshiftrq\0" "kshiftrw\0" "ktestb\0" - "ktestd\0" "ktestq\0" "ktestw\0" "kunpckbw\0" "kunpckdq\0" "kunpckwd\0" "kxnorb\0" "kxnord\0" "kxnorq\0" "kxnorw\0" - "kxorb\0" "kxord\0" "kxorq\0" "kxorw\0" "lahf\0" "lar\0" "lds\0" "ldtilecfg\0" "lea\0" "leave\0" "les\0" "lfence\0" - "lfs\0" "lgdt\0" "lgs\0" "lidt\0" "lldt\0" "llwpcb\0" "lmsw\0" "lods\0" "loop\0" "loope\0" "loopne\0" "lsl\0" "ltr\0" + "cdq\0" "cdqe\0" "clac\0" "clc\0" "cld\0" "cldemote\0" "clflush\0" "clflushopt\0" "clgi\0" "cli\0" "clrssbsy\0" + "clts\0" "clwb\0" "clzero\0" "cmc\0" "cmova\0" "cmovae\0" "cmovc\0" "cmovg\0" "cmovge\0" "cmovl\0" "cmovle\0" + "cmovna\0" "cmovnae\0" "cmovnc\0" "cmovng\0" "cmovnge\0" "cmovnl\0" "cmovnle\0" "cmovno\0" "cmovnp\0" "cmovns\0" + "cmovnz\0" "cmovo\0" "cmovp\0" "cmovpe\0" "cmovpo\0" "cmovs\0" "cmovz\0" "cmp\0" "cmps\0" "cmpxchg\0" "cmpxchg16b\0" + "cmpxchg8b\0" "cpuid\0" "cqo\0" "crc32\0" "cvtpd2pi\0" "cvtpi2pd\0" "cvtpi2ps\0" "cvtps2pi\0" "cvttpd2pi\0" + "cvttps2pi\0" "cwd\0" "cwde\0" "daa\0" "das\0" "endbr32\0" "endbr64\0" "enqcmd\0" "enqcmds\0" "f2xm1\0" "fabs\0" + "faddp\0" "fbld\0" "fbstp\0" "fchs\0" "fclex\0" "fcmovb\0" "fcmovbe\0" "fcmove\0" "fcmovnb\0" "fcmovnbe\0" + "fcmovne\0" "fcmovnu\0" "fcmovu\0" "fcom\0" "fcomi\0" "fcomip\0" "fcomp\0" "fcompp\0" "fcos\0" "fdecstp\0" "fdiv\0" + "fdivp\0" "fdivr\0" "fdivrp\0" "femms\0" "ffree\0" "fiadd\0" "ficom\0" "ficomp\0" "fidiv\0" "fidivr\0" "fild\0" + "fimul\0" "fincstp\0" "finit\0" "fist\0" "fistp\0" "fisttp\0" "fisub\0" "fisubr\0" "fld\0" "fld1\0" "fldcw\0" + "fldenv\0" "fldl2e\0" "fldl2t\0" "fldlg2\0" "fldln2\0" "fldpi\0" "fldz\0" "fmulp\0" "fnclex\0" "fninit\0" "fnop\0" + "fnsave\0" "fnstcw\0" "fnstenv\0" "fnstsw\0" "fpatan\0" "fprem\0" "fprem1\0" "fptan\0" "frndint\0" "frstor\0" + "fsave\0" "fscale\0" "fsin\0" "fsincos\0" "fsqrt\0" "fst\0" "fstcw\0" "fstenv\0" "fstp\0" "fstsw\0" "fsubp\0" + "fsubrp\0" "ftst\0" "fucom\0" "fucomi\0" "fucomip\0" "fucomp\0" "fucompp\0" "fwait\0" "fxam\0" "fxch\0" "fxrstor\0" + "fxrstor64\0" "fxsave\0" "fxsave64\0" "fxtract\0" "fyl2x\0" "fyl2xp1\0" "getsec\0" "hlt\0" "inc\0" "incsspd\0" + "incsspq\0" "insertq\0" "int3\0" "into\0" "invept\0" "invlpg\0" "invlpga\0" "invpcid\0" "invvpid\0" "iret\0" + "iretd\0" "iretq\0" "iretw\0" "ja\0" "jae\0" "jb\0" "jbe\0" "jc\0" "je\0" "jecxz\0" "jg\0" "jge\0" "jl\0" "jle\0" + "jmp\0" "jna\0" "jnae\0" "jnb\0" "jnbe\0" "jnc\0" "jne\0" "jng\0" "jnge\0" "jnl\0" "jnle\0" "jno\0" "jnp\0" "jns\0" + "jnz\0" "jo\0" "jp\0" "jpe\0" "jpo\0" "js\0" "jz\0" "kaddb\0" "kaddd\0" "kaddq\0" "kaddw\0" "kandb\0" "kandd\0" + "kandnb\0" "kandnd\0" "kandnq\0" "kandnw\0" "kandq\0" "kandw\0" "kmovb\0" "kmovw\0" "knotb\0" "knotd\0" "knotq\0" + "knotw\0" "korb\0" "kord\0" "korq\0" "kortestb\0" "kortestd\0" "kortestq\0" "kortestw\0" "korw\0" "kshiftlb\0" + "kshiftld\0" "kshiftlq\0" "kshiftlw\0" "kshiftrb\0" "kshiftrd\0" "kshiftrq\0" "kshiftrw\0" "ktestb\0" "ktestd\0" + "ktestq\0" "ktestw\0" "kunpckbw\0" "kunpckdq\0" "kunpckwd\0" "kxnorb\0" "kxnord\0" "kxnorq\0" "kxnorw\0" "kxorb\0" + "kxord\0" "kxorq\0" "kxorw\0" "lahf\0" "lar\0" "lds\0" "ldtilecfg\0" "lea\0" "leave\0" "les\0" "lfence\0" "lfs\0" + "lgdt\0" "lgs\0" "lidt\0" "lldt\0" "llwpcb\0" "lmsw\0" "lods\0" "loop\0" "loope\0" "loopne\0" "lsl\0" "ltr\0" "lwpins\0" "lwpval\0" "lzcnt\0" "mcommit\0" "mfence\0" "monitorx\0" "movdir64b\0" "movdiri\0" "movdq2q\0" "movnti\0" "movntq\0" "movntsd\0" "movntss\0" "movq2dq\0" "movsx\0" "movsxd\0" "movzx\0" "mulx\0" "mwaitx\0" "neg\0" "not\0" - "out\0" "outs\0" "pavgusb\0" "pcommit\0" "pconfig\0" "pdep\0" "pext\0" "pf2id\0" "pf2iw\0" "pfacc\0" "pfadd\0" - "pfcmpeq\0" "pfcmpge\0" "pfcmpgt\0" "pfmax\0" "pfmin\0" "pfmul\0" "pfnacc\0" "pfpnacc\0" "pfrcp\0" "pfrcpit1\0" - "pfrcpit2\0" "pfrcpv\0" "pfrsqit1\0" "pfrsqrt\0" "pfrsqrtv\0" "pfsub\0" "pfsubr\0" "pi2fd\0" "pi2fw\0" "pmulhrw\0" - "pop\0" "popa\0" "popad\0" "popcnt\0" "popf\0" "popfd\0" "popfq\0" "prefetch\0" "prefetchnta\0" "prefetcht0\0" - "prefetcht1\0" "prefetcht2\0" "prefetchw\0" "prefetchwt1\0" "pshufw\0" "psmash\0" "pswapd\0" "push\0" "pusha\0" + "out\0" "outs\0" "pavgusb\0" "pconfig\0" "pdep\0" "pext\0" "pf2id\0" "pf2iw\0" "pfacc\0" "pfadd\0" "pfcmpeq\0" + "pfcmpge\0" "pfcmpgt\0" "pfmax\0" "pfmin\0" "pfmul\0" "pfnacc\0" "pfpnacc\0" "pfrcp\0" "pfrcpit1\0" "pfrcpit2\0" + "pfrcpv\0" "pfrsqit1\0" "pfrsqrt\0" "pfrsqrtv\0" "pfsub\0" "pfsubr\0" "pi2fd\0" "pi2fw\0" "pmulhrw\0" "pop\0" + "popa\0" "popad\0" "popcnt\0" "popf\0" "popfd\0" "popfq\0" "prefetch\0" "prefetchnta\0" "prefetcht0\0" "prefetcht1\0" + "prefetcht2\0" "prefetchw\0" "prefetchwt1\0" "pshufw\0" "psmash\0" "pswapd\0" "ptwrite\0" "push\0" "pusha\0" "pushad\0" "pushf\0" "pushfd\0" "pushfq\0" "pvalidate\0" "rcl\0" "rcr\0" "rdfsbase\0" "rdgsbase\0" "rdmsr\0" - "rdpid\0" "rdpmc\0" "rdpru\0" "rdrand\0" "rdseed\0" "rdtsc\0" "rdtscp\0" "rmpadjust\0" "rmpupdate\0" "rol\0" "ror\0" - "rorx\0" "rsm\0" "sahf\0" "sal\0" "sar\0" "sarx\0" "sbb\0" "scas\0" "serialize\0" "seta\0" "setae\0" "setb\0" - "setbe\0" "setc\0" "sete\0" "setg\0" "setge\0" "setl\0" "setle\0" "setna\0" "setnae\0" "setnb\0" "setnbe\0" "setnc\0" - "setne\0" "setng\0" "setnge\0" "setnl\0" "setnle\0" "setno\0" "setnp\0" "setns\0" "setnz\0" "seto\0" "setp\0" - "setpe\0" "setpo\0" "sets\0" "setz\0" "sfence\0" "sgdt\0" "sha1msg1\0" "sha1msg2\0" "sha1nexte\0" "sha1rnds4\0" - "sha256msg1\0" "sha256msg2\0" "sha256rnds2\0" "shl\0" "shlx\0" "shr\0" "shrd\0" "shrx\0" "sidt\0" "skinit\0" "sldt\0" - "slwpcb\0" "smsw\0" "stac\0" "stc\0" "stgi\0" "sti\0" "stos\0" "str\0" "sttilecfg\0" "swapgs\0" "syscall\0" - "sysenter\0" "sysexit\0" "sysexit64\0" "sysret\0" "sysret64\0" "t1mskc\0" "tdpbf16ps\0" "tdpbssd\0" "tdpbsud\0" - "tdpbusd\0" "tdpbuud\0" "tileloadd\0" "tileloaddt1\0" "tilerelease\0" "tilestored\0" "tilezero\0" "tpause\0" - "tzcnt\0" "tzmsk\0" "ud2\0" "umonitor\0" "umwait\0" "v4fmaddps\0" "v4fmaddss\0" "v4fnmaddps\0" "v4fnmaddss\0" - "vaddpd\0" "vaddps\0" "vaddsd\0" "vaddss\0" "vaddsubpd\0" "vaddsubps\0" "vaesdec\0" "vaesdeclast\0" "vaesenc\0" - "vaesenclast\0" "vaesimc\0" "vaeskeygenassist\0" "valignd\0" "valignq\0" "vandnpd\0" "vandnps\0" "vandpd\0" - "vandps\0" "vblendmb\0" "vblendmd\0" "vblendmpd\0" "vblendmps\0" "vblendmq\0" "vblendmw\0" "vblendpd\0" "vblendps\0" - "vblendvpd\0" "vblendvps\0" "vbroadcastf128\0" "vbroadcastf32x2\0" "vbroadcastf32x4\0" "vbroadcastf32x8\0" - "vbroadcastf64x2\0" "vbroadcastf64x4\0" "vbroadcasti128\0" "vbroadcasti32x2\0" "vbroadcasti32x4\0" - "vbroadcasti32x8\0" "vbroadcasti64x2\0" "vbroadcasti64x4\0" "vbroadcastsd\0" "vbroadcastss\0" "vcmppd\0" "vcmpps\0" - "vcmpsd\0" "vcmpss\0" "vcomisd\0" "vcomiss\0" "vcompresspd\0" "vcompressps\0" "vcvtdq2pd\0" "vcvtdq2ps\0" - "vcvtne2ps2bf16\0" "vcvtneps2bf16\0" "vcvtpd2dq\0" "vcvtpd2ps\0" "vcvtpd2qq\0" "vcvtpd2udq\0" "vcvtpd2uqq\0" - "vcvtph2ps\0" "vcvtps2dq\0" "vcvtps2pd\0" "vcvtps2ph\0" "vcvtps2qq\0" "vcvtps2udq\0" "vcvtps2uqq\0" "vcvtqq2pd\0" - "vcvtqq2ps\0" "vcvtsd2si\0" "vcvtsd2ss\0" "vcvtsd2usi\0" "vcvtsi2sd\0" "vcvtsi2ss\0" "vcvtss2sd\0" "vcvtss2si\0" - "vcvtss2usi\0" "vcvttpd2dq\0" "vcvttpd2qq\0" "vcvttpd2udq\0" "vcvttpd2uqq\0" "vcvttps2dq\0" "vcvttps2qq\0" - "vcvttps2udq\0" "vcvttps2uqq\0" "vcvttsd2si\0" "vcvttsd2usi\0" "vcvttss2si\0" "vcvttss2usi\0" "vcvtudq2pd\0" - "vcvtudq2ps\0" "vcvtuqq2pd\0" "vcvtuqq2ps\0" "vcvtusi2sd\0" "vcvtusi2ss\0" "vdbpsadbw\0" "vdivpd\0" "vdivps\0" - "vdivsd\0" "vdivss\0" "vdpbf16ps\0" "vdppd\0" "vdpps\0" "verr\0" "verw\0" "vexp2pd\0" "vexp2ps\0" "vexpandpd\0" - "vexpandps\0" "vextractf128\0" "vextractf32x4\0" "vextractf32x8\0" "vextractf64x2\0" "vextractf64x4\0" - "vextracti128\0" "vextracti32x4\0" "vextracti32x8\0" "vextracti64x2\0" "vextracti64x4\0" "vextractps\0" - "vfixupimmpd\0" "vfixupimmps\0" "vfixupimmsd\0" "vfixupimmss\0" "vfmadd132pd\0" "vfmadd132ps\0" "vfmadd132sd\0" - "vfmadd132ss\0" "vfmadd213pd\0" "vfmadd213ps\0" "vfmadd213sd\0" "vfmadd213ss\0" "vfmadd231pd\0" "vfmadd231ps\0" - "vfmadd231sd\0" "vfmadd231ss\0" "vfmaddpd\0" "vfmaddps\0" "vfmaddsd\0" "vfmaddss\0" "vfmaddsub132pd\0" - "vfmaddsub132ps\0" "vfmaddsub213pd\0" "vfmaddsub213ps\0" "vfmaddsub231pd\0" "vfmaddsub231ps\0" "vfmaddsubpd\0" - "vfmaddsubps\0" "vfmsub132pd\0" "vfmsub132ps\0" "vfmsub132sd\0" "vfmsub132ss\0" "vfmsub213pd\0" "vfmsub213ps\0" - "vfmsub213sd\0" "vfmsub213ss\0" "vfmsub231pd\0" "vfmsub231ps\0" "vfmsub231sd\0" "vfmsub231ss\0" "vfmsubadd132pd\0" - "vfmsubadd132ps\0" "vfmsubadd213pd\0" "vfmsubadd213ps\0" "vfmsubadd231pd\0" "vfmsubadd231ps\0" "vfmsubaddpd\0" - "vfmsubaddps\0" "vfmsubpd\0" "vfmsubps\0" "vfmsubsd\0" "vfmsubss\0" "vfnmadd132pd\0" "vfnmadd132ps\0" - "vfnmadd132sd\0" "vfnmadd132ss\0" "vfnmadd213pd\0" "vfnmadd213ps\0" "vfnmadd213sd\0" "vfnmadd213ss\0" - "vfnmadd231pd\0" "vfnmadd231ps\0" "vfnmadd231sd\0" "vfnmadd231ss\0" "vfnmaddpd\0" "vfnmaddps\0" "vfnmaddsd\0" - "vfnmaddss\0" "vfnmsub132pd\0" "vfnmsub132ps\0" "vfnmsub132sd\0" "vfnmsub132ss\0" "vfnmsub213pd\0" "vfnmsub213ps\0" - "vfnmsub213sd\0" "vfnmsub213ss\0" "vfnmsub231pd\0" "vfnmsub231ps\0" "vfnmsub231sd\0" "vfnmsub231ss\0" "vfnmsubpd\0" - "vfnmsubps\0" "vfnmsubsd\0" "vfnmsubss\0" "vfpclasspd\0" "vfpclassps\0" "vfpclasssd\0" "vfpclassss\0" "vfrczpd\0" - "vfrczps\0" "vfrczsd\0" "vfrczss\0" "vgatherdpd\0" "vgatherdps\0" "vgatherpf0dpd\0" "vgatherpf0dps\0" - "vgatherpf0qpd\0" "vgatherpf0qps\0" "vgatherpf1dpd\0" "vgatherpf1dps\0" "vgatherpf1qpd\0" "vgatherpf1qps\0" - "vgatherqpd\0" "vgatherqps\0" "vgetexppd\0" "vgetexpps\0" "vgetexpsd\0" "vgetexpss\0" "vgetmantpd\0" "vgetmantps\0" - "vgetmantsd\0" "vgetmantss\0" "vgf2p8affineinvqb\0" "vgf2p8affineqb\0" "vgf2p8mulb\0" "vhaddpd\0" "vhaddps\0" - "vhsubpd\0" "vhsubps\0" "vinsertf128\0" "vinsertf32x4\0" "vinsertf32x8\0" "vinsertf64x2\0" "vinsertf64x4\0" - "vinserti128\0" "vinserti32x4\0" "vinserti32x8\0" "vinserti64x2\0" "vinserti64x4\0" "vinsertps\0" "vlddqu\0" - "vldmxcsr\0" "vmaskmovdqu\0" "vmaskmovpd\0" "vmaskmovps\0" "vmaxpd\0" "vmaxps\0" "vmaxsd\0" "vmaxss\0" "vmcall\0" - "vmclear\0" "vmfunc\0" "vminpd\0" "vminps\0" "vminsd\0" "vminss\0" "vmlaunch\0" "vmload\0" "vmmcall\0" "vmovapd\0" - "vmovaps\0" "vmovd\0" "vmovddup\0" "vmovdqa\0" "vmovdqa32\0" "vmovdqa64\0" "vmovdqu\0" "vmovdqu16\0" "vmovdqu32\0" - "vmovdqu64\0" "vmovdqu8\0" "vmovhlps\0" "vmovhpd\0" "vmovhps\0" "vmovlhps\0" "vmovlpd\0" "vmovlps\0" "vmovmskpd\0" - "vmovmskps\0" "vmovntdq\0" "vmovntdqa\0" "vmovntpd\0" "vmovntps\0" "vmovq\0" "vmovsd\0" "vmovshdup\0" "vmovsldup\0" - "vmovss\0" "vmovupd\0" "vmovups\0" "vmpsadbw\0" "vmptrld\0" "vmptrst\0" "vmread\0" "vmresume\0" "vmrun\0" "vmsave\0" - "vmulpd\0" "vmulps\0" "vmulsd\0" "vmulss\0" "vmwrite\0" "vmxon\0" "vorpd\0" "vorps\0" "vp2intersectd\0" - "vp2intersectq\0" "vp4dpwssd\0" "vp4dpwssds\0" "vpabsb\0" "vpabsd\0" "vpabsq\0" "vpabsw\0" "vpackssdw\0" - "vpacksswb\0" "vpackusdw\0" "vpackuswb\0" "vpaddb\0" "vpaddd\0" "vpaddq\0" "vpaddsb\0" "vpaddsw\0" "vpaddusb\0" - "vpaddusw\0" "vpaddw\0" "vpalignr\0" "vpand\0" "vpandd\0" "vpandn\0" "vpandnd\0" "vpandnq\0" "vpandq\0" "vpavgb\0" - "vpavgw\0" "vpblendd\0" "vpblendvb\0" "vpblendw\0" "vpbroadcastb\0" "vpbroadcastd\0" "vpbroadcastmb2d\0" - "vpbroadcastmb2q\0" "vpbroadcastq\0" "vpbroadcastw\0" "vpclmulqdq\0" "vpcmov\0" "vpcmpb\0" "vpcmpd\0" "vpcmpeqb\0" - "vpcmpeqd\0" "vpcmpeqq\0" "vpcmpeqw\0" "vpcmpestri\0" "vpcmpestrm\0" "vpcmpgtb\0" "vpcmpgtd\0" "vpcmpgtq\0" - "vpcmpgtw\0" "vpcmpistri\0" "vpcmpistrm\0" "vpcmpq\0" "vpcmpub\0" "vpcmpud\0" "vpcmpuq\0" "vpcmpuw\0" "vpcmpw\0" - "vpcomb\0" "vpcomd\0" "vpcompressb\0" "vpcompressd\0" "vpcompressq\0" "vpcompressw\0" "vpcomq\0" "vpcomub\0" - "vpcomud\0" "vpcomuq\0" "vpcomuw\0" "vpcomw\0" "vpconflictd\0" "vpconflictq\0" "vpdpbusd\0" "vpdpbusds\0" - "vpdpwssd\0" "vpdpwssds\0" "vperm2f128\0" "vperm2i128\0" "vpermb\0" "vpermd\0" "vpermi2b\0" "vpermi2d\0" - "vpermi2pd\0" "vpermi2ps\0" "vpermi2q\0" "vpermi2w\0" "vpermil2pd\0" "vpermil2ps\0" "vpermilpd\0" "vpermilps\0" - "vpermpd\0" "vpermps\0" "vpermq\0" "vpermt2b\0" "vpermt2d\0" "vpermt2pd\0" "vpermt2ps\0" "vpermt2q\0" "vpermt2w\0" - "vpermw\0" "vpexpandb\0" "vpexpandd\0" "vpexpandq\0" "vpexpandw\0" "vpextrb\0" "vpextrd\0" "vpextrq\0" "vpextrw\0" - "vpgatherdd\0" "vpgatherdq\0" "vpgatherqd\0" "vpgatherqq\0" "vphaddbd\0" "vphaddbq\0" "vphaddbw\0" "vphaddd\0" - "vphadddq\0" "vphaddsw\0" "vphaddubd\0" "vphaddubq\0" "vphaddubw\0" "vphaddudq\0" "vphadduwd\0" "vphadduwq\0" - "vphaddw\0" "vphaddwd\0" "vphaddwq\0" "vphminposuw\0" "vphsubbw\0" "vphsubd\0" "vphsubdq\0" "vphsubsw\0" "vphsubw\0" - "vphsubwd\0" "vpinsrb\0" "vpinsrd\0" "vpinsrq\0" "vpinsrw\0" "vplzcntd\0" "vplzcntq\0" "vpmacsdd\0" "vpmacsdqh\0" - "vpmacsdql\0" "vpmacssdd\0" "vpmacssdqh\0" "vpmacssdql\0" "vpmacsswd\0" "vpmacssww\0" "vpmacswd\0" "vpmacsww\0" - "vpmadcsswd\0" "vpmadcswd\0" "vpmadd52huq\0" "vpmadd52luq\0" "vpmaddubsw\0" "vpmaddwd\0" "vpmaskmovd\0" - "vpmaskmovq\0" "vpmaxsb\0" "vpmaxsd\0" "vpmaxsq\0" "vpmaxsw\0" "vpmaxub\0" "vpmaxud\0" "vpmaxuq\0" "vpmaxuw\0" - "vpminsb\0" "vpminsd\0" "vpminsq\0" "vpminsw\0" "vpminub\0" "vpminud\0" "vpminuq\0" "vpminuw\0" "vpmovb2m\0" - "vpmovd2m\0" "vpmovdb\0" "vpmovdw\0" "vpmovm2b\0" "vpmovm2d\0" "vpmovm2q\0" "vpmovm2w\0" "vpmovmskb\0" "vpmovq2m\0" - "vpmovqb\0" "vpmovqd\0" "vpmovqw\0" "vpmovsdb\0" "vpmovsdw\0" "vpmovsqb\0" "vpmovsqd\0" "vpmovsqw\0" "vpmovswb\0" - "vpmovsxbd\0" "vpmovsxbq\0" "vpmovsxbw\0" "vpmovsxdq\0" "vpmovsxwd\0" "vpmovsxwq\0" "vpmovusdb\0" "vpmovusdw\0" - "vpmovusqb\0" "vpmovusqd\0" "vpmovusqw\0" "vpmovuswb\0" "vpmovw2m\0" "vpmovwb\0" "vpmovzxbd\0" "vpmovzxbq\0" - "vpmovzxbw\0" "vpmovzxdq\0" "vpmovzxwd\0" "vpmovzxwq\0" "vpmuldq\0" "vpmulhrsw\0" "vpmulhuw\0" "vpmulhw\0" - "vpmulld\0" "vpmullq\0" "vpmullw\0" "vpmultishiftqb\0" "vpmuludq\0" "vpopcntb\0" "vpopcntd\0" "vpopcntq\0" - "vpopcntw\0" "vpor\0" "vpord\0" "vporq\0" "vpperm\0" "vprold\0" "vprolq\0" "vprolvd\0" "vprolvq\0" "vprord\0" - "vprorq\0" "vprorvd\0" "vprorvq\0" "vprotb\0" "vprotd\0" "vprotq\0" "vprotw\0" "vpsadbw\0" "vpscatterdd\0" + "rdpid\0" "rdpkru\0" "rdpmc\0" "rdpru\0" "rdrand\0" "rdseed\0" "rdsspd\0" "rdsspq\0" "rdtsc\0" "rdtscp\0" + "rmpadjust\0" "rmpupdate\0" "rol\0" "ror\0" "rorx\0" "rsm\0" "rstorssp\0" "sahf\0" "sal\0" "sar\0" "sarx\0" + "saveprevssp\0" "sbb\0" "scas\0" "serialize\0" "seta\0" "setae\0" "setb\0" "setbe\0" "setc\0" "sete\0" "setg\0" + "setge\0" "setl\0" "setle\0" "setna\0" "setnae\0" "setnb\0" "setnbe\0" "setnc\0" "setne\0" "setng\0" "setnge\0" + "setnl\0" "setnle\0" "setno\0" "setnp\0" "setns\0" "setnz\0" "seto\0" "setp\0" "setpe\0" "setpo\0" "sets\0" + "setssbsy\0" "setz\0" "sfence\0" "sgdt\0" "sha1msg1\0" "sha1msg2\0" "sha1nexte\0" "sha1rnds4\0" "sha256msg1\0" + "sha256msg2\0" "sha256rnds2\0" "shl\0" "shlx\0" "shr\0" "shrd\0" "shrx\0" "sidt\0" "skinit\0" "sldt\0" "slwpcb\0" + "smsw\0" "stac\0" "stc\0" "stgi\0" "sti\0" "stos\0" "str\0" "sttilecfg\0" "swapgs\0" "syscall\0" "sysenter\0" + "sysexit\0" "sysexit64\0" "sysret\0" "sysret64\0" "t1mskc\0" "tdpbf16ps\0" "tdpbssd\0" "tdpbsud\0" "tdpbusd\0" + "tdpbuud\0" "tileloadd\0" "tileloaddt1\0" "tilerelease\0" "tilestored\0" "tilezero\0" "tpause\0" "tzcnt\0" "tzmsk\0" + "ud0\0" "ud1\0" "ud2\0" "umonitor\0" "umwait\0" "v4fmaddps\0" "v4fmaddss\0" "v4fnmaddps\0" "v4fnmaddss\0" "vaddpd\0" + "vaddps\0" "vaddsd\0" "vaddss\0" "vaddsubpd\0" "vaddsubps\0" "vaesdec\0" "vaesdeclast\0" "vaesenc\0" "vaesenclast\0" + "vaesimc\0" "vaeskeygenassist\0" "valignd\0" "valignq\0" "vandnpd\0" "vandnps\0" "vandpd\0" "vandps\0" "vblendmb\0" + "vblendmd\0" "vblendmpd\0" "vblendmps\0" "vblendmq\0" "vblendmw\0" "vblendpd\0" "vblendps\0" "vblendvpd\0" + "vblendvps\0" "vbroadcastf128\0" "vbroadcastf32x2\0" "vbroadcastf32x4\0" "vbroadcastf32x8\0" "vbroadcastf64x2\0" + "vbroadcastf64x4\0" "vbroadcasti128\0" "vbroadcasti32x2\0" "vbroadcasti32x4\0" "vbroadcasti32x8\0" + "vbroadcasti64x2\0" "vbroadcasti64x4\0" "vbroadcastsd\0" "vbroadcastss\0" "vcmppd\0" "vcmpps\0" "vcmpsd\0" "vcmpss\0" + "vcomisd\0" "vcomiss\0" "vcompresspd\0" "vcompressps\0" "vcvtdq2pd\0" "vcvtdq2ps\0" "vcvtne2ps2bf16\0" + "vcvtneps2bf16\0" "vcvtpd2dq\0" "vcvtpd2ps\0" "vcvtpd2qq\0" "vcvtpd2udq\0" "vcvtpd2uqq\0" "vcvtph2ps\0" "vcvtps2dq\0" + "vcvtps2pd\0" "vcvtps2ph\0" "vcvtps2qq\0" "vcvtps2udq\0" "vcvtps2uqq\0" "vcvtqq2pd\0" "vcvtqq2ps\0" "vcvtsd2si\0" + "vcvtsd2ss\0" "vcvtsd2usi\0" "vcvtsi2sd\0" "vcvtsi2ss\0" "vcvtss2sd\0" "vcvtss2si\0" "vcvtss2usi\0" "vcvttpd2dq\0" + "vcvttpd2qq\0" "vcvttpd2udq\0" "vcvttpd2uqq\0" "vcvttps2dq\0" "vcvttps2qq\0" "vcvttps2udq\0" "vcvttps2uqq\0" + "vcvttsd2si\0" "vcvttsd2usi\0" "vcvttss2si\0" "vcvttss2usi\0" "vcvtudq2pd\0" "vcvtudq2ps\0" "vcvtuqq2pd\0" + "vcvtuqq2ps\0" "vcvtusi2sd\0" "vcvtusi2ss\0" "vdbpsadbw\0" "vdivpd\0" "vdivps\0" "vdivsd\0" "vdivss\0" "vdpbf16ps\0" + "vdppd\0" "vdpps\0" "verr\0" "verw\0" "vexp2pd\0" "vexp2ps\0" "vexpandpd\0" "vexpandps\0" "vextractf128\0" + "vextractf32x4\0" "vextractf32x8\0" "vextractf64x2\0" "vextractf64x4\0" "vextracti128\0" "vextracti32x4\0" + "vextracti32x8\0" "vextracti64x2\0" "vextracti64x4\0" "vextractps\0" "vfixupimmpd\0" "vfixupimmps\0" "vfixupimmsd\0" + "vfixupimmss\0" "vfmadd132pd\0" "vfmadd132ps\0" "vfmadd132sd\0" "vfmadd132ss\0" "vfmadd213pd\0" "vfmadd213ps\0" + "vfmadd213sd\0" "vfmadd213ss\0" "vfmadd231pd\0" "vfmadd231ps\0" "vfmadd231sd\0" "vfmadd231ss\0" "vfmaddpd\0" + "vfmaddps\0" "vfmaddsd\0" "vfmaddss\0" "vfmaddsub132pd\0" "vfmaddsub132ps\0" "vfmaddsub213pd\0" "vfmaddsub213ps\0" + "vfmaddsub231pd\0" "vfmaddsub231ps\0" "vfmaddsubpd\0" "vfmaddsubps\0" "vfmsub132pd\0" "vfmsub132ps\0" "vfmsub132sd\0" + "vfmsub132ss\0" "vfmsub213pd\0" "vfmsub213ps\0" "vfmsub213sd\0" "vfmsub213ss\0" "vfmsub231pd\0" "vfmsub231ps\0" + "vfmsub231sd\0" "vfmsub231ss\0" "vfmsubadd132pd\0" "vfmsubadd132ps\0" "vfmsubadd213pd\0" "vfmsubadd213ps\0" + "vfmsubadd231pd\0" "vfmsubadd231ps\0" "vfmsubaddpd\0" "vfmsubaddps\0" "vfmsubpd\0" "vfmsubps\0" "vfmsubsd\0" + "vfmsubss\0" "vfnmadd132pd\0" "vfnmadd132ps\0" "vfnmadd132sd\0" "vfnmadd132ss\0" "vfnmadd213pd\0" "vfnmadd213ps\0" + "vfnmadd213sd\0" "vfnmadd213ss\0" "vfnmadd231pd\0" "vfnmadd231ps\0" "vfnmadd231sd\0" "vfnmadd231ss\0" "vfnmaddpd\0" + "vfnmaddps\0" "vfnmaddsd\0" "vfnmaddss\0" "vfnmsub132pd\0" "vfnmsub132ps\0" "vfnmsub132sd\0" "vfnmsub132ss\0" + "vfnmsub213pd\0" "vfnmsub213ps\0" "vfnmsub213sd\0" "vfnmsub213ss\0" "vfnmsub231pd\0" "vfnmsub231ps\0" + "vfnmsub231sd\0" "vfnmsub231ss\0" "vfnmsubpd\0" "vfnmsubps\0" "vfnmsubsd\0" "vfnmsubss\0" "vfpclasspd\0" + "vfpclassps\0" "vfpclasssd\0" "vfpclassss\0" "vfrczpd\0" "vfrczps\0" "vfrczsd\0" "vfrczss\0" "vgatherdpd\0" + "vgatherdps\0" "vgatherpf0dpd\0" "vgatherpf0dps\0" "vgatherpf0qpd\0" "vgatherpf0qps\0" "vgatherpf1dpd\0" + "vgatherpf1dps\0" "vgatherpf1qpd\0" "vgatherpf1qps\0" "vgatherqpd\0" "vgatherqps\0" "vgetexppd\0" "vgetexpps\0" + "vgetexpsd\0" "vgetexpss\0" "vgetmantpd\0" "vgetmantps\0" "vgetmantsd\0" "vgetmantss\0" "vgf2p8affineinvqb\0" + "vgf2p8affineqb\0" "vgf2p8mulb\0" "vhaddpd\0" "vhaddps\0" "vhsubpd\0" "vhsubps\0" "vinsertf128\0" "vinsertf32x4\0" + "vinsertf32x8\0" "vinsertf64x2\0" "vinsertf64x4\0" "vinserti128\0" "vinserti32x4\0" "vinserti32x8\0" "vinserti64x2\0" + "vinserti64x4\0" "vinsertps\0" "vlddqu\0" "vldmxcsr\0" "vmaskmovdqu\0" "vmaskmovpd\0" "vmaskmovps\0" "vmaxpd\0" + "vmaxps\0" "vmaxsd\0" "vmaxss\0" "vmcall\0" "vmclear\0" "vmfunc\0" "vminpd\0" "vminps\0" "vminsd\0" "vminss\0" + "vmlaunch\0" "vmload\0" "vmmcall\0" "vmovapd\0" "vmovaps\0" "vmovd\0" "vmovddup\0" "vmovdqa\0" "vmovdqa32\0" + "vmovdqa64\0" "vmovdqu\0" "vmovdqu16\0" "vmovdqu32\0" "vmovdqu64\0" "vmovdqu8\0" "vmovhlps\0" "vmovhpd\0" "vmovhps\0" + "vmovlhps\0" "vmovlpd\0" "vmovlps\0" "vmovmskpd\0" "vmovmskps\0" "vmovntdq\0" "vmovntdqa\0" "vmovntpd\0" "vmovntps\0" + "vmovq\0" "vmovsd\0" "vmovshdup\0" "vmovsldup\0" "vmovss\0" "vmovupd\0" "vmovups\0" "vmpsadbw\0" "vmptrld\0" + "vmptrst\0" "vmread\0" "vmresume\0" "vmrun\0" "vmsave\0" "vmulpd\0" "vmulps\0" "vmulsd\0" "vmulss\0" "vmwrite\0" + "vmxon\0" "vorpd\0" "vorps\0" "vp2intersectd\0" "vp2intersectq\0" "vp4dpwssd\0" "vp4dpwssds\0" "vpabsb\0" "vpabsd\0" + "vpabsq\0" "vpabsw\0" "vpackssdw\0" "vpacksswb\0" "vpackusdw\0" "vpackuswb\0" "vpaddb\0" "vpaddd\0" "vpaddq\0" + "vpaddsb\0" "vpaddsw\0" "vpaddusb\0" "vpaddusw\0" "vpaddw\0" "vpalignr\0" "vpand\0" "vpandd\0" "vpandn\0" "vpandnd\0" + "vpandnq\0" "vpandq\0" "vpavgb\0" "vpavgw\0" "vpblendd\0" "vpblendvb\0" "vpblendw\0" "vpbroadcastb\0" + "vpbroadcastd\0" "vpbroadcastmb2d\0" "vpbroadcastmb2q\0" "vpbroadcastq\0" "vpbroadcastw\0" "vpclmulqdq\0" "vpcmov\0" + "vpcmpb\0" "vpcmpd\0" "vpcmpeqb\0" "vpcmpeqd\0" "vpcmpeqq\0" "vpcmpeqw\0" "vpcmpestri\0" "vpcmpestrm\0" "vpcmpgtb\0" + "vpcmpgtd\0" "vpcmpgtq\0" "vpcmpgtw\0" "vpcmpistri\0" "vpcmpistrm\0" "vpcmpq\0" "vpcmpub\0" "vpcmpud\0" "vpcmpuq\0" + "vpcmpuw\0" "vpcmpw\0" "vpcomb\0" "vpcomd\0" "vpcompressb\0" "vpcompressd\0" "vpcompressq\0" "vpcompressw\0" + "vpcomq\0" "vpcomub\0" "vpcomud\0" "vpcomuq\0" "vpcomuw\0" "vpcomw\0" "vpconflictd\0" "vpconflictq\0" "vpdpbusd\0" + "vpdpbusds\0" "vpdpwssd\0" "vpdpwssds\0" "vperm2f128\0" "vperm2i128\0" "vpermb\0" "vpermd\0" "vpermi2b\0" + "vpermi2d\0" "vpermi2pd\0" "vpermi2ps\0" "vpermi2q\0" "vpermi2w\0" "vpermil2pd\0" "vpermil2ps\0" "vpermilpd\0" + "vpermilps\0" "vpermpd\0" "vpermps\0" "vpermq\0" "vpermt2b\0" "vpermt2d\0" "vpermt2pd\0" "vpermt2ps\0" "vpermt2q\0" + "vpermt2w\0" "vpermw\0" "vpexpandb\0" "vpexpandd\0" "vpexpandq\0" "vpexpandw\0" "vpextrb\0" "vpextrd\0" "vpextrq\0" + "vpextrw\0" "vpgatherdd\0" "vpgatherdq\0" "vpgatherqd\0" "vpgatherqq\0" "vphaddbd\0" "vphaddbq\0" "vphaddbw\0" + "vphaddd\0" "vphadddq\0" "vphaddsw\0" "vphaddubd\0" "vphaddubq\0" "vphaddubw\0" "vphaddudq\0" "vphadduwd\0" + "vphadduwq\0" "vphaddw\0" "vphaddwd\0" "vphaddwq\0" "vphminposuw\0" "vphsubbw\0" "vphsubd\0" "vphsubdq\0" + "vphsubsw\0" "vphsubw\0" "vphsubwd\0" "vpinsrb\0" "vpinsrd\0" "vpinsrq\0" "vpinsrw\0" "vplzcntd\0" "vplzcntq\0" + "vpmacsdd\0" "vpmacsdqh\0" "vpmacsdql\0" "vpmacssdd\0" "vpmacssdqh\0" "vpmacssdql\0" "vpmacsswd\0" "vpmacssww\0" + "vpmacswd\0" "vpmacsww\0" "vpmadcsswd\0" "vpmadcswd\0" "vpmadd52huq\0" "vpmadd52luq\0" "vpmaddubsw\0" "vpmaddwd\0" + "vpmaskmovd\0" "vpmaskmovq\0" "vpmaxsb\0" "vpmaxsd\0" "vpmaxsq\0" "vpmaxsw\0" "vpmaxub\0" "vpmaxud\0" "vpmaxuq\0" + "vpmaxuw\0" "vpminsb\0" "vpminsd\0" "vpminsq\0" "vpminsw\0" "vpminub\0" "vpminud\0" "vpminuq\0" "vpminuw\0" + "vpmovb2m\0" "vpmovd2m\0" "vpmovdb\0" "vpmovdw\0" "vpmovm2b\0" "vpmovm2d\0" "vpmovm2q\0" "vpmovm2w\0" "vpmovmskb\0" + "vpmovq2m\0" "vpmovqb\0" "vpmovqd\0" "vpmovqw\0" "vpmovsdb\0" "vpmovsdw\0" "vpmovsqb\0" "vpmovsqd\0" "vpmovsqw\0" + "vpmovswb\0" "vpmovsxbd\0" "vpmovsxbq\0" "vpmovsxbw\0" "vpmovsxdq\0" "vpmovsxwd\0" "vpmovsxwq\0" "vpmovusdb\0" + "vpmovusdw\0" "vpmovusqb\0" "vpmovusqd\0" "vpmovusqw\0" "vpmovuswb\0" "vpmovw2m\0" "vpmovwb\0" "vpmovzxbd\0" + "vpmovzxbq\0" "vpmovzxbw\0" "vpmovzxdq\0" "vpmovzxwd\0" "vpmovzxwq\0" "vpmuldq\0" "vpmulhrsw\0" "vpmulhuw\0" + "vpmulhw\0" "vpmulld\0" "vpmullq\0" "vpmullw\0" "vpmultishiftqb\0" "vpmuludq\0" "vpopcntb\0" "vpopcntd\0" + "vpopcntq\0" "vpopcntw\0" "vpor\0" "vpord\0" "vporq\0" "vpperm\0" "vprold\0" "vprolq\0" "vprolvd\0" "vprolvq\0" + "vprord\0" "vprorq\0" "vprorvd\0" "vprorvq\0" "vprotb\0" "vprotd\0" "vprotq\0" "vprotw\0" "vpsadbw\0" "vpscatterdd\0" "vpscatterdq\0" "vpscatterqd\0" "vpscatterqq\0" "vpshab\0" "vpshad\0" "vpshaq\0" "vpshaw\0" "vpshlb\0" "vpshld\0" "vpshldd\0" "vpshldq\0" "vpshldvd\0" "vpshldvq\0" "vpshldvw\0" "vpshldw\0" "vpshlq\0" "vpshlw\0" "vpshrdd\0" "vpshrdq\0" "vpshrdvd\0" "vpshrdvq\0" "vpshrdvw\0" "vpshrdw\0" "vpshufb\0" "vpshufbitqmb\0" "vpshufd\0" "vpshufhw\0" @@ -2785,9 +2819,9 @@ const char InstDB::_nameData[] = "vshuff64x2\0" "vshufi32x4\0" "vshufi64x2\0" "vshufpd\0" "vshufps\0" "vsqrtpd\0" "vsqrtps\0" "vsqrtsd\0" "vsqrtss\0" "vstmxcsr\0" "vsubpd\0" "vsubps\0" "vsubsd\0" "vsubss\0" "vtestpd\0" "vtestps\0" "vucomisd\0" "vucomiss\0" "vunpckhpd\0" "vunpckhps\0" "vunpcklpd\0" "vunpcklps\0" "vxorpd\0" "vxorps\0" "vzeroall\0" "vzeroupper\0" "wbinvd\0" - "wbnoinvd\0" "wrfsbase\0" "wrgsbase\0" "wrmsr\0" "xabort\0" "xadd\0" "xbegin\0" "xend\0" "xgetbv\0" "xlatb\0" - "xresldtrk\0" "xrstors\0" "xrstors64\0" "xsavec\0" "xsavec64\0" "xsaveopt\0" "xsaveopt64\0" "xsaves\0" "xsaves64\0" - "xsetbv\0" "xsusldtrk\0" "xtest"; + "wbnoinvd\0" "wrfsbase\0" "wrgsbase\0" "wrmsr\0" "wrssd\0" "wrssq\0" "wrussd\0" "wrussq\0" "xabort\0" "xadd\0" + "xbegin\0" "xend\0" "xgetbv\0" "xlatb\0" "xresldtrk\0" "xrstors\0" "xrstors64\0" "xsavec\0" "xsavec64\0" "xsaveopt\0" + "xsaveopt64\0" "xsaves\0" "xsaves64\0" "xsetbv\0" "xsusldtrk\0" "xtest"; const InstDB::InstNameIndex InstDB::instNameIndex[26] = { { Inst::kIdAaa , Inst::kIdArpl + 1 }, @@ -2807,12 +2841,12 @@ const InstDB::InstNameIndex InstDB::instNameIndex[26] = { { Inst::kIdOr , Inst::kIdOuts + 1 }, { Inst::kIdPabsb , Inst::kIdPxor + 1 }, { Inst::kIdNone , Inst::kIdNone + 1 }, - { Inst::kIdRcl , Inst::kIdRsqrtss + 1 }, + { Inst::kIdRcl , Inst::kIdRstorssp + 1 }, { Inst::kIdSahf , Inst::kIdSysret64 + 1 }, { Inst::kIdT1mskc , Inst::kIdTzmsk + 1 }, { Inst::kIdUcomisd , Inst::kIdUnpcklps + 1 }, { Inst::kIdV4fmaddps , Inst::kIdVzeroupper + 1 }, - { Inst::kIdWbinvd , Inst::kIdWrmsr + 1 }, + { Inst::kIdWbinvd , Inst::kIdWrussq + 1 }, { Inst::kIdXabort , Inst::kIdXtest + 1 }, { Inst::kIdNone , Inst::kIdNone + 1 }, { Inst::kIdNone , Inst::kIdNone + 1 } @@ -2859,7 +2893,7 @@ const InstDB::InstSignature InstDB::_instSignatureTable[] = { ROW(2, 1, 1, 0, 25 , 26 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32|r64|m64|mem, i8} ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8|mem, r8lo|r8hi} ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // #23 {r32|m32|mem, r32} ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} ROW(2, 1, 1, 0, 6 , 29 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} @@ -2888,7 +2922,7 @@ const InstDB::InstSignature InstDB::_instSignatureTable[] = { ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // #49 {r8lo|r8hi|m8|mem, r8lo|r8hi} ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} - ROW(2, 0, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} + ROW(2, 0, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // #52 {r64|m64|mem, r64} ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} ROW(2, 1, 1, 0, 6 , 29 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} @@ -3147,7 +3181,7 @@ const InstDB::InstSignature InstDB::_instSignatureTable[] = { ROW(2, 1, 1, 0, 57 , 118, 0 , 0 , 0 , 0 ), // #308 {mm, i8|u8|mm|m64|mem} ROW(2, 1, 1, 0, 45 , 54 , 0 , 0 , 0 , 0 ), // {xmm, i8|u8|xmm|m128|mem} ROW(1, 1, 0, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #310 {r32} - ROW(1, 0, 1, 0, 8 , 0 , 0 , 0 , 0 , 0 ), // {r64} + ROW(1, 0, 1, 0, 8 , 0 , 0 , 0 , 0 , 0 ), // #311 {r64} ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #312 {} ROW(1, 1, 1, 0, 119, 0 , 0 , 0 , 0 , 0 ), // {u16} ROW(3, 1, 1, 0, 6 , 28 , 10 , 0 , 0 , 0 ), // #314 {r32, r32|m32|mem, i8|u8} @@ -3191,124 +3225,126 @@ const InstDB::InstSignature InstDB::_instSignatureTable[] = { ROW(1, 1, 1, 1, 33 , 0 , 0 , 0 , 0 , 0 ), // #352 {} ROW(2, 1, 1, 2, 35 , 36 , 0 , 0 , 0 , 0 ), // #353 {, } ROW(1, 1, 1, 0, 91 , 0 , 0 , 0 , 0 , 0 ), // #354 {mem} - ROW(1, 1, 1, 1, 125, 0 , 0 , 0 , 0 , 0 ), // #355 {} - ROW(2, 1, 1, 2, 126, 127, 0 , 0 , 0 , 0 ), // #356 {, } - ROW(3, 1, 1, 0, 45 , 60 , 10 , 0 , 0 , 0 ), // #357 {xmm, xmm|m64|mem, i8|u8} - ROW(3, 1, 1, 0, 45 , 87 , 10 , 0 , 0 , 0 ), // #358 {xmm, xmm|m32|mem, i8|u8} - ROW(5, 0, 1, 4, 47 , 37 , 38 , 128, 129, 0 ), // #359 {m128|mem, , , , } - ROW(5, 1, 1, 4, 30 , 35 , 36 , 99 , 130, 0 ), // #360 {m64|mem, , , , } - ROW(4, 1, 1, 4, 36 , 130, 99 , 35 , 0 , 0 ), // #361 {, , , } - ROW(2, 0, 1, 2, 37 , 38 , 0 , 0 , 0 , 0 ), // #362 {, } - ROW(2, 1, 1, 0, 57 , 46 , 0 , 0 , 0 , 0 ), // #363 {mm, xmm|m128|mem} - ROW(2, 1, 1, 0, 45 , 117, 0 , 0 , 0 , 0 ), // #364 {xmm, mm|m64|mem} - ROW(2, 1, 1, 0, 57 , 60 , 0 , 0 , 0 , 0 ), // #365 {mm, xmm|m64|mem} - ROW(2, 1, 1, 0, 114, 60 , 0 , 0 , 0 , 0 ), // #366 {r32|r64, xmm|m64|mem} - ROW(2, 1, 1, 0, 45 , 131, 0 , 0 , 0 , 0 ), // #367 {xmm, r32|m32|mem|r64|m64} - ROW(2, 1, 1, 0, 114, 87 , 0 , 0 , 0 , 0 ), // #368 {r32|r64, xmm|m32|mem} - ROW(2, 1, 1, 2, 34 , 33 , 0 , 0 , 0 , 0 ), // #369 {, } - ROW(1, 1, 1, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #370 {} - ROW(2, 1, 1, 0, 12 , 10 , 0 , 0 , 0 , 0 ), // #371 {i16|u16, i8|u8} - ROW(3, 1, 1, 0, 28 , 45 , 10 , 0 , 0 , 0 ), // #372 {r32|m32|mem, xmm, i8|u8} - ROW(1, 1, 1, 0, 80 , 0 , 0 , 0 , 0 , 0 ), // #373 {m80|mem} - ROW(1, 1, 1, 0, 132, 0 , 0 , 0 , 0 , 0 ), // #374 {m16|m32} - ROW(1, 1, 1, 0, 133, 0 , 0 , 0 , 0 , 0 ), // #375 {m16|m32|m64} - ROW(1, 1, 1, 0, 134, 0 , 0 , 0 , 0 , 0 ), // #376 {m32|m64|m80|st} - ROW(1, 1, 1, 0, 21 , 0 , 0 , 0 , 0 , 0 ), // #377 {m16|mem} - ROW(1, 1, 1, 0, 135, 0 , 0 , 0 , 0 , 0 ), // #378 {ax|m16|mem} - ROW(1, 0, 1, 0, 91 , 0 , 0 , 0 , 0 , 0 ), // #379 {mem} - ROW(2, 1, 1, 0, 136, 137, 0 , 0 , 0 , 0 ), // #380 {al|ax|eax, i8|u8|dx} - ROW(2, 1, 1, 0, 138, 139, 0 , 0 , 0 , 0 ), // #381 {es:[memBase|zdi], dx} - ROW(1, 1, 1, 0, 10 , 0 , 0 , 0 , 0 , 0 ), // #382 {i8|u8} - ROW(0, 1, 0, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #383 {} - ROW(0, 0, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #384 {} - ROW(3, 1, 1, 0, 84 , 84 , 84 , 0 , 0 , 0 ), // #385 {k, k, k} - ROW(2, 1, 1, 0, 84 , 84 , 0 , 0 , 0 , 0 ), // #386 {k, k} - ROW(3, 1, 1, 0, 84 , 84 , 10 , 0 , 0 , 0 ), // #387 {k, k, i8|u8} - ROW(1, 1, 1, 1, 140, 0 , 0 , 0 , 0 , 0 ), // #388 {} - ROW(1, 1, 1, 0, 29 , 0 , 0 , 0 , 0 , 0 ), // #389 {m32|mem} - ROW(1, 0, 1, 0, 53 , 0 , 0 , 0 , 0 , 0 ), // #390 {m512|mem} - ROW(2, 1, 1, 0, 124, 141, 0 , 0 , 0 , 0 ), // #391 {r16|r32|r64, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024} - ROW(1, 1, 1, 0, 27 , 0 , 0 , 0 , 0 , 0 ), // #392 {r16|m16|mem} - ROW(1, 1, 1, 0, 114, 0 , 0 , 0 , 0 , 0 ), // #393 {r32|r64} - ROW(2, 1, 1, 2, 142, 126, 0 , 0 , 0 , 0 ), // #394 {, } - ROW(3, 1, 1, 0, 114, 28 , 14 , 0 , 0 , 0 ), // #395 {r32|r64, r32|m32|mem, i32|u32} - ROW(3, 1, 1, 1, 45 , 45 , 143, 0 , 0 , 0 ), // #396 {xmm, xmm, } - ROW(3, 1, 1, 1, 57 , 57 , 143, 0 , 0 , 0 ), // #397 {mm, mm, } - ROW(3, 1, 1, 3, 125, 99 , 35 , 0 , 0 , 0 ), // #398 {, , } - ROW(2, 1, 1, 0, 97 , 53 , 0 , 0 , 0 , 0 ), // #399 {es:[memBase], m512|mem} - ROW(2, 1, 1, 0, 57 , 45 , 0 , 0 , 0 , 0 ), // #400 {mm, xmm} - ROW(2, 1, 1, 0, 6 , 45 , 0 , 0 , 0 , 0 ), // #401 {r32, xmm} - ROW(2, 1, 1, 0, 30 , 57 , 0 , 0 , 0 , 0 ), // #402 {m64|mem, mm} - ROW(2, 1, 1, 0, 45 , 57 , 0 , 0 , 0 , 0 ), // #403 {xmm, mm} - ROW(2, 1, 1, 2, 127, 126, 0 , 0 , 0 , 0 ), // #404 {, } - ROW(2, 1, 1, 2, 36 , 99 , 0 , 0 , 0 , 0 ), // #405 {, } - ROW(3, 1, 1, 3, 36 , 99 , 130, 0 , 0 , 0 ), // #406 {, , } - ROW(2, 1, 1, 0, 144, 136, 0 , 0 , 0 , 0 ), // #407 {u8|dx, al|ax|eax} - ROW(2, 1, 1, 0, 139, 145, 0 , 0 , 0 , 0 ), // #408 {dx, ds:[memBase|zsi]} - ROW(6, 1, 1, 3, 45 , 46 , 10 , 99 , 36 , 35 ), // #409 {xmm, xmm|m128|mem, i8|u8, , , } - ROW(6, 1, 1, 3, 45 , 46 , 10 , 122, 36 , 35 ), // #410 {xmm, xmm|m128|mem, i8|u8, , , } - ROW(4, 1, 1, 1, 45 , 46 , 10 , 99 , 0 , 0 ), // #411 {xmm, xmm|m128|mem, i8|u8, } - ROW(4, 1, 1, 1, 45 , 46 , 10 , 122, 0 , 0 ), // #412 {xmm, xmm|m128|mem, i8|u8, } - ROW(3, 1, 1, 0, 109, 45 , 10 , 0 , 0 , 0 ), // #413 {r32|m8|mem|r8lo|r8hi|r16, xmm, i8|u8} - ROW(3, 0, 1, 0, 15 , 45 , 10 , 0 , 0 , 0 ), // #414 {r64|m64|mem, xmm, i8|u8} - ROW(3, 1, 1, 0, 45 , 109, 10 , 0 , 0 , 0 ), // #415 {xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8} - ROW(3, 1, 1, 0, 45 , 28 , 10 , 0 , 0 , 0 ), // #416 {xmm, r32|m32|mem, i8|u8} - ROW(3, 0, 1, 0, 45 , 15 , 10 , 0 , 0 , 0 ), // #417 {xmm, r64|m64|mem, i8|u8} - ROW(3, 1, 1, 0, 59 , 113, 10 , 0 , 0 , 0 ), // #418 {mm|xmm, r32|m16|mem|r16, i8|u8} - ROW(2, 1, 1, 0, 6 , 59 , 0 , 0 , 0 , 0 ), // #419 {r32, mm|xmm} - ROW(2, 1, 1, 0, 45 , 10 , 0 , 0 , 0 , 0 ), // #420 {xmm, i8|u8} - ROW(2, 1, 1, 0, 31 , 81 , 0 , 0 , 0 , 0 ), // #421 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, cl|i8|u8} - ROW(1, 0, 1, 0, 114, 0 , 0 , 0 , 0 , 0 ), // #422 {r32|r64} - ROW(3, 1, 1, 3, 35 , 36 , 99 , 0 , 0 , 0 ), // #423 {, , } - ROW(3, 1, 1, 3, 99 , 35 , 36 , 0 , 0 , 0 ), // #424 {, , } - ROW(2, 1, 1, 2, 142, 127, 0 , 0 , 0 , 0 ), // #425 {, } - ROW(1, 1, 1, 0, 1 , 0 , 0 , 0 , 0 , 0 ), // #426 {r8lo|r8hi|m8|mem} - ROW(1, 1, 1, 0, 146, 0 , 0 , 0 , 0 , 0 ), // #427 {r16|m16|mem|r32|r64} - ROW(2, 1, 1, 2, 127, 142, 0 , 0 , 0 , 0 ), // #428 {, } - ROW(3, 0, 1, 0, 147, 147, 147, 0 , 0 , 0 ), // #429 {tmm, tmm, tmm} - ROW(2, 0, 1, 0, 147, 91 , 0 , 0 , 0 , 0 ), // #430 {tmm, tmem} - ROW(2, 0, 1, 0, 91 , 147, 0 , 0 , 0 , 0 ), // #431 {tmem, tmm} - ROW(1, 0, 1, 0, 147, 0 , 0 , 0 , 0 , 0 ), // #432 {tmm} - ROW(3, 1, 1, 2, 6 , 35 , 36 , 0 , 0 , 0 ), // #433 {r32, , } - ROW(1, 1, 1, 0, 148, 0 , 0 , 0 , 0 , 0 ), // #434 {ds:[memBase]} - ROW(6, 1, 1, 0, 51 , 51 , 51 , 51 , 51 , 47 ), // #435 {zmm, zmm, zmm, zmm, zmm, m128|mem} - ROW(6, 1, 1, 0, 45 , 45 , 45 , 45 , 45 , 47 ), // #436 {xmm, xmm, xmm, xmm, xmm, m128|mem} - ROW(3, 1, 1, 0, 45 , 45 , 60 , 0 , 0 , 0 ), // #437 {xmm, xmm, xmm|m64|mem} - ROW(3, 1, 1, 0, 45 , 45 , 87 , 0 , 0 , 0 ), // #438 {xmm, xmm, xmm|m32|mem} - ROW(2, 1, 1, 0, 48 , 47 , 0 , 0 , 0 , 0 ), // #439 {ymm, m128|mem} - ROW(2, 1, 1, 0, 149, 60 , 0 , 0 , 0 , 0 ), // #440 {ymm|zmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 149, 47 , 0 , 0 , 0 , 0 ), // #441 {ymm|zmm, m128|mem} - ROW(2, 1, 1, 0, 51 , 50 , 0 , 0 , 0 , 0 ), // #442 {zmm, m256|mem} - ROW(2, 1, 1, 0, 150, 60 , 0 , 0 , 0 , 0 ), // #443 {xmm|ymm|zmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 150, 87 , 0 , 0 , 0 , 0 ), // #444 {xmm|ymm|zmm, m32|mem|xmm} - ROW(4, 1, 1, 0, 82 , 45 , 60 , 10 , 0 , 0 ), // #445 {xmm|k, xmm, xmm|m64|mem, i8|u8} - ROW(4, 1, 1, 0, 82 , 45 , 87 , 10 , 0 , 0 ), // #446 {xmm|k, xmm, xmm|m32|mem, i8|u8} - ROW(3, 1, 1, 0, 45 , 45 , 131, 0 , 0 , 0 ), // #447 {xmm, xmm, r32|m32|mem|r64|m64} - ROW(3, 1, 1, 0, 46 , 149, 10 , 0 , 0 , 0 ), // #448 {xmm|m128|mem, ymm|zmm, i8|u8} - ROW(4, 1, 1, 0, 45 , 45 , 60 , 10 , 0 , 0 ), // #449 {xmm, xmm, xmm|m64|mem, i8|u8} - ROW(4, 1, 1, 0, 45 , 45 , 87 , 10 , 0 , 0 ), // #450 {xmm, xmm, xmm|m32|mem, i8|u8} - ROW(3, 1, 1, 0, 84 , 151, 10 , 0 , 0 , 0 ), // #451 {k, xmm|m128|ymm|m256|zmm|m512, i8|u8} - ROW(3, 1, 1, 0, 84 , 60 , 10 , 0 , 0 , 0 ), // #452 {k, xmm|m64|mem, i8|u8} - ROW(3, 1, 1, 0, 84 , 87 , 10 , 0 , 0 , 0 ), // #453 {k, xmm|m32|mem, i8|u8} - ROW(1, 1, 1, 0, 62 , 0 , 0 , 0 , 0 , 0 ), // #454 {vm32y} - ROW(1, 1, 1, 0, 63 , 0 , 0 , 0 , 0 , 0 ), // #455 {vm32z} - ROW(1, 1, 1, 0, 66 , 0 , 0 , 0 , 0 , 0 ), // #456 {vm64z} - ROW(4, 1, 1, 0, 51 , 51 , 49 , 10 , 0 , 0 ), // #457 {zmm, zmm, ymm|m256|mem, i8|u8} - ROW(1, 1, 1, 0, 30 , 0 , 0 , 0 , 0 , 0 ), // #458 {m64|mem} - ROW(2, 1, 1, 0, 6 , 86 , 0 , 0 , 0 , 0 ), // #459 {r32, xmm|ymm} - ROW(2, 1, 1, 0, 150, 152, 0 , 0 , 0 , 0 ), // #460 {xmm|ymm|zmm, xmm|m8|mem|r32|r8lo|r8hi|r16} - ROW(2, 1, 1, 0, 150, 153, 0 , 0 , 0 , 0 ), // #461 {xmm|ymm|zmm, xmm|m32|mem|r32} - ROW(2, 1, 1, 0, 150, 84 , 0 , 0 , 0 , 0 ), // #462 {xmm|ymm|zmm, k} - ROW(2, 1, 1, 0, 150, 154, 0 , 0 , 0 , 0 ), // #463 {xmm|ymm|zmm, xmm|m16|mem|r32|r16} - ROW(3, 1, 1, 0, 113, 45 , 10 , 0 , 0 , 0 ), // #464 {r32|m16|mem|r16, xmm, i8|u8} - ROW(4, 1, 1, 0, 45 , 45 , 109, 10 , 0 , 0 ), // #465 {xmm, xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8} - ROW(4, 1, 1, 0, 45 , 45 , 28 , 10 , 0 , 0 ), // #466 {xmm, xmm, r32|m32|mem, i8|u8} - ROW(4, 0, 1, 0, 45 , 45 , 15 , 10 , 0 , 0 ), // #467 {xmm, xmm, r64|m64|mem, i8|u8} - ROW(4, 1, 1, 0, 45 , 45 , 113, 10 , 0 , 0 ), // #468 {xmm, xmm, r32|m16|mem|r16, i8|u8} - ROW(2, 1, 1, 0, 84 , 150, 0 , 0 , 0 , 0 ), // #469 {k, xmm|ymm|zmm} - ROW(1, 1, 1, 0, 102, 0 , 0 , 0 , 0 , 0 ), // #470 {rel16|rel32} - ROW(3, 1, 1, 2, 91 , 35 , 36 , 0 , 0 , 0 ), // #471 {mem, , } - ROW(3, 0, 1, 2, 91 , 35 , 36 , 0 , 0 , 0 ) // #472 {mem, , } + ROW(1, 1, 1, 0, 30 , 0 , 0 , 0 , 0 , 0 ), // #355 {m64|mem} + ROW(1, 1, 1, 1, 125, 0 , 0 , 0 , 0 , 0 ), // #356 {} + ROW(2, 1, 1, 2, 126, 127, 0 , 0 , 0 , 0 ), // #357 {, } + ROW(3, 1, 1, 0, 45 , 60 , 10 , 0 , 0 , 0 ), // #358 {xmm, xmm|m64|mem, i8|u8} + ROW(3, 1, 1, 0, 45 , 87 , 10 , 0 , 0 , 0 ), // #359 {xmm, xmm|m32|mem, i8|u8} + ROW(5, 0, 1, 4, 47 , 37 , 38 , 128, 129, 0 ), // #360 {m128|mem, , , , } + ROW(5, 1, 1, 4, 30 , 35 , 36 , 99 , 130, 0 ), // #361 {m64|mem, , , , } + ROW(4, 1, 1, 4, 36 , 130, 99 , 35 , 0 , 0 ), // #362 {, , , } + ROW(2, 0, 1, 2, 37 , 38 , 0 , 0 , 0 , 0 ), // #363 {, } + ROW(2, 1, 1, 0, 57 , 46 , 0 , 0 , 0 , 0 ), // #364 {mm, xmm|m128|mem} + ROW(2, 1, 1, 0, 45 , 117, 0 , 0 , 0 , 0 ), // #365 {xmm, mm|m64|mem} + ROW(2, 1, 1, 0, 57 , 60 , 0 , 0 , 0 , 0 ), // #366 {mm, xmm|m64|mem} + ROW(2, 1, 1, 0, 114, 60 , 0 , 0 , 0 , 0 ), // #367 {r32|r64, xmm|m64|mem} + ROW(2, 1, 1, 0, 45 , 131, 0 , 0 , 0 , 0 ), // #368 {xmm, r32|m32|mem|r64|m64} + ROW(2, 1, 1, 0, 114, 87 , 0 , 0 , 0 , 0 ), // #369 {r32|r64, xmm|m32|mem} + ROW(2, 1, 1, 2, 34 , 33 , 0 , 0 , 0 , 0 ), // #370 {, } + ROW(1, 1, 1, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #371 {} + ROW(2, 1, 1, 0, 12 , 10 , 0 , 0 , 0 , 0 ), // #372 {i16|u16, i8|u8} + ROW(3, 1, 1, 0, 28 , 45 , 10 , 0 , 0 , 0 ), // #373 {r32|m32|mem, xmm, i8|u8} + ROW(1, 1, 1, 0, 80 , 0 , 0 , 0 , 0 , 0 ), // #374 {m80|mem} + ROW(1, 1, 1, 0, 132, 0 , 0 , 0 , 0 , 0 ), // #375 {m16|m32} + ROW(1, 1, 1, 0, 133, 0 , 0 , 0 , 0 , 0 ), // #376 {m16|m32|m64} + ROW(1, 1, 1, 0, 134, 0 , 0 , 0 , 0 , 0 ), // #377 {m32|m64|m80|st} + ROW(1, 1, 1, 0, 21 , 0 , 0 , 0 , 0 , 0 ), // #378 {m16|mem} + ROW(1, 1, 1, 0, 135, 0 , 0 , 0 , 0 , 0 ), // #379 {ax|m16|mem} + ROW(1, 0, 1, 0, 91 , 0 , 0 , 0 , 0 , 0 ), // #380 {mem} + ROW(2, 1, 1, 0, 136, 137, 0 , 0 , 0 , 0 ), // #381 {al|ax|eax, i8|u8|dx} + ROW(1, 1, 1, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #382 {r32} + ROW(2, 1, 1, 0, 138, 139, 0 , 0 , 0 , 0 ), // #383 {es:[memBase|zdi], dx} + ROW(1, 1, 1, 0, 10 , 0 , 0 , 0 , 0 , 0 ), // #384 {i8|u8} + ROW(0, 1, 0, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #385 {} + ROW(0, 0, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #386 {} + ROW(3, 1, 1, 0, 84 , 84 , 84 , 0 , 0 , 0 ), // #387 {k, k, k} + ROW(2, 1, 1, 0, 84 , 84 , 0 , 0 , 0 , 0 ), // #388 {k, k} + ROW(3, 1, 1, 0, 84 , 84 , 10 , 0 , 0 , 0 ), // #389 {k, k, i8|u8} + ROW(1, 1, 1, 1, 140, 0 , 0 , 0 , 0 , 0 ), // #390 {} + ROW(1, 1, 1, 0, 29 , 0 , 0 , 0 , 0 , 0 ), // #391 {m32|mem} + ROW(1, 0, 1, 0, 53 , 0 , 0 , 0 , 0 , 0 ), // #392 {m512|mem} + ROW(2, 1, 1, 0, 124, 141, 0 , 0 , 0 , 0 ), // #393 {r16|r32|r64, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024} + ROW(1, 1, 1, 0, 27 , 0 , 0 , 0 , 0 , 0 ), // #394 {r16|m16|mem} + ROW(1, 1, 1, 0, 114, 0 , 0 , 0 , 0 , 0 ), // #395 {r32|r64} + ROW(2, 1, 1, 2, 142, 126, 0 , 0 , 0 , 0 ), // #396 {, } + ROW(3, 1, 1, 0, 114, 28 , 14 , 0 , 0 , 0 ), // #397 {r32|r64, r32|m32|mem, i32|u32} + ROW(3, 1, 1, 1, 45 , 45 , 143, 0 , 0 , 0 ), // #398 {xmm, xmm, } + ROW(3, 1, 1, 1, 57 , 57 , 143, 0 , 0 , 0 ), // #399 {mm, mm, } + ROW(3, 1, 1, 3, 125, 99 , 35 , 0 , 0 , 0 ), // #400 {, , } + ROW(2, 1, 1, 0, 97 , 53 , 0 , 0 , 0 , 0 ), // #401 {es:[memBase], m512|mem} + ROW(2, 1, 1, 0, 57 , 45 , 0 , 0 , 0 , 0 ), // #402 {mm, xmm} + ROW(2, 1, 1, 0, 6 , 45 , 0 , 0 , 0 , 0 ), // #403 {r32, xmm} + ROW(2, 1, 1, 0, 30 , 57 , 0 , 0 , 0 , 0 ), // #404 {m64|mem, mm} + ROW(2, 1, 1, 0, 45 , 57 , 0 , 0 , 0 , 0 ), // #405 {xmm, mm} + ROW(2, 1, 1, 2, 127, 126, 0 , 0 , 0 , 0 ), // #406 {, } + ROW(2, 1, 1, 2, 36 , 99 , 0 , 0 , 0 , 0 ), // #407 {, } + ROW(3, 1, 1, 3, 36 , 99 , 130, 0 , 0 , 0 ), // #408 {, , } + ROW(2, 1, 1, 0, 144, 136, 0 , 0 , 0 , 0 ), // #409 {u8|dx, al|ax|eax} + ROW(2, 1, 1, 0, 139, 145, 0 , 0 , 0 , 0 ), // #410 {dx, ds:[memBase|zsi]} + ROW(6, 1, 1, 3, 45 , 46 , 10 , 99 , 36 , 35 ), // #411 {xmm, xmm|m128|mem, i8|u8, , , } + ROW(6, 1, 1, 3, 45 , 46 , 10 , 122, 36 , 35 ), // #412 {xmm, xmm|m128|mem, i8|u8, , , } + ROW(4, 1, 1, 1, 45 , 46 , 10 , 99 , 0 , 0 ), // #413 {xmm, xmm|m128|mem, i8|u8, } + ROW(4, 1, 1, 1, 45 , 46 , 10 , 122, 0 , 0 ), // #414 {xmm, xmm|m128|mem, i8|u8, } + ROW(3, 1, 1, 0, 109, 45 , 10 , 0 , 0 , 0 ), // #415 {r32|m8|mem|r8lo|r8hi|r16, xmm, i8|u8} + ROW(3, 0, 1, 0, 15 , 45 , 10 , 0 , 0 , 0 ), // #416 {r64|m64|mem, xmm, i8|u8} + ROW(3, 1, 1, 0, 45 , 109, 10 , 0 , 0 , 0 ), // #417 {xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8} + ROW(3, 1, 1, 0, 45 , 28 , 10 , 0 , 0 , 0 ), // #418 {xmm, r32|m32|mem, i8|u8} + ROW(3, 0, 1, 0, 45 , 15 , 10 , 0 , 0 , 0 ), // #419 {xmm, r64|m64|mem, i8|u8} + ROW(3, 1, 1, 0, 59 , 113, 10 , 0 , 0 , 0 ), // #420 {mm|xmm, r32|m16|mem|r16, i8|u8} + ROW(2, 1, 1, 0, 6 , 59 , 0 , 0 , 0 , 0 ), // #421 {r32, mm|xmm} + ROW(2, 1, 1, 0, 45 , 10 , 0 , 0 , 0 , 0 ), // #422 {xmm, i8|u8} + ROW(1, 1, 1, 0, 131, 0 , 0 , 0 , 0 , 0 ), // #423 {r32|m32|mem|r64|m64} + ROW(2, 1, 1, 0, 31 , 81 , 0 , 0 , 0 , 0 ), // #424 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, cl|i8|u8} + ROW(1, 0, 1, 0, 114, 0 , 0 , 0 , 0 , 0 ), // #425 {r32|r64} + ROW(3, 1, 1, 3, 35 , 36 , 99 , 0 , 0 , 0 ), // #426 {, , } + ROW(2, 1, 1, 2, 142, 127, 0 , 0 , 0 , 0 ), // #427 {, } + ROW(1, 1, 1, 0, 1 , 0 , 0 , 0 , 0 , 0 ), // #428 {r8lo|r8hi|m8|mem} + ROW(1, 1, 1, 0, 146, 0 , 0 , 0 , 0 , 0 ), // #429 {r16|m16|mem|r32|r64} + ROW(2, 1, 1, 2, 127, 142, 0 , 0 , 0 , 0 ), // #430 {, } + ROW(3, 0, 1, 0, 147, 147, 147, 0 , 0 , 0 ), // #431 {tmm, tmm, tmm} + ROW(2, 0, 1, 0, 147, 91 , 0 , 0 , 0 , 0 ), // #432 {tmm, tmem} + ROW(2, 0, 1, 0, 91 , 147, 0 , 0 , 0 , 0 ), // #433 {tmem, tmm} + ROW(1, 0, 1, 0, 147, 0 , 0 , 0 , 0 , 0 ), // #434 {tmm} + ROW(3, 1, 1, 2, 6 , 35 , 36 , 0 , 0 , 0 ), // #435 {r32, , } + ROW(1, 1, 1, 0, 28 , 0 , 0 , 0 , 0 , 0 ), // #436 {r32|m32|mem} + ROW(1, 1, 1, 0, 148, 0 , 0 , 0 , 0 , 0 ), // #437 {ds:[memBase]} + ROW(6, 1, 1, 0, 51 , 51 , 51 , 51 , 51 , 47 ), // #438 {zmm, zmm, zmm, zmm, zmm, m128|mem} + ROW(6, 1, 1, 0, 45 , 45 , 45 , 45 , 45 , 47 ), // #439 {xmm, xmm, xmm, xmm, xmm, m128|mem} + ROW(3, 1, 1, 0, 45 , 45 , 60 , 0 , 0 , 0 ), // #440 {xmm, xmm, xmm|m64|mem} + ROW(3, 1, 1, 0, 45 , 45 , 87 , 0 , 0 , 0 ), // #441 {xmm, xmm, xmm|m32|mem} + ROW(2, 1, 1, 0, 48 , 47 , 0 , 0 , 0 , 0 ), // #442 {ymm, m128|mem} + ROW(2, 1, 1, 0, 149, 60 , 0 , 0 , 0 , 0 ), // #443 {ymm|zmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 149, 47 , 0 , 0 , 0 , 0 ), // #444 {ymm|zmm, m128|mem} + ROW(2, 1, 1, 0, 51 , 50 , 0 , 0 , 0 , 0 ), // #445 {zmm, m256|mem} + ROW(2, 1, 1, 0, 150, 60 , 0 , 0 , 0 , 0 ), // #446 {xmm|ymm|zmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 150, 87 , 0 , 0 , 0 , 0 ), // #447 {xmm|ymm|zmm, m32|mem|xmm} + ROW(4, 1, 1, 0, 82 , 45 , 60 , 10 , 0 , 0 ), // #448 {xmm|k, xmm, xmm|m64|mem, i8|u8} + ROW(4, 1, 1, 0, 82 , 45 , 87 , 10 , 0 , 0 ), // #449 {xmm|k, xmm, xmm|m32|mem, i8|u8} + ROW(3, 1, 1, 0, 45 , 45 , 131, 0 , 0 , 0 ), // #450 {xmm, xmm, r32|m32|mem|r64|m64} + ROW(3, 1, 1, 0, 46 , 149, 10 , 0 , 0 , 0 ), // #451 {xmm|m128|mem, ymm|zmm, i8|u8} + ROW(4, 1, 1, 0, 45 , 45 , 60 , 10 , 0 , 0 ), // #452 {xmm, xmm, xmm|m64|mem, i8|u8} + ROW(4, 1, 1, 0, 45 , 45 , 87 , 10 , 0 , 0 ), // #453 {xmm, xmm, xmm|m32|mem, i8|u8} + ROW(3, 1, 1, 0, 84 , 151, 10 , 0 , 0 , 0 ), // #454 {k, xmm|m128|ymm|m256|zmm|m512, i8|u8} + ROW(3, 1, 1, 0, 84 , 60 , 10 , 0 , 0 , 0 ), // #455 {k, xmm|m64|mem, i8|u8} + ROW(3, 1, 1, 0, 84 , 87 , 10 , 0 , 0 , 0 ), // #456 {k, xmm|m32|mem, i8|u8} + ROW(1, 1, 1, 0, 62 , 0 , 0 , 0 , 0 , 0 ), // #457 {vm32y} + ROW(1, 1, 1, 0, 63 , 0 , 0 , 0 , 0 , 0 ), // #458 {vm32z} + ROW(1, 1, 1, 0, 66 , 0 , 0 , 0 , 0 , 0 ), // #459 {vm64z} + ROW(4, 1, 1, 0, 51 , 51 , 49 , 10 , 0 , 0 ), // #460 {zmm, zmm, ymm|m256|mem, i8|u8} + ROW(2, 1, 1, 0, 6 , 86 , 0 , 0 , 0 , 0 ), // #461 {r32, xmm|ymm} + ROW(2, 1, 1, 0, 150, 152, 0 , 0 , 0 , 0 ), // #462 {xmm|ymm|zmm, xmm|m8|mem|r32|r8lo|r8hi|r16} + ROW(2, 1, 1, 0, 150, 153, 0 , 0 , 0 , 0 ), // #463 {xmm|ymm|zmm, xmm|m32|mem|r32} + ROW(2, 1, 1, 0, 150, 84 , 0 , 0 , 0 , 0 ), // #464 {xmm|ymm|zmm, k} + ROW(2, 1, 1, 0, 150, 154, 0 , 0 , 0 , 0 ), // #465 {xmm|ymm|zmm, xmm|m16|mem|r32|r16} + ROW(3, 1, 1, 0, 113, 45 , 10 , 0 , 0 , 0 ), // #466 {r32|m16|mem|r16, xmm, i8|u8} + ROW(4, 1, 1, 0, 45 , 45 , 109, 10 , 0 , 0 ), // #467 {xmm, xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8} + ROW(4, 1, 1, 0, 45 , 45 , 28 , 10 , 0 , 0 ), // #468 {xmm, xmm, r32|m32|mem, i8|u8} + ROW(4, 0, 1, 0, 45 , 45 , 15 , 10 , 0 , 0 ), // #469 {xmm, xmm, r64|m64|mem, i8|u8} + ROW(4, 1, 1, 0, 45 , 45 , 113, 10 , 0 , 0 ), // #470 {xmm, xmm, r32|m16|mem|r16, i8|u8} + ROW(2, 1, 1, 0, 84 , 150, 0 , 0 , 0 , 0 ), // #471 {k, xmm|ymm|zmm} + ROW(1, 1, 1, 0, 102, 0 , 0 , 0 , 0 , 0 ), // #472 {rel16|rel32} + ROW(3, 1, 1, 2, 91 , 35 , 36 , 0 , 0 , 0 ), // #473 {mem, , } + ROW(3, 0, 1, 2, 91 , 35 , 36 , 0 , 0 , 0 ) // #474 {mem, , } }; #undef ROW @@ -3489,145 +3525,146 @@ const uint8_t InstDB::rwInfoIndexA[Inst::_kIdCount] = { 0, 0, 1, 1, 0, 2, 3, 2, 4, 4, 5, 6, 4, 4, 3, 4, 4, 4, 4, 7, 0, 2, 0, 4, 4, 4, 4, 8, 0, 9, 9, 9, 9, 9, 0, 0, 0, 0, 9, 9, 9, 9, 9, 10, 10, 10, 11, 11, 12, 13, 14, 9, 9, 0, 15, 16, 16, 16, 0, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 18, 0, 0, 19, 0, 0, 0, 0, 0, 20, 21, 0, 22, 23, 24, 7, 25, 25, - 25, 24, 26, 7, 24, 27, 28, 29, 30, 31, 32, 33, 25, 25, 7, 27, 28, 33, 34, 0, - 0, 0, 0, 35, 4, 4, 5, 6, 0, 0, 0, 36, 36, 0, 0, 37, 0, 0, 38, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 38, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 38, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 4, 0, 4, 4, 35, 39, 40, - 0, 41, 0, 37, 0, 0, 0, 0, 42, 0, 43, 42, 42, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 44, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 45, 46, 47, 48, 49, 50, 51, 52, 0, 0, 0, 53, - 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 53, 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 57, 58, 0, 59, 0, 60, 0, 59, 0, 59, 0, 59, 0, 0, 0, 0, 61, 62, - 62, 62, 57, 59, 0, 0, 0, 9, 0, 0, 4, 4, 5, 6, 0, 0, 4, 4, 5, 6, 0, 0, 63, 64, - 64, 65, 46, 24, 36, 65, 51, 64, 64, 66, 67, 67, 68, 69, 69, 70, 70, 58, 58, 65, - 58, 58, 69, 69, 71, 47, 51, 72, 47, 7, 7, 46, 73, 9, 64, 64, 73, 0, 35, 4, 4, - 5, 6, 0, 74, 0, 0, 0, 0, 2, 4, 4, 75, 76, 9, 9, 9, 3, 3, 4, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 0, 3, 3, 0, 3, 77, 3, 0, 0, 0, 3, 3, 4, 3, 0, 0, 3, 3, 4, 3, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 27, 27, 77, 77, 77, 77, 77, 77, 77, 77, 77, 77, 27, 77, - 77, 77, 27, 27, 77, 77, 77, 3, 3, 3, 78, 3, 3, 3, 27, 27, 0, 0, 0, 0, 3, 3, - 4, 4, 3, 3, 4, 4, 4, 4, 3, 3, 4, 4, 79, 80, 81, 24, 24, 24, 80, 80, 81, 24, 24, - 24, 80, 4, 3, 77, 3, 3, 4, 3, 3, 0, 0, 0, 9, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, - 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 82, 3, 3, 0, 3, 3, 3, 82, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 27, 83, 3, 3, 4, 3, 3, 3, 4, 3, 0, 0, 0, 0, 0, 0, 0, 3, 84, 7, 85, 84, - 0, 0, 0, 0, 0, 0, 0, 0, 86, 0, 0, 0, 0, 84, 84, 0, 0, 0, 0, 0, 0, 7, 85, 0, - 84, 84, 0, 2, 87, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 4, 0, 4, 4, 0, 84, 0, 0, 84, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 7, 7, 26, 85, 0, 0, 0, 0, 0, 0, 88, 0, 0, 2, 4, 4, 5, - 6, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 15, 89, 89, 0, 90, 0, 0, 9, 9, 20, 21, - 0, 0, 0, 4, 4, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 91, 28, 92, 93, 92, 93, 91, 28, 92, - 93, 92, 93, 94, 95, 0, 0, 0, 0, 20, 21, 96, 96, 97, 9, 0, 73, 98, 98, 9, 98, 9, - 97, 9, 97, 0, 97, 9, 97, 9, 98, 28, 0, 28, 0, 0, 0, 33, 33, 98, 9, 98, 9, 9, - 97, 9, 97, 28, 28, 33, 33, 97, 9, 9, 98, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 99, 99, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 18, 0, 0, 19, 0, 0, 0, 0, 0, 20, 21, 0, 22, 23, 24, 7, 25, + 25, 25, 24, 26, 7, 24, 27, 28, 29, 30, 31, 32, 33, 25, 25, 7, 27, 28, 33, 34, + 0, 0, 0, 0, 35, 4, 4, 5, 6, 0, 0, 0, 0, 0, 36, 36, 0, 0, 37, 0, 0, 38, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 38, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 38, 0, 38, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 4, 0, 4, 4, 35, + 39, 40, 0, 0, 0, 41, 0, 37, 0, 0, 0, 0, 42, 0, 43, 42, 42, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 44, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 45, 46, 47, 48, 49, 50, 51, + 52, 0, 0, 0, 53, 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 53, 54, 55, 56, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 57, 58, 0, 59, 0, 60, 0, 59, 0, 59, 0, 59, 0, 0, + 0, 0, 61, 62, 62, 62, 57, 59, 0, 0, 0, 9, 0, 0, 4, 4, 5, 6, 0, 0, 4, 4, 5, 6, + 0, 0, 63, 64, 64, 65, 46, 24, 36, 65, 51, 64, 64, 66, 67, 67, 68, 69, 69, 70, + 70, 58, 58, 65, 58, 58, 69, 69, 71, 47, 51, 72, 47, 7, 7, 46, 73, 9, 64, 64, + 73, 0, 35, 4, 4, 5, 6, 0, 74, 0, 0, 0, 0, 2, 4, 4, 75, 76, 9, 9, 9, 3, 3, 4, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 0, 3, 3, 0, 3, 77, 3, 0, 0, 0, 3, 3, 4, 3, 0, 0, 3, + 3, 4, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 27, 77, 77, 77, 77, 77, 77, 77, 77, 77, + 77, 27, 77, 77, 77, 27, 27, 77, 77, 77, 3, 3, 3, 78, 3, 3, 3, 27, 27, 0, 0, + 0, 0, 3, 3, 4, 4, 3, 3, 4, 4, 4, 4, 3, 3, 4, 4, 79, 80, 81, 24, 24, 24, 80, 80, + 81, 24, 24, 24, 80, 4, 3, 77, 3, 3, 4, 3, 3, 0, 0, 0, 9, 0, 0, 0, 3, 0, 0, 0, + 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 82, 3, 3, 0, 3, 3, 3, 82, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 27, 83, 0, 3, 3, 4, 3, 3, 3, 4, 3, 0, 0, 0, 0, 0, 0, 0, + 3, 84, 7, 85, 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 86, 0, 0, 0, 0, 84, 84, 0, + 0, 0, 0, 0, 0, 7, 85, 0, 0, 84, 84, 0, 0, 2, 87, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, + 4, 0, 4, 4, 0, 84, 0, 0, 84, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 7, 26, 85, 0, 0, 0, + 0, 0, 0, 88, 0, 0, 2, 4, 4, 5, 6, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 15, + 89, 89, 0, 90, 0, 0, 9, 9, 20, 21, 0, 0, 0, 0, 0, 4, 4, 4, 4, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 91, 28, 92, 93, 92, 93, 91, 28, 92, 93, 92, 93, 94, 95, 0, 0, 0, 0, 20, 21, + 96, 96, 97, 9, 0, 73, 98, 98, 9, 98, 9, 97, 9, 97, 0, 97, 9, 97, 9, 98, 28, 0, + 28, 0, 0, 0, 33, 33, 98, 9, 98, 9, 9, 97, 9, 97, 28, 28, 33, 33, 97, 9, 9, 98, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 99, 99, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, - 9, 27, 100, 59, 59, 0, 0, 0, 0, 0, 0, 0, 0, 59, 59, 9, 9, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101, 101, 46, 102, 101, 101, 101, 101, 101, - 101, 101, 101, 0, 103, 103, 0, 69, 69, 104, 105, 65, 65, 65, 65, 106, 69, 9, 9, - 71, 101, 101, 0, 0, 0, 96, 0, 0, 0, 0, 0, 0, 0, 107, 0, 0, 0, 0, 0, 0, 0, 9, - 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 108, 33, 109, 109, 28, 110, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 96, 96, 96, 96, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, - 9, 9, 0, 0, 0, 0, 59, 59, 59, 59, 7, 7, 7, 0, 7, 0, 7, 7, 7, 7, 7, 7, 0, 7, 7, - 78, 7, 0, 7, 0, 0, 7, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 111, 111, 112, - 113, 109, 109, 109, 109, 79, 111, 114, 113, 112, 112, 113, 114, 113, 112, 113, - 115, 116, 97, 97, 97, 115, 112, 113, 114, 113, 112, 113, 111, 113, 115, 116, - 97, 97, 97, 115, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 65, 117, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 107, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 99, - 99, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 99, 99, 0, 0, - 9, 0, 0, 0, 0, 0, 65, 65, 0, 0, 0, 0, 0, 0, 0, 0, 65, 117, 0, 0, 0, 0, 0, 0, 9, - 9, 0, 0, 0, 0, 0, 0, 0, 107, 107, 20, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 118, 0, 119, 0, 0, 0, 2, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 27, 100, 59, 59, 0, 0, 0, 0, 0, 0, + 0, 0, 59, 59, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101, + 101, 46, 102, 101, 101, 101, 101, 101, 101, 101, 101, 0, 103, 103, 0, 69, 69, + 104, 105, 65, 65, 65, 65, 106, 69, 9, 9, 71, 101, 101, 0, 0, 0, 96, 0, 0, 0, 0, + 0, 0, 0, 107, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 108, 33, 109, 109, 28, 110, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 96, 96, 96, 96, + 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 59, 59, 59, 59, 7, 7, + 7, 0, 7, 0, 7, 7, 7, 7, 7, 7, 0, 7, 7, 78, 7, 0, 7, 0, 0, 7, 0, 0, 0, 0, 9, 9, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 111, 111, 112, 113, 109, 109, 109, 109, 79, 111, 114, + 113, 112, 112, 113, 114, 113, 112, 113, 115, 116, 97, 97, 97, 115, 112, 113, + 114, 113, 112, 113, 111, 113, 115, 116, 97, 97, 97, 115, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 65, + 117, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 107, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 99, 99, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 9, 9, 0, 0, 99, 99, 0, 0, 9, 0, 0, 0, 0, 0, 65, 65, 0, 0, 0, 0, 0, + 0, 0, 0, 65, 117, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 107, 107, 20, + 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 118, 119, 118, 119, 0, 120, 0, 121, + 0, 0, 0, 2, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; const uint8_t InstDB::rwInfoIndexB[Inst::_kIdCount] = { 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 3, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 5, 5, 6, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 7, 0, 0, 0, 0, 4, 8, 1, 0, 9, 0, 0, 0, 10, 10, 10, 0, 0, 0, 10, 11, 0, 0, 0, + 0, 7, 0, 0, 0, 0, 4, 8, 1, 0, 9, 0, 0, 0, 10, 10, 10, 0, 0, 11, 0, 10, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 5, 5, 0, 12, 13, 14, 15, 16, 0, 0, 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 18, 1, 1, 19, 20, 0, 0, 0, 0, 5, - 5, 0, 0, 0, 0, 21, 22, 0, 0, 23, 24, 25, 26, 0, 0, 24, 24, 24, 24, 24, 24, 24, - 24, 27, 28, 28, 27, 0, 0, 0, 23, 24, 23, 24, 0, 24, 23, 23, 23, 23, 23, 23, - 23, 0, 0, 29, 29, 29, 23, 23, 27, 0, 30, 10, 0, 0, 0, 0, 0, 0, 23, 24, 0, 0, - 0, 31, 32, 31, 33, 0, 0, 0, 0, 0, 10, 31, 0, 0, 0, 0, 34, 32, 31, 34, 33, 23, - 24, 23, 24, 0, 28, 28, 28, 28, 0, 0, 0, 24, 10, 10, 31, 31, 0, 0, 0, 0, 5, 5, - 0, 0, 0, 0, 0, 0, 20, 35, 0, 19, 0, 36, 37, 0, 0, 0, 0, 0, 10, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 38, 39, 40, 41, 38, 39, 38, 39, 40, 41, 40, 41, 0, 0, - 0, 0, 0, 0, 0, 0, 38, 39, 40, 0, 0, 0, 0, 41, 42, 43, 44, 45, 42, 43, 44, 45, - 0, 0, 0, 0, 46, 47, 48, 38, 39, 40, 41, 38, 39, 40, 41, 49, 0, 0, 50, 0, 51, 0, - 0, 0, 0, 0, 10, 0, 10, 52, 53, 52, 0, 0, 0, 0, 0, 0, 52, 54, 54, 0, 55, 56, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 57, 57, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, - 58, 0, 0, 0, 0, 59, 0, 60, 19, 61, 19, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 62, 0, 0, 0, 0, 0, 0, 6, 5, 5, 0, 0, 0, 0, 63, 64, 0, 0, - 0, 0, 65, 66, 0, 0, 3, 3, 67, 21, 68, 69, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 70, 36, 71, 72, 0, 0, + 0, 0, 0, 0, 0, 5, 5, 0, 13, 14, 15, 16, 17, 0, 0, 18, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 19, 1, 1, 20, 21, 0, 0, 0, + 0, 5, 5, 0, 0, 0, 0, 0, 0, 22, 23, 0, 0, 24, 25, 26, 27, 0, 0, 25, 25, 25, 25, + 25, 25, 25, 25, 28, 29, 29, 28, 0, 0, 0, 24, 25, 24, 25, 0, 25, 24, 24, 24, 24, + 24, 24, 24, 0, 0, 30, 30, 30, 24, 24, 28, 0, 31, 10, 0, 0, 0, 0, 0, 0, 24, + 25, 0, 0, 0, 32, 33, 32, 34, 0, 0, 0, 0, 0, 10, 32, 0, 0, 0, 0, 35, 33, 32, 35, + 34, 24, 25, 24, 25, 0, 29, 29, 29, 29, 0, 0, 0, 25, 10, 10, 32, 32, 0, 0, 0, + 0, 5, 5, 0, 0, 0, 0, 0, 0, 21, 36, 0, 20, 37, 38, 0, 39, 40, 0, 0, 0, 0, 0, 10, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 41, 42, 43, 44, 41, 42, 41, 42, 43, + 44, 43, 44, 0, 0, 0, 0, 0, 0, 0, 0, 41, 42, 43, 0, 0, 0, 0, 44, 45, 46, 47, 48, + 45, 46, 47, 48, 0, 0, 0, 0, 49, 50, 51, 41, 42, 43, 44, 41, 42, 43, 44, 52, + 0, 0, 53, 0, 54, 0, 0, 0, 0, 0, 10, 0, 10, 55, 56, 55, 0, 0, 0, 0, 0, 0, 55, 57, + 57, 0, 58, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 60, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 73, 0, 0, 0, 0, 0, 0, 0, 10, 10, 10, 10, 10, 10, 10, 0, 0, - 2, 2, 2, 74, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 75, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 76, 76, - 77, 76, 77, 78, 76, 76, 0, 79, 0, 0, 0, 0, 0, 80, 2, 2, 81, 82, 0, 0, 0, 83, 0, - 0, 4, 0, 0, 0, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, - 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 84, 0, 31, 0, 0, 0, 5, - 0, 0, 6, 0, 85, 4, 0, 85, 4, 5, 5, 31, 18, 86, 76, 86, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 87, 0, 86, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 89, 89, 89, 89, 89, - 0, 0, 0, 0, 0, 90, 91, 0, 0, 0, 0, 0, 53, 91, 0, 0, 0, 0, 92, 93, 92, 93, 3, 3, - 94, 95, 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 96, - 96, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 97, 98, 0, 0, 0, 0, 0, 0, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 99, 0, 0, 0, 0, 0, 0, 100, 0, 101, 102, 103, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101, 102, 3, 3, 3, 94, 95, - 3, 104, 3, 52, 52, 0, 0, 0, 0, 105, 106, 107, 106, 107, 105, 106, 107, 106, - 107, 21, 108, 108, 109, 110, 108, 108, 111, 112, 108, 108, 111, 112, 108, 108, - 111, 112, 113, 113, 114, 115, 108, 108, 108, 108, 108, 108, 113, 113, 108, 108, - 111, 112, 108, 108, 111, 112, 108, 108, 111, 112, 108, 108, 108, 108, 108, - 108, 113, 113, 113, 113, 114, 115, 108, 108, 111, 112, 108, 108, 111, 112, 108, - 108, 111, 112, 113, 113, 114, 115, 108, 108, 111, 112, 108, 108, 111, 112, 108, - 108, 116, 117, 113, 113, 114, 115, 118, 118, 74, 119, 0, 0, 0, 0, 120, 121, - 10, 10, 10, 10, 10, 10, 10, 10, 121, 122, 0, 0, 123, 124, 80, 80, 123, 124, - 3, 3, 3, 3, 3, 3, 3, 125, 126, 127, 126, 127, 125, 126, 127, 126, 127, 95, 0, - 50, 55, 128, 128, 3, 3, 94, 95, 0, 129, 0, 3, 3, 94, 95, 0, 130, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 131, 132, 132, 133, 134, 134, 0, 0, 0, 0, 0, 0, 0, 135, - 0, 0, 136, 0, 0, 3, 137, 129, 0, 0, 138, 130, 3, 3, 94, 95, 0, 137, 3, 3, - 139, 139, 140, 140, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 96, 3, 0, 0, 0, 0, 0, 0, 3, 113, 141, 141, 3, 3, 3, 3, 63, - 64, 3, 3, 3, 3, 65, 66, 141, 141, 141, 141, 141, 141, 104, 104, 0, 0, 0, 0, 104, - 104, 104, 104, 104, 104, 0, 0, 108, 108, 108, 108, 142, 142, 3, 3, 3, 108, - 3, 3, 108, 108, 113, 113, 143, 143, 143, 3, 143, 3, 108, 108, 108, 108, 108, - 3, 0, 0, 0, 0, 67, 21, 68, 144, 121, 120, 122, 121, 0, 0, 0, 3, 0, 3, 0, 0, 0, - 0, 0, 0, 3, 0, 0, 0, 0, 3, 0, 3, 3, 0, 145, 95, 94, 146, 0, 0, 147, 147, 147, - 147, 147, 147, 147, 147, 147, 147, 147, 147, 108, 108, 3, 3, 128, 128, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 3, 3, 3, 148, 80, 80, 3, 3, 80, 80, - 3, 3, 149, 149, 149, 149, 3, 0, 0, 0, 0, 149, 149, 149, 149, 149, 149, 3, 3, 108, - 108, 108, 3, 149, 149, 3, 3, 108, 108, 108, 3, 3, 141, 80, 80, 80, 3, 3, 3, - 150, 151, 150, 3, 3, 3, 150, 150, 150, 3, 3, 3, 150, 150, 151, 150, 3, 3, 3, - 150, 3, 3, 3, 3, 3, 3, 3, 3, 108, 108, 0, 141, 141, 141, 141, 141, 141, 141, - 141, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 123, 124, 0, 0, 123, 124, 0, 0, 123, - 124, 0, 124, 80, 80, 123, 124, 80, 80, 123, 124, 80, 80, 123, 124, 0, 0, 123, - 124, 0, 0, 123, 124, 0, 124, 3, 3, 94, 95, 0, 0, 10, 10, 10, 10, 10, 10, 10, - 10, 0, 0, 3, 3, 3, 3, 3, 3, 0, 0, 123, 124, 87, 3, 3, 94, 95, 0, 0, 0, 0, 3, - 3, 3, 3, 3, 3, 0, 0, 0, 0, 53, 53, 152, 0, 0, 0, 0, 0, 77, 0, 0, 0, 0, 0, 153, - 153, 153, 153, 154, 154, 154, 154, 154, 154, 154, 154, 152, 0, 0 + 0, 0, 0, 0, 0, 5, 61, 0, 0, 0, 0, 62, 0, 63, 20, 64, 20, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 6, 5, 5, 0, 0, + 0, 0, 66, 67, 0, 0, 0, 0, 68, 69, 0, 3, 3, 70, 22, 71, 72, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 39, + 74, 75, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 76, 0, 0, 0, 0, 0, 0, 0, 10, 10, 10, 10, 10, + 10, 10, 0, 0, 2, 2, 2, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 78, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 79, 79, 80, 79, 80, 80, 80, 79, 79, 81, 82, 0, 83, 0, 0, 0, 0, 0, 84, + 2, 2, 85, 86, 0, 0, 0, 11, 87, 0, 0, 4, 0, 0, 0, 0, 88, 88, 88, 88, 88, 88, + 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, + 88, 88, 88, 0, 88, 0, 32, 0, 0, 0, 5, 0, 0, 6, 0, 89, 4, 0, 89, 4, 5, 5, 32, + 19, 90, 79, 90, 0, 0, 0, 0, 0, 0, 0, 0, 0, 91, 0, 90, 92, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 93, 93, 93, 93, 93, 0, 0, 0, 0, 0, 94, 95, 0, 0, 0, 0, 96, + 96, 0, 56, 95, 0, 0, 0, 0, 97, 98, 97, 98, 3, 3, 99, 100, 3, 3, 3, 3, 3, 3, + 0, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 101, 101, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 3, 3, 102, 103, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 104, 0, 0, 0, 0, 0, 0, 105, 0, 106, 107, 108, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 106, 107, 3, 3, 3, 99, 100, 3, 109, 3, 55, 55, 0, + 0, 0, 0, 110, 111, 112, 111, 112, 110, 111, 112, 111, 112, 22, 113, 113, 114, + 115, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 116, 117, 118, 118, 119, + 120, 113, 113, 113, 113, 113, 113, 118, 118, 113, 113, 116, 117, 113, 113, + 116, 117, 113, 113, 116, 117, 113, 113, 113, 113, 113, 113, 118, 118, 118, 118, + 119, 120, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 116, 117, 118, + 118, 119, 120, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 121, 122, 118, + 118, 119, 120, 123, 123, 77, 124, 0, 0, 0, 0, 125, 126, 10, 10, 10, 10, 10, + 10, 10, 10, 126, 127, 0, 0, 128, 129, 84, 84, 128, 129, 3, 3, 3, 3, 3, 3, 3, 130, + 131, 132, 131, 132, 130, 131, 132, 131, 132, 100, 0, 53, 58, 133, 133, 3, + 3, 99, 100, 0, 134, 0, 3, 3, 99, 100, 0, 135, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 136, 137, 137, 138, 139, 139, 0, 0, 0, 0, 0, 0, 0, 140, 0, 0, 141, 0, 0, + 3, 11, 134, 0, 0, 142, 135, 3, 3, 99, 100, 0, 11, 3, 3, 143, 143, 144, 144, + 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 101, 3, 0, 0, 0, 0, 0, 0, 3, 118, 145, 145, 3, 3, 3, 3, 66, 67, 3, 3, 3, 3, 68, + 69, 145, 145, 145, 145, 145, 145, 109, 109, 0, 0, 0, 0, 109, 109, 109, 109, + 109, 109, 0, 0, 113, 113, 113, 113, 146, 146, 3, 3, 3, 113, 3, 3, 113, 113, 118, + 118, 147, 147, 147, 3, 147, 3, 113, 113, 113, 113, 113, 3, 0, 0, 0, 0, 70, + 22, 71, 148, 126, 125, 127, 126, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 3, 0, 3, 3, 0, 149, 100, 99, 150, 0, 0, 151, 151, 151, 151, 151, 151, 151, + 151, 151, 151, 151, 151, 113, 113, 3, 3, 133, 133, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 0, 0, 0, 0, 3, 3, 3, 152, 84, 84, 3, 3, 84, 84, 3, 3, 153, 153, 153, + 153, 3, 0, 0, 0, 0, 153, 153, 153, 153, 153, 153, 3, 3, 113, 113, 113, 3, 153, + 153, 3, 3, 113, 113, 113, 3, 3, 145, 84, 84, 84, 3, 3, 3, 154, 155, 154, 3, + 3, 3, 154, 154, 154, 3, 3, 3, 154, 154, 155, 154, 3, 3, 3, 154, 3, 3, 3, 3, + 3, 3, 3, 3, 113, 113, 0, 145, 145, 145, 145, 145, 145, 145, 145, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 128, 129, 0, 0, 128, 129, 0, 0, 128, 129, 0, 129, 84, + 84, 128, 129, 84, 84, 128, 129, 84, 84, 128, 129, 0, 0, 128, 129, 0, 0, 128, + 129, 0, 129, 3, 3, 99, 100, 0, 0, 10, 10, 10, 10, 10, 10, 10, 10, 0, 0, 3, 3, + 3, 3, 3, 3, 0, 0, 128, 129, 91, 3, 3, 99, 100, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, + 0, 0, 0, 0, 56, 56, 156, 0, 0, 0, 0, 0, 0, 0, 0, 0, 80, 0, 0, 0, 0, 0, 157, 157, + 157, 157, 158, 158, 158, 158, 158, 158, 158, 158, 156, 0, 0 }; const InstDB::RWInfo InstDB::rwInfoA[] = { - { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=919x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=932x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 1 , 0 , 0 , 0 , 0 , 0 } }, // #1 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 1 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #2 [ref=7x] { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #3 [ref=99x] @@ -3668,15 +3705,15 @@ const InstDB::RWInfo InstDB::rwInfoA[] = { { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 45, 0 , 0 , 0 , 0 } }, // #38 [ref=6x] { InstDB::RWInfo::kCategoryImul , 2 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #39 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 50, 0 , 0 , 0 , 0 } }, // #40 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 51, 50, 0 , 0 , 0 , 0 } }, // #41 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 3 , 5 , 0 , 0 , 0 , 0 } }, // #42 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 52, 50, 0 , 0 , 0 , 0 } }, // #41 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 3 , 5 , 0 , 0 , 0 , 0 } }, // #42 [ref=3x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 21, 28, 0 , 0 , 0 , 0 } }, // #43 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 52, 0 , 0 , 0 , 0 , 0 } }, // #44 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 23, { 53, 39, 0 , 0 , 0 , 0 } }, // #45 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 0 , 0 , 0 , 0 , 0 } }, // #44 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 23, { 54, 39, 0 , 0 , 0 , 0 } }, // #45 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 24, { 43, 9 , 0 , 0 , 0 , 0 } }, // #46 [ref=4x] { InstDB::RWInfo::kCategoryGeneric , 25, { 34, 7 , 0 , 0 , 0 , 0 } }, // #47 [ref=3x] { InstDB::RWInfo::kCategoryGeneric , 26, { 47, 13, 0 , 0 , 0 , 0 } }, // #48 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 39, 0 , 0 , 0 , 0 } }, // #49 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 54, 39, 0 , 0 , 0 , 0 } }, // #49 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 9 , 0 , 0 , 0 , 0 } }, // #50 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 7 , 0 , 0 , 0 , 0 } }, // #51 [ref=3x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 13, 0 , 0 , 0 , 0 } }, // #52 [ref=1x] @@ -3685,52 +3722,52 @@ const InstDB::RWInfo InstDB::rwInfoA[] = { { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 7 , 0 , 0 , 0 , 0 } }, // #55 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 13, 13, 0 , 0 , 0 , 0 } }, // #56 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 3 , 0 , 0 , 0 , 0 } }, // #57 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 10, 5 , 0 , 0 , 0 , 0 } }, // #58 [ref=5x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 10, 5 , 0 , 0 , 0 , 0 } }, // #58 [ref=5x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #59 [ref=13x] { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #60 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 49, 19, 0 , 0 , 0 , 0 } }, // #61 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 55, 0 , 0 , 0 , 0 , 0 } }, // #62 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 56, 0 , 0 , 0 , 0 , 0 } }, // #62 [ref=3x] { InstDB::RWInfo::kCategoryMov , 29, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #63 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 30, { 10, 5 , 0 , 0 , 0 , 0 } }, // #64 [ref=6x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #65 [ref=14x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 57, 0 , 0 , 0 , 0 } }, // #66 [ref=1x] - { InstDB::RWInfo::kCategoryMovh64 , 13, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #67 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 58, 7 , 0 , 0 , 0 , 0 } }, // #68 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 13, { 34, 7 , 0 , 0 , 0 , 0 } }, // #69 [ref=7x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 5 , 0 , 0 , 0 , 0 } }, // #70 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 58, 0 , 0 , 0 , 0 } }, // #66 [ref=1x] + { InstDB::RWInfo::kCategoryMovh64 , 12, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #67 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 59, 7 , 0 , 0 , 0 , 0 } }, // #68 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 34, 7 , 0 , 0 , 0 , 0 } }, // #69 [ref=7x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 54, 5 , 0 , 0 , 0 , 0 } }, // #70 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 28, { 43, 9 , 0 , 0 , 0 , 0 } }, // #71 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 20, 19, 0 , 0 , 0 , 0 } }, // #72 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 14, { 11, 3 , 0 , 0 , 0 , 0 } }, // #73 [ref=3x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 28, 0 , 0 , 0 , 0 } }, // #74 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 50, 21, 0 , 0 , 0 , 0 } }, // #75 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 50, 61, 0 , 0 , 0 , 0 } }, // #76 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 50, 62, 0 , 0 , 0 , 0 } }, // #76 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 4 , { 25, 7 , 0 , 0 , 0 , 0 } }, // #77 [ref=18x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 64, 5 , 0 , 0 , 0 , 0 } }, // #78 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 65, 5 , 0 , 0 , 0 , 0 } }, // #78 [ref=2x] { InstDB::RWInfo::kCategoryVmov1_8 , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #79 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 5 , { 10, 9 , 0 , 0 , 0 , 0 } }, // #80 [ref=4x] { InstDB::RWInfo::kCategoryGeneric , 27, { 10, 13, 0 , 0 , 0 , 0 } }, // #81 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #82 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 0 , 0 , 0 } }, // #83 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 66, 0 , 0 , 0 , 0 } }, // #84 [ref=8x] + { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 67, 0 , 0 , 0 , 0 } }, // #84 [ref=8x] { InstDB::RWInfo::kCategoryGeneric , 5 , { 36, 9 , 0 , 0 , 0 , 0 } }, // #85 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 67, 0 , 0 , 0 , 0 } }, // #86 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 68, 0 , 0 , 0 , 0 } }, // #86 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 21, 20, 0 , 0 , 0 , 0 } }, // #87 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 20, 21, 0 , 0 , 0 , 0 } }, // #88 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 70, 3 , 0 , 0 , 0 , 0 } }, // #89 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 71, 3 , 0 , 0 , 0 , 0 } }, // #89 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 42, 0 , 0 , 0 , 0 } }, // #90 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 72, 5 , 0 , 0 , 0 , 0 } }, // #91 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 11, 5 , 0 , 0 , 0 , 0 } }, // #92 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 37, { 70, 73, 0 , 0 , 0 , 0 } }, // #93 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 73, 5 , 0 , 0 , 0 , 0 } }, // #91 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 11, 5 , 0 , 0 , 0 , 0 } }, // #92 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 37, { 71, 74, 0 , 0 , 0 , 0 } }, // #93 [ref=4x] { InstDB::RWInfo::kCategoryGeneric , 38, { 11, 7 , 0 , 0 , 0 , 0 } }, // #94 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 39, { 11, 9 , 0 , 0 , 0 , 0 } }, // #95 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 11, { 11, 3 , 0 , 0 , 0 , 0 } }, // #96 [ref=7x] { InstDB::RWInfo::kCategoryVmov2_1 , 40, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #97 [ref=14x] { InstDB::RWInfo::kCategoryVmov1_2 , 14, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #98 [ref=7x] - { InstDB::RWInfo::kCategoryGeneric , 44, { 70, 42, 0 , 0 , 0 , 0 } }, // #99 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 44, { 71, 42, 0 , 0 , 0 , 0 } }, // #99 [ref=6x] { InstDB::RWInfo::kCategoryGeneric , 5 , { 43, 9 , 0 , 0 , 0 , 0 } }, // #100 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 51, { 11, 3 , 0 , 0 , 0 , 0 } }, // #101 [ref=12x] { InstDB::RWInfo::kCategoryVmovddup , 52, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #102 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 13, { 34, 57, 0 , 0 , 0 , 0 } }, // #103 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 34, 58, 0 , 0 , 0 , 0 } }, // #103 [ref=2x] { InstDB::RWInfo::kCategoryVmovmskpd , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #104 [ref=1x] { InstDB::RWInfo::kCategoryVmovmskps , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #105 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 53, { 34, 7 , 0 , 0 , 0 , 0 } }, // #106 [ref=1x] @@ -3745,12 +3782,14 @@ const InstDB::RWInfo InstDB::rwInfoA[] = { { InstDB::RWInfo::kCategoryVmov4_1 , 59, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #115 [ref=4x] { InstDB::RWInfo::kCategoryVmov8_1 , 60, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #116 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 18, { 11, 3 , 0 , 0 , 0 , 0 } }, // #117 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 2 , 0 , 0 , 0 , 0 } }, // #118 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 51, { 2 , 2 , 0 , 0 , 0 , 0 } } // #119 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 17, { 43, 9 , 0 , 0 , 0 , 0 } }, // #118 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 32, { 34, 7 , 0 , 0 , 0 , 0 } }, // #119 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 2 , 0 , 0 , 0 , 0 } }, // #120 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 51, { 2 , 2 , 0 , 0 , 0 , 0 } } // #121 [ref=1x] }; const InstDB::RWInfo InstDB::rwInfoB[] = { - { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=727x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=734x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 1 , 0 , 0 , 0 , 0 , 0 } }, // #1 [ref=5x] { InstDB::RWInfo::kCategoryGeneric , 3 , { 10, 5 , 0 , 0 , 0 , 0 } }, // #2 [ref=7x] { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 0 , 0 , 0 } }, // #3 [ref=186x] @@ -3761,169 +3800,173 @@ const InstDB::RWInfo InstDB::rwInfoB[] = { { InstDB::RWInfo::kCategoryGeneric , 11, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #8 [ref=2x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 17, 0 , 0 , 0 , 0 , 0 } }, // #9 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #10 [ref=34x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 18, 0 , 0 , 0 , 0 , 0 } }, // #11 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 4 , { 6 , 7 , 0 , 0 , 0 , 0 } }, // #12 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 8 , 9 , 0 , 0 , 0 , 0 } }, // #13 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 21, 0 , 0 , 0 } }, // #14 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 4 , 22, 17, 23, 24, 0 } }, // #15 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 13, { 25, 26, 27, 28, 29, 0 } }, // #16 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 27, 30, 31, 15, 0 , 0 } }, // #17 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 27, 0 , 0 , 0 , 0 , 0 } }, // #18 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 0 , 0 , 0 , 0 , 0 } }, // #19 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 40, 41, 3 , 0 , 0 , 0 } }, // #20 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 17, { 43, 5 , 0 , 0 , 0 , 0 } }, // #21 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #22 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 18, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #23 [ref=15x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 0 , 0 , 0 , 0 , 0 } }, // #24 [ref=16x] - { InstDB::RWInfo::kCategoryGeneric , 19, { 45, 0 , 0 , 0 , 0 , 0 } }, // #25 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 19, { 46, 0 , 0 , 0 , 0 , 0 } }, // #26 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 20, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #27 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 0 , 0 , 0 , 0 , 0 } }, // #28 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 18, { 11, 0 , 0 , 0 , 0 , 0 } }, // #29 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 21, { 13, 0 , 0 , 0 , 0 , 0 } }, // #30 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #31 [ref=8x] - { InstDB::RWInfo::kCategoryGeneric , 21, { 47, 0 , 0 , 0 , 0 , 0 } }, // #32 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 7 , { 48, 0 , 0 , 0 , 0 , 0 } }, // #33 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 20, { 11, 0 , 0 , 0 , 0 , 0 } }, // #34 [ref=2x] - { InstDB::RWInfo::kCategoryImul , 22, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #35 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 4 , 9 , 0 , 0 , 0 , 0 } }, // #36 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #37 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 39, 39, 0 , 0 , 0 } }, // #38 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 9 , 9 , 0 , 0 , 0 } }, // #39 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 7 , 7 , 0 , 0 , 0 } }, // #40 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 13, 13, 0 , 0 , 0 } }, // #41 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 53, 39, 0 , 0 , 0 , 0 } }, // #42 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 9 , 0 , 0 , 0 , 0 } }, // #43 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 7 , 0 , 0 , 0 , 0 } }, // #44 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 13, 0 , 0 , 0 , 0 } }, // #45 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 39, 39, 0 , 0 , 0 } }, // #46 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 9 , 9 , 0 , 0 , 0 } }, // #47 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 13, 13, 0 , 0 , 0 } }, // #48 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 54, 0 , 0 , 0 , 0 , 0 } }, // #49 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 28, { 9 , 0 , 0 , 0 , 0 , 0 } }, // #50 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 16, { 42, 0 , 0 , 0 , 0 , 0 } }, // #51 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 7 , { 13, 0 , 0 , 0 , 0 , 0 } }, // #52 [ref=5x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #53 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 3 , 9 , 0 , 0 , 0 , 0 } }, // #54 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 5 , 5 , 20, 0 , 0 , 0 } }, // #55 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 7 , 20, 0 , 0 , 0 } }, // #56 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 18, 28, 56, 0 , 0 , 0 } }, // #57 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 59, 41, 3 , 0 , 0 , 0 } }, // #58 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 11, 3 , 60, 0 , 0 } }, // #59 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 28, 29, 0 , 0 , 0 } }, // #60 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 10, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #61 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #62 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 62, 16, 56 } }, // #63 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 63, 16, 56 } }, // #64 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 62, 0 , 0 } }, // #65 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 63, 0 , 0 } }, // #66 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 31, { 53, 5 , 0 , 0 , 0 , 0 } }, // #67 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 32, { 34, 5 , 0 , 0 , 0 , 0 } }, // #68 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 33, { 47, 3 , 0 , 0 , 0 , 0 } }, // #69 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 15, { 4 , 39, 0 , 0 , 0 , 0 } }, // #70 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 4 , { 4 , 7 , 0 , 0 , 0 , 0 } }, // #71 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 27, { 2 , 13, 0 , 0 , 0 , 0 } }, // #72 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 10, { 65, 0 , 0 , 0 , 0 , 0 } }, // #73 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 4 , { 34, 7 , 0 , 0 , 0 , 0 } }, // #74 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 10, { 60, 0 , 0 , 0 , 0 , 0 } }, // #75 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #76 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 67, 28, 0 , 0 , 0 } }, // #77 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 28, 15, 67, 0 , 0 , 0 } }, // #78 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 67, 62, 0 , 0 , 0 } }, // #79 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #80 [ref=16x] - { InstDB::RWInfo::kCategoryGeneric , 4 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #81 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 36, 9 , 0 , 0 , 0 , 0 } }, // #82 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 68, 0 , 0 , 0 , 0 , 0 } }, // #83 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 31, { 69, 0 , 0 , 0 , 0 , 0 } }, // #84 [ref=30x] - { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 66, 0 , 0 , 0 } }, // #85 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 34, { 11, 0 , 0 , 0 , 0 , 0 } }, // #86 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 28, { 43, 0 , 0 , 0 , 0 , 0 } }, // #87 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 16, { 70, 0 , 0 , 0 , 0 , 0 } }, // #88 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 71, 42, 42, 0 , 0 , 0 } }, // #89 [ref=5x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 70, 0 , 0 , 0 , 0 , 0 } }, // #90 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 9 , 56, 16, 0 , 0 , 0 } }, // #91 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 71, 42, 42, 42, 42, 5 } }, // #92 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 4 , 5 , 5 , 5 , 5 , 5 } }, // #93 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 5 , 7 , 0 , 0 , 0 } }, // #94 [ref=8x] - { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 5 , 9 , 0 , 0 , 0 } }, // #95 [ref=9x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 3 , 0 , 0 } }, // #96 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 35, { 11, 5 , 7 , 0 , 0 , 0 } }, // #97 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 36, { 11, 5 , 9 , 0 , 0 , 0 } }, // #98 [ref=1x] - { InstDB::RWInfo::kCategoryVmov1_2 , 41, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #99 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 74, 7 , 0 , 0 , 0 } }, // #100 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 57, 3 , 0 , 0 , 0 } }, // #101 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 74, 3 , 0 , 0 , 0 } }, // #102 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 57, 9 , 0 , 0 , 0 } }, // #103 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 43, { 10, 5 , 5 , 0 , 0 , 0 } }, // #104 [ref=9x] - { InstDB::RWInfo::kCategoryGeneric , 45, { 10, 73, 0 , 0 , 0 , 0 } }, // #105 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 45, { 10, 3 , 0 , 0 , 0 , 0 } }, // #106 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 46, { 72, 42, 0 , 0 , 0 , 0 } }, // #107 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 2 , 3 , 3 , 0 , 0 , 0 } }, // #108 [ref=60x] - { InstDB::RWInfo::kCategoryGeneric , 35, { 4 , 57, 7 , 0 , 0 , 0 } }, // #109 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 36, { 4 , 74, 9 , 0 , 0 , 0 } }, // #110 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 35, { 6 , 7 , 7 , 0 , 0 , 0 } }, // #111 [ref=11x] - { InstDB::RWInfo::kCategoryGeneric , 36, { 8 , 9 , 9 , 0 , 0 , 0 } }, // #112 [ref=11x] - { InstDB::RWInfo::kCategoryGeneric , 47, { 11, 3 , 3 , 3 , 0 , 0 } }, // #113 [ref=15x] - { InstDB::RWInfo::kCategoryGeneric , 48, { 34, 7 , 7 , 7 , 0 , 0 } }, // #114 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 49, { 43, 9 , 9 , 9 , 0 , 0 } }, // #115 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 35, { 25, 7 , 7 , 0 , 0 , 0 } }, // #116 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 36, { 75, 9 , 9 , 0 , 0 , 0 } }, // #117 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 14, { 34, 3 , 0 , 0 , 0 , 0 } }, // #118 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 34, 9 , 0 , 0 , 0 , 0 } }, // #119 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #120 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #121 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 18, { 4 , 3 , 4 , 0 , 0 , 0 } }, // #122 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 57, 7 , 0 , 0 , 0 } }, // #123 [ref=11x] - { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 74, 9 , 0 , 0 , 0 } }, // #124 [ref=13x] - { InstDB::RWInfo::kCategoryGeneric , 43, { 72, 73, 5 , 0 , 0 , 0 } }, // #125 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 43, { 11, 3 , 5 , 0 , 0 , 0 } }, // #126 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 50, { 70, 42, 73, 0 , 0 , 0 } }, // #127 [ref=4x] - { InstDB::RWInfo::kCategoryVmaskmov , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #128 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 13, { 34, 0 , 0 , 0 , 0 , 0 } }, // #129 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 21, 0 , 0 , 0 , 0 , 0 } }, // #130 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 57, 57, 0 , 0 , 0 } }, // #131 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 13, { 10, 7 , 7 , 0 , 0 , 0 } }, // #132 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 7 , 7 , 0 , 0 , 0 } }, // #133 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 13, { 10, 57, 7 , 0 , 0 , 0 } }, // #134 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 57, 7 , 0 , 0 , 0 } }, // #135 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 74, 9 , 0 , 0 , 0 } }, // #136 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 13, { 7 , 0 , 0 , 0 , 0 , 0 } }, // #137 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 76, 0 , 0 , 0 , 0 , 0 } }, // #138 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 54, { 34, 11, 3 , 3 , 0 , 0 } }, // #139 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 70, 42, 42, 42, 42, 5 } }, // #140 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 6 , { 34, 3 , 3 , 0 , 0 , 0 } }, // #141 [ref=17x] - { InstDB::RWInfo::kCategoryGeneric , 50, { 72, 73, 73, 0 , 0 , 0 } }, // #142 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 3 , 0 , 0 , 0 } }, // #143 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 7 , { 47, 5 , 0 , 0 , 0 , 0 } }, // #144 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 55, { 10, 5 , 39, 0 , 0 , 0 } }, // #145 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 56, { 10, 5 , 13, 0 , 0 , 0 } }, // #146 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 43, { 10, 5 , 5 , 5 , 0 , 0 } }, // #147 [ref=12x] - { InstDB::RWInfo::kCategoryGeneric , 61, { 10, 5 , 5 , 5 , 0 , 0 } }, // #148 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 62, { 10, 5 , 5 , 0 , 0 , 0 } }, // #149 [ref=12x] - { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 5 , 0 , 0 , 0 } }, // #150 [ref=9x] - { InstDB::RWInfo::kCategoryGeneric , 63, { 11, 3 , 0 , 0 , 0 , 0 } }, // #151 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 56, 16, 28, 0 , 0 , 0 } }, // #152 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 56, 16, 0 , 0 , 0 } }, // #153 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 56, 16, 0 , 0 , 0 } } // #154 [ref=8x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 7 , 0 , 0 , 0 , 0 , 0 } }, // #11 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 18, 0 , 0 , 0 , 0 , 0 } }, // #12 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 4 , { 6 , 7 , 0 , 0 , 0 , 0 } }, // #13 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 8 , 9 , 0 , 0 , 0 , 0 } }, // #14 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 21, 0 , 0 , 0 } }, // #15 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 4 , 22, 17, 23, 24, 0 } }, // #16 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 25, 26, 27, 28, 29, 0 } }, // #17 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 27, 30, 31, 15, 0 , 0 } }, // #18 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 27, 0 , 0 , 0 , 0 , 0 } }, // #19 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 0 , 0 , 0 , 0 , 0 } }, // #20 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 40, 41, 3 , 0 , 0 , 0 } }, // #21 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 17, { 43, 5 , 0 , 0 , 0 , 0 } }, // #22 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #23 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 18, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #24 [ref=15x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 44, 0 , 0 , 0 , 0 , 0 } }, // #25 [ref=16x] + { InstDB::RWInfo::kCategoryGeneric , 19, { 45, 0 , 0 , 0 , 0 , 0 } }, // #26 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 19, { 46, 0 , 0 , 0 , 0 , 0 } }, // #27 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 20, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #28 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 45, 0 , 0 , 0 , 0 , 0 } }, // #29 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 18, { 11, 0 , 0 , 0 , 0 , 0 } }, // #30 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 21, { 13, 0 , 0 , 0 , 0 , 0 } }, // #31 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #32 [ref=8x] + { InstDB::RWInfo::kCategoryGeneric , 21, { 47, 0 , 0 , 0 , 0 , 0 } }, // #33 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 7 , { 48, 0 , 0 , 0 , 0 , 0 } }, // #34 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 20, { 11, 0 , 0 , 0 , 0 , 0 } }, // #35 [ref=2x] + { InstDB::RWInfo::kCategoryImul , 22, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #36 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 51, 0 , 0 , 0 , 0 , 0 } }, // #37 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 25, 0 , 0 , 0 , 0 , 0 } }, // #38 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 4 , 9 , 0 , 0 , 0 , 0 } }, // #39 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 5 , 0 , 0 , 0 , 0 } }, // #40 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 54, 39, 39, 0 , 0 , 0 } }, // #41 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 9 , 9 , 0 , 0 , 0 } }, // #42 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 7 , 7 , 0 , 0 , 0 } }, // #43 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 13, 13, 0 , 0 , 0 } }, // #44 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 54, 39, 0 , 0 , 0 , 0 } }, // #45 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 9 , 0 , 0 , 0 , 0 } }, // #46 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 7 , 0 , 0 , 0 , 0 } }, // #47 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 13, 0 , 0 , 0 , 0 } }, // #48 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 47, 39, 39, 0 , 0 , 0 } }, // #49 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 9 , 9 , 0 , 0 , 0 } }, // #50 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 13, 13, 0 , 0 , 0 } }, // #51 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 55, 0 , 0 , 0 , 0 , 0 } }, // #52 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 28, { 9 , 0 , 0 , 0 , 0 , 0 } }, // #53 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 16, { 42, 0 , 0 , 0 , 0 , 0 } }, // #54 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 7 , { 13, 0 , 0 , 0 , 0 , 0 } }, // #55 [ref=5x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 3 , 0 , 0 , 0 , 0 , 0 } }, // #56 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 3 , 9 , 0 , 0 , 0 , 0 } }, // #57 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 5 , 5 , 20, 0 , 0 , 0 } }, // #58 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 7 , 7 , 20, 0 , 0 , 0 } }, // #59 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 18, 28, 57, 0 , 0 , 0 } }, // #60 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 60, 41, 3 , 0 , 0 , 0 } }, // #61 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 11, 3 , 61, 0 , 0 } }, // #62 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 28, 29, 0 , 0 , 0 } }, // #63 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 10, { 3 , 0 , 0 , 0 , 0 , 0 } }, // #64 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 2 , { 2 , 3 , 0 , 0 , 0 , 0 } }, // #65 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 63, 16, 57 } }, // #66 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 64, 16, 57 } }, // #67 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 63, 0 , 0 } }, // #68 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 64, 0 , 0 } }, // #69 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 31, { 54, 5 , 0 , 0 , 0 , 0 } }, // #70 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 32, { 34, 5 , 0 , 0 , 0 , 0 } }, // #71 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 33, { 47, 3 , 0 , 0 , 0 , 0 } }, // #72 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 15, { 4 , 39, 0 , 0 , 0 , 0 } }, // #73 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 4 , { 4 , 7 , 0 , 0 , 0 , 0 } }, // #74 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 27, { 2 , 13, 0 , 0 , 0 , 0 } }, // #75 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 10, { 66, 0 , 0 , 0 , 0 , 0 } }, // #76 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 4 , { 34, 7 , 0 , 0 , 0 , 0 } }, // #77 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 10, { 61, 0 , 0 , 0 , 0 , 0 } }, // #78 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 0 , 0 , 0 , 0 , 0 } }, // #79 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 68, 28, 0 , 0 , 0 } }, // #80 [ref=5x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 43, 0 , 0 , 0 , 0 , 0 } }, // #81 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 34, 0 , 0 , 0 , 0 , 0 } }, // #82 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 15, 68, 63, 0 , 0 , 0 } }, // #83 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 2 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #84 [ref=16x] + { InstDB::RWInfo::kCategoryGeneric , 4 , { 35, 7 , 0 , 0 , 0 , 0 } }, // #85 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 36, 9 , 0 , 0 , 0 , 0 } }, // #86 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 69, 0 , 0 , 0 , 0 , 0 } }, // #87 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 31, { 70, 0 , 0 , 0 , 0 , 0 } }, // #88 [ref=30x] + { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 3 , 67, 0 , 0 , 0 } }, // #89 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 34, { 11, 0 , 0 , 0 , 0 , 0 } }, // #90 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 28, { 43, 0 , 0 , 0 , 0 , 0 } }, // #91 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 16, { 71, 0 , 0 , 0 , 0 , 0 } }, // #92 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 72, 42, 42, 0 , 0 , 0 } }, // #93 [ref=5x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 71, 0 , 0 , 0 , 0 , 0 } }, // #94 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 9 , 57, 16, 0 , 0 , 0 } }, // #95 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 17, { 51, 0 , 0 , 0 , 0 , 0 } }, // #96 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 72, 42, 42, 42, 42, 5 } }, // #97 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 4 , 5 , 5 , 5 , 5 , 5 } }, // #98 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 5 , 7 , 0 , 0 , 0 } }, // #99 [ref=8x] + { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 5 , 9 , 0 , 0 , 0 } }, // #100 [ref=9x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 3 , 0 , 0 } }, // #101 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 35, { 11, 5 , 7 , 0 , 0 , 0 } }, // #102 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 36, { 11, 5 , 9 , 0 , 0 , 0 } }, // #103 [ref=1x] + { InstDB::RWInfo::kCategoryVmov1_2 , 41, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #104 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 75, 7 , 0 , 0 , 0 } }, // #105 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 58, 3 , 0 , 0 , 0 } }, // #106 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 42, { 10, 75, 3 , 0 , 0 , 0 } }, // #107 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 58, 9 , 0 , 0 , 0 } }, // #108 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 43, { 10, 5 , 5 , 0 , 0 , 0 } }, // #109 [ref=9x] + { InstDB::RWInfo::kCategoryGeneric , 45, { 10, 74, 0 , 0 , 0 , 0 } }, // #110 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 45, { 10, 3 , 0 , 0 , 0 , 0 } }, // #111 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 46, { 73, 42, 0 , 0 , 0 , 0 } }, // #112 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 2 , 3 , 3 , 0 , 0 , 0 } }, // #113 [ref=60x] + { InstDB::RWInfo::kCategoryGeneric , 35, { 4 , 58, 7 , 0 , 0 , 0 } }, // #114 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 36, { 4 , 75, 9 , 0 , 0 , 0 } }, // #115 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 35, { 6 , 7 , 7 , 0 , 0 , 0 } }, // #116 [ref=11x] + { InstDB::RWInfo::kCategoryGeneric , 36, { 8 , 9 , 9 , 0 , 0 , 0 } }, // #117 [ref=11x] + { InstDB::RWInfo::kCategoryGeneric , 47, { 11, 3 , 3 , 3 , 0 , 0 } }, // #118 [ref=15x] + { InstDB::RWInfo::kCategoryGeneric , 48, { 34, 7 , 7 , 7 , 0 , 0 } }, // #119 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 49, { 43, 9 , 9 , 9 , 0 , 0 } }, // #120 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 35, { 25, 7 , 7 , 0 , 0 , 0 } }, // #121 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 36, { 51, 9 , 9 , 0 , 0 , 0 } }, // #122 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 14, { 34, 3 , 0 , 0 , 0 , 0 } }, // #123 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 34, 9 , 0 , 0 , 0 , 0 } }, // #124 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #125 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 2 , 3 , 2 , 0 , 0 , 0 } }, // #126 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 18, { 4 , 3 , 4 , 0 , 0 , 0 } }, // #127 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 35, { 10, 58, 7 , 0 , 0 , 0 } }, // #128 [ref=11x] + { InstDB::RWInfo::kCategoryGeneric , 36, { 10, 75, 9 , 0 , 0 , 0 } }, // #129 [ref=13x] + { InstDB::RWInfo::kCategoryGeneric , 43, { 73, 74, 5 , 0 , 0 , 0 } }, // #130 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 43, { 11, 3 , 5 , 0 , 0 , 0 } }, // #131 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 50, { 71, 42, 74, 0 , 0 , 0 } }, // #132 [ref=4x] + { InstDB::RWInfo::kCategoryVmaskmov , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #133 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 34, 0 , 0 , 0 , 0 , 0 } }, // #134 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 21, 0 , 0 , 0 , 0 , 0 } }, // #135 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 58, 58, 0 , 0 , 0 } }, // #136 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 10, 7 , 7 , 0 , 0 , 0 } }, // #137 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 7 , 7 , 0 , 0 , 0 } }, // #138 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 10, 58, 7 , 0 , 0 , 0 } }, // #139 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 58, 7 , 0 , 0 , 0 } }, // #140 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 10, 75, 9 , 0 , 0 , 0 } }, // #141 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 76, 0 , 0 , 0 , 0 , 0 } }, // #142 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 54, { 34, 11, 3 , 3 , 0 , 0 } }, // #143 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 71, 42, 42, 42, 42, 5 } }, // #144 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 6 , { 34, 3 , 3 , 0 , 0 , 0 } }, // #145 [ref=17x] + { InstDB::RWInfo::kCategoryGeneric , 50, { 73, 74, 74, 0 , 0 , 0 } }, // #146 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 3 , 0 , 0 , 0 } }, // #147 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 7 , { 47, 5 , 0 , 0 , 0 , 0 } }, // #148 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 55, { 10, 5 , 39, 0 , 0 , 0 } }, // #149 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 56, { 10, 5 , 13, 0 , 0 , 0 } }, // #150 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 43, { 10, 5 , 5 , 5 , 0 , 0 } }, // #151 [ref=12x] + { InstDB::RWInfo::kCategoryGeneric , 61, { 10, 5 , 5 , 5 , 0 , 0 } }, // #152 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 62, { 10, 5 , 5 , 0 , 0 , 0 } }, // #153 [ref=12x] + { InstDB::RWInfo::kCategoryGeneric , 22, { 11, 3 , 5 , 0 , 0 , 0 } }, // #154 [ref=9x] + { InstDB::RWInfo::kCategoryGeneric , 63, { 11, 3 , 0 , 0 , 0 , 0 } }, // #155 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 57, 16, 28, 0 , 0 , 0 } }, // #156 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 3 , 57, 16, 0 , 0 , 0 } }, // #157 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 57, 16, 0 , 0 , 0 } } // #158 [ref=8x] }; const InstDB::RWInfoOp InstDB::rwInfoOp[] = { - { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, 0 }, // #0 [ref=15239x] + { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, 0 }, // #0 [ref=15423x] { 0x0000000000000003u, 0x0000000000000003u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId }, // #1 [ref=10x] { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #2 [ref=217x] - { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #3 [ref=986x] + { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #3 [ref=987x] { 0x000000000000FFFFu, 0x000000000000FFFFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #4 [ref=92x] { 0x000000000000FFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #5 [ref=305x] { 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kRW }, // #6 [ref=18x] - { 0x00000000000000FFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #7 [ref=181x] + { 0x00000000000000FFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #7 [ref=185x] { 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kRW }, // #8 [ref=18x] - { 0x000000000000000Fu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #9 [ref=131x] + { 0x000000000000000Fu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #9 [ref=133x] { 0x0000000000000000u, 0x000000000000FFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #10 [ref=160x] { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #11 [ref=421x] { 0x0000000000000003u, 0x0000000000000003u, 0xFF, { 0 }, OpRWInfo::kRW }, // #12 [ref=1x] { 0x0000000000000003u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #13 [ref=34x] { 0x000000000000FFFFu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #14 [ref=4x] - { 0x0000000000000000u, 0x000000000000000Fu, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #15 [ref=8x] + { 0x0000000000000000u, 0x000000000000000Fu, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #15 [ref=9x] { 0x000000000000000Fu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #16 [ref=23x] { 0x00000000000000FFu, 0x00000000000000FFu, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #17 [ref=2x] { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemPhysId }, // #18 [ref=3x] @@ -3933,16 +3976,16 @@ const InstDB::RWInfoOp InstDB::rwInfoOp[] = { { 0x00000000000000FFu, 0x00000000000000FFu, 0x02, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #22 [ref=1x] { 0x00000000000000FFu, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #23 [ref=1x] { 0x00000000000000FFu, 0x0000000000000000u, 0x03, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #24 [ref=1x] - { 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #25 [ref=20x] + { 0x00000000000000FFu, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #25 [ref=21x] { 0x000000000000000Fu, 0x000000000000000Fu, 0x02, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #26 [ref=1x] { 0x000000000000000Fu, 0x000000000000000Fu, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #27 [ref=4x] - { 0x000000000000000Fu, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #28 [ref=12x] + { 0x000000000000000Fu, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #28 [ref=13x] { 0x000000000000000Fu, 0x0000000000000000u, 0x03, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #29 [ref=2x] { 0x0000000000000000u, 0x000000000000000Fu, 0x03, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #30 [ref=1x] { 0x000000000000000Fu, 0x000000000000000Fu, 0x01, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #31 [ref=1x] { 0x0000000000000000u, 0x00000000000000FFu, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #32 [ref=1x] { 0x00000000000000FFu, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #33 [ref=1x] - { 0x0000000000000000u, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #34 [ref=77x] + { 0x0000000000000000u, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #34 [ref=80x] { 0x0000000000000000u, 0x00000000000000FFu, 0xFF, { 0 }, OpRWInfo::kWrite }, // #35 [ref=6x] { 0x0000000000000000u, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kWrite }, // #36 [ref=6x] { 0x0000000000000000u, 0x0000000000000003u, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId }, // #37 [ref=1x] @@ -3951,7 +3994,7 @@ const InstDB::RWInfoOp InstDB::rwInfoOp[] = { { 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #40 [ref=2x] { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #41 [ref=3x] { 0xFFFFFFFFFFFFFFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #42 [ref=45x] - { 0x0000000000000000u, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #43 [ref=27x] + { 0x0000000000000000u, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #43 [ref=30x] { 0x00000000000003FFu, 0x00000000000003FFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #44 [ref=22x] { 0x00000000000003FFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #45 [ref=13x] { 0x0000000000000000u, 0x00000000000003FFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #46 [ref=1x] @@ -3959,36 +4002,36 @@ const InstDB::RWInfoOp InstDB::rwInfoOp[] = { { 0x0000000000000000u, 0x0000000000000003u, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #48 [ref=2x] { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #49 [ref=2x] { 0x0000000000000003u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #50 [ref=4x] - { 0x0000000000000000u, 0x0000000000000000u, 0x07, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kMemPhysId }, // #51 [ref=1x] - { 0x0000000000000000u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #52 [ref=1x] - { 0x0000000000000000u, 0x0000000000000001u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #53 [ref=14x] - { 0x0000000000000000u, 0x0000000000000001u, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId }, // #54 [ref=1x] - { 0x0000000000000000u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #55 [ref=3x] - { 0x000000000000000Fu, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #56 [ref=22x] - { 0x000000000000FF00u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #57 [ref=23x] - { 0x0000000000000000u, 0x000000000000FF00u, 0xFF, { 0 }, OpRWInfo::kWrite }, // #58 [ref=1x] - { 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #59 [ref=1x] - { 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #60 [ref=2x] - { 0x0000000000000000u, 0x0000000000000000u, 0x06, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemPhysId }, // #61 [ref=1x] - { 0x0000000000000000u, 0x000000000000000Fu, 0x01, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #62 [ref=5x] - { 0x0000000000000000u, 0x000000000000FFFFu, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #63 [ref=4x] - { 0x0000000000000000u, 0x0000000000000007u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #64 [ref=2x] - { 0x0000000000000000u, 0x0000000000000000u, 0x04, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #65 [ref=1x] - { 0x0000000000000001u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #66 [ref=10x] - { 0x0000000000000000u, 0x000000000000000Fu, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #67 [ref=6x] - { 0x0000000000000001u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #68 [ref=1x] - { 0x0000000000000000u, 0x0000000000000001u, 0xFF, { 0 }, OpRWInfo::kWrite }, // #69 [ref=30x] - { 0x0000000000000000u, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #70 [ref=20x] - { 0xFFFFFFFFFFFFFFFFu, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #71 [ref=7x] - { 0x0000000000000000u, 0x00000000FFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #72 [ref=10x] - { 0x00000000FFFFFFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #73 [ref=16x] - { 0x000000000000FFF0u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #74 [ref=18x] - { 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #75 [ref=1x] + { 0x000000000000000Fu, 0x000000000000000Fu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #51 [ref=4x] + { 0x0000000000000000u, 0x0000000000000000u, 0x07, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kMemPhysId }, // #52 [ref=1x] + { 0x0000000000000000u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #53 [ref=1x] + { 0x0000000000000000u, 0x0000000000000001u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #54 [ref=14x] + { 0x0000000000000000u, 0x0000000000000001u, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId }, // #55 [ref=1x] + { 0x0000000000000000u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #56 [ref=3x] + { 0x000000000000000Fu, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #57 [ref=22x] + { 0x000000000000FF00u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #58 [ref=23x] + { 0x0000000000000000u, 0x000000000000FF00u, 0xFF, { 0 }, OpRWInfo::kWrite }, // #59 [ref=1x] + { 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kWrite | OpRWInfo::kRegPhysId | OpRWInfo::kZExt }, // #60 [ref=1x] + { 0x0000000000000000u, 0x0000000000000000u, 0x02, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #61 [ref=2x] + { 0x0000000000000000u, 0x0000000000000000u, 0x06, { 0 }, OpRWInfo::kRead | OpRWInfo::kMemPhysId }, // #62 [ref=1x] + { 0x0000000000000000u, 0x000000000000000Fu, 0x01, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #63 [ref=5x] + { 0x0000000000000000u, 0x000000000000FFFFu, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #64 [ref=4x] + { 0x0000000000000000u, 0x0000000000000007u, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #65 [ref=2x] + { 0x0000000000000000u, 0x0000000000000000u, 0x04, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #66 [ref=1x] + { 0x0000000000000001u, 0x0000000000000000u, 0x01, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #67 [ref=10x] + { 0x0000000000000000u, 0x000000000000000Fu, 0x00, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt | OpRWInfo::kRegPhysId }, // #68 [ref=7x] + { 0x0000000000000001u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRead | OpRWInfo::kRegPhysId }, // #69 [ref=1x] + { 0x0000000000000000u, 0x0000000000000001u, 0xFF, { 0 }, OpRWInfo::kWrite }, // #70 [ref=30x] + { 0x0000000000000000u, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #71 [ref=20x] + { 0xFFFFFFFFFFFFFFFFu, 0xFFFFFFFFFFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #72 [ref=7x] + { 0x0000000000000000u, 0x00000000FFFFFFFFu, 0xFF, { 0 }, OpRWInfo::kWrite | OpRWInfo::kZExt }, // #73 [ref=10x] + { 0x00000000FFFFFFFFu, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #74 [ref=16x] + { 0x000000000000FFF0u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #75 [ref=18x] { 0x0000000000000000u, 0x0000000000000000u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt | OpRWInfo::kRegPhysId } // #76 [ref=1x] }; const InstDB::RWInfoRm InstDB::rwInfoRm[] = { - { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , 0, 0 }, // #0 [ref=1856x] + { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , 0, 0 }, // #0 [ref=1881x] { InstDB::RWInfoRm::kCategoryConsistent, 0x03, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #1 [ref=8x] { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , 0, 0 }, // #2 [ref=194x] { InstDB::RWInfoRm::kCategoryFixed , 0x02, 16, 0, 0 }, // #3 [ref=122x] @@ -3998,14 +4041,14 @@ const InstDB::RWInfoRm InstDB::rwInfoRm[] = { { InstDB::RWInfoRm::kCategoryFixed , 0x01, 2 , 0, 0 }, // #7 [ref=9x] { InstDB::RWInfoRm::kCategoryFixed , 0x00, 0 , 0, 0 }, // #8 [ref=63x] { InstDB::RWInfoRm::kCategoryFixed , 0x03, 0 , 0, 0 }, // #9 [ref=1x] - { InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #10 [ref=20x] + { InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #10 [ref=21x] { InstDB::RWInfoRm::kCategoryConsistent, 0x01, 0 , 0, 0 }, // #11 [ref=13x] - { InstDB::RWInfoRm::kCategoryFixed , 0x00, 16, 0, 0 }, // #12 [ref=21x] - { InstDB::RWInfoRm::kCategoryFixed , 0x00, 8 , 0, 0 }, // #13 [ref=20x] + { InstDB::RWInfoRm::kCategoryFixed , 0x00, 8 , 0, 0 }, // #12 [ref=22x] + { InstDB::RWInfoRm::kCategoryFixed , 0x00, 16, 0, 0 }, // #13 [ref=21x] { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #14 [ref=15x] { InstDB::RWInfoRm::kCategoryFixed , 0x02, 1 , 0, 0 }, // #15 [ref=5x] { InstDB::RWInfoRm::kCategoryFixed , 0x00, 64, 0, 0 }, // #16 [ref=5x] - { InstDB::RWInfoRm::kCategoryFixed , 0x01, 4 , 0, 0 }, // #17 [ref=4x] + { InstDB::RWInfoRm::kCategoryFixed , 0x01, 4 , 0, 0 }, // #17 [ref=8x] { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #18 [ref=22x] { InstDB::RWInfoRm::kCategoryFixed , 0x00, 10, 0, 0 }, // #19 [ref=2x] { InstDB::RWInfoRm::kCategoryNone , 0x01, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #20 [ref=5x] @@ -4020,7 +4063,7 @@ const InstDB::RWInfoRm InstDB::rwInfoRm[] = { { InstDB::RWInfoRm::kCategoryNone , 0x03, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #29 [ref=1x] { InstDB::RWInfoRm::kCategoryFixed , 0x03, 16, 0, 0 }, // #30 [ref=6x] { InstDB::RWInfoRm::kCategoryFixed , 0x01, 1 , 0, 0 }, // #31 [ref=32x] - { InstDB::RWInfoRm::kCategoryFixed , 0x01, 8 , 0, 0 }, // #32 [ref=2x] + { InstDB::RWInfoRm::kCategoryFixed , 0x01, 8 , 0, 0 }, // #32 [ref=4x] { InstDB::RWInfoRm::kCategoryFixed , 0x01, 2 , 0, Features::kSSE4_1 }, // #33 [ref=1x] { InstDB::RWInfoRm::kCategoryFixed , 0x01, 2 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #34 [ref=3x] { InstDB::RWInfoRm::kCategoryFixed , 0x04, 8 , 0, 0 }, // #35 [ref=34x] diff --git a/src/asmjit/x86/x86instdb_p.h b/src/asmjit/x86/x86instdb_p.h index afeabd2..9c48bed 100644 --- a/src/asmjit/x86/x86instdb_p.h +++ b/src/asmjit/x86/x86instdb_p.h @@ -48,8 +48,8 @@ namespace InstDB { enum EncodingId : uint32_t { kEncodingNone = 0, //!< Never used. kEncodingX86Op, //!< X86 [OP]. - kEncodingX86Op_O, //!< X86 [OP] (opcode and /0-7). - kEncodingX86Op_O_I8, //!< X86 [OP] (opcode and /0-7 + 8-bit immediate). + kEncodingX86Op_Mod11RM, //!< X86 [OP] (opcode with ModRM byte where MOD must be 11b). + kEncodingX86Op_Mod11RM_I8, //!< X86 [OP] (opcode with ModRM byte + 8-bit immediate). kEncodingX86Op_xAddr, //!< X86 [OP] (implicit address in the first register operand). kEncodingX86Op_xAX, //!< X86 [OP] (implicit or explicit '?AX' form). kEncodingX86Op_xDX_xAX, //!< X86 [OP] (implicit or explicit '?DX, ?AX' form). diff --git a/src/asmjit/x86/x86opcode_p.h b/src/asmjit/x86/x86opcode_p.h index a8ccc93..5f936bf 100644 --- a/src/asmjit/x86/x86opcode_p.h +++ b/src/asmjit/x86/x86opcode_p.h @@ -230,21 +230,41 @@ struct Opcode { kCDTT_T4X = kCDTT_T1_4X, // Alias to have only 3 letters. - // `O` Field in MorR/M - // ------------------- + // `O` Field in ModR/M (??:xxx:???) + // -------------------------------- - kO_Shift = 18, - kO_Mask = 0x7u << kO_Shift, + kModO_Shift = 18, + kModO_Mask = 0x7u << kModO_Shift, - kO__ = 0x0u, - kO_0 = 0x0u << kO_Shift, - kO_1 = 0x1u << kO_Shift, - kO_2 = 0x2u << kO_Shift, - kO_3 = 0x3u << kO_Shift, - kO_4 = 0x4u << kO_Shift, - kO_5 = 0x5u << kO_Shift, - kO_6 = 0x6u << kO_Shift, - kO_7 = 0x7u << kO_Shift, + kModO__ = 0x0u, + kModO_0 = 0x0u << kModO_Shift, + kModO_1 = 0x1u << kModO_Shift, + kModO_2 = 0x2u << kModO_Shift, + kModO_3 = 0x3u << kModO_Shift, + kModO_4 = 0x4u << kModO_Shift, + kModO_5 = 0x5u << kModO_Shift, + kModO_6 = 0x6u << kModO_Shift, + kModO_7 = 0x7u << kModO_Shift, + + // `RM` Field in ModR/M (??:???:xxx) + // --------------------------------- + // + // Second data field used by ModR/M byte. This is only used by few + // instructions that use OPCODE+MOD/RM where both values in Mod/RM + // are part of the opcode. + + kModRM_Shift = 10, + kModRM_Mask = 0x7u << kModRM_Shift, + + kModRM__ = 0x0u, + kModRM_0 = 0x0u << kModRM_Shift, + kModRM_1 = 0x1u << kModRM_Shift, + kModRM_2 = 0x2u << kModRM_Shift, + kModRM_3 = 0x3u << kModRM_Shift, + kModRM_4 = 0x4u << kModRM_Shift, + kModRM_5 = 0x5u << kModRM_Shift, + kModRM_6 = 0x6u << kModRM_Shift, + kModRM_7 = 0x7u << kModRM_Shift, // `PP` Field // ---------- @@ -412,9 +432,14 @@ struct Opcode { return operator|=(mask[size & 0xF]); } - //! Extract `O` field from the opcode. - ASMJIT_INLINE uint32_t extractO() const noexcept { - return (v >> kO_Shift) & 0x07; + //! Extract `O` field (R) from the opcode (specified as /0..7 in instruction manuals). + ASMJIT_INLINE uint32_t extractModO() const noexcept { + return (v >> kModO_Shift) & 0x07; + } + + //! Extract `RM` field (RM) from the opcode (usually specified as another opcode value). + ASMJIT_INLINE uint32_t extractModRM() const noexcept { + return (v >> kModRM_Shift) & 0x07; } //! Extract `REX` prefix from opcode combined with `options`. diff --git a/test/asmjit_test_opcode.h b/test/asmjit_test_opcode.h index 6f052f5..47a3800 100644 --- a/test/asmjit_test_opcode.h +++ b/test/asmjit_test_opcode.h @@ -1066,10 +1066,6 @@ static void generateOpcodes(asmjit::x86::Emitter* e, bool useRex1 = false, bool e->mwait(); // Implicit , e->mwaitx(); // Implicit , , - // PCOMMIT. - e->nop(); - e->pcommit(); - // PREFETCH / PREFETCHW / PREFETCHWT1. e->nop(); e->prefetch(anyptr_gpA); // 3DNOW. diff --git a/tools/tablegen-x86.js b/tools/tablegen-x86.js index cc52b14..9bb1b9d 100644 --- a/tools/tablegen-x86.js +++ b/tools/tablegen-x86.js @@ -552,7 +552,7 @@ class X86TableGen extends core.TableGen { var enum_ = name[0].toUpperCase() + name.substr(1); var opcode = dbi.opcodeHex; - var rm = dbi.rm; + var modR = dbi.modR; var mm = dbi.mm; var pp = dbi.pp; var encoding = dbi.encoding; @@ -590,7 +590,7 @@ class X86TableGen extends core.TableGen { } if (opcode !== dbi.opcodeHex ) { console.log(`ISSUE: Opcode ${opcode} != ${dbi.opcodeHex}`); return null; } - if (rm !== dbi.rm ) { console.log(`ISSUE: RM ${rm} != ${dbi.rm}`); return null; } + if (modR !== dbi.modR ) { console.log(`ISSUE: ModR ${modR} != ${dbi.modR}`); return null; } if (mm !== dbi.mm ) { console.log(`ISSUE: MM ${mm} != ${dbi.mm}`); return null; } if (pp !== dbi.pp ) { console.log(`ISSUE: PP ${pp} != ${dbi.pp}`); return null; } if (encoding !== dbi.encoding ) { console.log(`ISSUE: Enc ${encoding} != ${dbi.encoding}`); return null; } @@ -605,12 +605,12 @@ class X86TableGen extends core.TableGen { type : isVec ? "V" : "O", prefix: ppmm, opcode: opcode, - o : rm === "r" ? "_" : (rm ? rm : "_"), + o : modR === "r" ? "_" : (modR ? modR : "_"), l : vexL !== undefined ? vexL : "_", w : vexW !== undefined ? vexW : "_", ew : evexW !== undefined ? evexW : "_", en : "_", - tt : "_ " + tt : dbi.modRM ? dbi.modRM + " " : "_ " }); return { @@ -736,7 +736,7 @@ class AltOpcodeTable extends core.Task { } // X(______,OP,_,_,_,_,_,_ ) - if (opcode.startsWith("O_FPU(") || opcode.startsWith("O(") || opcode.startsWith("V(") || opcode.startsWith("E(")) { + if (opcode.startsWith("O(") || opcode.startsWith("V(") || opcode.startsWith("E(")) { var value = opcode.substring(9, 11); var remaining = opcode.substring(0, 9) + "00" + opcode.substring(11);