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[Bug] Fixed LDURSW instruction on AArch64 (#389)

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The instruction was wrongly described as supporting both W/X registers, however, it only supports X register.
This commit is contained in:
aegistudio
2022-11-10 17:11:05 +08:00
committed by GitHub
parent ae63ced6dd
commit 5af57595a9
2 changed files with 6 additions and 2 deletions
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4
src/asmjit/arm/a64instdb.cpp
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@@ -300,7 +300,7 @@ const InstInfo _instInfoTable[] = {
INST(Ldurh , BaseRM_SImm9 , (0b0111100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0) , kRWI_W , 0 , 9 , 2153), // #230 INST(Ldurh , BaseRM_SImm9 , (0b0111100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0) , kRWI_W , 0 , 9 , 2153), // #230
INST(Ldursb , BaseRM_SImm9 , (0b0011100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0) , kRWI_W , 0 , 10 , 2159), // #231 INST(Ldursb , BaseRM_SImm9 , (0b0011100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0) , kRWI_W , 0 , 10 , 2159), // #231
INST(Ldursh , BaseRM_SImm9 , (0b0111100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0) , kRWI_W , 0 , 11 , 2166), // #232 INST(Ldursh , BaseRM_SImm9 , (0b0111100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0) , kRWI_W , 0 , 11 , 2166), // #232
INST(Ldursw , BaseRM_SImm9 , (0b1011100010000000000000, 0b0000000000000000000000, kWX, kZR, 0 , 0) , kRWI_W , 0 , 12 , 2173), // #233 INST(Ldursw , BaseRM_SImm9 , (0b1011100010000000000000, 0b0000000000000000000000, kX, kZR, 0 , 0) , kRWI_W , 0 , 12 , 2173), // #233
INST(Ldxp , BaseLdxp , (0b1000100001111111000000, kWX, 30) , kRWI_WW , 0 , 1 , 2180), // #234 INST(Ldxp , BaseLdxp , (0b1000100001111111000000, kWX, 30) , kRWI_WW , 0 , 1 , 2180), // #234
INST(Ldxr , BaseRM_NoImm , (0b1000100001011111011111, kWX, kZR, 30) , kRWI_W , 0 , 10 , 2185), // #235 INST(Ldxr , BaseRM_NoImm , (0b1000100001011111011111, kWX, kZR, 30) , kRWI_W , 0 , 10 , 2185), // #235
INST(Ldxrb , BaseRM_NoImm , (0b0000100001011111011111, kW , kZR, 0 ) , kRWI_W , 0 , 11 , 2190), // #236 INST(Ldxrb , BaseRM_NoImm , (0b0000100001011111011111, kW , kZR, 0 ) , kRWI_W , 0 , 11 , 2190), // #236
@@ -1275,7 +1275,7 @@ const BaseRM_SImm9 baseRM_SImm9[23] = {
{ 0b0111100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0 }, // ldurh { 0b0111100001000000000000, 0b0000000000000000000000, kW , kZR, 0 , 0 }, // ldurh
{ 0b0011100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldursb { 0b0011100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldursb
{ 0b0111100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldursh { 0b0111100011000000000000, 0b0000000000000000000000, kWX, kZR, 22, 0 }, // ldursh
{ 0b1011100010000000000000, 0b0000000000000000000000, kWX, kZR, 0 , 0 }, // ldursw { 0b1011100010000000000000, 0b0000000000000000000000, kX, kZR, 0 , 0 }, // ldursw
{ 0b1101100110100000000010, 0b1101100110100000000001, kX, kSP, 0, 4 }, // st2g { 0b1101100110100000000010, 0b1101100110100000000001, kX, kSP, 0, 4 }, // st2g
{ 0b1101100100100000000010, 0b1101100100100000000001, kX, kSP, 0, 4 }, // stg { 0b1101100100100000000010, 0b1101100100100000000001, kX, kSP, 0, 4 }, // stg
{ 0b1011100000000000000010, 0b0000000000000000000000, kWX, kZR, 30, 0 }, // sttr { 0b1011100000000000000010, 0b0000000000000000000000, kWX, kZR, 30, 0 }, // sttr

4
test/asmjit_test_assembler_a64.cpp
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@@ -746,6 +746,10 @@ static void ASMJIT_NOINLINE testA64AssemblerBase(AssemblerTester<a64::Assembler>
TEST_INSTRUCTION("411088B8", ldursw(x1, ptr(x2, 129))); TEST_INSTRUCTION("411088B8", ldursw(x1, ptr(x2, 129)));
TEST_INSTRUCTION("E10380B8", ldursw(x1, ptr(sp))); TEST_INSTRUCTION("E10380B8", ldursw(x1, ptr(sp)));
TEST_INSTRUCTION("E11388B8", ldursw(x1, ptr(sp, 129))); TEST_INSTRUCTION("E11388B8", ldursw(x1, ptr(sp, 129)));
TEST_INSTRUCTION("420080B8", ldursw(x2, ptr(x2)));
TEST_INSTRUCTION("421088B8", ldursw(x2, ptr(x2, 129)));
TEST_INSTRUCTION("E20380B8", ldursw(x2, ptr(sp)));
TEST_INSTRUCTION("E21388B8", ldursw(x2, ptr(sp, 129)));
TEST_INSTRUCTION("61087F88", ldxp(w1, w2, ptr(x3))); TEST_INSTRUCTION("61087F88", ldxp(w1, w2, ptr(x3)));
TEST_INSTRUCTION("E10B7F88", ldxp(w1, w2, ptr(sp))); TEST_INSTRUCTION("E10B7F88", ldxp(w1, w2, ptr(sp)));
TEST_INSTRUCTION("61087FC8", ldxp(x1, x2, ptr(x3))); TEST_INSTRUCTION("61087FC8", ldxp(x1, x2, ptr(x3)));