diff --git a/.github/workflows/build-config.json b/.github/workflows/build-config.json index 13166b3..857ddeb 100644 --- a/.github/workflows/build-config.json +++ b/.github/workflows/build-config.json @@ -20,17 +20,21 @@ "optional": true }, { - "cmd": ["asmjit_test_x86_asm"], + "cmd": ["asmjit_test_assembler", "--quiet"], + "optional": true + }, + { + "cmd": ["asmjit_test_emitters"], + "optional": true + }, + { + "cmd": ["asmjit_test_instinfo"], "optional": true }, { "cmd": ["asmjit_test_x86_sections"], "optional": true }, - { - "cmd": ["asmjit_test_x86_instinfo"], - "optional": true - }, { "cmd": ["asmjit_test_compiler"], "optional": true diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 1a22a36..dd0c324 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -79,14 +79,14 @@ jobs: - { title: "linux" , os: "ubuntu-latest" , cc: "clang-10", arch: "x64", build_type: "Debug" , defs: "ASMJIT_TEST=ON" } - { title: "linux" , os: "ubuntu-latest" , cc: "clang-10", arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=ON" } - - { title: "osx-10.15" , os: "macos-10.15" , cc: "gcc-9" , arch: "x64", build_type: "Debug" , defs: "ASMJIT_TEST=ON" } - - { title: "osx-10.15" , os: "macos-10.15" , cc: "gcc-9" , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=ON" } - - { title: "osx-10.15" , os: "macos-10.15" , cc: "clang" , arch: "x64", build_type: "Debug" , defs: "ASMJIT_TEST=ON" } - - { title: "osx-10.15" , os: "macos-10.15" , cc: "clang" , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=ON" } - - { title: "osx-11.0" , os: "macos-11.0" , cc: "gcc-9" , arch: "x64", build_type: "Debug" , defs: "ASMJIT_TEST=ON" } - - { title: "osx-11.0" , os: "macos-11.0" , cc: "gcc-9" , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=ON" } - - { title: "osx-11.0" , os: "macos-11.0" , cc: "clang" , arch: "x64", build_type: "Debug" , defs: "ASMJIT_TEST=ON" } - - { title: "osx-11.0" , os: "macos-11.0" , cc: "clang" , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=ON" } + - { title: "macos-10.15" , os: "macos-10.15" , cc: "gcc-9" , arch: "x64", build_type: "Debug" , defs: "ASMJIT_TEST=ON" } + - { title: "macos-10.15" , os: "macos-10.15" , cc: "gcc-9" , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=ON" } + - { title: "macos-10.15" , os: "macos-10.15" , cc: "clang" , arch: "x64", build_type: "Debug" , defs: "ASMJIT_TEST=ON" } + - { title: "macos-10.15" , os: "macos-10.15" , cc: "clang" , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=ON" } + - { title: "macos-11.0" , os: "macos-11.0" , cc: "gcc-10" , arch: "x64", build_type: "Debug" , defs: "ASMJIT_TEST=ON" } + - { title: "macos-11.0" , os: "macos-11.0" , cc: "gcc-10" , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=ON" } + - { title: "macos-11.0" , os: "macos-11.0" , cc: "clang" , arch: "x64", build_type: "Debug" , defs: "ASMJIT_TEST=ON" } + - { title: "macos-11.0" , os: "macos-11.0" , cc: "clang" , arch: "x64", build_type: "Release", defs: "ASMJIT_TEST=ON" } - { title: "windows" , os: "windows-latest", cc: "vs2019" , arch: "x86", build_type: "Debug" , defs: "ASMJIT_TEST=ON" } - { title: "windows" , os: "windows-latest", cc: "vs2019" , arch: "x86", build_type: "Release", defs: "ASMJIT_TEST=ON" } diff --git a/CMakeLists.txt b/CMakeLists.txt index fd2efab..3d5b9b8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -498,7 +498,7 @@ if (NOT ASMJIT_EMBED) target_include_directories(asmjit_test_unit BEFORE PRIVATE ${ASMJIT_INCLUDE_DIRS}) foreach(_target asmjit_test_opcode - asmjit_test_x86_asm + asmjit_test_emitters asmjit_test_x86_sections) asmjit_add_target(${_target} TEST SOURCES test/${_target}.cpp @@ -508,9 +508,18 @@ if (NOT ASMJIT_EMBED) CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL}) endforeach() + asmjit_add_target(asmjit_test_assembler TEST + SOURCES test/asmjit_test_assembler.cpp + test/asmjit_test_assembler_x86.cpp + test/asmjit_test_assembler.h + LIBRARIES asmjit::asmjit + CFLAGS ${ASMJIT_PRIVATE_CFLAGS} + CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG} + CFLAGS_REL ${ASMJIT_PRIVATE_CFLAGS_REL}) + if (NOT ASMJIT_NO_INTROSPECTION) - asmjit_add_target(asmjit_test_x86_instinfo TEST - SOURCES test/asmjit_test_x86_instinfo.cpp + asmjit_add_target(asmjit_test_instinfo TEST + SOURCES test/asmjit_test_instinfo.cpp LIBRARIES asmjit::asmjit CFLAGS ${ASMJIT_PRIVATE_CFLAGS} CFLAGS_DBG ${ASMJIT_PRIVATE_CFLAGS_DBG} diff --git a/README.md b/README.md index cf64245..08ac033 100644 --- a/README.md +++ b/README.md @@ -23,9 +23,11 @@ Breaking the API is sometimes inevitable, what to do? * See [Breaking Changes Guide](https://asmjit.com/doc/group__asmjit__breaking__changes.html), which is now part of AsmJit documentation. * See asmjit tests, they always compile and provide implementation of many use-cases: - * [asmjit_test_x86_asm.cpp](./test/asmjit_test_x86_asm.cpp) - Tests that demonstrate the purpose of emitters. - * [asmjit_test_x86_sections.cpp](./test/asmjit_test_x86_sections.cpp) - Multiple sections test. + * [asmjit_test_emitters.cpp](./test/asmjit_test_emitters.cpp) - Tests that demonstrate the purpose of emitters. + * [asmjit_test_assembler_x86.cpp](./test/asmjit_test_assembler_x86.cpp) - Tests targeting AsmJit's Assembler (x86/x64). * [asmjit_test_compiler_x86.cpp](./test/asmjit_test_compiler_x86.cpp) - Tests targeting AsmJit's Compiler (x86/x64). + * [asmjit_test_instinfo.cpp](./test/asmjit_test_instinfo.cpp) - Tests that query instruction information. + * [asmjit_test_x86_sections.cpp](./test/asmjit_test_x86_sections.cpp) - Multiple sections test. * Visit our [Official Chat](https://gitter.im/asmjit/asmjit) if you need a quick help. Project Organization diff --git a/src/asmjit/core/features.h b/src/asmjit/core/features.h index 095ca8c..0f2cfe2 100644 --- a/src/asmjit/core/features.h +++ b/src/asmjit/core/features.h @@ -47,7 +47,7 @@ public: typedef Support::BitVectorIterator Iterator; enum : uint32_t { - kMaxFeatures = 128, + kMaxFeatures = 256, kNumBitWords = kMaxFeatures / Support::kBitWordSizeInBits }; diff --git a/src/asmjit/core/inst.h b/src/asmjit/core/inst.h index 79619ae..bc3708d 100644 --- a/src/asmjit/core/inst.h +++ b/src/asmjit/core/inst.h @@ -62,7 +62,7 @@ public: kOptionReserved = 0x00000001u, //! Prevents following a jump during compilation (BaseCompiler). - kOptionUnfollow = 0x00000010u, + kOptionUnfollow = 0x00000002u, //! Overwrite the destination operand(s) (BaseCompiler). //! @@ -102,17 +102,17 @@ public: //! //! - `sqrtss x, y` - only LO element of `x` is changed, if you don't //! use HI elements, use `compiler.overwrite().sqrtss(x, y)`. - kOptionOverwrite = 0x00000020u, + kOptionOverwrite = 0x00000004u, //! Emit short-form of the instruction. - kOptionShortForm = 0x00000040u, + kOptionShortForm = 0x00000010u, //! Emit long-form of the instruction. - kOptionLongForm = 0x00000080u, + kOptionLongForm = 0x00000020u, //! Conditional jump is likely to be taken. - kOptionTaken = 0x00000100u, + kOptionTaken = 0x00000040u, //! Conditional jump is unlikely to be taken. - kOptionNotTaken = 0x00000200u + kOptionNotTaken = 0x00000080u }; //! Control type. diff --git a/src/asmjit/x86/x86assembler.cpp b/src/asmjit/x86/x86assembler.cpp index 3f9e3af..492b70f 100644 --- a/src/asmjit/x86/x86assembler.cpp +++ b/src/asmjit/x86/x86assembler.cpp @@ -505,33 +505,37 @@ static ASMJIT_INLINE uint32_t x86GetMovAbsInstSize64Bit(uint32_t regSize, uint32 return segmentPrefixSize + _66hPrefixSize + rexPrefixSize + opCodeByteSize + immediateSize; } -static ASMJIT_INLINE uint32_t x86GetMovAbsAddrType(Assembler* self, X86BufferWriter& writer, uint32_t regSize, uint32_t options, const Mem& rmRel) noexcept { - uint32_t addrType = rmRel.addrType(); - int64_t addrValue = rmRel.offset(); +static ASMJIT_INLINE bool x86ShouldUseMovabs(Assembler* self, X86BufferWriter& writer, uint32_t regSize, uint32_t options, const Mem& rmRel) noexcept { + if (self->is32Bit()) { + // There is no relative addressing, just decide whether to use MOV encoded with MOD R/M or absolute. + return !(options & Inst::kOptionModMR); + } + else { + // If the addressing type is REL or MOD R/M was specified then absolute mov won't be used. + if (rmRel.addrType() == Mem::kAddrTypeRel || (options & Inst::kOptionModMR) != 0) + return false; - if (addrType == Mem::kAddrTypeDefault && !(options & Inst::kOptionModMR)) { - if (self->is64Bit()) { - uint64_t baseAddress = self->code()->baseAddress(); - if (baseAddress != Globals::kNoBaseAddress && !rmRel.hasSegment()) { - uint32_t instructionSize = x86GetMovAbsInstSize64Bit(regSize, options, rmRel); - uint64_t virtualOffset = uint64_t(writer.offsetFrom(self->_bufferData)); - uint64_t rip64 = baseAddress + self->_section->offset() + virtualOffset + instructionSize; - uint64_t rel64 = uint64_t(addrValue) - rip64; + int64_t addrValue = rmRel.offset(); + uint64_t baseAddress = self->code()->baseAddress(); - if (!Support::isInt32(int64_t(rel64))) - addrType = Mem::kAddrTypeAbs; - } - else { - if (!Support::isInt32(addrValue)) - addrType = Mem::kAddrTypeAbs; - } + // If the address type is default, it means to basically check whether relative addressing is possible. However, + // this is only possible when the base address is known - relative encoding uses RIP+N it has to be calculated. + if (rmRel.addrType() == Mem::kAddrTypeDefault && baseAddress != Globals::kNoBaseAddress && !rmRel.hasSegment()) { + uint32_t instructionSize = x86GetMovAbsInstSize64Bit(regSize, options, rmRel); + uint64_t virtualOffset = uint64_t(writer.offsetFrom(self->_bufferData)); + uint64_t rip64 = baseAddress + self->_section->offset() + virtualOffset + instructionSize; + uint64_t rel64 = uint64_t(addrValue) - rip64; + + if (Support::isInt32(int64_t(rel64))) + return false; } else { - addrType = Mem::kAddrTypeAbs; + if (Support::isInt32(addrValue)) + return false; } - } - return addrType; + return uint64_t(addrValue) > 0xFFFFFFFFu; + } } // ============================================================================ @@ -1631,18 +1635,18 @@ CaseX86M_GPB_MulDiv: opcode = 0; opcode.addArithBySize(o0.size()); - if (o0.size() == 1) - FIXUP_GPB(o0, opReg); - // Handle a special form of `mov al|ax|eax|rax, [ptr64]` that doesn't use MOD. if (opReg == Gp::kIdAx && !rmRel->as().hasBaseOrIndex()) { - immValue = rmRel->as().offset(); - if (x86GetMovAbsAddrType(this, writer, o0.size(), options, rmRel->as()) == Mem::kAddrTypeAbs) { + if (x86ShouldUseMovabs(this, writer, o0.size(), options, rmRel->as())) { opcode += 0xA0; + immValue = rmRel->as().offset(); goto EmitX86OpMovAbs; } } + if (o0.size() == 1) + FIXUP_GPB(o0, opReg); + opcode += 0x8A; goto EmitX86M; } @@ -1664,18 +1668,18 @@ CaseX86M_GPB_MulDiv: opcode = 0; opcode.addArithBySize(o1.size()); - if (o1.size() == 1) - FIXUP_GPB(o1, opReg); - // Handle a special form of `mov [ptr64], al|ax|eax|rax` that doesn't use MOD. if (opReg == Gp::kIdAx && !rmRel->as().hasBaseOrIndex()) { - immValue = rmRel->as().offset(); - if (x86GetMovAbsAddrType(this, writer, o1.size(), options, rmRel->as()) == Mem::kAddrTypeAbs) { + if (x86ShouldUseMovabs(this, writer, o1.size(), options, rmRel->as())) { opcode += 0xA2; + immValue = rmRel->as().offset(); goto EmitX86OpMovAbs; } } + if (o1.size() == 1) + FIXUP_GPB(o1, opReg); + opcode += 0x88; goto EmitX86M; } @@ -1736,6 +1740,62 @@ CaseX86M_GPB_MulDiv: } break; + case InstDB::kEncodingX86Movabs: + // Reg <- Mem + if (isign3 == ENC_OPS2(Reg, Mem)) { + opReg = o0.id(); + rmRel = &o1; + + opcode = 0xA0; + opcode.addArithBySize(o0.size()); + + if (ASMJIT_UNLIKELY(!o0.as().isGp()) || opReg != Gp::kIdAx) + goto InvalidInstruction; + + if (ASMJIT_UNLIKELY(rmRel->as().hasBaseOrIndex())) + goto InvalidAddress; + + if (ASMJIT_UNLIKELY(rmRel->as().addrType() == Mem::kAddrTypeRel)) + goto InvalidAddress; + + immValue = rmRel->as().offset(); + goto EmitX86OpMovAbs; + } + + // Mem <- Reg + if (isign3 == ENC_OPS2(Mem, Reg)) { + opReg = o1.id(); + rmRel = &o0; + + opcode = 0xA2; + opcode.addArithBySize(o1.size()); + + if (ASMJIT_UNLIKELY(!o1.as().isGp()) || opReg != Gp::kIdAx) + goto InvalidInstruction; + + if (ASMJIT_UNLIKELY(rmRel->as().hasBaseOrIndex())) + goto InvalidAddress; + + immValue = rmRel->as().offset(); + goto EmitX86OpMovAbs; + } + + // Reg <- Imm. + if (isign3 == ENC_OPS2(Reg, Imm)) { + if (ASMJIT_UNLIKELY(!o0.as().isGpq())) + goto InvalidInstruction; + + opReg = o0.id(); + opcode = 0xB8; + + immSize = 8; + immValue = o1.as().value(); + + opcode.addPrefixBySize(8); + goto EmitX86OpReg; + } + break; + case InstDB::kEncodingX86MovsxMovzx: opcode.add(o1.size() != 1); opcode.addPrefixBySize(o0.size()); @@ -4424,8 +4484,20 @@ EmitVexEvexR: } } + // If these bits are used then EVEX prefix is required. + constexpr uint32_t kEvexBits = 0x00D78150u; // [........|xx.x.xxx|x......x|.x.x....]. + + // Force EVEX prefix even in case the instruction has VEX encoding, because EVEX encoding is preferred. At the + // moment this is only required for AVX_VNNI instructions, which were added after AVX512_VNNI instructions. If + // such instruction doesn't specify prefix, EVEX (AVX512_VNNI) would be used by default, + if (commonInfo->preferEvex()) { + if ((x & kEvexBits) == 0 && (options & (Inst::kOptionVex | Inst::kOptionVex3)) == 0) { + x |= (Opcode::kMM_ForceEvex) >> Opcode::kMM_Shift; + } + } + // Check if EVEX is required by checking bits in `x` : [........|xx.x.xxx|x......x|.x.x....]. - if (x & 0x00D78150u) { + if (x & kEvexBits) { uint32_t y = ((x << 4) & 0x00080000u) | // [........|...bV...|........|........]. ((x >> 4) & 0x00000010u) ; // [........|...bV...|........|...R....]. x = (x & 0x00FF78E3u) | y; // [........|zLLbVaaa|0vvvv000|RBBR00mm]. @@ -4525,8 +4597,20 @@ EmitVexEvexM: x |= options & (Inst::kOptionZMask); // [@.......|zLLbXaaa|Vvvvv..R|RXBmmmmm]. } + // If these bits are used then EVEX prefix is required. + constexpr uint32_t kEvexBits = 0x80DF8110u; // [@.......|xx.xxxxx|x......x|...x....]. + + // Force EVEX prefix even in case the instruction has VEX encoding, because EVEX encoding is preferred. At the + // moment this is only required for AVX_VNNI instructions, which were added after AVX512_VNNI instructions. If + // such instruction doesn't specify prefix, EVEX (AVX512_VNNI) would be used by default, + if (commonInfo->preferEvex()) { + if ((x & kEvexBits) == 0 && (options & (Inst::kOptionVex | Inst::kOptionVex3)) == 0) { + x |= (Opcode::kMM_ForceEvex) >> Opcode::kMM_Shift; + } + } + // Check if EVEX is required by checking bits in `x` : [@.......|xx.xxxxx|x......x|...x....]. - if (x & 0x80DF8110u) { + if (x & kEvexBits) { uint32_t y = ((x << 4) & 0x00080000u) | // [@.......|....V...|........|........]. ((x >> 4) & 0x00000010u) ; // [@.......|....V...|........|...R....]. x = (x & 0x00FF78E3u) | y; // [........|zLLbVaaa|0vvvv000|RXBR00mm]. diff --git a/src/asmjit/x86/x86emitter.h b/src/asmjit/x86/x86emitter.h index d15485e..5e1f2d5 100644 --- a/src/asmjit/x86/x86emitter.h +++ b/src/asmjit/x86/x86emitter.h @@ -37,9 +37,6 @@ ASMJIT_BEGIN_SUB_NAMESPACE(x86) #define ASMJIT_INST_1x(NAME, ID, T0) \ inline Error NAME(const T0& o0) { return _emitter()->_emitI(Inst::kId##ID, o0); } -#define ASMJIT_INST_1i(NAME, ID, T0) \ - inline Error NAME(const T0& o0) { return _emitter()->_emitI(Inst::kId##ID, o0); } - #define ASMJIT_INST_1c(NAME, ID, CONV, T0) \ inline Error NAME(uint32_t cc, const T0& o0) { return _emitter()->_emitI(CONV(cc), o0); } \ inline Error NAME##a(const T0& o0) { return _emitter()->_emitI(Inst::kId##ID##a, o0); } \ @@ -76,9 +73,6 @@ ASMJIT_BEGIN_SUB_NAMESPACE(x86) #define ASMJIT_INST_2x(NAME, ID, T0, T1) \ inline Error NAME(const T0& o0, const T1& o1) { return _emitter()->_emitI(Inst::kId##ID, o0, o1); } -#define ASMJIT_INST_2i(NAME, ID, T0, T1) \ - inline Error NAME(const T0& o0, const T1& o1) { return _emitter()->_emitI(Inst::kId##ID, o0, o1); } - #define ASMJIT_INST_2c(NAME, ID, CONV, T0, T1) \ inline Error NAME(uint32_t cc, const T0& o0, const T1& o1) { return _emitter()->_emitI(CONV(cc), o0, o1); } \ inline Error NAME##a(const T0& o0, const T1& o1) { return _emitter()->_emitI(Inst::kId##ID##a, o0, o1); } \ @@ -115,27 +109,12 @@ ASMJIT_BEGIN_SUB_NAMESPACE(x86) #define ASMJIT_INST_3x(NAME, ID, T0, T1, T2) \ inline Error NAME(const T0& o0, const T1& o1, const T2& o2) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2); } -#define ASMJIT_INST_3i(NAME, ID, T0, T1, T2) \ - inline Error NAME(const T0& o0, const T1& o1, const T2& o2) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2); } - -#define ASMJIT_INST_3ii(NAME, ID, T0, T1, T2) \ - inline Error NAME(const T0& o0, const T1& o1, const T2& o2) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2); } - #define ASMJIT_INST_4x(NAME, ID, T0, T1, T2, T3) \ inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2, o3); } -#define ASMJIT_INST_4i(NAME, ID, T0, T1, T2, T3) \ - inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2, o3); } - -#define ASMJIT_INST_4ii(NAME, ID, T0, T1, T2, T3) \ - inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2, o3); } - #define ASMJIT_INST_5x(NAME, ID, T0, T1, T2, T3, T4) \ inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, const T4& o4) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2, o3, o4); } -#define ASMJIT_INST_5i(NAME, ID, T0, T1, T2, T3, T4) \ - inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, const T4& o4) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2, o3, o4); } - #define ASMJIT_INST_6x(NAME, ID, T0, T1, T2, T3, T4, T5) \ inline Error NAME(const T0& o0, const T1& o1, const T2& o2, const T3& o3, const T4& o4, const T5& o5) { return _emitter()->_emitI(Inst::kId##ID, o0, o1, o2, o3, o4, o5); } @@ -444,6 +423,8 @@ public: //! \name VEX and EVEX Options //! \{ + //! Use VEX prefix instead of EVEX prefix (useful to select AVX_VNNI instruction instead of AVX512_VNNI). + inline This& vex() noexcept { return _addInstOptions(Inst::kOptionVex); } //! Force 3-byte VEX prefix (AVX+). inline This& vex3() noexcept { return _addInstOptions(Inst::kOptionVex3); } //! Force 4-byte EVEX prefix (AVX512+). @@ -481,19 +462,19 @@ public: ASMJIT_INST_2x(adc, Adc, Gp, Gp) // ANY ASMJIT_INST_2x(adc, Adc, Gp, Mem) // ANY - ASMJIT_INST_2i(adc, Adc, Gp, Imm) // ANY + ASMJIT_INST_2x(adc, Adc, Gp, Imm) // ANY ASMJIT_INST_2x(adc, Adc, Mem, Gp) // ANY - ASMJIT_INST_2i(adc, Adc, Mem, Imm) // ANY + ASMJIT_INST_2x(adc, Adc, Mem, Imm) // ANY ASMJIT_INST_2x(add, Add, Gp, Gp) // ANY ASMJIT_INST_2x(add, Add, Gp, Mem) // ANY - ASMJIT_INST_2i(add, Add, Gp, Imm) // ANY + ASMJIT_INST_2x(add, Add, Gp, Imm) // ANY ASMJIT_INST_2x(add, Add, Mem, Gp) // ANY - ASMJIT_INST_2i(add, Add, Mem, Imm) // ANY + ASMJIT_INST_2x(add, Add, Mem, Imm) // ANY ASMJIT_INST_2x(and_, And, Gp, Gp) // ANY ASMJIT_INST_2x(and_, And, Gp, Mem) // ANY - ASMJIT_INST_2i(and_, And, Gp, Imm) // ANY + ASMJIT_INST_2x(and_, And, Gp, Imm) // ANY ASMJIT_INST_2x(and_, And, Mem, Gp) // ANY - ASMJIT_INST_2i(and_, And, Mem, Imm) // ANY + ASMJIT_INST_2x(and_, And, Mem, Imm) // ANY ASMJIT_INST_2x(bound, Bound, Gp, Mem) // X86 ASMJIT_INST_2x(bsf, Bsf, Gp, Gp) // ANY ASMJIT_INST_2x(bsf, Bsf, Gp, Mem) // ANY @@ -501,21 +482,21 @@ public: ASMJIT_INST_2x(bsr, Bsr, Gp, Mem) // ANY ASMJIT_INST_1x(bswap, Bswap, Gp) // ANY ASMJIT_INST_2x(bt, Bt, Gp, Gp) // ANY - ASMJIT_INST_2i(bt, Bt, Gp, Imm) // ANY + ASMJIT_INST_2x(bt, Bt, Gp, Imm) // ANY ASMJIT_INST_2x(bt, Bt, Mem, Gp) // ANY - ASMJIT_INST_2i(bt, Bt, Mem, Imm) // ANY + ASMJIT_INST_2x(bt, Bt, Mem, Imm) // ANY ASMJIT_INST_2x(btc, Btc, Gp, Gp) // ANY - ASMJIT_INST_2i(btc, Btc, Gp, Imm) // ANY + ASMJIT_INST_2x(btc, Btc, Gp, Imm) // ANY ASMJIT_INST_2x(btc, Btc, Mem, Gp) // ANY - ASMJIT_INST_2i(btc, Btc, Mem, Imm) // ANY + ASMJIT_INST_2x(btc, Btc, Mem, Imm) // ANY ASMJIT_INST_2x(btr, Btr, Gp, Gp) // ANY - ASMJIT_INST_2i(btr, Btr, Gp, Imm) // ANY + ASMJIT_INST_2x(btr, Btr, Gp, Imm) // ANY ASMJIT_INST_2x(btr, Btr, Mem, Gp) // ANY - ASMJIT_INST_2i(btr, Btr, Mem, Imm) // ANY + ASMJIT_INST_2x(btr, Btr, Mem, Imm) // ANY ASMJIT_INST_2x(bts, Bts, Gp, Gp) // ANY - ASMJIT_INST_2i(bts, Bts, Gp, Imm) // ANY + ASMJIT_INST_2x(bts, Bts, Gp, Imm) // ANY ASMJIT_INST_2x(bts, Bts, Mem, Gp) // ANY - ASMJIT_INST_2i(bts, Bts, Mem, Imm) // ANY + ASMJIT_INST_2x(bts, Bts, Mem, Imm) // ANY ASMJIT_INST_1x(cbw, Cbw, Gp_AX) // ANY [EXPLICIT] AX <- Sign Extend AL ASMJIT_INST_2x(cdq, Cdq, Gp_EDX, Gp_EAX) // ANY [EXPLICIT] EDX:EAX <- Sign Extend EAX ASMJIT_INST_1x(cdqe, Cdqe, Gp_EAX) // X64 [EXPLICIT] RAX <- Sign Extend EAX @@ -525,14 +506,14 @@ public: ASMJIT_INST_1x(call, Call, Gp) // ANY ASMJIT_INST_1x(call, Call, Mem) // ANY ASMJIT_INST_1x(call, Call, Label) // ANY - ASMJIT_INST_1i(call, Call, Imm) // ANY + ASMJIT_INST_1x(call, Call, Imm) // ANY ASMJIT_INST_2c(cmov, Cmov, Condition::toCmovcc, Gp, Gp) // CMOV ASMJIT_INST_2c(cmov, Cmov, Condition::toCmovcc, Gp, Mem) // CMOV ASMJIT_INST_2x(cmp, Cmp, Gp, Gp) // ANY ASMJIT_INST_2x(cmp, Cmp, Gp, Mem) // ANY - ASMJIT_INST_2i(cmp, Cmp, Gp, Imm) // ANY + ASMJIT_INST_2x(cmp, Cmp, Gp, Imm) // ANY ASMJIT_INST_2x(cmp, Cmp, Mem, Gp) // ANY - ASMJIT_INST_2i(cmp, Cmp, Mem, Imm) // ANY + ASMJIT_INST_2x(cmp, Cmp, Mem, Imm) // ANY ASMJIT_INST_2x(cmps, Cmps, DS_ZSI, ES_ZDI) // ANY [EXPLICIT] ASMJIT_INST_3x(cmpxchg, Cmpxchg, Gp, Gp, Gp_ZAX) // I486 [EXPLICIT] ASMJIT_INST_3x(cmpxchg, Cmpxchg, Mem, Gp, Gp_ZAX) // I486 [EXPLICIT] @@ -550,9 +531,9 @@ public: ASMJIT_INST_3x(idiv, Idiv, Gp, Gp, Mem) // ANY [EXPLICIT] xDX[Rem]:xAX[Quot] <- xDX:xAX / m16|m32|m64 ASMJIT_INST_2x(imul, Imul, Gp, Gp) // ANY [EXPLICIT] AX <- AL * r8 | ra <- ra * rb ASMJIT_INST_2x(imul, Imul, Gp, Mem) // ANY [EXPLICIT] AX <- AL * m8 | ra <- ra * m16|m32|m64 - ASMJIT_INST_2i(imul, Imul, Gp, Imm) // ANY - ASMJIT_INST_3i(imul, Imul, Gp, Gp, Imm) // ANY - ASMJIT_INST_3i(imul, Imul, Gp, Mem, Imm) // ANY + ASMJIT_INST_2x(imul, Imul, Gp, Imm) // ANY + ASMJIT_INST_3x(imul, Imul, Gp, Gp, Imm) // ANY + ASMJIT_INST_3x(imul, Imul, Gp, Mem, Imm) // ANY ASMJIT_INST_3x(imul, Imul, Gp, Gp, Gp) // ANY [EXPLICIT] xDX:xAX <- xAX * r16|r32|r64 ASMJIT_INST_3x(imul, Imul, Gp, Gp, Mem) // ANY [EXPLICIT] xDX:xAX <- xAX * m16|m32|m64 ASMJIT_INST_1x(inc, Inc, Gp) // ANY @@ -575,9 +556,9 @@ public: ASMJIT_INST_2x(loopne, Loopne, Gp_ZCX, Imm) // ANY [EXPLICIT] Decrement xCX; short jump if xCX != 0 && ZF == 0. ASMJIT_INST_2x(mov, Mov, Gp, Gp) // ANY ASMJIT_INST_2x(mov, Mov, Gp, Mem) // ANY - ASMJIT_INST_2i(mov, Mov, Gp, Imm) // ANY + ASMJIT_INST_2x(mov, Mov, Gp, Imm) // ANY ASMJIT_INST_2x(mov, Mov, Mem, Gp) // ANY - ASMJIT_INST_2i(mov, Mov, Mem, Imm) // ANY + ASMJIT_INST_2x(mov, Mov, Mem, Imm) // ANY ASMJIT_INST_2x(mov, Mov, Gp, CReg) // ANY ASMJIT_INST_2x(mov, Mov, CReg, Gp) // ANY ASMJIT_INST_2x(mov, Mov, Gp, DReg) // ANY @@ -586,6 +567,9 @@ public: ASMJIT_INST_2x(mov, Mov, Mem, SReg) // ANY ASMJIT_INST_2x(mov, Mov, SReg, Gp) // ANY ASMJIT_INST_2x(mov, Mov, SReg, Mem) // ANY + ASMJIT_INST_2x(movabs, Movabs, Gp, Mem) // X64 + ASMJIT_INST_2x(movabs, Movabs, Gp, Imm) // X64 + ASMJIT_INST_2x(movabs, Movabs, Mem, Gp) // X64 ASMJIT_INST_2x(movnti, Movnti, Mem, Gp) // SSE2 ASMJIT_INST_2x(movs, Movs, ES_ZDI, DS_ZSI) // ANY [EXPLICIT] ASMJIT_INST_2x(movsx, Movsx, Gp, Gp) // ANY @@ -609,9 +593,9 @@ public: ASMJIT_INST_1x(not_, Not, Mem) // ANY ASMJIT_INST_2x(or_, Or, Gp, Gp) // ANY ASMJIT_INST_2x(or_, Or, Gp, Mem) // ANY - ASMJIT_INST_2i(or_, Or, Gp, Imm) // ANY + ASMJIT_INST_2x(or_, Or, Gp, Imm) // ANY ASMJIT_INST_2x(or_, Or, Mem, Gp) // ANY - ASMJIT_INST_2i(or_, Or, Mem, Imm) // ANY + ASMJIT_INST_2x(or_, Or, Mem, Imm) // ANY ASMJIT_INST_1x(pop, Pop, Gp) // ANY ASMJIT_INST_1x(pop, Pop, Mem) // ANY ASMJIT_INST_1x(pop, Pop, SReg); // ANY @@ -623,7 +607,7 @@ public: ASMJIT_INST_1x(push, Push, Gp) // ANY ASMJIT_INST_1x(push, Push, Mem) // ANY ASMJIT_INST_1x(push, Push, SReg) // ANY - ASMJIT_INST_1i(push, Push, Imm) // ANY + ASMJIT_INST_1x(push, Push, Imm) // ANY ASMJIT_INST_0x(pusha, Pusha) // X86 ASMJIT_INST_0x(pushad, Pushad) // X86 ASMJIT_INST_0x(pushf, Pushf) // ANY @@ -631,62 +615,62 @@ public: ASMJIT_INST_0x(pushfq, Pushfq) // X64 ASMJIT_INST_2x(rcl, Rcl, Gp, Gp_CL) // ANY ASMJIT_INST_2x(rcl, Rcl, Mem, Gp_CL) // ANY - ASMJIT_INST_2i(rcl, Rcl, Gp, Imm) // ANY - ASMJIT_INST_2i(rcl, Rcl, Mem, Imm) // ANY + ASMJIT_INST_2x(rcl, Rcl, Gp, Imm) // ANY + ASMJIT_INST_2x(rcl, Rcl, Mem, Imm) // ANY ASMJIT_INST_2x(rcr, Rcr, Gp, Gp_CL) // ANY ASMJIT_INST_2x(rcr, Rcr, Mem, Gp_CL) // ANY - ASMJIT_INST_2i(rcr, Rcr, Gp, Imm) // ANY - ASMJIT_INST_2i(rcr, Rcr, Mem, Imm) // ANY + ASMJIT_INST_2x(rcr, Rcr, Gp, Imm) // ANY + ASMJIT_INST_2x(rcr, Rcr, Mem, Imm) // ANY ASMJIT_INST_2x(rol, Rol, Gp, Gp_CL) // ANY ASMJIT_INST_2x(rol, Rol, Mem, Gp_CL) // ANY - ASMJIT_INST_2i(rol, Rol, Gp, Imm) // ANY - ASMJIT_INST_2i(rol, Rol, Mem, Imm) // ANY + ASMJIT_INST_2x(rol, Rol, Gp, Imm) // ANY + ASMJIT_INST_2x(rol, Rol, Mem, Imm) // ANY ASMJIT_INST_2x(ror, Ror, Gp, Gp_CL) // ANY ASMJIT_INST_2x(ror, Ror, Mem, Gp_CL) // ANY - ASMJIT_INST_2i(ror, Ror, Gp, Imm) // ANY - ASMJIT_INST_2i(ror, Ror, Mem, Imm) // ANY + ASMJIT_INST_2x(ror, Ror, Gp, Imm) // ANY + ASMJIT_INST_2x(ror, Ror, Mem, Imm) // ANY ASMJIT_INST_2x(sbb, Sbb, Gp, Gp) // ANY ASMJIT_INST_2x(sbb, Sbb, Gp, Mem) // ANY - ASMJIT_INST_2i(sbb, Sbb, Gp, Imm) // ANY + ASMJIT_INST_2x(sbb, Sbb, Gp, Imm) // ANY ASMJIT_INST_2x(sbb, Sbb, Mem, Gp) // ANY - ASMJIT_INST_2i(sbb, Sbb, Mem, Imm) // ANY + ASMJIT_INST_2x(sbb, Sbb, Mem, Imm) // ANY ASMJIT_INST_2x(sal, Sal, Gp, Gp_CL) // ANY ASMJIT_INST_2x(sal, Sal, Mem, Gp_CL) // ANY - ASMJIT_INST_2i(sal, Sal, Gp, Imm) // ANY - ASMJIT_INST_2i(sal, Sal, Mem, Imm) // ANY + ASMJIT_INST_2x(sal, Sal, Gp, Imm) // ANY + ASMJIT_INST_2x(sal, Sal, Mem, Imm) // ANY ASMJIT_INST_2x(sar, Sar, Gp, Gp_CL) // ANY ASMJIT_INST_2x(sar, Sar, Mem, Gp_CL) // ANY - ASMJIT_INST_2i(sar, Sar, Gp, Imm) // ANY - ASMJIT_INST_2i(sar, Sar, Mem, Imm) // ANY + ASMJIT_INST_2x(sar, Sar, Gp, Imm) // ANY + ASMJIT_INST_2x(sar, Sar, Mem, Imm) // ANY ASMJIT_INST_2x(scas, Scas, Gp_ZAX, ES_ZDI) // ANY [EXPLICIT] ASMJIT_INST_1c(set, Set, Condition::toSetcc, Gp) // ANY ASMJIT_INST_1c(set, Set, Condition::toSetcc, Mem) // ANY ASMJIT_INST_2x(shl, Shl, Gp, Gp_CL) // ANY ASMJIT_INST_2x(shl, Shl, Mem, Gp_CL) // ANY - ASMJIT_INST_2i(shl, Shl, Gp, Imm) // ANY - ASMJIT_INST_2i(shl, Shl, Mem, Imm) // ANY + ASMJIT_INST_2x(shl, Shl, Gp, Imm) // ANY + ASMJIT_INST_2x(shl, Shl, Mem, Imm) // ANY ASMJIT_INST_2x(shr, Shr, Gp, Gp_CL) // ANY ASMJIT_INST_2x(shr, Shr, Mem, Gp_CL) // ANY - ASMJIT_INST_2i(shr, Shr, Gp, Imm) // ANY - ASMJIT_INST_2i(shr, Shr, Mem, Imm) // ANY + ASMJIT_INST_2x(shr, Shr, Gp, Imm) // ANY + ASMJIT_INST_2x(shr, Shr, Mem, Imm) // ANY ASMJIT_INST_3x(shld, Shld, Gp, Gp, Gp_CL) // ANY ASMJIT_INST_3x(shld, Shld, Mem, Gp, Gp_CL) // ANY - ASMJIT_INST_3i(shld, Shld, Gp, Gp, Imm) // ANY - ASMJIT_INST_3i(shld, Shld, Mem, Gp, Imm) // ANY + ASMJIT_INST_3x(shld, Shld, Gp, Gp, Imm) // ANY + ASMJIT_INST_3x(shld, Shld, Mem, Gp, Imm) // ANY ASMJIT_INST_3x(shrd, Shrd, Gp, Gp, Gp_CL) // ANY ASMJIT_INST_3x(shrd, Shrd, Mem, Gp, Gp_CL) // ANY - ASMJIT_INST_3i(shrd, Shrd, Gp, Gp, Imm) // ANY - ASMJIT_INST_3i(shrd, Shrd, Mem, Gp, Imm) // ANY + ASMJIT_INST_3x(shrd, Shrd, Gp, Gp, Imm) // ANY + ASMJIT_INST_3x(shrd, Shrd, Mem, Gp, Imm) // ANY ASMJIT_INST_2x(stos, Stos, ES_ZDI, Gp_ZAX) // ANY [EXPLICIT] ASMJIT_INST_2x(sub, Sub, Gp, Gp) // ANY ASMJIT_INST_2x(sub, Sub, Gp, Mem) // ANY - ASMJIT_INST_2i(sub, Sub, Gp, Imm) // ANY + ASMJIT_INST_2x(sub, Sub, Gp, Imm) // ANY ASMJIT_INST_2x(sub, Sub, Mem, Gp) // ANY - ASMJIT_INST_2i(sub, Sub, Mem, Imm) // ANY + ASMJIT_INST_2x(sub, Sub, Mem, Imm) // ANY ASMJIT_INST_2x(test, Test, Gp, Gp) // ANY - ASMJIT_INST_2i(test, Test, Gp, Imm) // ANY + ASMJIT_INST_2x(test, Test, Gp, Imm) // ANY ASMJIT_INST_2x(test, Test, Mem, Gp) // ANY - ASMJIT_INST_2i(test, Test, Mem, Imm) // ANY + ASMJIT_INST_2x(test, Test, Mem, Imm) // ANY ASMJIT_INST_1x(ud0, Ud0, Reg) // ANY ASMJIT_INST_1x(ud0, Ud0, Mem) // ANY ASMJIT_INST_1x(ud1, Ud1, Reg) // ANY @@ -699,9 +683,9 @@ public: ASMJIT_INST_2x(xchg, Xchg, Gp, Mem) // ANY ASMJIT_INST_2x(xor_, Xor, Gp, Gp) // ANY ASMJIT_INST_2x(xor_, Xor, Gp, Mem) // ANY - ASMJIT_INST_2i(xor_, Xor, Gp, Imm) // ANY + ASMJIT_INST_2x(xor_, Xor, Gp, Imm) // ANY ASMJIT_INST_2x(xor_, Xor, Mem, Gp) // ANY - ASMJIT_INST_2i(xor_, Xor, Mem, Imm) // ANY + ASMJIT_INST_2x(xor_, Xor, Mem, Imm) // ANY //! \} @@ -709,8 +693,8 @@ public: //! \{ ASMJIT_INST_1x(aaa, Aaa, Gp) // X86 [EXPLICIT] - ASMJIT_INST_2i(aad, Aad, Gp, Imm) // X86 [EXPLICIT] - ASMJIT_INST_2i(aam, Aam, Gp, Imm) // X86 [EXPLICIT] + ASMJIT_INST_2x(aad, Aad, Gp, Imm) // X86 [EXPLICIT] + ASMJIT_INST_2x(aam, Aam, Gp, Imm) // X86 [EXPLICIT] ASMJIT_INST_1x(aas, Aas, Gp) // X86 [EXPLICIT] ASMJIT_INST_1x(daa, Daa, Gp) // X86 [EXPLICIT] ASMJIT_INST_1x(das, Das, Gp) // X86 [EXPLICIT] @@ -731,12 +715,12 @@ public: // NOTE: For some reason Doxygen is messed up here and thinks we are in cond. //! \endcond - ASMJIT_INST_2i(in, In, Gp_ZAX, Imm) // ANY + ASMJIT_INST_2x(in, In, Gp_ZAX, Imm) // ANY ASMJIT_INST_2x(in, In, Gp_ZAX, Gp_DX) // ANY ASMJIT_INST_2x(ins, Ins, ES_ZDI, Gp_DX) // ANY ASMJIT_INST_2x(out, Out, Imm, Gp_ZAX) // ANY - ASMJIT_INST_2i(out, Out, Gp_DX, Gp_ZAX) // ANY - ASMJIT_INST_2i(outs, Outs, Gp_DX, DS_ZSI) // ANY + ASMJIT_INST_2x(out, Out, Gp_DX, Gp_ZAX) // ANY + ASMJIT_INST_2x(outs, Outs, Gp_DX, DS_ZSI) // ANY //! \} @@ -808,8 +792,8 @@ public: ASMJIT_INST_3x(pdep, Pdep, Gp, Gp, Mem) // BMI2 ASMJIT_INST_3x(pext, Pext, Gp, Gp, Gp) // BMI2 ASMJIT_INST_3x(pext, Pext, Gp, Gp, Mem) // BMI2 - ASMJIT_INST_3i(rorx, Rorx, Gp, Gp, Imm) // BMI2 - ASMJIT_INST_3i(rorx, Rorx, Gp, Mem, Imm) // BMI2 + ASMJIT_INST_3x(rorx, Rorx, Gp, Gp, Imm) // BMI2 + ASMJIT_INST_3x(rorx, Rorx, Gp, Mem, Imm) // BMI2 ASMJIT_INST_3x(sarx, Sarx, Gp, Gp, Gp) // BMI2 ASMJIT_INST_3x(sarx, Sarx, Gp, Mem, Gp) // BMI2 ASMJIT_INST_3x(shlx, Shlx, Gp, Gp, Gp) // BMI2 @@ -952,7 +936,7 @@ public: ASMJIT_INST_2x(arpl, Arpl, Mem, Gp) // X86 ASMJIT_INST_0x(cli, Cli) // ANY ASMJIT_INST_0x(getsec, Getsec) // SMX - ASMJIT_INST_1i(int_, Int, Imm) // ANY + ASMJIT_INST_1x(int_, Int, Imm) // ANY ASMJIT_INST_0x(int3, Int3) // ANY ASMJIT_INST_0x(into, Into) // ANY ASMJIT_INST_2x(lar, Lar, Gp, Gp) // ANY @@ -1079,10 +1063,10 @@ public: //! \{ ASMJIT_INST_1x(llwpcb, Llwpcb, Gp) // LWP - ASMJIT_INST_3i(lwpins, Lwpins, Gp, Gp, Imm) // LWP - ASMJIT_INST_3i(lwpins, Lwpins, Gp, Mem, Imm) // LWP - ASMJIT_INST_3i(lwpval, Lwpval, Gp, Gp, Imm) // LWP - ASMJIT_INST_3i(lwpval, Lwpval, Gp, Mem, Imm) // LWP + ASMJIT_INST_3x(lwpins, Lwpins, Gp, Gp, Imm) // LWP + ASMJIT_INST_3x(lwpins, Lwpins, Gp, Mem, Imm) // LWP + ASMJIT_INST_3x(lwpval, Lwpval, Gp, Gp, Imm) // LWP + ASMJIT_INST_3x(lwpval, Lwpval, Gp, Mem, Imm) // LWP ASMJIT_INST_1x(slwpcb, Slwpcb, Gp) // LWP //! \} @@ -1090,7 +1074,7 @@ public: //! \name RTM & TSX Instructions //! \{ - ASMJIT_INST_0x(xabort, Xabort) // RTM + ASMJIT_INST_1x(xabort, Xabort, Imm) // RTM ASMJIT_INST_1x(xbegin, Xbegin, Label) // RTM ASMJIT_INST_1x(xbegin, Xbegin, Imm) // RTM ASMJIT_INST_0x(xend, Xend) // RTM @@ -1369,22 +1353,22 @@ public: ASMJIT_INST_2x(andpd, Andpd, Xmm, Mem) // SSE2 ASMJIT_INST_2x(andps, Andps, Xmm, Xmm) // SSE ASMJIT_INST_2x(andps, Andps, Xmm, Mem) // SSE - ASMJIT_INST_3i(blendpd, Blendpd, Xmm, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(blendpd, Blendpd, Xmm, Mem, Imm) // SSE4_1 - ASMJIT_INST_3i(blendps, Blendps, Xmm, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(blendps, Blendps, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(blendpd, Blendpd, Xmm, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(blendpd, Blendpd, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(blendps, Blendps, Xmm, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(blendps, Blendps, Xmm, Mem, Imm) // SSE4_1 ASMJIT_INST_3x(blendvpd, Blendvpd, Xmm, Xmm, XMM0) // SSE4_1 [EXPLICIT] ASMJIT_INST_3x(blendvpd, Blendvpd, Xmm, Mem, XMM0) // SSE4_1 [EXPLICIT] ASMJIT_INST_3x(blendvps, Blendvps, Xmm, Xmm, XMM0) // SSE4_1 [EXPLICIT] ASMJIT_INST_3x(blendvps, Blendvps, Xmm, Mem, XMM0) // SSE4_1 [EXPLICIT] - ASMJIT_INST_3i(cmppd, Cmppd, Xmm, Xmm, Imm) // SSE2 - ASMJIT_INST_3i(cmppd, Cmppd, Xmm, Mem, Imm) // SSE2 - ASMJIT_INST_3i(cmpps, Cmpps, Xmm, Xmm, Imm) // SSE - ASMJIT_INST_3i(cmpps, Cmpps, Xmm, Mem, Imm) // SSE - ASMJIT_INST_3i(cmpsd, Cmpsd, Xmm, Xmm, Imm) // SSE2 - ASMJIT_INST_3i(cmpsd, Cmpsd, Xmm, Mem, Imm) // SSE2 - ASMJIT_INST_3i(cmpss, Cmpss, Xmm, Xmm, Imm) // SSE - ASMJIT_INST_3i(cmpss, Cmpss, Xmm, Mem, Imm) // SSE + ASMJIT_INST_3x(cmppd, Cmppd, Xmm, Xmm, Imm) // SSE2 + ASMJIT_INST_3x(cmppd, Cmppd, Xmm, Mem, Imm) // SSE2 + ASMJIT_INST_3x(cmpps, Cmpps, Xmm, Xmm, Imm) // SSE + ASMJIT_INST_3x(cmpps, Cmpps, Xmm, Mem, Imm) // SSE + ASMJIT_INST_3x(cmpsd, Cmpsd, Xmm, Xmm, Imm) // SSE2 + ASMJIT_INST_3x(cmpsd, Cmpsd, Xmm, Mem, Imm) // SSE2 + ASMJIT_INST_3x(cmpss, Cmpss, Xmm, Xmm, Imm) // SSE + ASMJIT_INST_3x(cmpss, Cmpss, Xmm, Mem, Imm) // SSE ASMJIT_INST_2x(comisd, Comisd, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(comisd, Comisd, Xmm, Mem) // SSE2 ASMJIT_INST_2x(comiss, Comiss, Xmm, Xmm) // SSE @@ -1441,14 +1425,14 @@ public: ASMJIT_INST_2x(divsd, Divsd, Xmm, Mem) // SSE2 ASMJIT_INST_2x(divss, Divss, Xmm, Xmm) // SSE ASMJIT_INST_2x(divss, Divss, Xmm, Mem) // SSE - ASMJIT_INST_3i(dppd, Dppd, Xmm, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(dppd, Dppd, Xmm, Mem, Imm) // SSE4_1 - ASMJIT_INST_3i(dpps, Dpps, Xmm, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(dpps, Dpps, Xmm, Mem, Imm) // SSE4_1 - ASMJIT_INST_3i(extractps, Extractps, Gp, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(extractps, Extractps, Mem, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(dppd, Dppd, Xmm, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(dppd, Dppd, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(dpps, Dpps, Xmm, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(dpps, Dpps, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(extractps, Extractps, Gp, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(extractps, Extractps, Mem, Xmm, Imm) // SSE4_1 ASMJIT_INST_2x(extrq, Extrq, Xmm, Xmm) // SSE4A - ASMJIT_INST_3ii(extrq, Extrq, Xmm, Imm, Imm) // SSE4A + ASMJIT_INST_3x(extrq, Extrq, Xmm, Imm, Imm) // SSE4A ASMJIT_INST_2x(haddpd, Haddpd, Xmm, Xmm) // SSE3 ASMJIT_INST_2x(haddpd, Haddpd, Xmm, Mem) // SSE3 ASMJIT_INST_2x(haddps, Haddps, Xmm, Xmm) // SSE3 @@ -1457,10 +1441,10 @@ public: ASMJIT_INST_2x(hsubpd, Hsubpd, Xmm, Mem) // SSE3 ASMJIT_INST_2x(hsubps, Hsubps, Xmm, Xmm) // SSE3 ASMJIT_INST_2x(hsubps, Hsubps, Xmm, Mem) // SSE3 - ASMJIT_INST_3i(insertps, Insertps, Xmm, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(insertps, Insertps, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(insertps, Insertps, Xmm, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(insertps, Insertps, Xmm, Mem, Imm) // SSE4_1 ASMJIT_INST_2x(insertq, Insertq, Xmm, Xmm) // SSE4A - ASMJIT_INST_4ii(insertq, Insertq, Xmm, Xmm, Imm, Imm) // SSE4A + ASMJIT_INST_4x(insertq, Insertq, Xmm, Xmm, Imm, Imm) // SSE4A ASMJIT_INST_2x(lddqu, Lddqu, Xmm, Mem) // SSE3 ASMJIT_INST_3x(maskmovq, Maskmovq, Mm, Mm, DS_ZDI) // SSE [EXPLICIT] ASMJIT_INST_3x(maskmovdqu, Maskmovdqu, Xmm, Xmm, DS_ZDI) // SSE2 [EXPLICIT] @@ -1549,8 +1533,8 @@ public: ASMJIT_INST_2x(movups, Movups, Xmm, Xmm) // SSE ASMJIT_INST_2x(movups, Movups, Xmm, Mem) // SSE ASMJIT_INST_2x(movups, Movups, Mem, Xmm) // SSE - ASMJIT_INST_3i(mpsadbw, Mpsadbw, Xmm, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(mpsadbw, Mpsadbw, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(mpsadbw, Mpsadbw, Xmm, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(mpsadbw, Mpsadbw, Xmm, Mem, Imm) // SSE4_1 ASMJIT_INST_2x(mulpd, Mulpd, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(mulpd, Mulpd, Xmm, Mem) // SSE2 ASMJIT_INST_2x(mulps, Mulps, Xmm, Xmm) // SSE @@ -1621,10 +1605,10 @@ public: ASMJIT_INST_2x(paddw, Paddw, Mm, Mem) // MMX ASMJIT_INST_2x(paddw, Paddw, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(paddw, Paddw, Xmm, Mem) // SSE2 - ASMJIT_INST_3i(palignr, Palignr, Mm, Mm, Imm) // SSSE3 - ASMJIT_INST_3i(palignr, Palignr, Mm, Mem, Imm) // SSSE3 - ASMJIT_INST_3i(palignr, Palignr, Xmm, Xmm, Imm) // SSSE3 - ASMJIT_INST_3i(palignr, Palignr, Xmm, Mem, Imm) // SSSE3 + ASMJIT_INST_3x(palignr, Palignr, Mm, Mm, Imm) // SSSE3 + ASMJIT_INST_3x(palignr, Palignr, Mm, Mem, Imm) // SSSE3 + ASMJIT_INST_3x(palignr, Palignr, Xmm, Xmm, Imm) // SSSE3 + ASMJIT_INST_3x(palignr, Palignr, Xmm, Mem, Imm) // SSSE3 ASMJIT_INST_2x(pand, Pand, Mm, Mm) // MMX ASMJIT_INST_2x(pand, Pand, Mm, Mem) // MMX ASMJIT_INST_2x(pand, Pand, Xmm, Xmm) // SSE2 @@ -1643,10 +1627,10 @@ public: ASMJIT_INST_2x(pavgw, Pavgw, Xmm, Mem) // SSE2 ASMJIT_INST_3x(pblendvb, Pblendvb, Xmm, Xmm, XMM0) // SSE4_1 [EXPLICIT] ASMJIT_INST_3x(pblendvb, Pblendvb, Xmm, Mem, XMM0) // SSE4_1 [EXPLICIT] - ASMJIT_INST_3i(pblendw, Pblendw, Xmm, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(pblendw, Pblendw, Xmm, Mem, Imm) // SSE4_1 - ASMJIT_INST_3i(pclmulqdq, Pclmulqdq, Xmm, Xmm, Imm) // PCLMULQDQ. - ASMJIT_INST_3i(pclmulqdq, Pclmulqdq, Xmm, Mem, Imm) // PCLMULQDQ. + ASMJIT_INST_3x(pblendw, Pblendw, Xmm, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(pblendw, Pblendw, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(pclmulqdq, Pclmulqdq, Xmm, Xmm, Imm) // PCLMULQDQ. + ASMJIT_INST_3x(pclmulqdq, Pclmulqdq, Xmm, Mem, Imm) // PCLMULQDQ. ASMJIT_INST_6x(pcmpestri, Pcmpestri, Xmm, Xmm, Imm, Gp_ECX, Gp_EAX, Gp_EDX) // SSE4_2 [EXPLICIT] ASMJIT_INST_6x(pcmpestri, Pcmpestri, Xmm, Mem, Imm, Gp_ECX, Gp_EAX, Gp_EDX) // SSE4_2 [EXPLICIT] ASMJIT_INST_6x(pcmpestrm, Pcmpestrm, Xmm, Xmm, Imm, XMM0, Gp_EAX, Gp_EDX) // SSE4_2 [EXPLICIT] @@ -1683,15 +1667,15 @@ public: ASMJIT_INST_4x(pcmpistri, Pcmpistri, Xmm, Mem, Imm, Gp_ECX) // SSE4_2 [EXPLICIT] ASMJIT_INST_4x(pcmpistrm, Pcmpistrm, Xmm, Xmm, Imm, XMM0) // SSE4_2 [EXPLICIT] ASMJIT_INST_4x(pcmpistrm, Pcmpistrm, Xmm, Mem, Imm, XMM0) // SSE4_2 [EXPLICIT] - ASMJIT_INST_3i(pextrb, Pextrb, Gp, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(pextrb, Pextrb, Mem, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(pextrd, Pextrd, Gp, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(pextrd, Pextrd, Mem, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(pextrq, Pextrq, Gp, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(pextrq, Pextrq, Mem, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(pextrw, Pextrw, Gp, Mm, Imm) // SSE - ASMJIT_INST_3i(pextrw, Pextrw, Gp, Xmm, Imm) // SSE2 - ASMJIT_INST_3i(pextrw, Pextrw, Mem, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(pextrb, Pextrb, Gp, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(pextrb, Pextrb, Mem, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(pextrd, Pextrd, Gp, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(pextrd, Pextrd, Mem, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(pextrq, Pextrq, Gp, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(pextrq, Pextrq, Mem, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(pextrw, Pextrw, Gp, Mm, Imm) // SSE + ASMJIT_INST_3x(pextrw, Pextrw, Gp, Xmm, Imm) // SSE2 + ASMJIT_INST_3x(pextrw, Pextrw, Mem, Xmm, Imm) // SSE4_1 ASMJIT_INST_2x(phaddd, Phaddd, Mm, Mm) // SSSE3 ASMJIT_INST_2x(phaddd, Phaddd, Mm, Mem) // SSSE3 ASMJIT_INST_2x(phaddd, Phaddd, Xmm, Xmm) // SSSE3 @@ -1718,16 +1702,16 @@ public: ASMJIT_INST_2x(phsubw, Phsubw, Mm, Mem) // SSSE3 ASMJIT_INST_2x(phsubw, Phsubw, Xmm, Xmm) // SSSE3 ASMJIT_INST_2x(phsubw, Phsubw, Xmm, Mem) // SSSE3 - ASMJIT_INST_3i(pinsrb, Pinsrb, Xmm, Gp, Imm) // SSE4_1 - ASMJIT_INST_3i(pinsrb, Pinsrb, Xmm, Mem, Imm) // SSE4_1 - ASMJIT_INST_3i(pinsrd, Pinsrd, Xmm, Gp, Imm) // SSE4_1 - ASMJIT_INST_3i(pinsrd, Pinsrd, Xmm, Mem, Imm) // SSE4_1 - ASMJIT_INST_3i(pinsrq, Pinsrq, Xmm, Gp, Imm) // SSE4_1 - ASMJIT_INST_3i(pinsrq, Pinsrq, Xmm, Mem, Imm) // SSE4_1 - ASMJIT_INST_3i(pinsrw, Pinsrw, Mm, Gp, Imm) // SSE - ASMJIT_INST_3i(pinsrw, Pinsrw, Mm, Mem, Imm) // SSE - ASMJIT_INST_3i(pinsrw, Pinsrw, Xmm, Gp, Imm) // SSE2 - ASMJIT_INST_3i(pinsrw, Pinsrw, Xmm, Mem, Imm) // SSE2 + ASMJIT_INST_3x(pinsrb, Pinsrb, Xmm, Gp, Imm) // SSE4_1 + ASMJIT_INST_3x(pinsrb, Pinsrb, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(pinsrd, Pinsrd, Xmm, Gp, Imm) // SSE4_1 + ASMJIT_INST_3x(pinsrd, Pinsrd, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(pinsrq, Pinsrq, Xmm, Gp, Imm) // SSE4_1 + ASMJIT_INST_3x(pinsrq, Pinsrq, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(pinsrw, Pinsrw, Mm, Gp, Imm) // SSE + ASMJIT_INST_3x(pinsrw, Pinsrw, Mm, Mem, Imm) // SSE + ASMJIT_INST_3x(pinsrw, Pinsrw, Xmm, Gp, Imm) // SSE2 + ASMJIT_INST_3x(pinsrw, Pinsrw, Xmm, Mem, Imm) // SSE2 ASMJIT_INST_2x(pmaddubsw, Pmaddubsw, Mm, Mm) // SSSE3 ASMJIT_INST_2x(pmaddubsw, Pmaddubsw, Mm, Mem) // SSSE3 ASMJIT_INST_2x(pmaddubsw, Pmaddubsw, Xmm, Xmm) // SSSE3 @@ -1828,47 +1812,47 @@ public: ASMJIT_INST_2x(psadbw, Psadbw, Xmm, Mem) // SSE ASMJIT_INST_2x(pslld, Pslld, Mm, Mm) // MMX ASMJIT_INST_2x(pslld, Pslld, Mm, Mem) // MMX - ASMJIT_INST_2i(pslld, Pslld, Mm, Imm) // MMX + ASMJIT_INST_2x(pslld, Pslld, Mm, Imm) // MMX ASMJIT_INST_2x(pslld, Pslld, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(pslld, Pslld, Xmm, Mem) // SSE2 - ASMJIT_INST_2i(pslld, Pslld, Xmm, Imm) // SSE2 - ASMJIT_INST_2i(pslldq, Pslldq, Xmm, Imm) // SSE2 + ASMJIT_INST_2x(pslld, Pslld, Xmm, Imm) // SSE2 + ASMJIT_INST_2x(pslldq, Pslldq, Xmm, Imm) // SSE2 ASMJIT_INST_2x(psllq, Psllq, Mm, Mm) // MMX ASMJIT_INST_2x(psllq, Psllq, Mm, Mem) // MMX - ASMJIT_INST_2i(psllq, Psllq, Mm, Imm) // MMX + ASMJIT_INST_2x(psllq, Psllq, Mm, Imm) // MMX ASMJIT_INST_2x(psllq, Psllq, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(psllq, Psllq, Xmm, Mem) // SSE2 - ASMJIT_INST_2i(psllq, Psllq, Xmm, Imm) // SSE2 + ASMJIT_INST_2x(psllq, Psllq, Xmm, Imm) // SSE2 ASMJIT_INST_2x(psllw, Psllw, Mm, Mm) // MMX ASMJIT_INST_2x(psllw, Psllw, Mm, Mem) // MMX - ASMJIT_INST_2i(psllw, Psllw, Mm, Imm) // MMX + ASMJIT_INST_2x(psllw, Psllw, Mm, Imm) // MMX ASMJIT_INST_2x(psllw, Psllw, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(psllw, Psllw, Xmm, Mem) // SSE2 - ASMJIT_INST_2i(psllw, Psllw, Xmm, Imm) // SSE2 + ASMJIT_INST_2x(psllw, Psllw, Xmm, Imm) // SSE2 ASMJIT_INST_2x(psrad, Psrad, Mm, Mm) // MMX ASMJIT_INST_2x(psrad, Psrad, Mm, Mem) // MMX - ASMJIT_INST_2i(psrad, Psrad, Mm, Imm) // MMX + ASMJIT_INST_2x(psrad, Psrad, Mm, Imm) // MMX ASMJIT_INST_2x(psrad, Psrad, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(psrad, Psrad, Xmm, Mem) // SSE2 - ASMJIT_INST_2i(psrad, Psrad, Xmm, Imm) // SSE2 + ASMJIT_INST_2x(psrad, Psrad, Xmm, Imm) // SSE2 ASMJIT_INST_2x(psraw, Psraw, Mm, Mm) // MMX ASMJIT_INST_2x(psraw, Psraw, Mm, Mem) // MMX - ASMJIT_INST_2i(psraw, Psraw, Mm, Imm) // MMX + ASMJIT_INST_2x(psraw, Psraw, Mm, Imm) // MMX ASMJIT_INST_2x(psraw, Psraw, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(psraw, Psraw, Xmm, Mem) // SSE2 - ASMJIT_INST_2i(psraw, Psraw, Xmm, Imm) // SSE2 + ASMJIT_INST_2x(psraw, Psraw, Xmm, Imm) // SSE2 ASMJIT_INST_2x(pshufb, Pshufb, Mm, Mm) // SSSE3 ASMJIT_INST_2x(pshufb, Pshufb, Mm, Mem) // SSSE3 ASMJIT_INST_2x(pshufb, Pshufb, Xmm, Xmm) // SSSE3 ASMJIT_INST_2x(pshufb, Pshufb, Xmm, Mem) // SSSE3 - ASMJIT_INST_3i(pshufd, Pshufd, Xmm, Xmm, Imm) // SSE2 - ASMJIT_INST_3i(pshufd, Pshufd, Xmm, Mem, Imm) // SSE2 - ASMJIT_INST_3i(pshufhw, Pshufhw, Xmm, Xmm, Imm) // SSE2 - ASMJIT_INST_3i(pshufhw, Pshufhw, Xmm, Mem, Imm) // SSE2 - ASMJIT_INST_3i(pshuflw, Pshuflw, Xmm, Xmm, Imm) // SSE2 - ASMJIT_INST_3i(pshuflw, Pshuflw, Xmm, Mem, Imm) // SSE2 - ASMJIT_INST_3i(pshufw, Pshufw, Mm, Mm, Imm) // SSE - ASMJIT_INST_3i(pshufw, Pshufw, Mm, Mem, Imm) // SSE + ASMJIT_INST_3x(pshufd, Pshufd, Xmm, Xmm, Imm) // SSE2 + ASMJIT_INST_3x(pshufd, Pshufd, Xmm, Mem, Imm) // SSE2 + ASMJIT_INST_3x(pshufhw, Pshufhw, Xmm, Xmm, Imm) // SSE2 + ASMJIT_INST_3x(pshufhw, Pshufhw, Xmm, Mem, Imm) // SSE2 + ASMJIT_INST_3x(pshuflw, Pshuflw, Xmm, Xmm, Imm) // SSE2 + ASMJIT_INST_3x(pshuflw, Pshuflw, Xmm, Mem, Imm) // SSE2 + ASMJIT_INST_3x(pshufw, Pshufw, Mm, Mm, Imm) // SSE + ASMJIT_INST_3x(pshufw, Pshufw, Mm, Mem, Imm) // SSE ASMJIT_INST_2x(psignb, Psignb, Mm, Mm) // SSSE3 ASMJIT_INST_2x(psignb, Psignb, Mm, Mem) // SSSE3 ASMJIT_INST_2x(psignb, Psignb, Xmm, Xmm) // SSSE3 @@ -1883,23 +1867,23 @@ public: ASMJIT_INST_2x(psignw, Psignw, Xmm, Mem) // SSSE3 ASMJIT_INST_2x(psrld, Psrld, Mm, Mm) // MMX ASMJIT_INST_2x(psrld, Psrld, Mm, Mem) // MMX - ASMJIT_INST_2i(psrld, Psrld, Mm, Imm) // MMX + ASMJIT_INST_2x(psrld, Psrld, Mm, Imm) // MMX ASMJIT_INST_2x(psrld, Psrld, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(psrld, Psrld, Xmm, Mem) // SSE2 - ASMJIT_INST_2i(psrld, Psrld, Xmm, Imm) // SSE2 - ASMJIT_INST_2i(psrldq, Psrldq, Xmm, Imm) // SSE2 + ASMJIT_INST_2x(psrld, Psrld, Xmm, Imm) // SSE2 + ASMJIT_INST_2x(psrldq, Psrldq, Xmm, Imm) // SSE2 ASMJIT_INST_2x(psrlq, Psrlq, Mm, Mm) // MMX ASMJIT_INST_2x(psrlq, Psrlq, Mm, Mem) // MMX - ASMJIT_INST_2i(psrlq, Psrlq, Mm, Imm) // MMX + ASMJIT_INST_2x(psrlq, Psrlq, Mm, Imm) // MMX ASMJIT_INST_2x(psrlq, Psrlq, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(psrlq, Psrlq, Xmm, Mem) // SSE2 - ASMJIT_INST_2i(psrlq, Psrlq, Xmm, Imm) // SSE2 + ASMJIT_INST_2x(psrlq, Psrlq, Xmm, Imm) // SSE2 ASMJIT_INST_2x(psrlw, Psrlw, Mm, Mm) // MMX ASMJIT_INST_2x(psrlw, Psrlw, Mm, Mem) // MMX - ASMJIT_INST_2i(psrlw, Psrlw, Mm, Imm) // MMX + ASMJIT_INST_2x(psrlw, Psrlw, Mm, Imm) // MMX ASMJIT_INST_2x(psrlw, Psrlw, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(psrlw, Psrlw, Xmm, Mem) // SSE2 - ASMJIT_INST_2i(psrlw, Psrlw, Xmm, Imm) // SSE2 + ASMJIT_INST_2x(psrlw, Psrlw, Xmm, Imm) // SSE2 ASMJIT_INST_2x(psubb, Psubb, Mm, Mm) // MMX ASMJIT_INST_2x(psubb, Psubb, Mm, Mem) // MMX ASMJIT_INST_2x(psubb, Psubb, Xmm, Xmm) // SSE2 @@ -1970,22 +1954,22 @@ public: ASMJIT_INST_2x(rcpps, Rcpps, Xmm, Mem) // SSE ASMJIT_INST_2x(rcpss, Rcpss, Xmm, Xmm) // SSE ASMJIT_INST_2x(rcpss, Rcpss, Xmm, Mem) // SSE - ASMJIT_INST_3i(roundpd, Roundpd, Xmm, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(roundpd, Roundpd, Xmm, Mem, Imm) // SSE4_1 - ASMJIT_INST_3i(roundps, Roundps, Xmm, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(roundps, Roundps, Xmm, Mem, Imm) // SSE4_1 - ASMJIT_INST_3i(roundsd, Roundsd, Xmm, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(roundsd, Roundsd, Xmm, Mem, Imm) // SSE4_1 - ASMJIT_INST_3i(roundss, Roundss, Xmm, Xmm, Imm) // SSE4_1 - ASMJIT_INST_3i(roundss, Roundss, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(roundpd, Roundpd, Xmm, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(roundpd, Roundpd, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(roundps, Roundps, Xmm, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(roundps, Roundps, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(roundsd, Roundsd, Xmm, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(roundsd, Roundsd, Xmm, Mem, Imm) // SSE4_1 + ASMJIT_INST_3x(roundss, Roundss, Xmm, Xmm, Imm) // SSE4_1 + ASMJIT_INST_3x(roundss, Roundss, Xmm, Mem, Imm) // SSE4_1 ASMJIT_INST_2x(rsqrtps, Rsqrtps, Xmm, Xmm) // SSE ASMJIT_INST_2x(rsqrtps, Rsqrtps, Xmm, Mem) // SSE ASMJIT_INST_2x(rsqrtss, Rsqrtss, Xmm, Xmm) // SSE ASMJIT_INST_2x(rsqrtss, Rsqrtss, Xmm, Mem) // SSE - ASMJIT_INST_3i(shufpd, Shufpd, Xmm, Xmm, Imm) // SSE2 - ASMJIT_INST_3i(shufpd, Shufpd, Xmm, Mem, Imm) // SSE2 - ASMJIT_INST_3i(shufps, Shufps, Xmm, Xmm, Imm) // SSE - ASMJIT_INST_3i(shufps, Shufps, Xmm, Mem, Imm) // SSE + ASMJIT_INST_3x(shufpd, Shufpd, Xmm, Xmm, Imm) // SSE2 + ASMJIT_INST_3x(shufpd, Shufpd, Xmm, Mem, Imm) // SSE2 + ASMJIT_INST_3x(shufps, Shufps, Xmm, Xmm, Imm) // SSE + ASMJIT_INST_3x(shufps, Shufps, Xmm, Mem, Imm) // SSE ASMJIT_INST_2x(sqrtpd, Sqrtpd, Xmm, Xmm) // SSE2 ASMJIT_INST_2x(sqrtpd, Sqrtpd, Xmm, Mem) // SSE2 ASMJIT_INST_2x(sqrtps, Sqrtps, Xmm, Xmm) // SSE @@ -2100,8 +2084,8 @@ public: ASMJIT_INST_2x(aesenclast, Aesenclast, Xmm, Mem) // AESNI ASMJIT_INST_2x(aesimc, Aesimc, Xmm, Xmm) // AESNI ASMJIT_INST_2x(aesimc, Aesimc, Xmm, Mem) // AESNI - ASMJIT_INST_3i(aeskeygenassist, Aeskeygenassist, Xmm, Xmm, Imm) // AESNI - ASMJIT_INST_3i(aeskeygenassist, Aeskeygenassist, Xmm, Mem, Imm) // AESNI + ASMJIT_INST_3x(aeskeygenassist, Aeskeygenassist, Xmm, Xmm, Imm) // AESNI + ASMJIT_INST_3x(aeskeygenassist, Aeskeygenassist, Xmm, Mem, Imm) // AESNI //! \} @@ -2114,8 +2098,8 @@ public: ASMJIT_INST_2x(sha1msg2, Sha1msg2, Xmm, Mem) // SHA ASMJIT_INST_2x(sha1nexte, Sha1nexte, Xmm, Xmm) // SHA ASMJIT_INST_2x(sha1nexte, Sha1nexte, Xmm, Mem) // SHA - ASMJIT_INST_3i(sha1rnds4, Sha1rnds4, Xmm, Xmm, Imm) // SHA - ASMJIT_INST_3i(sha1rnds4, Sha1rnds4, Xmm, Mem, Imm) // SHA + ASMJIT_INST_3x(sha1rnds4, Sha1rnds4, Xmm, Xmm, Imm) // SHA + ASMJIT_INST_3x(sha1rnds4, Sha1rnds4, Xmm, Mem, Imm) // SHA ASMJIT_INST_2x(sha256msg1, Sha256msg1, Xmm, Xmm) // SHA ASMJIT_INST_2x(sha256msg1, Sha256msg1, Xmm, Mem) // SHA ASMJIT_INST_2x(sha256msg2, Sha256msg2, Xmm, Xmm) // SHA @@ -2131,10 +2115,10 @@ public: // NOTE: For some reason Doxygen is messed up here and thinks we are in cond. //! \endcond - ASMJIT_INST_3i(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Xmm, Imm) // GFNI - ASMJIT_INST_3i(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Mem, Imm) // GFNI - ASMJIT_INST_3i(gf2p8affineqb, Gf2p8affineqb, Xmm, Xmm, Imm) // GFNI - ASMJIT_INST_3i(gf2p8affineqb, Gf2p8affineqb, Xmm, Mem, Imm) // GFNI + ASMJIT_INST_3x(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Xmm, Imm) // GFNI + ASMJIT_INST_3x(gf2p8affineinvqb, Gf2p8affineinvqb, Xmm, Mem, Imm) // GFNI + ASMJIT_INST_3x(gf2p8affineqb, Gf2p8affineqb, Xmm, Xmm, Imm) // GFNI + ASMJIT_INST_3x(gf2p8affineqb, Gf2p8affineqb, Xmm, Mem, Imm) // GFNI ASMJIT_INST_2x(gf2p8mulb, Gf2p8mulb, Xmm, Xmm) // GFNI ASMJIT_INST_2x(gf2p8mulb, Gf2p8mulb, Xmm, Mem) // GFNI @@ -2187,14 +2171,14 @@ public: ASMJIT_INST_2x(kortestq, Kortestq, KReg, KReg) // AVX512_BW ASMJIT_INST_2x(kortestw, Kortestw, KReg, KReg) // AVX512_F ASMJIT_INST_3x(korw, Korw, KReg, KReg, KReg) // AVX512_F - ASMJIT_INST_3i(kshiftlb, Kshiftlb, KReg, KReg, Imm) // AVX512_DQ - ASMJIT_INST_3i(kshiftld, Kshiftld, KReg, KReg, Imm) // AVX512_BW - ASMJIT_INST_3i(kshiftlq, Kshiftlq, KReg, KReg, Imm) // AVX512_BW - ASMJIT_INST_3i(kshiftlw, Kshiftlw, KReg, KReg, Imm) // AVX512_F - ASMJIT_INST_3i(kshiftrb, Kshiftrb, KReg, KReg, Imm) // AVX512_DQ - ASMJIT_INST_3i(kshiftrd, Kshiftrd, KReg, KReg, Imm) // AVX512_BW - ASMJIT_INST_3i(kshiftrq, Kshiftrq, KReg, KReg, Imm) // AVX512_BW - ASMJIT_INST_3i(kshiftrw, Kshiftrw, KReg, KReg, Imm) // AVX512_F + ASMJIT_INST_3x(kshiftlb, Kshiftlb, KReg, KReg, Imm) // AVX512_DQ + ASMJIT_INST_3x(kshiftld, Kshiftld, KReg, KReg, Imm) // AVX512_BW + ASMJIT_INST_3x(kshiftlq, Kshiftlq, KReg, KReg, Imm) // AVX512_BW + ASMJIT_INST_3x(kshiftlw, Kshiftlw, KReg, KReg, Imm) // AVX512_F + ASMJIT_INST_3x(kshiftrb, Kshiftrb, KReg, KReg, Imm) // AVX512_DQ + ASMJIT_INST_3x(kshiftrd, Kshiftrd, KReg, KReg, Imm) // AVX512_BW + ASMJIT_INST_3x(kshiftrq, Kshiftrq, KReg, KReg, Imm) // AVX512_BW + ASMJIT_INST_3x(kshiftrw, Kshiftrw, KReg, KReg, Imm) // AVX512_F ASMJIT_INST_2x(ktestb, Ktestb, KReg, KReg) // AVX512_DQ ASMJIT_INST_2x(ktestd, Ktestd, KReg, KReg) // AVX512_BW ASMJIT_INST_2x(ktestq, Ktestq, KReg, KReg) // AVX512_BW @@ -2236,12 +2220,12 @@ public: ASMJIT_INST_3x(vaesenclast, Vaesenclast, Vec, Vec, Mem) // AVX+AESNI VAES ASMJIT_INST_2x(vaesimc, Vaesimc, Xmm, Xmm) // AVX+AESNI ASMJIT_INST_2x(vaesimc, Vaesimc, Xmm, Mem) // AVX+AESNI - ASMJIT_INST_3i(vaeskeygenassist, Vaeskeygenassist, Xmm, Xmm, Imm) // AVX+AESNI - ASMJIT_INST_3i(vaeskeygenassist, Vaeskeygenassist, Xmm, Mem, Imm) // AVX+AESNI - ASMJIT_INST_4i(valignd, Valignd, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(valignd, Valignd, Vec, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(valignq, Valignq, Vec, Vec, Vec, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_4i(valignq, Valignq, Vec, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vaeskeygenassist, Vaeskeygenassist, Xmm, Xmm, Imm) // AVX+AESNI + ASMJIT_INST_3x(vaeskeygenassist, Vaeskeygenassist, Xmm, Mem, Imm) // AVX+AESNI + ASMJIT_INST_4x(valignd, Valignd, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(valignd, Valignd, Vec, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(valignq, Valignq, Vec, Vec, Vec, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_4x(valignq, Valignq, Vec, Vec, Mem, Imm) // AVX512_F{kz|b64} ASMJIT_INST_3x(vandnpd, Vandnpd, Vec, Vec, Vec) // AVX AVX512_DQ{kz|b64} ASMJIT_INST_3x(vandnpd, Vandnpd, Vec, Vec, Mem) // AVX AVX512_DQ{kz|b64} ASMJIT_INST_3x(vandnps, Vandnps, Vec, Vec, Vec) // AVX AVX512_DQ{kz|b32} @@ -2262,10 +2246,10 @@ public: ASMJIT_INST_3x(vblendmq, Vblendmq, Vec, Vec, Mem) // AVX512_F{kz|b64} ASMJIT_INST_3x(vblendmw, Vblendmw, Vec, Vec, Vec) // AVX512_BW{kz} ASMJIT_INST_3x(vblendmw, Vblendmw, Vec, Vec, Mem) // AVX512_BW{kz} - ASMJIT_INST_4i(vblendpd, Vblendpd, Vec, Vec, Vec, Imm) // AVX - ASMJIT_INST_4i(vblendpd, Vblendpd, Vec, Vec, Mem, Imm) // AVX - ASMJIT_INST_4i(vblendps, Vblendps, Vec, Vec, Vec, Imm) // AVX - ASMJIT_INST_4i(vblendps, Vblendps, Vec, Vec, Mem, Imm) // AVX + ASMJIT_INST_4x(vblendpd, Vblendpd, Vec, Vec, Vec, Imm) // AVX + ASMJIT_INST_4x(vblendpd, Vblendpd, Vec, Vec, Mem, Imm) // AVX + ASMJIT_INST_4x(vblendps, Vblendps, Vec, Vec, Vec, Imm) // AVX + ASMJIT_INST_4x(vblendps, Vblendps, Vec, Vec, Mem, Imm) // AVX ASMJIT_INST_4x(vblendvpd, Vblendvpd, Vec, Vec, Vec, Vec) // AVX ASMJIT_INST_4x(vblendvpd, Vblendvpd, Vec, Vec, Mem, Vec) // AVX ASMJIT_INST_4x(vblendvps, Vblendvps, Vec, Vec, Vec, Vec) // AVX @@ -2290,22 +2274,22 @@ public: ASMJIT_INST_2x(vbroadcastsd, Vbroadcastsd, Vec, Xmm) // AVX2 AVX512_F{kz} ASMJIT_INST_2x(vbroadcastss, Vbroadcastss, Vec, Mem) // AVX AVX512_F{kz} ASMJIT_INST_2x(vbroadcastss, Vbroadcastss, Vec, Xmm) // AVX2 AVX512_F{kz} - ASMJIT_INST_4i(vcmppd, Vcmppd, Vec, Vec, Vec, Imm) // AVX - ASMJIT_INST_4i(vcmppd, Vcmppd, Vec, Vec, Mem, Imm) // AVX - ASMJIT_INST_4i(vcmppd, Vcmppd, KReg, Vec, Vec, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_4i(vcmppd, Vcmppd, KReg, Vec, Mem, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_4i(vcmpps, Vcmpps, Vec, Vec, Vec, Imm) // AVX - ASMJIT_INST_4i(vcmpps, Vcmpps, Vec, Vec, Mem, Imm) // AVX - ASMJIT_INST_4i(vcmpps, Vcmpps, KReg, Vec, Vec, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vcmpps, Vcmpps, KReg, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vcmpsd, Vcmpsd, Xmm, Xmm, Xmm, Imm) // AVX - ASMJIT_INST_4i(vcmpsd, Vcmpsd, Xmm, Xmm, Mem, Imm) // AVX - ASMJIT_INST_4i(vcmpsd, Vcmpsd, KReg, Xmm, Xmm, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vcmpsd, Vcmpsd, KReg, Xmm, Mem, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vcmpss, Vcmpss, Xmm, Xmm, Xmm, Imm) // AVX - ASMJIT_INST_4i(vcmpss, Vcmpss, Xmm, Xmm, Mem, Imm) // AVX - ASMJIT_INST_4i(vcmpss, Vcmpss, KReg, Xmm, Xmm, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vcmpss, Vcmpss, KReg, Xmm, Mem, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vcmppd, Vcmppd, Vec, Vec, Vec, Imm) // AVX + ASMJIT_INST_4x(vcmppd, Vcmppd, Vec, Vec, Mem, Imm) // AVX + ASMJIT_INST_4x(vcmppd, Vcmppd, KReg, Vec, Vec, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_4x(vcmppd, Vcmppd, KReg, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_4x(vcmpps, Vcmpps, Vec, Vec, Vec, Imm) // AVX + ASMJIT_INST_4x(vcmpps, Vcmpps, Vec, Vec, Mem, Imm) // AVX + ASMJIT_INST_4x(vcmpps, Vcmpps, KReg, Vec, Vec, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vcmpps, Vcmpps, KReg, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vcmpsd, Vcmpsd, Xmm, Xmm, Xmm, Imm) // AVX + ASMJIT_INST_4x(vcmpsd, Vcmpsd, Xmm, Xmm, Mem, Imm) // AVX + ASMJIT_INST_4x(vcmpsd, Vcmpsd, KReg, Xmm, Xmm, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vcmpsd, Vcmpsd, KReg, Xmm, Mem, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vcmpss, Vcmpss, Xmm, Xmm, Xmm, Imm) // AVX + ASMJIT_INST_4x(vcmpss, Vcmpss, Xmm, Xmm, Mem, Imm) // AVX + ASMJIT_INST_4x(vcmpss, Vcmpss, KReg, Xmm, Xmm, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vcmpss, Vcmpss, KReg, Xmm, Mem, Imm) // AVX512_F{kz|sae} ASMJIT_INST_2x(vcomisd, Vcomisd, Xmm, Xmm) // AVX AVX512_F{sae} ASMJIT_INST_2x(vcomisd, Vcomisd, Xmm, Mem) // AVX AVX512_F{sae} ASMJIT_INST_2x(vcomiss, Vcomiss, Xmm, Xmm) // AVX AVX512_F{sae} @@ -2338,8 +2322,8 @@ public: ASMJIT_INST_2x(vcvtps2dq, Vcvtps2dq, Vec, Mem) // AVX AVX512_F{kz|b32} ASMJIT_INST_2x(vcvtps2pd, Vcvtps2pd, Vec, Vec) // AVX AVX512_F{kz|b32} ASMJIT_INST_2x(vcvtps2pd, Vcvtps2pd, Vec, Mem) // AVX AVX512_F{kz|b32} - ASMJIT_INST_3i(vcvtps2ph, Vcvtps2ph, Vec, Vec, Imm) // F16C AVX512_F{kz} - ASMJIT_INST_3i(vcvtps2ph, Vcvtps2ph, Mem, Vec, Imm) // F16C AVX512_F{kz} + ASMJIT_INST_3x(vcvtps2ph, Vcvtps2ph, Vec, Vec, Imm) // F16C AVX512_F{kz} + ASMJIT_INST_3x(vcvtps2ph, Vcvtps2ph, Mem, Vec, Imm) // F16C AVX512_F{kz} ASMJIT_INST_2x(vcvtps2qq, Vcvtps2qq, Vec, Vec) // AVX512_DQ{kz|b32} ASMJIT_INST_2x(vcvtps2qq, Vcvtps2qq, Vec, Mem) // AVX512_DQ{kz|b32} ASMJIT_INST_2x(vcvtps2udq, Vcvtps2udq, Vec, Vec) // AVX512_F{kz|b32} @@ -2402,8 +2386,8 @@ public: ASMJIT_INST_3x(vcvtusi2sd, Vcvtusi2sd, Xmm, Xmm, Mem) // AVX512_F{er} ASMJIT_INST_3x(vcvtusi2ss, Vcvtusi2ss, Xmm, Xmm, Gp) // AVX512_F{er} ASMJIT_INST_3x(vcvtusi2ss, Vcvtusi2ss, Xmm, Xmm, Mem) // AVX512_F{er} - ASMJIT_INST_4i(vdbpsadbw, Vdbpsadbw, Vec, Vec, Vec, Imm) // AVX512_BW{kz} - ASMJIT_INST_4i(vdbpsadbw, Vdbpsadbw, Vec, Vec, Mem, Imm) // AVX512_BW{kz} + ASMJIT_INST_4x(vdbpsadbw, Vdbpsadbw, Vec, Vec, Vec, Imm) // AVX512_BW{kz} + ASMJIT_INST_4x(vdbpsadbw, Vdbpsadbw, Vec, Vec, Mem, Imm) // AVX512_BW{kz} ASMJIT_INST_3x(vdivpd, Vdivpd, Vec, Vec, Vec) // AVX AVX512_F{kz|b64} ASMJIT_INST_3x(vdivpd, Vdivpd, Vec, Vec, Mem) // AVX AVX512_F{kz|b64} ASMJIT_INST_3x(vdivps, Vdivps, Vec, Vec, Vec) // AVX AVX512_F{kz|b32} @@ -2414,10 +2398,10 @@ public: ASMJIT_INST_3x(vdivss, Vdivss, Xmm, Xmm, Mem) // AVX AVX512_F{kz|er} ASMJIT_INST_3x(vdpbf16ps, Vdpbf16ps, Vec, Vec, Vec) // AVX512_BF16{kz|b32} ASMJIT_INST_3x(vdpbf16ps, Vdpbf16ps, Vec, Vec, Mem) // AVX512_BF16{kz|b32} - ASMJIT_INST_4i(vdppd, Vdppd, Vec, Vec, Vec, Imm) // AVX - ASMJIT_INST_4i(vdppd, Vdppd, Vec, Vec, Mem, Imm) // AVX - ASMJIT_INST_4i(vdpps, Vdpps, Vec, Vec, Vec, Imm) // AVX - ASMJIT_INST_4i(vdpps, Vdpps, Vec, Vec, Mem, Imm) // AVX + ASMJIT_INST_4x(vdppd, Vdppd, Vec, Vec, Vec, Imm) // AVX + ASMJIT_INST_4x(vdppd, Vdppd, Vec, Vec, Mem, Imm) // AVX + ASMJIT_INST_4x(vdpps, Vdpps, Vec, Vec, Vec, Imm) // AVX + ASMJIT_INST_4x(vdpps, Vdpps, Vec, Vec, Mem, Imm) // AVX ASMJIT_INST_2x(vexp2pd, Vexp2pd, Vec, Vec) // AVX512_ER{kz|sae|b64} ASMJIT_INST_2x(vexp2pd, Vexp2pd, Vec, Mem) // AVX512_ER{kz|sae|b64} ASMJIT_INST_2x(vexp2ps, Vexp2ps, Vec, Vec) // AVX512_ER{kz|sae|b32} @@ -2426,36 +2410,36 @@ public: ASMJIT_INST_2x(vexpandpd, Vexpandpd, Vec, Mem) // AVX512_F{kz} ASMJIT_INST_2x(vexpandps, Vexpandps, Vec, Vec) // AVX512_F{kz} ASMJIT_INST_2x(vexpandps, Vexpandps, Vec, Mem) // AVX512_F{kz} - ASMJIT_INST_3i(vextractf128, Vextractf128, Vec, Vec, Imm) // AVX - ASMJIT_INST_3i(vextractf128, Vextractf128, Mem, Vec, Imm) // AVX - ASMJIT_INST_3i(vextractf32x4, Vextractf32x4, Vec, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_3i(vextractf32x4, Vextractf32x4, Mem, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_3i(vextractf32x8, Vextractf32x8, Vec, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_3i(vextractf32x8, Vextractf32x8, Mem, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_3i(vextractf64x2, Vextractf64x2, Vec, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_3i(vextractf64x2, Vextractf64x2, Mem, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_3i(vextractf64x4, Vextractf64x4, Vec, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_3i(vextractf64x4, Vextractf64x4, Mem, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_3i(vextracti128, Vextracti128, Vec, Vec, Imm) // AVX2 - ASMJIT_INST_3i(vextracti128, Vextracti128, Mem, Vec, Imm) // AVX2 - ASMJIT_INST_3i(vextracti32x4, Vextracti32x4, Vec, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_3i(vextracti32x4, Vextracti32x4, Mem, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_3i(vextracti32x8, Vextracti32x8, Vec, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_3i(vextracti32x8, Vextracti32x8, Mem, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_3i(vextracti64x2, Vextracti64x2, Vec, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_3i(vextracti64x2, Vextracti64x2, Mem, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_3i(vextracti64x4, Vextracti64x4, Vec, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_3i(vextracti64x4, Vextracti64x4, Mem, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_3i(vextractps, Vextractps, Gp, Xmm, Imm) // AVX AVX512_F - ASMJIT_INST_3i(vextractps, Vextractps, Mem, Xmm, Imm) // AVX AVX512_F - ASMJIT_INST_4i(vfixupimmpd, Vfixupimmpd, Vec, Vec, Vec, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_4i(vfixupimmpd, Vfixupimmpd, Vec, Vec, Mem, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_4i(vfixupimmps, Vfixupimmps, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vfixupimmps, Vfixupimmps, Vec, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vfixupimmsd, Vfixupimmsd, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vfixupimmsd, Vfixupimmsd, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vfixupimmss, Vfixupimmss, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vfixupimmss, Vfixupimmss, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_3x(vextractf128, Vextractf128, Vec, Vec, Imm) // AVX + ASMJIT_INST_3x(vextractf128, Vextractf128, Mem, Vec, Imm) // AVX + ASMJIT_INST_3x(vextractf32x4, Vextractf32x4, Vec, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_3x(vextractf32x4, Vextractf32x4, Mem, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_3x(vextractf32x8, Vextractf32x8, Vec, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_3x(vextractf32x8, Vextractf32x8, Mem, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_3x(vextractf64x2, Vextractf64x2, Vec, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_3x(vextractf64x2, Vextractf64x2, Mem, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_3x(vextractf64x4, Vextractf64x4, Vec, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_3x(vextractf64x4, Vextractf64x4, Mem, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_3x(vextracti128, Vextracti128, Vec, Vec, Imm) // AVX2 + ASMJIT_INST_3x(vextracti128, Vextracti128, Mem, Vec, Imm) // AVX2 + ASMJIT_INST_3x(vextracti32x4, Vextracti32x4, Vec, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_3x(vextracti32x4, Vextracti32x4, Mem, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_3x(vextracti32x8, Vextracti32x8, Vec, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_3x(vextracti32x8, Vextracti32x8, Mem, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_3x(vextracti64x2, Vextracti64x2, Vec, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_3x(vextracti64x2, Vextracti64x2, Mem, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_3x(vextracti64x4, Vextracti64x4, Vec, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_3x(vextracti64x4, Vextracti64x4, Mem, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_3x(vextractps, Vextractps, Gp, Xmm, Imm) // AVX AVX512_F + ASMJIT_INST_3x(vextractps, Vextractps, Mem, Xmm, Imm) // AVX AVX512_F + ASMJIT_INST_4x(vfixupimmpd, Vfixupimmpd, Vec, Vec, Vec, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_4x(vfixupimmpd, Vfixupimmpd, Vec, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_4x(vfixupimmps, Vfixupimmps, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vfixupimmps, Vfixupimmps, Vec, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vfixupimmsd, Vfixupimmsd, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vfixupimmsd, Vfixupimmsd, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vfixupimmss, Vfixupimmss, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vfixupimmss, Vfixupimmss, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} ASMJIT_INST_3x(vfmadd132pd, Vfmadd132pd, Vec, Vec, Vec) // FMA AVX512_F{kz|b64} ASMJIT_INST_3x(vfmadd132pd, Vfmadd132pd, Vec, Vec, Mem) // FMA AVX512_F{kz|b64} ASMJIT_INST_3x(vfmadd132ps, Vfmadd132ps, Vec, Vec, Vec) // FMA AVX512_F{kz|b32} @@ -2576,14 +2560,14 @@ public: ASMJIT_INST_3x(vfnmsub231sd, Vfnmsub231sd, Xmm, Xmm, Mem) // FMA AVX512_F{kz|er} ASMJIT_INST_3x(vfnmsub231ss, Vfnmsub231ss, Xmm, Xmm, Xmm) // FMA AVX512_F{kz|er} ASMJIT_INST_3x(vfnmsub231ss, Vfnmsub231ss, Xmm, Xmm, Mem) // FMA AVX512_F{kz|er} - ASMJIT_INST_3i(vfpclasspd, Vfpclasspd, KReg, Vec, Imm) // AVX512_DQ{k|b64} - ASMJIT_INST_3i(vfpclasspd, Vfpclasspd, KReg, Mem, Imm) // AVX512_DQ{k|b64} - ASMJIT_INST_3i(vfpclassps, Vfpclassps, KReg, Vec, Imm) // AVX512_DQ{k|b32} - ASMJIT_INST_3i(vfpclassps, Vfpclassps, KReg, Mem, Imm) // AVX512_DQ{k|b32} - ASMJIT_INST_3i(vfpclasssd, Vfpclasssd, KReg, Xmm, Imm) // AVX512_DQ{k} - ASMJIT_INST_3i(vfpclasssd, Vfpclasssd, KReg, Mem, Imm) // AVX512_DQ{k} - ASMJIT_INST_3i(vfpclassss, Vfpclassss, KReg, Xmm, Imm) // AVX512_DQ{k} - ASMJIT_INST_3i(vfpclassss, Vfpclassss, KReg, Mem, Imm) // AVX512_DQ{k} + ASMJIT_INST_3x(vfpclasspd, Vfpclasspd, KReg, Vec, Imm) // AVX512_DQ{k|b64} + ASMJIT_INST_3x(vfpclasspd, Vfpclasspd, KReg, Mem, Imm) // AVX512_DQ{k|b64} + ASMJIT_INST_3x(vfpclassps, Vfpclassps, KReg, Vec, Imm) // AVX512_DQ{k|b32} + ASMJIT_INST_3x(vfpclassps, Vfpclassps, KReg, Mem, Imm) // AVX512_DQ{k|b32} + ASMJIT_INST_3x(vfpclasssd, Vfpclasssd, KReg, Xmm, Imm) // AVX512_DQ{k} + ASMJIT_INST_3x(vfpclasssd, Vfpclasssd, KReg, Mem, Imm) // AVX512_DQ{k} + ASMJIT_INST_3x(vfpclassss, Vfpclassss, KReg, Xmm, Imm) // AVX512_DQ{k} + ASMJIT_INST_3x(vfpclassss, Vfpclassss, KReg, Mem, Imm) // AVX512_DQ{k} ASMJIT_INST_2x(vgatherdpd, Vgatherdpd, Vec, Mem) // AVX512_F{k} ASMJIT_INST_3x(vgatherdpd, Vgatherdpd, Vec, Mem, Vec) // AVX2 ASMJIT_INST_2x(vgatherdps, Vgatherdps, Vec, Mem) // AVX512_F{k} @@ -2608,18 +2592,18 @@ public: ASMJIT_INST_3x(vgetexpsd, Vgetexpsd, Xmm, Xmm, Mem) // AVX512_F{kz|sae} ASMJIT_INST_3x(vgetexpss, Vgetexpss, Xmm, Xmm, Xmm) // AVX512_F{kz|sae} ASMJIT_INST_3x(vgetexpss, Vgetexpss, Xmm, Xmm, Mem) // AVX512_F{kz|sae} - ASMJIT_INST_3i(vgetmantpd, Vgetmantpd, Vec, Vec, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_3i(vgetmantpd, Vgetmantpd, Vec, Mem, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_3i(vgetmantps, Vgetmantps, Vec, Vec, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_3i(vgetmantps, Vgetmantps, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vgetmantsd, Vgetmantsd, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vgetmantsd, Vgetmantsd, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vgetmantss, Vgetmantss, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vgetmantss, Vgetmantss, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vgf2p8affineinvqb, Vgf2p8affineinvqb,Vec,Vec,Vec,Imm) // AVX AVX512_VL{kz} GFNI - ASMJIT_INST_4i(vgf2p8affineinvqb, Vgf2p8affineinvqb,Vec,Vec,Mem,Imm) // AVX AVX512_VL{kz} GFNI - ASMJIT_INST_4i(vgf2p8affineqb, Vgf2p8affineqb, Vec, Vec, Vec, Imm) // AVX AVX512_VL{kz} GFNI - ASMJIT_INST_4i(vgf2p8affineqb, Vgf2p8affineqb, Vec, Vec, Mem, Imm) // AVX AVX512_VL{kz} GFNI + ASMJIT_INST_3x(vgetmantpd, Vgetmantpd, Vec, Vec, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vgetmantpd, Vgetmantpd, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vgetmantps, Vgetmantps, Vec, Vec, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_3x(vgetmantps, Vgetmantps, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vgetmantsd, Vgetmantsd, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vgetmantsd, Vgetmantsd, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vgetmantss, Vgetmantss, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vgetmantss, Vgetmantss, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vgf2p8affineinvqb, Vgf2p8affineinvqb,Vec,Vec,Vec,Imm) // AVX AVX512_VL{kz} GFNI + ASMJIT_INST_4x(vgf2p8affineinvqb, Vgf2p8affineinvqb,Vec,Vec,Mem,Imm) // AVX AVX512_VL{kz} GFNI + ASMJIT_INST_4x(vgf2p8affineqb, Vgf2p8affineqb, Vec, Vec, Vec, Imm) // AVX AVX512_VL{kz} GFNI + ASMJIT_INST_4x(vgf2p8affineqb, Vgf2p8affineqb, Vec, Vec, Mem, Imm) // AVX AVX512_VL{kz} GFNI ASMJIT_INST_3x(vgf2p8mulb, Vgf2p8mulb, Vec, Vec, Vec) // AVX AVX512_VL{kz} GFNI ASMJIT_INST_3x(vgf2p8mulb, Vgf2p8mulb, Vec, Vec, Mem) // AVX AVX512_VL{kz} GFNI ASMJIT_INST_3x(vhaddpd, Vhaddpd, Vec, Vec, Vec) // AVX @@ -2630,28 +2614,28 @@ public: ASMJIT_INST_3x(vhsubpd, Vhsubpd, Vec, Vec, Mem) // AVX ASMJIT_INST_3x(vhsubps, Vhsubps, Vec, Vec, Vec) // AVX ASMJIT_INST_3x(vhsubps, Vhsubps, Vec, Vec, Mem) // AVX - ASMJIT_INST_4i(vinsertf128, Vinsertf128, Vec, Vec, Vec, Imm) // AVX - ASMJIT_INST_4i(vinsertf128, Vinsertf128, Vec, Vec, Mem, Imm) // AVX - ASMJIT_INST_4i(vinsertf32x4, Vinsertf32x4, Vec, Vec, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_4i(vinsertf32x4, Vinsertf32x4, Vec, Vec, Mem, Imm) // AVX512_F{kz} - ASMJIT_INST_4i(vinsertf32x8, Vinsertf32x8, Vec, Vec, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_4i(vinsertf32x8, Vinsertf32x8, Vec, Vec, Mem, Imm) // AVX512_DQ{kz} - ASMJIT_INST_4i(vinsertf64x2, Vinsertf64x2, Vec, Vec, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_4i(vinsertf64x2, Vinsertf64x2, Vec, Vec, Mem, Imm) // AVX512_DQ{kz} - ASMJIT_INST_4i(vinsertf64x4, Vinsertf64x4, Vec, Vec, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_4i(vinsertf64x4, Vinsertf64x4, Vec, Vec, Mem, Imm) // AVX512_F{kz} - ASMJIT_INST_4i(vinserti128, Vinserti128, Vec, Vec, Vec, Imm) // AVX2 - ASMJIT_INST_4i(vinserti128, Vinserti128, Vec, Vec, Mem, Imm) // AVX2 - ASMJIT_INST_4i(vinserti32x4, Vinserti32x4, Vec, Vec, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_4i(vinserti32x4, Vinserti32x4, Vec, Vec, Mem, Imm) // AVX512_F{kz} - ASMJIT_INST_4i(vinserti32x8, Vinserti32x8, Vec, Vec, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_4i(vinserti32x8, Vinserti32x8, Vec, Vec, Mem, Imm) // AVX512_DQ{kz} - ASMJIT_INST_4i(vinserti64x2, Vinserti64x2, Vec, Vec, Vec, Imm) // AVX512_DQ{kz} - ASMJIT_INST_4i(vinserti64x2, Vinserti64x2, Vec, Vec, Mem, Imm) // AVX512_DQ{kz} - ASMJIT_INST_4i(vinserti64x4, Vinserti64x4, Vec, Vec, Vec, Imm) // AVX512_F{kz} - ASMJIT_INST_4i(vinserti64x4, Vinserti64x4, Vec, Vec, Mem, Imm) // AVX512_F{kz} - ASMJIT_INST_4i(vinsertps, Vinsertps, Xmm, Xmm, Xmm, Imm) // AVX AVX512_F - ASMJIT_INST_4i(vinsertps, Vinsertps, Xmm, Xmm, Mem, Imm) // AVX AVX512_F + ASMJIT_INST_4x(vinsertf128, Vinsertf128, Vec, Vec, Vec, Imm) // AVX + ASMJIT_INST_4x(vinsertf128, Vinsertf128, Vec, Vec, Mem, Imm) // AVX + ASMJIT_INST_4x(vinsertf32x4, Vinsertf32x4, Vec, Vec, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_4x(vinsertf32x4, Vinsertf32x4, Vec, Vec, Mem, Imm) // AVX512_F{kz} + ASMJIT_INST_4x(vinsertf32x8, Vinsertf32x8, Vec, Vec, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_4x(vinsertf32x8, Vinsertf32x8, Vec, Vec, Mem, Imm) // AVX512_DQ{kz} + ASMJIT_INST_4x(vinsertf64x2, Vinsertf64x2, Vec, Vec, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_4x(vinsertf64x2, Vinsertf64x2, Vec, Vec, Mem, Imm) // AVX512_DQ{kz} + ASMJIT_INST_4x(vinsertf64x4, Vinsertf64x4, Vec, Vec, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_4x(vinsertf64x4, Vinsertf64x4, Vec, Vec, Mem, Imm) // AVX512_F{kz} + ASMJIT_INST_4x(vinserti128, Vinserti128, Vec, Vec, Vec, Imm) // AVX2 + ASMJIT_INST_4x(vinserti128, Vinserti128, Vec, Vec, Mem, Imm) // AVX2 + ASMJIT_INST_4x(vinserti32x4, Vinserti32x4, Vec, Vec, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_4x(vinserti32x4, Vinserti32x4, Vec, Vec, Mem, Imm) // AVX512_F{kz} + ASMJIT_INST_4x(vinserti32x8, Vinserti32x8, Vec, Vec, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_4x(vinserti32x8, Vinserti32x8, Vec, Vec, Mem, Imm) // AVX512_DQ{kz} + ASMJIT_INST_4x(vinserti64x2, Vinserti64x2, Vec, Vec, Vec, Imm) // AVX512_DQ{kz} + ASMJIT_INST_4x(vinserti64x2, Vinserti64x2, Vec, Vec, Mem, Imm) // AVX512_DQ{kz} + ASMJIT_INST_4x(vinserti64x4, Vinserti64x4, Vec, Vec, Vec, Imm) // AVX512_F{kz} + ASMJIT_INST_4x(vinserti64x4, Vinserti64x4, Vec, Vec, Mem, Imm) // AVX512_F{kz} + ASMJIT_INST_4x(vinsertps, Vinsertps, Xmm, Xmm, Xmm, Imm) // AVX AVX512_F + ASMJIT_INST_4x(vinsertps, Vinsertps, Xmm, Xmm, Mem, Imm) // AVX AVX512_F ASMJIT_INST_2x(vlddqu, Vlddqu, Vec, Mem) // AVX ASMJIT_INST_1x(vldmxcsr, Vldmxcsr, Mem) // AVX ASMJIT_INST_3x(vmaskmovdqu, Vmaskmovdqu, Vec, Vec, DS_ZDI) // AVX [EXPLICIT] @@ -2748,8 +2732,8 @@ public: ASMJIT_INST_2x(vmovups, Vmovups, Vec, Vec) // AVX AVX512_F{kz} ASMJIT_INST_2x(vmovups, Vmovups, Vec, Mem) // AVX AVX512_F{kz} ASMJIT_INST_2x(vmovups, Vmovups, Mem, Vec) // AVX AVX512_F{kz} - ASMJIT_INST_4i(vmpsadbw, Vmpsadbw, Vec, Vec, Vec, Imm) // AVX+ - ASMJIT_INST_4i(vmpsadbw, Vmpsadbw, Vec, Vec, Mem, Imm) // AVX+ + ASMJIT_INST_4x(vmpsadbw, Vmpsadbw, Vec, Vec, Vec, Imm) // AVX+ + ASMJIT_INST_4x(vmpsadbw, Vmpsadbw, Vec, Vec, Mem, Imm) // AVX+ ASMJIT_INST_3x(vmulpd, Vmulpd, Vec, Vec, Vec) // AVX AVX512_F{kz|b64} ASMJIT_INST_3x(vmulpd, Vmulpd, Vec, Vec, Mem) // AVX AVX512_F{kz|b64} ASMJIT_INST_3x(vmulps, Vmulps, Vec, Vec, Vec) // AVX AVX512_F{kz|b32} @@ -2800,8 +2784,8 @@ public: ASMJIT_INST_3x(vpaddusw, Vpaddusw, Vec, Vec, Mem) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpaddw, Vpaddw, Vec, Vec, Vec) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpaddw, Vpaddw, Vec, Vec, Mem) // AVX+ AVX512_BW{kz} - ASMJIT_INST_4i(vpalignr, Vpalignr, Vec, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} - ASMJIT_INST_4i(vpalignr, Vpalignr, Vec, Vec, Mem, Imm) // AVX+ AVX512_BW{kz} + ASMJIT_INST_4x(vpalignr, Vpalignr, Vec, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} + ASMJIT_INST_4x(vpalignr, Vpalignr, Vec, Vec, Mem, Imm) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpand, Vpand, Vec, Vec, Vec) // AVX+ ASMJIT_INST_3x(vpand, Vpand, Vec, Vec, Mem) // AVX+ ASMJIT_INST_3x(vpandd, Vpandd, Vec, Vec, Vec) // AVX512_F{kz|b32} @@ -2818,12 +2802,12 @@ public: ASMJIT_INST_3x(vpavgb, Vpavgb, Vec, Vec, Mem) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpavgw, Vpavgw, Vec, Vec, Vec) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpavgw, Vpavgw, Vec, Vec, Mem) // AVX+ AVX512_BW{kz} - ASMJIT_INST_4i(vpblendd, Vpblendd, Vec, Vec, Vec, Imm) // AVX2 - ASMJIT_INST_4i(vpblendd, Vpblendd, Vec, Vec, Mem, Imm) // AVX2 + ASMJIT_INST_4x(vpblendd, Vpblendd, Vec, Vec, Vec, Imm) // AVX2 + ASMJIT_INST_4x(vpblendd, Vpblendd, Vec, Vec, Mem, Imm) // AVX2 ASMJIT_INST_4x(vpblendvb, Vpblendvb, Vec, Vec, Vec, Vec) // AVX+ ASMJIT_INST_4x(vpblendvb, Vpblendvb, Vec, Vec, Mem, Vec) // AVX+ - ASMJIT_INST_4i(vpblendw, Vpblendw, Vec, Vec, Vec, Imm) // AVX+ - ASMJIT_INST_4i(vpblendw, Vpblendw, Vec, Vec, Mem, Imm) // AVX+ + ASMJIT_INST_4x(vpblendw, Vpblendw, Vec, Vec, Vec, Imm) // AVX+ + ASMJIT_INST_4x(vpblendw, Vpblendw, Vec, Vec, Mem, Imm) // AVX+ ASMJIT_INST_2x(vpbroadcastb, Vpbroadcastb, Vec, Vec) // AVX2 AVX512_BW{kz} ASMJIT_INST_2x(vpbroadcastb, Vpbroadcastb, Vec, Mem) // AVX2 AVX512_BW{kz} ASMJIT_INST_2x(vpbroadcastb, Vpbroadcastb, Vec, Gp) // AVX512_BW{kz} @@ -2838,12 +2822,12 @@ public: ASMJIT_INST_2x(vpbroadcastw, Vpbroadcastw, Vec, Vec) // AVX2 AVX512_BW{kz} ASMJIT_INST_2x(vpbroadcastw, Vpbroadcastw, Vec, Mem) // AVX2 AVX512_BW{kz} ASMJIT_INST_2x(vpbroadcastw, Vpbroadcastw, Vec, Gp) // AVX512_BW{kz} - ASMJIT_INST_4i(vpclmulqdq, Vpclmulqdq, Vec, Vec, Vec, Imm) // AVX VPCLMULQDQ AVX512_F - ASMJIT_INST_4i(vpclmulqdq, Vpclmulqdq, Vec, Vec, Mem, Imm) // AVX VPCLMULQDQ AVX512_F - ASMJIT_INST_4i(vpcmpb, Vpcmpb, KReg, Vec, Vec, Imm) // AVX512_BW{k} - ASMJIT_INST_4i(vpcmpb, Vpcmpb, KReg, Vec, Mem, Imm) // AVX512_BW{k} - ASMJIT_INST_4i(vpcmpd, Vpcmpd, KReg, Vec, Vec, Imm) // AVX512_F{k|b32} - ASMJIT_INST_4i(vpcmpd, Vpcmpd, KReg, Vec, Mem, Imm) // AVX512_F{k|b32} + ASMJIT_INST_4x(vpclmulqdq, Vpclmulqdq, Vec, Vec, Vec, Imm) // AVX VPCLMULQDQ AVX512_F + ASMJIT_INST_4x(vpclmulqdq, Vpclmulqdq, Vec, Vec, Mem, Imm) // AVX VPCLMULQDQ AVX512_F + ASMJIT_INST_4x(vpcmpb, Vpcmpb, KReg, Vec, Vec, Imm) // AVX512_BW{k} + ASMJIT_INST_4x(vpcmpb, Vpcmpb, KReg, Vec, Mem, Imm) // AVX512_BW{k} + ASMJIT_INST_4x(vpcmpd, Vpcmpd, KReg, Vec, Vec, Imm) // AVX512_F{k|b32} + ASMJIT_INST_4x(vpcmpd, Vpcmpd, KReg, Vec, Mem, Imm) // AVX512_F{k|b32} ASMJIT_INST_3x(vpcmpeqb, Vpcmpeqb, Vec, Vec, Vec) // AVX+ ASMJIT_INST_3x(vpcmpeqb, Vpcmpeqb, Vec, Vec, Mem) // AVX+ ASMJIT_INST_3x(vpcmpeqb, Vpcmpeqb, KReg, Vec, Vec) // AVX512_BW{k} @@ -2884,18 +2868,18 @@ public: ASMJIT_INST_4x(vpcmpistri, Vpcmpistri, Vec, Mem, Imm, Gp_ECX) // AVX [EXPLICIT] ASMJIT_INST_4x(vpcmpistrm, Vpcmpistrm, Vec, Vec, Imm, XMM0) // AVX [EXPLICIT] ASMJIT_INST_4x(vpcmpistrm, Vpcmpistrm, Vec, Mem, Imm, XMM0) // AVX [EXPLICIT] - ASMJIT_INST_4i(vpcmpq, Vpcmpq, KReg, Vec, Vec, Imm) // AVX512_F{k|b64} - ASMJIT_INST_4i(vpcmpq, Vpcmpq, KReg, Vec, Mem, Imm) // AVX512_F{k|b64} - ASMJIT_INST_4i(vpcmpub, Vpcmpub, KReg, Vec, Vec, Imm) // AVX512_BW{k} - ASMJIT_INST_4i(vpcmpub, Vpcmpub, KReg, Vec, Mem, Imm) // AVX512_BW{k} - ASMJIT_INST_4i(vpcmpud, Vpcmpud, KReg, Vec, Vec, Imm) // AVX512_F{k|b32} - ASMJIT_INST_4i(vpcmpud, Vpcmpud, KReg, Vec, Mem, Imm) // AVX512_F{k|b32} - ASMJIT_INST_4i(vpcmpuq, Vpcmpuq, KReg, Vec, Vec, Imm) // AVX512_F{k|b64} - ASMJIT_INST_4i(vpcmpuq, Vpcmpuq, KReg, Vec, Mem, Imm) // AVX512_F{k|b64} - ASMJIT_INST_4i(vpcmpuw, Vpcmpuw, KReg, Vec, Vec, Imm) // AVX512_BW{k|b64} - ASMJIT_INST_4i(vpcmpuw, Vpcmpuw, KReg, Vec, Mem, Imm) // AVX512_BW{k|b64} - ASMJIT_INST_4i(vpcmpw, Vpcmpw, KReg, Vec, Vec, Imm) // AVX512_BW{k|b64} - ASMJIT_INST_4i(vpcmpw, Vpcmpw, KReg, Vec, Mem, Imm) // AVX512_BW{k|b64} + ASMJIT_INST_4x(vpcmpq, Vpcmpq, KReg, Vec, Vec, Imm) // AVX512_F{k|b64} + ASMJIT_INST_4x(vpcmpq, Vpcmpq, KReg, Vec, Mem, Imm) // AVX512_F{k|b64} + ASMJIT_INST_4x(vpcmpub, Vpcmpub, KReg, Vec, Vec, Imm) // AVX512_BW{k} + ASMJIT_INST_4x(vpcmpub, Vpcmpub, KReg, Vec, Mem, Imm) // AVX512_BW{k} + ASMJIT_INST_4x(vpcmpud, Vpcmpud, KReg, Vec, Vec, Imm) // AVX512_F{k|b32} + ASMJIT_INST_4x(vpcmpud, Vpcmpud, KReg, Vec, Mem, Imm) // AVX512_F{k|b32} + ASMJIT_INST_4x(vpcmpuq, Vpcmpuq, KReg, Vec, Vec, Imm) // AVX512_F{k|b64} + ASMJIT_INST_4x(vpcmpuq, Vpcmpuq, KReg, Vec, Mem, Imm) // AVX512_F{k|b64} + ASMJIT_INST_4x(vpcmpuw, Vpcmpuw, KReg, Vec, Vec, Imm) // AVX512_BW{k|b64} + ASMJIT_INST_4x(vpcmpuw, Vpcmpuw, KReg, Vec, Mem, Imm) // AVX512_BW{k|b64} + ASMJIT_INST_4x(vpcmpw, Vpcmpw, KReg, Vec, Vec, Imm) // AVX512_BW{k|b64} + ASMJIT_INST_4x(vpcmpw, Vpcmpw, KReg, Vec, Mem, Imm) // AVX512_BW{k|b64} ASMJIT_INST_2x(vpcompressb, Vpcompressb, Vec, Vec) // AVX512_VBMI2{kz} ASMJIT_INST_2x(vpcompressb, Vpcompressb, Mem, Vec) // AVX512_VBMI2{kz} ASMJIT_INST_2x(vpcompressd, Vpcompressd, Vec, Vec) // AVX512_F{kz} @@ -2908,18 +2892,18 @@ public: ASMJIT_INST_2x(vpconflictd, Vpconflictd, Vec, Mem) // AVX512_CD{kz|b32} ASMJIT_INST_2x(vpconflictq, Vpconflictq, Vec, Vec) // AVX512_CD{kz|b32} ASMJIT_INST_2x(vpconflictq, Vpconflictq, Vec, Mem) // AVX512_CD{kz|b32} - ASMJIT_INST_3x(vpdpbusd, Vpdpbusd, Vec, Vec, Vec) // AVX512_VNNI{kz|b32} - ASMJIT_INST_3x(vpdpbusd, Vpdpbusd, Vec, Vec, Mem) // AVX512_VNNI{kz|b32} - ASMJIT_INST_3x(vpdpbusds, Vpdpbusds, Vec, Vec, Vec) // AVX512_VNNI{kz|b32} - ASMJIT_INST_3x(vpdpbusds, Vpdpbusds, Vec, Vec, Mem) // AVX512_VNNI{kz|b32} - ASMJIT_INST_3x(vpdpwssd, Vpdpwssd, Vec, Vec, Vec) // AVX512_VNNI{kz|b32} - ASMJIT_INST_3x(vpdpwssd, Vpdpwssd, Vec, Vec, Mem) // AVX512_VNNI{kz|b32} - ASMJIT_INST_3x(vpdpwssds, Vpdpwssds, Vec, Vec, Vec) // AVX512_VNNI{kz|b32} - ASMJIT_INST_3x(vpdpwssds, Vpdpwssds, Vec, Vec, Mem) // AVX512_VNNI{kz|b32} - ASMJIT_INST_4i(vperm2f128, Vperm2f128, Vec, Vec, Vec, Imm) // AVX - ASMJIT_INST_4i(vperm2f128, Vperm2f128, Vec, Vec, Mem, Imm) // AVX - ASMJIT_INST_4i(vperm2i128, Vperm2i128, Vec, Vec, Vec, Imm) // AVX2 - ASMJIT_INST_4i(vperm2i128, Vperm2i128, Vec, Vec, Mem, Imm) // AVX2 + ASMJIT_INST_3x(vpdpbusd, Vpdpbusd, Vec, Vec, Vec) // AVX_VNNI AVX512_VNNI{kz|b32} + ASMJIT_INST_3x(vpdpbusd, Vpdpbusd, Vec, Vec, Mem) // AVX_VNNI AVX512_VNNI{kz|b32} + ASMJIT_INST_3x(vpdpbusds, Vpdpbusds, Vec, Vec, Vec) // AVX_VNNI AVX512_VNNI{kz|b32} + ASMJIT_INST_3x(vpdpbusds, Vpdpbusds, Vec, Vec, Mem) // AVX_VNNI AVX512_VNNI{kz|b32} + ASMJIT_INST_3x(vpdpwssd, Vpdpwssd, Vec, Vec, Vec) // AVX_VNNI AVX512_VNNI{kz|b32} + ASMJIT_INST_3x(vpdpwssd, Vpdpwssd, Vec, Vec, Mem) // AVX_VNNI AVX512_VNNI{kz|b32} + ASMJIT_INST_3x(vpdpwssds, Vpdpwssds, Vec, Vec, Vec) // AVX_VNNI AVX512_VNNI{kz|b32} + ASMJIT_INST_3x(vpdpwssds, Vpdpwssds, Vec, Vec, Mem) // AVX_VNNI AVX512_VNNI{kz|b32} + ASMJIT_INST_4x(vperm2f128, Vperm2f128, Vec, Vec, Vec, Imm) // AVX + ASMJIT_INST_4x(vperm2f128, Vperm2f128, Vec, Vec, Mem, Imm) // AVX + ASMJIT_INST_4x(vperm2i128, Vperm2i128, Vec, Vec, Vec, Imm) // AVX2 + ASMJIT_INST_4x(vperm2i128, Vperm2i128, Vec, Vec, Mem, Imm) // AVX2 ASMJIT_INST_3x(vpermb, Vpermb, Vec, Vec, Vec) // AVX512_VBMI{kz} ASMJIT_INST_3x(vpermb, Vpermb, Vec, Vec, Mem) // AVX512_VBMI{kz} ASMJIT_INST_3x(vpermd, Vpermd, Vec, Vec, Vec) // AVX2 AVX512_F{kz|b32} @@ -2938,18 +2922,20 @@ public: ASMJIT_INST_3x(vpermi2w, Vpermi2w, Vec, Vec, Mem) // AVX512_BW{kz} ASMJIT_INST_3x(vpermilpd, Vpermilpd, Vec, Vec, Vec) // AVX AVX512_F{kz|b64} ASMJIT_INST_3x(vpermilpd, Vpermilpd, Vec, Vec, Mem) // AVX AVX512_F{kz|b64} - ASMJIT_INST_3i(vpermilpd, Vpermilpd, Vec, Vec, Imm) // AVX AVX512_F{kz|b64} - ASMJIT_INST_3i(vpermilpd, Vpermilpd, Vec, Mem, Imm) // AVX AVX512_F{kz|b64} + ASMJIT_INST_3x(vpermilpd, Vpermilpd, Vec, Vec, Imm) // AVX AVX512_F{kz|b64} + ASMJIT_INST_3x(vpermilpd, Vpermilpd, Vec, Mem, Imm) // AVX AVX512_F{kz|b64} ASMJIT_INST_3x(vpermilps, Vpermilps, Vec, Vec, Vec) // AVX AVX512_F{kz|b64} ASMJIT_INST_3x(vpermilps, Vpermilps, Vec, Vec, Mem) // AVX AVX512_F{kz|b64} - ASMJIT_INST_3i(vpermilps, Vpermilps, Vec, Vec, Imm) // AVX AVX512_F{kz|b64} - ASMJIT_INST_3i(vpermilps, Vpermilps, Vec, Mem, Imm) // AVX AVX512_F{kz|b64} - ASMJIT_INST_3i(vpermpd, Vpermpd, Vec, Vec, Imm) // AVX2 - ASMJIT_INST_3i(vpermpd, Vpermpd, Vec, Mem, Imm) // AVX2 - ASMJIT_INST_3x(vpermps, Vpermps, Vec, Vec, Vec) // AVX2 - ASMJIT_INST_3x(vpermps, Vpermps, Vec, Vec, Mem) // AVX2 - ASMJIT_INST_3i(vpermq, Vpermq, Vec, Vec, Imm) // AVX2 AVX512_F{kz|b64} - ASMJIT_INST_3i(vpermq, Vpermq, Vec, Mem, Imm) // AVX2 AVX512_F{kz|b64} + ASMJIT_INST_3x(vpermilps, Vpermilps, Vec, Vec, Imm) // AVX AVX512_F{kz|b64} + ASMJIT_INST_3x(vpermilps, Vpermilps, Vec, Mem, Imm) // AVX AVX512_F{kz|b64} + ASMJIT_INST_3x(vpermpd, Vpermpd, Vec, Vec, Imm) // AVX2 + ASMJIT_INST_3x(vpermpd, Vpermpd, Vec, Mem, Imm) // AVX2 + ASMJIT_INST_3x(vpermpd, Vpermpd, Vec, Vec, Vec) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vpermpd, Vpermpd, Vec, Vec, Mem) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vpermps, Vpermps, Vec, Vec, Vec) // AVX2 AVX512_F{kz|b32} + ASMJIT_INST_3x(vpermps, Vpermps, Vec, Vec, Mem) // AVX2 AVX512_F{kz|b32} + ASMJIT_INST_3x(vpermq, Vpermq, Vec, Vec, Imm) // AVX2 AVX512_F{kz|b64} + ASMJIT_INST_3x(vpermq, Vpermq, Vec, Mem, Imm) // AVX2 AVX512_F{kz|b64} ASMJIT_INST_3x(vpermq, Vpermq, Vec, Vec, Vec) // AVX512_F{kz|b64} ASMJIT_INST_3x(vpermq, Vpermq, Vec, Vec, Mem) // AVX512_F{kz|b64} ASMJIT_INST_3x(vpermt2b, Vpermt2b, Vec, Vec, Vec) // AVX512_VBMI{kz} @@ -2974,14 +2960,14 @@ public: ASMJIT_INST_2x(vpexpandq, Vpexpandq, Vec, Mem) // AVX512_F{kz} ASMJIT_INST_2x(vpexpandw, Vpexpandw, Vec, Vec) // AVX512_VBMI2{kz} ASMJIT_INST_2x(vpexpandw, Vpexpandw, Vec, Mem) // AVX512_VBMI2{kz} - ASMJIT_INST_3i(vpextrb, Vpextrb, Gp, Xmm, Imm) // AVX AVX512_BW - ASMJIT_INST_3i(vpextrb, Vpextrb, Mem, Xmm, Imm) // AVX AVX512_BW - ASMJIT_INST_3i(vpextrd, Vpextrd, Gp, Xmm, Imm) // AVX AVX512_DQ - ASMJIT_INST_3i(vpextrd, Vpextrd, Mem, Xmm, Imm) // AVX AVX512_DQ - ASMJIT_INST_3i(vpextrq, Vpextrq, Gp, Xmm, Imm) // AVX AVX512_DQ - ASMJIT_INST_3i(vpextrq, Vpextrq, Mem, Xmm, Imm) // AVX AVX512_DQ - ASMJIT_INST_3i(vpextrw, Vpextrw, Gp, Xmm, Imm) // AVX AVX512_BW - ASMJIT_INST_3i(vpextrw, Vpextrw, Mem, Xmm, Imm) // AVX AVX512_BW + ASMJIT_INST_3x(vpextrb, Vpextrb, Gp, Xmm, Imm) // AVX AVX512_BW + ASMJIT_INST_3x(vpextrb, Vpextrb, Mem, Xmm, Imm) // AVX AVX512_BW + ASMJIT_INST_3x(vpextrd, Vpextrd, Gp, Xmm, Imm) // AVX AVX512_DQ + ASMJIT_INST_3x(vpextrd, Vpextrd, Mem, Xmm, Imm) // AVX AVX512_DQ + ASMJIT_INST_3x(vpextrq, Vpextrq, Gp, Xmm, Imm) // AVX AVX512_DQ + ASMJIT_INST_3x(vpextrq, Vpextrq, Mem, Xmm, Imm) // AVX AVX512_DQ + ASMJIT_INST_3x(vpextrw, Vpextrw, Gp, Xmm, Imm) // AVX AVX512_BW + ASMJIT_INST_3x(vpextrw, Vpextrw, Mem, Xmm, Imm) // AVX AVX512_BW ASMJIT_INST_2x(vpgatherdd, Vpgatherdd, Vec, Mem) // AVX512_F{k} ASMJIT_INST_3x(vpgatherdd, Vpgatherdd, Vec, Mem, Vec) // AVX2 ASMJIT_INST_2x(vpgatherdq, Vpgatherdq, Vec, Mem) // AVX512_F{k} @@ -3004,14 +2990,14 @@ public: ASMJIT_INST_3x(vphsubsw, Vphsubsw, Vec, Vec, Mem) // AVX+ ASMJIT_INST_3x(vphsubw, Vphsubw, Vec, Vec, Vec) // AVX+ ASMJIT_INST_3x(vphsubw, Vphsubw, Vec, Vec, Mem) // AVX+ - ASMJIT_INST_4i(vpinsrb, Vpinsrb, Xmm, Xmm, Gp, Imm) // AVX AVX512_BW{kz} - ASMJIT_INST_4i(vpinsrb, Vpinsrb, Xmm, Xmm, Mem, Imm) // AVX AVX512_BW{kz} - ASMJIT_INST_4i(vpinsrd, Vpinsrd, Xmm, Xmm, Gp, Imm) // AVX AVX512_DQ{kz} - ASMJIT_INST_4i(vpinsrd, Vpinsrd, Xmm, Xmm, Mem, Imm) // AVX AVX512_DQ{kz} - ASMJIT_INST_4i(vpinsrq, Vpinsrq, Xmm, Xmm, Gp, Imm) // AVX AVX512_DQ{kz} - ASMJIT_INST_4i(vpinsrq, Vpinsrq, Xmm, Xmm, Mem, Imm) // AVX AVX512_DQ{kz} - ASMJIT_INST_4i(vpinsrw, Vpinsrw, Xmm, Xmm, Gp, Imm) // AVX AVX512_BW{kz} - ASMJIT_INST_4i(vpinsrw, Vpinsrw, Xmm, Xmm, Mem, Imm) // AVX AVX512_BW{kz} + ASMJIT_INST_4x(vpinsrb, Vpinsrb, Xmm, Xmm, Gp, Imm) // AVX AVX512_BW{kz} + ASMJIT_INST_4x(vpinsrb, Vpinsrb, Xmm, Xmm, Mem, Imm) // AVX AVX512_BW{kz} + ASMJIT_INST_4x(vpinsrd, Vpinsrd, Xmm, Xmm, Gp, Imm) // AVX AVX512_DQ{kz} + ASMJIT_INST_4x(vpinsrd, Vpinsrd, Xmm, Xmm, Mem, Imm) // AVX AVX512_DQ{kz} + ASMJIT_INST_4x(vpinsrq, Vpinsrq, Xmm, Xmm, Gp, Imm) // AVX AVX512_DQ{kz} + ASMJIT_INST_4x(vpinsrq, Vpinsrq, Xmm, Xmm, Mem, Imm) // AVX AVX512_DQ{kz} + ASMJIT_INST_4x(vpinsrw, Vpinsrw, Xmm, Xmm, Gp, Imm) // AVX AVX512_BW{kz} + ASMJIT_INST_4x(vpinsrw, Vpinsrw, Xmm, Xmm, Mem, Imm) // AVX AVX512_BW{kz} ASMJIT_INST_2x(vplzcntd, Vplzcntd, Vec, Vec) // AVX512_CD{kz|b32} ASMJIT_INST_2x(vplzcntd, Vplzcntd, Vec, Mem) // AVX512_CD{kz|b32} ASMJIT_INST_2x(vplzcntq, Vplzcntq, Vec, Vec) // AVX512_CD{kz|b64} @@ -3161,18 +3147,18 @@ public: ASMJIT_INST_3x(vpord, Vpord, Vec, Vec, Mem) // AVX512_F{kz|b32} ASMJIT_INST_3x(vporq, Vporq, Vec, Vec, Vec) // AVX512_F{kz|b64} ASMJIT_INST_3x(vporq, Vporq, Vec, Vec, Mem) // AVX512_F{kz|b64} - ASMJIT_INST_3i(vprold, Vprold, Vec, Vec, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_3i(vprold, Vprold, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_3i(vprolq, Vprolq, Vec, Vec, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_3i(vprolq, Vprolq, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vprold, Vprold, Vec, Vec, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_3x(vprold, Vprold, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_3x(vprolq, Vprolq, Vec, Vec, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vprolq, Vprolq, Vec, Mem, Imm) // AVX512_F{kz|b64} ASMJIT_INST_3x(vprolvd, Vprolvd, Vec, Vec, Vec) // AVX512_F{kz|b32} ASMJIT_INST_3x(vprolvd, Vprolvd, Vec, Vec, Mem) // AVX512_F{kz|b32} ASMJIT_INST_3x(vprolvq, Vprolvq, Vec, Vec, Vec) // AVX512_F{kz|b64} ASMJIT_INST_3x(vprolvq, Vprolvq, Vec, Vec, Mem) // AVX512_F{kz|b64} - ASMJIT_INST_3i(vprord, Vprord, Vec, Vec, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_3i(vprord, Vprord, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_3i(vprorq, Vprorq, Vec, Vec, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_3i(vprorq, Vprorq, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vprord, Vprord, Vec, Vec, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_3x(vprord, Vprord, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_3x(vprorq, Vprorq, Vec, Vec, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vprorq, Vprorq, Vec, Mem, Imm) // AVX512_F{kz|b64} ASMJIT_INST_3x(vprorvd, Vprorvd, Vec, Vec, Vec) // AVX512_F{kz|b32} ASMJIT_INST_3x(vprorvd, Vprorvd, Vec, Vec, Mem) // AVX512_F{kz|b32} ASMJIT_INST_3x(vprorvq, Vprorvq, Vec, Vec, Vec) // AVX512_F{kz|b64} @@ -3183,98 +3169,98 @@ public: ASMJIT_INST_2x(vpscatterdq, Vpscatterdq, Mem, Vec) // AVX512_F{k} ASMJIT_INST_2x(vpscatterqd, Vpscatterqd, Mem, Vec) // AVX512_F{k} ASMJIT_INST_2x(vpscatterqq, Vpscatterqq, Mem, Vec) // AVX512_F{k} - ASMJIT_INST_4i(vpshldd, Vpshldd, Vec, Vec, Vec, Imm) // AVX512_VBMI2{kz} - ASMJIT_INST_4i(vpshldd, Vpshldd, Vec, Vec, Mem, Imm) // AVX512_VBMI2{kz} + ASMJIT_INST_4x(vpshldd, Vpshldd, Vec, Vec, Vec, Imm) // AVX512_VBMI2{kz} + ASMJIT_INST_4x(vpshldd, Vpshldd, Vec, Vec, Mem, Imm) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshldvd, Vpshldvd, Vec, Vec, Vec) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshldvd, Vpshldvd, Vec, Vec, Mem) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshldvq, Vpshldvq, Vec, Vec, Vec) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshldvq, Vpshldvq, Vec, Vec, Mem) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshldvw, Vpshldvw, Vec, Vec, Vec) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshldvw, Vpshldvw, Vec, Vec, Mem) // AVX512_VBMI2{kz} - ASMJIT_INST_4i(vpshrdd, Vpshrdd, Vec, Vec, Vec, Imm) // AVX512_VBMI2{kz} - ASMJIT_INST_4i(vpshrdd, Vpshrdd, Vec, Vec, Mem, Imm) // AVX512_VBMI2{kz} + ASMJIT_INST_4x(vpshrdd, Vpshrdd, Vec, Vec, Vec, Imm) // AVX512_VBMI2{kz} + ASMJIT_INST_4x(vpshrdd, Vpshrdd, Vec, Vec, Mem, Imm) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshrdvd, Vpshrdvd, Vec, Vec, Vec) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshrdvd, Vpshrdvd, Vec, Vec, Mem) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshrdvq, Vpshrdvq, Vec, Vec, Vec) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshrdvq, Vpshrdvq, Vec, Vec, Mem) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshrdvw, Vpshrdvw, Vec, Vec, Vec) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshrdvw, Vpshrdvw, Vec, Vec, Mem) // AVX512_VBMI2{kz} - ASMJIT_INST_4i(vpshrdw, Vpshrdw, Vec, Vec, Vec, Imm) // AVX512_VBMI2{kz} - ASMJIT_INST_4i(vpshrdw, Vpshrdw, Vec, Vec, Mem, Imm) // AVX512_VBMI2{kz} + ASMJIT_INST_4x(vpshrdw, Vpshrdw, Vec, Vec, Vec, Imm) // AVX512_VBMI2{kz} + ASMJIT_INST_4x(vpshrdw, Vpshrdw, Vec, Vec, Mem, Imm) // AVX512_VBMI2{kz} ASMJIT_INST_3x(vpshufb, Vpshufb, Vec, Vec, Vec) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpshufb, Vpshufb, Vec, Vec, Mem) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpshufbitqmb, Vpshufbitqmb, KReg, Vec, Vec) // AVX512_BITALG{k} ASMJIT_INST_3x(vpshufbitqmb, Vpshufbitqmb, KReg, Vec, Mem) // AVX512_BITALG{k} - ASMJIT_INST_3i(vpshufd, Vpshufd, Vec, Vec, Imm) // AVX+ AVX512_F{kz|b32} - ASMJIT_INST_3i(vpshufd, Vpshufd, Vec, Mem, Imm) // AVX+ AVX512_F{kz|b32} - ASMJIT_INST_3i(vpshufhw, Vpshufhw, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} - ASMJIT_INST_3i(vpshufhw, Vpshufhw, Vec, Mem, Imm) // AVX+ AVX512_BW{kz} - ASMJIT_INST_3i(vpshuflw, Vpshuflw, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} - ASMJIT_INST_3i(vpshuflw, Vpshuflw, Vec, Mem, Imm) // AVX+ AVX512_BW{kz} + ASMJIT_INST_3x(vpshufd, Vpshufd, Vec, Vec, Imm) // AVX+ AVX512_F{kz|b32} + ASMJIT_INST_3x(vpshufd, Vpshufd, Vec, Mem, Imm) // AVX+ AVX512_F{kz|b32} + ASMJIT_INST_3x(vpshufhw, Vpshufhw, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} + ASMJIT_INST_3x(vpshufhw, Vpshufhw, Vec, Mem, Imm) // AVX+ AVX512_BW{kz} + ASMJIT_INST_3x(vpshuflw, Vpshuflw, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} + ASMJIT_INST_3x(vpshuflw, Vpshuflw, Vec, Mem, Imm) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpsignb, Vpsignb, Vec, Vec, Vec) // AVX+ ASMJIT_INST_3x(vpsignb, Vpsignb, Vec, Vec, Mem) // AVX+ ASMJIT_INST_3x(vpsignd, Vpsignd, Vec, Vec, Vec) // AVX+ ASMJIT_INST_3x(vpsignd, Vpsignd, Vec, Vec, Mem) // AVX+ ASMJIT_INST_3x(vpsignw, Vpsignw, Vec, Vec, Vec) // AVX+ ASMJIT_INST_3x(vpsignw, Vpsignw, Vec, Vec, Mem) // AVX+ - ASMJIT_INST_3i(vpslld, Vpslld, Vec, Vec, Imm) // AVX+ AVX512_F{kz|b32} + ASMJIT_INST_3x(vpslld, Vpslld, Vec, Vec, Imm) // AVX+ AVX512_F{kz|b32} ASMJIT_INST_3x(vpslld, Vpslld, Vec, Vec, Vec) // AVX+ AVX512_F{kz} ASMJIT_INST_3x(vpslld, Vpslld, Vec, Vec, Mem) // AVX+ AVX512_F{kz} - ASMJIT_INST_3i(vpslld, Vpslld, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_3i(vpslldq, Vpslldq, Vec, Vec, Imm) // AVX+ AVX512_BW - ASMJIT_INST_3i(vpslldq, Vpslldq, Vec, Mem, Imm) // AVX512_BW - ASMJIT_INST_3i(vpsllq, Vpsllq, Vec, Vec, Imm) // AVX+ AVX512_F{kz|b64} + ASMJIT_INST_3x(vpslld, Vpslld, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_3x(vpslldq, Vpslldq, Vec, Vec, Imm) // AVX+ AVX512_BW + ASMJIT_INST_3x(vpslldq, Vpslldq, Vec, Mem, Imm) // AVX512_BW + ASMJIT_INST_3x(vpsllq, Vpsllq, Vec, Vec, Imm) // AVX+ AVX512_F{kz|b64} ASMJIT_INST_3x(vpsllq, Vpsllq, Vec, Vec, Vec) // AVX+ AVX512_F{kz} ASMJIT_INST_3x(vpsllq, Vpsllq, Vec, Vec, Mem) // AVX+ AVX512_F{kz} - ASMJIT_INST_3i(vpsllq, Vpsllq, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vpsllq, Vpsllq, Vec, Mem, Imm) // AVX512_F{kz|b64} ASMJIT_INST_3x(vpsllvd, Vpsllvd, Vec, Vec, Vec) // AVX2 AVX512_F{kz|b32} ASMJIT_INST_3x(vpsllvd, Vpsllvd, Vec, Vec, Mem) // AVX2 AVX512_F{kz|b32} ASMJIT_INST_3x(vpsllvq, Vpsllvq, Vec, Vec, Vec) // AVX2 AVX512_F{kz|b64} ASMJIT_INST_3x(vpsllvq, Vpsllvq, Vec, Vec, Mem) // AVX2 AVX512_F{kz|b64} ASMJIT_INST_3x(vpsllvw, Vpsllvw, Vec, Vec, Vec) // AVX512_BW{kz} ASMJIT_INST_3x(vpsllvw, Vpsllvw, Vec, Vec, Mem) // AVX512_BW{kz} - ASMJIT_INST_3i(vpsllw, Vpsllw, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} + ASMJIT_INST_3x(vpsllw, Vpsllw, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpsllw, Vpsllw, Vec, Vec, Vec) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpsllw, Vpsllw, Vec, Vec, Mem) // AVX+ AVX512_BW{kz} - ASMJIT_INST_3i(vpsllw, Vpsllw, Vec, Mem, Imm) // AVX512_BW{kz} - ASMJIT_INST_3i(vpsrad, Vpsrad, Vec, Vec, Imm) // AVX+ AVX512_F{kz|b32} + ASMJIT_INST_3x(vpsllw, Vpsllw, Vec, Mem, Imm) // AVX512_BW{kz} + ASMJIT_INST_3x(vpsrad, Vpsrad, Vec, Vec, Imm) // AVX+ AVX512_F{kz|b32} ASMJIT_INST_3x(vpsrad, Vpsrad, Vec, Vec, Vec) // AVX+ AVX512_F{kz} ASMJIT_INST_3x(vpsrad, Vpsrad, Vec, Vec, Mem) // AVX+ AVX512_F{kz} - ASMJIT_INST_3i(vpsrad, Vpsrad, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_3x(vpsrad, Vpsrad, Vec, Mem, Imm) // AVX512_F{kz|b32} ASMJIT_INST_3x(vpsraq, Vpsraq, Vec, Vec, Vec) // AVX512_F{kz} ASMJIT_INST_3x(vpsraq, Vpsraq, Vec, Vec, Mem) // AVX512_F{kz} - ASMJIT_INST_3i(vpsraq, Vpsraq, Vec, Vec, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_3i(vpsraq, Vpsraq, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vpsraq, Vpsraq, Vec, Vec, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vpsraq, Vpsraq, Vec, Mem, Imm) // AVX512_F{kz|b64} ASMJIT_INST_3x(vpsravd, Vpsravd, Vec, Vec, Vec) // AVX2 AVX512_F{kz|b32} ASMJIT_INST_3x(vpsravd, Vpsravd, Vec, Vec, Mem) // AVX2 AVX512_F{kz|b32} ASMJIT_INST_3x(vpsravq, Vpsravq, Vec, Vec, Vec) // AVX512_F{kz|b64} ASMJIT_INST_3x(vpsravq, Vpsravq, Vec, Vec, Mem) // AVX512_F{kz|b64} ASMJIT_INST_3x(vpsravw, Vpsravw, Vec, Vec, Vec) // AVX512_BW{kz} ASMJIT_INST_3x(vpsravw, Vpsravw, Vec, Vec, Mem) // AVX512_BW{kz} - ASMJIT_INST_3i(vpsraw, Vpsraw, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} + ASMJIT_INST_3x(vpsraw, Vpsraw, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpsraw, Vpsraw, Vec, Vec, Vec) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpsraw, Vpsraw, Vec, Vec, Mem) // AVX+ AVX512_BW{kz} - ASMJIT_INST_3i(vpsraw, Vpsraw, Vec, Mem, Imm) // AVX512_BW{kz} - ASMJIT_INST_3i(vpsrld, Vpsrld, Vec, Vec, Imm) // AVX+ AVX512_F{kz|b32} + ASMJIT_INST_3x(vpsraw, Vpsraw, Vec, Mem, Imm) // AVX512_BW{kz} + ASMJIT_INST_3x(vpsrld, Vpsrld, Vec, Vec, Imm) // AVX+ AVX512_F{kz|b32} ASMJIT_INST_3x(vpsrld, Vpsrld, Vec, Vec, Vec) // AVX+ AVX512_F{kz} ASMJIT_INST_3x(vpsrld, Vpsrld, Vec, Vec, Mem) // AVX+ AVX512_F{kz} - ASMJIT_INST_3i(vpsrld, Vpsrld, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_3i(vpsrldq, Vpsrldq, Vec, Vec, Imm) // AVX+ AVX512_BW - ASMJIT_INST_3i(vpsrldq, Vpsrldq, Vec, Mem, Imm) // AVX512_BW - ASMJIT_INST_3i(vpsrlq, Vpsrlq, Vec, Vec, Imm) // AVX AVX512_F{kz|b64} + ASMJIT_INST_3x(vpsrld, Vpsrld, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_3x(vpsrldq, Vpsrldq, Vec, Vec, Imm) // AVX+ AVX512_BW + ASMJIT_INST_3x(vpsrldq, Vpsrldq, Vec, Mem, Imm) // AVX512_BW + ASMJIT_INST_3x(vpsrlq, Vpsrlq, Vec, Vec, Imm) // AVX AVX512_F{kz|b64} ASMJIT_INST_3x(vpsrlq, Vpsrlq, Vec, Vec, Vec) // AVX AVX512_F{kz} ASMJIT_INST_3x(vpsrlq, Vpsrlq, Vec, Vec, Mem) // AVX AVX512_F{kz} - ASMJIT_INST_3i(vpsrlq, Vpsrlq, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vpsrlq, Vpsrlq, Vec, Mem, Imm) // AVX512_F{kz|b64} ASMJIT_INST_3x(vpsrlvd, Vpsrlvd, Vec, Vec, Vec) // AVX2 AVX512_F{kz|b32} ASMJIT_INST_3x(vpsrlvd, Vpsrlvd, Vec, Vec, Mem) // AVX2 AVX512_F{kz|b32} ASMJIT_INST_3x(vpsrlvq, Vpsrlvq, Vec, Vec, Vec) // AVX2 AVX512_F{kz|b64} ASMJIT_INST_3x(vpsrlvq, Vpsrlvq, Vec, Vec, Mem) // AVX2 AVX512_F{kz|b64} ASMJIT_INST_3x(vpsrlvw, Vpsrlvw, Vec, Vec, Vec) // AVX512_BW{kz} ASMJIT_INST_3x(vpsrlvw, Vpsrlvw, Vec, Vec, Mem) // AVX512_BW{kz} - ASMJIT_INST_3i(vpsrlw, Vpsrlw, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} + ASMJIT_INST_3x(vpsrlw, Vpsrlw, Vec, Vec, Imm) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpsrlw, Vpsrlw, Vec, Vec, Vec) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpsrlw, Vpsrlw, Vec, Vec, Mem) // AVX+ AVX512_BW{kz} - ASMJIT_INST_3i(vpsrlw, Vpsrlw, Vec, Mem, Imm) // AVX512_BW{kz} + ASMJIT_INST_3x(vpsrlw, Vpsrlw, Vec, Mem, Imm) // AVX512_BW{kz} ASMJIT_INST_3x(vpsubb, Vpsubb, Vec, Vec, Vec) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpsubb, Vpsubb, Vec, Vec, Mem) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpsubd, Vpsubd, Vec, Vec, Vec) // AVX+ AVX512_F{kz|b32} @@ -3291,10 +3277,10 @@ public: ASMJIT_INST_3x(vpsubusw, Vpsubusw, Vec, Vec, Mem) // AVX+ AVX512_BW{kz} ASMJIT_INST_3x(vpsubw, Vpsubw, Vec, Vec, Vec) // AVX AVX512_BW{kz} ASMJIT_INST_3x(vpsubw, Vpsubw, Vec, Vec, Mem) // AVX AVX512_BW{kz} - ASMJIT_INST_4i(vpternlogd, Vpternlogd, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vpternlogd, Vpternlogd, Vec, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vpternlogq, Vpternlogq, Vec, Vec, Vec, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_4i(vpternlogq, Vpternlogq, Vec, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_4x(vpternlogd, Vpternlogd, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vpternlogd, Vpternlogd, Vec, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vpternlogq, Vpternlogq, Vec, Vec, Vec, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_4x(vpternlogq, Vpternlogq, Vec, Vec, Mem, Imm) // AVX512_F{kz|b64} ASMJIT_INST_2x(vptest, Vptest, Vec, Vec) // AVX ASMJIT_INST_2x(vptest, Vptest, Vec, Mem) // AVX ASMJIT_INST_3x(vptestmb, Vptestmb, KReg, Vec, Vec) // AVX512_BW{k} @@ -3335,14 +3321,14 @@ public: ASMJIT_INST_3x(vpxord, Vpxord, Vec, Vec, Mem) // AVX512_F{kz|b32} ASMJIT_INST_3x(vpxorq, Vpxorq, Vec, Vec, Vec) // AVX512_F{kz|b64} ASMJIT_INST_3x(vpxorq, Vpxorq, Vec, Vec, Mem) // AVX512_F{kz|b64} - ASMJIT_INST_4i(vrangepd, Vrangepd, Vec, Vec, Vec, Imm) // AVX512_DQ{kz|b64} - ASMJIT_INST_4i(vrangepd, Vrangepd, Vec, Vec, Mem, Imm) // AVX512_DQ{kz|b64} - ASMJIT_INST_4i(vrangeps, Vrangeps, Vec, Vec, Vec, Imm) // AVX512_DQ{kz|b32} - ASMJIT_INST_4i(vrangeps, Vrangeps, Vec, Vec, Mem, Imm) // AVX512_DQ{kz|b32} - ASMJIT_INST_4i(vrangesd, Vrangesd, Xmm, Xmm, Xmm, Imm) // AVX512_DQ{kz|sae} - ASMJIT_INST_4i(vrangesd, Vrangesd, Xmm, Xmm, Mem, Imm) // AVX512_DQ{kz|sae} - ASMJIT_INST_4i(vrangess, Vrangess, Xmm, Xmm, Xmm, Imm) // AVX512_DQ{kz|sae} - ASMJIT_INST_4i(vrangess, Vrangess, Xmm, Xmm, Mem, Imm) // AVX512_DQ{kz|sae} + ASMJIT_INST_4x(vrangepd, Vrangepd, Vec, Vec, Vec, Imm) // AVX512_DQ{kz|b64} + ASMJIT_INST_4x(vrangepd, Vrangepd, Vec, Vec, Mem, Imm) // AVX512_DQ{kz|b64} + ASMJIT_INST_4x(vrangeps, Vrangeps, Vec, Vec, Vec, Imm) // AVX512_DQ{kz|b32} + ASMJIT_INST_4x(vrangeps, Vrangeps, Vec, Vec, Mem, Imm) // AVX512_DQ{kz|b32} + ASMJIT_INST_4x(vrangesd, Vrangesd, Xmm, Xmm, Xmm, Imm) // AVX512_DQ{kz|sae} + ASMJIT_INST_4x(vrangesd, Vrangesd, Xmm, Xmm, Mem, Imm) // AVX512_DQ{kz|sae} + ASMJIT_INST_4x(vrangess, Vrangess, Xmm, Xmm, Xmm, Imm) // AVX512_DQ{kz|sae} + ASMJIT_INST_4x(vrangess, Vrangess, Xmm, Xmm, Mem, Imm) // AVX512_DQ{kz|sae} ASMJIT_INST_2x(vrcp14pd, Vrcp14pd, Vec, Vec) // AVX512_F{kz|b64} ASMJIT_INST_2x(vrcp14pd, Vrcp14pd, Vec, Mem) // AVX512_F{kz|b64} ASMJIT_INST_2x(vrcp14ps, Vrcp14ps, Vec, Vec) // AVX512_F{kz|b32} @@ -3363,30 +3349,30 @@ public: ASMJIT_INST_2x(vrcpps, Vrcpps, Vec, Mem) // AVX ASMJIT_INST_3x(vrcpss, Vrcpss, Xmm, Xmm, Xmm) // AVX ASMJIT_INST_3x(vrcpss, Vrcpss, Xmm, Xmm, Mem) // AVX - ASMJIT_INST_3i(vreducepd, Vreducepd, Vec, Vec, Imm) // AVX512_DQ{kz|b64} - ASMJIT_INST_3i(vreducepd, Vreducepd, Vec, Mem, Imm) // AVX512_DQ{kz|b64} - ASMJIT_INST_3i(vreduceps, Vreduceps, Vec, Vec, Imm) // AVX512_DQ{kz|b32} - ASMJIT_INST_3i(vreduceps, Vreduceps, Vec, Mem, Imm) // AVX512_DQ{kz|b32} - ASMJIT_INST_4i(vreducesd, Vreducesd, Xmm, Xmm, Xmm, Imm) // AVX512_DQ{kz} - ASMJIT_INST_4i(vreducesd, Vreducesd, Xmm, Xmm, Mem, Imm) // AVX512_DQ{kz} - ASMJIT_INST_4i(vreducess, Vreducess, Xmm, Xmm, Xmm, Imm) // AVX512_DQ{kz} - ASMJIT_INST_4i(vreducess, Vreducess, Xmm, Xmm, Mem, Imm) // AVX512_DQ{kz} - ASMJIT_INST_3i(vrndscalepd, Vrndscalepd, Vec, Vec, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_3i(vrndscalepd, Vrndscalepd, Vec, Mem, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_3i(vrndscaleps, Vrndscaleps, Vec, Vec, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_3i(vrndscaleps, Vrndscaleps, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vrndscalesd, Vrndscalesd, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vrndscalesd, Vrndscalesd, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vrndscaless, Vrndscaless, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_4i(vrndscaless, Vrndscaless, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} - ASMJIT_INST_3i(vroundpd, Vroundpd, Vec, Vec, Imm) // AVX - ASMJIT_INST_3i(vroundpd, Vroundpd, Vec, Mem, Imm) // AVX - ASMJIT_INST_3i(vroundps, Vroundps, Vec, Vec, Imm) // AVX - ASMJIT_INST_3i(vroundps, Vroundps, Vec, Mem, Imm) // AVX - ASMJIT_INST_4i(vroundsd, Vroundsd, Xmm, Xmm, Xmm, Imm) // AVX - ASMJIT_INST_4i(vroundsd, Vroundsd, Xmm, Xmm, Mem, Imm) // AVX - ASMJIT_INST_4i(vroundss, Vroundss, Xmm, Xmm, Xmm, Imm) // AVX - ASMJIT_INST_4i(vroundss, Vroundss, Xmm, Xmm, Mem, Imm) // AVX + ASMJIT_INST_3x(vreducepd, Vreducepd, Vec, Vec, Imm) // AVX512_DQ{kz|b64} + ASMJIT_INST_3x(vreducepd, Vreducepd, Vec, Mem, Imm) // AVX512_DQ{kz|b64} + ASMJIT_INST_3x(vreduceps, Vreduceps, Vec, Vec, Imm) // AVX512_DQ{kz|b32} + ASMJIT_INST_3x(vreduceps, Vreduceps, Vec, Mem, Imm) // AVX512_DQ{kz|b32} + ASMJIT_INST_4x(vreducesd, Vreducesd, Xmm, Xmm, Xmm, Imm) // AVX512_DQ{kz} + ASMJIT_INST_4x(vreducesd, Vreducesd, Xmm, Xmm, Mem, Imm) // AVX512_DQ{kz} + ASMJIT_INST_4x(vreducess, Vreducess, Xmm, Xmm, Xmm, Imm) // AVX512_DQ{kz} + ASMJIT_INST_4x(vreducess, Vreducess, Xmm, Xmm, Mem, Imm) // AVX512_DQ{kz} + ASMJIT_INST_3x(vrndscalepd, Vrndscalepd, Vec, Vec, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vrndscalepd, Vrndscalepd, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_3x(vrndscaleps, Vrndscaleps, Vec, Vec, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_3x(vrndscaleps, Vrndscaleps, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vrndscalesd, Vrndscalesd, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vrndscalesd, Vrndscalesd, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vrndscaless, Vrndscaless, Xmm, Xmm, Xmm, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_4x(vrndscaless, Vrndscaless, Xmm, Xmm, Mem, Imm) // AVX512_F{kz|sae} + ASMJIT_INST_3x(vroundpd, Vroundpd, Vec, Vec, Imm) // AVX + ASMJIT_INST_3x(vroundpd, Vroundpd, Vec, Mem, Imm) // AVX + ASMJIT_INST_3x(vroundps, Vroundps, Vec, Vec, Imm) // AVX + ASMJIT_INST_3x(vroundps, Vroundps, Vec, Mem, Imm) // AVX + ASMJIT_INST_4x(vroundsd, Vroundsd, Xmm, Xmm, Xmm, Imm) // AVX + ASMJIT_INST_4x(vroundsd, Vroundsd, Xmm, Xmm, Mem, Imm) // AVX + ASMJIT_INST_4x(vroundss, Vroundss, Xmm, Xmm, Xmm, Imm) // AVX + ASMJIT_INST_4x(vroundss, Vroundss, Xmm, Xmm, Mem, Imm) // AVX ASMJIT_INST_2x(vrsqrt14pd, Vrsqrt14pd, Vec, Vec) // AVX512_F{kz|b64} ASMJIT_INST_2x(vrsqrt14pd, Vrsqrt14pd, Vec, Mem) // AVX512_F{kz|b64} ASMJIT_INST_2x(vrsqrt14ps, Vrsqrt14ps, Vec, Vec) // AVX512_F{kz|b32} @@ -3427,18 +3413,18 @@ public: ASMJIT_INST_1x(vscatterpf1qps, Vscatterpf1qps, Mem) // AVX512_PF{k} ASMJIT_INST_2x(vscatterqpd, Vscatterqpd, Mem, Vec) // AVX512_F{k} ASMJIT_INST_2x(vscatterqps, Vscatterqps, Mem, Vec) // AVX512_F{k} - ASMJIT_INST_4i(vshuff32x4, Vshuff32x4, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vshuff32x4, Vshuff32x4, Vec, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vshuff64x2, Vshuff64x2, Vec, Vec, Vec, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_4i(vshuff64x2, Vshuff64x2, Vec, Vec, Mem, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_4i(vshufi32x4, Vshufi32x4, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vshufi32x4, Vshufi32x4, Vec, Vec, Mem, Imm) // AVX512_F{kz|b32} - ASMJIT_INST_4i(vshufi64x2, Vshufi64x2, Vec, Vec, Vec, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_4i(vshufi64x2, Vshufi64x2, Vec, Vec, Mem, Imm) // AVX512_F{kz|b64} - ASMJIT_INST_4i(vshufpd, Vshufpd, Vec, Vec, Vec, Imm) // AVX AVX512_F{kz|b32} - ASMJIT_INST_4i(vshufpd, Vshufpd, Vec, Vec, Mem, Imm) // AVX AVX512_F{kz|b32} - ASMJIT_INST_4i(vshufps, Vshufps, Vec, Vec, Vec, Imm) // AVX AVX512_F{kz|b64} - ASMJIT_INST_4i(vshufps, Vshufps, Vec, Vec, Mem, Imm) // AVX AVX512_F{kz|b64} + ASMJIT_INST_4x(vshuff32x4, Vshuff32x4, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vshuff32x4, Vshuff32x4, Vec, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vshuff64x2, Vshuff64x2, Vec, Vec, Vec, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_4x(vshuff64x2, Vshuff64x2, Vec, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_4x(vshufi32x4, Vshufi32x4, Vec, Vec, Vec, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vshufi32x4, Vshufi32x4, Vec, Vec, Mem, Imm) // AVX512_F{kz|b32} + ASMJIT_INST_4x(vshufi64x2, Vshufi64x2, Vec, Vec, Vec, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_4x(vshufi64x2, Vshufi64x2, Vec, Vec, Mem, Imm) // AVX512_F{kz|b64} + ASMJIT_INST_4x(vshufpd, Vshufpd, Vec, Vec, Vec, Imm) // AVX AVX512_F{kz|b32} + ASMJIT_INST_4x(vshufpd, Vshufpd, Vec, Vec, Mem, Imm) // AVX AVX512_F{kz|b32} + ASMJIT_INST_4x(vshufps, Vshufps, Vec, Vec, Vec, Imm) // AVX AVX512_F{kz|b64} + ASMJIT_INST_4x(vshufps, Vshufps, Vec, Vec, Mem, Imm) // AVX AVX512_F{kz|b64} ASMJIT_INST_2x(vsqrtpd, Vsqrtpd, Vec, Vec) // AVX AVX512_F{kz|b64} ASMJIT_INST_2x(vsqrtpd, Vsqrtpd, Vec, Mem) // AVX AVX512_F{kz|b64} ASMJIT_INST_2x(vsqrtps, Vsqrtps, Vec, Vec) // AVX AVX512_F{kz|b32} @@ -3561,28 +3547,28 @@ public: ASMJIT_INST_4x(vpcmov, Vpcmov, Vec, Vec, Vec, Vec) // XOP ASMJIT_INST_4x(vpcmov, Vpcmov, Vec, Vec, Mem, Vec) // XOP ASMJIT_INST_4x(vpcmov, Vpcmov, Vec, Vec, Vec, Mem) // XOP - ASMJIT_INST_4i(vpcomb, Vpcomb, Xmm, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_4i(vpcomb, Vpcomb, Xmm, Xmm, Mem, Imm) // XOP - ASMJIT_INST_4i(vpcomd, Vpcomd, Xmm, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_4i(vpcomd, Vpcomd, Xmm, Xmm, Mem, Imm) // XOP - ASMJIT_INST_4i(vpcomq, Vpcomq, Xmm, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_4i(vpcomq, Vpcomq, Xmm, Xmm, Mem, Imm) // XOP - ASMJIT_INST_4i(vpcomw, Vpcomw, Xmm, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_4i(vpcomw, Vpcomw, Xmm, Xmm, Mem, Imm) // XOP - ASMJIT_INST_4i(vpcomub, Vpcomub, Xmm, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_4i(vpcomub, Vpcomub, Xmm, Xmm, Mem, Imm) // XOP - ASMJIT_INST_4i(vpcomud, Vpcomud, Xmm, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_4i(vpcomud, Vpcomud, Xmm, Xmm, Mem, Imm) // XOP - ASMJIT_INST_4i(vpcomuq, Vpcomuq, Xmm, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_4i(vpcomuq, Vpcomuq, Xmm, Xmm, Mem, Imm) // XOP - ASMJIT_INST_4i(vpcomuw, Vpcomuw, Xmm, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_4i(vpcomuw, Vpcomuw, Xmm, Xmm, Mem, Imm) // XOP - ASMJIT_INST_5i(vpermil2pd, Vpermil2pd, Vec, Vec, Vec, Vec, Imm) // XOP - ASMJIT_INST_5i(vpermil2pd, Vpermil2pd, Vec, Vec, Mem, Vec, Imm) // XOP - ASMJIT_INST_5i(vpermil2pd, Vpermil2pd, Vec, Vec, Vec, Mem, Imm) // XOP - ASMJIT_INST_5i(vpermil2ps, Vpermil2ps, Vec, Vec, Vec, Vec, Imm) // XOP - ASMJIT_INST_5i(vpermil2ps, Vpermil2ps, Vec, Vec, Mem, Vec, Imm) // XOP - ASMJIT_INST_5i(vpermil2ps, Vpermil2ps, Vec, Vec, Vec, Mem, Imm) // XOP + ASMJIT_INST_4x(vpcomb, Vpcomb, Xmm, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_4x(vpcomb, Vpcomb, Xmm, Xmm, Mem, Imm) // XOP + ASMJIT_INST_4x(vpcomd, Vpcomd, Xmm, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_4x(vpcomd, Vpcomd, Xmm, Xmm, Mem, Imm) // XOP + ASMJIT_INST_4x(vpcomq, Vpcomq, Xmm, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_4x(vpcomq, Vpcomq, Xmm, Xmm, Mem, Imm) // XOP + ASMJIT_INST_4x(vpcomw, Vpcomw, Xmm, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_4x(vpcomw, Vpcomw, Xmm, Xmm, Mem, Imm) // XOP + ASMJIT_INST_4x(vpcomub, Vpcomub, Xmm, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_4x(vpcomub, Vpcomub, Xmm, Xmm, Mem, Imm) // XOP + ASMJIT_INST_4x(vpcomud, Vpcomud, Xmm, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_4x(vpcomud, Vpcomud, Xmm, Xmm, Mem, Imm) // XOP + ASMJIT_INST_4x(vpcomuq, Vpcomuq, Xmm, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_4x(vpcomuq, Vpcomuq, Xmm, Xmm, Mem, Imm) // XOP + ASMJIT_INST_4x(vpcomuw, Vpcomuw, Xmm, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_4x(vpcomuw, Vpcomuw, Xmm, Xmm, Mem, Imm) // XOP + ASMJIT_INST_5x(vpermil2pd, Vpermil2pd, Vec, Vec, Vec, Vec, Imm) // XOP + ASMJIT_INST_5x(vpermil2pd, Vpermil2pd, Vec, Vec, Mem, Vec, Imm) // XOP + ASMJIT_INST_5x(vpermil2pd, Vpermil2pd, Vec, Vec, Vec, Mem, Imm) // XOP + ASMJIT_INST_5x(vpermil2ps, Vpermil2ps, Vec, Vec, Vec, Vec, Imm) // XOP + ASMJIT_INST_5x(vpermil2ps, Vpermil2ps, Vec, Vec, Mem, Vec, Imm) // XOP + ASMJIT_INST_5x(vpermil2ps, Vpermil2ps, Vec, Vec, Vec, Mem, Imm) // XOP ASMJIT_INST_2x(vphaddbd, Vphaddbd, Xmm, Xmm) // XOP ASMJIT_INST_2x(vphaddbd, Vphaddbd, Xmm, Mem) // XOP ASMJIT_INST_2x(vphaddbq, Vphaddbq, Xmm, Xmm) // XOP @@ -3643,23 +3629,23 @@ public: ASMJIT_INST_3x(vprotb, Vprotb, Xmm, Xmm, Xmm) // XOP ASMJIT_INST_3x(vprotb, Vprotb, Xmm, Mem, Xmm) // XOP ASMJIT_INST_3x(vprotb, Vprotb, Xmm, Xmm, Mem) // XOP - ASMJIT_INST_3i(vprotb, Vprotb, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_3i(vprotb, Vprotb, Xmm, Mem, Imm) // XOP + ASMJIT_INST_3x(vprotb, Vprotb, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_3x(vprotb, Vprotb, Xmm, Mem, Imm) // XOP ASMJIT_INST_3x(vprotd, Vprotd, Xmm, Xmm, Xmm) // XOP ASMJIT_INST_3x(vprotd, Vprotd, Xmm, Mem, Xmm) // XOP ASMJIT_INST_3x(vprotd, Vprotd, Xmm, Xmm, Mem) // XOP - ASMJIT_INST_3i(vprotd, Vprotd, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_3i(vprotd, Vprotd, Xmm, Mem, Imm) // XOP + ASMJIT_INST_3x(vprotd, Vprotd, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_3x(vprotd, Vprotd, Xmm, Mem, Imm) // XOP ASMJIT_INST_3x(vprotq, Vprotq, Xmm, Xmm, Xmm) // XOP ASMJIT_INST_3x(vprotq, Vprotq, Xmm, Mem, Xmm) // XOP ASMJIT_INST_3x(vprotq, Vprotq, Xmm, Xmm, Mem) // XOP - ASMJIT_INST_3i(vprotq, Vprotq, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_3i(vprotq, Vprotq, Xmm, Mem, Imm) // XOP + ASMJIT_INST_3x(vprotq, Vprotq, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_3x(vprotq, Vprotq, Xmm, Mem, Imm) // XOP ASMJIT_INST_3x(vprotw, Vprotw, Xmm, Xmm, Xmm) // XOP ASMJIT_INST_3x(vprotw, Vprotw, Xmm, Mem, Xmm) // XOP ASMJIT_INST_3x(vprotw, Vprotw, Xmm, Xmm, Mem) // XOP - ASMJIT_INST_3i(vprotw, Vprotw, Xmm, Xmm, Imm) // XOP - ASMJIT_INST_3i(vprotw, Vprotw, Xmm, Mem, Imm) // XOP + ASMJIT_INST_3x(vprotw, Vprotw, Xmm, Xmm, Imm) // XOP + ASMJIT_INST_3x(vprotw, Vprotw, Xmm, Mem, Imm) // XOP ASMJIT_INST_3x(vpshab, Vpshab, Xmm, Xmm, Xmm) // XOP ASMJIT_INST_3x(vpshab, Vpshab, Xmm, Mem, Xmm) // XOP ASMJIT_INST_3x(vpshab, Vpshab, Xmm, Xmm, Mem) // XOP @@ -3790,7 +3776,7 @@ struct EmitterImplicitT : public EmitterExplicitT { ASMJIT_INST_1x(mul, Mul, Gp) // ANY [IMPLICIT] {AX <- AL * r8} {xDX:xAX <- xAX * r16|r32|r64} ASMJIT_INST_1x(mul, Mul, Mem) // ANY [IMPLICIT] {AX <- AL * m8} {xDX:xAX <- xAX * m16|m32|m64} ASMJIT_INST_0x(ret, Ret) - ASMJIT_INST_1i(ret, Ret, Imm) + ASMJIT_INST_1x(ret, Ret, Imm) ASMJIT_INST_0x(xlatb, Xlatb) // ANY [IMPLICIT] //! \} @@ -3842,8 +3828,8 @@ struct EmitterImplicitT : public EmitterExplicitT { //! \endcond ASMJIT_INST_0x(aaa, Aaa) // X86 [IMPLICIT] - ASMJIT_INST_1i(aad, Aad, Imm) // X86 [IMPLICIT] - ASMJIT_INST_1i(aam, Aam, Imm) // X86 [IMPLICIT] + ASMJIT_INST_1x(aad, Aad, Imm) // X86 [IMPLICIT] + ASMJIT_INST_1x(aam, Aam, Imm) // X86 [IMPLICIT] ASMJIT_INST_0x(aas, Aas) // X86 [IMPLICIT] ASMJIT_INST_0x(daa, Daa) // X86 [IMPLICIT] ASMJIT_INST_0x(das, Das) // X86 [IMPLICIT] @@ -4031,14 +4017,14 @@ struct EmitterImplicitT : public EmitterExplicitT { ASMJIT_INST_2x(pblendvb, Pblendvb, Xmm, Mem) // SSE4_1 [IMPLICIT] ASMJIT_INST_2x(maskmovq, Maskmovq, Mm, Mm) // SSE [IMPLICIT] ASMJIT_INST_2x(maskmovdqu, Maskmovdqu, Xmm, Xmm) // SSE2 [IMPLICIT] - ASMJIT_INST_3i(pcmpestri, Pcmpestri, Xmm, Xmm, Imm) // SSE4_1 [IMPLICIT] - ASMJIT_INST_3i(pcmpestri, Pcmpestri, Xmm, Mem, Imm) // SSE4_1 [IMPLICIT] - ASMJIT_INST_3i(pcmpestrm, Pcmpestrm, Xmm, Xmm, Imm) // SSE4_1 [IMPLICIT] - ASMJIT_INST_3i(pcmpestrm, Pcmpestrm, Xmm, Mem, Imm) // SSE4_1 [IMPLICIT] - ASMJIT_INST_3i(pcmpistri, Pcmpistri, Xmm, Xmm, Imm) // SSE4_1 [IMPLICIT] - ASMJIT_INST_3i(pcmpistri, Pcmpistri, Xmm, Mem, Imm) // SSE4_1 [IMPLICIT] - ASMJIT_INST_3i(pcmpistrm, Pcmpistrm, Xmm, Xmm, Imm) // SSE4_1 [IMPLICIT] - ASMJIT_INST_3i(pcmpistrm, Pcmpistrm, Xmm, Mem, Imm) // SSE4_1 [IMPLICIT] + ASMJIT_INST_3x(pcmpestri, Pcmpestri, Xmm, Xmm, Imm) // SSE4_1 [IMPLICIT] + ASMJIT_INST_3x(pcmpestri, Pcmpestri, Xmm, Mem, Imm) // SSE4_1 [IMPLICIT] + ASMJIT_INST_3x(pcmpestrm, Pcmpestrm, Xmm, Xmm, Imm) // SSE4_1 [IMPLICIT] + ASMJIT_INST_3x(pcmpestrm, Pcmpestrm, Xmm, Mem, Imm) // SSE4_1 [IMPLICIT] + ASMJIT_INST_3x(pcmpistri, Pcmpistri, Xmm, Xmm, Imm) // SSE4_1 [IMPLICIT] + ASMJIT_INST_3x(pcmpistri, Pcmpistri, Xmm, Mem, Imm) // SSE4_1 [IMPLICIT] + ASMJIT_INST_3x(pcmpistrm, Pcmpistrm, Xmm, Xmm, Imm) // SSE4_1 [IMPLICIT] + ASMJIT_INST_3x(pcmpistrm, Pcmpistrm, Xmm, Mem, Imm) // SSE4_1 [IMPLICIT] //! \} @@ -4066,14 +4052,14 @@ struct EmitterImplicitT : public EmitterExplicitT { //! \endcond ASMJIT_INST_2x(vmaskmovdqu, Vmaskmovdqu, Xmm, Xmm) // AVX [IMPLICIT] - ASMJIT_INST_3i(vpcmpestri, Vpcmpestri, Xmm, Xmm, Imm) // AVX [IMPLICIT] - ASMJIT_INST_3i(vpcmpestri, Vpcmpestri, Xmm, Mem, Imm) // AVX [IMPLICIT] - ASMJIT_INST_3i(vpcmpestrm, Vpcmpestrm, Xmm, Xmm, Imm) // AVX [IMPLICIT] - ASMJIT_INST_3i(vpcmpestrm, Vpcmpestrm, Xmm, Mem, Imm) // AVX [IMPLICIT] - ASMJIT_INST_3i(vpcmpistri, Vpcmpistri, Xmm, Xmm, Imm) // AVX [IMPLICIT] - ASMJIT_INST_3i(vpcmpistri, Vpcmpistri, Xmm, Mem, Imm) // AVX [IMPLICIT] - ASMJIT_INST_3i(vpcmpistrm, Vpcmpistrm, Xmm, Xmm, Imm) // AVX [IMPLICIT] - ASMJIT_INST_3i(vpcmpistrm, Vpcmpistrm, Xmm, Mem, Imm) // AVX [IMPLICIT] + ASMJIT_INST_3x(vpcmpestri, Vpcmpestri, Xmm, Xmm, Imm) // AVX [IMPLICIT] + ASMJIT_INST_3x(vpcmpestri, Vpcmpestri, Xmm, Mem, Imm) // AVX [IMPLICIT] + ASMJIT_INST_3x(vpcmpestrm, Vpcmpestrm, Xmm, Xmm, Imm) // AVX [IMPLICIT] + ASMJIT_INST_3x(vpcmpestrm, Vpcmpestrm, Xmm, Mem, Imm) // AVX [IMPLICIT] + ASMJIT_INST_3x(vpcmpistri, Vpcmpistri, Xmm, Xmm, Imm) // AVX [IMPLICIT] + ASMJIT_INST_3x(vpcmpistri, Vpcmpistri, Xmm, Mem, Imm) // AVX [IMPLICIT] + ASMJIT_INST_3x(vpcmpistrm, Vpcmpistrm, Xmm, Xmm, Imm) // AVX [IMPLICIT] + ASMJIT_INST_3x(vpcmpistrm, Vpcmpistrm, Xmm, Mem, Imm) // AVX [IMPLICIT] //! \} }; @@ -4096,19 +4082,12 @@ class Emitter : public BaseEmitter, public EmitterImplicitT { #undef ASMJIT_INST_0x #undef ASMJIT_INST_1x -#undef ASMJIT_INST_1i #undef ASMJIT_INST_1c #undef ASMJIT_INST_2x -#undef ASMJIT_INST_2i #undef ASMJIT_INST_2c #undef ASMJIT_INST_3x -#undef ASMJIT_INST_3i -#undef ASMJIT_INST_3ii #undef ASMJIT_INST_4x -#undef ASMJIT_INST_4i -#undef ASMJIT_INST_4ii #undef ASMJIT_INST_5x -#undef ASMJIT_INST_5i #undef ASMJIT_INST_6x ASMJIT_END_SUB_NAMESPACE diff --git a/src/asmjit/x86/x86features.cpp b/src/asmjit/x86/x86features.cpp index 16698c8..2a55c94 100644 --- a/src/asmjit/x86/x86features.cpp +++ b/src/asmjit/x86/x86features.cpp @@ -273,6 +273,7 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept { if (bitTest(regs.ecx, 0)) features.add(Features::kPREFETCHWT1); if (bitTest(regs.ecx, 4)) features.add(Features::kOSPKE); if (bitTest(regs.ecx, 5)) features.add(Features::kWAITPKG); + if (bitTest(regs.ecx, 7)) features.add(Features::kCET_SS); if (bitTest(regs.ecx, 8)) features.add(Features::kGFNI); if (bitTest(regs.ecx, 9)) features.add(Features::kVAES); if (bitTest(regs.ecx, 10)) features.add(Features::kVPCLMULQDQ); @@ -281,9 +282,11 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept { if (bitTest(regs.ecx, 27)) features.add(Features::kMOVDIRI); if (bitTest(regs.ecx, 28)) features.add(Features::kMOVDIR64B); if (bitTest(regs.ecx, 29)) features.add(Features::kENQCMD); + if (bitTest(regs.edx, 5)) features.add(Features::kUINTR); if (bitTest(regs.edx, 14)) features.add(Features::kSERIALIZE); if (bitTest(regs.edx, 16)) features.add(Features::kTSXLDTRK); if (bitTest(regs.edx, 18)) features.add(Features::kPCONFIG); + if (bitTest(regs.edx, 20)) features.add(Features::kCET_IBT); // Detect 'TSX' - Requires at least one of `HLE` and `RTM` features. if (features.hasHLE() || features.hasRTM()) @@ -329,7 +332,9 @@ ASMJIT_FAVOR_SIZE void detectCpu(CpuInfo& cpu) noexcept { if (features.hasAVX512_F() && maxSubLeafId_0x7 >= 1) { cpuidQuery(®s, 0x7, 1); + if (bitTest(regs.eax, 3)) features.add(Features::kAVX_VNNI); if (bitTest(regs.eax, 5)) features.add(Features::kAVX512_BF16); + if (bitTest(regs.eax, 22)) features.add(Features::kHRESET); } // -------------------------------------------------------------------------- diff --git a/src/asmjit/x86/x86features.h b/src/asmjit/x86/x86features.h index 527a765..4d098ec 100644 --- a/src/asmjit/x86/x86features.h +++ b/src/asmjit/x86/x86features.h @@ -74,9 +74,10 @@ public: kAVX512_VNNI, //!< CPU has AVX512_VNNI (vector neural network instructions). kAVX512_VP2INTERSECT, //!< CPU has AVX512_VP2INTERSECT kAVX512_VPOPCNTDQ, //!< CPU has AVX512_VPOPCNTDQ (VPOPCNT[D|Q] instructions). + kAVX_VNNI, //!< CPU has AVX_VNNI (VEX encoding of vpdpbusd/vpdpbusds/vpdpwssd/vpdpwssds). kBMI, //!< CPU has BMI (bit manipulation instructions #1). kBMI2, //!< CPU has BMI2 (bit manipulation instructions #2). - kCET_IBT, //!< CPU has CET-IBT. + kCET_IBT, //!< CPU has CET-IBT (indirect branch tracking). kCET_SS, //!< CPU has CET-SS. kCLDEMOTE, //!< CPU has CLDEMOTE (cache line demote). kCLFLUSH, //!< CPU has CLFUSH (Cache Line flush). @@ -99,6 +100,7 @@ public: kGEODE, //!< CPU has GEODE extensions (3DNOW additions). kGFNI, //!< CPU has GFNI (Galois field instructions). kHLE, //!< CPU has HLE. + kHRESET, //!< CPU has HRESET. kI486, //!< CPU has I486 features (I486+ support). kLAHFSAHF, //!< CPU has LAHF/SAHF (LAHF/SAHF in 64-bit mode) [X86_64]. kLWP, //!< CPU has LWP (lightweight profiling) [AMD]. @@ -147,6 +149,7 @@ public: kTBM, //!< CPU has TBM (trailing bit manipulation) [AMD]. kTSX, //!< CPU has TSX. kTSXLDTRK, //!< CPU has TSXLDTRK. + kUINTR, //!< CPU has UINTR (user interrupts). kVAES, //!< CPU has VAES (vector AES 256|512 bit support). kVMX, //!< CPU has VMX (virtualization) [INTEL]. kVPCLMULQDQ, //!< CPU has VPCLMULQDQ (vector PCLMULQDQ 256|512-bit support). @@ -217,8 +220,11 @@ public: ASMJIT_X86_FEATURE(AVX512_VNNI) ASMJIT_X86_FEATURE(AVX512_VP2INTERSECT) ASMJIT_X86_FEATURE(AVX512_VPOPCNTDQ) + ASMJIT_X86_FEATURE(AVX_VNNI) ASMJIT_X86_FEATURE(BMI) ASMJIT_X86_FEATURE(BMI2) + ASMJIT_X86_FEATURE(CET_IBT) + ASMJIT_X86_FEATURE(CET_SS) ASMJIT_X86_FEATURE(CLDEMOTE) ASMJIT_X86_FEATURE(CLFLUSH) ASMJIT_X86_FEATURE(CLFLUSHOPT) @@ -240,6 +246,7 @@ public: ASMJIT_X86_FEATURE(GEODE) ASMJIT_X86_FEATURE(GFNI) ASMJIT_X86_FEATURE(HLE) + ASMJIT_X86_FEATURE(HRESET) ASMJIT_X86_FEATURE(I486) ASMJIT_X86_FEATURE(LAHFSAHF) ASMJIT_X86_FEATURE(LWP) @@ -287,6 +294,7 @@ public: ASMJIT_X86_FEATURE(TBM) ASMJIT_X86_FEATURE(TSX) ASMJIT_X86_FEATURE(TSXLDTRK) + ASMJIT_X86_FEATURE(UINTR) ASMJIT_X86_FEATURE(XSAVE) ASMJIT_X86_FEATURE(XSAVEC) ASMJIT_X86_FEATURE(XSAVEOPT) diff --git a/src/asmjit/x86/x86formatter.cpp b/src/asmjit/x86/x86formatter.cpp index d7b065c..7774ff1 100644 --- a/src/asmjit/x86/x86formatter.cpp +++ b/src/asmjit/x86/x86formatter.cpp @@ -238,6 +238,7 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept "AVX512_VNNI\0" "AVX512_VP2INTERSECT\0" "AVX512_VPOPCNTDQ\0" + "AVX_VNNI\0" "BMI\0" "BMI2\0" "CET_IBT\0" @@ -263,6 +264,7 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept "GEODE\0" "GFNI\0" "HLE\0" + "HRESET\0" "I486\0" "LAHFSAHF\0" "LWP\0" @@ -311,6 +313,7 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept "TBM\0" "TSX\0" "TSXLDTRK\0" + "UINTR\0" "VAES\0" "VMX\0" "VPCLMULQDQ\0" @@ -325,13 +328,13 @@ Error FormatterInternal::formatFeature(String& sb, uint32_t featureId) noexcept static const uint16_t sFeatureIndex[] = { 0, 5, 8, 11, 17, 24, 28, 34, 44, 53, 62, 71, 75, 80, 94, 108, 120, 134, 144, - 155, 165, 176, 185, 197, 208, 220, 233, 243, 255, 275, 292, 296, 301, 309, - 316, 325, 333, 344, 349, 356, 361, 372, 382, 388, 395, 400, 405, 409, 414, - 418, 427, 432, 440, 446, 451, 455, 460, 469, 473, 479, 487, 491, 496, 504, - 513, 519, 529, 537, 541, 545, 550, 558, 564, 574, 582, 589, 599, 611, 619, - 625, 631, 638, 645, 651, 658, 662, 672, 676, 683, 688, 693, 697, 701, 705, - 710, 715, 722, 729, 735, 741, 745, 749, 753, 762, 767, 771, 782, 790, 799, - 803, 809, 816, 825, 832 + 155, 165, 176, 185, 197, 208, 220, 233, 243, 255, 275, 292, 301, 305, 310, + 318, 325, 334, 342, 353, 358, 365, 370, 381, 391, 397, 404, 409, 414, 418, + 423, 427, 436, 441, 449, 455, 460, 464, 471, 476, 485, 489, 495, 503, 507, + 512, 520, 529, 535, 545, 553, 557, 561, 566, 574, 580, 590, 598, 605, 615, + 627, 635, 641, 647, 654, 661, 667, 674, 678, 688, 692, 699, 704, 709, 713, + 717, 721, 726, 731, 738, 745, 751, 757, 761, 765, 769, 778, 784, 789, 793, + 804, 812, 821, 825, 831, 838, 847, 854 }; // @EnumStringEnd@ @@ -871,8 +874,9 @@ ASMJIT_FAVOR_SIZE Error FormatterInternal::formatInstruction( } // VEX|EVEX options. - if (options & Inst::kOptionVex3) ASMJIT_PROPAGATE(sb.append("vex3 ")); - if (options & Inst::kOptionEvex) ASMJIT_PROPAGATE(sb.append("evex ")); + if (options & Inst::kOptionVex) ASMJIT_PROPAGATE(sb.append("{vex} ")); + if (options & Inst::kOptionVex3) ASMJIT_PROPAGATE(sb.append("{vex3} ")); + if (options & Inst::kOptionEvex) ASMJIT_PROPAGATE(sb.append("{evex} ")); ASMJIT_PROPAGATE(InstAPI::instIdToString(arch, instId, sb)); } diff --git a/src/asmjit/x86/x86globals.h b/src/asmjit/x86/x86globals.h index 95838fc..6e6f452 100644 --- a/src/asmjit/x86/x86globals.h +++ b/src/asmjit/x86/x86globals.h @@ -27,13 +27,13 @@ #include "../core/archtraits.h" #include "../core/inst.h" -ASMJIT_BEGIN_SUB_NAMESPACE(x86) - //! \namespace asmjit::x86 //! \ingroup asmjit_x86 //! //! X86/X64 API. +ASMJIT_BEGIN_SUB_NAMESPACE(x86) + //! \addtogroup asmjit_x86 //! \{ @@ -464,6 +464,7 @@ struct Inst : public BaseInst { kIdMonitor, //!< Instruction 'monitor' {MONITOR}. kIdMonitorx, //!< Instruction 'monitorx' {MONITORX}. kIdMov, //!< Instruction 'mov'. + kIdMovabs, //!< Instruction 'movabs' (X64). kIdMovapd, //!< Instruction 'movapd' {SSE2}. kIdMovaps, //!< Instruction 'movaps' {SSE}. kIdMovbe, //!< Instruction 'movbe' {MOVBE}. @@ -1229,10 +1230,10 @@ struct Inst : public BaseInst { kIdVpcomw, //!< Instruction 'vpcomw' {XOP}. kIdVpconflictd, //!< Instruction 'vpconflictd' {AVX512_CDI+VL}. kIdVpconflictq, //!< Instruction 'vpconflictq' {AVX512_CDI+VL}. - kIdVpdpbusd, //!< Instruction 'vpdpbusd' {AVX512_VNNI+VL}. - kIdVpdpbusds, //!< Instruction 'vpdpbusds' {AVX512_VNNI+VL}. - kIdVpdpwssd, //!< Instruction 'vpdpwssd' {AVX512_VNNI+VL}. - kIdVpdpwssds, //!< Instruction 'vpdpwssds' {AVX512_VNNI+VL}. + kIdVpdpbusd, //!< Instruction 'vpdpbusd' {AVX_VNNI|AVX512_VNNI+VL}. + kIdVpdpbusds, //!< Instruction 'vpdpbusds' {AVX_VNNI|AVX512_VNNI+VL}. + kIdVpdpwssd, //!< Instruction 'vpdpwssd' {AVX_VNNI|AVX512_VNNI+VL}. + kIdVpdpwssds, //!< Instruction 'vpdpwssds' {AVX_VNNI|AVX512_VNNI+VL}. kIdVperm2f128, //!< Instruction 'vperm2f128' {AVX}. kIdVperm2i128, //!< Instruction 'vperm2i128' {AVX2}. kIdVpermb, //!< Instruction 'vpermb' {AVX512_VBMI+VL}. @@ -1602,8 +1603,9 @@ struct Inst : public BaseInst { //! Instruction options. enum Options : uint32_t { + kOptionModMR = 0x00000100u, //!< Use ModMR instead of ModRM when it's available. kOptionVex3 = 0x00000400u, //!< Use 3-byte VEX prefix if possible (AVX) (must be 0x00000400). - kOptionModMR = 0x00000800u, //!< Use ModMR instead of ModRM when it's available. + kOptionVex = 0x00000800u, //!< Use VEX prefix when both VEX|EVEX prefixes are available (HINT: AVX_VNNI). kOptionEvex = 0x00001000u, //!< Use 4-byte EVEX prefix if possible (AVX-512) (must be 0x00001000). kOptionLock = 0x00002000u, //!< LOCK prefix (lock-enabled instructions only). diff --git a/src/asmjit/x86/x86instapi.cpp b/src/asmjit/x86/x86instapi.cpp index 114bca2..19d4e60 100644 --- a/src/asmjit/x86/x86instapi.cpp +++ b/src/asmjit/x86/x86instapi.cpp @@ -1067,6 +1067,35 @@ Error InstInternal::queryRWInfo(uint32_t arch, const BaseInst& inst, const Opera break; } + case InstDB::RWInfo::kCategoryMovabs: { + if (opCount == 2) { + if (Reg::isGp(operands[0]) && operands[1].isMem()) { + const Reg& o0 = operands[0].as(); + out->_operands[0].reset(W | RegPhys, o0.size(), Gp::kIdAx); + out->_operands[1].reset(R | MibRead, o0.size()); + rwZeroExtendGp(out->_operands[0], operands[0].as(), nativeGpSize); + return kErrorOk; + } + + if (operands[0].isMem() && Reg::isGp(operands[1])) { + const Reg& o1 = operands[1].as(); + out->_operands[0].reset(W | MibRead, o1.size()); + out->_operands[1].reset(R | RegPhys, o1.size(), Gp::kIdAx); + return kErrorOk; + } + + if (Reg::isGp(operands[0]) && operands[1].isImm()) { + const Reg& o0 = operands[0].as(); + out->_operands[0].reset(W, o0.size()); + out->_operands[1].reset(); + + rwZeroExtendGp(out->_operands[0], operands[0].as(), nativeGpSize); + return kErrorOk; + } + } + break; + } + case InstDB::RWInfo::kCategoryImul: { // Special case for 'imul' instruction. // @@ -1400,6 +1429,14 @@ static RegAnalysis InstInternal_regAnalysis(const Operand_* operands, size_t opC return RegAnalysis { mask, highVecUsed }; } +static ASMJIT_INLINE uint32_t InstInternal_usesAvx512(uint32_t instOptions, const RegOnly& extraReg, const RegAnalysis& regAnalysis) noexcept { + uint32_t hasEvex = instOptions & (Inst::kOptionEvex | Inst::_kOptionAvx512Mask); + uint32_t hasKMask = extraReg.type() == Reg::kTypeKReg; + uint32_t hasKOrZmm = regAnalysis.regTypeMask & Support::bitMask(Reg::kTypeZmm, Reg::kTypeKReg); + + return hasEvex | hasKMask | hasKOrZmm; +} + Error InstInternal::queryFeatures(uint32_t arch, const BaseInst& inst, const Operand_* operands, size_t opCount, BaseFeatures* out) noexcept { // Only called when `arch` matches X86 family. DebugUtils::unused(arch); @@ -1509,10 +1546,7 @@ Error InstInternal::queryFeatures(uint32_t arch, const BaseInst& inst, const Ope if (out->has(Features::kAVX) || out->has(Features::kAVX2) || out->has(Features::kFMA) || out->has(Features::kF16C)) { // Only AVX512-F|BW|DQ allow to encode AVX/AVX2/FMA/F16C instructions if (out->has(Features::kAVX512_F) || out->has(Features::kAVX512_BW) || out->has(Features::kAVX512_DQ)) { - uint32_t hasEvex = options & (Inst::kOptionEvex | Inst::_kOptionAvx512Mask); - uint32_t hasKMask = inst.extraReg().type() == Reg::kTypeKReg; - uint32_t hasKOrZmm = regAnalysis.regTypeMask & Support::bitMask(Reg::kTypeZmm, Reg::kTypeKReg); - + uint32_t usesAvx512 = InstInternal_usesAvx512(options, inst.extraReg(), regAnalysis); uint32_t mustUseEvex = 0; switch (instId) { @@ -1540,13 +1574,26 @@ Error InstInternal::queryFeatures(uint32_t arch, const BaseInst& inst, const Ope break; } - if (!(hasEvex | mustUseEvex | hasKMask | hasKOrZmm | regAnalysis.highVecUsed)) + if (!(usesAvx512 | mustUseEvex | regAnalysis.highVecUsed)) out->remove(Features::kAVX512_F, Features::kAVX512_BW, Features::kAVX512_DQ, Features::kAVX512_VL); else out->remove(Features::kAVX, Features::kAVX2, Features::kFMA, Features::kF16C); } } + // Handle AVX_VNNI vs AVX512_VNNI overlap. + if (out->has(Features::kAVX512_VNNI)) { + // By default the AVX512_VNNI instruction should be used, because it was + // introduced first. However, VEX|VEX3 prefix can be used to force AVX_VNNI + // instead. + uint32_t usesAvx512 = InstInternal_usesAvx512(options, inst.extraReg(), regAnalysis); + + if (!usesAvx512 && (options & (Inst::kOptionVex | Inst::kOptionVex3)) != 0) + out->remove(Features::kAVX512_VNNI, Features::kAVX512_VL); + else + out->remove(Features::kAVX_VNNI); + } + // Clear AVX512_VL if ZMM register is used. if (regAnalysis.hasRegType(Reg::kTypeZmm)) out->remove(Features::kAVX512_VL); diff --git a/src/asmjit/x86/x86instdb.cpp b/src/asmjit/x86/x86instdb.cpp index 911682b..861ba1f 100644 --- a/src/asmjit/x86/x86instdb.cpp +++ b/src/asmjit/x86/x86instdb.cpp @@ -101,26 +101,26 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Aas , X86Op_xAX , O(000000,3F,_,_,_,_,_,_ ), 0 , 0 , 0 , 13 , 1 , 1 ), // #4 INST(Adc , X86Arith , O(000000,10,2,_,x,_,_,_ ), 0 , 1 , 0 , 17 , 3 , 2 ), // #5 INST(Adcx , X86Rm , O(660F38,F6,_,_,x,_,_,_ ), 0 , 2 , 0 , 21 , 4 , 3 ), // #6 - INST(Add , X86Arith , O(000000,00,0,_,x,_,_,_ ), 0 , 0 , 0 , 3112 , 3 , 1 ), // #7 - INST(Addpd , ExtRm , O(660F00,58,_,_,_,_,_,_ ), 0 , 3 , 0 , 5102 , 5 , 4 ), // #8 - INST(Addps , ExtRm , O(000F00,58,_,_,_,_,_,_ ), 0 , 4 , 0 , 5114 , 5 , 5 ), // #9 - INST(Addsd , ExtRm , O(F20F00,58,_,_,_,_,_,_ ), 0 , 5 , 0 , 5336 , 6 , 4 ), // #10 - INST(Addss , ExtRm , O(F30F00,58,_,_,_,_,_,_ ), 0 , 6 , 0 , 3243 , 7 , 5 ), // #11 - INST(Addsubpd , ExtRm , O(660F00,D0,_,_,_,_,_,_ ), 0 , 3 , 0 , 4841 , 5 , 6 ), // #12 - INST(Addsubps , ExtRm , O(F20F00,D0,_,_,_,_,_,_ ), 0 , 5 , 0 , 4853 , 5 , 6 ), // #13 + INST(Add , X86Arith , O(000000,00,0,_,x,_,_,_ ), 0 , 0 , 0 , 3119 , 3 , 1 ), // #7 + INST(Addpd , ExtRm , O(660F00,58,_,_,_,_,_,_ ), 0 , 3 , 0 , 5109 , 5 , 4 ), // #8 + INST(Addps , ExtRm , O(000F00,58,_,_,_,_,_,_ ), 0 , 4 , 0 , 5121 , 5 , 5 ), // #9 + INST(Addsd , ExtRm , O(F20F00,58,_,_,_,_,_,_ ), 0 , 5 , 0 , 5343 , 6 , 4 ), // #10 + INST(Addss , ExtRm , O(F30F00,58,_,_,_,_,_,_ ), 0 , 6 , 0 , 3250 , 7 , 5 ), // #11 + INST(Addsubpd , ExtRm , O(660F00,D0,_,_,_,_,_,_ ), 0 , 3 , 0 , 4848 , 5 , 6 ), // #12 + INST(Addsubps , ExtRm , O(F20F00,D0,_,_,_,_,_,_ ), 0 , 5 , 0 , 4860 , 5 , 6 ), // #13 INST(Adox , X86Rm , O(F30F38,F6,_,_,x,_,_,_ ), 0 , 7 , 0 , 26 , 4 , 7 ), // #14 - INST(Aesdec , ExtRm , O(660F38,DE,_,_,_,_,_,_ ), 0 , 2 , 0 , 3298 , 5 , 8 ), // #15 - INST(Aesdeclast , ExtRm , O(660F38,DF,_,_,_,_,_,_ ), 0 , 2 , 0 , 3306 , 5 , 8 ), // #16 - INST(Aesenc , ExtRm , O(660F38,DC,_,_,_,_,_,_ ), 0 , 2 , 0 , 3318 , 5 , 8 ), // #17 - INST(Aesenclast , ExtRm , O(660F38,DD,_,_,_,_,_,_ ), 0 , 2 , 0 , 3326 , 5 , 8 ), // #18 - INST(Aesimc , ExtRm , O(660F38,DB,_,_,_,_,_,_ ), 0 , 2 , 0 , 3338 , 5 , 8 ), // #19 - INST(Aeskeygenassist , ExtRmi , O(660F3A,DF,_,_,_,_,_,_ ), 0 , 8 , 0 , 3346 , 8 , 8 ), // #20 - INST(And , X86Arith , O(000000,20,4,_,x,_,_,_ ), 0 , 9 , 0 , 2510 , 9 , 1 ), // #21 - INST(Andn , VexRvm_Wx , V(000F38,F2,_,0,x,_,_,_ ), 0 , 10 , 0 , 6810 , 10 , 9 ), // #22 - INST(Andnpd , ExtRm , O(660F00,55,_,_,_,_,_,_ ), 0 , 3 , 0 , 3379 , 5 , 4 ), // #23 - INST(Andnps , ExtRm , O(000F00,55,_,_,_,_,_,_ ), 0 , 4 , 0 , 3387 , 5 , 5 ), // #24 - INST(Andpd , ExtRm , O(660F00,54,_,_,_,_,_,_ ), 0 , 3 , 0 , 4355 , 11 , 4 ), // #25 - INST(Andps , ExtRm , O(000F00,54,_,_,_,_,_,_ ), 0 , 4 , 0 , 4365 , 11 , 5 ), // #26 + INST(Aesdec , ExtRm , O(660F38,DE,_,_,_,_,_,_ ), 0 , 2 , 0 , 3305 , 5 , 8 ), // #15 + INST(Aesdeclast , ExtRm , O(660F38,DF,_,_,_,_,_,_ ), 0 , 2 , 0 , 3313 , 5 , 8 ), // #16 + INST(Aesenc , ExtRm , O(660F38,DC,_,_,_,_,_,_ ), 0 , 2 , 0 , 3325 , 5 , 8 ), // #17 + INST(Aesenclast , ExtRm , O(660F38,DD,_,_,_,_,_,_ ), 0 , 2 , 0 , 3333 , 5 , 8 ), // #18 + INST(Aesimc , ExtRm , O(660F38,DB,_,_,_,_,_,_ ), 0 , 2 , 0 , 3345 , 5 , 8 ), // #19 + INST(Aeskeygenassist , ExtRmi , O(660F3A,DF,_,_,_,_,_,_ ), 0 , 8 , 0 , 3353 , 8 , 8 ), // #20 + INST(And , X86Arith , O(000000,20,4,_,x,_,_,_ ), 0 , 9 , 0 , 2517 , 9 , 1 ), // #21 + INST(Andn , VexRvm_Wx , V(000F38,F2,_,0,x,_,_,_ ), 0 , 10 , 0 , 6817 , 10 , 9 ), // #22 + INST(Andnpd , ExtRm , O(660F00,55,_,_,_,_,_,_ ), 0 , 3 , 0 , 3386 , 5 , 4 ), // #23 + INST(Andnps , ExtRm , O(000F00,55,_,_,_,_,_,_ ), 0 , 4 , 0 , 3394 , 5 , 5 ), // #24 + INST(Andpd , ExtRm , O(660F00,54,_,_,_,_,_,_ ), 0 , 3 , 0 , 4362 , 11 , 4 ), // #25 + INST(Andps , ExtRm , O(000F00,54,_,_,_,_,_,_ ), 0 , 4 , 0 , 4372 , 11 , 5 ), // #26 INST(Arpl , X86Mr_NoSize , O(000000,63,_,_,_,_,_,_ ), 0 , 0 , 0 , 31 , 12 , 10 ), // #27 INST(Bextr , VexRmv_Wx , V(000F38,F7,_,0,x,_,_,_ ), 0 , 10 , 0 , 36 , 13 , 9 ), // #28 INST(Blcfill , VexVm_Wx , V(XOP_M9,01,1,0,x,_,_,_ ), 0 , 11 , 0 , 42 , 14 , 11 ), // #29 @@ -128,10 +128,10 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Blcic , VexVm_Wx , V(XOP_M9,01,5,0,x,_,_,_ ), 0 , 13 , 0 , 55 , 14 , 11 ), // #31 INST(Blcmsk , VexVm_Wx , V(XOP_M9,02,1,0,x,_,_,_ ), 0 , 11 , 0 , 61 , 14 , 11 ), // #32 INST(Blcs , VexVm_Wx , V(XOP_M9,01,3,0,x,_,_,_ ), 0 , 14 , 0 , 68 , 14 , 11 ), // #33 - INST(Blendpd , ExtRmi , O(660F3A,0D,_,_,_,_,_,_ ), 0 , 8 , 0 , 3465 , 8 , 12 ), // #34 - INST(Blendps , ExtRmi , O(660F3A,0C,_,_,_,_,_,_ ), 0 , 8 , 0 , 3474 , 8 , 12 ), // #35 - INST(Blendvpd , ExtRm_XMM0 , O(660F38,15,_,_,_,_,_,_ ), 0 , 2 , 0 , 3483 , 15 , 12 ), // #36 - INST(Blendvps , ExtRm_XMM0 , O(660F38,14,_,_,_,_,_,_ ), 0 , 2 , 0 , 3493 , 15 , 12 ), // #37 + INST(Blendpd , ExtRmi , O(660F3A,0D,_,_,_,_,_,_ ), 0 , 8 , 0 , 3472 , 8 , 12 ), // #34 + INST(Blendps , ExtRmi , O(660F3A,0C,_,_,_,_,_,_ ), 0 , 8 , 0 , 3481 , 8 , 12 ), // #35 + INST(Blendvpd , ExtRm_XMM0 , O(660F38,15,_,_,_,_,_,_ ), 0 , 2 , 0 , 3490 , 15 , 12 ), // #36 + INST(Blendvps , ExtRm_XMM0 , O(660F38,14,_,_,_,_,_,_ ), 0 , 2 , 0 , 3500 , 15 , 12 ), // #37 INST(Blsfill , VexVm_Wx , V(XOP_M9,01,2,0,x,_,_,_ ), 0 , 15 , 0 , 73 , 14 , 11 ), // #38 INST(Blsi , VexVm_Wx , V(000F38,F3,3,0,x,_,_,_ ), 0 , 16 , 0 , 81 , 14 , 9 ), // #39 INST(Blsic , VexVm_Wx , V(XOP_M9,01,6,0,x,_,_,_ ), 0 , 12 , 0 , 86 , 14 , 11 ), // #40 @@ -153,7 +153,7 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Btr , X86Bt , O(000F00,B3,_,_,x,_,_,_ ), O(000F00,BA,6,_,x,_,_,_ ), 4 , 4 , 176 , 25 , 14 ), // #56 INST(Bts , X86Bt , O(000F00,AB,_,_,x,_,_,_ ), O(000F00,BA,5,_,x,_,_,_ ), 4 , 5 , 180 , 25 , 14 ), // #57 INST(Bzhi , VexRmv_Wx , V(000F38,F5,_,0,x,_,_,_ ), 0 , 10 , 0 , 184 , 13 , 15 ), // #58 - INST(Call , X86Call , O(000000,FF,2,_,_,_,_,_ ), 0 , 1 , 0 , 3009 , 26 , 1 ), // #59 + INST(Call , X86Call , O(000000,FF,2,_,_,_,_,_ ), 0 , 1 , 0 , 3016 , 26 , 1 ), // #59 INST(Cbw , X86Op_xAX , O(660000,98,_,_,_,_,_,_ ), 0 , 19 , 0 , 189 , 27 , 0 ), // #60 INST(Cdq , X86Op_xDX_xAX , O(000000,99,_,_,_,_,_,_ ), 0 , 0 , 0 , 193 , 28 , 0 ), // #61 INST(Cdqe , X86Op_xAX , O(000000,98,_,_,1,_,_,_ ), 0 , 20 , 0 , 197 , 29 , 0 ), // #62 @@ -201,64 +201,64 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Cmovs , X86Rm , O(000F00,48,_,_,x,_,_,_ ), 0 , 4 , 0 , 433 , 22 , 35 ), // #104 INST(Cmovz , X86Rm , O(000F00,44,_,_,x,_,_,_ ), 0 , 4 , 0 , 439 , 22 , 30 ), // #105 INST(Cmp , X86Arith , O(000000,38,7,_,x,_,_,_ ), 0 , 26 , 0 , 445 , 34 , 1 ), // #106 - INST(Cmppd , ExtRmi , O(660F00,C2,_,_,_,_,_,_ ), 0 , 3 , 0 , 3719 , 8 , 4 ), // #107 - INST(Cmpps , ExtRmi , O(000F00,C2,_,_,_,_,_,_ ), 0 , 4 , 0 , 3726 , 8 , 5 ), // #108 + INST(Cmppd , ExtRmi , O(660F00,C2,_,_,_,_,_,_ ), 0 , 3 , 0 , 3726 , 8 , 4 ), // #107 + INST(Cmpps , ExtRmi , O(000F00,C2,_,_,_,_,_,_ ), 0 , 4 , 0 , 3733 , 8 , 5 ), // #108 INST(Cmps , X86StrMm , O(000000,A6,_,_,_,_,_,_ ), 0 , 0 , 0 , 449 , 35 , 36 ), // #109 - INST(Cmpsd , ExtRmi , O(F20F00,C2,_,_,_,_,_,_ ), 0 , 5 , 0 , 3733 , 36 , 4 ), // #110 - INST(Cmpss , ExtRmi , O(F30F00,C2,_,_,_,_,_,_ ), 0 , 6 , 0 , 3740 , 37 , 5 ), // #111 + INST(Cmpsd , ExtRmi , O(F20F00,C2,_,_,_,_,_,_ ), 0 , 5 , 0 , 3740 , 36 , 4 ), // #110 + INST(Cmpss , ExtRmi , O(F30F00,C2,_,_,_,_,_,_ ), 0 , 6 , 0 , 3747 , 37 , 5 ), // #111 INST(Cmpxchg , X86Cmpxchg , O(000F00,B0,_,_,x,_,_,_ ), 0 , 4 , 0 , 454 , 38 , 37 ), // #112 INST(Cmpxchg16b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,1,_,_,_ ), 0 , 27 , 0 , 462 , 39 , 38 ), // #113 INST(Cmpxchg8b , X86Cmpxchg8b_16b , O(000F00,C7,1,_,_,_,_,_ ), 0 , 28 , 0 , 473 , 40 , 39 ), // #114 - INST(Comisd , ExtRm , O(660F00,2F,_,_,_,_,_,_ ), 0 , 3 , 0 , 10246, 6 , 40 ), // #115 - INST(Comiss , ExtRm , O(000F00,2F,_,_,_,_,_,_ ), 0 , 4 , 0 , 10255, 7 , 41 ), // #116 + INST(Comisd , ExtRm , O(660F00,2F,_,_,_,_,_,_ ), 0 , 3 , 0 , 10253, 6 , 40 ), // #115 + INST(Comiss , ExtRm , O(000F00,2F,_,_,_,_,_,_ ), 0 , 4 , 0 , 10262, 7 , 41 ), // #116 INST(Cpuid , X86Op , O(000F00,A2,_,_,_,_,_,_ ), 0 , 4 , 0 , 483 , 41 , 42 ), // #117 INST(Cqo , X86Op_xDX_xAX , O(000000,99,_,_,1,_,_,_ ), 0 , 20 , 0 , 489 , 42 , 0 ), // #118 INST(Crc32 , X86Crc , O(F20F38,F0,_,_,x,_,_,_ ), 0 , 29 , 0 , 493 , 43 , 43 ), // #119 - INST(Cvtdq2pd , ExtRm , O(F30F00,E6,_,_,_,_,_,_ ), 0 , 6 , 0 , 3787 , 6 , 4 ), // #120 - INST(Cvtdq2ps , ExtRm , O(000F00,5B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3797 , 5 , 4 ), // #121 - INST(Cvtpd2dq , ExtRm , O(F20F00,E6,_,_,_,_,_,_ ), 0 , 5 , 0 , 3836 , 5 , 4 ), // #122 + INST(Cvtdq2pd , ExtRm , O(F30F00,E6,_,_,_,_,_,_ ), 0 , 6 , 0 , 3794 , 6 , 4 ), // #120 + INST(Cvtdq2ps , ExtRm , O(000F00,5B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3804 , 5 , 4 ), // #121 + INST(Cvtpd2dq , ExtRm , O(F20F00,E6,_,_,_,_,_,_ ), 0 , 5 , 0 , 3843 , 5 , 4 ), // #122 INST(Cvtpd2pi , ExtRm , O(660F00,2D,_,_,_,_,_,_ ), 0 , 3 , 0 , 499 , 44 , 4 ), // #123 - INST(Cvtpd2ps , ExtRm , O(660F00,5A,_,_,_,_,_,_ ), 0 , 3 , 0 , 3846 , 5 , 4 ), // #124 + INST(Cvtpd2ps , ExtRm , O(660F00,5A,_,_,_,_,_,_ ), 0 , 3 , 0 , 3853 , 5 , 4 ), // #124 INST(Cvtpi2pd , ExtRm , O(660F00,2A,_,_,_,_,_,_ ), 0 , 3 , 0 , 508 , 45 , 4 ), // #125 INST(Cvtpi2ps , ExtRm , O(000F00,2A,_,_,_,_,_,_ ), 0 , 4 , 0 , 517 , 45 , 5 ), // #126 - INST(Cvtps2dq , ExtRm , O(660F00,5B,_,_,_,_,_,_ ), 0 , 3 , 0 , 3898 , 5 , 4 ), // #127 - INST(Cvtps2pd , ExtRm , O(000F00,5A,_,_,_,_,_,_ ), 0 , 4 , 0 , 3908 , 6 , 4 ), // #128 + INST(Cvtps2dq , ExtRm , O(660F00,5B,_,_,_,_,_,_ ), 0 , 3 , 0 , 3905 , 5 , 4 ), // #127 + INST(Cvtps2pd , ExtRm , O(000F00,5A,_,_,_,_,_,_ ), 0 , 4 , 0 , 3915 , 6 , 4 ), // #128 INST(Cvtps2pi , ExtRm , O(000F00,2D,_,_,_,_,_,_ ), 0 , 4 , 0 , 526 , 46 , 5 ), // #129 - INST(Cvtsd2si , ExtRm_Wx , O(F20F00,2D,_,_,x,_,_,_ ), 0 , 5 , 0 , 3980 , 47 , 4 ), // #130 - INST(Cvtsd2ss , ExtRm , O(F20F00,5A,_,_,_,_,_,_ ), 0 , 5 , 0 , 3990 , 6 , 4 ), // #131 - INST(Cvtsi2sd , ExtRm_Wx , O(F20F00,2A,_,_,x,_,_,_ ), 0 , 5 , 0 , 4011 , 48 , 4 ), // #132 - INST(Cvtsi2ss , ExtRm_Wx , O(F30F00,2A,_,_,x,_,_,_ ), 0 , 6 , 0 , 4021 , 48 , 5 ), // #133 - INST(Cvtss2sd , ExtRm , O(F30F00,5A,_,_,_,_,_,_ ), 0 , 6 , 0 , 4031 , 7 , 4 ), // #134 - INST(Cvtss2si , ExtRm_Wx , O(F30F00,2D,_,_,x,_,_,_ ), 0 , 6 , 0 , 4041 , 49 , 5 ), // #135 - INST(Cvttpd2dq , ExtRm , O(660F00,E6,_,_,_,_,_,_ ), 0 , 3 , 0 , 4062 , 5 , 4 ), // #136 + INST(Cvtsd2si , ExtRm_Wx , O(F20F00,2D,_,_,x,_,_,_ ), 0 , 5 , 0 , 3987 , 47 , 4 ), // #130 + INST(Cvtsd2ss , ExtRm , O(F20F00,5A,_,_,_,_,_,_ ), 0 , 5 , 0 , 3997 , 6 , 4 ), // #131 + INST(Cvtsi2sd , ExtRm_Wx , O(F20F00,2A,_,_,x,_,_,_ ), 0 , 5 , 0 , 4018 , 48 , 4 ), // #132 + INST(Cvtsi2ss , ExtRm_Wx , O(F30F00,2A,_,_,x,_,_,_ ), 0 , 6 , 0 , 4028 , 48 , 5 ), // #133 + INST(Cvtss2sd , ExtRm , O(F30F00,5A,_,_,_,_,_,_ ), 0 , 6 , 0 , 4038 , 7 , 4 ), // #134 + INST(Cvtss2si , ExtRm_Wx , O(F30F00,2D,_,_,x,_,_,_ ), 0 , 6 , 0 , 4048 , 49 , 5 ), // #135 + INST(Cvttpd2dq , ExtRm , O(660F00,E6,_,_,_,_,_,_ ), 0 , 3 , 0 , 4069 , 5 , 4 ), // #136 INST(Cvttpd2pi , ExtRm , O(660F00,2C,_,_,_,_,_,_ ), 0 , 3 , 0 , 535 , 44 , 4 ), // #137 - INST(Cvttps2dq , ExtRm , O(F30F00,5B,_,_,_,_,_,_ ), 0 , 6 , 0 , 4108 , 5 , 4 ), // #138 + INST(Cvttps2dq , ExtRm , O(F30F00,5B,_,_,_,_,_,_ ), 0 , 6 , 0 , 4115 , 5 , 4 ), // #138 INST(Cvttps2pi , ExtRm , O(000F00,2C,_,_,_,_,_,_ ), 0 , 4 , 0 , 545 , 46 , 5 ), // #139 - INST(Cvttsd2si , ExtRm_Wx , O(F20F00,2C,_,_,x,_,_,_ ), 0 , 5 , 0 , 4154 , 47 , 4 ), // #140 - INST(Cvttss2si , ExtRm_Wx , O(F30F00,2C,_,_,x,_,_,_ ), 0 , 6 , 0 , 4177 , 49 , 5 ), // #141 + INST(Cvttsd2si , ExtRm_Wx , O(F20F00,2C,_,_,x,_,_,_ ), 0 , 5 , 0 , 4161 , 47 , 4 ), // #140 + INST(Cvttss2si , ExtRm_Wx , O(F30F00,2C,_,_,x,_,_,_ ), 0 , 6 , 0 , 4184 , 49 , 5 ), // #141 INST(Cwd , X86Op_xDX_xAX , O(660000,99,_,_,_,_,_,_ ), 0 , 19 , 0 , 555 , 50 , 0 ), // #142 INST(Cwde , X86Op_xAX , O(000000,98,_,_,_,_,_,_ ), 0 , 0 , 0 , 559 , 51 , 0 ), // #143 INST(Daa , X86Op , O(000000,27,_,_,_,_,_,_ ), 0 , 0 , 0 , 564 , 1 , 1 ), // #144 INST(Das , X86Op , O(000000,2F,_,_,_,_,_,_ ), 0 , 0 , 0 , 568 , 1 , 1 ), // #145 - INST(Dec , X86IncDec , O(000000,FE,1,_,x,_,_,_ ), O(000000,48,_,_,x,_,_,_ ), 30 , 6 , 3301 , 52 , 44 ), // #146 + INST(Dec , X86IncDec , O(000000,FE,1,_,x,_,_,_ ), O(000000,48,_,_,x,_,_,_ ), 30 , 6 , 3308 , 52 , 44 ), // #146 INST(Div , X86M_GPB_MulDiv , O(000000,F6,6,_,x,_,_,_ ), 0 , 31 , 0 , 805 , 53 , 1 ), // #147 - INST(Divpd , ExtRm , O(660F00,5E,_,_,_,_,_,_ ), 0 , 3 , 0 , 4276 , 5 , 4 ), // #148 - INST(Divps , ExtRm , O(000F00,5E,_,_,_,_,_,_ ), 0 , 4 , 0 , 4283 , 5 , 5 ), // #149 - INST(Divsd , ExtRm , O(F20F00,5E,_,_,_,_,_,_ ), 0 , 5 , 0 , 4290 , 6 , 4 ), // #150 - INST(Divss , ExtRm , O(F30F00,5E,_,_,_,_,_,_ ), 0 , 6 , 0 , 4297 , 7 , 5 ), // #151 - INST(Dppd , ExtRmi , O(660F3A,41,_,_,_,_,_,_ ), 0 , 8 , 0 , 4314 , 8 , 12 ), // #152 - INST(Dpps , ExtRmi , O(660F3A,40,_,_,_,_,_,_ ), 0 , 8 , 0 , 4320 , 8 , 12 ), // #153 + INST(Divpd , ExtRm , O(660F00,5E,_,_,_,_,_,_ ), 0 , 3 , 0 , 4283 , 5 , 4 ), // #148 + INST(Divps , ExtRm , O(000F00,5E,_,_,_,_,_,_ ), 0 , 4 , 0 , 4290 , 5 , 5 ), // #149 + INST(Divsd , ExtRm , O(F20F00,5E,_,_,_,_,_,_ ), 0 , 5 , 0 , 4297 , 6 , 4 ), // #150 + INST(Divss , ExtRm , O(F30F00,5E,_,_,_,_,_,_ ), 0 , 6 , 0 , 4304 , 7 , 5 ), // #151 + INST(Dppd , ExtRmi , O(660F3A,41,_,_,_,_,_,_ ), 0 , 8 , 0 , 4321 , 8 , 12 ), // #152 + INST(Dpps , ExtRmi , O(660F3A,40,_,_,_,_,_,_ ), 0 , 8 , 0 , 4327 , 8 , 12 ), // #153 INST(Emms , X86Op , O(000F00,77,_,_,_,_,_,_ ), 0 , 4 , 0 , 773 , 54 , 45 ), // #154 INST(Endbr32 , X86Op_Mod11RM , O(F30F00,FB,7,_,_,_,_,3 ), 0 , 32 , 0 , 572 , 30 , 46 ), // #155 INST(Endbr64 , X86Op_Mod11RM , O(F30F00,FA,7,_,_,_,_,2 ), 0 , 33 , 0 , 580 , 30 , 46 ), // #156 INST(Enqcmd , X86EnqcmdMovdir64b , O(F20F38,F8,_,_,_,_,_,_ ), 0 , 29 , 0 , 588 , 55 , 47 ), // #157 INST(Enqcmds , X86EnqcmdMovdir64b , O(F30F38,F8,_,_,_,_,_,_ ), 0 , 7 , 0 , 595 , 55 , 47 ), // #158 - INST(Enter , X86Enter , O(000000,C8,_,_,_,_,_,_ ), 0 , 0 , 0 , 3017 , 56 , 0 ), // #159 - INST(Extractps , ExtExtract , O(660F3A,17,_,_,_,_,_,_ ), 0 , 8 , 0 , 4510 , 57 , 12 ), // #160 - INST(Extrq , ExtExtrq , O(660F00,79,_,_,_,_,_,_ ), O(660F00,78,0,_,_,_,_,_ ), 3 , 7 , 7606 , 58 , 48 ), // #161 + INST(Enter , X86Enter , O(000000,C8,_,_,_,_,_,_ ), 0 , 0 , 0 , 3024 , 56 , 0 ), // #159 + INST(Extractps , ExtExtract , O(660F3A,17,_,_,_,_,_,_ ), 0 , 8 , 0 , 4517 , 57 , 12 ), // #160 + INST(Extrq , ExtExtrq , O(660F00,79,_,_,_,_,_,_ ), O(660F00,78,0,_,_,_,_,_ ), 3 , 7 , 7613 , 58 , 48 ), // #161 INST(F2xm1 , FpuOp , O_FPU(00,D9F0,_) , 0 , 34 , 0 , 603 , 30 , 0 ), // #162 INST(Fabs , FpuOp , O_FPU(00,D9E1,_) , 0 , 34 , 0 , 609 , 30 , 0 ), // #163 - INST(Fadd , FpuArith , O_FPU(00,C0C0,0) , 0 , 35 , 0 , 2106 , 59 , 0 ), // #164 + INST(Fadd , FpuArith , O_FPU(00,C0C0,0) , 0 , 35 , 0 , 2113 , 59 , 0 ), // #164 INST(Faddp , FpuRDef , O_FPU(00,DEC0,_) , 0 , 36 , 0 , 614 , 60 , 0 ), // #165 INST(Fbld , X86M_Only , O_FPU(00,00DF,4) , 0 , 37 , 0 , 620 , 61 , 0 ), // #166 INST(Fbstp , X86M_Only , O_FPU(00,00DF,6) , 0 , 38 , 0 , 625 , 61 , 0 ), // #167 @@ -309,7 +309,7 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Fldln2 , FpuOp , O_FPU(00,D9ED,_) , 0 , 34 , 0 , 915 , 30 , 0 ), // #212 INST(Fldpi , FpuOp , O_FPU(00,D9EB,_) , 0 , 34 , 0 , 922 , 30 , 0 ), // #213 INST(Fldz , FpuOp , O_FPU(00,D9EE,_) , 0 , 34 , 0 , 928 , 30 , 0 ), // #214 - INST(Fmul , FpuArith , O_FPU(00,C8C8,1) , 0 , 54 , 0 , 2148 , 59 , 0 ), // #215 + INST(Fmul , FpuArith , O_FPU(00,C8C8,1) , 0 , 54 , 0 , 2155 , 59 , 0 ), // #215 INST(Fmulp , FpuRDef , O_FPU(00,DEC8,_) , 0 , 36 , 0 , 933 , 60 , 0 ), // #216 INST(Fnclex , FpuOp , O_FPU(00,DBE2,_) , 0 , 41 , 0 , 939 , 30 , 0 ), // #217 INST(Fninit , FpuOp , O_FPU(00,DBE3,_) , 0 , 41 , 0 , 946 , 30 , 0 ), // #218 @@ -334,9 +334,9 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Fstenv , X86M_Only , O_FPU(9B,00D9,6) , 0 , 55 , 0 , 1070 , 31 , 0 ), // #237 INST(Fstp , FpuFldFst , O_FPU(00,00D9,3) , O(000000,DB,7,_,_,_,_,_ ), 50 , 13 , 1077 , 66 , 0 ), // #238 INST(Fstsw , FpuStsw , O_FPU(9B,00DD,7) , O_FPU(9B,DFE0,_) , 56 , 14 , 1082 , 68 , 0 ), // #239 - INST(Fsub , FpuArith , O_FPU(00,E0E8,4) , 0 , 57 , 0 , 2226 , 59 , 0 ), // #240 + INST(Fsub , FpuArith , O_FPU(00,E0E8,4) , 0 , 57 , 0 , 2233 , 59 , 0 ), // #240 INST(Fsubp , FpuRDef , O_FPU(00,DEE8,_) , 0 , 36 , 0 , 1088 , 60 , 0 ), // #241 - INST(Fsubr , FpuArith , O_FPU(00,E8E0,5) , 0 , 58 , 0 , 2232 , 59 , 0 ), // #242 + INST(Fsubr , FpuArith , O_FPU(00,E8E0,5) , 0 , 58 , 0 , 2239 , 59 , 0 ), // #242 INST(Fsubrp , FpuRDef , O_FPU(00,DEE0,_) , 0 , 36 , 0 , 1094 , 60 , 0 ), // #243 INST(Ftst , FpuOp , O_FPU(00,D9E4,_) , 0 , 34 , 0 , 1101 , 30 , 0 ), // #244 INST(Fucom , FpuRDef , O_FPU(00,DDE0,_) , 0 , 47 , 0 , 1106 , 60 , 0 ), // #245 @@ -355,27 +355,27 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Fyl2x , FpuOp , O_FPU(00,D9F1,_) , 0 , 34 , 0 , 1200 , 30 , 0 ), // #258 INST(Fyl2xp1 , FpuOp , O_FPU(00,D9F9,_) , 0 , 34 , 0 , 1206 , 30 , 0 ), // #259 INST(Getsec , X86Op , O(000F00,37,_,_,_,_,_,_ ), 0 , 4 , 0 , 1214 , 30 , 52 ), // #260 - INST(Gf2p8affineinvqb , ExtRmi , O(660F3A,CF,_,_,_,_,_,_ ), 0 , 8 , 0 , 5865 , 8 , 53 ), // #261 - INST(Gf2p8affineqb , ExtRmi , O(660F3A,CE,_,_,_,_,_,_ ), 0 , 8 , 0 , 5883 , 8 , 53 ), // #262 - INST(Gf2p8mulb , ExtRm , O(660F38,CF,_,_,_,_,_,_ ), 0 , 2 , 0 , 5898 , 5 , 53 ), // #263 - INST(Haddpd , ExtRm , O(660F00,7C,_,_,_,_,_,_ ), 0 , 3 , 0 , 5909 , 5 , 6 ), // #264 - INST(Haddps , ExtRm , O(F20F00,7C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5917 , 5 , 6 ), // #265 + INST(Gf2p8affineinvqb , ExtRmi , O(660F3A,CF,_,_,_,_,_,_ ), 0 , 8 , 0 , 5872 , 8 , 53 ), // #261 + INST(Gf2p8affineqb , ExtRmi , O(660F3A,CE,_,_,_,_,_,_ ), 0 , 8 , 0 , 5890 , 8 , 53 ), // #262 + INST(Gf2p8mulb , ExtRm , O(660F38,CF,_,_,_,_,_,_ ), 0 , 2 , 0 , 5905 , 5 , 53 ), // #263 + INST(Haddpd , ExtRm , O(660F00,7C,_,_,_,_,_,_ ), 0 , 3 , 0 , 5916 , 5 , 6 ), // #264 + INST(Haddps , ExtRm , O(F20F00,7C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5924 , 5 , 6 ), // #265 INST(Hlt , X86Op , O(000000,F4,_,_,_,_,_,_ ), 0 , 0 , 0 , 1221 , 30 , 0 ), // #266 - INST(Hsubpd , ExtRm , O(660F00,7D,_,_,_,_,_,_ ), 0 , 3 , 0 , 5925 , 5 , 6 ), // #267 - INST(Hsubps , ExtRm , O(F20F00,7D,_,_,_,_,_,_ ), 0 , 5 , 0 , 5933 , 5 , 6 ), // #268 + INST(Hsubpd , ExtRm , O(660F00,7D,_,_,_,_,_,_ ), 0 , 3 , 0 , 5932 , 5 , 6 ), // #267 + INST(Hsubps , ExtRm , O(F20F00,7D,_,_,_,_,_,_ ), 0 , 5 , 0 , 5940 , 5 , 6 ), // #268 INST(Idiv , X86M_GPB_MulDiv , O(000000,F6,7,_,x,_,_,_ ), 0 , 26 , 0 , 804 , 53 , 1 ), // #269 INST(Imul , X86Imul , O(000000,F6,5,_,x,_,_,_ ), 0 , 61 , 0 , 822 , 71 , 1 ), // #270 - INST(In , X86In , O(000000,EC,_,_,_,_,_,_ ), O(000000,E4,_,_,_,_,_,_ ), 0 , 15 , 10418, 72 , 0 ), // #271 + INST(In , X86In , O(000000,EC,_,_,_,_,_,_ ), O(000000,E4,_,_,_,_,_,_ ), 0 , 15 , 10425, 72 , 0 ), // #271 INST(Inc , X86IncDec , O(000000,FE,0,_,x,_,_,_ ), O(000000,40,_,_,x,_,_,_ ), 0 , 16 , 1225 , 52 , 44 ), // #272 INST(Incsspd , X86M , O(F30F00,AE,5,_,0,_,_,_ ), 0 , 62 , 0 , 1229 , 73 , 54 ), // #273 INST(Incsspq , X86M , O(F30F00,AE,5,_,1,_,_,_ ), 0 , 63 , 0 , 1237 , 74 , 54 ), // #274 INST(Ins , X86Ins , O(000000,6C,_,_,_,_,_,_ ), 0 , 0 , 0 , 1908 , 75 , 0 ), // #275 - INST(Insertps , ExtRmi , O(660F3A,21,_,_,_,_,_,_ ), 0 , 8 , 0 , 6069 , 37 , 12 ), // #276 + INST(Insertps , ExtRmi , O(660F3A,21,_,_,_,_,_,_ ), 0 , 8 , 0 , 6076 , 37 , 12 ), // #276 INST(Insertq , ExtInsertq , O(F20F00,79,_,_,_,_,_,_ ), O(F20F00,78,_,_,_,_,_,_ ), 5 , 17 , 1245 , 76 , 48 ), // #277 INST(Int , X86Int , O(000000,CD,_,_,_,_,_,_ ), 0 , 0 , 0 , 1017 , 77 , 0 ), // #278 INST(Int3 , X86Op , O(000000,CC,_,_,_,_,_,_ ), 0 , 0 , 0 , 1253 , 30 , 0 ), // #279 INST(Into , X86Op , O(000000,CE,_,_,_,_,_,_ ), 0 , 0 , 0 , 1258 , 78 , 55 ), // #280 - INST(Invd , X86Op , O(000F00,08,_,_,_,_,_,_ ), 0 , 4 , 0 , 10347, 30 , 42 ), // #281 + INST(Invd , X86Op , O(000F00,08,_,_,_,_,_,_ ), 0 , 4 , 0 , 10354, 30 , 42 ), // #281 INST(Invept , X86Rm_NoSize , O(660F38,80,_,_,_,_,_,_ ), 0 , 2 , 0 , 1263 , 79 , 56 ), // #282 INST(Invlpg , X86M_Only , O(000F00,01,7,_,_,_,_,_ ), 0 , 22 , 0 , 1270 , 31 , 42 ), // #283 INST(Invlpga , X86Op_xAddr , O(000F01,DF,_,_,_,_,_,_ ), 0 , 21 , 0 , 1277 , 80 , 22 ), // #284 @@ -430,8 +430,8 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Kandq , VexRvm , V(000F00,41,_,1,1,_,_,_ ), 0 , 66 , 0 , 1512 , 86 , 65 ), // #333 INST(Kandw , VexRvm , V(000F00,41,_,1,0,_,_,_ ), 0 , 67 , 0 , 1518 , 86 , 66 ), // #334 INST(Kmovb , VexKmov , V(660F00,90,_,0,0,_,_,_ ), V(660F00,92,_,0,0,_,_,_ ), 68 , 36 , 1524 , 87 , 64 ), // #335 - INST(Kmovd , VexKmov , V(660F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,0,_,_,_ ), 69 , 37 , 8086 , 88 , 65 ), // #336 - INST(Kmovq , VexKmov , V(000F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,1,_,_,_ ), 70 , 38 , 8097 , 89 , 65 ), // #337 + INST(Kmovd , VexKmov , V(660F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,0,_,_,_ ), 69 , 37 , 8093 , 88 , 65 ), // #336 + INST(Kmovq , VexKmov , V(000F00,90,_,0,1,_,_,_ ), V(F20F00,92,_,0,1,_,_,_ ), 70 , 38 , 8104 , 89 , 65 ), // #337 INST(Kmovw , VexKmov , V(000F00,90,_,0,0,_,_,_ ), V(000F00,92,_,0,0,_,_,_ ), 71 , 39 , 1530 , 90 , 66 ), // #338 INST(Knotb , VexRm , V(660F00,44,_,0,0,_,_,_ ), 0 , 68 , 0 , 1536 , 91 , 64 ), // #339 INST(Knotd , VexRm , V(660F00,44,_,0,1,_,_,_ ), 0 , 69 , 0 , 1542 , 91 , 65 ), // #340 @@ -470,8 +470,8 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Kxorw , VexRvm , V(000F00,47,_,1,0,_,_,_ ), 0 , 67 , 0 , 1789 , 86 , 66 ), // #373 INST(Lahf , X86Op , O(000000,9F,_,_,_,_,_,_ ), 0 , 0 , 0 , 1795 , 93 , 70 ), // #374 INST(Lar , X86Rm , O(000F00,02,_,_,_,_,_,_ ), 0 , 4 , 0 , 1800 , 94 , 10 ), // #375 - INST(Lddqu , ExtRm , O(F20F00,F0,_,_,_,_,_,_ ), 0 , 5 , 0 , 6079 , 95 , 6 ), // #376 - INST(Ldmxcsr , X86M_Only , O(000F00,AE,2,_,_,_,_,_ ), 0 , 74 , 0 , 6086 , 96 , 5 ), // #377 + INST(Lddqu , ExtRm , O(F20F00,F0,_,_,_,_,_,_ ), 0 , 5 , 0 , 6086 , 95 , 6 ), // #376 + INST(Ldmxcsr , X86M_Only , O(000F00,AE,2,_,_,_,_,_ ), 0 , 74 , 0 , 6093 , 96 , 5 ), // #377 INST(Lds , X86Rm , O(000000,C5,_,_,_,_,_,_ ), 0 , 0 , 0 , 1804 , 97 , 0 ), // #378 INST(Ldtilecfg , AmxCfg , V(000F38,49,_,0,0,_,_,_ ), 0 , 10 , 0 , 1808 , 98 , 71 ), // #379 INST(Lea , X86Lea , O(000000,8D,_,_,x,_,_,_ ), 0 , 0 , 0 , 1818 , 99 , 0 ), // #380 @@ -490,1158 +490,1159 @@ const InstDB::InstInfo InstDB::_instInfoTable[] = { INST(Loope , X86JecxzLoop , 0 , O(000000,E1,_,_,_,_,_,_ ), 0 , 41 , 1884 , 104, 59 ), // #393 INST(Loopne , X86JecxzLoop , 0 , O(000000,E0,_,_,_,_,_,_ ), 0 , 42 , 1890 , 104, 59 ), // #394 INST(Lsl , X86Rm , O(000F00,03,_,_,_,_,_,_ ), 0 , 4 , 0 , 1897 , 105, 10 ), // #395 - INST(Lss , X86Rm , O(000F00,B2,_,_,_,_,_,_ ), 0 , 4 , 0 , 6577 , 100, 0 ), // #396 + INST(Lss , X86Rm , O(000F00,B2,_,_,_,_,_,_ ), 0 , 4 , 0 , 6584 , 100, 0 ), // #396 INST(Ltr , X86M_NoSize , O(000F00,00,3,_,_,_,_,_ ), 0 , 76 , 0 , 1901 , 101, 0 ), // #397 INST(Lwpins , VexVmi4_Wx , V(XOP_MA,12,0,0,x,_,_,_ ), 0 , 79 , 0 , 1905 , 106, 72 ), // #398 INST(Lwpval , VexVmi4_Wx , V(XOP_MA,12,1,0,x,_,_,_ ), 0 , 80 , 0 , 1912 , 106, 72 ), // #399 INST(Lzcnt , X86Rm_Raw66H , O(F30F00,BD,_,_,x,_,_,_ ), 0 , 6 , 0 , 1919 , 22 , 74 ), // #400 - INST(Maskmovdqu , ExtRm_ZDI , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 6095 , 107, 4 ), // #401 - INST(Maskmovq , ExtRm_ZDI , O(000F00,F7,_,_,_,_,_,_ ), 0 , 4 , 0 , 8094 , 108, 75 ), // #402 - INST(Maxpd , ExtRm , O(660F00,5F,_,_,_,_,_,_ ), 0 , 3 , 0 , 6129 , 5 , 4 ), // #403 - INST(Maxps , ExtRm , O(000F00,5F,_,_,_,_,_,_ ), 0 , 4 , 0 , 6136 , 5 , 5 ), // #404 - INST(Maxsd , ExtRm , O(F20F00,5F,_,_,_,_,_,_ ), 0 , 5 , 0 , 8113 , 6 , 4 ), // #405 - INST(Maxss , ExtRm , O(F30F00,5F,_,_,_,_,_,_ ), 0 , 6 , 0 , 6150 , 7 , 5 ), // #406 + INST(Maskmovdqu , ExtRm_ZDI , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 6102 , 107, 4 ), // #401 + INST(Maskmovq , ExtRm_ZDI , O(000F00,F7,_,_,_,_,_,_ ), 0 , 4 , 0 , 8101 , 108, 75 ), // #402 + INST(Maxpd , ExtRm , O(660F00,5F,_,_,_,_,_,_ ), 0 , 3 , 0 , 6136 , 5 , 4 ), // #403 + INST(Maxps , ExtRm , O(000F00,5F,_,_,_,_,_,_ ), 0 , 4 , 0 , 6143 , 5 , 5 ), // #404 + INST(Maxsd , ExtRm , O(F20F00,5F,_,_,_,_,_,_ ), 0 , 5 , 0 , 8120 , 6 , 4 ), // #405 + INST(Maxss , ExtRm , O(F30F00,5F,_,_,_,_,_,_ ), 0 , 6 , 0 , 6157 , 7 , 5 ), // #406 INST(Mcommit , X86Op , O(F30F01,FA,_,_,_,_,_,_ ), 0 , 81 , 0 , 1925 , 30 , 76 ), // #407 INST(Mfence , X86Fence , O(000F00,AE,6,_,_,_,_,_ ), 0 , 78 , 0 , 1933 , 30 , 4 ), // #408 - INST(Minpd , ExtRm , O(660F00,5D,_,_,_,_,_,_ ), 0 , 3 , 0 , 6179 , 5 , 4 ), // #409 - INST(Minps , ExtRm , O(000F00,5D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6186 , 5 , 5 ), // #410 - INST(Minsd , ExtRm , O(F20F00,5D,_,_,_,_,_,_ ), 0 , 5 , 0 , 8177 , 6 , 4 ), // #411 - INST(Minss , ExtRm , O(F30F00,5D,_,_,_,_,_,_ ), 0 , 6 , 0 , 6200 , 7 , 5 ), // #412 - INST(Monitor , X86Op , O(000F01,C8,_,_,_,_,_,_ ), 0 , 21 , 0 , 3192 , 109, 77 ), // #413 + INST(Minpd , ExtRm , O(660F00,5D,_,_,_,_,_,_ ), 0 , 3 , 0 , 6186 , 5 , 4 ), // #409 + INST(Minps , ExtRm , O(000F00,5D,_,_,_,_,_,_ ), 0 , 4 , 0 , 6193 , 5 , 5 ), // #410 + INST(Minsd , ExtRm , O(F20F00,5D,_,_,_,_,_,_ ), 0 , 5 , 0 , 8184 , 6 , 4 ), // #411 + INST(Minss , ExtRm , O(F30F00,5D,_,_,_,_,_,_ ), 0 , 6 , 0 , 6207 , 7 , 5 ), // #412 + INST(Monitor , X86Op , O(000F01,C8,_,_,_,_,_,_ ), 0 , 21 , 0 , 3199 , 109, 77 ), // #413 INST(Monitorx , X86Op , O(000F01,FA,_,_,_,_,_,_ ), 0 , 21 , 0 , 1940 , 109, 78 ), // #414 INST(Mov , X86Mov , 0 , 0 , 0 , 0 , 138 , 110, 0 ), // #415 - INST(Movapd , ExtMov , O(660F00,28,_,_,_,_,_,_ ), O(660F00,29,_,_,_,_,_,_ ), 3 , 43 , 6231 , 111, 4 ), // #416 - INST(Movaps , ExtMov , O(000F00,28,_,_,_,_,_,_ ), O(000F00,29,_,_,_,_,_,_ ), 4 , 44 , 6239 , 111, 5 ), // #417 - INST(Movbe , ExtMovbe , O(000F38,F0,_,_,x,_,_,_ ), O(000F38,F1,_,_,x,_,_,_ ), 82 , 45 , 651 , 112, 79 ), // #418 - INST(Movd , ExtMovd , O(000F00,6E,_,_,_,_,_,_ ), O(000F00,7E,_,_,_,_,_,_ ), 4 , 46 , 8087 , 113, 80 ), // #419 - INST(Movddup , ExtMov , O(F20F00,12,_,_,_,_,_,_ ), 0 , 5 , 0 , 6253 , 6 , 6 ), // #420 - INST(Movdir64b , X86EnqcmdMovdir64b , O(660F38,F8,_,_,_,_,_,_ ), 0 , 2 , 0 , 1949 , 114, 81 ), // #421 - INST(Movdiri , X86MovntiMovdiri , O(000F38,F9,_,_,_,_,_,_ ), 0 , 82 , 0 , 1959 , 115, 82 ), // #422 - INST(Movdq2q , ExtMov , O(F20F00,D6,_,_,_,_,_,_ ), 0 , 5 , 0 , 1967 , 116, 4 ), // #423 - INST(Movdqa , ExtMov , O(660F00,6F,_,_,_,_,_,_ ), O(660F00,7F,_,_,_,_,_,_ ), 3 , 47 , 6262 , 111, 4 ), // #424 - INST(Movdqu , ExtMov , O(F30F00,6F,_,_,_,_,_,_ ), O(F30F00,7F,_,_,_,_,_,_ ), 6 , 48 , 6099 , 111, 4 ), // #425 - INST(Movhlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), 0 , 4 , 0 , 6337 , 117, 5 ), // #426 - INST(Movhpd , ExtMov , O(660F00,16,_,_,_,_,_,_ ), O(660F00,17,_,_,_,_,_,_ ), 3 , 49 , 6346 , 118, 4 ), // #427 - INST(Movhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), O(000F00,17,_,_,_,_,_,_ ), 4 , 50 , 6354 , 118, 5 ), // #428 - INST(Movlhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), 0 , 4 , 0 , 6362 , 117, 5 ), // #429 - INST(Movlpd , ExtMov , O(660F00,12,_,_,_,_,_,_ ), O(660F00,13,_,_,_,_,_,_ ), 3 , 51 , 6371 , 118, 4 ), // #430 - INST(Movlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), O(000F00,13,_,_,_,_,_,_ ), 4 , 52 , 6379 , 118, 5 ), // #431 - INST(Movmskpd , ExtMov , O(660F00,50,_,_,_,_,_,_ ), 0 , 3 , 0 , 6387 , 119, 4 ), // #432 - INST(Movmskps , ExtMov , O(000F00,50,_,_,_,_,_,_ ), 0 , 4 , 0 , 6397 , 119, 5 ), // #433 - INST(Movntdq , ExtMov , 0 , O(660F00,E7,_,_,_,_,_,_ ), 0 , 53 , 6407 , 120, 4 ), // #434 - INST(Movntdqa , ExtMov , O(660F38,2A,_,_,_,_,_,_ ), 0 , 2 , 0 , 6416 , 95 , 12 ), // #435 - INST(Movnti , X86MovntiMovdiri , O(000F00,C3,_,_,x,_,_,_ ), 0 , 4 , 0 , 1975 , 115, 4 ), // #436 - INST(Movntpd , ExtMov , 0 , O(660F00,2B,_,_,_,_,_,_ ), 0 , 54 , 6426 , 120, 4 ), // #437 - INST(Movntps , ExtMov , 0 , O(000F00,2B,_,_,_,_,_,_ ), 0 , 55 , 6435 , 120, 5 ), // #438 - INST(Movntq , ExtMov , 0 , O(000F00,E7,_,_,_,_,_,_ ), 0 , 56 , 1982 , 121, 75 ), // #439 - INST(Movntsd , ExtMov , 0 , O(F20F00,2B,_,_,_,_,_,_ ), 0 , 57 , 1989 , 122, 48 ), // #440 - INST(Movntss , ExtMov , 0 , O(F30F00,2B,_,_,_,_,_,_ ), 0 , 58 , 1997 , 123, 48 ), // #441 - INST(Movq , ExtMovq , O(000F00,6E,_,_,x,_,_,_ ), O(000F00,7E,_,_,x,_,_,_ ), 4 , 59 , 8098 , 124, 80 ), // #442 - INST(Movq2dq , ExtRm , O(F30F00,D6,_,_,_,_,_,_ ), 0 , 6 , 0 , 2005 , 125, 4 ), // #443 - INST(Movs , X86StrMm , O(000000,A4,_,_,_,_,_,_ ), 0 , 0 , 0 , 434 , 126, 73 ), // #444 - INST(Movsd , ExtMov , O(F20F00,10,_,_,_,_,_,_ ), O(F20F00,11,_,_,_,_,_,_ ), 5 , 60 , 6450 , 127, 4 ), // #445 - INST(Movshdup , ExtRm , O(F30F00,16,_,_,_,_,_,_ ), 0 , 6 , 0 , 6457 , 5 , 6 ), // #446 - INST(Movsldup , ExtRm , O(F30F00,12,_,_,_,_,_,_ ), 0 , 6 , 0 , 6467 , 5 , 6 ), // #447 - INST(Movss , ExtMov , O(F30F00,10,_,_,_,_,_,_ ), O(F30F00,11,_,_,_,_,_,_ ), 6 , 61 , 6477 , 128, 5 ), // #448 - INST(Movsx , X86MovsxMovzx , O(000F00,BE,_,_,x,_,_,_ ), 0 , 4 , 0 , 2013 , 129, 0 ), // #449 - INST(Movsxd , X86Rm , O(000000,63,_,_,x,_,_,_ ), 0 , 0 , 0 , 2019 , 130, 0 ), // #450 - INST(Movupd , ExtMov , O(660F00,10,_,_,_,_,_,_ ), O(660F00,11,_,_,_,_,_,_ ), 3 , 62 , 6484 , 111, 4 ), // #451 - INST(Movups , ExtMov , O(000F00,10,_,_,_,_,_,_ ), O(000F00,11,_,_,_,_,_,_ ), 4 , 63 , 6492 , 111, 5 ), // #452 - INST(Movzx , X86MovsxMovzx , O(000F00,B6,_,_,x,_,_,_ ), 0 , 4 , 0 , 2026 , 129, 0 ), // #453 - INST(Mpsadbw , ExtRmi , O(660F3A,42,_,_,_,_,_,_ ), 0 , 8 , 0 , 6500 , 8 , 12 ), // #454 - INST(Mul , X86M_GPB_MulDiv , O(000000,F6,4,_,x,_,_,_ ), 0 , 9 , 0 , 823 , 53 , 1 ), // #455 - INST(Mulpd , ExtRm , O(660F00,59,_,_,_,_,_,_ ), 0 , 3 , 0 , 6554 , 5 , 4 ), // #456 - INST(Mulps , ExtRm , O(000F00,59,_,_,_,_,_,_ ), 0 , 4 , 0 , 6561 , 5 , 5 ), // #457 - INST(Mulsd , ExtRm , O(F20F00,59,_,_,_,_,_,_ ), 0 , 5 , 0 , 6568 , 6 , 4 ), // #458 - INST(Mulss , ExtRm , O(F30F00,59,_,_,_,_,_,_ ), 0 , 6 , 0 , 6575 , 7 , 5 ), // #459 - INST(Mulx , VexRvm_ZDX_Wx , V(F20F38,F6,_,0,x,_,_,_ ), 0 , 83 , 0 , 2032 , 131, 83 ), // #460 - INST(Mwait , X86Op , O(000F01,C9,_,_,_,_,_,_ ), 0 , 21 , 0 , 3201 , 132, 77 ), // #461 - INST(Mwaitx , X86Op , O(000F01,FB,_,_,_,_,_,_ ), 0 , 21 , 0 , 2037 , 133, 78 ), // #462 - INST(Neg , X86M_GPB , O(000000,F6,3,_,x,_,_,_ ), 0 , 84 , 0 , 2044 , 134, 1 ), // #463 - INST(Nop , X86M_Nop , O(000000,90,_,_,_,_,_,_ ), 0 , 0 , 0 , 954 , 135, 0 ), // #464 - INST(Not , X86M_GPB , O(000000,F6,2,_,x,_,_,_ ), 0 , 1 , 0 , 2048 , 134, 0 ), // #465 - INST(Or , X86Arith , O(000000,08,1,_,x,_,_,_ ), 0 , 30 , 0 , 3197 , 136, 1 ), // #466 - INST(Orpd , ExtRm , O(660F00,56,_,_,_,_,_,_ ), 0 , 3 , 0 , 10304, 11 , 4 ), // #467 - INST(Orps , ExtRm , O(000F00,56,_,_,_,_,_,_ ), 0 , 4 , 0 , 10311, 11 , 5 ), // #468 - INST(Out , X86Out , O(000000,EE,_,_,_,_,_,_ ), O(000000,E6,_,_,_,_,_,_ ), 0 , 64 , 2052 , 137, 0 ), // #469 - INST(Outs , X86Outs , O(000000,6E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2056 , 138, 0 ), // #470 - INST(Pabsb , ExtRm_P , O(000F38,1C,_,_,_,_,_,_ ), 0 , 82 , 0 , 6657 , 139, 84 ), // #471 - INST(Pabsd , ExtRm_P , O(000F38,1E,_,_,_,_,_,_ ), 0 , 82 , 0 , 6664 , 139, 84 ), // #472 - INST(Pabsw , ExtRm_P , O(000F38,1D,_,_,_,_,_,_ ), 0 , 82 , 0 , 6678 , 139, 84 ), // #473 - INST(Packssdw , ExtRm_P , O(000F00,6B,_,_,_,_,_,_ ), 0 , 4 , 0 , 6685 , 139, 80 ), // #474 - INST(Packsswb , ExtRm_P , O(000F00,63,_,_,_,_,_,_ ), 0 , 4 , 0 , 6695 , 139, 80 ), // #475 - INST(Packusdw , ExtRm , O(660F38,2B,_,_,_,_,_,_ ), 0 , 2 , 0 , 6705 , 5 , 12 ), // #476 - INST(Packuswb , ExtRm_P , O(000F00,67,_,_,_,_,_,_ ), 0 , 4 , 0 , 6715 , 139, 80 ), // #477 - INST(Paddb , ExtRm_P , O(000F00,FC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6725 , 139, 80 ), // #478 - INST(Paddd , ExtRm_P , O(000F00,FE,_,_,_,_,_,_ ), 0 , 4 , 0 , 6732 , 139, 80 ), // #479 - INST(Paddq , ExtRm_P , O(000F00,D4,_,_,_,_,_,_ ), 0 , 4 , 0 , 6739 , 139, 4 ), // #480 - INST(Paddsb , ExtRm_P , O(000F00,EC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6746 , 139, 80 ), // #481 - INST(Paddsw , ExtRm_P , O(000F00,ED,_,_,_,_,_,_ ), 0 , 4 , 0 , 6754 , 139, 80 ), // #482 - INST(Paddusb , ExtRm_P , O(000F00,DC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6762 , 139, 80 ), // #483 - INST(Paddusw , ExtRm_P , O(000F00,DD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6771 , 139, 80 ), // #484 - INST(Paddw , ExtRm_P , O(000F00,FD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6780 , 139, 80 ), // #485 - INST(Palignr , ExtRmi_P , O(000F3A,0F,_,_,_,_,_,_ ), 0 , 85 , 0 , 6787 , 140, 6 ), // #486 - INST(Pand , ExtRm_P , O(000F00,DB,_,_,_,_,_,_ ), 0 , 4 , 0 , 6796 , 141, 80 ), // #487 - INST(Pandn , ExtRm_P , O(000F00,DF,_,_,_,_,_,_ ), 0 , 4 , 0 , 6809 , 142, 80 ), // #488 - INST(Pause , X86Op , O(F30000,90,_,_,_,_,_,_ ), 0 , 86 , 0 , 3161 , 30 , 0 ), // #489 - INST(Pavgb , ExtRm_P , O(000F00,E0,_,_,_,_,_,_ ), 0 , 4 , 0 , 6839 , 139, 85 ), // #490 - INST(Pavgusb , Ext3dNow , O(000F0F,BF,_,_,_,_,_,_ ), 0 , 87 , 0 , 2061 , 143, 50 ), // #491 - INST(Pavgw , ExtRm_P , O(000F00,E3,_,_,_,_,_,_ ), 0 , 4 , 0 , 6846 , 139, 85 ), // #492 - INST(Pblendvb , ExtRm_XMM0 , O(660F38,10,_,_,_,_,_,_ ), 0 , 2 , 0 , 6862 , 15 , 12 ), // #493 - INST(Pblendw , ExtRmi , O(660F3A,0E,_,_,_,_,_,_ ), 0 , 8 , 0 , 6872 , 8 , 12 ), // #494 - INST(Pclmulqdq , ExtRmi , O(660F3A,44,_,_,_,_,_,_ ), 0 , 8 , 0 , 6965 , 8 , 86 ), // #495 - INST(Pcmpeqb , ExtRm_P , O(000F00,74,_,_,_,_,_,_ ), 0 , 4 , 0 , 6997 , 142, 80 ), // #496 - INST(Pcmpeqd , ExtRm_P , O(000F00,76,_,_,_,_,_,_ ), 0 , 4 , 0 , 7006 , 142, 80 ), // #497 - INST(Pcmpeqq , ExtRm , O(660F38,29,_,_,_,_,_,_ ), 0 , 2 , 0 , 7015 , 144, 12 ), // #498 - INST(Pcmpeqw , ExtRm_P , O(000F00,75,_,_,_,_,_,_ ), 0 , 4 , 0 , 7024 , 142, 80 ), // #499 - INST(Pcmpestri , ExtRmi , O(660F3A,61,_,_,_,_,_,_ ), 0 , 8 , 0 , 7033 , 145, 87 ), // #500 - INST(Pcmpestrm , ExtRmi , O(660F3A,60,_,_,_,_,_,_ ), 0 , 8 , 0 , 7044 , 146, 87 ), // #501 - INST(Pcmpgtb , ExtRm_P , O(000F00,64,_,_,_,_,_,_ ), 0 , 4 , 0 , 7055 , 142, 80 ), // #502 - INST(Pcmpgtd , ExtRm_P , O(000F00,66,_,_,_,_,_,_ ), 0 , 4 , 0 , 7064 , 142, 80 ), // #503 - INST(Pcmpgtq , ExtRm , O(660F38,37,_,_,_,_,_,_ ), 0 , 2 , 0 , 7073 , 144, 43 ), // #504 - INST(Pcmpgtw , ExtRm_P , O(000F00,65,_,_,_,_,_,_ ), 0 , 4 , 0 , 7082 , 142, 80 ), // #505 - INST(Pcmpistri , ExtRmi , O(660F3A,63,_,_,_,_,_,_ ), 0 , 8 , 0 , 7091 , 147, 87 ), // #506 - INST(Pcmpistrm , ExtRmi , O(660F3A,62,_,_,_,_,_,_ ), 0 , 8 , 0 , 7102 , 148, 87 ), // #507 - INST(Pconfig , X86Op , O(000F01,C5,_,_,_,_,_,_ ), 0 , 21 , 0 , 2069 , 30 , 88 ), // #508 - INST(Pdep , VexRvm_Wx , V(F20F38,F5,_,0,x,_,_,_ ), 0 , 83 , 0 , 2077 , 10 , 83 ), // #509 - INST(Pext , VexRvm_Wx , V(F30F38,F5,_,0,x,_,_,_ ), 0 , 88 , 0 , 2082 , 10 , 83 ), // #510 - INST(Pextrb , ExtExtract , O(000F3A,14,_,_,_,_,_,_ ), 0 , 85 , 0 , 7589 , 149, 12 ), // #511 - INST(Pextrd , ExtExtract , O(000F3A,16,_,_,_,_,_,_ ), 0 , 85 , 0 , 7597 , 57 , 12 ), // #512 - INST(Pextrq , ExtExtract , O(000F3A,16,_,_,1,_,_,_ ), 0 , 89 , 0 , 7605 , 150, 12 ), // #513 - INST(Pextrw , ExtPextrw , O(000F00,C5,_,_,_,_,_,_ ), O(000F3A,15,_,_,_,_,_,_ ), 4 , 65 , 7613 , 151, 89 ), // #514 - INST(Pf2id , Ext3dNow , O(000F0F,1D,_,_,_,_,_,_ ), 0 , 87 , 0 , 2087 , 143, 50 ), // #515 - INST(Pf2iw , Ext3dNow , O(000F0F,1C,_,_,_,_,_,_ ), 0 , 87 , 0 , 2093 , 143, 90 ), // #516 - INST(Pfacc , Ext3dNow , O(000F0F,AE,_,_,_,_,_,_ ), 0 , 87 , 0 , 2099 , 143, 50 ), // #517 - INST(Pfadd , Ext3dNow , O(000F0F,9E,_,_,_,_,_,_ ), 0 , 87 , 0 , 2105 , 143, 50 ), // #518 - INST(Pfcmpeq , Ext3dNow , O(000F0F,B0,_,_,_,_,_,_ ), 0 , 87 , 0 , 2111 , 143, 50 ), // #519 - INST(Pfcmpge , Ext3dNow , O(000F0F,90,_,_,_,_,_,_ ), 0 , 87 , 0 , 2119 , 143, 50 ), // #520 - INST(Pfcmpgt , Ext3dNow , O(000F0F,A0,_,_,_,_,_,_ ), 0 , 87 , 0 , 2127 , 143, 50 ), // #521 - INST(Pfmax , Ext3dNow , O(000F0F,A4,_,_,_,_,_,_ ), 0 , 87 , 0 , 2135 , 143, 50 ), // #522 - INST(Pfmin , Ext3dNow , O(000F0F,94,_,_,_,_,_,_ ), 0 , 87 , 0 , 2141 , 143, 50 ), // #523 - INST(Pfmul , Ext3dNow , O(000F0F,B4,_,_,_,_,_,_ ), 0 , 87 , 0 , 2147 , 143, 50 ), // #524 - INST(Pfnacc , Ext3dNow , O(000F0F,8A,_,_,_,_,_,_ ), 0 , 87 , 0 , 2153 , 143, 90 ), // #525 - INST(Pfpnacc , Ext3dNow , O(000F0F,8E,_,_,_,_,_,_ ), 0 , 87 , 0 , 2160 , 143, 90 ), // #526 - INST(Pfrcp , Ext3dNow , O(000F0F,96,_,_,_,_,_,_ ), 0 , 87 , 0 , 2168 , 143, 50 ), // #527 - INST(Pfrcpit1 , Ext3dNow , O(000F0F,A6,_,_,_,_,_,_ ), 0 , 87 , 0 , 2174 , 143, 50 ), // #528 - INST(Pfrcpit2 , Ext3dNow , O(000F0F,B6,_,_,_,_,_,_ ), 0 , 87 , 0 , 2183 , 143, 50 ), // #529 - INST(Pfrcpv , Ext3dNow , O(000F0F,86,_,_,_,_,_,_ ), 0 , 87 , 0 , 2192 , 143, 91 ), // #530 - INST(Pfrsqit1 , Ext3dNow , O(000F0F,A7,_,_,_,_,_,_ ), 0 , 87 , 0 , 2199 , 143, 50 ), // #531 - INST(Pfrsqrt , Ext3dNow , O(000F0F,97,_,_,_,_,_,_ ), 0 , 87 , 0 , 2208 , 143, 50 ), // #532 - INST(Pfrsqrtv , Ext3dNow , O(000F0F,87,_,_,_,_,_,_ ), 0 , 87 , 0 , 2216 , 143, 91 ), // #533 - INST(Pfsub , Ext3dNow , O(000F0F,9A,_,_,_,_,_,_ ), 0 , 87 , 0 , 2225 , 143, 50 ), // #534 - INST(Pfsubr , Ext3dNow , O(000F0F,AA,_,_,_,_,_,_ ), 0 , 87 , 0 , 2231 , 143, 50 ), // #535 - INST(Phaddd , ExtRm_P , O(000F38,02,_,_,_,_,_,_ ), 0 , 82 , 0 , 7692 , 139, 84 ), // #536 - INST(Phaddsw , ExtRm_P , O(000F38,03,_,_,_,_,_,_ ), 0 , 82 , 0 , 7709 , 139, 84 ), // #537 - INST(Phaddw , ExtRm_P , O(000F38,01,_,_,_,_,_,_ ), 0 , 82 , 0 , 7778 , 139, 84 ), // #538 - INST(Phminposuw , ExtRm , O(660F38,41,_,_,_,_,_,_ ), 0 , 2 , 0 , 7804 , 5 , 12 ), // #539 - INST(Phsubd , ExtRm_P , O(000F38,06,_,_,_,_,_,_ ), 0 , 82 , 0 , 7825 , 139, 84 ), // #540 - INST(Phsubsw , ExtRm_P , O(000F38,07,_,_,_,_,_,_ ), 0 , 82 , 0 , 7842 , 139, 84 ), // #541 - INST(Phsubw , ExtRm_P , O(000F38,05,_,_,_,_,_,_ ), 0 , 82 , 0 , 7851 , 139, 84 ), // #542 - INST(Pi2fd , Ext3dNow , O(000F0F,0D,_,_,_,_,_,_ ), 0 , 87 , 0 , 2238 , 143, 50 ), // #543 - INST(Pi2fw , Ext3dNow , O(000F0F,0C,_,_,_,_,_,_ ), 0 , 87 , 0 , 2244 , 143, 90 ), // #544 - INST(Pinsrb , ExtRmi , O(660F3A,20,_,_,_,_,_,_ ), 0 , 8 , 0 , 7868 , 152, 12 ), // #545 - INST(Pinsrd , ExtRmi , O(660F3A,22,_,_,_,_,_,_ ), 0 , 8 , 0 , 7876 , 153, 12 ), // #546 - INST(Pinsrq , ExtRmi , O(660F3A,22,_,_,1,_,_,_ ), 0 , 90 , 0 , 7884 , 154, 12 ), // #547 - INST(Pinsrw , ExtRmi_P , O(000F00,C4,_,_,_,_,_,_ ), 0 , 4 , 0 , 7892 , 155, 85 ), // #548 - INST(Pmaddubsw , ExtRm_P , O(000F38,04,_,_,_,_,_,_ ), 0 , 82 , 0 , 8062 , 139, 84 ), // #549 - INST(Pmaddwd , ExtRm_P , O(000F00,F5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8073 , 139, 80 ), // #550 - INST(Pmaxsb , ExtRm , O(660F38,3C,_,_,_,_,_,_ ), 0 , 2 , 0 , 8104 , 11 , 12 ), // #551 - INST(Pmaxsd , ExtRm , O(660F38,3D,_,_,_,_,_,_ ), 0 , 2 , 0 , 8112 , 11 , 12 ), // #552 - INST(Pmaxsw , ExtRm_P , O(000F00,EE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8128 , 141, 85 ), // #553 - INST(Pmaxub , ExtRm_P , O(000F00,DE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8136 , 141, 85 ), // #554 - INST(Pmaxud , ExtRm , O(660F38,3F,_,_,_,_,_,_ ), 0 , 2 , 0 , 8144 , 11 , 12 ), // #555 - INST(Pmaxuw , ExtRm , O(660F38,3E,_,_,_,_,_,_ ), 0 , 2 , 0 , 8160 , 11 , 12 ), // #556 - INST(Pminsb , ExtRm , O(660F38,38,_,_,_,_,_,_ ), 0 , 2 , 0 , 8168 , 11 , 12 ), // #557 - INST(Pminsd , ExtRm , O(660F38,39,_,_,_,_,_,_ ), 0 , 2 , 0 , 8176 , 11 , 12 ), // #558 - INST(Pminsw , ExtRm_P , O(000F00,EA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8192 , 141, 85 ), // #559 - INST(Pminub , ExtRm_P , O(000F00,DA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8200 , 141, 85 ), // #560 - INST(Pminud , ExtRm , O(660F38,3B,_,_,_,_,_,_ ), 0 , 2 , 0 , 8208 , 11 , 12 ), // #561 - INST(Pminuw , ExtRm , O(660F38,3A,_,_,_,_,_,_ ), 0 , 2 , 0 , 8224 , 11 , 12 ), // #562 - INST(Pmovmskb , ExtRm_P , O(000F00,D7,_,_,_,_,_,_ ), 0 , 4 , 0 , 8302 , 156, 85 ), // #563 - INST(Pmovsxbd , ExtRm , O(660F38,21,_,_,_,_,_,_ ), 0 , 2 , 0 , 8399 , 7 , 12 ), // #564 - INST(Pmovsxbq , ExtRm , O(660F38,22,_,_,_,_,_,_ ), 0 , 2 , 0 , 8409 , 157, 12 ), // #565 - INST(Pmovsxbw , ExtRm , O(660F38,20,_,_,_,_,_,_ ), 0 , 2 , 0 , 8419 , 6 , 12 ), // #566 - INST(Pmovsxdq , ExtRm , O(660F38,25,_,_,_,_,_,_ ), 0 , 2 , 0 , 8429 , 6 , 12 ), // #567 - INST(Pmovsxwd , ExtRm , O(660F38,23,_,_,_,_,_,_ ), 0 , 2 , 0 , 8439 , 6 , 12 ), // #568 - INST(Pmovsxwq , ExtRm , O(660F38,24,_,_,_,_,_,_ ), 0 , 2 , 0 , 8449 , 7 , 12 ), // #569 - INST(Pmovzxbd , ExtRm , O(660F38,31,_,_,_,_,_,_ ), 0 , 2 , 0 , 8536 , 7 , 12 ), // #570 - INST(Pmovzxbq , ExtRm , O(660F38,32,_,_,_,_,_,_ ), 0 , 2 , 0 , 8546 , 157, 12 ), // #571 - INST(Pmovzxbw , ExtRm , O(660F38,30,_,_,_,_,_,_ ), 0 , 2 , 0 , 8556 , 6 , 12 ), // #572 - INST(Pmovzxdq , ExtRm , O(660F38,35,_,_,_,_,_,_ ), 0 , 2 , 0 , 8566 , 6 , 12 ), // #573 - INST(Pmovzxwd , ExtRm , O(660F38,33,_,_,_,_,_,_ ), 0 , 2 , 0 , 8576 , 6 , 12 ), // #574 - INST(Pmovzxwq , ExtRm , O(660F38,34,_,_,_,_,_,_ ), 0 , 2 , 0 , 8586 , 7 , 12 ), // #575 - INST(Pmuldq , ExtRm , O(660F38,28,_,_,_,_,_,_ ), 0 , 2 , 0 , 8596 , 5 , 12 ), // #576 - INST(Pmulhrsw , ExtRm_P , O(000F38,0B,_,_,_,_,_,_ ), 0 , 82 , 0 , 8604 , 139, 84 ), // #577 - INST(Pmulhrw , Ext3dNow , O(000F0F,B7,_,_,_,_,_,_ ), 0 , 87 , 0 , 2250 , 143, 50 ), // #578 - INST(Pmulhuw , ExtRm_P , O(000F00,E4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8614 , 139, 85 ), // #579 - INST(Pmulhw , ExtRm_P , O(000F00,E5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8623 , 139, 80 ), // #580 - INST(Pmulld , ExtRm , O(660F38,40,_,_,_,_,_,_ ), 0 , 2 , 0 , 8631 , 5 , 12 ), // #581 - INST(Pmullw , ExtRm_P , O(000F00,D5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8647 , 139, 80 ), // #582 - INST(Pmuludq , ExtRm_P , O(000F00,F4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8670 , 139, 4 ), // #583 - INST(Pop , X86Pop , O(000000,8F,0,_,_,_,_,_ ), O(000000,58,_,_,_,_,_,_ ), 0 , 66 , 2258 , 158, 0 ), // #584 - INST(Popa , X86Op , O(660000,61,_,_,_,_,_,_ ), 0 , 19 , 0 , 2262 , 78 , 0 ), // #585 - INST(Popad , X86Op , O(000000,61,_,_,_,_,_,_ ), 0 , 0 , 0 , 2267 , 78 , 0 ), // #586 - INST(Popcnt , X86Rm_Raw66H , O(F30F00,B8,_,_,x,_,_,_ ), 0 , 6 , 0 , 2273 , 22 , 92 ), // #587 - INST(Popf , X86Op , O(660000,9D,_,_,_,_,_,_ ), 0 , 19 , 0 , 2280 , 30 , 93 ), // #588 - INST(Popfd , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2285 , 78 , 93 ), // #589 - INST(Popfq , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2291 , 159, 93 ), // #590 - INST(Por , ExtRm_P , O(000F00,EB,_,_,_,_,_,_ ), 0 , 4 , 0 , 8715 , 141, 80 ), // #591 - INST(Prefetch , X86M_Only , O(000F00,0D,0,_,_,_,_,_ ), 0 , 4 , 0 , 2297 , 31 , 50 ), // #592 - INST(Prefetchnta , X86M_Only , O(000F00,18,0,_,_,_,_,_ ), 0 , 4 , 0 , 2306 , 31 , 75 ), // #593 - INST(Prefetcht0 , X86M_Only , O(000F00,18,1,_,_,_,_,_ ), 0 , 28 , 0 , 2318 , 31 , 75 ), // #594 - INST(Prefetcht1 , X86M_Only , O(000F00,18,2,_,_,_,_,_ ), 0 , 74 , 0 , 2329 , 31 , 75 ), // #595 - INST(Prefetcht2 , X86M_Only , O(000F00,18,3,_,_,_,_,_ ), 0 , 76 , 0 , 2340 , 31 , 75 ), // #596 - INST(Prefetchw , X86M_Only , O(000F00,0D,1,_,_,_,_,_ ), 0 , 28 , 0 , 2351 , 31 , 94 ), // #597 - INST(Prefetchwt1 , X86M_Only , O(000F00,0D,2,_,_,_,_,_ ), 0 , 74 , 0 , 2361 , 31 , 95 ), // #598 - INST(Psadbw , ExtRm_P , O(000F00,F6,_,_,_,_,_,_ ), 0 , 4 , 0 , 4268 , 139, 85 ), // #599 - INST(Pshufb , ExtRm_P , O(000F38,00,_,_,_,_,_,_ ), 0 , 82 , 0 , 9041 , 139, 84 ), // #600 - INST(Pshufd , ExtRmi , O(660F00,70,_,_,_,_,_,_ ), 0 , 3 , 0 , 9062 , 8 , 4 ), // #601 - INST(Pshufhw , ExtRmi , O(F30F00,70,_,_,_,_,_,_ ), 0 , 6 , 0 , 9070 , 8 , 4 ), // #602 - INST(Pshuflw , ExtRmi , O(F20F00,70,_,_,_,_,_,_ ), 0 , 5 , 0 , 9079 , 8 , 4 ), // #603 - INST(Pshufw , ExtRmi_P , O(000F00,70,_,_,_,_,_,_ ), 0 , 4 , 0 , 2373 , 160, 75 ), // #604 - INST(Psignb , ExtRm_P , O(000F38,08,_,_,_,_,_,_ ), 0 , 82 , 0 , 9088 , 139, 84 ), // #605 - INST(Psignd , ExtRm_P , O(000F38,0A,_,_,_,_,_,_ ), 0 , 82 , 0 , 9096 , 139, 84 ), // #606 - INST(Psignw , ExtRm_P , O(000F38,09,_,_,_,_,_,_ ), 0 , 82 , 0 , 9104 , 139, 84 ), // #607 - INST(Pslld , ExtRmRi_P , O(000F00,F2,_,_,_,_,_,_ ), O(000F00,72,6,_,_,_,_,_ ), 4 , 67 , 9112 , 161, 80 ), // #608 - INST(Pslldq , ExtRmRi , 0 , O(660F00,73,7,_,_,_,_,_ ), 0 , 68 , 9119 , 162, 4 ), // #609 - INST(Psllq , ExtRmRi_P , O(000F00,F3,_,_,_,_,_,_ ), O(000F00,73,6,_,_,_,_,_ ), 4 , 69 , 9127 , 161, 80 ), // #610 - INST(Psllw , ExtRmRi_P , O(000F00,F1,_,_,_,_,_,_ ), O(000F00,71,6,_,_,_,_,_ ), 4 , 70 , 9158 , 161, 80 ), // #611 - INST(Psmash , X86Op , O(F30F01,FF,_,_,_,_,_,_ ), 0 , 81 , 0 , 2380 , 159, 96 ), // #612 - INST(Psrad , ExtRmRi_P , O(000F00,E2,_,_,_,_,_,_ ), O(000F00,72,4,_,_,_,_,_ ), 4 , 71 , 9165 , 161, 80 ), // #613 - INST(Psraw , ExtRmRi_P , O(000F00,E1,_,_,_,_,_,_ ), O(000F00,71,4,_,_,_,_,_ ), 4 , 72 , 9203 , 161, 80 ), // #614 - INST(Psrld , ExtRmRi_P , O(000F00,D2,_,_,_,_,_,_ ), O(000F00,72,2,_,_,_,_,_ ), 4 , 73 , 9210 , 161, 80 ), // #615 - INST(Psrldq , ExtRmRi , 0 , O(660F00,73,3,_,_,_,_,_ ), 0 , 74 , 9217 , 162, 4 ), // #616 - INST(Psrlq , ExtRmRi_P , O(000F00,D3,_,_,_,_,_,_ ), O(000F00,73,2,_,_,_,_,_ ), 4 , 75 , 9225 , 161, 80 ), // #617 - INST(Psrlw , ExtRmRi_P , O(000F00,D1,_,_,_,_,_,_ ), O(000F00,71,2,_,_,_,_,_ ), 4 , 76 , 9256 , 161, 80 ), // #618 - INST(Psubb , ExtRm_P , O(000F00,F8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9263 , 142, 80 ), // #619 - INST(Psubd , ExtRm_P , O(000F00,FA,_,_,_,_,_,_ ), 0 , 4 , 0 , 9270 , 142, 80 ), // #620 - INST(Psubq , ExtRm_P , O(000F00,FB,_,_,_,_,_,_ ), 0 , 4 , 0 , 9277 , 142, 4 ), // #621 - INST(Psubsb , ExtRm_P , O(000F00,E8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9284 , 142, 80 ), // #622 - INST(Psubsw , ExtRm_P , O(000F00,E9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9292 , 142, 80 ), // #623 - INST(Psubusb , ExtRm_P , O(000F00,D8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9300 , 142, 80 ), // #624 - INST(Psubusw , ExtRm_P , O(000F00,D9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9309 , 142, 80 ), // #625 - INST(Psubw , ExtRm_P , O(000F00,F9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9318 , 142, 80 ), // #626 - INST(Pswapd , Ext3dNow , O(000F0F,BB,_,_,_,_,_,_ ), 0 , 87 , 0 , 2387 , 143, 90 ), // #627 - INST(Ptest , ExtRm , O(660F38,17,_,_,_,_,_,_ ), 0 , 2 , 0 , 9347 , 5 , 97 ), // #628 - INST(Ptwrite , X86M , O(F30F00,AE,4,_,_,_,_,_ ), 0 , 91 , 0 , 2394 , 163, 98 ), // #629 - INST(Punpckhbw , ExtRm_P , O(000F00,68,_,_,_,_,_,_ ), 0 , 4 , 0 , 9430 , 139, 80 ), // #630 - INST(Punpckhdq , ExtRm_P , O(000F00,6A,_,_,_,_,_,_ ), 0 , 4 , 0 , 9441 , 139, 80 ), // #631 - INST(Punpckhqdq , ExtRm , O(660F00,6D,_,_,_,_,_,_ ), 0 , 3 , 0 , 9452 , 5 , 4 ), // #632 - INST(Punpckhwd , ExtRm_P , O(000F00,69,_,_,_,_,_,_ ), 0 , 4 , 0 , 9464 , 139, 80 ), // #633 - INST(Punpcklbw , ExtRm_P , O(000F00,60,_,_,_,_,_,_ ), 0 , 4 , 0 , 9475 , 139, 80 ), // #634 - INST(Punpckldq , ExtRm_P , O(000F00,62,_,_,_,_,_,_ ), 0 , 4 , 0 , 9486 , 139, 80 ), // #635 - INST(Punpcklqdq , ExtRm , O(660F00,6C,_,_,_,_,_,_ ), 0 , 3 , 0 , 9497 , 5 , 4 ), // #636 - INST(Punpcklwd , ExtRm_P , O(000F00,61,_,_,_,_,_,_ ), 0 , 4 , 0 , 9509 , 139, 80 ), // #637 - INST(Push , X86Push , O(000000,FF,6,_,_,_,_,_ ), O(000000,50,_,_,_,_,_,_ ), 31 , 77 , 2402 , 164, 0 ), // #638 - INST(Pusha , X86Op , O(660000,60,_,_,_,_,_,_ ), 0 , 19 , 0 , 2407 , 78 , 0 ), // #639 - INST(Pushad , X86Op , O(000000,60,_,_,_,_,_,_ ), 0 , 0 , 0 , 2413 , 78 , 0 ), // #640 - INST(Pushf , X86Op , O(660000,9C,_,_,_,_,_,_ ), 0 , 19 , 0 , 2420 , 30 , 99 ), // #641 - INST(Pushfd , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2426 , 78 , 99 ), // #642 - INST(Pushfq , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2433 , 159, 99 ), // #643 - INST(Pvalidate , X86Op , O(F20F01,FF,_,_,_,_,_,_ ), 0 , 92 , 0 , 2440 , 30 , 100), // #644 - INST(Pxor , ExtRm_P , O(000F00,EF,_,_,_,_,_,_ ), 0 , 4 , 0 , 9520 , 142, 80 ), // #645 - INST(Rcl , X86Rot , O(000000,D0,2,_,x,_,_,_ ), 0 , 1 , 0 , 2450 , 165, 101), // #646 - INST(Rcpps , ExtRm , O(000F00,53,_,_,_,_,_,_ ), 0 , 4 , 0 , 9648 , 5 , 5 ), // #647 - INST(Rcpss , ExtRm , O(F30F00,53,_,_,_,_,_,_ ), 0 , 6 , 0 , 9655 , 7 , 5 ), // #648 - INST(Rcr , X86Rot , O(000000,D0,3,_,x,_,_,_ ), 0 , 84 , 0 , 2454 , 165, 101), // #649 - INST(Rdfsbase , X86M , O(F30F00,AE,0,_,x,_,_,_ ), 0 , 6 , 0 , 2458 , 166, 102), // #650 - INST(Rdgsbase , X86M , O(F30F00,AE,1,_,x,_,_,_ ), 0 , 93 , 0 , 2467 , 166, 102), // #651 - INST(Rdmsr , X86Op , O(000F00,32,_,_,_,_,_,_ ), 0 , 4 , 0 , 2476 , 167, 103), // #652 - INST(Rdpid , X86R_Native , O(F30F00,C7,7,_,_,_,_,_ ), 0 , 94 , 0 , 2482 , 168, 104), // #653 - INST(Rdpkru , X86Op , O(000F01,EE,_,_,_,_,_,_ ), 0 , 21 , 0 , 2488 , 167, 105), // #654 - INST(Rdpmc , X86Op , O(000F00,33,_,_,_,_,_,_ ), 0 , 4 , 0 , 2495 , 167, 0 ), // #655 - INST(Rdpru , X86Op , O(000F01,FD,_,_,_,_,_,_ ), 0 , 21 , 0 , 2501 , 167, 106), // #656 - INST(Rdrand , X86M , O(000F00,C7,6,_,x,_,_,_ ), 0 , 78 , 0 , 2507 , 23 , 107), // #657 - INST(Rdseed , X86M , O(000F00,C7,7,_,x,_,_,_ ), 0 , 22 , 0 , 2514 , 23 , 108), // #658 - INST(Rdsspd , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 93 , 0 , 2521 , 73 , 54 ), // #659 - INST(Rdsspq , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 93 , 0 , 2528 , 74 , 54 ), // #660 - INST(Rdtsc , X86Op , O(000F00,31,_,_,_,_,_,_ ), 0 , 4 , 0 , 2535 , 28 , 109), // #661 - INST(Rdtscp , X86Op , O(000F01,F9,_,_,_,_,_,_ ), 0 , 21 , 0 , 2541 , 167, 110), // #662 - INST(Ret , X86Ret , O(000000,C2,_,_,_,_,_,_ ), 0 , 0 , 0 , 3044 , 169, 0 ), // #663 - INST(Rmpadjust , X86Op , O(F30F01,FE,_,_,_,_,_,_ ), 0 , 81 , 0 , 2548 , 159, 96 ), // #664 - INST(Rmpupdate , X86Op , O(F20F01,FE,_,_,_,_,_,_ ), 0 , 92 , 0 , 2558 , 159, 96 ), // #665 - INST(Rol , X86Rot , O(000000,D0,0,_,x,_,_,_ ), 0 , 0 , 0 , 2568 , 165, 111), // #666 - INST(Ror , X86Rot , O(000000,D0,1,_,x,_,_,_ ), 0 , 30 , 0 , 2572 , 165, 111), // #667 - INST(Rorx , VexRmi_Wx , V(F20F3A,F0,_,0,x,_,_,_ ), 0 , 95 , 0 , 2576 , 170, 83 ), // #668 - INST(Roundpd , ExtRmi , O(660F3A,09,_,_,_,_,_,_ ), 0 , 8 , 0 , 9750 , 8 , 12 ), // #669 - INST(Roundps , ExtRmi , O(660F3A,08,_,_,_,_,_,_ ), 0 , 8 , 0 , 9759 , 8 , 12 ), // #670 - INST(Roundsd , ExtRmi , O(660F3A,0B,_,_,_,_,_,_ ), 0 , 8 , 0 , 9768 , 36 , 12 ), // #671 - INST(Roundss , ExtRmi , O(660F3A,0A,_,_,_,_,_,_ ), 0 , 8 , 0 , 9777 , 37 , 12 ), // #672 - INST(Rsm , X86Op , O(000F00,AA,_,_,_,_,_,_ ), 0 , 4 , 0 , 2581 , 78 , 1 ), // #673 - INST(Rsqrtps , ExtRm , O(000F00,52,_,_,_,_,_,_ ), 0 , 4 , 0 , 9874 , 5 , 5 ), // #674 - INST(Rsqrtss , ExtRm , O(F30F00,52,_,_,_,_,_,_ ), 0 , 6 , 0 , 9883 , 7 , 5 ), // #675 - INST(Rstorssp , X86M , O(F30F00,01,5,_,_,_,_,_ ), 0 , 62 , 0 , 2585 , 32 , 24 ), // #676 - INST(Sahf , X86Op , O(000000,9E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2594 , 93 , 112), // #677 - INST(Sal , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2599 , 165, 1 ), // #678 - INST(Sar , X86Rot , O(000000,D0,7,_,x,_,_,_ ), 0 , 26 , 0 , 2603 , 165, 1 ), // #679 - INST(Sarx , VexRmv_Wx , V(F30F38,F7,_,0,x,_,_,_ ), 0 , 88 , 0 , 2607 , 13 , 83 ), // #680 - INST(Saveprevssp , X86Op , O(F30F01,EA,_,_,_,_,_,_ ), 0 , 81 , 0 , 2612 , 30 , 24 ), // #681 - INST(Sbb , X86Arith , O(000000,18,3,_,x,_,_,_ ), 0 , 84 , 0 , 2624 , 171, 2 ), // #682 - INST(Scas , X86StrRm , O(000000,AE,_,_,_,_,_,_ ), 0 , 0 , 0 , 2628 , 172, 36 ), // #683 - INST(Serialize , X86Op , O(000F01,E8,_,_,_,_,_,_ ), 0 , 21 , 0 , 2633 , 30 , 113), // #684 - INST(Seta , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2643 , 173, 57 ), // #685 - INST(Setae , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2648 , 173, 58 ), // #686 - INST(Setb , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2654 , 173, 58 ), // #687 - INST(Setbe , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2659 , 173, 57 ), // #688 - INST(Setc , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2665 , 173, 58 ), // #689 - INST(Sete , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2670 , 173, 59 ), // #690 - INST(Setg , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2675 , 173, 60 ), // #691 - INST(Setge , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2680 , 173, 61 ), // #692 - INST(Setl , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2686 , 173, 61 ), // #693 - INST(Setle , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2691 , 173, 60 ), // #694 - INST(Setna , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2697 , 173, 57 ), // #695 - INST(Setnae , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2703 , 173, 58 ), // #696 - INST(Setnb , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2710 , 173, 58 ), // #697 - INST(Setnbe , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2716 , 173, 57 ), // #698 - INST(Setnc , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2723 , 173, 58 ), // #699 - INST(Setne , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2729 , 173, 59 ), // #700 - INST(Setng , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2735 , 173, 60 ), // #701 - INST(Setnge , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2741 , 173, 61 ), // #702 - INST(Setnl , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2748 , 173, 61 ), // #703 - INST(Setnle , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2754 , 173, 60 ), // #704 - INST(Setno , X86Set , O(000F00,91,_,_,_,_,_,_ ), 0 , 4 , 0 , 2761 , 173, 55 ), // #705 - INST(Setnp , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2767 , 173, 62 ), // #706 - INST(Setns , X86Set , O(000F00,99,_,_,_,_,_,_ ), 0 , 4 , 0 , 2773 , 173, 63 ), // #707 - INST(Setnz , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2779 , 173, 59 ), // #708 - INST(Seto , X86Set , O(000F00,90,_,_,_,_,_,_ ), 0 , 4 , 0 , 2785 , 173, 55 ), // #709 - INST(Setp , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2790 , 173, 62 ), // #710 - INST(Setpe , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2795 , 173, 62 ), // #711 - INST(Setpo , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2801 , 173, 62 ), // #712 - INST(Sets , X86Set , O(000F00,98,_,_,_,_,_,_ ), 0 , 4 , 0 , 2807 , 173, 63 ), // #713 - INST(Setssbsy , X86Op , O(F30F01,E8,_,_,_,_,_,_ ), 0 , 81 , 0 , 2812 , 30 , 54 ), // #714 - INST(Setz , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2821 , 173, 59 ), // #715 - INST(Sfence , X86Fence , O(000F00,AE,7,_,_,_,_,_ ), 0 , 22 , 0 , 2826 , 30 , 75 ), // #716 - INST(Sgdt , X86M_Only , O(000F00,01,0,_,_,_,_,_ ), 0 , 4 , 0 , 2833 , 31 , 0 ), // #717 - INST(Sha1msg1 , ExtRm , O(000F38,C9,_,_,_,_,_,_ ), 0 , 82 , 0 , 2838 , 5 , 114), // #718 - INST(Sha1msg2 , ExtRm , O(000F38,CA,_,_,_,_,_,_ ), 0 , 82 , 0 , 2847 , 5 , 114), // #719 - INST(Sha1nexte , ExtRm , O(000F38,C8,_,_,_,_,_,_ ), 0 , 82 , 0 , 2856 , 5 , 114), // #720 - INST(Sha1rnds4 , ExtRmi , O(000F3A,CC,_,_,_,_,_,_ ), 0 , 85 , 0 , 2866 , 8 , 114), // #721 - INST(Sha256msg1 , ExtRm , O(000F38,CC,_,_,_,_,_,_ ), 0 , 82 , 0 , 2876 , 5 , 114), // #722 - INST(Sha256msg2 , ExtRm , O(000F38,CD,_,_,_,_,_,_ ), 0 , 82 , 0 , 2887 , 5 , 114), // #723 - INST(Sha256rnds2 , ExtRm_XMM0 , O(000F38,CB,_,_,_,_,_,_ ), 0 , 82 , 0 , 2898 , 15 , 114), // #724 - INST(Shl , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2910 , 165, 1 ), // #725 - INST(Shld , X86ShldShrd , O(000F00,A4,_,_,x,_,_,_ ), 0 , 4 , 0 , 8919 , 174, 1 ), // #726 - INST(Shlx , VexRmv_Wx , V(660F38,F7,_,0,x,_,_,_ ), 0 , 96 , 0 , 2914 , 13 , 83 ), // #727 - INST(Shr , X86Rot , O(000000,D0,5,_,x,_,_,_ ), 0 , 61 , 0 , 2919 , 165, 1 ), // #728 - INST(Shrd , X86ShldShrd , O(000F00,AC,_,_,x,_,_,_ ), 0 , 4 , 0 , 2923 , 174, 1 ), // #729 - INST(Shrx , VexRmv_Wx , V(F20F38,F7,_,0,x,_,_,_ ), 0 , 83 , 0 , 2928 , 13 , 83 ), // #730 - INST(Shufpd , ExtRmi , O(660F00,C6,_,_,_,_,_,_ ), 0 , 3 , 0 , 10144, 8 , 4 ), // #731 - INST(Shufps , ExtRmi , O(000F00,C6,_,_,_,_,_,_ ), 0 , 4 , 0 , 10152, 8 , 5 ), // #732 - INST(Sidt , X86M_Only , O(000F00,01,1,_,_,_,_,_ ), 0 , 28 , 0 , 2933 , 31 , 0 ), // #733 - INST(Skinit , X86Op_xAX , O(000F01,DE,_,_,_,_,_,_ ), 0 , 21 , 0 , 2938 , 51 , 115), // #734 - INST(Sldt , X86M , O(000F00,00,0,_,_,_,_,_ ), 0 , 4 , 0 , 2945 , 175, 0 ), // #735 - INST(Slwpcb , VexR_Wx , V(XOP_M9,12,1,0,x,_,_,_ ), 0 , 11 , 0 , 2950 , 102, 72 ), // #736 - INST(Smsw , X86M , O(000F00,01,4,_,_,_,_,_ ), 0 , 97 , 0 , 2957 , 175, 0 ), // #737 - INST(Sqrtpd , ExtRm , O(660F00,51,_,_,_,_,_,_ ), 0 , 3 , 0 , 10160, 5 , 4 ), // #738 - INST(Sqrtps , ExtRm , O(000F00,51,_,_,_,_,_,_ ), 0 , 4 , 0 , 9875 , 5 , 5 ), // #739 - INST(Sqrtsd , ExtRm , O(F20F00,51,_,_,_,_,_,_ ), 0 , 5 , 0 , 10176, 6 , 4 ), // #740 - INST(Sqrtss , ExtRm , O(F30F00,51,_,_,_,_,_,_ ), 0 , 6 , 0 , 9884 , 7 , 5 ), // #741 - INST(Stac , X86Op , O(000F01,CB,_,_,_,_,_,_ ), 0 , 21 , 0 , 2962 , 30 , 16 ), // #742 - INST(Stc , X86Op , O(000000,F9,_,_,_,_,_,_ ), 0 , 0 , 0 , 2967 , 30 , 17 ), // #743 - INST(Std , X86Op , O(000000,FD,_,_,_,_,_,_ ), 0 , 0 , 0 , 6902 , 30 , 18 ), // #744 - INST(Stgi , X86Op , O(000F01,DC,_,_,_,_,_,_ ), 0 , 21 , 0 , 2971 , 30 , 115), // #745 - INST(Sti , X86Op , O(000000,FB,_,_,_,_,_,_ ), 0 , 0 , 0 , 2976 , 30 , 23 ), // #746 - INST(Stmxcsr , X86M_Only , O(000F00,AE,3,_,_,_,_,_ ), 0 , 76 , 0 , 10192, 96 , 5 ), // #747 - INST(Stos , X86StrMr , O(000000,AA,_,_,_,_,_,_ ), 0 , 0 , 0 , 2980 , 176, 73 ), // #748 - INST(Str , X86M , O(000F00,00,1,_,_,_,_,_ ), 0 , 28 , 0 , 2985 , 175, 0 ), // #749 - INST(Sttilecfg , AmxCfg , V(660F38,49,_,0,0,_,_,_ ), 0 , 96 , 0 , 2989 , 98 , 71 ), // #750 - INST(Sub , X86Arith , O(000000,28,5,_,x,_,_,_ ), 0 , 61 , 0 , 861 , 171, 1 ), // #751 - INST(Subpd , ExtRm , O(660F00,5C,_,_,_,_,_,_ ), 0 , 3 , 0 , 4844 , 5 , 4 ), // #752 - INST(Subps , ExtRm , O(000F00,5C,_,_,_,_,_,_ ), 0 , 4 , 0 , 4856 , 5 , 5 ), // #753 - INST(Subsd , ExtRm , O(F20F00,5C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5532 , 6 , 4 ), // #754 - INST(Subss , ExtRm , O(F30F00,5C,_,_,_,_,_,_ ), 0 , 6 , 0 , 5542 , 7 , 5 ), // #755 - INST(Swapgs , X86Op , O(000F01,F8,_,_,_,_,_,_ ), 0 , 21 , 0 , 2999 , 159, 0 ), // #756 - INST(Syscall , X86Op , O(000F00,05,_,_,_,_,_,_ ), 0 , 4 , 0 , 3006 , 159, 0 ), // #757 - INST(Sysenter , X86Op , O(000F00,34,_,_,_,_,_,_ ), 0 , 4 , 0 , 3014 , 30 , 0 ), // #758 - INST(Sysexit , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 3023 , 30 , 0 ), // #759 - INST(Sysexit64 , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 3031 , 30 , 0 ), // #760 - INST(Sysret , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 3041 , 159, 0 ), // #761 - INST(Sysret64 , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 3048 , 159, 0 ), // #762 - INST(T1mskc , VexVm_Wx , V(XOP_M9,01,7,0,x,_,_,_ ), 0 , 98 , 0 , 3057 , 14 , 11 ), // #763 - INST(Tdpbf16ps , AmxRmv , V(F30F38,5C,_,0,0,_,_,_ ), 0 , 88 , 0 , 3064 , 177, 116), // #764 - INST(Tdpbssd , AmxRmv , V(F20F38,5E,_,0,0,_,_,_ ), 0 , 83 , 0 , 3074 , 177, 117), // #765 - INST(Tdpbsud , AmxRmv , V(F30F38,5E,_,0,0,_,_,_ ), 0 , 88 , 0 , 3082 , 177, 117), // #766 - INST(Tdpbusd , AmxRmv , V(660F38,5E,_,0,0,_,_,_ ), 0 , 96 , 0 , 3090 , 177, 117), // #767 - INST(Tdpbuud , AmxRmv , V(000F38,5E,_,0,0,_,_,_ ), 0 , 10 , 0 , 3098 , 177, 117), // #768 - INST(Test , X86Test , O(000000,84,_,_,x,_,_,_ ), O(000000,F6,_,_,x,_,_,_ ), 0 , 78 , 9348 , 178, 1 ), // #769 - INST(Tileloadd , AmxRm , V(F20F38,4B,_,0,0,_,_,_ ), 0 , 83 , 0 , 3106 , 179, 71 ), // #770 - INST(Tileloaddt1 , AmxRm , V(660F38,4B,_,0,0,_,_,_ ), 0 , 96 , 0 , 3116 , 179, 71 ), // #771 - INST(Tilerelease , VexOpMod , V(000F38,49,0,0,0,_,_,_ ), 0 , 10 , 0 , 3128 , 180, 71 ), // #772 - INST(Tilestored , AmxMr , V(F30F38,4B,_,0,0,_,_,_ ), 0 , 88 , 0 , 3140 , 181, 71 ), // #773 - INST(Tilezero , AmxR , V(F20F38,49,_,0,0,_,_,_ ), 0 , 83 , 0 , 3151 , 182, 71 ), // #774 - INST(Tpause , X86R32_EDX_EAX , O(660F00,AE,6,_,_,_,_,_ ), 0 , 25 , 0 , 3160 , 183, 118), // #775 - INST(Tzcnt , X86Rm_Raw66H , O(F30F00,BC,_,_,x,_,_,_ ), 0 , 6 , 0 , 3167 , 22 , 9 ), // #776 - INST(Tzmsk , VexVm_Wx , V(XOP_M9,01,4,0,x,_,_,_ ), 0 , 99 , 0 , 3173 , 14 , 11 ), // #777 - INST(Ucomisd , ExtRm , O(660F00,2E,_,_,_,_,_,_ ), 0 , 3 , 0 , 10245, 6 , 40 ), // #778 - INST(Ucomiss , ExtRm , O(000F00,2E,_,_,_,_,_,_ ), 0 , 4 , 0 , 10254, 7 , 41 ), // #779 - INST(Ud0 , X86M , O(000F00,FF,_,_,_,_,_,_ ), 0 , 4 , 0 , 3179 , 184, 0 ), // #780 - INST(Ud1 , X86M , O(000F00,B9,_,_,_,_,_,_ ), 0 , 4 , 0 , 3183 , 184, 0 ), // #781 - INST(Ud2 , X86Op , O(000F00,0B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3187 , 30 , 0 ), // #782 - INST(Umonitor , X86R_FromM , O(F30F00,AE,6,_,_,_,_,_ ), 0 , 24 , 0 , 3191 , 185, 119), // #783 - INST(Umwait , X86R32_EDX_EAX , O(F20F00,AE,6,_,_,_,_,_ ), 0 , 100, 0 , 3200 , 183, 118), // #784 - INST(Unpckhpd , ExtRm , O(660F00,15,_,_,_,_,_,_ ), 0 , 3 , 0 , 10263, 5 , 4 ), // #785 - INST(Unpckhps , ExtRm , O(000F00,15,_,_,_,_,_,_ ), 0 , 4 , 0 , 10273, 5 , 5 ), // #786 - INST(Unpcklpd , ExtRm , O(660F00,14,_,_,_,_,_,_ ), 0 , 3 , 0 , 10283, 5 , 4 ), // #787 - INST(Unpcklps , ExtRm , O(000F00,14,_,_,_,_,_,_ ), 0 , 4 , 0 , 10293, 5 , 5 ), // #788 - INST(V4fmaddps , VexRm_T1_4X , E(F20F38,9A,_,2,_,0,2,T4X), 0 , 101, 0 , 3207 , 186, 120), // #789 - INST(V4fmaddss , VexRm_T1_4X , E(F20F38,9B,_,2,_,0,2,T4X), 0 , 101, 0 , 3217 , 187, 120), // #790 - INST(V4fnmaddps , VexRm_T1_4X , E(F20F38,AA,_,2,_,0,2,T4X), 0 , 101, 0 , 3227 , 186, 120), // #791 - INST(V4fnmaddss , VexRm_T1_4X , E(F20F38,AB,_,2,_,0,2,T4X), 0 , 101, 0 , 3238 , 187, 120), // #792 - INST(Vaddpd , VexRvm_Lx , V(660F00,58,_,x,I,1,4,FV ), 0 , 102, 0 , 3249 , 188, 121), // #793 - INST(Vaddps , VexRvm_Lx , V(000F00,58,_,x,I,0,4,FV ), 0 , 103, 0 , 3256 , 189, 121), // #794 - INST(Vaddsd , VexRvm , V(F20F00,58,_,I,I,1,3,T1S), 0 , 104, 0 , 3263 , 190, 122), // #795 - INST(Vaddss , VexRvm , V(F30F00,58,_,I,I,0,2,T1S), 0 , 105, 0 , 3270 , 191, 122), // #796 - INST(Vaddsubpd , VexRvm_Lx , V(660F00,D0,_,x,I,_,_,_ ), 0 , 68 , 0 , 3277 , 192, 123), // #797 - INST(Vaddsubps , VexRvm_Lx , V(F20F00,D0,_,x,I,_,_,_ ), 0 , 106, 0 , 3287 , 192, 123), // #798 - INST(Vaesdec , VexRvm_Lx , V(660F38,DE,_,x,I,_,4,FVM), 0 , 107, 0 , 3297 , 193, 124), // #799 - INST(Vaesdeclast , VexRvm_Lx , V(660F38,DF,_,x,I,_,4,FVM), 0 , 107, 0 , 3305 , 193, 124), // #800 - INST(Vaesenc , VexRvm_Lx , V(660F38,DC,_,x,I,_,4,FVM), 0 , 107, 0 , 3317 , 193, 124), // #801 - INST(Vaesenclast , VexRvm_Lx , V(660F38,DD,_,x,I,_,4,FVM), 0 , 107, 0 , 3325 , 193, 124), // #802 - INST(Vaesimc , VexRm , V(660F38,DB,_,0,I,_,_,_ ), 0 , 96 , 0 , 3337 , 194, 125), // #803 - INST(Vaeskeygenassist , VexRmi , V(660F3A,DF,_,0,I,_,_,_ ), 0 , 72 , 0 , 3345 , 195, 125), // #804 - INST(Valignd , VexRvmi_Lx , E(660F3A,03,_,x,_,0,4,FV ), 0 , 108, 0 , 3362 , 196, 126), // #805 - INST(Valignq , VexRvmi_Lx , E(660F3A,03,_,x,_,1,4,FV ), 0 , 109, 0 , 3370 , 197, 126), // #806 - INST(Vandnpd , VexRvm_Lx , V(660F00,55,_,x,I,1,4,FV ), 0 , 102, 0 , 3378 , 198, 127), // #807 - INST(Vandnps , VexRvm_Lx , V(000F00,55,_,x,I,0,4,FV ), 0 , 103, 0 , 3386 , 199, 127), // #808 - INST(Vandpd , VexRvm_Lx , V(660F00,54,_,x,I,1,4,FV ), 0 , 102, 0 , 3394 , 200, 127), // #809 - INST(Vandps , VexRvm_Lx , V(000F00,54,_,x,I,0,4,FV ), 0 , 103, 0 , 3401 , 201, 127), // #810 - INST(Vblendmb , VexRvm_Lx , E(660F38,66,_,x,_,0,4,FVM), 0 , 110, 0 , 3408 , 202, 128), // #811 - INST(Vblendmd , VexRvm_Lx , E(660F38,64,_,x,_,0,4,FV ), 0 , 111, 0 , 3417 , 203, 126), // #812 - INST(Vblendmpd , VexRvm_Lx , E(660F38,65,_,x,_,1,4,FV ), 0 , 112, 0 , 3426 , 204, 126), // #813 - INST(Vblendmps , VexRvm_Lx , E(660F38,65,_,x,_,0,4,FV ), 0 , 111, 0 , 3436 , 203, 126), // #814 - INST(Vblendmq , VexRvm_Lx , E(660F38,64,_,x,_,1,4,FV ), 0 , 112, 0 , 3446 , 204, 126), // #815 - INST(Vblendmw , VexRvm_Lx , E(660F38,66,_,x,_,1,4,FVM), 0 , 113, 0 , 3455 , 202, 128), // #816 - INST(Vblendpd , VexRvmi_Lx , V(660F3A,0D,_,x,I,_,_,_ ), 0 , 72 , 0 , 3464 , 205, 123), // #817 - INST(Vblendps , VexRvmi_Lx , V(660F3A,0C,_,x,I,_,_,_ ), 0 , 72 , 0 , 3473 , 205, 123), // #818 - INST(Vblendvpd , VexRvmr_Lx , V(660F3A,4B,_,x,0,_,_,_ ), 0 , 72 , 0 , 3482 , 206, 123), // #819 - INST(Vblendvps , VexRvmr_Lx , V(660F3A,4A,_,x,0,_,_,_ ), 0 , 72 , 0 , 3492 , 206, 123), // #820 - INST(Vbroadcastf128 , VexRm , V(660F38,1A,_,1,0,_,_,_ ), 0 , 114, 0 , 3502 , 207, 123), // #821 - INST(Vbroadcastf32x2 , VexRm_Lx , E(660F38,19,_,x,_,0,3,T2 ), 0 , 115, 0 , 3517 , 208, 129), // #822 - INST(Vbroadcastf32x4 , VexRm_Lx , E(660F38,1A,_,x,_,0,4,T4 ), 0 , 116, 0 , 3533 , 209, 66 ), // #823 - INST(Vbroadcastf32x8 , VexRm , E(660F38,1B,_,2,_,0,5,T8 ), 0 , 117, 0 , 3549 , 210, 64 ), // #824 - INST(Vbroadcastf64x2 , VexRm_Lx , E(660F38,1A,_,x,_,1,4,T2 ), 0 , 118, 0 , 3565 , 209, 129), // #825 - INST(Vbroadcastf64x4 , VexRm , E(660F38,1B,_,2,_,1,5,T4 ), 0 , 119, 0 , 3581 , 210, 66 ), // #826 - INST(Vbroadcasti128 , VexRm , V(660F38,5A,_,1,0,_,_,_ ), 0 , 114, 0 , 3597 , 207, 130), // #827 - INST(Vbroadcasti32x2 , VexRm_Lx , E(660F38,59,_,x,_,0,3,T2 ), 0 , 115, 0 , 3612 , 211, 129), // #828 - INST(Vbroadcasti32x4 , VexRm_Lx , E(660F38,5A,_,x,_,0,4,T4 ), 0 , 116, 0 , 3628 , 209, 126), // #829 - INST(Vbroadcasti32x8 , VexRm , E(660F38,5B,_,2,_,0,5,T8 ), 0 , 117, 0 , 3644 , 210, 64 ), // #830 - INST(Vbroadcasti64x2 , VexRm_Lx , E(660F38,5A,_,x,_,1,4,T2 ), 0 , 118, 0 , 3660 , 209, 129), // #831 - INST(Vbroadcasti64x4 , VexRm , E(660F38,5B,_,2,_,1,5,T4 ), 0 , 119, 0 , 3676 , 210, 66 ), // #832 - INST(Vbroadcastsd , VexRm_Lx , V(660F38,19,_,x,0,1,3,T1S), 0 , 120, 0 , 3692 , 212, 131), // #833 - INST(Vbroadcastss , VexRm_Lx , V(660F38,18,_,x,0,0,2,T1S), 0 , 121, 0 , 3705 , 213, 131), // #834 - INST(Vcmppd , VexRvmi_Lx , V(660F00,C2,_,x,I,1,4,FV ), 0 , 102, 0 , 3718 , 214, 121), // #835 - INST(Vcmpps , VexRvmi_Lx , V(000F00,C2,_,x,I,0,4,FV ), 0 , 103, 0 , 3725 , 215, 121), // #836 - INST(Vcmpsd , VexRvmi , V(F20F00,C2,_,I,I,1,3,T1S), 0 , 104, 0 , 3732 , 216, 122), // #837 - INST(Vcmpss , VexRvmi , V(F30F00,C2,_,I,I,0,2,T1S), 0 , 105, 0 , 3739 , 217, 122), // #838 - INST(Vcomisd , VexRm , V(660F00,2F,_,I,I,1,3,T1S), 0 , 122, 0 , 3746 , 218, 132), // #839 - INST(Vcomiss , VexRm , V(000F00,2F,_,I,I,0,2,T1S), 0 , 123, 0 , 3754 , 219, 132), // #840 - INST(Vcompresspd , VexMr_Lx , E(660F38,8A,_,x,_,1,3,T1S), 0 , 124, 0 , 3762 , 220, 126), // #841 - INST(Vcompressps , VexMr_Lx , E(660F38,8A,_,x,_,0,2,T1S), 0 , 125, 0 , 3774 , 220, 126), // #842 - INST(Vcvtdq2pd , VexRm_Lx , V(F30F00,E6,_,x,I,0,3,HV ), 0 , 126, 0 , 3786 , 221, 121), // #843 - INST(Vcvtdq2ps , VexRm_Lx , V(000F00,5B,_,x,I,0,4,FV ), 0 , 103, 0 , 3796 , 222, 121), // #844 - INST(Vcvtne2ps2bf16 , VexRvm , E(F20F38,72,_,_,_,0,_,_ ), 0 , 127, 0 , 3806 , 203, 133), // #845 - INST(Vcvtneps2bf16 , VexRm , E(F30F38,72,_,_,_,0,_,_ ), 0 , 128, 0 , 3821 , 223, 133), // #846 - INST(Vcvtpd2dq , VexRm_Lx , V(F20F00,E6,_,x,I,1,4,FV ), 0 , 129, 0 , 3835 , 224, 121), // #847 - INST(Vcvtpd2ps , VexRm_Lx , V(660F00,5A,_,x,I,1,4,FV ), 0 , 102, 0 , 3845 , 224, 121), // #848 - INST(Vcvtpd2qq , VexRm_Lx , E(660F00,7B,_,x,_,1,4,FV ), 0 , 130, 0 , 3855 , 225, 129), // #849 - INST(Vcvtpd2udq , VexRm_Lx , E(000F00,79,_,x,_,1,4,FV ), 0 , 131, 0 , 3865 , 226, 126), // #850 - INST(Vcvtpd2uqq , VexRm_Lx , E(660F00,79,_,x,_,1,4,FV ), 0 , 130, 0 , 3876 , 225, 129), // #851 - INST(Vcvtph2ps , VexRm_Lx , V(660F38,13,_,x,0,0,3,HVM), 0 , 132, 0 , 3887 , 227, 134), // #852 - INST(Vcvtps2dq , VexRm_Lx , V(660F00,5B,_,x,I,0,4,FV ), 0 , 133, 0 , 3897 , 222, 121), // #853 - INST(Vcvtps2pd , VexRm_Lx , V(000F00,5A,_,x,I,0,4,HV ), 0 , 134, 0 , 3907 , 228, 121), // #854 - INST(Vcvtps2ph , VexMri_Lx , V(660F3A,1D,_,x,0,0,3,HVM), 0 , 135, 0 , 3917 , 229, 134), // #855 - INST(Vcvtps2qq , VexRm_Lx , E(660F00,7B,_,x,_,0,3,HV ), 0 , 136, 0 , 3927 , 230, 129), // #856 - INST(Vcvtps2udq , VexRm_Lx , E(000F00,79,_,x,_,0,4,FV ), 0 , 137, 0 , 3937 , 231, 126), // #857 - INST(Vcvtps2uqq , VexRm_Lx , E(660F00,79,_,x,_,0,3,HV ), 0 , 136, 0 , 3948 , 230, 129), // #858 - INST(Vcvtqq2pd , VexRm_Lx , E(F30F00,E6,_,x,_,1,4,FV ), 0 , 138, 0 , 3959 , 225, 129), // #859 - INST(Vcvtqq2ps , VexRm_Lx , E(000F00,5B,_,x,_,1,4,FV ), 0 , 131, 0 , 3969 , 226, 129), // #860 - INST(Vcvtsd2si , VexRm_Wx , V(F20F00,2D,_,I,x,x,3,T1F), 0 , 139, 0 , 3979 , 232, 122), // #861 - INST(Vcvtsd2ss , VexRvm , V(F20F00,5A,_,I,I,1,3,T1S), 0 , 104, 0 , 3989 , 190, 122), // #862 - INST(Vcvtsd2usi , VexRm_Wx , E(F20F00,79,_,I,_,x,3,T1F), 0 , 140, 0 , 3999 , 233, 66 ), // #863 - INST(Vcvtsi2sd , VexRvm_Wx , V(F20F00,2A,_,I,x,x,2,T1W), 0 , 141, 0 , 4010 , 234, 122), // #864 - INST(Vcvtsi2ss , VexRvm_Wx , V(F30F00,2A,_,I,x,x,2,T1W), 0 , 142, 0 , 4020 , 234, 122), // #865 - INST(Vcvtss2sd , VexRvm , V(F30F00,5A,_,I,I,0,2,T1S), 0 , 105, 0 , 4030 , 235, 122), // #866 - INST(Vcvtss2si , VexRm_Wx , V(F30F00,2D,_,I,x,x,2,T1F), 0 , 143, 0 , 4040 , 236, 122), // #867 - INST(Vcvtss2usi , VexRm_Wx , E(F30F00,79,_,I,_,x,2,T1F), 0 , 144, 0 , 4050 , 237, 66 ), // #868 - INST(Vcvttpd2dq , VexRm_Lx , V(660F00,E6,_,x,I,1,4,FV ), 0 , 102, 0 , 4061 , 238, 121), // #869 - INST(Vcvttpd2qq , VexRm_Lx , E(660F00,7A,_,x,_,1,4,FV ), 0 , 130, 0 , 4072 , 239, 126), // #870 - INST(Vcvttpd2udq , VexRm_Lx , E(000F00,78,_,x,_,1,4,FV ), 0 , 131, 0 , 4083 , 240, 126), // #871 - INST(Vcvttpd2uqq , VexRm_Lx , E(660F00,78,_,x,_,1,4,FV ), 0 , 130, 0 , 4095 , 239, 129), // #872 - INST(Vcvttps2dq , VexRm_Lx , V(F30F00,5B,_,x,I,0,4,FV ), 0 , 145, 0 , 4107 , 241, 121), // #873 - INST(Vcvttps2qq , VexRm_Lx , E(660F00,7A,_,x,_,0,3,HV ), 0 , 136, 0 , 4118 , 242, 129), // #874 - INST(Vcvttps2udq , VexRm_Lx , E(000F00,78,_,x,_,0,4,FV ), 0 , 137, 0 , 4129 , 243, 126), // #875 - INST(Vcvttps2uqq , VexRm_Lx , E(660F00,78,_,x,_,0,3,HV ), 0 , 136, 0 , 4141 , 242, 129), // #876 - INST(Vcvttsd2si , VexRm_Wx , V(F20F00,2C,_,I,x,x,3,T1F), 0 , 139, 0 , 4153 , 244, 122), // #877 - INST(Vcvttsd2usi , VexRm_Wx , E(F20F00,78,_,I,_,x,3,T1F), 0 , 140, 0 , 4164 , 245, 66 ), // #878 - INST(Vcvttss2si , VexRm_Wx , V(F30F00,2C,_,I,x,x,2,T1F), 0 , 143, 0 , 4176 , 246, 122), // #879 - INST(Vcvttss2usi , VexRm_Wx , E(F30F00,78,_,I,_,x,2,T1F), 0 , 144, 0 , 4187 , 247, 66 ), // #880 - INST(Vcvtudq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,0,3,HV ), 0 , 146, 0 , 4199 , 248, 126), // #881 - INST(Vcvtudq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,0,4,FV ), 0 , 147, 0 , 4210 , 231, 126), // #882 - INST(Vcvtuqq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,1,4,FV ), 0 , 138, 0 , 4221 , 225, 129), // #883 - INST(Vcvtuqq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,1,4,FV ), 0 , 148, 0 , 4232 , 226, 129), // #884 - INST(Vcvtusi2sd , VexRvm_Wx , E(F20F00,7B,_,I,_,x,2,T1W), 0 , 149, 0 , 4243 , 249, 66 ), // #885 - INST(Vcvtusi2ss , VexRvm_Wx , E(F30F00,7B,_,I,_,x,2,T1W), 0 , 150, 0 , 4254 , 249, 66 ), // #886 - INST(Vdbpsadbw , VexRvmi_Lx , E(660F3A,42,_,x,_,0,4,FVM), 0 , 151, 0 , 4265 , 250, 128), // #887 - INST(Vdivpd , VexRvm_Lx , V(660F00,5E,_,x,I,1,4,FV ), 0 , 102, 0 , 4275 , 188, 121), // #888 - INST(Vdivps , VexRvm_Lx , V(000F00,5E,_,x,I,0,4,FV ), 0 , 103, 0 , 4282 , 189, 121), // #889 - INST(Vdivsd , VexRvm , V(F20F00,5E,_,I,I,1,3,T1S), 0 , 104, 0 , 4289 , 190, 122), // #890 - INST(Vdivss , VexRvm , V(F30F00,5E,_,I,I,0,2,T1S), 0 , 105, 0 , 4296 , 191, 122), // #891 - INST(Vdpbf16ps , VexRvm , E(F30F38,52,_,_,_,0,_,_ ), 0 , 128, 0 , 4303 , 203, 133), // #892 - INST(Vdppd , VexRvmi_Lx , V(660F3A,41,_,x,I,_,_,_ ), 0 , 72 , 0 , 4313 , 251, 123), // #893 - INST(Vdpps , VexRvmi_Lx , V(660F3A,40,_,x,I,_,_,_ ), 0 , 72 , 0 , 4319 , 205, 123), // #894 - INST(Verr , X86M_NoSize , O(000F00,00,4,_,_,_,_,_ ), 0 , 97 , 0 , 4325 , 101, 10 ), // #895 - INST(Verw , X86M_NoSize , O(000F00,00,5,_,_,_,_,_ ), 0 , 75 , 0 , 4330 , 101, 10 ), // #896 - INST(Vexp2pd , VexRm , E(660F38,C8,_,2,_,1,4,FV ), 0 , 152, 0 , 4335 , 252, 135), // #897 - INST(Vexp2ps , VexRm , E(660F38,C8,_,2,_,0,4,FV ), 0 , 153, 0 , 4343 , 253, 135), // #898 - INST(Vexpandpd , VexRm_Lx , E(660F38,88,_,x,_,1,3,T1S), 0 , 124, 0 , 4351 , 254, 126), // #899 - INST(Vexpandps , VexRm_Lx , E(660F38,88,_,x,_,0,2,T1S), 0 , 125, 0 , 4361 , 254, 126), // #900 - INST(Vextractf128 , VexMri , V(660F3A,19,_,1,0,_,_,_ ), 0 , 154, 0 , 4371 , 255, 123), // #901 - INST(Vextractf32x4 , VexMri_Lx , E(660F3A,19,_,x,_,0,4,T4 ), 0 , 155, 0 , 4384 , 256, 126), // #902 - INST(Vextractf32x8 , VexMri , E(660F3A,1B,_,2,_,0,5,T8 ), 0 , 156, 0 , 4398 , 257, 64 ), // #903 - INST(Vextractf64x2 , VexMri_Lx , E(660F3A,19,_,x,_,1,4,T2 ), 0 , 157, 0 , 4412 , 256, 129), // #904 - INST(Vextractf64x4 , VexMri , E(660F3A,1B,_,2,_,1,5,T4 ), 0 , 158, 0 , 4426 , 257, 66 ), // #905 - INST(Vextracti128 , VexMri , V(660F3A,39,_,1,0,_,_,_ ), 0 , 154, 0 , 4440 , 255, 130), // #906 - INST(Vextracti32x4 , VexMri_Lx , E(660F3A,39,_,x,_,0,4,T4 ), 0 , 155, 0 , 4453 , 256, 126), // #907 - INST(Vextracti32x8 , VexMri , E(660F3A,3B,_,2,_,0,5,T8 ), 0 , 156, 0 , 4467 , 257, 64 ), // #908 - INST(Vextracti64x2 , VexMri_Lx , E(660F3A,39,_,x,_,1,4,T2 ), 0 , 157, 0 , 4481 , 256, 129), // #909 - INST(Vextracti64x4 , VexMri , E(660F3A,3B,_,2,_,1,5,T4 ), 0 , 158, 0 , 4495 , 257, 66 ), // #910 - INST(Vextractps , VexMri , V(660F3A,17,_,0,I,I,2,T1S), 0 , 159, 0 , 4509 , 258, 122), // #911 - INST(Vfixupimmpd , VexRvmi_Lx , E(660F3A,54,_,x,_,1,4,FV ), 0 , 109, 0 , 4520 , 259, 126), // #912 - INST(Vfixupimmps , VexRvmi_Lx , E(660F3A,54,_,x,_,0,4,FV ), 0 , 108, 0 , 4532 , 260, 126), // #913 - INST(Vfixupimmsd , VexRvmi , E(660F3A,55,_,I,_,1,3,T1S), 0 , 160, 0 , 4544 , 261, 66 ), // #914 - INST(Vfixupimmss , VexRvmi , E(660F3A,55,_,I,_,0,2,T1S), 0 , 161, 0 , 4556 , 262, 66 ), // #915 - INST(Vfmadd132pd , VexRvm_Lx , V(660F38,98,_,x,1,1,4,FV ), 0 , 162, 0 , 4568 , 188, 136), // #916 - INST(Vfmadd132ps , VexRvm_Lx , V(660F38,98,_,x,0,0,4,FV ), 0 , 163, 0 , 4580 , 189, 136), // #917 - INST(Vfmadd132sd , VexRvm , V(660F38,99,_,I,1,1,3,T1S), 0 , 164, 0 , 4592 , 190, 137), // #918 - INST(Vfmadd132ss , VexRvm , V(660F38,99,_,I,0,0,2,T1S), 0 , 121, 0 , 4604 , 191, 137), // #919 - INST(Vfmadd213pd , VexRvm_Lx , V(660F38,A8,_,x,1,1,4,FV ), 0 , 162, 0 , 4616 , 188, 136), // #920 - INST(Vfmadd213ps , VexRvm_Lx , V(660F38,A8,_,x,0,0,4,FV ), 0 , 163, 0 , 4628 , 189, 136), // #921 - INST(Vfmadd213sd , VexRvm , V(660F38,A9,_,I,1,1,3,T1S), 0 , 164, 0 , 4640 , 190, 137), // #922 - INST(Vfmadd213ss , VexRvm , V(660F38,A9,_,I,0,0,2,T1S), 0 , 121, 0 , 4652 , 191, 137), // #923 - INST(Vfmadd231pd , VexRvm_Lx , V(660F38,B8,_,x,1,1,4,FV ), 0 , 162, 0 , 4664 , 188, 136), // #924 - INST(Vfmadd231ps , VexRvm_Lx , V(660F38,B8,_,x,0,0,4,FV ), 0 , 163, 0 , 4676 , 189, 136), // #925 - INST(Vfmadd231sd , VexRvm , V(660F38,B9,_,I,1,1,3,T1S), 0 , 164, 0 , 4688 , 190, 137), // #926 - INST(Vfmadd231ss , VexRvm , V(660F38,B9,_,I,0,0,2,T1S), 0 , 121, 0 , 4700 , 191, 137), // #927 - INST(Vfmaddpd , Fma4_Lx , V(660F3A,69,_,x,x,_,_,_ ), 0 , 72 , 0 , 4712 , 263, 138), // #928 - INST(Vfmaddps , Fma4_Lx , V(660F3A,68,_,x,x,_,_,_ ), 0 , 72 , 0 , 4721 , 263, 138), // #929 - INST(Vfmaddsd , Fma4 , V(660F3A,6B,_,0,x,_,_,_ ), 0 , 72 , 0 , 4730 , 264, 138), // #930 - INST(Vfmaddss , Fma4 , V(660F3A,6A,_,0,x,_,_,_ ), 0 , 72 , 0 , 4739 , 265, 138), // #931 - INST(Vfmaddsub132pd , VexRvm_Lx , V(660F38,96,_,x,1,1,4,FV ), 0 , 162, 0 , 4748 , 188, 136), // #932 - INST(Vfmaddsub132ps , VexRvm_Lx , V(660F38,96,_,x,0,0,4,FV ), 0 , 163, 0 , 4763 , 189, 136), // #933 - INST(Vfmaddsub213pd , VexRvm_Lx , V(660F38,A6,_,x,1,1,4,FV ), 0 , 162, 0 , 4778 , 188, 136), // #934 - INST(Vfmaddsub213ps , VexRvm_Lx , V(660F38,A6,_,x,0,0,4,FV ), 0 , 163, 0 , 4793 , 189, 136), // #935 - INST(Vfmaddsub231pd , VexRvm_Lx , V(660F38,B6,_,x,1,1,4,FV ), 0 , 162, 0 , 4808 , 188, 136), // #936 - INST(Vfmaddsub231ps , VexRvm_Lx , V(660F38,B6,_,x,0,0,4,FV ), 0 , 163, 0 , 4823 , 189, 136), // #937 - INST(Vfmaddsubpd , Fma4_Lx , V(660F3A,5D,_,x,x,_,_,_ ), 0 , 72 , 0 , 4838 , 263, 138), // #938 - INST(Vfmaddsubps , Fma4_Lx , V(660F3A,5C,_,x,x,_,_,_ ), 0 , 72 , 0 , 4850 , 263, 138), // #939 - INST(Vfmsub132pd , VexRvm_Lx , V(660F38,9A,_,x,1,1,4,FV ), 0 , 162, 0 , 4862 , 188, 136), // #940 - INST(Vfmsub132ps , VexRvm_Lx , V(660F38,9A,_,x,0,0,4,FV ), 0 , 163, 0 , 4874 , 189, 136), // #941 - INST(Vfmsub132sd , VexRvm , V(660F38,9B,_,I,1,1,3,T1S), 0 , 164, 0 , 4886 , 190, 137), // #942 - INST(Vfmsub132ss , VexRvm , V(660F38,9B,_,I,0,0,2,T1S), 0 , 121, 0 , 4898 , 191, 137), // #943 - INST(Vfmsub213pd , VexRvm_Lx , V(660F38,AA,_,x,1,1,4,FV ), 0 , 162, 0 , 4910 , 188, 136), // #944 - INST(Vfmsub213ps , VexRvm_Lx , V(660F38,AA,_,x,0,0,4,FV ), 0 , 163, 0 , 4922 , 189, 136), // #945 - INST(Vfmsub213sd , VexRvm , V(660F38,AB,_,I,1,1,3,T1S), 0 , 164, 0 , 4934 , 190, 137), // #946 - INST(Vfmsub213ss , VexRvm , V(660F38,AB,_,I,0,0,2,T1S), 0 , 121, 0 , 4946 , 191, 137), // #947 - INST(Vfmsub231pd , VexRvm_Lx , V(660F38,BA,_,x,1,1,4,FV ), 0 , 162, 0 , 4958 , 188, 136), // #948 - INST(Vfmsub231ps , VexRvm_Lx , V(660F38,BA,_,x,0,0,4,FV ), 0 , 163, 0 , 4970 , 189, 136), // #949 - INST(Vfmsub231sd , VexRvm , V(660F38,BB,_,I,1,1,3,T1S), 0 , 164, 0 , 4982 , 190, 137), // #950 - INST(Vfmsub231ss , VexRvm , V(660F38,BB,_,I,0,0,2,T1S), 0 , 121, 0 , 4994 , 191, 137), // #951 - INST(Vfmsubadd132pd , VexRvm_Lx , V(660F38,97,_,x,1,1,4,FV ), 0 , 162, 0 , 5006 , 188, 136), // #952 - INST(Vfmsubadd132ps , VexRvm_Lx , V(660F38,97,_,x,0,0,4,FV ), 0 , 163, 0 , 5021 , 189, 136), // #953 - INST(Vfmsubadd213pd , VexRvm_Lx , V(660F38,A7,_,x,1,1,4,FV ), 0 , 162, 0 , 5036 , 188, 136), // #954 - INST(Vfmsubadd213ps , VexRvm_Lx , V(660F38,A7,_,x,0,0,4,FV ), 0 , 163, 0 , 5051 , 189, 136), // #955 - INST(Vfmsubadd231pd , VexRvm_Lx , V(660F38,B7,_,x,1,1,4,FV ), 0 , 162, 0 , 5066 , 188, 136), // #956 - INST(Vfmsubadd231ps , VexRvm_Lx , V(660F38,B7,_,x,0,0,4,FV ), 0 , 163, 0 , 5081 , 189, 136), // #957 - INST(Vfmsubaddpd , Fma4_Lx , V(660F3A,5F,_,x,x,_,_,_ ), 0 , 72 , 0 , 5096 , 263, 138), // #958 - INST(Vfmsubaddps , Fma4_Lx , V(660F3A,5E,_,x,x,_,_,_ ), 0 , 72 , 0 , 5108 , 263, 138), // #959 - INST(Vfmsubpd , Fma4_Lx , V(660F3A,6D,_,x,x,_,_,_ ), 0 , 72 , 0 , 5120 , 263, 138), // #960 - INST(Vfmsubps , Fma4_Lx , V(660F3A,6C,_,x,x,_,_,_ ), 0 , 72 , 0 , 5129 , 263, 138), // #961 - INST(Vfmsubsd , Fma4 , V(660F3A,6F,_,0,x,_,_,_ ), 0 , 72 , 0 , 5138 , 264, 138), // #962 - INST(Vfmsubss , Fma4 , V(660F3A,6E,_,0,x,_,_,_ ), 0 , 72 , 0 , 5147 , 265, 138), // #963 - INST(Vfnmadd132pd , VexRvm_Lx , V(660F38,9C,_,x,1,1,4,FV ), 0 , 162, 0 , 5156 , 188, 136), // #964 - INST(Vfnmadd132ps , VexRvm_Lx , V(660F38,9C,_,x,0,0,4,FV ), 0 , 163, 0 , 5169 , 189, 136), // #965 - INST(Vfnmadd132sd , VexRvm , V(660F38,9D,_,I,1,1,3,T1S), 0 , 164, 0 , 5182 , 190, 137), // #966 - INST(Vfnmadd132ss , VexRvm , V(660F38,9D,_,I,0,0,2,T1S), 0 , 121, 0 , 5195 , 191, 137), // #967 - INST(Vfnmadd213pd , VexRvm_Lx , V(660F38,AC,_,x,1,1,4,FV ), 0 , 162, 0 , 5208 , 188, 136), // #968 - INST(Vfnmadd213ps , VexRvm_Lx , V(660F38,AC,_,x,0,0,4,FV ), 0 , 163, 0 , 5221 , 189, 136), // #969 - INST(Vfnmadd213sd , VexRvm , V(660F38,AD,_,I,1,1,3,T1S), 0 , 164, 0 , 5234 , 190, 137), // #970 - INST(Vfnmadd213ss , VexRvm , V(660F38,AD,_,I,0,0,2,T1S), 0 , 121, 0 , 5247 , 191, 137), // #971 - INST(Vfnmadd231pd , VexRvm_Lx , V(660F38,BC,_,x,1,1,4,FV ), 0 , 162, 0 , 5260 , 188, 136), // #972 - INST(Vfnmadd231ps , VexRvm_Lx , V(660F38,BC,_,x,0,0,4,FV ), 0 , 163, 0 , 5273 , 189, 136), // #973 - INST(Vfnmadd231sd , VexRvm , V(660F38,BC,_,I,1,1,3,T1S), 0 , 164, 0 , 5286 , 190, 137), // #974 - INST(Vfnmadd231ss , VexRvm , V(660F38,BC,_,I,0,0,2,T1S), 0 , 121, 0 , 5299 , 191, 137), // #975 - INST(Vfnmaddpd , Fma4_Lx , V(660F3A,79,_,x,x,_,_,_ ), 0 , 72 , 0 , 5312 , 263, 138), // #976 - INST(Vfnmaddps , Fma4_Lx , V(660F3A,78,_,x,x,_,_,_ ), 0 , 72 , 0 , 5322 , 263, 138), // #977 - INST(Vfnmaddsd , Fma4 , V(660F3A,7B,_,0,x,_,_,_ ), 0 , 72 , 0 , 5332 , 264, 138), // #978 - INST(Vfnmaddss , Fma4 , V(660F3A,7A,_,0,x,_,_,_ ), 0 , 72 , 0 , 5342 , 265, 138), // #979 - INST(Vfnmsub132pd , VexRvm_Lx , V(660F38,9E,_,x,1,1,4,FV ), 0 , 162, 0 , 5352 , 188, 136), // #980 - INST(Vfnmsub132ps , VexRvm_Lx , V(660F38,9E,_,x,0,0,4,FV ), 0 , 163, 0 , 5365 , 189, 136), // #981 - INST(Vfnmsub132sd , VexRvm , V(660F38,9F,_,I,1,1,3,T1S), 0 , 164, 0 , 5378 , 190, 137), // #982 - INST(Vfnmsub132ss , VexRvm , V(660F38,9F,_,I,0,0,2,T1S), 0 , 121, 0 , 5391 , 191, 137), // #983 - INST(Vfnmsub213pd , VexRvm_Lx , V(660F38,AE,_,x,1,1,4,FV ), 0 , 162, 0 , 5404 , 188, 136), // #984 - INST(Vfnmsub213ps , VexRvm_Lx , V(660F38,AE,_,x,0,0,4,FV ), 0 , 163, 0 , 5417 , 189, 136), // #985 - INST(Vfnmsub213sd , VexRvm , V(660F38,AF,_,I,1,1,3,T1S), 0 , 164, 0 , 5430 , 190, 137), // #986 - INST(Vfnmsub213ss , VexRvm , V(660F38,AF,_,I,0,0,2,T1S), 0 , 121, 0 , 5443 , 191, 137), // #987 - INST(Vfnmsub231pd , VexRvm_Lx , V(660F38,BE,_,x,1,1,4,FV ), 0 , 162, 0 , 5456 , 188, 136), // #988 - INST(Vfnmsub231ps , VexRvm_Lx , V(660F38,BE,_,x,0,0,4,FV ), 0 , 163, 0 , 5469 , 189, 136), // #989 - INST(Vfnmsub231sd , VexRvm , V(660F38,BF,_,I,1,1,3,T1S), 0 , 164, 0 , 5482 , 190, 137), // #990 - INST(Vfnmsub231ss , VexRvm , V(660F38,BF,_,I,0,0,2,T1S), 0 , 121, 0 , 5495 , 191, 137), // #991 - INST(Vfnmsubpd , Fma4_Lx , V(660F3A,7D,_,x,x,_,_,_ ), 0 , 72 , 0 , 5508 , 263, 138), // #992 - INST(Vfnmsubps , Fma4_Lx , V(660F3A,7C,_,x,x,_,_,_ ), 0 , 72 , 0 , 5518 , 263, 138), // #993 - INST(Vfnmsubsd , Fma4 , V(660F3A,7F,_,0,x,_,_,_ ), 0 , 72 , 0 , 5528 , 264, 138), // #994 - INST(Vfnmsubss , Fma4 , V(660F3A,7E,_,0,x,_,_,_ ), 0 , 72 , 0 , 5538 , 265, 138), // #995 - INST(Vfpclasspd , VexRmi_Lx , E(660F3A,66,_,x,_,1,4,FV ), 0 , 109, 0 , 5548 , 266, 129), // #996 - INST(Vfpclassps , VexRmi_Lx , E(660F3A,66,_,x,_,0,4,FV ), 0 , 108, 0 , 5559 , 267, 129), // #997 - INST(Vfpclasssd , VexRmi_Lx , E(660F3A,67,_,I,_,1,3,T1S), 0 , 160, 0 , 5570 , 268, 64 ), // #998 - INST(Vfpclassss , VexRmi_Lx , E(660F3A,67,_,I,_,0,2,T1S), 0 , 161, 0 , 5581 , 269, 64 ), // #999 - INST(Vfrczpd , VexRm_Lx , V(XOP_M9,81,_,x,0,_,_,_ ), 0 , 77 , 0 , 5592 , 270, 139), // #1000 - INST(Vfrczps , VexRm_Lx , V(XOP_M9,80,_,x,0,_,_,_ ), 0 , 77 , 0 , 5600 , 270, 139), // #1001 - INST(Vfrczsd , VexRm , V(XOP_M9,83,_,0,0,_,_,_ ), 0 , 77 , 0 , 5608 , 271, 139), // #1002 - INST(Vfrczss , VexRm , V(XOP_M9,82,_,0,0,_,_,_ ), 0 , 77 , 0 , 5616 , 272, 139), // #1003 - INST(Vgatherdpd , VexRmvRm_VM , V(660F38,92,_,x,1,_,_,_ ), V(660F38,92,_,x,_,1,3,T1S), 165, 79 , 5624 , 273, 140), // #1004 - INST(Vgatherdps , VexRmvRm_VM , V(660F38,92,_,x,0,_,_,_ ), V(660F38,92,_,x,_,0,2,T1S), 96 , 80 , 5635 , 274, 140), // #1005 - INST(Vgatherpf0dpd , VexM_VM , E(660F38,C6,1,2,_,1,3,T1S), 0 , 166, 0 , 5646 , 275, 141), // #1006 - INST(Vgatherpf0dps , VexM_VM , E(660F38,C6,1,2,_,0,2,T1S), 0 , 167, 0 , 5660 , 276, 141), // #1007 - INST(Vgatherpf0qpd , VexM_VM , E(660F38,C7,1,2,_,1,3,T1S), 0 , 166, 0 , 5674 , 277, 141), // #1008 - INST(Vgatherpf0qps , VexM_VM , E(660F38,C7,1,2,_,0,2,T1S), 0 , 167, 0 , 5688 , 277, 141), // #1009 - INST(Vgatherpf1dpd , VexM_VM , E(660F38,C6,2,2,_,1,3,T1S), 0 , 168, 0 , 5702 , 275, 141), // #1010 - INST(Vgatherpf1dps , VexM_VM , E(660F38,C6,2,2,_,0,2,T1S), 0 , 169, 0 , 5716 , 276, 141), // #1011 - INST(Vgatherpf1qpd , VexM_VM , E(660F38,C7,2,2,_,1,3,T1S), 0 , 168, 0 , 5730 , 277, 141), // #1012 - INST(Vgatherpf1qps , VexM_VM , E(660F38,C7,2,2,_,0,2,T1S), 0 , 169, 0 , 5744 , 277, 141), // #1013 - INST(Vgatherqpd , VexRmvRm_VM , V(660F38,93,_,x,1,_,_,_ ), V(660F38,93,_,x,_,1,3,T1S), 165, 81 , 5758 , 278, 140), // #1014 - INST(Vgatherqps , VexRmvRm_VM , V(660F38,93,_,x,0,_,_,_ ), V(660F38,93,_,x,_,0,2,T1S), 96 , 82 , 5769 , 279, 140), // #1015 - INST(Vgetexppd , VexRm_Lx , E(660F38,42,_,x,_,1,4,FV ), 0 , 112, 0 , 5780 , 239, 126), // #1016 - INST(Vgetexpps , VexRm_Lx , E(660F38,42,_,x,_,0,4,FV ), 0 , 111, 0 , 5790 , 243, 126), // #1017 - INST(Vgetexpsd , VexRvm , E(660F38,43,_,I,_,1,3,T1S), 0 , 124, 0 , 5800 , 280, 66 ), // #1018 - INST(Vgetexpss , VexRvm , E(660F38,43,_,I,_,0,2,T1S), 0 , 125, 0 , 5810 , 281, 66 ), // #1019 - INST(Vgetmantpd , VexRmi_Lx , E(660F3A,26,_,x,_,1,4,FV ), 0 , 109, 0 , 5820 , 282, 126), // #1020 - INST(Vgetmantps , VexRmi_Lx , E(660F3A,26,_,x,_,0,4,FV ), 0 , 108, 0 , 5831 , 283, 126), // #1021 - INST(Vgetmantsd , VexRvmi , E(660F3A,27,_,I,_,1,3,T1S), 0 , 160, 0 , 5842 , 261, 66 ), // #1022 - INST(Vgetmantss , VexRvmi , E(660F3A,27,_,I,_,0,2,T1S), 0 , 161, 0 , 5853 , 262, 66 ), // #1023 - INST(Vgf2p8affineinvqb, VexRvmi_Lx , V(660F3A,CF,_,x,1,1,4,FV ), 0 , 170, 0 , 5864 , 284, 142), // #1024 - INST(Vgf2p8affineqb , VexRvmi_Lx , V(660F3A,CE,_,x,1,1,4,FV ), 0 , 170, 0 , 5882 , 284, 142), // #1025 - INST(Vgf2p8mulb , VexRvm_Lx , V(660F38,CF,_,x,0,0,4,FV ), 0 , 163, 0 , 5897 , 285, 142), // #1026 - INST(Vhaddpd , VexRvm_Lx , V(660F00,7C,_,x,I,_,_,_ ), 0 , 68 , 0 , 5908 , 192, 123), // #1027 - INST(Vhaddps , VexRvm_Lx , V(F20F00,7C,_,x,I,_,_,_ ), 0 , 106, 0 , 5916 , 192, 123), // #1028 - INST(Vhsubpd , VexRvm_Lx , V(660F00,7D,_,x,I,_,_,_ ), 0 , 68 , 0 , 5924 , 192, 123), // #1029 - INST(Vhsubps , VexRvm_Lx , V(F20F00,7D,_,x,I,_,_,_ ), 0 , 106, 0 , 5932 , 192, 123), // #1030 - INST(Vinsertf128 , VexRvmi , V(660F3A,18,_,1,0,_,_,_ ), 0 , 154, 0 , 5940 , 286, 123), // #1031 - INST(Vinsertf32x4 , VexRvmi_Lx , E(660F3A,18,_,x,_,0,4,T4 ), 0 , 155, 0 , 5952 , 287, 126), // #1032 - INST(Vinsertf32x8 , VexRvmi , E(660F3A,1A,_,2,_,0,5,T8 ), 0 , 156, 0 , 5965 , 288, 64 ), // #1033 - INST(Vinsertf64x2 , VexRvmi_Lx , E(660F3A,18,_,x,_,1,4,T2 ), 0 , 157, 0 , 5978 , 287, 129), // #1034 - INST(Vinsertf64x4 , VexRvmi , E(660F3A,1A,_,2,_,1,5,T4 ), 0 , 158, 0 , 5991 , 288, 66 ), // #1035 - INST(Vinserti128 , VexRvmi , V(660F3A,38,_,1,0,_,_,_ ), 0 , 154, 0 , 6004 , 286, 130), // #1036 - INST(Vinserti32x4 , VexRvmi_Lx , E(660F3A,38,_,x,_,0,4,T4 ), 0 , 155, 0 , 6016 , 287, 126), // #1037 - INST(Vinserti32x8 , VexRvmi , E(660F3A,3A,_,2,_,0,5,T8 ), 0 , 156, 0 , 6029 , 288, 64 ), // #1038 - INST(Vinserti64x2 , VexRvmi_Lx , E(660F3A,38,_,x,_,1,4,T2 ), 0 , 157, 0 , 6042 , 287, 129), // #1039 - INST(Vinserti64x4 , VexRvmi , E(660F3A,3A,_,2,_,1,5,T4 ), 0 , 158, 0 , 6055 , 288, 66 ), // #1040 - INST(Vinsertps , VexRvmi , V(660F3A,21,_,0,I,0,2,T1S), 0 , 159, 0 , 6068 , 289, 122), // #1041 - INST(Vlddqu , VexRm_Lx , V(F20F00,F0,_,x,I,_,_,_ ), 0 , 106, 0 , 6078 , 290, 123), // #1042 - INST(Vldmxcsr , VexM , V(000F00,AE,2,0,I,_,_,_ ), 0 , 171, 0 , 6085 , 291, 123), // #1043 - INST(Vmaskmovdqu , VexRm_ZDI , V(660F00,F7,_,0,I,_,_,_ ), 0 , 68 , 0 , 6094 , 292, 123), // #1044 - INST(Vmaskmovpd , VexRvmMvr_Lx , V(660F38,2D,_,x,0,_,_,_ ), V(660F38,2F,_,x,0,_,_,_ ), 96 , 83 , 6106 , 293, 123), // #1045 - INST(Vmaskmovps , VexRvmMvr_Lx , V(660F38,2C,_,x,0,_,_,_ ), V(660F38,2E,_,x,0,_,_,_ ), 96 , 84 , 6117 , 293, 123), // #1046 - INST(Vmaxpd , VexRvm_Lx , V(660F00,5F,_,x,I,1,4,FV ), 0 , 102, 0 , 6128 , 294, 121), // #1047 - INST(Vmaxps , VexRvm_Lx , V(000F00,5F,_,x,I,0,4,FV ), 0 , 103, 0 , 6135 , 295, 121), // #1048 - INST(Vmaxsd , VexRvm , V(F20F00,5F,_,I,I,1,3,T1S), 0 , 104, 0 , 6142 , 296, 121), // #1049 - INST(Vmaxss , VexRvm , V(F30F00,5F,_,I,I,0,2,T1S), 0 , 105, 0 , 6149 , 235, 121), // #1050 - INST(Vmcall , X86Op , O(000F01,C1,_,_,_,_,_,_ ), 0 , 21 , 0 , 6156 , 30 , 56 ), // #1051 - INST(Vmclear , X86M_Only , O(660F00,C7,6,_,_,_,_,_ ), 0 , 25 , 0 , 6163 , 32 , 56 ), // #1052 - INST(Vmfunc , X86Op , O(000F01,D4,_,_,_,_,_,_ ), 0 , 21 , 0 , 6171 , 30 , 56 ), // #1053 - INST(Vminpd , VexRvm_Lx , V(660F00,5D,_,x,I,1,4,FV ), 0 , 102, 0 , 6178 , 294, 121), // #1054 - INST(Vminps , VexRvm_Lx , V(000F00,5D,_,x,I,0,4,FV ), 0 , 103, 0 , 6185 , 295, 121), // #1055 - INST(Vminsd , VexRvm , V(F20F00,5D,_,I,I,1,3,T1S), 0 , 104, 0 , 6192 , 296, 121), // #1056 - INST(Vminss , VexRvm , V(F30F00,5D,_,I,I,0,2,T1S), 0 , 105, 0 , 6199 , 235, 121), // #1057 - INST(Vmlaunch , X86Op , O(000F01,C2,_,_,_,_,_,_ ), 0 , 21 , 0 , 6206 , 30 , 56 ), // #1058 - INST(Vmload , X86Op_xAX , O(000F01,DA,_,_,_,_,_,_ ), 0 , 21 , 0 , 6215 , 297, 22 ), // #1059 - INST(Vmmcall , X86Op , O(000F01,D9,_,_,_,_,_,_ ), 0 , 21 , 0 , 6222 , 30 , 22 ), // #1060 - INST(Vmovapd , VexRmMr_Lx , V(660F00,28,_,x,I,1,4,FVM), V(660F00,29,_,x,I,1,4,FVM), 172, 85 , 6230 , 298, 121), // #1061 - INST(Vmovaps , VexRmMr_Lx , V(000F00,28,_,x,I,0,4,FVM), V(000F00,29,_,x,I,0,4,FVM), 173, 86 , 6238 , 298, 121), // #1062 - INST(Vmovd , VexMovdMovq , V(660F00,6E,_,0,0,0,2,T1S), V(660F00,7E,_,0,0,0,2,T1S), 174, 87 , 6246 , 299, 122), // #1063 - INST(Vmovddup , VexRm_Lx , V(F20F00,12,_,x,I,1,3,DUP), 0 , 175, 0 , 6252 , 300, 121), // #1064 - INST(Vmovdqa , VexRmMr_Lx , V(660F00,6F,_,x,I,_,_,_ ), V(660F00,7F,_,x,I,_,_,_ ), 68 , 88 , 6261 , 301, 123), // #1065 - INST(Vmovdqa32 , VexRmMr_Lx , E(660F00,6F,_,x,_,0,4,FVM), E(660F00,7F,_,x,_,0,4,FVM), 176, 89 , 6269 , 302, 126), // #1066 - INST(Vmovdqa64 , VexRmMr_Lx , E(660F00,6F,_,x,_,1,4,FVM), E(660F00,7F,_,x,_,1,4,FVM), 177, 90 , 6279 , 302, 126), // #1067 - INST(Vmovdqu , VexRmMr_Lx , V(F30F00,6F,_,x,I,_,_,_ ), V(F30F00,7F,_,x,I,_,_,_ ), 178, 91 , 6289 , 301, 123), // #1068 - INST(Vmovdqu16 , VexRmMr_Lx , E(F20F00,6F,_,x,_,1,4,FVM), E(F20F00,7F,_,x,_,1,4,FVM), 179, 92 , 6297 , 302, 128), // #1069 - INST(Vmovdqu32 , VexRmMr_Lx , E(F30F00,6F,_,x,_,0,4,FVM), E(F30F00,7F,_,x,_,0,4,FVM), 180, 93 , 6307 , 302, 126), // #1070 - INST(Vmovdqu64 , VexRmMr_Lx , E(F30F00,6F,_,x,_,1,4,FVM), E(F30F00,7F,_,x,_,1,4,FVM), 181, 94 , 6317 , 302, 126), // #1071 - INST(Vmovdqu8 , VexRmMr_Lx , E(F20F00,6F,_,x,_,0,4,FVM), E(F20F00,7F,_,x,_,0,4,FVM), 182, 95 , 6327 , 302, 128), // #1072 - INST(Vmovhlps , VexRvm , V(000F00,12,_,0,I,0,_,_ ), 0 , 71 , 0 , 6336 , 303, 122), // #1073 - INST(Vmovhpd , VexRvmMr , V(660F00,16,_,0,I,1,3,T1S), V(660F00,17,_,0,I,1,3,T1S), 122, 96 , 6345 , 304, 122), // #1074 - INST(Vmovhps , VexRvmMr , V(000F00,16,_,0,I,0,3,T2 ), V(000F00,17,_,0,I,0,3,T2 ), 183, 97 , 6353 , 304, 122), // #1075 - INST(Vmovlhps , VexRvm , V(000F00,16,_,0,I,0,_,_ ), 0 , 71 , 0 , 6361 , 303, 122), // #1076 - INST(Vmovlpd , VexRvmMr , V(660F00,12,_,0,I,1,3,T1S), V(660F00,13,_,0,I,1,3,T1S), 122, 98 , 6370 , 304, 122), // #1077 - INST(Vmovlps , VexRvmMr , V(000F00,12,_,0,I,0,3,T2 ), V(000F00,13,_,0,I,0,3,T2 ), 183, 99 , 6378 , 304, 122), // #1078 - INST(Vmovmskpd , VexRm_Lx , V(660F00,50,_,x,I,_,_,_ ), 0 , 68 , 0 , 6386 , 305, 123), // #1079 - INST(Vmovmskps , VexRm_Lx , V(000F00,50,_,x,I,_,_,_ ), 0 , 71 , 0 , 6396 , 305, 123), // #1080 - INST(Vmovntdq , VexMr_Lx , V(660F00,E7,_,x,I,0,4,FVM), 0 , 184, 0 , 6406 , 306, 121), // #1081 - INST(Vmovntdqa , VexRm_Lx , V(660F38,2A,_,x,I,0,4,FVM), 0 , 107, 0 , 6415 , 307, 131), // #1082 - INST(Vmovntpd , VexMr_Lx , V(660F00,2B,_,x,I,1,4,FVM), 0 , 172, 0 , 6425 , 306, 121), // #1083 - INST(Vmovntps , VexMr_Lx , V(000F00,2B,_,x,I,0,4,FVM), 0 , 173, 0 , 6434 , 306, 121), // #1084 - INST(Vmovq , VexMovdMovq , V(660F00,6E,_,0,I,1,3,T1S), V(660F00,7E,_,0,I,1,3,T1S), 122, 100, 6443 , 308, 122), // #1085 - INST(Vmovsd , VexMovssMovsd , V(F20F00,10,_,I,I,1,3,T1S), V(F20F00,11,_,I,I,1,3,T1S), 104, 101, 6449 , 309, 122), // #1086 - INST(Vmovshdup , VexRm_Lx , V(F30F00,16,_,x,I,0,4,FVM), 0 , 185, 0 , 6456 , 310, 121), // #1087 - INST(Vmovsldup , VexRm_Lx , V(F30F00,12,_,x,I,0,4,FVM), 0 , 185, 0 , 6466 , 310, 121), // #1088 - INST(Vmovss , VexMovssMovsd , V(F30F00,10,_,I,I,0,2,T1S), V(F30F00,11,_,I,I,0,2,T1S), 105, 102, 6476 , 311, 122), // #1089 - INST(Vmovupd , VexRmMr_Lx , V(660F00,10,_,x,I,1,4,FVM), V(660F00,11,_,x,I,1,4,FVM), 172, 103, 6483 , 298, 121), // #1090 - INST(Vmovups , VexRmMr_Lx , V(000F00,10,_,x,I,0,4,FVM), V(000F00,11,_,x,I,0,4,FVM), 173, 104, 6491 , 298, 121), // #1091 - INST(Vmpsadbw , VexRvmi_Lx , V(660F3A,42,_,x,I,_,_,_ ), 0 , 72 , 0 , 6499 , 205, 143), // #1092 - INST(Vmptrld , X86M_Only , O(000F00,C7,6,_,_,_,_,_ ), 0 , 78 , 0 , 6508 , 32 , 56 ), // #1093 - INST(Vmptrst , X86M_Only , O(000F00,C7,7,_,_,_,_,_ ), 0 , 22 , 0 , 6516 , 32 , 56 ), // #1094 - INST(Vmread , X86Mr_NoSize , O(000F00,78,_,_,_,_,_,_ ), 0 , 4 , 0 , 6524 , 312, 56 ), // #1095 - INST(Vmresume , X86Op , O(000F01,C3,_,_,_,_,_,_ ), 0 , 21 , 0 , 6531 , 30 , 56 ), // #1096 - INST(Vmrun , X86Op_xAX , O(000F01,D8,_,_,_,_,_,_ ), 0 , 21 , 0 , 6540 , 297, 22 ), // #1097 - INST(Vmsave , X86Op_xAX , O(000F01,DB,_,_,_,_,_,_ ), 0 , 21 , 0 , 6546 , 297, 22 ), // #1098 - INST(Vmulpd , VexRvm_Lx , V(660F00,59,_,x,I,1,4,FV ), 0 , 102, 0 , 6553 , 188, 121), // #1099 - INST(Vmulps , VexRvm_Lx , V(000F00,59,_,x,I,0,4,FV ), 0 , 103, 0 , 6560 , 189, 121), // #1100 - INST(Vmulsd , VexRvm_Lx , V(F20F00,59,_,I,I,1,3,T1S), 0 , 104, 0 , 6567 , 190, 122), // #1101 - INST(Vmulss , VexRvm_Lx , V(F30F00,59,_,I,I,0,2,T1S), 0 , 105, 0 , 6574 , 191, 122), // #1102 - INST(Vmwrite , X86Rm_NoSize , O(000F00,79,_,_,_,_,_,_ ), 0 , 4 , 0 , 6581 , 313, 56 ), // #1103 - INST(Vmxon , X86M_Only , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 24 , 0 , 6589 , 32 , 56 ), // #1104 - INST(Vorpd , VexRvm_Lx , V(660F00,56,_,x,I,1,4,FV ), 0 , 102, 0 , 6595 , 200, 127), // #1105 - INST(Vorps , VexRvm_Lx , V(000F00,56,_,x,I,0,4,FV ), 0 , 103, 0 , 6601 , 201, 127), // #1106 - INST(Vp2intersectd , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,0,4,FV ), 0 , 186, 0 , 6607 , 314, 144), // #1107 - INST(Vp2intersectq , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,1,4,FV ), 0 , 187, 0 , 6621 , 315, 144), // #1108 - INST(Vp4dpwssd , VexRm_T1_4X , E(F20F38,52,_,2,_,0,2,T4X), 0 , 101, 0 , 6635 , 186, 145), // #1109 - INST(Vp4dpwssds , VexRm_T1_4X , E(F20F38,53,_,2,_,0,2,T4X), 0 , 101, 0 , 6645 , 186, 145), // #1110 - INST(Vpabsb , VexRm_Lx , V(660F38,1C,_,x,I,_,4,FVM), 0 , 107, 0 , 6656 , 310, 146), // #1111 - INST(Vpabsd , VexRm_Lx , V(660F38,1E,_,x,I,0,4,FV ), 0 , 163, 0 , 6663 , 310, 131), // #1112 - INST(Vpabsq , VexRm_Lx , E(660F38,1F,_,x,_,1,4,FV ), 0 , 112, 0 , 6670 , 254, 126), // #1113 - INST(Vpabsw , VexRm_Lx , V(660F38,1D,_,x,I,_,4,FVM), 0 , 107, 0 , 6677 , 310, 146), // #1114 - INST(Vpackssdw , VexRvm_Lx , V(660F00,6B,_,x,I,0,4,FV ), 0 , 133, 0 , 6684 , 199, 146), // #1115 - INST(Vpacksswb , VexRvm_Lx , V(660F00,63,_,x,I,I,4,FVM), 0 , 184, 0 , 6694 , 285, 146), // #1116 - INST(Vpackusdw , VexRvm_Lx , V(660F38,2B,_,x,I,0,4,FV ), 0 , 163, 0 , 6704 , 199, 146), // #1117 - INST(Vpackuswb , VexRvm_Lx , V(660F00,67,_,x,I,I,4,FVM), 0 , 184, 0 , 6714 , 285, 146), // #1118 - INST(Vpaddb , VexRvm_Lx , V(660F00,FC,_,x,I,I,4,FVM), 0 , 184, 0 , 6724 , 285, 146), // #1119 - INST(Vpaddd , VexRvm_Lx , V(660F00,FE,_,x,I,0,4,FV ), 0 , 133, 0 , 6731 , 199, 131), // #1120 - INST(Vpaddq , VexRvm_Lx , V(660F00,D4,_,x,I,1,4,FV ), 0 , 102, 0 , 6738 , 198, 131), // #1121 - INST(Vpaddsb , VexRvm_Lx , V(660F00,EC,_,x,I,I,4,FVM), 0 , 184, 0 , 6745 , 285, 146), // #1122 - INST(Vpaddsw , VexRvm_Lx , V(660F00,ED,_,x,I,I,4,FVM), 0 , 184, 0 , 6753 , 285, 146), // #1123 - INST(Vpaddusb , VexRvm_Lx , V(660F00,DC,_,x,I,I,4,FVM), 0 , 184, 0 , 6761 , 285, 146), // #1124 - INST(Vpaddusw , VexRvm_Lx , V(660F00,DD,_,x,I,I,4,FVM), 0 , 184, 0 , 6770 , 285, 146), // #1125 - INST(Vpaddw , VexRvm_Lx , V(660F00,FD,_,x,I,I,4,FVM), 0 , 184, 0 , 6779 , 285, 146), // #1126 - INST(Vpalignr , VexRvmi_Lx , V(660F3A,0F,_,x,I,I,4,FVM), 0 , 188, 0 , 6786 , 284, 146), // #1127 - INST(Vpand , VexRvm_Lx , V(660F00,DB,_,x,I,_,_,_ ), 0 , 68 , 0 , 6795 , 316, 143), // #1128 - INST(Vpandd , VexRvm_Lx , E(660F00,DB,_,x,_,0,4,FV ), 0 , 189, 0 , 6801 , 317, 126), // #1129 - INST(Vpandn , VexRvm_Lx , V(660F00,DF,_,x,I,_,_,_ ), 0 , 68 , 0 , 6808 , 318, 143), // #1130 - INST(Vpandnd , VexRvm_Lx , E(660F00,DF,_,x,_,0,4,FV ), 0 , 189, 0 , 6815 , 319, 126), // #1131 - INST(Vpandnq , VexRvm_Lx , E(660F00,DF,_,x,_,1,4,FV ), 0 , 130, 0 , 6823 , 320, 126), // #1132 - INST(Vpandq , VexRvm_Lx , E(660F00,DB,_,x,_,1,4,FV ), 0 , 130, 0 , 6831 , 321, 126), // #1133 - INST(Vpavgb , VexRvm_Lx , V(660F00,E0,_,x,I,I,4,FVM), 0 , 184, 0 , 6838 , 285, 146), // #1134 - INST(Vpavgw , VexRvm_Lx , V(660F00,E3,_,x,I,I,4,FVM), 0 , 184, 0 , 6845 , 285, 146), // #1135 - INST(Vpblendd , VexRvmi_Lx , V(660F3A,02,_,x,0,_,_,_ ), 0 , 72 , 0 , 6852 , 205, 130), // #1136 - INST(Vpblendvb , VexRvmr , V(660F3A,4C,_,x,0,_,_,_ ), 0 , 72 , 0 , 6861 , 206, 143), // #1137 - INST(Vpblendw , VexRvmi_Lx , V(660F3A,0E,_,x,I,_,_,_ ), 0 , 72 , 0 , 6871 , 205, 143), // #1138 - INST(Vpbroadcastb , VexRm_Lx_Bcst , V(660F38,78,_,x,0,0,0,T1S), E(660F38,7A,_,x,0,0,0,T1S), 190, 105, 6880 , 322, 147), // #1139 - INST(Vpbroadcastd , VexRm_Lx_Bcst , V(660F38,58,_,x,0,0,2,T1S), E(660F38,7C,_,x,0,0,0,T1S), 121, 106, 6893 , 323, 140), // #1140 - INST(Vpbroadcastmb2d , VexRm_Lx , E(F30F38,3A,_,x,_,0,_,_ ), 0 , 128, 0 , 6906 , 324, 148), // #1141 - INST(Vpbroadcastmb2q , VexRm_Lx , E(F30F38,2A,_,x,_,1,_,_ ), 0 , 191, 0 , 6922 , 324, 148), // #1142 - INST(Vpbroadcastq , VexRm_Lx_Bcst , V(660F38,59,_,x,0,1,3,T1S), E(660F38,7C,_,x,0,1,0,T1S), 120, 107, 6938 , 325, 140), // #1143 - INST(Vpbroadcastw , VexRm_Lx_Bcst , V(660F38,79,_,x,0,0,1,T1S), E(660F38,7B,_,x,0,0,0,T1S), 192, 108, 6951 , 326, 147), // #1144 - INST(Vpclmulqdq , VexRvmi_Lx , V(660F3A,44,_,x,I,_,4,FVM), 0 , 188, 0 , 6964 , 327, 149), // #1145 - INST(Vpcmov , VexRvrmRvmr_Lx , V(XOP_M8,A2,_,x,x,_,_,_ ), 0 , 193, 0 , 6975 , 263, 139), // #1146 - INST(Vpcmpb , VexRvmi_Lx , E(660F3A,3F,_,x,_,0,4,FVM), 0 , 151, 0 , 6982 , 328, 128), // #1147 - INST(Vpcmpd , VexRvmi_Lx , E(660F3A,1F,_,x,_,0,4,FV ), 0 , 108, 0 , 6989 , 329, 126), // #1148 - INST(Vpcmpeqb , VexRvm_Lx , V(660F00,74,_,x,I,I,4,FV ), 0 , 133, 0 , 6996 , 330, 146), // #1149 - INST(Vpcmpeqd , VexRvm_Lx , V(660F00,76,_,x,I,0,4,FVM), 0 , 184, 0 , 7005 , 331, 131), // #1150 - INST(Vpcmpeqq , VexRvm_Lx , V(660F38,29,_,x,I,1,4,FVM), 0 , 194, 0 , 7014 , 332, 131), // #1151 - INST(Vpcmpeqw , VexRvm_Lx , V(660F00,75,_,x,I,I,4,FV ), 0 , 133, 0 , 7023 , 330, 146), // #1152 - INST(Vpcmpestri , VexRmi , V(660F3A,61,_,0,I,_,_,_ ), 0 , 72 , 0 , 7032 , 333, 150), // #1153 - INST(Vpcmpestrm , VexRmi , V(660F3A,60,_,0,I,_,_,_ ), 0 , 72 , 0 , 7043 , 334, 150), // #1154 - INST(Vpcmpgtb , VexRvm_Lx , V(660F00,64,_,x,I,I,4,FV ), 0 , 133, 0 , 7054 , 330, 146), // #1155 - INST(Vpcmpgtd , VexRvm_Lx , V(660F00,66,_,x,I,0,4,FVM), 0 , 184, 0 , 7063 , 331, 131), // #1156 - INST(Vpcmpgtq , VexRvm_Lx , V(660F38,37,_,x,I,1,4,FVM), 0 , 194, 0 , 7072 , 332, 131), // #1157 - INST(Vpcmpgtw , VexRvm_Lx , V(660F00,65,_,x,I,I,4,FV ), 0 , 133, 0 , 7081 , 330, 146), // #1158 - INST(Vpcmpistri , VexRmi , V(660F3A,63,_,0,I,_,_,_ ), 0 , 72 , 0 , 7090 , 335, 150), // #1159 - INST(Vpcmpistrm , VexRmi , V(660F3A,62,_,0,I,_,_,_ ), 0 , 72 , 0 , 7101 , 336, 150), // #1160 - INST(Vpcmpq , VexRvmi_Lx , E(660F3A,1F,_,x,_,1,4,FV ), 0 , 109, 0 , 7112 , 337, 126), // #1161 - INST(Vpcmpub , VexRvmi_Lx , E(660F3A,3E,_,x,_,0,4,FVM), 0 , 151, 0 , 7119 , 328, 128), // #1162 - INST(Vpcmpud , VexRvmi_Lx , E(660F3A,1E,_,x,_,0,4,FV ), 0 , 108, 0 , 7127 , 329, 126), // #1163 - INST(Vpcmpuq , VexRvmi_Lx , E(660F3A,1E,_,x,_,1,4,FV ), 0 , 109, 0 , 7135 , 337, 126), // #1164 - INST(Vpcmpuw , VexRvmi_Lx , E(660F3A,3E,_,x,_,1,4,FVM), 0 , 195, 0 , 7143 , 337, 128), // #1165 - INST(Vpcmpw , VexRvmi_Lx , E(660F3A,3F,_,x,_,1,4,FVM), 0 , 195, 0 , 7151 , 337, 128), // #1166 - INST(Vpcomb , VexRvmi , V(XOP_M8,CC,_,0,0,_,_,_ ), 0 , 193, 0 , 7158 , 251, 139), // #1167 - INST(Vpcomd , VexRvmi , V(XOP_M8,CE,_,0,0,_,_,_ ), 0 , 193, 0 , 7165 , 251, 139), // #1168 - INST(Vpcompressb , VexMr_Lx , E(660F38,63,_,x,_,0,0,T1S), 0 , 196, 0 , 7172 , 220, 151), // #1169 - INST(Vpcompressd , VexMr_Lx , E(660F38,8B,_,x,_,0,2,T1S), 0 , 125, 0 , 7184 , 220, 126), // #1170 - INST(Vpcompressq , VexMr_Lx , E(660F38,8B,_,x,_,1,3,T1S), 0 , 124, 0 , 7196 , 220, 126), // #1171 - INST(Vpcompressw , VexMr_Lx , E(660F38,63,_,x,_,1,1,T1S), 0 , 197, 0 , 7208 , 220, 151), // #1172 - INST(Vpcomq , VexRvmi , V(XOP_M8,CF,_,0,0,_,_,_ ), 0 , 193, 0 , 7220 , 251, 139), // #1173 - INST(Vpcomub , VexRvmi , V(XOP_M8,EC,_,0,0,_,_,_ ), 0 , 193, 0 , 7227 , 251, 139), // #1174 - INST(Vpcomud , VexRvmi , V(XOP_M8,EE,_,0,0,_,_,_ ), 0 , 193, 0 , 7235 , 251, 139), // #1175 - INST(Vpcomuq , VexRvmi , V(XOP_M8,EF,_,0,0,_,_,_ ), 0 , 193, 0 , 7243 , 251, 139), // #1176 - INST(Vpcomuw , VexRvmi , V(XOP_M8,ED,_,0,0,_,_,_ ), 0 , 193, 0 , 7251 , 251, 139), // #1177 - INST(Vpcomw , VexRvmi , V(XOP_M8,CD,_,0,0,_,_,_ ), 0 , 193, 0 , 7259 , 251, 139), // #1178 - INST(Vpconflictd , VexRm_Lx , E(660F38,C4,_,x,_,0,4,FV ), 0 , 111, 0 , 7266 , 338, 148), // #1179 - INST(Vpconflictq , VexRm_Lx , E(660F38,C4,_,x,_,1,4,FV ), 0 , 112, 0 , 7278 , 338, 148), // #1180 - INST(Vpdpbusd , VexRvm_Lx , E(660F38,50,_,x,_,0,4,FV ), 0 , 111, 0 , 7290 , 203, 152), // #1181 - INST(Vpdpbusds , VexRvm_Lx , E(660F38,51,_,x,_,0,4,FV ), 0 , 111, 0 , 7299 , 203, 152), // #1182 - INST(Vpdpwssd , VexRvm_Lx , E(660F38,52,_,x,_,0,4,FV ), 0 , 111, 0 , 7309 , 203, 152), // #1183 - INST(Vpdpwssds , VexRvm_Lx , E(660F38,53,_,x,_,0,4,FV ), 0 , 111, 0 , 7318 , 203, 152), // #1184 - INST(Vperm2f128 , VexRvmi , V(660F3A,06,_,1,0,_,_,_ ), 0 , 154, 0 , 7328 , 339, 123), // #1185 - INST(Vperm2i128 , VexRvmi , V(660F3A,46,_,1,0,_,_,_ ), 0 , 154, 0 , 7339 , 339, 130), // #1186 - INST(Vpermb , VexRvm_Lx , E(660F38,8D,_,x,_,0,4,FVM), 0 , 110, 0 , 7350 , 202, 153), // #1187 - INST(Vpermd , VexRvm_Lx , V(660F38,36,_,x,0,0,4,FV ), 0 , 163, 0 , 7357 , 340, 140), // #1188 - INST(Vpermi2b , VexRvm_Lx , E(660F38,75,_,x,_,0,4,FVM), 0 , 110, 0 , 7364 , 202, 153), // #1189 - INST(Vpermi2d , VexRvm_Lx , E(660F38,76,_,x,_,0,4,FV ), 0 , 111, 0 , 7373 , 203, 126), // #1190 - INST(Vpermi2pd , VexRvm_Lx , E(660F38,77,_,x,_,1,4,FV ), 0 , 112, 0 , 7382 , 204, 126), // #1191 - INST(Vpermi2ps , VexRvm_Lx , E(660F38,77,_,x,_,0,4,FV ), 0 , 111, 0 , 7392 , 203, 126), // #1192 - INST(Vpermi2q , VexRvm_Lx , E(660F38,76,_,x,_,1,4,FV ), 0 , 112, 0 , 7402 , 204, 126), // #1193 - INST(Vpermi2w , VexRvm_Lx , E(660F38,75,_,x,_,1,4,FVM), 0 , 113, 0 , 7411 , 202, 128), // #1194 - INST(Vpermil2pd , VexRvrmiRvmri_Lx , V(660F3A,49,_,x,x,_,_,_ ), 0 , 72 , 0 , 7420 , 341, 139), // #1195 - INST(Vpermil2ps , VexRvrmiRvmri_Lx , V(660F3A,48,_,x,x,_,_,_ ), 0 , 72 , 0 , 7431 , 341, 139), // #1196 - INST(Vpermilpd , VexRvmRmi_Lx , V(660F38,0D,_,x,0,1,4,FV ), V(660F3A,05,_,x,0,1,4,FV ), 198, 109, 7442 , 342, 121), // #1197 - INST(Vpermilps , VexRvmRmi_Lx , V(660F38,0C,_,x,0,0,4,FV ), V(660F3A,04,_,x,0,0,4,FV ), 163, 110, 7452 , 342, 121), // #1198 - INST(Vpermpd , VexRvmRmi_Lx , E(660F38,16,_,x,1,1,4,FV ), V(660F3A,01,_,x,1,1,4,FV ), 199, 111, 7462 , 343, 140), // #1199 - INST(Vpermps , VexRvm_Lx , V(660F38,16,_,x,0,0,4,FV ), 0 , 163, 0 , 7470 , 340, 140), // #1200 - INST(Vpermq , VexRvmRmi_Lx , V(660F38,36,_,x,_,1,4,FV ), V(660F3A,00,_,x,1,1,4,FV ), 198, 112, 7478 , 343, 140), // #1201 - INST(Vpermt2b , VexRvm_Lx , E(660F38,7D,_,x,_,0,4,FVM), 0 , 110, 0 , 7485 , 202, 153), // #1202 - INST(Vpermt2d , VexRvm_Lx , E(660F38,7E,_,x,_,0,4,FV ), 0 , 111, 0 , 7494 , 203, 126), // #1203 - INST(Vpermt2pd , VexRvm_Lx , E(660F38,7F,_,x,_,1,4,FV ), 0 , 112, 0 , 7503 , 204, 126), // #1204 - INST(Vpermt2ps , VexRvm_Lx , E(660F38,7F,_,x,_,0,4,FV ), 0 , 111, 0 , 7513 , 203, 126), // #1205 - INST(Vpermt2q , VexRvm_Lx , E(660F38,7E,_,x,_,1,4,FV ), 0 , 112, 0 , 7523 , 204, 126), // #1206 - INST(Vpermt2w , VexRvm_Lx , E(660F38,7D,_,x,_,1,4,FVM), 0 , 113, 0 , 7532 , 202, 128), // #1207 - INST(Vpermw , VexRvm_Lx , E(660F38,8D,_,x,_,1,4,FVM), 0 , 113, 0 , 7541 , 202, 128), // #1208 - INST(Vpexpandb , VexRm_Lx , E(660F38,62,_,x,_,0,0,T1S), 0 , 196, 0 , 7548 , 254, 151), // #1209 - INST(Vpexpandd , VexRm_Lx , E(660F38,89,_,x,_,0,2,T1S), 0 , 125, 0 , 7558 , 254, 126), // #1210 - INST(Vpexpandq , VexRm_Lx , E(660F38,89,_,x,_,1,3,T1S), 0 , 124, 0 , 7568 , 254, 126), // #1211 - INST(Vpexpandw , VexRm_Lx , E(660F38,62,_,x,_,1,1,T1S), 0 , 197, 0 , 7578 , 254, 151), // #1212 - INST(Vpextrb , VexMri , V(660F3A,14,_,0,0,I,0,T1S), 0 , 200, 0 , 7588 , 344, 154), // #1213 - INST(Vpextrd , VexMri , V(660F3A,16,_,0,0,0,2,T1S), 0 , 159, 0 , 7596 , 258, 155), // #1214 - INST(Vpextrq , VexMri , V(660F3A,16,_,0,1,1,3,T1S), 0 , 201, 0 , 7604 , 345, 155), // #1215 - INST(Vpextrw , VexMri , V(660F3A,15,_,0,0,I,1,T1S), 0 , 202, 0 , 7612 , 346, 154), // #1216 - INST(Vpgatherdd , VexRmvRm_VM , V(660F38,90,_,x,0,_,_,_ ), V(660F38,90,_,x,_,0,2,T1S), 96 , 113, 7620 , 274, 140), // #1217 - INST(Vpgatherdq , VexRmvRm_VM , V(660F38,90,_,x,1,_,_,_ ), V(660F38,90,_,x,_,1,3,T1S), 165, 114, 7631 , 273, 140), // #1218 - INST(Vpgatherqd , VexRmvRm_VM , V(660F38,91,_,x,0,_,_,_ ), V(660F38,91,_,x,_,0,2,T1S), 96 , 115, 7642 , 279, 140), // #1219 - INST(Vpgatherqq , VexRmvRm_VM , V(660F38,91,_,x,1,_,_,_ ), V(660F38,91,_,x,_,1,3,T1S), 165, 116, 7653 , 278, 140), // #1220 - INST(Vphaddbd , VexRm , V(XOP_M9,C2,_,0,0,_,_,_ ), 0 , 77 , 0 , 7664 , 194, 139), // #1221 - INST(Vphaddbq , VexRm , V(XOP_M9,C3,_,0,0,_,_,_ ), 0 , 77 , 0 , 7673 , 194, 139), // #1222 - INST(Vphaddbw , VexRm , V(XOP_M9,C1,_,0,0,_,_,_ ), 0 , 77 , 0 , 7682 , 194, 139), // #1223 - INST(Vphaddd , VexRvm_Lx , V(660F38,02,_,x,I,_,_,_ ), 0 , 96 , 0 , 7691 , 192, 143), // #1224 - INST(Vphadddq , VexRm , V(XOP_M9,CB,_,0,0,_,_,_ ), 0 , 77 , 0 , 7699 , 194, 139), // #1225 - INST(Vphaddsw , VexRvm_Lx , V(660F38,03,_,x,I,_,_,_ ), 0 , 96 , 0 , 7708 , 192, 143), // #1226 - INST(Vphaddubd , VexRm , V(XOP_M9,D2,_,0,0,_,_,_ ), 0 , 77 , 0 , 7717 , 194, 139), // #1227 - INST(Vphaddubq , VexRm , V(XOP_M9,D3,_,0,0,_,_,_ ), 0 , 77 , 0 , 7727 , 194, 139), // #1228 - INST(Vphaddubw , VexRm , V(XOP_M9,D1,_,0,0,_,_,_ ), 0 , 77 , 0 , 7737 , 194, 139), // #1229 - INST(Vphaddudq , VexRm , V(XOP_M9,DB,_,0,0,_,_,_ ), 0 , 77 , 0 , 7747 , 194, 139), // #1230 - INST(Vphadduwd , VexRm , V(XOP_M9,D6,_,0,0,_,_,_ ), 0 , 77 , 0 , 7757 , 194, 139), // #1231 - INST(Vphadduwq , VexRm , V(XOP_M9,D7,_,0,0,_,_,_ ), 0 , 77 , 0 , 7767 , 194, 139), // #1232 - INST(Vphaddw , VexRvm_Lx , V(660F38,01,_,x,I,_,_,_ ), 0 , 96 , 0 , 7777 , 192, 143), // #1233 - INST(Vphaddwd , VexRm , V(XOP_M9,C6,_,0,0,_,_,_ ), 0 , 77 , 0 , 7785 , 194, 139), // #1234 - INST(Vphaddwq , VexRm , V(XOP_M9,C7,_,0,0,_,_,_ ), 0 , 77 , 0 , 7794 , 194, 139), // #1235 - INST(Vphminposuw , VexRm , V(660F38,41,_,0,I,_,_,_ ), 0 , 96 , 0 , 7803 , 194, 123), // #1236 - INST(Vphsubbw , VexRm , V(XOP_M9,E1,_,0,0,_,_,_ ), 0 , 77 , 0 , 7815 , 194, 139), // #1237 - INST(Vphsubd , VexRvm_Lx , V(660F38,06,_,x,I,_,_,_ ), 0 , 96 , 0 , 7824 , 192, 143), // #1238 - INST(Vphsubdq , VexRm , V(XOP_M9,E3,_,0,0,_,_,_ ), 0 , 77 , 0 , 7832 , 194, 139), // #1239 - INST(Vphsubsw , VexRvm_Lx , V(660F38,07,_,x,I,_,_,_ ), 0 , 96 , 0 , 7841 , 192, 143), // #1240 - INST(Vphsubw , VexRvm_Lx , V(660F38,05,_,x,I,_,_,_ ), 0 , 96 , 0 , 7850 , 192, 143), // #1241 - INST(Vphsubwd , VexRm , V(XOP_M9,E2,_,0,0,_,_,_ ), 0 , 77 , 0 , 7858 , 194, 139), // #1242 - INST(Vpinsrb , VexRvmi , V(660F3A,20,_,0,0,I,0,T1S), 0 , 200, 0 , 7867 , 347, 154), // #1243 - INST(Vpinsrd , VexRvmi , V(660F3A,22,_,0,0,0,2,T1S), 0 , 159, 0 , 7875 , 348, 155), // #1244 - INST(Vpinsrq , VexRvmi , V(660F3A,22,_,0,1,1,3,T1S), 0 , 201, 0 , 7883 , 349, 155), // #1245 - INST(Vpinsrw , VexRvmi , V(660F00,C4,_,0,0,I,1,T1S), 0 , 203, 0 , 7891 , 350, 154), // #1246 - INST(Vplzcntd , VexRm_Lx , E(660F38,44,_,x,_,0,4,FV ), 0 , 111, 0 , 7899 , 338, 148), // #1247 - INST(Vplzcntq , VexRm_Lx , E(660F38,44,_,x,_,1,4,FV ), 0 , 112, 0 , 7908 , 351, 148), // #1248 - INST(Vpmacsdd , VexRvmr , V(XOP_M8,9E,_,0,0,_,_,_ ), 0 , 193, 0 , 7917 , 352, 139), // #1249 - INST(Vpmacsdqh , VexRvmr , V(XOP_M8,9F,_,0,0,_,_,_ ), 0 , 193, 0 , 7926 , 352, 139), // #1250 - INST(Vpmacsdql , VexRvmr , V(XOP_M8,97,_,0,0,_,_,_ ), 0 , 193, 0 , 7936 , 352, 139), // #1251 - INST(Vpmacssdd , VexRvmr , V(XOP_M8,8E,_,0,0,_,_,_ ), 0 , 193, 0 , 7946 , 352, 139), // #1252 - INST(Vpmacssdqh , VexRvmr , V(XOP_M8,8F,_,0,0,_,_,_ ), 0 , 193, 0 , 7956 , 352, 139), // #1253 - INST(Vpmacssdql , VexRvmr , V(XOP_M8,87,_,0,0,_,_,_ ), 0 , 193, 0 , 7967 , 352, 139), // #1254 - INST(Vpmacsswd , VexRvmr , V(XOP_M8,86,_,0,0,_,_,_ ), 0 , 193, 0 , 7978 , 352, 139), // #1255 - INST(Vpmacssww , VexRvmr , V(XOP_M8,85,_,0,0,_,_,_ ), 0 , 193, 0 , 7988 , 352, 139), // #1256 - INST(Vpmacswd , VexRvmr , V(XOP_M8,96,_,0,0,_,_,_ ), 0 , 193, 0 , 7998 , 352, 139), // #1257 - INST(Vpmacsww , VexRvmr , V(XOP_M8,95,_,0,0,_,_,_ ), 0 , 193, 0 , 8007 , 352, 139), // #1258 - INST(Vpmadcsswd , VexRvmr , V(XOP_M8,A6,_,0,0,_,_,_ ), 0 , 193, 0 , 8016 , 352, 139), // #1259 - INST(Vpmadcswd , VexRvmr , V(XOP_M8,B6,_,0,0,_,_,_ ), 0 , 193, 0 , 8027 , 352, 139), // #1260 - INST(Vpmadd52huq , VexRvm_Lx , E(660F38,B5,_,x,_,1,4,FV ), 0 , 112, 0 , 8037 , 204, 156), // #1261 - INST(Vpmadd52luq , VexRvm_Lx , E(660F38,B4,_,x,_,1,4,FV ), 0 , 112, 0 , 8049 , 204, 156), // #1262 - INST(Vpmaddubsw , VexRvm_Lx , V(660F38,04,_,x,I,I,4,FVM), 0 , 107, 0 , 8061 , 285, 146), // #1263 - INST(Vpmaddwd , VexRvm_Lx , V(660F00,F5,_,x,I,I,4,FVM), 0 , 184, 0 , 8072 , 285, 146), // #1264 - INST(Vpmaskmovd , VexRvmMvr_Lx , V(660F38,8C,_,x,0,_,_,_ ), V(660F38,8E,_,x,0,_,_,_ ), 96 , 117, 8081 , 293, 130), // #1265 - INST(Vpmaskmovq , VexRvmMvr_Lx , V(660F38,8C,_,x,1,_,_,_ ), V(660F38,8E,_,x,1,_,_,_ ), 165, 118, 8092 , 293, 130), // #1266 - INST(Vpmaxsb , VexRvm_Lx , V(660F38,3C,_,x,I,I,4,FVM), 0 , 107, 0 , 8103 , 353, 146), // #1267 - INST(Vpmaxsd , VexRvm_Lx , V(660F38,3D,_,x,I,0,4,FV ), 0 , 163, 0 , 8111 , 201, 131), // #1268 - INST(Vpmaxsq , VexRvm_Lx , E(660F38,3D,_,x,_,1,4,FV ), 0 , 112, 0 , 8119 , 204, 126), // #1269 - INST(Vpmaxsw , VexRvm_Lx , V(660F00,EE,_,x,I,I,4,FVM), 0 , 184, 0 , 8127 , 353, 146), // #1270 - INST(Vpmaxub , VexRvm_Lx , V(660F00,DE,_,x,I,I,4,FVM), 0 , 184, 0 , 8135 , 353, 146), // #1271 - INST(Vpmaxud , VexRvm_Lx , V(660F38,3F,_,x,I,0,4,FV ), 0 , 163, 0 , 8143 , 201, 131), // #1272 - INST(Vpmaxuq , VexRvm_Lx , E(660F38,3F,_,x,_,1,4,FV ), 0 , 112, 0 , 8151 , 204, 126), // #1273 - INST(Vpmaxuw , VexRvm_Lx , V(660F38,3E,_,x,I,I,4,FVM), 0 , 107, 0 , 8159 , 353, 146), // #1274 - INST(Vpminsb , VexRvm_Lx , V(660F38,38,_,x,I,I,4,FVM), 0 , 107, 0 , 8167 , 353, 146), // #1275 - INST(Vpminsd , VexRvm_Lx , V(660F38,39,_,x,I,0,4,FV ), 0 , 163, 0 , 8175 , 201, 131), // #1276 - INST(Vpminsq , VexRvm_Lx , E(660F38,39,_,x,_,1,4,FV ), 0 , 112, 0 , 8183 , 204, 126), // #1277 - INST(Vpminsw , VexRvm_Lx , V(660F00,EA,_,x,I,I,4,FVM), 0 , 184, 0 , 8191 , 353, 146), // #1278 - INST(Vpminub , VexRvm_Lx , V(660F00,DA,_,x,I,_,4,FVM), 0 , 184, 0 , 8199 , 353, 146), // #1279 - INST(Vpminud , VexRvm_Lx , V(660F38,3B,_,x,I,0,4,FV ), 0 , 163, 0 , 8207 , 201, 131), // #1280 - INST(Vpminuq , VexRvm_Lx , E(660F38,3B,_,x,_,1,4,FV ), 0 , 112, 0 , 8215 , 204, 126), // #1281 - INST(Vpminuw , VexRvm_Lx , V(660F38,3A,_,x,I,_,4,FVM), 0 , 107, 0 , 8223 , 353, 146), // #1282 - INST(Vpmovb2m , VexRm_Lx , E(F30F38,29,_,x,_,0,_,_ ), 0 , 128, 0 , 8231 , 354, 128), // #1283 - INST(Vpmovd2m , VexRm_Lx , E(F30F38,39,_,x,_,0,_,_ ), 0 , 128, 0 , 8240 , 354, 129), // #1284 - INST(Vpmovdb , VexMr_Lx , E(F30F38,31,_,x,_,0,2,QVM), 0 , 204, 0 , 8249 , 355, 126), // #1285 - INST(Vpmovdw , VexMr_Lx , E(F30F38,33,_,x,_,0,3,HVM), 0 , 205, 0 , 8257 , 356, 126), // #1286 - INST(Vpmovm2b , VexRm_Lx , E(F30F38,28,_,x,_,0,_,_ ), 0 , 128, 0 , 8265 , 324, 128), // #1287 - INST(Vpmovm2d , VexRm_Lx , E(F30F38,38,_,x,_,0,_,_ ), 0 , 128, 0 , 8274 , 324, 129), // #1288 - INST(Vpmovm2q , VexRm_Lx , E(F30F38,38,_,x,_,1,_,_ ), 0 , 191, 0 , 8283 , 324, 129), // #1289 - INST(Vpmovm2w , VexRm_Lx , E(F30F38,28,_,x,_,1,_,_ ), 0 , 191, 0 , 8292 , 324, 128), // #1290 - INST(Vpmovmskb , VexRm_Lx , V(660F00,D7,_,x,I,_,_,_ ), 0 , 68 , 0 , 8301 , 305, 143), // #1291 - INST(Vpmovq2m , VexRm_Lx , E(F30F38,39,_,x,_,1,_,_ ), 0 , 191, 0 , 8311 , 354, 129), // #1292 - INST(Vpmovqb , VexMr_Lx , E(F30F38,32,_,x,_,0,1,OVM), 0 , 206, 0 , 8320 , 357, 126), // #1293 - INST(Vpmovqd , VexMr_Lx , E(F30F38,35,_,x,_,0,3,HVM), 0 , 205, 0 , 8328 , 356, 126), // #1294 - INST(Vpmovqw , VexMr_Lx , E(F30F38,34,_,x,_,0,2,QVM), 0 , 204, 0 , 8336 , 355, 126), // #1295 - INST(Vpmovsdb , VexMr_Lx , E(F30F38,21,_,x,_,0,2,QVM), 0 , 204, 0 , 8344 , 355, 126), // #1296 - INST(Vpmovsdw , VexMr_Lx , E(F30F38,23,_,x,_,0,3,HVM), 0 , 205, 0 , 8353 , 356, 126), // #1297 - INST(Vpmovsqb , VexMr_Lx , E(F30F38,22,_,x,_,0,1,OVM), 0 , 206, 0 , 8362 , 357, 126), // #1298 - INST(Vpmovsqd , VexMr_Lx , E(F30F38,25,_,x,_,0,3,HVM), 0 , 205, 0 , 8371 , 356, 126), // #1299 - INST(Vpmovsqw , VexMr_Lx , E(F30F38,24,_,x,_,0,2,QVM), 0 , 204, 0 , 8380 , 355, 126), // #1300 - INST(Vpmovswb , VexMr_Lx , E(F30F38,20,_,x,_,0,3,HVM), 0 , 205, 0 , 8389 , 356, 128), // #1301 - INST(Vpmovsxbd , VexRm_Lx , V(660F38,21,_,x,I,I,2,QVM), 0 , 207, 0 , 8398 , 358, 131), // #1302 - INST(Vpmovsxbq , VexRm_Lx , V(660F38,22,_,x,I,I,1,OVM), 0 , 208, 0 , 8408 , 359, 131), // #1303 - INST(Vpmovsxbw , VexRm_Lx , V(660F38,20,_,x,I,I,3,HVM), 0 , 132, 0 , 8418 , 360, 146), // #1304 - INST(Vpmovsxdq , VexRm_Lx , V(660F38,25,_,x,I,0,3,HVM), 0 , 132, 0 , 8428 , 360, 131), // #1305 - INST(Vpmovsxwd , VexRm_Lx , V(660F38,23,_,x,I,I,3,HVM), 0 , 132, 0 , 8438 , 360, 131), // #1306 - INST(Vpmovsxwq , VexRm_Lx , V(660F38,24,_,x,I,I,2,QVM), 0 , 207, 0 , 8448 , 358, 131), // #1307 - INST(Vpmovusdb , VexMr_Lx , E(F30F38,11,_,x,_,0,2,QVM), 0 , 204, 0 , 8458 , 355, 126), // #1308 - INST(Vpmovusdw , VexMr_Lx , E(F30F38,13,_,x,_,0,3,HVM), 0 , 205, 0 , 8468 , 356, 126), // #1309 - INST(Vpmovusqb , VexMr_Lx , E(F30F38,12,_,x,_,0,1,OVM), 0 , 206, 0 , 8478 , 357, 126), // #1310 - INST(Vpmovusqd , VexMr_Lx , E(F30F38,15,_,x,_,0,3,HVM), 0 , 205, 0 , 8488 , 356, 126), // #1311 - INST(Vpmovusqw , VexMr_Lx , E(F30F38,14,_,x,_,0,2,QVM), 0 , 204, 0 , 8498 , 355, 126), // #1312 - INST(Vpmovuswb , VexMr_Lx , E(F30F38,10,_,x,_,0,3,HVM), 0 , 205, 0 , 8508 , 356, 128), // #1313 - INST(Vpmovw2m , VexRm_Lx , E(F30F38,29,_,x,_,1,_,_ ), 0 , 191, 0 , 8518 , 354, 128), // #1314 - INST(Vpmovwb , VexMr_Lx , E(F30F38,30,_,x,_,0,3,HVM), 0 , 205, 0 , 8527 , 356, 128), // #1315 - INST(Vpmovzxbd , VexRm_Lx , V(660F38,31,_,x,I,I,2,QVM), 0 , 207, 0 , 8535 , 358, 131), // #1316 - INST(Vpmovzxbq , VexRm_Lx , V(660F38,32,_,x,I,I,1,OVM), 0 , 208, 0 , 8545 , 359, 131), // #1317 - INST(Vpmovzxbw , VexRm_Lx , V(660F38,30,_,x,I,I,3,HVM), 0 , 132, 0 , 8555 , 360, 146), // #1318 - INST(Vpmovzxdq , VexRm_Lx , V(660F38,35,_,x,I,0,3,HVM), 0 , 132, 0 , 8565 , 360, 131), // #1319 - INST(Vpmovzxwd , VexRm_Lx , V(660F38,33,_,x,I,I,3,HVM), 0 , 132, 0 , 8575 , 360, 131), // #1320 - INST(Vpmovzxwq , VexRm_Lx , V(660F38,34,_,x,I,I,2,QVM), 0 , 207, 0 , 8585 , 358, 131), // #1321 - INST(Vpmuldq , VexRvm_Lx , V(660F38,28,_,x,I,1,4,FV ), 0 , 198, 0 , 8595 , 198, 131), // #1322 - INST(Vpmulhrsw , VexRvm_Lx , V(660F38,0B,_,x,I,I,4,FVM), 0 , 107, 0 , 8603 , 285, 146), // #1323 - INST(Vpmulhuw , VexRvm_Lx , V(660F00,E4,_,x,I,I,4,FVM), 0 , 184, 0 , 8613 , 285, 146), // #1324 - INST(Vpmulhw , VexRvm_Lx , V(660F00,E5,_,x,I,I,4,FVM), 0 , 184, 0 , 8622 , 285, 146), // #1325 - INST(Vpmulld , VexRvm_Lx , V(660F38,40,_,x,I,0,4,FV ), 0 , 163, 0 , 8630 , 199, 131), // #1326 - INST(Vpmullq , VexRvm_Lx , E(660F38,40,_,x,_,1,4,FV ), 0 , 112, 0 , 8638 , 204, 129), // #1327 - INST(Vpmullw , VexRvm_Lx , V(660F00,D5,_,x,I,I,4,FVM), 0 , 184, 0 , 8646 , 285, 146), // #1328 - INST(Vpmultishiftqb , VexRvm_Lx , E(660F38,83,_,x,_,1,4,FV ), 0 , 112, 0 , 8654 , 204, 153), // #1329 - INST(Vpmuludq , VexRvm_Lx , V(660F00,F4,_,x,I,1,4,FV ), 0 , 102, 0 , 8669 , 198, 131), // #1330 - INST(Vpopcntb , VexRm_Lx , E(660F38,54,_,x,_,0,4,FV ), 0 , 111, 0 , 8678 , 254, 157), // #1331 - INST(Vpopcntd , VexRm_Lx , E(660F38,55,_,x,_,0,4,FVM), 0 , 110, 0 , 8687 , 338, 158), // #1332 - INST(Vpopcntq , VexRm_Lx , E(660F38,55,_,x,_,1,4,FVM), 0 , 113, 0 , 8696 , 351, 158), // #1333 - INST(Vpopcntw , VexRm_Lx , E(660F38,54,_,x,_,1,4,FV ), 0 , 112, 0 , 8705 , 254, 157), // #1334 - INST(Vpor , VexRvm_Lx , V(660F00,EB,_,x,I,_,_,_ ), 0 , 68 , 0 , 8714 , 316, 143), // #1335 - INST(Vpord , VexRvm_Lx , E(660F00,EB,_,x,_,0,4,FV ), 0 , 189, 0 , 8719 , 317, 126), // #1336 - INST(Vporq , VexRvm_Lx , E(660F00,EB,_,x,_,1,4,FV ), 0 , 130, 0 , 8725 , 321, 126), // #1337 - INST(Vpperm , VexRvrmRvmr , V(XOP_M8,A3,_,0,x,_,_,_ ), 0 , 193, 0 , 8731 , 361, 139), // #1338 - INST(Vprold , VexVmi_Lx , E(660F00,72,1,x,_,0,4,FV ), 0 , 209, 0 , 8738 , 362, 126), // #1339 - INST(Vprolq , VexVmi_Lx , E(660F00,72,1,x,_,1,4,FV ), 0 , 210, 0 , 8745 , 363, 126), // #1340 - INST(Vprolvd , VexRvm_Lx , E(660F38,15,_,x,_,0,4,FV ), 0 , 111, 0 , 8752 , 203, 126), // #1341 - INST(Vprolvq , VexRvm_Lx , E(660F38,15,_,x,_,1,4,FV ), 0 , 112, 0 , 8760 , 204, 126), // #1342 - INST(Vprord , VexVmi_Lx , E(660F00,72,0,x,_,0,4,FV ), 0 , 189, 0 , 8768 , 362, 126), // #1343 - INST(Vprorq , VexVmi_Lx , E(660F00,72,0,x,_,1,4,FV ), 0 , 130, 0 , 8775 , 363, 126), // #1344 - INST(Vprorvd , VexRvm_Lx , E(660F38,14,_,x,_,0,4,FV ), 0 , 111, 0 , 8782 , 203, 126), // #1345 - INST(Vprorvq , VexRvm_Lx , E(660F38,14,_,x,_,1,4,FV ), 0 , 112, 0 , 8790 , 204, 126), // #1346 - INST(Vprotb , VexRvmRmvRmi , V(XOP_M9,90,_,0,x,_,_,_ ), V(XOP_M8,C0,_,0,x,_,_,_ ), 77 , 119, 8798 , 364, 139), // #1347 - INST(Vprotd , VexRvmRmvRmi , V(XOP_M9,92,_,0,x,_,_,_ ), V(XOP_M8,C2,_,0,x,_,_,_ ), 77 , 120, 8805 , 364, 139), // #1348 - INST(Vprotq , VexRvmRmvRmi , V(XOP_M9,93,_,0,x,_,_,_ ), V(XOP_M8,C3,_,0,x,_,_,_ ), 77 , 121, 8812 , 364, 139), // #1349 - INST(Vprotw , VexRvmRmvRmi , V(XOP_M9,91,_,0,x,_,_,_ ), V(XOP_M8,C1,_,0,x,_,_,_ ), 77 , 122, 8819 , 364, 139), // #1350 - INST(Vpsadbw , VexRvm_Lx , V(660F00,F6,_,x,I,I,4,FVM), 0 , 184, 0 , 8826 , 193, 146), // #1351 - INST(Vpscatterdd , VexMr_VM , E(660F38,A0,_,x,_,0,2,T1S), 0 , 125, 0 , 8834 , 365, 126), // #1352 - INST(Vpscatterdq , VexMr_VM , E(660F38,A0,_,x,_,1,3,T1S), 0 , 124, 0 , 8846 , 365, 126), // #1353 - INST(Vpscatterqd , VexMr_VM , E(660F38,A1,_,x,_,0,2,T1S), 0 , 125, 0 , 8858 , 366, 126), // #1354 - INST(Vpscatterqq , VexMr_VM , E(660F38,A1,_,x,_,1,3,T1S), 0 , 124, 0 , 8870 , 367, 126), // #1355 - INST(Vpshab , VexRvmRmv , V(XOP_M9,98,_,0,x,_,_,_ ), 0 , 77 , 0 , 8882 , 368, 139), // #1356 - INST(Vpshad , VexRvmRmv , V(XOP_M9,9A,_,0,x,_,_,_ ), 0 , 77 , 0 , 8889 , 368, 139), // #1357 - INST(Vpshaq , VexRvmRmv , V(XOP_M9,9B,_,0,x,_,_,_ ), 0 , 77 , 0 , 8896 , 368, 139), // #1358 - INST(Vpshaw , VexRvmRmv , V(XOP_M9,99,_,0,x,_,_,_ ), 0 , 77 , 0 , 8903 , 368, 139), // #1359 - INST(Vpshlb , VexRvmRmv , V(XOP_M9,94,_,0,x,_,_,_ ), 0 , 77 , 0 , 8910 , 368, 139), // #1360 - INST(Vpshld , VexRvmRmv , V(XOP_M9,96,_,0,x,_,_,_ ), 0 , 77 , 0 , 8917 , 368, 139), // #1361 - INST(Vpshldd , VexRvmi_Lx , E(660F3A,71,_,x,_,0,4,FV ), 0 , 108, 0 , 8924 , 196, 151), // #1362 - INST(Vpshldq , VexRvmi_Lx , E(660F3A,71,_,x,_,1,4,FV ), 0 , 109, 0 , 8932 , 197, 151), // #1363 - INST(Vpshldvd , VexRvm_Lx , E(660F38,71,_,x,_,0,4,FV ), 0 , 111, 0 , 8940 , 203, 151), // #1364 - INST(Vpshldvq , VexRvm_Lx , E(660F38,71,_,x,_,1,4,FV ), 0 , 112, 0 , 8949 , 204, 151), // #1365 - INST(Vpshldvw , VexRvm_Lx , E(660F38,70,_,x,_,0,4,FVM), 0 , 110, 0 , 8958 , 202, 151), // #1366 - INST(Vpshldw , VexRvmi_Lx , E(660F3A,70,_,x,_,0,4,FVM), 0 , 151, 0 , 8967 , 250, 151), // #1367 - INST(Vpshlq , VexRvmRmv , V(XOP_M9,97,_,0,x,_,_,_ ), 0 , 77 , 0 , 8975 , 368, 139), // #1368 - INST(Vpshlw , VexRvmRmv , V(XOP_M9,95,_,0,x,_,_,_ ), 0 , 77 , 0 , 8982 , 368, 139), // #1369 - INST(Vpshrdd , VexRvmi_Lx , E(660F3A,73,_,x,_,0,4,FV ), 0 , 108, 0 , 8989 , 196, 151), // #1370 - INST(Vpshrdq , VexRvmi_Lx , E(660F3A,73,_,x,_,1,4,FV ), 0 , 109, 0 , 8997 , 197, 151), // #1371 - INST(Vpshrdvd , VexRvm_Lx , E(660F38,73,_,x,_,0,4,FV ), 0 , 111, 0 , 9005 , 203, 151), // #1372 - INST(Vpshrdvq , VexRvm_Lx , E(660F38,73,_,x,_,1,4,FV ), 0 , 112, 0 , 9014 , 204, 151), // #1373 - INST(Vpshrdvw , VexRvm_Lx , E(660F38,72,_,x,_,0,4,FVM), 0 , 110, 0 , 9023 , 202, 151), // #1374 - INST(Vpshrdw , VexRvmi_Lx , E(660F3A,72,_,x,_,0,4,FVM), 0 , 151, 0 , 9032 , 250, 151), // #1375 - INST(Vpshufb , VexRvm_Lx , V(660F38,00,_,x,I,I,4,FVM), 0 , 107, 0 , 9040 , 285, 146), // #1376 - INST(Vpshufbitqmb , VexRvm_Lx , E(660F38,8F,_,x,0,0,4,FVM), 0 , 110, 0 , 9048 , 369, 157), // #1377 - INST(Vpshufd , VexRmi_Lx , V(660F00,70,_,x,I,0,4,FV ), 0 , 133, 0 , 9061 , 370, 131), // #1378 - INST(Vpshufhw , VexRmi_Lx , V(F30F00,70,_,x,I,I,4,FVM), 0 , 185, 0 , 9069 , 371, 146), // #1379 - INST(Vpshuflw , VexRmi_Lx , V(F20F00,70,_,x,I,I,4,FVM), 0 , 211, 0 , 9078 , 371, 146), // #1380 - INST(Vpsignb , VexRvm_Lx , V(660F38,08,_,x,I,_,_,_ ), 0 , 96 , 0 , 9087 , 192, 143), // #1381 - INST(Vpsignd , VexRvm_Lx , V(660F38,0A,_,x,I,_,_,_ ), 0 , 96 , 0 , 9095 , 192, 143), // #1382 - INST(Vpsignw , VexRvm_Lx , V(660F38,09,_,x,I,_,_,_ ), 0 , 96 , 0 , 9103 , 192, 143), // #1383 - INST(Vpslld , VexRvmVmi_Lx , V(660F00,F2,_,x,I,0,4,128), V(660F00,72,6,x,I,0,4,FV ), 212, 123, 9111 , 372, 131), // #1384 - INST(Vpslldq , VexEvexVmi_Lx , V(660F00,73,7,x,I,I,4,FVM), 0 , 213, 0 , 9118 , 373, 146), // #1385 - INST(Vpsllq , VexRvmVmi_Lx , V(660F00,F3,_,x,I,1,4,128), V(660F00,73,6,x,I,1,4,FV ), 214, 124, 9126 , 374, 131), // #1386 - INST(Vpsllvd , VexRvm_Lx , V(660F38,47,_,x,0,0,4,FV ), 0 , 163, 0 , 9133 , 199, 140), // #1387 - INST(Vpsllvq , VexRvm_Lx , V(660F38,47,_,x,1,1,4,FV ), 0 , 162, 0 , 9141 , 198, 140), // #1388 - INST(Vpsllvw , VexRvm_Lx , E(660F38,12,_,x,_,1,4,FVM), 0 , 113, 0 , 9149 , 202, 128), // #1389 - INST(Vpsllw , VexRvmVmi_Lx , V(660F00,F1,_,x,I,I,4,FVM), V(660F00,71,6,x,I,I,4,FVM), 184, 125, 9157 , 375, 146), // #1390 - INST(Vpsrad , VexRvmVmi_Lx , V(660F00,E2,_,x,I,0,4,128), V(660F00,72,4,x,I,0,4,FV ), 212, 126, 9164 , 372, 131), // #1391 - INST(Vpsraq , VexRvmVmi_Lx , E(660F00,E2,_,x,_,1,4,128), E(660F00,72,4,x,_,1,4,FV ), 215, 127, 9171 , 376, 126), // #1392 - INST(Vpsravd , VexRvm_Lx , V(660F38,46,_,x,0,0,4,FV ), 0 , 163, 0 , 9178 , 199, 140), // #1393 - INST(Vpsravq , VexRvm_Lx , E(660F38,46,_,x,_,1,4,FV ), 0 , 112, 0 , 9186 , 204, 126), // #1394 - INST(Vpsravw , VexRvm_Lx , E(660F38,11,_,x,_,1,4,FVM), 0 , 113, 0 , 9194 , 202, 128), // #1395 - INST(Vpsraw , VexRvmVmi_Lx , V(660F00,E1,_,x,I,I,4,128), V(660F00,71,4,x,I,I,4,FVM), 212, 128, 9202 , 375, 146), // #1396 - INST(Vpsrld , VexRvmVmi_Lx , V(660F00,D2,_,x,I,0,4,128), V(660F00,72,2,x,I,0,4,FV ), 212, 129, 9209 , 372, 131), // #1397 - INST(Vpsrldq , VexEvexVmi_Lx , V(660F00,73,3,x,I,I,4,FVM), 0 , 216, 0 , 9216 , 373, 146), // #1398 - INST(Vpsrlq , VexRvmVmi_Lx , V(660F00,D3,_,x,I,1,4,128), V(660F00,73,2,x,I,1,4,FV ), 214, 130, 9224 , 374, 131), // #1399 - INST(Vpsrlvd , VexRvm_Lx , V(660F38,45,_,x,0,0,4,FV ), 0 , 163, 0 , 9231 , 199, 140), // #1400 - INST(Vpsrlvq , VexRvm_Lx , V(660F38,45,_,x,1,1,4,FV ), 0 , 162, 0 , 9239 , 198, 140), // #1401 - INST(Vpsrlvw , VexRvm_Lx , E(660F38,10,_,x,_,1,4,FVM), 0 , 113, 0 , 9247 , 202, 128), // #1402 - INST(Vpsrlw , VexRvmVmi_Lx , V(660F00,D1,_,x,I,I,4,128), V(660F00,71,2,x,I,I,4,FVM), 212, 131, 9255 , 375, 146), // #1403 - INST(Vpsubb , VexRvm_Lx , V(660F00,F8,_,x,I,I,4,FVM), 0 , 184, 0 , 9262 , 377, 146), // #1404 - INST(Vpsubd , VexRvm_Lx , V(660F00,FA,_,x,I,0,4,FV ), 0 , 133, 0 , 9269 , 378, 131), // #1405 - INST(Vpsubq , VexRvm_Lx , V(660F00,FB,_,x,I,1,4,FV ), 0 , 102, 0 , 9276 , 379, 131), // #1406 - INST(Vpsubsb , VexRvm_Lx , V(660F00,E8,_,x,I,I,4,FVM), 0 , 184, 0 , 9283 , 377, 146), // #1407 - INST(Vpsubsw , VexRvm_Lx , V(660F00,E9,_,x,I,I,4,FVM), 0 , 184, 0 , 9291 , 377, 146), // #1408 - INST(Vpsubusb , VexRvm_Lx , V(660F00,D8,_,x,I,I,4,FVM), 0 , 184, 0 , 9299 , 377, 146), // #1409 - INST(Vpsubusw , VexRvm_Lx , V(660F00,D9,_,x,I,I,4,FVM), 0 , 184, 0 , 9308 , 377, 146), // #1410 - INST(Vpsubw , VexRvm_Lx , V(660F00,F9,_,x,I,I,4,FVM), 0 , 184, 0 , 9317 , 377, 146), // #1411 - INST(Vpternlogd , VexRvmi_Lx , E(660F3A,25,_,x,_,0,4,FV ), 0 , 108, 0 , 9324 , 196, 126), // #1412 - INST(Vpternlogq , VexRvmi_Lx , E(660F3A,25,_,x,_,1,4,FV ), 0 , 109, 0 , 9335 , 197, 126), // #1413 - INST(Vptest , VexRm_Lx , V(660F38,17,_,x,I,_,_,_ ), 0 , 96 , 0 , 9346 , 270, 150), // #1414 - INST(Vptestmb , VexRvm_Lx , E(660F38,26,_,x,_,0,4,FVM), 0 , 110, 0 , 9353 , 369, 128), // #1415 - INST(Vptestmd , VexRvm_Lx , E(660F38,27,_,x,_,0,4,FV ), 0 , 111, 0 , 9362 , 380, 126), // #1416 - INST(Vptestmq , VexRvm_Lx , E(660F38,27,_,x,_,1,4,FV ), 0 , 112, 0 , 9371 , 381, 126), // #1417 - INST(Vptestmw , VexRvm_Lx , E(660F38,26,_,x,_,1,4,FVM), 0 , 113, 0 , 9380 , 369, 128), // #1418 - INST(Vptestnmb , VexRvm_Lx , E(F30F38,26,_,x,_,0,4,FVM), 0 , 217, 0 , 9389 , 369, 128), // #1419 - INST(Vptestnmd , VexRvm_Lx , E(F30F38,27,_,x,_,0,4,FV ), 0 , 218, 0 , 9399 , 380, 126), // #1420 - INST(Vptestnmq , VexRvm_Lx , E(F30F38,27,_,x,_,1,4,FV ), 0 , 219, 0 , 9409 , 381, 126), // #1421 - INST(Vptestnmw , VexRvm_Lx , E(F30F38,26,_,x,_,1,4,FVM), 0 , 220, 0 , 9419 , 369, 128), // #1422 - INST(Vpunpckhbw , VexRvm_Lx , V(660F00,68,_,x,I,I,4,FVM), 0 , 184, 0 , 9429 , 285, 146), // #1423 - INST(Vpunpckhdq , VexRvm_Lx , V(660F00,6A,_,x,I,0,4,FV ), 0 , 133, 0 , 9440 , 199, 131), // #1424 - INST(Vpunpckhqdq , VexRvm_Lx , V(660F00,6D,_,x,I,1,4,FV ), 0 , 102, 0 , 9451 , 198, 131), // #1425 - INST(Vpunpckhwd , VexRvm_Lx , V(660F00,69,_,x,I,I,4,FVM), 0 , 184, 0 , 9463 , 285, 146), // #1426 - INST(Vpunpcklbw , VexRvm_Lx , V(660F00,60,_,x,I,I,4,FVM), 0 , 184, 0 , 9474 , 285, 146), // #1427 - INST(Vpunpckldq , VexRvm_Lx , V(660F00,62,_,x,I,0,4,FV ), 0 , 133, 0 , 9485 , 199, 131), // #1428 - INST(Vpunpcklqdq , VexRvm_Lx , V(660F00,6C,_,x,I,1,4,FV ), 0 , 102, 0 , 9496 , 198, 131), // #1429 - INST(Vpunpcklwd , VexRvm_Lx , V(660F00,61,_,x,I,I,4,FVM), 0 , 184, 0 , 9508 , 285, 146), // #1430 - INST(Vpxor , VexRvm_Lx , V(660F00,EF,_,x,I,_,_,_ ), 0 , 68 , 0 , 9519 , 318, 143), // #1431 - INST(Vpxord , VexRvm_Lx , E(660F00,EF,_,x,_,0,4,FV ), 0 , 189, 0 , 9525 , 319, 126), // #1432 - INST(Vpxorq , VexRvm_Lx , E(660F00,EF,_,x,_,1,4,FV ), 0 , 130, 0 , 9532 , 320, 126), // #1433 - INST(Vrangepd , VexRvmi_Lx , E(660F3A,50,_,x,_,1,4,FV ), 0 , 109, 0 , 9539 , 259, 129), // #1434 - INST(Vrangeps , VexRvmi_Lx , E(660F3A,50,_,x,_,0,4,FV ), 0 , 108, 0 , 9548 , 260, 129), // #1435 - INST(Vrangesd , VexRvmi , E(660F3A,51,_,I,_,1,3,T1S), 0 , 160, 0 , 9557 , 261, 64 ), // #1436 - INST(Vrangess , VexRvmi , E(660F3A,51,_,I,_,0,2,T1S), 0 , 161, 0 , 9566 , 262, 64 ), // #1437 - INST(Vrcp14pd , VexRm_Lx , E(660F38,4C,_,x,_,1,4,FV ), 0 , 112, 0 , 9575 , 351, 126), // #1438 - INST(Vrcp14ps , VexRm_Lx , E(660F38,4C,_,x,_,0,4,FV ), 0 , 111, 0 , 9584 , 338, 126), // #1439 - INST(Vrcp14sd , VexRvm , E(660F38,4D,_,I,_,1,3,T1S), 0 , 124, 0 , 9593 , 382, 66 ), // #1440 - INST(Vrcp14ss , VexRvm , E(660F38,4D,_,I,_,0,2,T1S), 0 , 125, 0 , 9602 , 383, 66 ), // #1441 - INST(Vrcp28pd , VexRm , E(660F38,CA,_,2,_,1,4,FV ), 0 , 152, 0 , 9611 , 252, 135), // #1442 - INST(Vrcp28ps , VexRm , E(660F38,CA,_,2,_,0,4,FV ), 0 , 153, 0 , 9620 , 253, 135), // #1443 - INST(Vrcp28sd , VexRvm , E(660F38,CB,_,I,_,1,3,T1S), 0 , 124, 0 , 9629 , 280, 135), // #1444 - INST(Vrcp28ss , VexRvm , E(660F38,CB,_,I,_,0,2,T1S), 0 , 125, 0 , 9638 , 281, 135), // #1445 - INST(Vrcpps , VexRm_Lx , V(000F00,53,_,x,I,_,_,_ ), 0 , 71 , 0 , 9647 , 270, 123), // #1446 - INST(Vrcpss , VexRvm , V(F30F00,53,_,I,I,_,_,_ ), 0 , 178, 0 , 9654 , 384, 123), // #1447 - INST(Vreducepd , VexRmi_Lx , E(660F3A,56,_,x,_,1,4,FV ), 0 , 109, 0 , 9661 , 363, 129), // #1448 - INST(Vreduceps , VexRmi_Lx , E(660F3A,56,_,x,_,0,4,FV ), 0 , 108, 0 , 9671 , 362, 129), // #1449 - INST(Vreducesd , VexRvmi , E(660F3A,57,_,I,_,1,3,T1S), 0 , 160, 0 , 9681 , 385, 64 ), // #1450 - INST(Vreducess , VexRvmi , E(660F3A,57,_,I,_,0,2,T1S), 0 , 161, 0 , 9691 , 386, 64 ), // #1451 - INST(Vrndscalepd , VexRmi_Lx , E(660F3A,09,_,x,_,1,4,FV ), 0 , 109, 0 , 9701 , 282, 126), // #1452 - INST(Vrndscaleps , VexRmi_Lx , E(660F3A,08,_,x,_,0,4,FV ), 0 , 108, 0 , 9713 , 283, 126), // #1453 - INST(Vrndscalesd , VexRvmi , E(660F3A,0B,_,I,_,1,3,T1S), 0 , 160, 0 , 9725 , 261, 66 ), // #1454 - INST(Vrndscaless , VexRvmi , E(660F3A,0A,_,I,_,0,2,T1S), 0 , 161, 0 , 9737 , 262, 66 ), // #1455 - INST(Vroundpd , VexRmi_Lx , V(660F3A,09,_,x,I,_,_,_ ), 0 , 72 , 0 , 9749 , 387, 123), // #1456 - INST(Vroundps , VexRmi_Lx , V(660F3A,08,_,x,I,_,_,_ ), 0 , 72 , 0 , 9758 , 387, 123), // #1457 - INST(Vroundsd , VexRvmi , V(660F3A,0B,_,I,I,_,_,_ ), 0 , 72 , 0 , 9767 , 388, 123), // #1458 - INST(Vroundss , VexRvmi , V(660F3A,0A,_,I,I,_,_,_ ), 0 , 72 , 0 , 9776 , 389, 123), // #1459 - INST(Vrsqrt14pd , VexRm_Lx , E(660F38,4E,_,x,_,1,4,FV ), 0 , 112, 0 , 9785 , 351, 126), // #1460 - INST(Vrsqrt14ps , VexRm_Lx , E(660F38,4E,_,x,_,0,4,FV ), 0 , 111, 0 , 9796 , 338, 126), // #1461 - INST(Vrsqrt14sd , VexRvm , E(660F38,4F,_,I,_,1,3,T1S), 0 , 124, 0 , 9807 , 382, 66 ), // #1462 - INST(Vrsqrt14ss , VexRvm , E(660F38,4F,_,I,_,0,2,T1S), 0 , 125, 0 , 9818 , 383, 66 ), // #1463 - INST(Vrsqrt28pd , VexRm , E(660F38,CC,_,2,_,1,4,FV ), 0 , 152, 0 , 9829 , 252, 135), // #1464 - INST(Vrsqrt28ps , VexRm , E(660F38,CC,_,2,_,0,4,FV ), 0 , 153, 0 , 9840 , 253, 135), // #1465 - INST(Vrsqrt28sd , VexRvm , E(660F38,CD,_,I,_,1,3,T1S), 0 , 124, 0 , 9851 , 280, 135), // #1466 - INST(Vrsqrt28ss , VexRvm , E(660F38,CD,_,I,_,0,2,T1S), 0 , 125, 0 , 9862 , 281, 135), // #1467 - INST(Vrsqrtps , VexRm_Lx , V(000F00,52,_,x,I,_,_,_ ), 0 , 71 , 0 , 9873 , 270, 123), // #1468 - INST(Vrsqrtss , VexRvm , V(F30F00,52,_,I,I,_,_,_ ), 0 , 178, 0 , 9882 , 384, 123), // #1469 - INST(Vscalefpd , VexRvm_Lx , E(660F38,2C,_,x,_,1,4,FV ), 0 , 112, 0 , 9891 , 390, 126), // #1470 - INST(Vscalefps , VexRvm_Lx , E(660F38,2C,_,x,_,0,4,FV ), 0 , 111, 0 , 9901 , 391, 126), // #1471 - INST(Vscalefsd , VexRvm , E(660F38,2D,_,I,_,1,3,T1S), 0 , 124, 0 , 9911 , 392, 66 ), // #1472 - INST(Vscalefss , VexRvm , E(660F38,2D,_,I,_,0,2,T1S), 0 , 125, 0 , 9921 , 393, 66 ), // #1473 - INST(Vscatterdpd , VexMr_Lx , E(660F38,A2,_,x,_,1,3,T1S), 0 , 124, 0 , 9931 , 394, 126), // #1474 - INST(Vscatterdps , VexMr_Lx , E(660F38,A2,_,x,_,0,2,T1S), 0 , 125, 0 , 9943 , 365, 126), // #1475 - INST(Vscatterpf0dpd , VexM_VM , E(660F38,C6,5,2,_,1,3,T1S), 0 , 221, 0 , 9955 , 275, 141), // #1476 - INST(Vscatterpf0dps , VexM_VM , E(660F38,C6,5,2,_,0,2,T1S), 0 , 222, 0 , 9970 , 276, 141), // #1477 - INST(Vscatterpf0qpd , VexM_VM , E(660F38,C7,5,2,_,1,3,T1S), 0 , 221, 0 , 9985 , 277, 141), // #1478 - INST(Vscatterpf0qps , VexM_VM , E(660F38,C7,5,2,_,0,2,T1S), 0 , 222, 0 , 10000, 277, 141), // #1479 - INST(Vscatterpf1dpd , VexM_VM , E(660F38,C6,6,2,_,1,3,T1S), 0 , 223, 0 , 10015, 275, 141), // #1480 - INST(Vscatterpf1dps , VexM_VM , E(660F38,C6,6,2,_,0,2,T1S), 0 , 224, 0 , 10030, 276, 141), // #1481 - INST(Vscatterpf1qpd , VexM_VM , E(660F38,C7,6,2,_,1,3,T1S), 0 , 223, 0 , 10045, 277, 141), // #1482 - INST(Vscatterpf1qps , VexM_VM , E(660F38,C7,6,2,_,0,2,T1S), 0 , 224, 0 , 10060, 277, 141), // #1483 - INST(Vscatterqpd , VexMr_Lx , E(660F38,A3,_,x,_,1,3,T1S), 0 , 124, 0 , 10075, 367, 126), // #1484 - INST(Vscatterqps , VexMr_Lx , E(660F38,A3,_,x,_,0,2,T1S), 0 , 125, 0 , 10087, 366, 126), // #1485 - INST(Vshuff32x4 , VexRvmi_Lx , E(660F3A,23,_,x,_,0,4,FV ), 0 , 108, 0 , 10099, 395, 126), // #1486 - INST(Vshuff64x2 , VexRvmi_Lx , E(660F3A,23,_,x,_,1,4,FV ), 0 , 109, 0 , 10110, 396, 126), // #1487 - INST(Vshufi32x4 , VexRvmi_Lx , E(660F3A,43,_,x,_,0,4,FV ), 0 , 108, 0 , 10121, 395, 126), // #1488 - INST(Vshufi64x2 , VexRvmi_Lx , E(660F3A,43,_,x,_,1,4,FV ), 0 , 109, 0 , 10132, 396, 126), // #1489 - INST(Vshufpd , VexRvmi_Lx , V(660F00,C6,_,x,I,1,4,FV ), 0 , 102, 0 , 10143, 397, 121), // #1490 - INST(Vshufps , VexRvmi_Lx , V(000F00,C6,_,x,I,0,4,FV ), 0 , 103, 0 , 10151, 398, 121), // #1491 - INST(Vsqrtpd , VexRm_Lx , V(660F00,51,_,x,I,1,4,FV ), 0 , 102, 0 , 10159, 399, 121), // #1492 - INST(Vsqrtps , VexRm_Lx , V(000F00,51,_,x,I,0,4,FV ), 0 , 103, 0 , 10167, 222, 121), // #1493 - INST(Vsqrtsd , VexRvm , V(F20F00,51,_,I,I,1,3,T1S), 0 , 104, 0 , 10175, 190, 122), // #1494 - INST(Vsqrtss , VexRvm , V(F30F00,51,_,I,I,0,2,T1S), 0 , 105, 0 , 10183, 191, 122), // #1495 - INST(Vstmxcsr , VexM , V(000F00,AE,3,0,I,_,_,_ ), 0 , 225, 0 , 10191, 291, 123), // #1496 - INST(Vsubpd , VexRvm_Lx , V(660F00,5C,_,x,I,1,4,FV ), 0 , 102, 0 , 10200, 188, 121), // #1497 - INST(Vsubps , VexRvm_Lx , V(000F00,5C,_,x,I,0,4,FV ), 0 , 103, 0 , 10207, 189, 121), // #1498 - INST(Vsubsd , VexRvm , V(F20F00,5C,_,I,I,1,3,T1S), 0 , 104, 0 , 10214, 190, 122), // #1499 - INST(Vsubss , VexRvm , V(F30F00,5C,_,I,I,0,2,T1S), 0 , 105, 0 , 10221, 191, 122), // #1500 - INST(Vtestpd , VexRm_Lx , V(660F38,0F,_,x,0,_,_,_ ), 0 , 96 , 0 , 10228, 270, 150), // #1501 - INST(Vtestps , VexRm_Lx , V(660F38,0E,_,x,0,_,_,_ ), 0 , 96 , 0 , 10236, 270, 150), // #1502 - INST(Vucomisd , VexRm , V(660F00,2E,_,I,I,1,3,T1S), 0 , 122, 0 , 10244, 218, 132), // #1503 - INST(Vucomiss , VexRm , V(000F00,2E,_,I,I,0,2,T1S), 0 , 123, 0 , 10253, 219, 132), // #1504 - INST(Vunpckhpd , VexRvm_Lx , V(660F00,15,_,x,I,1,4,FV ), 0 , 102, 0 , 10262, 198, 121), // #1505 - INST(Vunpckhps , VexRvm_Lx , V(000F00,15,_,x,I,0,4,FV ), 0 , 103, 0 , 10272, 199, 121), // #1506 - INST(Vunpcklpd , VexRvm_Lx , V(660F00,14,_,x,I,1,4,FV ), 0 , 102, 0 , 10282, 198, 121), // #1507 - INST(Vunpcklps , VexRvm_Lx , V(000F00,14,_,x,I,0,4,FV ), 0 , 103, 0 , 10292, 199, 121), // #1508 - INST(Vxorpd , VexRvm_Lx , V(660F00,57,_,x,I,1,4,FV ), 0 , 102, 0 , 10302, 379, 127), // #1509 - INST(Vxorps , VexRvm_Lx , V(000F00,57,_,x,I,0,4,FV ), 0 , 103, 0 , 10309, 378, 127), // #1510 - INST(Vzeroall , VexOp , V(000F00,77,_,1,I,_,_,_ ), 0 , 67 , 0 , 10316, 400, 123), // #1511 - INST(Vzeroupper , VexOp , V(000F00,77,_,0,I,_,_,_ ), 0 , 71 , 0 , 10325, 400, 123), // #1512 - INST(Wbinvd , X86Op , O(000F00,09,_,_,_,_,_,_ ), 0 , 4 , 0 , 10336, 30 , 0 ), // #1513 - INST(Wbnoinvd , X86Op , O(F30F00,09,_,_,_,_,_,_ ), 0 , 6 , 0 , 10343, 30 , 159), // #1514 - INST(Wrfsbase , X86M , O(F30F00,AE,2,_,x,_,_,_ ), 0 , 226, 0 , 10352, 166, 102), // #1515 - INST(Wrgsbase , X86M , O(F30F00,AE,3,_,x,_,_,_ ), 0 , 227, 0 , 10361, 166, 102), // #1516 - INST(Wrmsr , X86Op , O(000F00,30,_,_,_,_,_,_ ), 0 , 4 , 0 , 10370, 167, 103), // #1517 - INST(Wrssd , X86Mr , O(000F38,F6,_,_,_,_,_,_ ), 0 , 82 , 0 , 10376, 401, 54 ), // #1518 - INST(Wrssq , X86Mr , O(000F38,F6,_,_,1,_,_,_ ), 0 , 228, 0 , 10382, 402, 54 ), // #1519 - INST(Wrussd , X86Mr , O(660F38,F5,_,_,_,_,_,_ ), 0 , 2 , 0 , 10388, 401, 54 ), // #1520 - INST(Wrussq , X86Mr , O(660F38,F5,_,_,1,_,_,_ ), 0 , 229, 0 , 10395, 402, 54 ), // #1521 - INST(Xabort , X86Op_Mod11RM_I8 , O(000000,C6,7,_,_,_,_,_ ), 0 , 26 , 0 , 10402, 77 , 160), // #1522 - INST(Xadd , X86Xadd , O(000F00,C0,_,_,x,_,_,_ ), 0 , 4 , 0 , 10409, 403, 37 ), // #1523 - INST(Xbegin , X86JmpRel , O(000000,C7,7,_,_,_,_,_ ), 0 , 26 , 0 , 10414, 404, 160), // #1524 - INST(Xchg , X86Xchg , O(000000,86,_,_,x,_,_,_ ), 0 , 0 , 0 , 457 , 405, 0 ), // #1525 - INST(Xend , X86Op , O(000F01,D5,_,_,_,_,_,_ ), 0 , 21 , 0 , 10421, 30 , 160), // #1526 - INST(Xgetbv , X86Op , O(000F01,D0,_,_,_,_,_,_ ), 0 , 21 , 0 , 10426, 167, 161), // #1527 - INST(Xlatb , X86Op , O(000000,D7,_,_,_,_,_,_ ), 0 , 0 , 0 , 10433, 30 , 0 ), // #1528 - INST(Xor , X86Arith , O(000000,30,6,_,x,_,_,_ ), 0 , 31 , 0 , 9521 , 171, 1 ), // #1529 - INST(Xorpd , ExtRm , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 10303, 144, 4 ), // #1530 - INST(Xorps , ExtRm , O(000F00,57,_,_,_,_,_,_ ), 0 , 4 , 0 , 10310, 144, 5 ), // #1531 - INST(Xresldtrk , X86Op , O(F20F01,E9,_,_,_,_,_,_ ), 0 , 92 , 0 , 10439, 30 , 162), // #1532 - INST(Xrstor , X86M_Only , O(000F00,AE,5,_,_,_,_,_ ), 0 , 75 , 0 , 1159 , 406, 161), // #1533 - INST(Xrstor64 , X86M_Only , O(000F00,AE,5,_,1,_,_,_ ), 0 , 230, 0 , 1167 , 407, 161), // #1534 - INST(Xrstors , X86M_Only , O(000F00,C7,3,_,_,_,_,_ ), 0 , 76 , 0 , 10449, 406, 163), // #1535 - INST(Xrstors64 , X86M_Only , O(000F00,C7,3,_,1,_,_,_ ), 0 , 231, 0 , 10457, 407, 163), // #1536 - INST(Xsave , X86M_Only , O(000F00,AE,4,_,_,_,_,_ ), 0 , 97 , 0 , 1177 , 406, 161), // #1537 - INST(Xsave64 , X86M_Only , O(000F00,AE,4,_,1,_,_,_ ), 0 , 232, 0 , 1184 , 407, 161), // #1538 - INST(Xsavec , X86M_Only , O(000F00,C7,4,_,_,_,_,_ ), 0 , 97 , 0 , 10467, 406, 164), // #1539 - INST(Xsavec64 , X86M_Only , O(000F00,C7,4,_,1,_,_,_ ), 0 , 232, 0 , 10474, 407, 164), // #1540 - INST(Xsaveopt , X86M_Only , O(000F00,AE,6,_,_,_,_,_ ), 0 , 78 , 0 , 10483, 406, 165), // #1541 - INST(Xsaveopt64 , X86M_Only , O(000F00,AE,6,_,1,_,_,_ ), 0 , 233, 0 , 10492, 407, 165), // #1542 - INST(Xsaves , X86M_Only , O(000F00,C7,5,_,_,_,_,_ ), 0 , 75 , 0 , 10503, 406, 163), // #1543 - INST(Xsaves64 , X86M_Only , O(000F00,C7,5,_,1,_,_,_ ), 0 , 230, 0 , 10510, 407, 163), // #1544 - INST(Xsetbv , X86Op , O(000F01,D1,_,_,_,_,_,_ ), 0 , 21 , 0 , 10519, 167, 161), // #1545 - INST(Xsusldtrk , X86Op , O(F20F01,E8,_,_,_,_,_,_ ), 0 , 92 , 0 , 10526, 30 , 162), // #1546 - INST(Xtest , X86Op , O(000F01,D6,_,_,_,_,_,_ ), 0 , 21 , 0 , 10536, 30 , 166) // #1547 + INST(Movabs , X86Movabs , 0 , 0 , 0 , 0 , 1949 , 111, 0 ), // #416 + INST(Movapd , ExtMov , O(660F00,28,_,_,_,_,_,_ ), O(660F00,29,_,_,_,_,_,_ ), 3 , 43 , 6238 , 112, 4 ), // #417 + INST(Movaps , ExtMov , O(000F00,28,_,_,_,_,_,_ ), O(000F00,29,_,_,_,_,_,_ ), 4 , 44 , 6246 , 112, 5 ), // #418 + INST(Movbe , ExtMovbe , O(000F38,F0,_,_,x,_,_,_ ), O(000F38,F1,_,_,x,_,_,_ ), 82 , 45 , 651 , 113, 79 ), // #419 + INST(Movd , ExtMovd , O(000F00,6E,_,_,_,_,_,_ ), O(000F00,7E,_,_,_,_,_,_ ), 4 , 46 , 8094 , 114, 80 ), // #420 + INST(Movddup , ExtMov , O(F20F00,12,_,_,_,_,_,_ ), 0 , 5 , 0 , 6260 , 6 , 6 ), // #421 + INST(Movdir64b , X86EnqcmdMovdir64b , O(660F38,F8,_,_,_,_,_,_ ), 0 , 2 , 0 , 1956 , 115, 81 ), // #422 + INST(Movdiri , X86MovntiMovdiri , O(000F38,F9,_,_,_,_,_,_ ), 0 , 82 , 0 , 1966 , 116, 82 ), // #423 + INST(Movdq2q , ExtMov , O(F20F00,D6,_,_,_,_,_,_ ), 0 , 5 , 0 , 1974 , 117, 4 ), // #424 + INST(Movdqa , ExtMov , O(660F00,6F,_,_,_,_,_,_ ), O(660F00,7F,_,_,_,_,_,_ ), 3 , 47 , 6269 , 112, 4 ), // #425 + INST(Movdqu , ExtMov , O(F30F00,6F,_,_,_,_,_,_ ), O(F30F00,7F,_,_,_,_,_,_ ), 6 , 48 , 6106 , 112, 4 ), // #426 + INST(Movhlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), 0 , 4 , 0 , 6344 , 118, 5 ), // #427 + INST(Movhpd , ExtMov , O(660F00,16,_,_,_,_,_,_ ), O(660F00,17,_,_,_,_,_,_ ), 3 , 49 , 6353 , 119, 4 ), // #428 + INST(Movhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), O(000F00,17,_,_,_,_,_,_ ), 4 , 50 , 6361 , 119, 5 ), // #429 + INST(Movlhps , ExtMov , O(000F00,16,_,_,_,_,_,_ ), 0 , 4 , 0 , 6369 , 118, 5 ), // #430 + INST(Movlpd , ExtMov , O(660F00,12,_,_,_,_,_,_ ), O(660F00,13,_,_,_,_,_,_ ), 3 , 51 , 6378 , 119, 4 ), // #431 + INST(Movlps , ExtMov , O(000F00,12,_,_,_,_,_,_ ), O(000F00,13,_,_,_,_,_,_ ), 4 , 52 , 6386 , 119, 5 ), // #432 + INST(Movmskpd , ExtMov , O(660F00,50,_,_,_,_,_,_ ), 0 , 3 , 0 , 6394 , 120, 4 ), // #433 + INST(Movmskps , ExtMov , O(000F00,50,_,_,_,_,_,_ ), 0 , 4 , 0 , 6404 , 120, 5 ), // #434 + INST(Movntdq , ExtMov , 0 , O(660F00,E7,_,_,_,_,_,_ ), 0 , 53 , 6414 , 121, 4 ), // #435 + INST(Movntdqa , ExtMov , O(660F38,2A,_,_,_,_,_,_ ), 0 , 2 , 0 , 6423 , 95 , 12 ), // #436 + INST(Movnti , X86MovntiMovdiri , O(000F00,C3,_,_,x,_,_,_ ), 0 , 4 , 0 , 1982 , 116, 4 ), // #437 + INST(Movntpd , ExtMov , 0 , O(660F00,2B,_,_,_,_,_,_ ), 0 , 54 , 6433 , 121, 4 ), // #438 + INST(Movntps , ExtMov , 0 , O(000F00,2B,_,_,_,_,_,_ ), 0 , 55 , 6442 , 121, 5 ), // #439 + INST(Movntq , ExtMov , 0 , O(000F00,E7,_,_,_,_,_,_ ), 0 , 56 , 1989 , 122, 75 ), // #440 + INST(Movntsd , ExtMov , 0 , O(F20F00,2B,_,_,_,_,_,_ ), 0 , 57 , 1996 , 123, 48 ), // #441 + INST(Movntss , ExtMov , 0 , O(F30F00,2B,_,_,_,_,_,_ ), 0 , 58 , 2004 , 124, 48 ), // #442 + INST(Movq , ExtMovq , O(000F00,6E,_,_,x,_,_,_ ), O(000F00,7E,_,_,x,_,_,_ ), 4 , 59 , 8105 , 125, 80 ), // #443 + INST(Movq2dq , ExtRm , O(F30F00,D6,_,_,_,_,_,_ ), 0 , 6 , 0 , 2012 , 126, 4 ), // #444 + INST(Movs , X86StrMm , O(000000,A4,_,_,_,_,_,_ ), 0 , 0 , 0 , 434 , 127, 73 ), // #445 + INST(Movsd , ExtMov , O(F20F00,10,_,_,_,_,_,_ ), O(F20F00,11,_,_,_,_,_,_ ), 5 , 60 , 6457 , 128, 4 ), // #446 + INST(Movshdup , ExtRm , O(F30F00,16,_,_,_,_,_,_ ), 0 , 6 , 0 , 6464 , 5 , 6 ), // #447 + INST(Movsldup , ExtRm , O(F30F00,12,_,_,_,_,_,_ ), 0 , 6 , 0 , 6474 , 5 , 6 ), // #448 + INST(Movss , ExtMov , O(F30F00,10,_,_,_,_,_,_ ), O(F30F00,11,_,_,_,_,_,_ ), 6 , 61 , 6484 , 129, 5 ), // #449 + INST(Movsx , X86MovsxMovzx , O(000F00,BE,_,_,x,_,_,_ ), 0 , 4 , 0 , 2020 , 130, 0 ), // #450 + INST(Movsxd , X86Rm , O(000000,63,_,_,x,_,_,_ ), 0 , 0 , 0 , 2026 , 131, 0 ), // #451 + INST(Movupd , ExtMov , O(660F00,10,_,_,_,_,_,_ ), O(660F00,11,_,_,_,_,_,_ ), 3 , 62 , 6491 , 112, 4 ), // #452 + INST(Movups , ExtMov , O(000F00,10,_,_,_,_,_,_ ), O(000F00,11,_,_,_,_,_,_ ), 4 , 63 , 6499 , 112, 5 ), // #453 + INST(Movzx , X86MovsxMovzx , O(000F00,B6,_,_,x,_,_,_ ), 0 , 4 , 0 , 2033 , 130, 0 ), // #454 + INST(Mpsadbw , ExtRmi , O(660F3A,42,_,_,_,_,_,_ ), 0 , 8 , 0 , 6507 , 8 , 12 ), // #455 + INST(Mul , X86M_GPB_MulDiv , O(000000,F6,4,_,x,_,_,_ ), 0 , 9 , 0 , 823 , 53 , 1 ), // #456 + INST(Mulpd , ExtRm , O(660F00,59,_,_,_,_,_,_ ), 0 , 3 , 0 , 6561 , 5 , 4 ), // #457 + INST(Mulps , ExtRm , O(000F00,59,_,_,_,_,_,_ ), 0 , 4 , 0 , 6568 , 5 , 5 ), // #458 + INST(Mulsd , ExtRm , O(F20F00,59,_,_,_,_,_,_ ), 0 , 5 , 0 , 6575 , 6 , 4 ), // #459 + INST(Mulss , ExtRm , O(F30F00,59,_,_,_,_,_,_ ), 0 , 6 , 0 , 6582 , 7 , 5 ), // #460 + INST(Mulx , VexRvm_ZDX_Wx , V(F20F38,F6,_,0,x,_,_,_ ), 0 , 83 , 0 , 2039 , 132, 83 ), // #461 + INST(Mwait , X86Op , O(000F01,C9,_,_,_,_,_,_ ), 0 , 21 , 0 , 3208 , 133, 77 ), // #462 + INST(Mwaitx , X86Op , O(000F01,FB,_,_,_,_,_,_ ), 0 , 21 , 0 , 2044 , 134, 78 ), // #463 + INST(Neg , X86M_GPB , O(000000,F6,3,_,x,_,_,_ ), 0 , 84 , 0 , 2051 , 135, 1 ), // #464 + INST(Nop , X86M_Nop , O(000000,90,_,_,_,_,_,_ ), 0 , 0 , 0 , 954 , 136, 0 ), // #465 + INST(Not , X86M_GPB , O(000000,F6,2,_,x,_,_,_ ), 0 , 1 , 0 , 2055 , 135, 0 ), // #466 + INST(Or , X86Arith , O(000000,08,1,_,x,_,_,_ ), 0 , 30 , 0 , 3204 , 137, 1 ), // #467 + INST(Orpd , ExtRm , O(660F00,56,_,_,_,_,_,_ ), 0 , 3 , 0 , 10311, 11 , 4 ), // #468 + INST(Orps , ExtRm , O(000F00,56,_,_,_,_,_,_ ), 0 , 4 , 0 , 10318, 11 , 5 ), // #469 + INST(Out , X86Out , O(000000,EE,_,_,_,_,_,_ ), O(000000,E6,_,_,_,_,_,_ ), 0 , 64 , 2059 , 138, 0 ), // #470 + INST(Outs , X86Outs , O(000000,6E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2063 , 139, 0 ), // #471 + INST(Pabsb , ExtRm_P , O(000F38,1C,_,_,_,_,_,_ ), 0 , 82 , 0 , 6664 , 140, 84 ), // #472 + INST(Pabsd , ExtRm_P , O(000F38,1E,_,_,_,_,_,_ ), 0 , 82 , 0 , 6671 , 140, 84 ), // #473 + INST(Pabsw , ExtRm_P , O(000F38,1D,_,_,_,_,_,_ ), 0 , 82 , 0 , 6685 , 140, 84 ), // #474 + INST(Packssdw , ExtRm_P , O(000F00,6B,_,_,_,_,_,_ ), 0 , 4 , 0 , 6692 , 140, 80 ), // #475 + INST(Packsswb , ExtRm_P , O(000F00,63,_,_,_,_,_,_ ), 0 , 4 , 0 , 6702 , 140, 80 ), // #476 + INST(Packusdw , ExtRm , O(660F38,2B,_,_,_,_,_,_ ), 0 , 2 , 0 , 6712 , 5 , 12 ), // #477 + INST(Packuswb , ExtRm_P , O(000F00,67,_,_,_,_,_,_ ), 0 , 4 , 0 , 6722 , 140, 80 ), // #478 + INST(Paddb , ExtRm_P , O(000F00,FC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6732 , 140, 80 ), // #479 + INST(Paddd , ExtRm_P , O(000F00,FE,_,_,_,_,_,_ ), 0 , 4 , 0 , 6739 , 140, 80 ), // #480 + INST(Paddq , ExtRm_P , O(000F00,D4,_,_,_,_,_,_ ), 0 , 4 , 0 , 6746 , 140, 4 ), // #481 + INST(Paddsb , ExtRm_P , O(000F00,EC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6753 , 140, 80 ), // #482 + INST(Paddsw , ExtRm_P , O(000F00,ED,_,_,_,_,_,_ ), 0 , 4 , 0 , 6761 , 140, 80 ), // #483 + INST(Paddusb , ExtRm_P , O(000F00,DC,_,_,_,_,_,_ ), 0 , 4 , 0 , 6769 , 140, 80 ), // #484 + INST(Paddusw , ExtRm_P , O(000F00,DD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6778 , 140, 80 ), // #485 + INST(Paddw , ExtRm_P , O(000F00,FD,_,_,_,_,_,_ ), 0 , 4 , 0 , 6787 , 140, 80 ), // #486 + INST(Palignr , ExtRmi_P , O(000F3A,0F,_,_,_,_,_,_ ), 0 , 85 , 0 , 6794 , 141, 6 ), // #487 + INST(Pand , ExtRm_P , O(000F00,DB,_,_,_,_,_,_ ), 0 , 4 , 0 , 6803 , 142, 80 ), // #488 + INST(Pandn , ExtRm_P , O(000F00,DF,_,_,_,_,_,_ ), 0 , 4 , 0 , 6816 , 143, 80 ), // #489 + INST(Pause , X86Op , O(F30000,90,_,_,_,_,_,_ ), 0 , 86 , 0 , 3168 , 30 , 0 ), // #490 + INST(Pavgb , ExtRm_P , O(000F00,E0,_,_,_,_,_,_ ), 0 , 4 , 0 , 6846 , 140, 85 ), // #491 + INST(Pavgusb , Ext3dNow , O(000F0F,BF,_,_,_,_,_,_ ), 0 , 87 , 0 , 2068 , 144, 50 ), // #492 + INST(Pavgw , ExtRm_P , O(000F00,E3,_,_,_,_,_,_ ), 0 , 4 , 0 , 6853 , 140, 85 ), // #493 + INST(Pblendvb , ExtRm_XMM0 , O(660F38,10,_,_,_,_,_,_ ), 0 , 2 , 0 , 6869 , 15 , 12 ), // #494 + INST(Pblendw , ExtRmi , O(660F3A,0E,_,_,_,_,_,_ ), 0 , 8 , 0 , 6879 , 8 , 12 ), // #495 + INST(Pclmulqdq , ExtRmi , O(660F3A,44,_,_,_,_,_,_ ), 0 , 8 , 0 , 6972 , 8 , 86 ), // #496 + INST(Pcmpeqb , ExtRm_P , O(000F00,74,_,_,_,_,_,_ ), 0 , 4 , 0 , 7004 , 143, 80 ), // #497 + INST(Pcmpeqd , ExtRm_P , O(000F00,76,_,_,_,_,_,_ ), 0 , 4 , 0 , 7013 , 143, 80 ), // #498 + INST(Pcmpeqq , ExtRm , O(660F38,29,_,_,_,_,_,_ ), 0 , 2 , 0 , 7022 , 145, 12 ), // #499 + INST(Pcmpeqw , ExtRm_P , O(000F00,75,_,_,_,_,_,_ ), 0 , 4 , 0 , 7031 , 143, 80 ), // #500 + INST(Pcmpestri , ExtRmi , O(660F3A,61,_,_,_,_,_,_ ), 0 , 8 , 0 , 7040 , 146, 87 ), // #501 + INST(Pcmpestrm , ExtRmi , O(660F3A,60,_,_,_,_,_,_ ), 0 , 8 , 0 , 7051 , 147, 87 ), // #502 + INST(Pcmpgtb , ExtRm_P , O(000F00,64,_,_,_,_,_,_ ), 0 , 4 , 0 , 7062 , 143, 80 ), // #503 + INST(Pcmpgtd , ExtRm_P , O(000F00,66,_,_,_,_,_,_ ), 0 , 4 , 0 , 7071 , 143, 80 ), // #504 + INST(Pcmpgtq , ExtRm , O(660F38,37,_,_,_,_,_,_ ), 0 , 2 , 0 , 7080 , 145, 43 ), // #505 + INST(Pcmpgtw , ExtRm_P , O(000F00,65,_,_,_,_,_,_ ), 0 , 4 , 0 , 7089 , 143, 80 ), // #506 + INST(Pcmpistri , ExtRmi , O(660F3A,63,_,_,_,_,_,_ ), 0 , 8 , 0 , 7098 , 148, 87 ), // #507 + INST(Pcmpistrm , ExtRmi , O(660F3A,62,_,_,_,_,_,_ ), 0 , 8 , 0 , 7109 , 149, 87 ), // #508 + INST(Pconfig , X86Op , O(000F01,C5,_,_,_,_,_,_ ), 0 , 21 , 0 , 2076 , 30 , 88 ), // #509 + INST(Pdep , VexRvm_Wx , V(F20F38,F5,_,0,x,_,_,_ ), 0 , 83 , 0 , 2084 , 10 , 83 ), // #510 + INST(Pext , VexRvm_Wx , V(F30F38,F5,_,0,x,_,_,_ ), 0 , 88 , 0 , 2089 , 10 , 83 ), // #511 + INST(Pextrb , ExtExtract , O(000F3A,14,_,_,_,_,_,_ ), 0 , 85 , 0 , 7596 , 150, 12 ), // #512 + INST(Pextrd , ExtExtract , O(000F3A,16,_,_,_,_,_,_ ), 0 , 85 , 0 , 7604 , 57 , 12 ), // #513 + INST(Pextrq , ExtExtract , O(000F3A,16,_,_,1,_,_,_ ), 0 , 89 , 0 , 7612 , 151, 12 ), // #514 + INST(Pextrw , ExtPextrw , O(000F00,C5,_,_,_,_,_,_ ), O(000F3A,15,_,_,_,_,_,_ ), 4 , 65 , 7620 , 152, 89 ), // #515 + INST(Pf2id , Ext3dNow , O(000F0F,1D,_,_,_,_,_,_ ), 0 , 87 , 0 , 2094 , 144, 50 ), // #516 + INST(Pf2iw , Ext3dNow , O(000F0F,1C,_,_,_,_,_,_ ), 0 , 87 , 0 , 2100 , 144, 90 ), // #517 + INST(Pfacc , Ext3dNow , O(000F0F,AE,_,_,_,_,_,_ ), 0 , 87 , 0 , 2106 , 144, 50 ), // #518 + INST(Pfadd , Ext3dNow , O(000F0F,9E,_,_,_,_,_,_ ), 0 , 87 , 0 , 2112 , 144, 50 ), // #519 + INST(Pfcmpeq , Ext3dNow , O(000F0F,B0,_,_,_,_,_,_ ), 0 , 87 , 0 , 2118 , 144, 50 ), // #520 + INST(Pfcmpge , Ext3dNow , O(000F0F,90,_,_,_,_,_,_ ), 0 , 87 , 0 , 2126 , 144, 50 ), // #521 + INST(Pfcmpgt , Ext3dNow , O(000F0F,A0,_,_,_,_,_,_ ), 0 , 87 , 0 , 2134 , 144, 50 ), // #522 + INST(Pfmax , Ext3dNow , O(000F0F,A4,_,_,_,_,_,_ ), 0 , 87 , 0 , 2142 , 144, 50 ), // #523 + INST(Pfmin , Ext3dNow , O(000F0F,94,_,_,_,_,_,_ ), 0 , 87 , 0 , 2148 , 144, 50 ), // #524 + INST(Pfmul , Ext3dNow , O(000F0F,B4,_,_,_,_,_,_ ), 0 , 87 , 0 , 2154 , 144, 50 ), // #525 + INST(Pfnacc , Ext3dNow , O(000F0F,8A,_,_,_,_,_,_ ), 0 , 87 , 0 , 2160 , 144, 90 ), // #526 + INST(Pfpnacc , Ext3dNow , O(000F0F,8E,_,_,_,_,_,_ ), 0 , 87 , 0 , 2167 , 144, 90 ), // #527 + INST(Pfrcp , Ext3dNow , O(000F0F,96,_,_,_,_,_,_ ), 0 , 87 , 0 , 2175 , 144, 50 ), // #528 + INST(Pfrcpit1 , Ext3dNow , O(000F0F,A6,_,_,_,_,_,_ ), 0 , 87 , 0 , 2181 , 144, 50 ), // #529 + INST(Pfrcpit2 , Ext3dNow , O(000F0F,B6,_,_,_,_,_,_ ), 0 , 87 , 0 , 2190 , 144, 50 ), // #530 + INST(Pfrcpv , Ext3dNow , O(000F0F,86,_,_,_,_,_,_ ), 0 , 87 , 0 , 2199 , 144, 91 ), // #531 + INST(Pfrsqit1 , Ext3dNow , O(000F0F,A7,_,_,_,_,_,_ ), 0 , 87 , 0 , 2206 , 144, 50 ), // #532 + INST(Pfrsqrt , Ext3dNow , O(000F0F,97,_,_,_,_,_,_ ), 0 , 87 , 0 , 2215 , 144, 50 ), // #533 + INST(Pfrsqrtv , Ext3dNow , O(000F0F,87,_,_,_,_,_,_ ), 0 , 87 , 0 , 2223 , 144, 91 ), // #534 + INST(Pfsub , Ext3dNow , O(000F0F,9A,_,_,_,_,_,_ ), 0 , 87 , 0 , 2232 , 144, 50 ), // #535 + INST(Pfsubr , Ext3dNow , O(000F0F,AA,_,_,_,_,_,_ ), 0 , 87 , 0 , 2238 , 144, 50 ), // #536 + INST(Phaddd , ExtRm_P , O(000F38,02,_,_,_,_,_,_ ), 0 , 82 , 0 , 7699 , 140, 84 ), // #537 + INST(Phaddsw , ExtRm_P , O(000F38,03,_,_,_,_,_,_ ), 0 , 82 , 0 , 7716 , 140, 84 ), // #538 + INST(Phaddw , ExtRm_P , O(000F38,01,_,_,_,_,_,_ ), 0 , 82 , 0 , 7785 , 140, 84 ), // #539 + INST(Phminposuw , ExtRm , O(660F38,41,_,_,_,_,_,_ ), 0 , 2 , 0 , 7811 , 5 , 12 ), // #540 + INST(Phsubd , ExtRm_P , O(000F38,06,_,_,_,_,_,_ ), 0 , 82 , 0 , 7832 , 140, 84 ), // #541 + INST(Phsubsw , ExtRm_P , O(000F38,07,_,_,_,_,_,_ ), 0 , 82 , 0 , 7849 , 140, 84 ), // #542 + INST(Phsubw , ExtRm_P , O(000F38,05,_,_,_,_,_,_ ), 0 , 82 , 0 , 7858 , 140, 84 ), // #543 + INST(Pi2fd , Ext3dNow , O(000F0F,0D,_,_,_,_,_,_ ), 0 , 87 , 0 , 2245 , 144, 50 ), // #544 + INST(Pi2fw , Ext3dNow , O(000F0F,0C,_,_,_,_,_,_ ), 0 , 87 , 0 , 2251 , 144, 90 ), // #545 + INST(Pinsrb , ExtRmi , O(660F3A,20,_,_,_,_,_,_ ), 0 , 8 , 0 , 7875 , 153, 12 ), // #546 + INST(Pinsrd , ExtRmi , O(660F3A,22,_,_,_,_,_,_ ), 0 , 8 , 0 , 7883 , 154, 12 ), // #547 + INST(Pinsrq , ExtRmi , O(660F3A,22,_,_,1,_,_,_ ), 0 , 90 , 0 , 7891 , 155, 12 ), // #548 + INST(Pinsrw , ExtRmi_P , O(000F00,C4,_,_,_,_,_,_ ), 0 , 4 , 0 , 7899 , 156, 85 ), // #549 + INST(Pmaddubsw , ExtRm_P , O(000F38,04,_,_,_,_,_,_ ), 0 , 82 , 0 , 8069 , 140, 84 ), // #550 + INST(Pmaddwd , ExtRm_P , O(000F00,F5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8080 , 140, 80 ), // #551 + INST(Pmaxsb , ExtRm , O(660F38,3C,_,_,_,_,_,_ ), 0 , 2 , 0 , 8111 , 11 , 12 ), // #552 + INST(Pmaxsd , ExtRm , O(660F38,3D,_,_,_,_,_,_ ), 0 , 2 , 0 , 8119 , 11 , 12 ), // #553 + INST(Pmaxsw , ExtRm_P , O(000F00,EE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8135 , 142, 85 ), // #554 + INST(Pmaxub , ExtRm_P , O(000F00,DE,_,_,_,_,_,_ ), 0 , 4 , 0 , 8143 , 142, 85 ), // #555 + INST(Pmaxud , ExtRm , O(660F38,3F,_,_,_,_,_,_ ), 0 , 2 , 0 , 8151 , 11 , 12 ), // #556 + INST(Pmaxuw , ExtRm , O(660F38,3E,_,_,_,_,_,_ ), 0 , 2 , 0 , 8167 , 11 , 12 ), // #557 + INST(Pminsb , ExtRm , O(660F38,38,_,_,_,_,_,_ ), 0 , 2 , 0 , 8175 , 11 , 12 ), // #558 + INST(Pminsd , ExtRm , O(660F38,39,_,_,_,_,_,_ ), 0 , 2 , 0 , 8183 , 11 , 12 ), // #559 + INST(Pminsw , ExtRm_P , O(000F00,EA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8199 , 142, 85 ), // #560 + INST(Pminub , ExtRm_P , O(000F00,DA,_,_,_,_,_,_ ), 0 , 4 , 0 , 8207 , 142, 85 ), // #561 + INST(Pminud , ExtRm , O(660F38,3B,_,_,_,_,_,_ ), 0 , 2 , 0 , 8215 , 11 , 12 ), // #562 + INST(Pminuw , ExtRm , O(660F38,3A,_,_,_,_,_,_ ), 0 , 2 , 0 , 8231 , 11 , 12 ), // #563 + INST(Pmovmskb , ExtRm_P , O(000F00,D7,_,_,_,_,_,_ ), 0 , 4 , 0 , 8309 , 157, 85 ), // #564 + INST(Pmovsxbd , ExtRm , O(660F38,21,_,_,_,_,_,_ ), 0 , 2 , 0 , 8406 , 7 , 12 ), // #565 + INST(Pmovsxbq , ExtRm , O(660F38,22,_,_,_,_,_,_ ), 0 , 2 , 0 , 8416 , 158, 12 ), // #566 + INST(Pmovsxbw , ExtRm , O(660F38,20,_,_,_,_,_,_ ), 0 , 2 , 0 , 8426 , 6 , 12 ), // #567 + INST(Pmovsxdq , ExtRm , O(660F38,25,_,_,_,_,_,_ ), 0 , 2 , 0 , 8436 , 6 , 12 ), // #568 + INST(Pmovsxwd , ExtRm , O(660F38,23,_,_,_,_,_,_ ), 0 , 2 , 0 , 8446 , 6 , 12 ), // #569 + INST(Pmovsxwq , ExtRm , O(660F38,24,_,_,_,_,_,_ ), 0 , 2 , 0 , 8456 , 7 , 12 ), // #570 + INST(Pmovzxbd , ExtRm , O(660F38,31,_,_,_,_,_,_ ), 0 , 2 , 0 , 8543 , 7 , 12 ), // #571 + INST(Pmovzxbq , ExtRm , O(660F38,32,_,_,_,_,_,_ ), 0 , 2 , 0 , 8553 , 158, 12 ), // #572 + INST(Pmovzxbw , ExtRm , O(660F38,30,_,_,_,_,_,_ ), 0 , 2 , 0 , 8563 , 6 , 12 ), // #573 + INST(Pmovzxdq , ExtRm , O(660F38,35,_,_,_,_,_,_ ), 0 , 2 , 0 , 8573 , 6 , 12 ), // #574 + INST(Pmovzxwd , ExtRm , O(660F38,33,_,_,_,_,_,_ ), 0 , 2 , 0 , 8583 , 6 , 12 ), // #575 + INST(Pmovzxwq , ExtRm , O(660F38,34,_,_,_,_,_,_ ), 0 , 2 , 0 , 8593 , 7 , 12 ), // #576 + INST(Pmuldq , ExtRm , O(660F38,28,_,_,_,_,_,_ ), 0 , 2 , 0 , 8603 , 5 , 12 ), // #577 + INST(Pmulhrsw , ExtRm_P , O(000F38,0B,_,_,_,_,_,_ ), 0 , 82 , 0 , 8611 , 140, 84 ), // #578 + INST(Pmulhrw , Ext3dNow , O(000F0F,B7,_,_,_,_,_,_ ), 0 , 87 , 0 , 2257 , 144, 50 ), // #579 + INST(Pmulhuw , ExtRm_P , O(000F00,E4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8621 , 140, 85 ), // #580 + INST(Pmulhw , ExtRm_P , O(000F00,E5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8630 , 140, 80 ), // #581 + INST(Pmulld , ExtRm , O(660F38,40,_,_,_,_,_,_ ), 0 , 2 , 0 , 8638 , 5 , 12 ), // #582 + INST(Pmullw , ExtRm_P , O(000F00,D5,_,_,_,_,_,_ ), 0 , 4 , 0 , 8654 , 140, 80 ), // #583 + INST(Pmuludq , ExtRm_P , O(000F00,F4,_,_,_,_,_,_ ), 0 , 4 , 0 , 8677 , 140, 4 ), // #584 + INST(Pop , X86Pop , O(000000,8F,0,_,_,_,_,_ ), O(000000,58,_,_,_,_,_,_ ), 0 , 66 , 2265 , 159, 0 ), // #585 + INST(Popa , X86Op , O(660000,61,_,_,_,_,_,_ ), 0 , 19 , 0 , 2269 , 78 , 0 ), // #586 + INST(Popad , X86Op , O(000000,61,_,_,_,_,_,_ ), 0 , 0 , 0 , 2274 , 78 , 0 ), // #587 + INST(Popcnt , X86Rm_Raw66H , O(F30F00,B8,_,_,x,_,_,_ ), 0 , 6 , 0 , 2280 , 22 , 92 ), // #588 + INST(Popf , X86Op , O(660000,9D,_,_,_,_,_,_ ), 0 , 19 , 0 , 2287 , 30 , 93 ), // #589 + INST(Popfd , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2292 , 78 , 93 ), // #590 + INST(Popfq , X86Op , O(000000,9D,_,_,_,_,_,_ ), 0 , 0 , 0 , 2298 , 160, 93 ), // #591 + INST(Por , ExtRm_P , O(000F00,EB,_,_,_,_,_,_ ), 0 , 4 , 0 , 8722 , 142, 80 ), // #592 + INST(Prefetch , X86M_Only , O(000F00,0D,0,_,_,_,_,_ ), 0 , 4 , 0 , 2304 , 31 , 50 ), // #593 + INST(Prefetchnta , X86M_Only , O(000F00,18,0,_,_,_,_,_ ), 0 , 4 , 0 , 2313 , 31 , 75 ), // #594 + INST(Prefetcht0 , X86M_Only , O(000F00,18,1,_,_,_,_,_ ), 0 , 28 , 0 , 2325 , 31 , 75 ), // #595 + INST(Prefetcht1 , X86M_Only , O(000F00,18,2,_,_,_,_,_ ), 0 , 74 , 0 , 2336 , 31 , 75 ), // #596 + INST(Prefetcht2 , X86M_Only , O(000F00,18,3,_,_,_,_,_ ), 0 , 76 , 0 , 2347 , 31 , 75 ), // #597 + INST(Prefetchw , X86M_Only , O(000F00,0D,1,_,_,_,_,_ ), 0 , 28 , 0 , 2358 , 31 , 94 ), // #598 + INST(Prefetchwt1 , X86M_Only , O(000F00,0D,2,_,_,_,_,_ ), 0 , 74 , 0 , 2368 , 31 , 95 ), // #599 + INST(Psadbw , ExtRm_P , O(000F00,F6,_,_,_,_,_,_ ), 0 , 4 , 0 , 4275 , 140, 85 ), // #600 + INST(Pshufb , ExtRm_P , O(000F38,00,_,_,_,_,_,_ ), 0 , 82 , 0 , 9048 , 140, 84 ), // #601 + INST(Pshufd , ExtRmi , O(660F00,70,_,_,_,_,_,_ ), 0 , 3 , 0 , 9069 , 8 , 4 ), // #602 + INST(Pshufhw , ExtRmi , O(F30F00,70,_,_,_,_,_,_ ), 0 , 6 , 0 , 9077 , 8 , 4 ), // #603 + INST(Pshuflw , ExtRmi , O(F20F00,70,_,_,_,_,_,_ ), 0 , 5 , 0 , 9086 , 8 , 4 ), // #604 + INST(Pshufw , ExtRmi_P , O(000F00,70,_,_,_,_,_,_ ), 0 , 4 , 0 , 2380 , 161, 75 ), // #605 + INST(Psignb , ExtRm_P , O(000F38,08,_,_,_,_,_,_ ), 0 , 82 , 0 , 9095 , 140, 84 ), // #606 + INST(Psignd , ExtRm_P , O(000F38,0A,_,_,_,_,_,_ ), 0 , 82 , 0 , 9103 , 140, 84 ), // #607 + INST(Psignw , ExtRm_P , O(000F38,09,_,_,_,_,_,_ ), 0 , 82 , 0 , 9111 , 140, 84 ), // #608 + INST(Pslld , ExtRmRi_P , O(000F00,F2,_,_,_,_,_,_ ), O(000F00,72,6,_,_,_,_,_ ), 4 , 67 , 9119 , 162, 80 ), // #609 + INST(Pslldq , ExtRmRi , 0 , O(660F00,73,7,_,_,_,_,_ ), 0 , 68 , 9126 , 163, 4 ), // #610 + INST(Psllq , ExtRmRi_P , O(000F00,F3,_,_,_,_,_,_ ), O(000F00,73,6,_,_,_,_,_ ), 4 , 69 , 9134 , 162, 80 ), // #611 + INST(Psllw , ExtRmRi_P , O(000F00,F1,_,_,_,_,_,_ ), O(000F00,71,6,_,_,_,_,_ ), 4 , 70 , 9165 , 162, 80 ), // #612 + INST(Psmash , X86Op , O(F30F01,FF,_,_,_,_,_,_ ), 0 , 81 , 0 , 2387 , 160, 96 ), // #613 + INST(Psrad , ExtRmRi_P , O(000F00,E2,_,_,_,_,_,_ ), O(000F00,72,4,_,_,_,_,_ ), 4 , 71 , 9172 , 162, 80 ), // #614 + INST(Psraw , ExtRmRi_P , O(000F00,E1,_,_,_,_,_,_ ), O(000F00,71,4,_,_,_,_,_ ), 4 , 72 , 9210 , 162, 80 ), // #615 + INST(Psrld , ExtRmRi_P , O(000F00,D2,_,_,_,_,_,_ ), O(000F00,72,2,_,_,_,_,_ ), 4 , 73 , 9217 , 162, 80 ), // #616 + INST(Psrldq , ExtRmRi , 0 , O(660F00,73,3,_,_,_,_,_ ), 0 , 74 , 9224 , 163, 4 ), // #617 + INST(Psrlq , ExtRmRi_P , O(000F00,D3,_,_,_,_,_,_ ), O(000F00,73,2,_,_,_,_,_ ), 4 , 75 , 9232 , 162, 80 ), // #618 + INST(Psrlw , ExtRmRi_P , O(000F00,D1,_,_,_,_,_,_ ), O(000F00,71,2,_,_,_,_,_ ), 4 , 76 , 9263 , 162, 80 ), // #619 + INST(Psubb , ExtRm_P , O(000F00,F8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9270 , 143, 80 ), // #620 + INST(Psubd , ExtRm_P , O(000F00,FA,_,_,_,_,_,_ ), 0 , 4 , 0 , 9277 , 143, 80 ), // #621 + INST(Psubq , ExtRm_P , O(000F00,FB,_,_,_,_,_,_ ), 0 , 4 , 0 , 9284 , 143, 4 ), // #622 + INST(Psubsb , ExtRm_P , O(000F00,E8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9291 , 143, 80 ), // #623 + INST(Psubsw , ExtRm_P , O(000F00,E9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9299 , 143, 80 ), // #624 + INST(Psubusb , ExtRm_P , O(000F00,D8,_,_,_,_,_,_ ), 0 , 4 , 0 , 9307 , 143, 80 ), // #625 + INST(Psubusw , ExtRm_P , O(000F00,D9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9316 , 143, 80 ), // #626 + INST(Psubw , ExtRm_P , O(000F00,F9,_,_,_,_,_,_ ), 0 , 4 , 0 , 9325 , 143, 80 ), // #627 + INST(Pswapd , Ext3dNow , O(000F0F,BB,_,_,_,_,_,_ ), 0 , 87 , 0 , 2394 , 144, 90 ), // #628 + INST(Ptest , ExtRm , O(660F38,17,_,_,_,_,_,_ ), 0 , 2 , 0 , 9354 , 5 , 97 ), // #629 + INST(Ptwrite , X86M , O(F30F00,AE,4,_,_,_,_,_ ), 0 , 91 , 0 , 2401 , 164, 98 ), // #630 + INST(Punpckhbw , ExtRm_P , O(000F00,68,_,_,_,_,_,_ ), 0 , 4 , 0 , 9437 , 140, 80 ), // #631 + INST(Punpckhdq , ExtRm_P , O(000F00,6A,_,_,_,_,_,_ ), 0 , 4 , 0 , 9448 , 140, 80 ), // #632 + INST(Punpckhqdq , ExtRm , O(660F00,6D,_,_,_,_,_,_ ), 0 , 3 , 0 , 9459 , 5 , 4 ), // #633 + INST(Punpckhwd , ExtRm_P , O(000F00,69,_,_,_,_,_,_ ), 0 , 4 , 0 , 9471 , 140, 80 ), // #634 + INST(Punpcklbw , ExtRm_P , O(000F00,60,_,_,_,_,_,_ ), 0 , 4 , 0 , 9482 , 140, 80 ), // #635 + INST(Punpckldq , ExtRm_P , O(000F00,62,_,_,_,_,_,_ ), 0 , 4 , 0 , 9493 , 140, 80 ), // #636 + INST(Punpcklqdq , ExtRm , O(660F00,6C,_,_,_,_,_,_ ), 0 , 3 , 0 , 9504 , 5 , 4 ), // #637 + INST(Punpcklwd , ExtRm_P , O(000F00,61,_,_,_,_,_,_ ), 0 , 4 , 0 , 9516 , 140, 80 ), // #638 + INST(Push , X86Push , O(000000,FF,6,_,_,_,_,_ ), O(000000,50,_,_,_,_,_,_ ), 31 , 77 , 2409 , 165, 0 ), // #639 + INST(Pusha , X86Op , O(660000,60,_,_,_,_,_,_ ), 0 , 19 , 0 , 2414 , 78 , 0 ), // #640 + INST(Pushad , X86Op , O(000000,60,_,_,_,_,_,_ ), 0 , 0 , 0 , 2420 , 78 , 0 ), // #641 + INST(Pushf , X86Op , O(660000,9C,_,_,_,_,_,_ ), 0 , 19 , 0 , 2427 , 30 , 99 ), // #642 + INST(Pushfd , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2433 , 78 , 99 ), // #643 + INST(Pushfq , X86Op , O(000000,9C,_,_,_,_,_,_ ), 0 , 0 , 0 , 2440 , 160, 99 ), // #644 + INST(Pvalidate , X86Op , O(F20F01,FF,_,_,_,_,_,_ ), 0 , 92 , 0 , 2447 , 30 , 100), // #645 + INST(Pxor , ExtRm_P , O(000F00,EF,_,_,_,_,_,_ ), 0 , 4 , 0 , 9527 , 143, 80 ), // #646 + INST(Rcl , X86Rot , O(000000,D0,2,_,x,_,_,_ ), 0 , 1 , 0 , 2457 , 166, 101), // #647 + INST(Rcpps , ExtRm , O(000F00,53,_,_,_,_,_,_ ), 0 , 4 , 0 , 9655 , 5 , 5 ), // #648 + INST(Rcpss , ExtRm , O(F30F00,53,_,_,_,_,_,_ ), 0 , 6 , 0 , 9662 , 7 , 5 ), // #649 + INST(Rcr , X86Rot , O(000000,D0,3,_,x,_,_,_ ), 0 , 84 , 0 , 2461 , 166, 101), // #650 + INST(Rdfsbase , X86M , O(F30F00,AE,0,_,x,_,_,_ ), 0 , 6 , 0 , 2465 , 167, 102), // #651 + INST(Rdgsbase , X86M , O(F30F00,AE,1,_,x,_,_,_ ), 0 , 93 , 0 , 2474 , 167, 102), // #652 + INST(Rdmsr , X86Op , O(000F00,32,_,_,_,_,_,_ ), 0 , 4 , 0 , 2483 , 168, 103), // #653 + INST(Rdpid , X86R_Native , O(F30F00,C7,7,_,_,_,_,_ ), 0 , 94 , 0 , 2489 , 169, 104), // #654 + INST(Rdpkru , X86Op , O(000F01,EE,_,_,_,_,_,_ ), 0 , 21 , 0 , 2495 , 168, 105), // #655 + INST(Rdpmc , X86Op , O(000F00,33,_,_,_,_,_,_ ), 0 , 4 , 0 , 2502 , 168, 0 ), // #656 + INST(Rdpru , X86Op , O(000F01,FD,_,_,_,_,_,_ ), 0 , 21 , 0 , 2508 , 168, 106), // #657 + INST(Rdrand , X86M , O(000F00,C7,6,_,x,_,_,_ ), 0 , 78 , 0 , 2514 , 23 , 107), // #658 + INST(Rdseed , X86M , O(000F00,C7,7,_,x,_,_,_ ), 0 , 22 , 0 , 2521 , 23 , 108), // #659 + INST(Rdsspd , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 93 , 0 , 2528 , 73 , 54 ), // #660 + INST(Rdsspq , X86M , O(F30F00,1E,1,_,_,_,_,_ ), 0 , 93 , 0 , 2535 , 74 , 54 ), // #661 + INST(Rdtsc , X86Op , O(000F00,31,_,_,_,_,_,_ ), 0 , 4 , 0 , 2542 , 28 , 109), // #662 + INST(Rdtscp , X86Op , O(000F01,F9,_,_,_,_,_,_ ), 0 , 21 , 0 , 2548 , 168, 110), // #663 + INST(Ret , X86Ret , O(000000,C2,_,_,_,_,_,_ ), 0 , 0 , 0 , 3051 , 170, 0 ), // #664 + INST(Rmpadjust , X86Op , O(F30F01,FE,_,_,_,_,_,_ ), 0 , 81 , 0 , 2555 , 160, 96 ), // #665 + INST(Rmpupdate , X86Op , O(F20F01,FE,_,_,_,_,_,_ ), 0 , 92 , 0 , 2565 , 160, 96 ), // #666 + INST(Rol , X86Rot , O(000000,D0,0,_,x,_,_,_ ), 0 , 0 , 0 , 2575 , 166, 111), // #667 + INST(Ror , X86Rot , O(000000,D0,1,_,x,_,_,_ ), 0 , 30 , 0 , 2579 , 166, 111), // #668 + INST(Rorx , VexRmi_Wx , V(F20F3A,F0,_,0,x,_,_,_ ), 0 , 95 , 0 , 2583 , 171, 83 ), // #669 + INST(Roundpd , ExtRmi , O(660F3A,09,_,_,_,_,_,_ ), 0 , 8 , 0 , 9757 , 8 , 12 ), // #670 + INST(Roundps , ExtRmi , O(660F3A,08,_,_,_,_,_,_ ), 0 , 8 , 0 , 9766 , 8 , 12 ), // #671 + INST(Roundsd , ExtRmi , O(660F3A,0B,_,_,_,_,_,_ ), 0 , 8 , 0 , 9775 , 36 , 12 ), // #672 + INST(Roundss , ExtRmi , O(660F3A,0A,_,_,_,_,_,_ ), 0 , 8 , 0 , 9784 , 37 , 12 ), // #673 + INST(Rsm , X86Op , O(000F00,AA,_,_,_,_,_,_ ), 0 , 4 , 0 , 2588 , 78 , 1 ), // #674 + INST(Rsqrtps , ExtRm , O(000F00,52,_,_,_,_,_,_ ), 0 , 4 , 0 , 9881 , 5 , 5 ), // #675 + INST(Rsqrtss , ExtRm , O(F30F00,52,_,_,_,_,_,_ ), 0 , 6 , 0 , 9890 , 7 , 5 ), // #676 + INST(Rstorssp , X86M , O(F30F00,01,5,_,_,_,_,_ ), 0 , 62 , 0 , 2592 , 32 , 24 ), // #677 + INST(Sahf , X86Op , O(000000,9E,_,_,_,_,_,_ ), 0 , 0 , 0 , 2601 , 93 , 112), // #678 + INST(Sal , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2606 , 166, 1 ), // #679 + INST(Sar , X86Rot , O(000000,D0,7,_,x,_,_,_ ), 0 , 26 , 0 , 2610 , 166, 1 ), // #680 + INST(Sarx , VexRmv_Wx , V(F30F38,F7,_,0,x,_,_,_ ), 0 , 88 , 0 , 2614 , 13 , 83 ), // #681 + INST(Saveprevssp , X86Op , O(F30F01,EA,_,_,_,_,_,_ ), 0 , 81 , 0 , 2619 , 30 , 24 ), // #682 + INST(Sbb , X86Arith , O(000000,18,3,_,x,_,_,_ ), 0 , 84 , 0 , 2631 , 172, 2 ), // #683 + INST(Scas , X86StrRm , O(000000,AE,_,_,_,_,_,_ ), 0 , 0 , 0 , 2635 , 173, 36 ), // #684 + INST(Serialize , X86Op , O(000F01,E8,_,_,_,_,_,_ ), 0 , 21 , 0 , 2640 , 30 , 113), // #685 + INST(Seta , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2650 , 174, 57 ), // #686 + INST(Setae , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2655 , 174, 58 ), // #687 + INST(Setb , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2661 , 174, 58 ), // #688 + INST(Setbe , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2666 , 174, 57 ), // #689 + INST(Setc , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2672 , 174, 58 ), // #690 + INST(Sete , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2677 , 174, 59 ), // #691 + INST(Setg , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2682 , 174, 60 ), // #692 + INST(Setge , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2687 , 174, 61 ), // #693 + INST(Setl , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2693 , 174, 61 ), // #694 + INST(Setle , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2698 , 174, 60 ), // #695 + INST(Setna , X86Set , O(000F00,96,_,_,_,_,_,_ ), 0 , 4 , 0 , 2704 , 174, 57 ), // #696 + INST(Setnae , X86Set , O(000F00,92,_,_,_,_,_,_ ), 0 , 4 , 0 , 2710 , 174, 58 ), // #697 + INST(Setnb , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2717 , 174, 58 ), // #698 + INST(Setnbe , X86Set , O(000F00,97,_,_,_,_,_,_ ), 0 , 4 , 0 , 2723 , 174, 57 ), // #699 + INST(Setnc , X86Set , O(000F00,93,_,_,_,_,_,_ ), 0 , 4 , 0 , 2730 , 174, 58 ), // #700 + INST(Setne , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2736 , 174, 59 ), // #701 + INST(Setng , X86Set , O(000F00,9E,_,_,_,_,_,_ ), 0 , 4 , 0 , 2742 , 174, 60 ), // #702 + INST(Setnge , X86Set , O(000F00,9C,_,_,_,_,_,_ ), 0 , 4 , 0 , 2748 , 174, 61 ), // #703 + INST(Setnl , X86Set , O(000F00,9D,_,_,_,_,_,_ ), 0 , 4 , 0 , 2755 , 174, 61 ), // #704 + INST(Setnle , X86Set , O(000F00,9F,_,_,_,_,_,_ ), 0 , 4 , 0 , 2761 , 174, 60 ), // #705 + INST(Setno , X86Set , O(000F00,91,_,_,_,_,_,_ ), 0 , 4 , 0 , 2768 , 174, 55 ), // #706 + INST(Setnp , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2774 , 174, 62 ), // #707 + INST(Setns , X86Set , O(000F00,99,_,_,_,_,_,_ ), 0 , 4 , 0 , 2780 , 174, 63 ), // #708 + INST(Setnz , X86Set , O(000F00,95,_,_,_,_,_,_ ), 0 , 4 , 0 , 2786 , 174, 59 ), // #709 + INST(Seto , X86Set , O(000F00,90,_,_,_,_,_,_ ), 0 , 4 , 0 , 2792 , 174, 55 ), // #710 + INST(Setp , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2797 , 174, 62 ), // #711 + INST(Setpe , X86Set , O(000F00,9A,_,_,_,_,_,_ ), 0 , 4 , 0 , 2802 , 174, 62 ), // #712 + INST(Setpo , X86Set , O(000F00,9B,_,_,_,_,_,_ ), 0 , 4 , 0 , 2808 , 174, 62 ), // #713 + INST(Sets , X86Set , O(000F00,98,_,_,_,_,_,_ ), 0 , 4 , 0 , 2814 , 174, 63 ), // #714 + INST(Setssbsy , X86Op , O(F30F01,E8,_,_,_,_,_,_ ), 0 , 81 , 0 , 2819 , 30 , 54 ), // #715 + INST(Setz , X86Set , O(000F00,94,_,_,_,_,_,_ ), 0 , 4 , 0 , 2828 , 174, 59 ), // #716 + INST(Sfence , X86Fence , O(000F00,AE,7,_,_,_,_,_ ), 0 , 22 , 0 , 2833 , 30 , 75 ), // #717 + INST(Sgdt , X86M_Only , O(000F00,01,0,_,_,_,_,_ ), 0 , 4 , 0 , 2840 , 31 , 0 ), // #718 + INST(Sha1msg1 , ExtRm , O(000F38,C9,_,_,_,_,_,_ ), 0 , 82 , 0 , 2845 , 5 , 114), // #719 + INST(Sha1msg2 , ExtRm , O(000F38,CA,_,_,_,_,_,_ ), 0 , 82 , 0 , 2854 , 5 , 114), // #720 + INST(Sha1nexte , ExtRm , O(000F38,C8,_,_,_,_,_,_ ), 0 , 82 , 0 , 2863 , 5 , 114), // #721 + INST(Sha1rnds4 , ExtRmi , O(000F3A,CC,_,_,_,_,_,_ ), 0 , 85 , 0 , 2873 , 8 , 114), // #722 + INST(Sha256msg1 , ExtRm , O(000F38,CC,_,_,_,_,_,_ ), 0 , 82 , 0 , 2883 , 5 , 114), // #723 + INST(Sha256msg2 , ExtRm , O(000F38,CD,_,_,_,_,_,_ ), 0 , 82 , 0 , 2894 , 5 , 114), // #724 + INST(Sha256rnds2 , ExtRm_XMM0 , O(000F38,CB,_,_,_,_,_,_ ), 0 , 82 , 0 , 2905 , 15 , 114), // #725 + INST(Shl , X86Rot , O(000000,D0,4,_,x,_,_,_ ), 0 , 9 , 0 , 2917 , 166, 1 ), // #726 + INST(Shld , X86ShldShrd , O(000F00,A4,_,_,x,_,_,_ ), 0 , 4 , 0 , 8926 , 175, 1 ), // #727 + INST(Shlx , VexRmv_Wx , V(660F38,F7,_,0,x,_,_,_ ), 0 , 96 , 0 , 2921 , 13 , 83 ), // #728 + INST(Shr , X86Rot , O(000000,D0,5,_,x,_,_,_ ), 0 , 61 , 0 , 2926 , 166, 1 ), // #729 + INST(Shrd , X86ShldShrd , O(000F00,AC,_,_,x,_,_,_ ), 0 , 4 , 0 , 2930 , 175, 1 ), // #730 + INST(Shrx , VexRmv_Wx , V(F20F38,F7,_,0,x,_,_,_ ), 0 , 83 , 0 , 2935 , 13 , 83 ), // #731 + INST(Shufpd , ExtRmi , O(660F00,C6,_,_,_,_,_,_ ), 0 , 3 , 0 , 10151, 8 , 4 ), // #732 + INST(Shufps , ExtRmi , O(000F00,C6,_,_,_,_,_,_ ), 0 , 4 , 0 , 10159, 8 , 5 ), // #733 + INST(Sidt , X86M_Only , O(000F00,01,1,_,_,_,_,_ ), 0 , 28 , 0 , 2940 , 31 , 0 ), // #734 + INST(Skinit , X86Op_xAX , O(000F01,DE,_,_,_,_,_,_ ), 0 , 21 , 0 , 2945 , 51 , 115), // #735 + INST(Sldt , X86M , O(000F00,00,0,_,_,_,_,_ ), 0 , 4 , 0 , 2952 , 176, 0 ), // #736 + INST(Slwpcb , VexR_Wx , V(XOP_M9,12,1,0,x,_,_,_ ), 0 , 11 , 0 , 2957 , 102, 72 ), // #737 + INST(Smsw , X86M , O(000F00,01,4,_,_,_,_,_ ), 0 , 97 , 0 , 2964 , 176, 0 ), // #738 + INST(Sqrtpd , ExtRm , O(660F00,51,_,_,_,_,_,_ ), 0 , 3 , 0 , 10167, 5 , 4 ), // #739 + INST(Sqrtps , ExtRm , O(000F00,51,_,_,_,_,_,_ ), 0 , 4 , 0 , 9882 , 5 , 5 ), // #740 + INST(Sqrtsd , ExtRm , O(F20F00,51,_,_,_,_,_,_ ), 0 , 5 , 0 , 10183, 6 , 4 ), // #741 + INST(Sqrtss , ExtRm , O(F30F00,51,_,_,_,_,_,_ ), 0 , 6 , 0 , 9891 , 7 , 5 ), // #742 + INST(Stac , X86Op , O(000F01,CB,_,_,_,_,_,_ ), 0 , 21 , 0 , 2969 , 30 , 16 ), // #743 + INST(Stc , X86Op , O(000000,F9,_,_,_,_,_,_ ), 0 , 0 , 0 , 2974 , 30 , 17 ), // #744 + INST(Std , X86Op , O(000000,FD,_,_,_,_,_,_ ), 0 , 0 , 0 , 6909 , 30 , 18 ), // #745 + INST(Stgi , X86Op , O(000F01,DC,_,_,_,_,_,_ ), 0 , 21 , 0 , 2978 , 30 , 115), // #746 + INST(Sti , X86Op , O(000000,FB,_,_,_,_,_,_ ), 0 , 0 , 0 , 2983 , 30 , 23 ), // #747 + INST(Stmxcsr , X86M_Only , O(000F00,AE,3,_,_,_,_,_ ), 0 , 76 , 0 , 10199, 96 , 5 ), // #748 + INST(Stos , X86StrMr , O(000000,AA,_,_,_,_,_,_ ), 0 , 0 , 0 , 2987 , 177, 73 ), // #749 + INST(Str , X86M , O(000F00,00,1,_,_,_,_,_ ), 0 , 28 , 0 , 2992 , 176, 0 ), // #750 + INST(Sttilecfg , AmxCfg , V(660F38,49,_,0,0,_,_,_ ), 0 , 96 , 0 , 2996 , 98 , 71 ), // #751 + INST(Sub , X86Arith , O(000000,28,5,_,x,_,_,_ ), 0 , 61 , 0 , 861 , 172, 1 ), // #752 + INST(Subpd , ExtRm , O(660F00,5C,_,_,_,_,_,_ ), 0 , 3 , 0 , 4851 , 5 , 4 ), // #753 + INST(Subps , ExtRm , O(000F00,5C,_,_,_,_,_,_ ), 0 , 4 , 0 , 4863 , 5 , 5 ), // #754 + INST(Subsd , ExtRm , O(F20F00,5C,_,_,_,_,_,_ ), 0 , 5 , 0 , 5539 , 6 , 4 ), // #755 + INST(Subss , ExtRm , O(F30F00,5C,_,_,_,_,_,_ ), 0 , 6 , 0 , 5549 , 7 , 5 ), // #756 + INST(Swapgs , X86Op , O(000F01,F8,_,_,_,_,_,_ ), 0 , 21 , 0 , 3006 , 160, 0 ), // #757 + INST(Syscall , X86Op , O(000F00,05,_,_,_,_,_,_ ), 0 , 4 , 0 , 3013 , 160, 0 ), // #758 + INST(Sysenter , X86Op , O(000F00,34,_,_,_,_,_,_ ), 0 , 4 , 0 , 3021 , 30 , 0 ), // #759 + INST(Sysexit , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 3030 , 30 , 0 ), // #760 + INST(Sysexit64 , X86Op , O(000F00,35,_,_,_,_,_,_ ), 0 , 4 , 0 , 3038 , 30 , 0 ), // #761 + INST(Sysret , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 3048 , 160, 0 ), // #762 + INST(Sysret64 , X86Op , O(000F00,07,_,_,_,_,_,_ ), 0 , 4 , 0 , 3055 , 160, 0 ), // #763 + INST(T1mskc , VexVm_Wx , V(XOP_M9,01,7,0,x,_,_,_ ), 0 , 98 , 0 , 3064 , 14 , 11 ), // #764 + INST(Tdpbf16ps , AmxRmv , V(F30F38,5C,_,0,0,_,_,_ ), 0 , 88 , 0 , 3071 , 178, 116), // #765 + INST(Tdpbssd , AmxRmv , V(F20F38,5E,_,0,0,_,_,_ ), 0 , 83 , 0 , 3081 , 178, 117), // #766 + INST(Tdpbsud , AmxRmv , V(F30F38,5E,_,0,0,_,_,_ ), 0 , 88 , 0 , 3089 , 178, 117), // #767 + INST(Tdpbusd , AmxRmv , V(660F38,5E,_,0,0,_,_,_ ), 0 , 96 , 0 , 3097 , 178, 117), // #768 + INST(Tdpbuud , AmxRmv , V(000F38,5E,_,0,0,_,_,_ ), 0 , 10 , 0 , 3105 , 178, 117), // #769 + INST(Test , X86Test , O(000000,84,_,_,x,_,_,_ ), O(000000,F6,_,_,x,_,_,_ ), 0 , 78 , 9355 , 179, 1 ), // #770 + INST(Tileloadd , AmxRm , V(F20F38,4B,_,0,0,_,_,_ ), 0 , 83 , 0 , 3113 , 180, 71 ), // #771 + INST(Tileloaddt1 , AmxRm , V(660F38,4B,_,0,0,_,_,_ ), 0 , 96 , 0 , 3123 , 180, 71 ), // #772 + INST(Tilerelease , VexOpMod , V(000F38,49,0,0,0,_,_,_ ), 0 , 10 , 0 , 3135 , 181, 71 ), // #773 + INST(Tilestored , AmxMr , V(F30F38,4B,_,0,0,_,_,_ ), 0 , 88 , 0 , 3147 , 182, 71 ), // #774 + INST(Tilezero , AmxR , V(F20F38,49,_,0,0,_,_,_ ), 0 , 83 , 0 , 3158 , 183, 71 ), // #775 + INST(Tpause , X86R32_EDX_EAX , O(660F00,AE,6,_,_,_,_,_ ), 0 , 25 , 0 , 3167 , 184, 118), // #776 + INST(Tzcnt , X86Rm_Raw66H , O(F30F00,BC,_,_,x,_,_,_ ), 0 , 6 , 0 , 3174 , 22 , 9 ), // #777 + INST(Tzmsk , VexVm_Wx , V(XOP_M9,01,4,0,x,_,_,_ ), 0 , 99 , 0 , 3180 , 14 , 11 ), // #778 + INST(Ucomisd , ExtRm , O(660F00,2E,_,_,_,_,_,_ ), 0 , 3 , 0 , 10252, 6 , 40 ), // #779 + INST(Ucomiss , ExtRm , O(000F00,2E,_,_,_,_,_,_ ), 0 , 4 , 0 , 10261, 7 , 41 ), // #780 + INST(Ud0 , X86M , O(000F00,FF,_,_,_,_,_,_ ), 0 , 4 , 0 , 3186 , 185, 0 ), // #781 + INST(Ud1 , X86M , O(000F00,B9,_,_,_,_,_,_ ), 0 , 4 , 0 , 3190 , 185, 0 ), // #782 + INST(Ud2 , X86Op , O(000F00,0B,_,_,_,_,_,_ ), 0 , 4 , 0 , 3194 , 30 , 0 ), // #783 + INST(Umonitor , X86R_FromM , O(F30F00,AE,6,_,_,_,_,_ ), 0 , 24 , 0 , 3198 , 186, 119), // #784 + INST(Umwait , X86R32_EDX_EAX , O(F20F00,AE,6,_,_,_,_,_ ), 0 , 100, 0 , 3207 , 184, 118), // #785 + INST(Unpckhpd , ExtRm , O(660F00,15,_,_,_,_,_,_ ), 0 , 3 , 0 , 10270, 5 , 4 ), // #786 + INST(Unpckhps , ExtRm , O(000F00,15,_,_,_,_,_,_ ), 0 , 4 , 0 , 10280, 5 , 5 ), // #787 + INST(Unpcklpd , ExtRm , O(660F00,14,_,_,_,_,_,_ ), 0 , 3 , 0 , 10290, 5 , 4 ), // #788 + INST(Unpcklps , ExtRm , O(000F00,14,_,_,_,_,_,_ ), 0 , 4 , 0 , 10300, 5 , 5 ), // #789 + INST(V4fmaddps , VexRm_T1_4X , E(F20F38,9A,_,2,_,0,2,T4X), 0 , 101, 0 , 3214 , 187, 120), // #790 + INST(V4fmaddss , VexRm_T1_4X , E(F20F38,9B,_,2,_,0,2,T4X), 0 , 101, 0 , 3224 , 188, 120), // #791 + INST(V4fnmaddps , VexRm_T1_4X , E(F20F38,AA,_,2,_,0,2,T4X), 0 , 101, 0 , 3234 , 187, 120), // #792 + INST(V4fnmaddss , VexRm_T1_4X , E(F20F38,AB,_,2,_,0,2,T4X), 0 , 101, 0 , 3245 , 188, 120), // #793 + INST(Vaddpd , VexRvm_Lx , V(660F00,58,_,x,I,1,4,FV ), 0 , 102, 0 , 3256 , 189, 121), // #794 + INST(Vaddps , VexRvm_Lx , V(000F00,58,_,x,I,0,4,FV ), 0 , 103, 0 , 3263 , 190, 121), // #795 + INST(Vaddsd , VexRvm , V(F20F00,58,_,I,I,1,3,T1S), 0 , 104, 0 , 3270 , 191, 122), // #796 + INST(Vaddss , VexRvm , V(F30F00,58,_,I,I,0,2,T1S), 0 , 105, 0 , 3277 , 192, 122), // #797 + INST(Vaddsubpd , VexRvm_Lx , V(660F00,D0,_,x,I,_,_,_ ), 0 , 68 , 0 , 3284 , 193, 123), // #798 + INST(Vaddsubps , VexRvm_Lx , V(F20F00,D0,_,x,I,_,_,_ ), 0 , 106, 0 , 3294 , 193, 123), // #799 + INST(Vaesdec , VexRvm_Lx , V(660F38,DE,_,x,I,_,4,FVM), 0 , 107, 0 , 3304 , 194, 124), // #800 + INST(Vaesdeclast , VexRvm_Lx , V(660F38,DF,_,x,I,_,4,FVM), 0 , 107, 0 , 3312 , 194, 124), // #801 + INST(Vaesenc , VexRvm_Lx , V(660F38,DC,_,x,I,_,4,FVM), 0 , 107, 0 , 3324 , 194, 124), // #802 + INST(Vaesenclast , VexRvm_Lx , V(660F38,DD,_,x,I,_,4,FVM), 0 , 107, 0 , 3332 , 194, 124), // #803 + INST(Vaesimc , VexRm , V(660F38,DB,_,0,I,_,_,_ ), 0 , 96 , 0 , 3344 , 195, 125), // #804 + INST(Vaeskeygenassist , VexRmi , V(660F3A,DF,_,0,I,_,_,_ ), 0 , 72 , 0 , 3352 , 196, 125), // #805 + INST(Valignd , VexRvmi_Lx , E(660F3A,03,_,x,_,0,4,FV ), 0 , 108, 0 , 3369 , 197, 126), // #806 + INST(Valignq , VexRvmi_Lx , E(660F3A,03,_,x,_,1,4,FV ), 0 , 109, 0 , 3377 , 198, 126), // #807 + INST(Vandnpd , VexRvm_Lx , V(660F00,55,_,x,I,1,4,FV ), 0 , 102, 0 , 3385 , 199, 127), // #808 + INST(Vandnps , VexRvm_Lx , V(000F00,55,_,x,I,0,4,FV ), 0 , 103, 0 , 3393 , 200, 127), // #809 + INST(Vandpd , VexRvm_Lx , V(660F00,54,_,x,I,1,4,FV ), 0 , 102, 0 , 3401 , 201, 127), // #810 + INST(Vandps , VexRvm_Lx , V(000F00,54,_,x,I,0,4,FV ), 0 , 103, 0 , 3408 , 202, 127), // #811 + INST(Vblendmb , VexRvm_Lx , E(660F38,66,_,x,_,0,4,FVM), 0 , 110, 0 , 3415 , 203, 128), // #812 + INST(Vblendmd , VexRvm_Lx , E(660F38,64,_,x,_,0,4,FV ), 0 , 111, 0 , 3424 , 204, 126), // #813 + INST(Vblendmpd , VexRvm_Lx , E(660F38,65,_,x,_,1,4,FV ), 0 , 112, 0 , 3433 , 205, 126), // #814 + INST(Vblendmps , VexRvm_Lx , E(660F38,65,_,x,_,0,4,FV ), 0 , 111, 0 , 3443 , 204, 126), // #815 + INST(Vblendmq , VexRvm_Lx , E(660F38,64,_,x,_,1,4,FV ), 0 , 112, 0 , 3453 , 205, 126), // #816 + INST(Vblendmw , VexRvm_Lx , E(660F38,66,_,x,_,1,4,FVM), 0 , 113, 0 , 3462 , 203, 128), // #817 + INST(Vblendpd , VexRvmi_Lx , V(660F3A,0D,_,x,I,_,_,_ ), 0 , 72 , 0 , 3471 , 206, 123), // #818 + INST(Vblendps , VexRvmi_Lx , V(660F3A,0C,_,x,I,_,_,_ ), 0 , 72 , 0 , 3480 , 206, 123), // #819 + INST(Vblendvpd , VexRvmr_Lx , V(660F3A,4B,_,x,0,_,_,_ ), 0 , 72 , 0 , 3489 , 207, 123), // #820 + INST(Vblendvps , VexRvmr_Lx , V(660F3A,4A,_,x,0,_,_,_ ), 0 , 72 , 0 , 3499 , 207, 123), // #821 + INST(Vbroadcastf128 , VexRm , V(660F38,1A,_,1,0,_,_,_ ), 0 , 114, 0 , 3509 , 208, 123), // #822 + INST(Vbroadcastf32x2 , VexRm_Lx , E(660F38,19,_,x,_,0,3,T2 ), 0 , 115, 0 , 3524 , 209, 129), // #823 + INST(Vbroadcastf32x4 , VexRm_Lx , E(660F38,1A,_,x,_,0,4,T4 ), 0 , 116, 0 , 3540 , 210, 66 ), // #824 + INST(Vbroadcastf32x8 , VexRm , E(660F38,1B,_,2,_,0,5,T8 ), 0 , 117, 0 , 3556 , 211, 64 ), // #825 + INST(Vbroadcastf64x2 , VexRm_Lx , E(660F38,1A,_,x,_,1,4,T2 ), 0 , 118, 0 , 3572 , 210, 129), // #826 + INST(Vbroadcastf64x4 , VexRm , E(660F38,1B,_,2,_,1,5,T4 ), 0 , 119, 0 , 3588 , 211, 66 ), // #827 + INST(Vbroadcasti128 , VexRm , V(660F38,5A,_,1,0,_,_,_ ), 0 , 114, 0 , 3604 , 208, 130), // #828 + INST(Vbroadcasti32x2 , VexRm_Lx , E(660F38,59,_,x,_,0,3,T2 ), 0 , 115, 0 , 3619 , 212, 129), // #829 + INST(Vbroadcasti32x4 , VexRm_Lx , E(660F38,5A,_,x,_,0,4,T4 ), 0 , 116, 0 , 3635 , 210, 126), // #830 + INST(Vbroadcasti32x8 , VexRm , E(660F38,5B,_,2,_,0,5,T8 ), 0 , 117, 0 , 3651 , 211, 64 ), // #831 + INST(Vbroadcasti64x2 , VexRm_Lx , E(660F38,5A,_,x,_,1,4,T2 ), 0 , 118, 0 , 3667 , 210, 129), // #832 + INST(Vbroadcasti64x4 , VexRm , E(660F38,5B,_,2,_,1,5,T4 ), 0 , 119, 0 , 3683 , 211, 66 ), // #833 + INST(Vbroadcastsd , VexRm_Lx , V(660F38,19,_,x,0,1,3,T1S), 0 , 120, 0 , 3699 , 213, 131), // #834 + INST(Vbroadcastss , VexRm_Lx , V(660F38,18,_,x,0,0,2,T1S), 0 , 121, 0 , 3712 , 214, 131), // #835 + INST(Vcmppd , VexRvmi_Lx , V(660F00,C2,_,x,I,1,4,FV ), 0 , 102, 0 , 3725 , 215, 121), // #836 + INST(Vcmpps , VexRvmi_Lx , V(000F00,C2,_,x,I,0,4,FV ), 0 , 103, 0 , 3732 , 216, 121), // #837 + INST(Vcmpsd , VexRvmi , V(F20F00,C2,_,I,I,1,3,T1S), 0 , 104, 0 , 3739 , 217, 122), // #838 + INST(Vcmpss , VexRvmi , V(F30F00,C2,_,I,I,0,2,T1S), 0 , 105, 0 , 3746 , 218, 122), // #839 + INST(Vcomisd , VexRm , V(660F00,2F,_,I,I,1,3,T1S), 0 , 122, 0 , 3753 , 219, 132), // #840 + INST(Vcomiss , VexRm , V(000F00,2F,_,I,I,0,2,T1S), 0 , 123, 0 , 3761 , 220, 132), // #841 + INST(Vcompresspd , VexMr_Lx , E(660F38,8A,_,x,_,1,3,T1S), 0 , 124, 0 , 3769 , 221, 126), // #842 + INST(Vcompressps , VexMr_Lx , E(660F38,8A,_,x,_,0,2,T1S), 0 , 125, 0 , 3781 , 221, 126), // #843 + INST(Vcvtdq2pd , VexRm_Lx , V(F30F00,E6,_,x,I,0,3,HV ), 0 , 126, 0 , 3793 , 222, 121), // #844 + INST(Vcvtdq2ps , VexRm_Lx , V(000F00,5B,_,x,I,0,4,FV ), 0 , 103, 0 , 3803 , 223, 121), // #845 + INST(Vcvtne2ps2bf16 , VexRvm , E(F20F38,72,_,_,_,0,_,_ ), 0 , 127, 0 , 3813 , 204, 133), // #846 + INST(Vcvtneps2bf16 , VexRm , E(F30F38,72,_,_,_,0,_,_ ), 0 , 128, 0 , 3828 , 224, 133), // #847 + INST(Vcvtpd2dq , VexRm_Lx , V(F20F00,E6,_,x,I,1,4,FV ), 0 , 129, 0 , 3842 , 225, 121), // #848 + INST(Vcvtpd2ps , VexRm_Lx , V(660F00,5A,_,x,I,1,4,FV ), 0 , 102, 0 , 3852 , 225, 121), // #849 + INST(Vcvtpd2qq , VexRm_Lx , E(660F00,7B,_,x,_,1,4,FV ), 0 , 130, 0 , 3862 , 226, 129), // #850 + INST(Vcvtpd2udq , VexRm_Lx , E(000F00,79,_,x,_,1,4,FV ), 0 , 131, 0 , 3872 , 227, 126), // #851 + INST(Vcvtpd2uqq , VexRm_Lx , E(660F00,79,_,x,_,1,4,FV ), 0 , 130, 0 , 3883 , 226, 129), // #852 + INST(Vcvtph2ps , VexRm_Lx , V(660F38,13,_,x,0,0,3,HVM), 0 , 132, 0 , 3894 , 228, 134), // #853 + INST(Vcvtps2dq , VexRm_Lx , V(660F00,5B,_,x,I,0,4,FV ), 0 , 133, 0 , 3904 , 223, 121), // #854 + INST(Vcvtps2pd , VexRm_Lx , V(000F00,5A,_,x,I,0,4,HV ), 0 , 134, 0 , 3914 , 229, 121), // #855 + INST(Vcvtps2ph , VexMri_Lx , V(660F3A,1D,_,x,0,0,3,HVM), 0 , 135, 0 , 3924 , 230, 134), // #856 + INST(Vcvtps2qq , VexRm_Lx , E(660F00,7B,_,x,_,0,3,HV ), 0 , 136, 0 , 3934 , 231, 129), // #857 + INST(Vcvtps2udq , VexRm_Lx , E(000F00,79,_,x,_,0,4,FV ), 0 , 137, 0 , 3944 , 232, 126), // #858 + INST(Vcvtps2uqq , VexRm_Lx , E(660F00,79,_,x,_,0,3,HV ), 0 , 136, 0 , 3955 , 231, 129), // #859 + INST(Vcvtqq2pd , VexRm_Lx , E(F30F00,E6,_,x,_,1,4,FV ), 0 , 138, 0 , 3966 , 226, 129), // #860 + INST(Vcvtqq2ps , VexRm_Lx , E(000F00,5B,_,x,_,1,4,FV ), 0 , 131, 0 , 3976 , 227, 129), // #861 + INST(Vcvtsd2si , VexRm_Wx , V(F20F00,2D,_,I,x,x,3,T1F), 0 , 139, 0 , 3986 , 233, 122), // #862 + INST(Vcvtsd2ss , VexRvm , V(F20F00,5A,_,I,I,1,3,T1S), 0 , 104, 0 , 3996 , 191, 122), // #863 + INST(Vcvtsd2usi , VexRm_Wx , E(F20F00,79,_,I,_,x,3,T1F), 0 , 140, 0 , 4006 , 234, 66 ), // #864 + INST(Vcvtsi2sd , VexRvm_Wx , V(F20F00,2A,_,I,x,x,2,T1W), 0 , 141, 0 , 4017 , 235, 122), // #865 + INST(Vcvtsi2ss , VexRvm_Wx , V(F30F00,2A,_,I,x,x,2,T1W), 0 , 142, 0 , 4027 , 235, 122), // #866 + INST(Vcvtss2sd , VexRvm , V(F30F00,5A,_,I,I,0,2,T1S), 0 , 105, 0 , 4037 , 236, 122), // #867 + INST(Vcvtss2si , VexRm_Wx , V(F30F00,2D,_,I,x,x,2,T1F), 0 , 143, 0 , 4047 , 237, 122), // #868 + INST(Vcvtss2usi , VexRm_Wx , E(F30F00,79,_,I,_,x,2,T1F), 0 , 144, 0 , 4057 , 238, 66 ), // #869 + INST(Vcvttpd2dq , VexRm_Lx , V(660F00,E6,_,x,I,1,4,FV ), 0 , 102, 0 , 4068 , 239, 121), // #870 + INST(Vcvttpd2qq , VexRm_Lx , E(660F00,7A,_,x,_,1,4,FV ), 0 , 130, 0 , 4079 , 240, 126), // #871 + INST(Vcvttpd2udq , VexRm_Lx , E(000F00,78,_,x,_,1,4,FV ), 0 , 131, 0 , 4090 , 241, 126), // #872 + INST(Vcvttpd2uqq , VexRm_Lx , E(660F00,78,_,x,_,1,4,FV ), 0 , 130, 0 , 4102 , 240, 129), // #873 + INST(Vcvttps2dq , VexRm_Lx , V(F30F00,5B,_,x,I,0,4,FV ), 0 , 145, 0 , 4114 , 242, 121), // #874 + INST(Vcvttps2qq , VexRm_Lx , E(660F00,7A,_,x,_,0,3,HV ), 0 , 136, 0 , 4125 , 243, 129), // #875 + INST(Vcvttps2udq , VexRm_Lx , E(000F00,78,_,x,_,0,4,FV ), 0 , 137, 0 , 4136 , 244, 126), // #876 + INST(Vcvttps2uqq , VexRm_Lx , E(660F00,78,_,x,_,0,3,HV ), 0 , 136, 0 , 4148 , 243, 129), // #877 + INST(Vcvttsd2si , VexRm_Wx , V(F20F00,2C,_,I,x,x,3,T1F), 0 , 139, 0 , 4160 , 245, 122), // #878 + INST(Vcvttsd2usi , VexRm_Wx , E(F20F00,78,_,I,_,x,3,T1F), 0 , 140, 0 , 4171 , 246, 66 ), // #879 + INST(Vcvttss2si , VexRm_Wx , V(F30F00,2C,_,I,x,x,2,T1F), 0 , 143, 0 , 4183 , 247, 122), // #880 + INST(Vcvttss2usi , VexRm_Wx , E(F30F00,78,_,I,_,x,2,T1F), 0 , 144, 0 , 4194 , 248, 66 ), // #881 + INST(Vcvtudq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,0,3,HV ), 0 , 146, 0 , 4206 , 249, 126), // #882 + INST(Vcvtudq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,0,4,FV ), 0 , 147, 0 , 4217 , 232, 126), // #883 + INST(Vcvtuqq2pd , VexRm_Lx , E(F30F00,7A,_,x,_,1,4,FV ), 0 , 138, 0 , 4228 , 226, 129), // #884 + INST(Vcvtuqq2ps , VexRm_Lx , E(F20F00,7A,_,x,_,1,4,FV ), 0 , 148, 0 , 4239 , 227, 129), // #885 + INST(Vcvtusi2sd , VexRvm_Wx , E(F20F00,7B,_,I,_,x,2,T1W), 0 , 149, 0 , 4250 , 250, 66 ), // #886 + INST(Vcvtusi2ss , VexRvm_Wx , E(F30F00,7B,_,I,_,x,2,T1W), 0 , 150, 0 , 4261 , 250, 66 ), // #887 + INST(Vdbpsadbw , VexRvmi_Lx , E(660F3A,42,_,x,_,0,4,FVM), 0 , 151, 0 , 4272 , 251, 128), // #888 + INST(Vdivpd , VexRvm_Lx , V(660F00,5E,_,x,I,1,4,FV ), 0 , 102, 0 , 4282 , 189, 121), // #889 + INST(Vdivps , VexRvm_Lx , V(000F00,5E,_,x,I,0,4,FV ), 0 , 103, 0 , 4289 , 190, 121), // #890 + INST(Vdivsd , VexRvm , V(F20F00,5E,_,I,I,1,3,T1S), 0 , 104, 0 , 4296 , 191, 122), // #891 + INST(Vdivss , VexRvm , V(F30F00,5E,_,I,I,0,2,T1S), 0 , 105, 0 , 4303 , 192, 122), // #892 + INST(Vdpbf16ps , VexRvm , E(F30F38,52,_,_,_,0,_,_ ), 0 , 128, 0 , 4310 , 204, 133), // #893 + INST(Vdppd , VexRvmi_Lx , V(660F3A,41,_,x,I,_,_,_ ), 0 , 72 , 0 , 4320 , 252, 123), // #894 + INST(Vdpps , VexRvmi_Lx , V(660F3A,40,_,x,I,_,_,_ ), 0 , 72 , 0 , 4326 , 206, 123), // #895 + INST(Verr , X86M_NoSize , O(000F00,00,4,_,_,_,_,_ ), 0 , 97 , 0 , 4332 , 101, 10 ), // #896 + INST(Verw , X86M_NoSize , O(000F00,00,5,_,_,_,_,_ ), 0 , 75 , 0 , 4337 , 101, 10 ), // #897 + INST(Vexp2pd , VexRm , E(660F38,C8,_,2,_,1,4,FV ), 0 , 152, 0 , 4342 , 253, 135), // #898 + INST(Vexp2ps , VexRm , E(660F38,C8,_,2,_,0,4,FV ), 0 , 153, 0 , 4350 , 254, 135), // #899 + INST(Vexpandpd , VexRm_Lx , E(660F38,88,_,x,_,1,3,T1S), 0 , 124, 0 , 4358 , 255, 126), // #900 + INST(Vexpandps , VexRm_Lx , E(660F38,88,_,x,_,0,2,T1S), 0 , 125, 0 , 4368 , 255, 126), // #901 + INST(Vextractf128 , VexMri , V(660F3A,19,_,1,0,_,_,_ ), 0 , 154, 0 , 4378 , 256, 123), // #902 + INST(Vextractf32x4 , VexMri_Lx , E(660F3A,19,_,x,_,0,4,T4 ), 0 , 155, 0 , 4391 , 257, 126), // #903 + INST(Vextractf32x8 , VexMri , E(660F3A,1B,_,2,_,0,5,T8 ), 0 , 156, 0 , 4405 , 258, 64 ), // #904 + INST(Vextractf64x2 , VexMri_Lx , E(660F3A,19,_,x,_,1,4,T2 ), 0 , 157, 0 , 4419 , 257, 129), // #905 + INST(Vextractf64x4 , VexMri , E(660F3A,1B,_,2,_,1,5,T4 ), 0 , 158, 0 , 4433 , 258, 66 ), // #906 + INST(Vextracti128 , VexMri , V(660F3A,39,_,1,0,_,_,_ ), 0 , 154, 0 , 4447 , 256, 130), // #907 + INST(Vextracti32x4 , VexMri_Lx , E(660F3A,39,_,x,_,0,4,T4 ), 0 , 155, 0 , 4460 , 257, 126), // #908 + INST(Vextracti32x8 , VexMri , E(660F3A,3B,_,2,_,0,5,T8 ), 0 , 156, 0 , 4474 , 258, 64 ), // #909 + INST(Vextracti64x2 , VexMri_Lx , E(660F3A,39,_,x,_,1,4,T2 ), 0 , 157, 0 , 4488 , 257, 129), // #910 + INST(Vextracti64x4 , VexMri , E(660F3A,3B,_,2,_,1,5,T4 ), 0 , 158, 0 , 4502 , 258, 66 ), // #911 + INST(Vextractps , VexMri , V(660F3A,17,_,0,I,I,2,T1S), 0 , 159, 0 , 4516 , 259, 122), // #912 + INST(Vfixupimmpd , VexRvmi_Lx , E(660F3A,54,_,x,_,1,4,FV ), 0 , 109, 0 , 4527 , 260, 126), // #913 + INST(Vfixupimmps , VexRvmi_Lx , E(660F3A,54,_,x,_,0,4,FV ), 0 , 108, 0 , 4539 , 261, 126), // #914 + INST(Vfixupimmsd , VexRvmi , E(660F3A,55,_,I,_,1,3,T1S), 0 , 160, 0 , 4551 , 262, 66 ), // #915 + INST(Vfixupimmss , VexRvmi , E(660F3A,55,_,I,_,0,2,T1S), 0 , 161, 0 , 4563 , 263, 66 ), // #916 + INST(Vfmadd132pd , VexRvm_Lx , V(660F38,98,_,x,1,1,4,FV ), 0 , 162, 0 , 4575 , 189, 136), // #917 + INST(Vfmadd132ps , VexRvm_Lx , V(660F38,98,_,x,0,0,4,FV ), 0 , 163, 0 , 4587 , 190, 136), // #918 + INST(Vfmadd132sd , VexRvm , V(660F38,99,_,I,1,1,3,T1S), 0 , 164, 0 , 4599 , 191, 137), // #919 + INST(Vfmadd132ss , VexRvm , V(660F38,99,_,I,0,0,2,T1S), 0 , 121, 0 , 4611 , 192, 137), // #920 + INST(Vfmadd213pd , VexRvm_Lx , V(660F38,A8,_,x,1,1,4,FV ), 0 , 162, 0 , 4623 , 189, 136), // #921 + INST(Vfmadd213ps , VexRvm_Lx , V(660F38,A8,_,x,0,0,4,FV ), 0 , 163, 0 , 4635 , 190, 136), // #922 + INST(Vfmadd213sd , VexRvm , V(660F38,A9,_,I,1,1,3,T1S), 0 , 164, 0 , 4647 , 191, 137), // #923 + INST(Vfmadd213ss , VexRvm , V(660F38,A9,_,I,0,0,2,T1S), 0 , 121, 0 , 4659 , 192, 137), // #924 + INST(Vfmadd231pd , VexRvm_Lx , V(660F38,B8,_,x,1,1,4,FV ), 0 , 162, 0 , 4671 , 189, 136), // #925 + INST(Vfmadd231ps , VexRvm_Lx , V(660F38,B8,_,x,0,0,4,FV ), 0 , 163, 0 , 4683 , 190, 136), // #926 + INST(Vfmadd231sd , VexRvm , V(660F38,B9,_,I,1,1,3,T1S), 0 , 164, 0 , 4695 , 191, 137), // #927 + INST(Vfmadd231ss , VexRvm , V(660F38,B9,_,I,0,0,2,T1S), 0 , 121, 0 , 4707 , 192, 137), // #928 + INST(Vfmaddpd , Fma4_Lx , V(660F3A,69,_,x,x,_,_,_ ), 0 , 72 , 0 , 4719 , 264, 138), // #929 + INST(Vfmaddps , Fma4_Lx , V(660F3A,68,_,x,x,_,_,_ ), 0 , 72 , 0 , 4728 , 264, 138), // #930 + INST(Vfmaddsd , Fma4 , V(660F3A,6B,_,0,x,_,_,_ ), 0 , 72 , 0 , 4737 , 265, 138), // #931 + INST(Vfmaddss , Fma4 , V(660F3A,6A,_,0,x,_,_,_ ), 0 , 72 , 0 , 4746 , 266, 138), // #932 + INST(Vfmaddsub132pd , VexRvm_Lx , V(660F38,96,_,x,1,1,4,FV ), 0 , 162, 0 , 4755 , 189, 136), // #933 + INST(Vfmaddsub132ps , VexRvm_Lx , V(660F38,96,_,x,0,0,4,FV ), 0 , 163, 0 , 4770 , 190, 136), // #934 + INST(Vfmaddsub213pd , VexRvm_Lx , V(660F38,A6,_,x,1,1,4,FV ), 0 , 162, 0 , 4785 , 189, 136), // #935 + INST(Vfmaddsub213ps , VexRvm_Lx , V(660F38,A6,_,x,0,0,4,FV ), 0 , 163, 0 , 4800 , 190, 136), // #936 + INST(Vfmaddsub231pd , VexRvm_Lx , V(660F38,B6,_,x,1,1,4,FV ), 0 , 162, 0 , 4815 , 189, 136), // #937 + INST(Vfmaddsub231ps , VexRvm_Lx , V(660F38,B6,_,x,0,0,4,FV ), 0 , 163, 0 , 4830 , 190, 136), // #938 + INST(Vfmaddsubpd , Fma4_Lx , V(660F3A,5D,_,x,x,_,_,_ ), 0 , 72 , 0 , 4845 , 264, 138), // #939 + INST(Vfmaddsubps , Fma4_Lx , V(660F3A,5C,_,x,x,_,_,_ ), 0 , 72 , 0 , 4857 , 264, 138), // #940 + INST(Vfmsub132pd , VexRvm_Lx , V(660F38,9A,_,x,1,1,4,FV ), 0 , 162, 0 , 4869 , 189, 136), // #941 + INST(Vfmsub132ps , VexRvm_Lx , V(660F38,9A,_,x,0,0,4,FV ), 0 , 163, 0 , 4881 , 190, 136), // #942 + INST(Vfmsub132sd , VexRvm , V(660F38,9B,_,I,1,1,3,T1S), 0 , 164, 0 , 4893 , 191, 137), // #943 + INST(Vfmsub132ss , VexRvm , V(660F38,9B,_,I,0,0,2,T1S), 0 , 121, 0 , 4905 , 192, 137), // #944 + INST(Vfmsub213pd , VexRvm_Lx , V(660F38,AA,_,x,1,1,4,FV ), 0 , 162, 0 , 4917 , 189, 136), // #945 + INST(Vfmsub213ps , VexRvm_Lx , V(660F38,AA,_,x,0,0,4,FV ), 0 , 163, 0 , 4929 , 190, 136), // #946 + INST(Vfmsub213sd , VexRvm , V(660F38,AB,_,I,1,1,3,T1S), 0 , 164, 0 , 4941 , 191, 137), // #947 + INST(Vfmsub213ss , VexRvm , V(660F38,AB,_,I,0,0,2,T1S), 0 , 121, 0 , 4953 , 192, 137), // #948 + INST(Vfmsub231pd , VexRvm_Lx , V(660F38,BA,_,x,1,1,4,FV ), 0 , 162, 0 , 4965 , 189, 136), // #949 + INST(Vfmsub231ps , VexRvm_Lx , V(660F38,BA,_,x,0,0,4,FV ), 0 , 163, 0 , 4977 , 190, 136), // #950 + INST(Vfmsub231sd , VexRvm , V(660F38,BB,_,I,1,1,3,T1S), 0 , 164, 0 , 4989 , 191, 137), // #951 + INST(Vfmsub231ss , VexRvm , V(660F38,BB,_,I,0,0,2,T1S), 0 , 121, 0 , 5001 , 192, 137), // #952 + INST(Vfmsubadd132pd , VexRvm_Lx , V(660F38,97,_,x,1,1,4,FV ), 0 , 162, 0 , 5013 , 189, 136), // #953 + INST(Vfmsubadd132ps , VexRvm_Lx , V(660F38,97,_,x,0,0,4,FV ), 0 , 163, 0 , 5028 , 190, 136), // #954 + INST(Vfmsubadd213pd , VexRvm_Lx , V(660F38,A7,_,x,1,1,4,FV ), 0 , 162, 0 , 5043 , 189, 136), // #955 + INST(Vfmsubadd213ps , VexRvm_Lx , V(660F38,A7,_,x,0,0,4,FV ), 0 , 163, 0 , 5058 , 190, 136), // #956 + INST(Vfmsubadd231pd , VexRvm_Lx , V(660F38,B7,_,x,1,1,4,FV ), 0 , 162, 0 , 5073 , 189, 136), // #957 + INST(Vfmsubadd231ps , VexRvm_Lx , V(660F38,B7,_,x,0,0,4,FV ), 0 , 163, 0 , 5088 , 190, 136), // #958 + INST(Vfmsubaddpd , Fma4_Lx , V(660F3A,5F,_,x,x,_,_,_ ), 0 , 72 , 0 , 5103 , 264, 138), // #959 + INST(Vfmsubaddps , Fma4_Lx , V(660F3A,5E,_,x,x,_,_,_ ), 0 , 72 , 0 , 5115 , 264, 138), // #960 + INST(Vfmsubpd , Fma4_Lx , V(660F3A,6D,_,x,x,_,_,_ ), 0 , 72 , 0 , 5127 , 264, 138), // #961 + INST(Vfmsubps , Fma4_Lx , V(660F3A,6C,_,x,x,_,_,_ ), 0 , 72 , 0 , 5136 , 264, 138), // #962 + INST(Vfmsubsd , Fma4 , V(660F3A,6F,_,0,x,_,_,_ ), 0 , 72 , 0 , 5145 , 265, 138), // #963 + INST(Vfmsubss , Fma4 , V(660F3A,6E,_,0,x,_,_,_ ), 0 , 72 , 0 , 5154 , 266, 138), // #964 + INST(Vfnmadd132pd , VexRvm_Lx , V(660F38,9C,_,x,1,1,4,FV ), 0 , 162, 0 , 5163 , 189, 136), // #965 + INST(Vfnmadd132ps , VexRvm_Lx , V(660F38,9C,_,x,0,0,4,FV ), 0 , 163, 0 , 5176 , 190, 136), // #966 + INST(Vfnmadd132sd , VexRvm , V(660F38,9D,_,I,1,1,3,T1S), 0 , 164, 0 , 5189 , 191, 137), // #967 + INST(Vfnmadd132ss , VexRvm , V(660F38,9D,_,I,0,0,2,T1S), 0 , 121, 0 , 5202 , 192, 137), // #968 + INST(Vfnmadd213pd , VexRvm_Lx , V(660F38,AC,_,x,1,1,4,FV ), 0 , 162, 0 , 5215 , 189, 136), // #969 + INST(Vfnmadd213ps , VexRvm_Lx , V(660F38,AC,_,x,0,0,4,FV ), 0 , 163, 0 , 5228 , 190, 136), // #970 + INST(Vfnmadd213sd , VexRvm , V(660F38,AD,_,I,1,1,3,T1S), 0 , 164, 0 , 5241 , 191, 137), // #971 + INST(Vfnmadd213ss , VexRvm , V(660F38,AD,_,I,0,0,2,T1S), 0 , 121, 0 , 5254 , 192, 137), // #972 + INST(Vfnmadd231pd , VexRvm_Lx , V(660F38,BC,_,x,1,1,4,FV ), 0 , 162, 0 , 5267 , 189, 136), // #973 + INST(Vfnmadd231ps , VexRvm_Lx , V(660F38,BC,_,x,0,0,4,FV ), 0 , 163, 0 , 5280 , 190, 136), // #974 + INST(Vfnmadd231sd , VexRvm , V(660F38,BC,_,I,1,1,3,T1S), 0 , 164, 0 , 5293 , 191, 137), // #975 + INST(Vfnmadd231ss , VexRvm , V(660F38,BC,_,I,0,0,2,T1S), 0 , 121, 0 , 5306 , 192, 137), // #976 + INST(Vfnmaddpd , Fma4_Lx , V(660F3A,79,_,x,x,_,_,_ ), 0 , 72 , 0 , 5319 , 264, 138), // #977 + INST(Vfnmaddps , Fma4_Lx , V(660F3A,78,_,x,x,_,_,_ ), 0 , 72 , 0 , 5329 , 264, 138), // #978 + INST(Vfnmaddsd , Fma4 , V(660F3A,7B,_,0,x,_,_,_ ), 0 , 72 , 0 , 5339 , 265, 138), // #979 + INST(Vfnmaddss , Fma4 , V(660F3A,7A,_,0,x,_,_,_ ), 0 , 72 , 0 , 5349 , 266, 138), // #980 + INST(Vfnmsub132pd , VexRvm_Lx , V(660F38,9E,_,x,1,1,4,FV ), 0 , 162, 0 , 5359 , 189, 136), // #981 + INST(Vfnmsub132ps , VexRvm_Lx , V(660F38,9E,_,x,0,0,4,FV ), 0 , 163, 0 , 5372 , 190, 136), // #982 + INST(Vfnmsub132sd , VexRvm , V(660F38,9F,_,I,1,1,3,T1S), 0 , 164, 0 , 5385 , 191, 137), // #983 + INST(Vfnmsub132ss , VexRvm , V(660F38,9F,_,I,0,0,2,T1S), 0 , 121, 0 , 5398 , 192, 137), // #984 + INST(Vfnmsub213pd , VexRvm_Lx , V(660F38,AE,_,x,1,1,4,FV ), 0 , 162, 0 , 5411 , 189, 136), // #985 + INST(Vfnmsub213ps , VexRvm_Lx , V(660F38,AE,_,x,0,0,4,FV ), 0 , 163, 0 , 5424 , 190, 136), // #986 + INST(Vfnmsub213sd , VexRvm , V(660F38,AF,_,I,1,1,3,T1S), 0 , 164, 0 , 5437 , 191, 137), // #987 + INST(Vfnmsub213ss , VexRvm , V(660F38,AF,_,I,0,0,2,T1S), 0 , 121, 0 , 5450 , 192, 137), // #988 + INST(Vfnmsub231pd , VexRvm_Lx , V(660F38,BE,_,x,1,1,4,FV ), 0 , 162, 0 , 5463 , 189, 136), // #989 + INST(Vfnmsub231ps , VexRvm_Lx , V(660F38,BE,_,x,0,0,4,FV ), 0 , 163, 0 , 5476 , 190, 136), // #990 + INST(Vfnmsub231sd , VexRvm , V(660F38,BF,_,I,1,1,3,T1S), 0 , 164, 0 , 5489 , 191, 137), // #991 + INST(Vfnmsub231ss , VexRvm , V(660F38,BF,_,I,0,0,2,T1S), 0 , 121, 0 , 5502 , 192, 137), // #992 + INST(Vfnmsubpd , Fma4_Lx , V(660F3A,7D,_,x,x,_,_,_ ), 0 , 72 , 0 , 5515 , 264, 138), // #993 + INST(Vfnmsubps , Fma4_Lx , V(660F3A,7C,_,x,x,_,_,_ ), 0 , 72 , 0 , 5525 , 264, 138), // #994 + INST(Vfnmsubsd , Fma4 , V(660F3A,7F,_,0,x,_,_,_ ), 0 , 72 , 0 , 5535 , 265, 138), // #995 + INST(Vfnmsubss , Fma4 , V(660F3A,7E,_,0,x,_,_,_ ), 0 , 72 , 0 , 5545 , 266, 138), // #996 + INST(Vfpclasspd , VexRmi_Lx , E(660F3A,66,_,x,_,1,4,FV ), 0 , 109, 0 , 5555 , 267, 129), // #997 + INST(Vfpclassps , VexRmi_Lx , E(660F3A,66,_,x,_,0,4,FV ), 0 , 108, 0 , 5566 , 268, 129), // #998 + INST(Vfpclasssd , VexRmi_Lx , E(660F3A,67,_,I,_,1,3,T1S), 0 , 160, 0 , 5577 , 269, 64 ), // #999 + INST(Vfpclassss , VexRmi_Lx , E(660F3A,67,_,I,_,0,2,T1S), 0 , 161, 0 , 5588 , 270, 64 ), // #1000 + INST(Vfrczpd , VexRm_Lx , V(XOP_M9,81,_,x,0,_,_,_ ), 0 , 77 , 0 , 5599 , 271, 139), // #1001 + INST(Vfrczps , VexRm_Lx , V(XOP_M9,80,_,x,0,_,_,_ ), 0 , 77 , 0 , 5607 , 271, 139), // #1002 + INST(Vfrczsd , VexRm , V(XOP_M9,83,_,0,0,_,_,_ ), 0 , 77 , 0 , 5615 , 272, 139), // #1003 + INST(Vfrczss , VexRm , V(XOP_M9,82,_,0,0,_,_,_ ), 0 , 77 , 0 , 5623 , 273, 139), // #1004 + INST(Vgatherdpd , VexRmvRm_VM , V(660F38,92,_,x,1,_,_,_ ), V(660F38,92,_,x,_,1,3,T1S), 165, 79 , 5631 , 274, 140), // #1005 + INST(Vgatherdps , VexRmvRm_VM , V(660F38,92,_,x,0,_,_,_ ), V(660F38,92,_,x,_,0,2,T1S), 96 , 80 , 5642 , 275, 140), // #1006 + INST(Vgatherpf0dpd , VexM_VM , E(660F38,C6,1,2,_,1,3,T1S), 0 , 166, 0 , 5653 , 276, 141), // #1007 + INST(Vgatherpf0dps , VexM_VM , E(660F38,C6,1,2,_,0,2,T1S), 0 , 167, 0 , 5667 , 277, 141), // #1008 + INST(Vgatherpf0qpd , VexM_VM , E(660F38,C7,1,2,_,1,3,T1S), 0 , 166, 0 , 5681 , 278, 141), // #1009 + INST(Vgatherpf0qps , VexM_VM , E(660F38,C7,1,2,_,0,2,T1S), 0 , 167, 0 , 5695 , 278, 141), // #1010 + INST(Vgatherpf1dpd , VexM_VM , E(660F38,C6,2,2,_,1,3,T1S), 0 , 168, 0 , 5709 , 276, 141), // #1011 + INST(Vgatherpf1dps , VexM_VM , E(660F38,C6,2,2,_,0,2,T1S), 0 , 169, 0 , 5723 , 277, 141), // #1012 + INST(Vgatherpf1qpd , VexM_VM , E(660F38,C7,2,2,_,1,3,T1S), 0 , 168, 0 , 5737 , 278, 141), // #1013 + INST(Vgatherpf1qps , VexM_VM , E(660F38,C7,2,2,_,0,2,T1S), 0 , 169, 0 , 5751 , 278, 141), // #1014 + INST(Vgatherqpd , VexRmvRm_VM , V(660F38,93,_,x,1,_,_,_ ), V(660F38,93,_,x,_,1,3,T1S), 165, 81 , 5765 , 279, 140), // #1015 + INST(Vgatherqps , VexRmvRm_VM , V(660F38,93,_,x,0,_,_,_ ), V(660F38,93,_,x,_,0,2,T1S), 96 , 82 , 5776 , 280, 140), // #1016 + INST(Vgetexppd , VexRm_Lx , E(660F38,42,_,x,_,1,4,FV ), 0 , 112, 0 , 5787 , 240, 126), // #1017 + INST(Vgetexpps , VexRm_Lx , E(660F38,42,_,x,_,0,4,FV ), 0 , 111, 0 , 5797 , 244, 126), // #1018 + INST(Vgetexpsd , VexRvm , E(660F38,43,_,I,_,1,3,T1S), 0 , 124, 0 , 5807 , 281, 66 ), // #1019 + INST(Vgetexpss , VexRvm , E(660F38,43,_,I,_,0,2,T1S), 0 , 125, 0 , 5817 , 282, 66 ), // #1020 + INST(Vgetmantpd , VexRmi_Lx , E(660F3A,26,_,x,_,1,4,FV ), 0 , 109, 0 , 5827 , 283, 126), // #1021 + INST(Vgetmantps , VexRmi_Lx , E(660F3A,26,_,x,_,0,4,FV ), 0 , 108, 0 , 5838 , 284, 126), // #1022 + INST(Vgetmantsd , VexRvmi , E(660F3A,27,_,I,_,1,3,T1S), 0 , 160, 0 , 5849 , 262, 66 ), // #1023 + INST(Vgetmantss , VexRvmi , E(660F3A,27,_,I,_,0,2,T1S), 0 , 161, 0 , 5860 , 263, 66 ), // #1024 + INST(Vgf2p8affineinvqb, VexRvmi_Lx , V(660F3A,CF,_,x,1,1,4,FV ), 0 , 170, 0 , 5871 , 285, 142), // #1025 + INST(Vgf2p8affineqb , VexRvmi_Lx , V(660F3A,CE,_,x,1,1,4,FV ), 0 , 170, 0 , 5889 , 285, 142), // #1026 + INST(Vgf2p8mulb , VexRvm_Lx , V(660F38,CF,_,x,0,0,4,FV ), 0 , 163, 0 , 5904 , 286, 142), // #1027 + INST(Vhaddpd , VexRvm_Lx , V(660F00,7C,_,x,I,_,_,_ ), 0 , 68 , 0 , 5915 , 193, 123), // #1028 + INST(Vhaddps , VexRvm_Lx , V(F20F00,7C,_,x,I,_,_,_ ), 0 , 106, 0 , 5923 , 193, 123), // #1029 + INST(Vhsubpd , VexRvm_Lx , V(660F00,7D,_,x,I,_,_,_ ), 0 , 68 , 0 , 5931 , 193, 123), // #1030 + INST(Vhsubps , VexRvm_Lx , V(F20F00,7D,_,x,I,_,_,_ ), 0 , 106, 0 , 5939 , 193, 123), // #1031 + INST(Vinsertf128 , VexRvmi , V(660F3A,18,_,1,0,_,_,_ ), 0 , 154, 0 , 5947 , 287, 123), // #1032 + INST(Vinsertf32x4 , VexRvmi_Lx , E(660F3A,18,_,x,_,0,4,T4 ), 0 , 155, 0 , 5959 , 288, 126), // #1033 + INST(Vinsertf32x8 , VexRvmi , E(660F3A,1A,_,2,_,0,5,T8 ), 0 , 156, 0 , 5972 , 289, 64 ), // #1034 + INST(Vinsertf64x2 , VexRvmi_Lx , E(660F3A,18,_,x,_,1,4,T2 ), 0 , 157, 0 , 5985 , 288, 129), // #1035 + INST(Vinsertf64x4 , VexRvmi , E(660F3A,1A,_,2,_,1,5,T4 ), 0 , 158, 0 , 5998 , 289, 66 ), // #1036 + INST(Vinserti128 , VexRvmi , V(660F3A,38,_,1,0,_,_,_ ), 0 , 154, 0 , 6011 , 287, 130), // #1037 + INST(Vinserti32x4 , VexRvmi_Lx , E(660F3A,38,_,x,_,0,4,T4 ), 0 , 155, 0 , 6023 , 288, 126), // #1038 + INST(Vinserti32x8 , VexRvmi , E(660F3A,3A,_,2,_,0,5,T8 ), 0 , 156, 0 , 6036 , 289, 64 ), // #1039 + INST(Vinserti64x2 , VexRvmi_Lx , E(660F3A,38,_,x,_,1,4,T2 ), 0 , 157, 0 , 6049 , 288, 129), // #1040 + INST(Vinserti64x4 , VexRvmi , E(660F3A,3A,_,2,_,1,5,T4 ), 0 , 158, 0 , 6062 , 289, 66 ), // #1041 + INST(Vinsertps , VexRvmi , V(660F3A,21,_,0,I,0,2,T1S), 0 , 159, 0 , 6075 , 290, 122), // #1042 + INST(Vlddqu , VexRm_Lx , V(F20F00,F0,_,x,I,_,_,_ ), 0 , 106, 0 , 6085 , 291, 123), // #1043 + INST(Vldmxcsr , VexM , V(000F00,AE,2,0,I,_,_,_ ), 0 , 171, 0 , 6092 , 292, 123), // #1044 + INST(Vmaskmovdqu , VexRm_ZDI , V(660F00,F7,_,0,I,_,_,_ ), 0 , 68 , 0 , 6101 , 293, 123), // #1045 + INST(Vmaskmovpd , VexRvmMvr_Lx , V(660F38,2D,_,x,0,_,_,_ ), V(660F38,2F,_,x,0,_,_,_ ), 96 , 83 , 6113 , 294, 123), // #1046 + INST(Vmaskmovps , VexRvmMvr_Lx , V(660F38,2C,_,x,0,_,_,_ ), V(660F38,2E,_,x,0,_,_,_ ), 96 , 84 , 6124 , 294, 123), // #1047 + INST(Vmaxpd , VexRvm_Lx , V(660F00,5F,_,x,I,1,4,FV ), 0 , 102, 0 , 6135 , 295, 121), // #1048 + INST(Vmaxps , VexRvm_Lx , V(000F00,5F,_,x,I,0,4,FV ), 0 , 103, 0 , 6142 , 296, 121), // #1049 + INST(Vmaxsd , VexRvm , V(F20F00,5F,_,I,I,1,3,T1S), 0 , 104, 0 , 6149 , 297, 121), // #1050 + INST(Vmaxss , VexRvm , V(F30F00,5F,_,I,I,0,2,T1S), 0 , 105, 0 , 6156 , 236, 121), // #1051 + INST(Vmcall , X86Op , O(000F01,C1,_,_,_,_,_,_ ), 0 , 21 , 0 , 6163 , 30 , 56 ), // #1052 + INST(Vmclear , X86M_Only , O(660F00,C7,6,_,_,_,_,_ ), 0 , 25 , 0 , 6170 , 32 , 56 ), // #1053 + INST(Vmfunc , X86Op , O(000F01,D4,_,_,_,_,_,_ ), 0 , 21 , 0 , 6178 , 30 , 56 ), // #1054 + INST(Vminpd , VexRvm_Lx , V(660F00,5D,_,x,I,1,4,FV ), 0 , 102, 0 , 6185 , 295, 121), // #1055 + INST(Vminps , VexRvm_Lx , V(000F00,5D,_,x,I,0,4,FV ), 0 , 103, 0 , 6192 , 296, 121), // #1056 + INST(Vminsd , VexRvm , V(F20F00,5D,_,I,I,1,3,T1S), 0 , 104, 0 , 6199 , 297, 121), // #1057 + INST(Vminss , VexRvm , V(F30F00,5D,_,I,I,0,2,T1S), 0 , 105, 0 , 6206 , 236, 121), // #1058 + INST(Vmlaunch , X86Op , O(000F01,C2,_,_,_,_,_,_ ), 0 , 21 , 0 , 6213 , 30 , 56 ), // #1059 + INST(Vmload , X86Op_xAX , O(000F01,DA,_,_,_,_,_,_ ), 0 , 21 , 0 , 6222 , 298, 22 ), // #1060 + INST(Vmmcall , X86Op , O(000F01,D9,_,_,_,_,_,_ ), 0 , 21 , 0 , 6229 , 30 , 22 ), // #1061 + INST(Vmovapd , VexRmMr_Lx , V(660F00,28,_,x,I,1,4,FVM), V(660F00,29,_,x,I,1,4,FVM), 172, 85 , 6237 , 299, 121), // #1062 + INST(Vmovaps , VexRmMr_Lx , V(000F00,28,_,x,I,0,4,FVM), V(000F00,29,_,x,I,0,4,FVM), 173, 86 , 6245 , 299, 121), // #1063 + INST(Vmovd , VexMovdMovq , V(660F00,6E,_,0,0,0,2,T1S), V(660F00,7E,_,0,0,0,2,T1S), 174, 87 , 6253 , 300, 122), // #1064 + INST(Vmovddup , VexRm_Lx , V(F20F00,12,_,x,I,1,3,DUP), 0 , 175, 0 , 6259 , 301, 121), // #1065 + INST(Vmovdqa , VexRmMr_Lx , V(660F00,6F,_,x,I,_,_,_ ), V(660F00,7F,_,x,I,_,_,_ ), 68 , 88 , 6268 , 302, 123), // #1066 + INST(Vmovdqa32 , VexRmMr_Lx , E(660F00,6F,_,x,_,0,4,FVM), E(660F00,7F,_,x,_,0,4,FVM), 176, 89 , 6276 , 303, 126), // #1067 + INST(Vmovdqa64 , VexRmMr_Lx , E(660F00,6F,_,x,_,1,4,FVM), E(660F00,7F,_,x,_,1,4,FVM), 177, 90 , 6286 , 303, 126), // #1068 + INST(Vmovdqu , VexRmMr_Lx , V(F30F00,6F,_,x,I,_,_,_ ), V(F30F00,7F,_,x,I,_,_,_ ), 178, 91 , 6296 , 302, 123), // #1069 + INST(Vmovdqu16 , VexRmMr_Lx , E(F20F00,6F,_,x,_,1,4,FVM), E(F20F00,7F,_,x,_,1,4,FVM), 179, 92 , 6304 , 303, 128), // #1070 + INST(Vmovdqu32 , VexRmMr_Lx , E(F30F00,6F,_,x,_,0,4,FVM), E(F30F00,7F,_,x,_,0,4,FVM), 180, 93 , 6314 , 303, 126), // #1071 + INST(Vmovdqu64 , VexRmMr_Lx , E(F30F00,6F,_,x,_,1,4,FVM), E(F30F00,7F,_,x,_,1,4,FVM), 181, 94 , 6324 , 303, 126), // #1072 + INST(Vmovdqu8 , VexRmMr_Lx , E(F20F00,6F,_,x,_,0,4,FVM), E(F20F00,7F,_,x,_,0,4,FVM), 182, 95 , 6334 , 303, 128), // #1073 + INST(Vmovhlps , VexRvm , V(000F00,12,_,0,I,0,_,_ ), 0 , 71 , 0 , 6343 , 304, 122), // #1074 + INST(Vmovhpd , VexRvmMr , V(660F00,16,_,0,I,1,3,T1S), V(660F00,17,_,0,I,1,3,T1S), 122, 96 , 6352 , 305, 122), // #1075 + INST(Vmovhps , VexRvmMr , V(000F00,16,_,0,I,0,3,T2 ), V(000F00,17,_,0,I,0,3,T2 ), 183, 97 , 6360 , 305, 122), // #1076 + INST(Vmovlhps , VexRvm , V(000F00,16,_,0,I,0,_,_ ), 0 , 71 , 0 , 6368 , 304, 122), // #1077 + INST(Vmovlpd , VexRvmMr , V(660F00,12,_,0,I,1,3,T1S), V(660F00,13,_,0,I,1,3,T1S), 122, 98 , 6377 , 305, 122), // #1078 + INST(Vmovlps , VexRvmMr , V(000F00,12,_,0,I,0,3,T2 ), V(000F00,13,_,0,I,0,3,T2 ), 183, 99 , 6385 , 305, 122), // #1079 + INST(Vmovmskpd , VexRm_Lx , V(660F00,50,_,x,I,_,_,_ ), 0 , 68 , 0 , 6393 , 306, 123), // #1080 + INST(Vmovmskps , VexRm_Lx , V(000F00,50,_,x,I,_,_,_ ), 0 , 71 , 0 , 6403 , 306, 123), // #1081 + INST(Vmovntdq , VexMr_Lx , V(660F00,E7,_,x,I,0,4,FVM), 0 , 184, 0 , 6413 , 307, 121), // #1082 + INST(Vmovntdqa , VexRm_Lx , V(660F38,2A,_,x,I,0,4,FVM), 0 , 107, 0 , 6422 , 308, 131), // #1083 + INST(Vmovntpd , VexMr_Lx , V(660F00,2B,_,x,I,1,4,FVM), 0 , 172, 0 , 6432 , 307, 121), // #1084 + INST(Vmovntps , VexMr_Lx , V(000F00,2B,_,x,I,0,4,FVM), 0 , 173, 0 , 6441 , 307, 121), // #1085 + INST(Vmovq , VexMovdMovq , V(660F00,6E,_,0,I,1,3,T1S), V(660F00,7E,_,0,I,1,3,T1S), 122, 100, 6450 , 309, 122), // #1086 + INST(Vmovsd , VexMovssMovsd , V(F20F00,10,_,I,I,1,3,T1S), V(F20F00,11,_,I,I,1,3,T1S), 104, 101, 6456 , 310, 122), // #1087 + INST(Vmovshdup , VexRm_Lx , V(F30F00,16,_,x,I,0,4,FVM), 0 , 185, 0 , 6463 , 311, 121), // #1088 + INST(Vmovsldup , VexRm_Lx , V(F30F00,12,_,x,I,0,4,FVM), 0 , 185, 0 , 6473 , 311, 121), // #1089 + INST(Vmovss , VexMovssMovsd , V(F30F00,10,_,I,I,0,2,T1S), V(F30F00,11,_,I,I,0,2,T1S), 105, 102, 6483 , 312, 122), // #1090 + INST(Vmovupd , VexRmMr_Lx , V(660F00,10,_,x,I,1,4,FVM), V(660F00,11,_,x,I,1,4,FVM), 172, 103, 6490 , 299, 121), // #1091 + INST(Vmovups , VexRmMr_Lx , V(000F00,10,_,x,I,0,4,FVM), V(000F00,11,_,x,I,0,4,FVM), 173, 104, 6498 , 299, 121), // #1092 + INST(Vmpsadbw , VexRvmi_Lx , V(660F3A,42,_,x,I,_,_,_ ), 0 , 72 , 0 , 6506 , 206, 143), // #1093 + INST(Vmptrld , X86M_Only , O(000F00,C7,6,_,_,_,_,_ ), 0 , 78 , 0 , 6515 , 32 , 56 ), // #1094 + INST(Vmptrst , X86M_Only , O(000F00,C7,7,_,_,_,_,_ ), 0 , 22 , 0 , 6523 , 32 , 56 ), // #1095 + INST(Vmread , X86Mr_NoSize , O(000F00,78,_,_,_,_,_,_ ), 0 , 4 , 0 , 6531 , 313, 56 ), // #1096 + INST(Vmresume , X86Op , O(000F01,C3,_,_,_,_,_,_ ), 0 , 21 , 0 , 6538 , 30 , 56 ), // #1097 + INST(Vmrun , X86Op_xAX , O(000F01,D8,_,_,_,_,_,_ ), 0 , 21 , 0 , 6547 , 298, 22 ), // #1098 + INST(Vmsave , X86Op_xAX , O(000F01,DB,_,_,_,_,_,_ ), 0 , 21 , 0 , 6553 , 298, 22 ), // #1099 + INST(Vmulpd , VexRvm_Lx , V(660F00,59,_,x,I,1,4,FV ), 0 , 102, 0 , 6560 , 189, 121), // #1100 + INST(Vmulps , VexRvm_Lx , V(000F00,59,_,x,I,0,4,FV ), 0 , 103, 0 , 6567 , 190, 121), // #1101 + INST(Vmulsd , VexRvm_Lx , V(F20F00,59,_,I,I,1,3,T1S), 0 , 104, 0 , 6574 , 191, 122), // #1102 + INST(Vmulss , VexRvm_Lx , V(F30F00,59,_,I,I,0,2,T1S), 0 , 105, 0 , 6581 , 192, 122), // #1103 + INST(Vmwrite , X86Rm_NoSize , O(000F00,79,_,_,_,_,_,_ ), 0 , 4 , 0 , 6588 , 314, 56 ), // #1104 + INST(Vmxon , X86M_Only , O(F30F00,C7,6,_,_,_,_,_ ), 0 , 24 , 0 , 6596 , 32 , 56 ), // #1105 + INST(Vorpd , VexRvm_Lx , V(660F00,56,_,x,I,1,4,FV ), 0 , 102, 0 , 6602 , 201, 127), // #1106 + INST(Vorps , VexRvm_Lx , V(000F00,56,_,x,I,0,4,FV ), 0 , 103, 0 , 6608 , 202, 127), // #1107 + INST(Vp2intersectd , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,0,4,FV ), 0 , 186, 0 , 6614 , 315, 144), // #1108 + INST(Vp2intersectq , VexRvm_Lx_2xK , E(F20F38,68,_,_,_,1,4,FV ), 0 , 187, 0 , 6628 , 316, 144), // #1109 + INST(Vp4dpwssd , VexRm_T1_4X , E(F20F38,52,_,2,_,0,2,T4X), 0 , 101, 0 , 6642 , 187, 145), // #1110 + INST(Vp4dpwssds , VexRm_T1_4X , E(F20F38,53,_,2,_,0,2,T4X), 0 , 101, 0 , 6652 , 187, 145), // #1111 + INST(Vpabsb , VexRm_Lx , V(660F38,1C,_,x,I,_,4,FVM), 0 , 107, 0 , 6663 , 311, 146), // #1112 + INST(Vpabsd , VexRm_Lx , V(660F38,1E,_,x,I,0,4,FV ), 0 , 163, 0 , 6670 , 311, 131), // #1113 + INST(Vpabsq , VexRm_Lx , E(660F38,1F,_,x,_,1,4,FV ), 0 , 112, 0 , 6677 , 255, 126), // #1114 + INST(Vpabsw , VexRm_Lx , V(660F38,1D,_,x,I,_,4,FVM), 0 , 107, 0 , 6684 , 311, 146), // #1115 + INST(Vpackssdw , VexRvm_Lx , V(660F00,6B,_,x,I,0,4,FV ), 0 , 133, 0 , 6691 , 200, 146), // #1116 + INST(Vpacksswb , VexRvm_Lx , V(660F00,63,_,x,I,I,4,FVM), 0 , 184, 0 , 6701 , 286, 146), // #1117 + INST(Vpackusdw , VexRvm_Lx , V(660F38,2B,_,x,I,0,4,FV ), 0 , 163, 0 , 6711 , 200, 146), // #1118 + INST(Vpackuswb , VexRvm_Lx , V(660F00,67,_,x,I,I,4,FVM), 0 , 184, 0 , 6721 , 286, 146), // #1119 + INST(Vpaddb , VexRvm_Lx , V(660F00,FC,_,x,I,I,4,FVM), 0 , 184, 0 , 6731 , 286, 146), // #1120 + INST(Vpaddd , VexRvm_Lx , V(660F00,FE,_,x,I,0,4,FV ), 0 , 133, 0 , 6738 , 200, 131), // #1121 + INST(Vpaddq , VexRvm_Lx , V(660F00,D4,_,x,I,1,4,FV ), 0 , 102, 0 , 6745 , 199, 131), // #1122 + INST(Vpaddsb , VexRvm_Lx , V(660F00,EC,_,x,I,I,4,FVM), 0 , 184, 0 , 6752 , 286, 146), // #1123 + INST(Vpaddsw , VexRvm_Lx , V(660F00,ED,_,x,I,I,4,FVM), 0 , 184, 0 , 6760 , 286, 146), // #1124 + INST(Vpaddusb , VexRvm_Lx , V(660F00,DC,_,x,I,I,4,FVM), 0 , 184, 0 , 6768 , 286, 146), // #1125 + INST(Vpaddusw , VexRvm_Lx , V(660F00,DD,_,x,I,I,4,FVM), 0 , 184, 0 , 6777 , 286, 146), // #1126 + INST(Vpaddw , VexRvm_Lx , V(660F00,FD,_,x,I,I,4,FVM), 0 , 184, 0 , 6786 , 286, 146), // #1127 + INST(Vpalignr , VexRvmi_Lx , V(660F3A,0F,_,x,I,I,4,FVM), 0 , 188, 0 , 6793 , 285, 146), // #1128 + INST(Vpand , VexRvm_Lx , V(660F00,DB,_,x,I,_,_,_ ), 0 , 68 , 0 , 6802 , 317, 143), // #1129 + INST(Vpandd , VexRvm_Lx , E(660F00,DB,_,x,_,0,4,FV ), 0 , 189, 0 , 6808 , 318, 126), // #1130 + INST(Vpandn , VexRvm_Lx , V(660F00,DF,_,x,I,_,_,_ ), 0 , 68 , 0 , 6815 , 319, 143), // #1131 + INST(Vpandnd , VexRvm_Lx , E(660F00,DF,_,x,_,0,4,FV ), 0 , 189, 0 , 6822 , 320, 126), // #1132 + INST(Vpandnq , VexRvm_Lx , E(660F00,DF,_,x,_,1,4,FV ), 0 , 130, 0 , 6830 , 321, 126), // #1133 + INST(Vpandq , VexRvm_Lx , E(660F00,DB,_,x,_,1,4,FV ), 0 , 130, 0 , 6838 , 322, 126), // #1134 + INST(Vpavgb , VexRvm_Lx , V(660F00,E0,_,x,I,I,4,FVM), 0 , 184, 0 , 6845 , 286, 146), // #1135 + INST(Vpavgw , VexRvm_Lx , V(660F00,E3,_,x,I,I,4,FVM), 0 , 184, 0 , 6852 , 286, 146), // #1136 + INST(Vpblendd , VexRvmi_Lx , V(660F3A,02,_,x,0,_,_,_ ), 0 , 72 , 0 , 6859 , 206, 130), // #1137 + INST(Vpblendvb , VexRvmr , V(660F3A,4C,_,x,0,_,_,_ ), 0 , 72 , 0 , 6868 , 207, 143), // #1138 + INST(Vpblendw , VexRvmi_Lx , V(660F3A,0E,_,x,I,_,_,_ ), 0 , 72 , 0 , 6878 , 206, 143), // #1139 + INST(Vpbroadcastb , VexRm_Lx_Bcst , V(660F38,78,_,x,0,0,0,T1S), E(660F38,7A,_,x,0,0,0,T1S), 190, 105, 6887 , 323, 147), // #1140 + INST(Vpbroadcastd , VexRm_Lx_Bcst , V(660F38,58,_,x,0,0,2,T1S), E(660F38,7C,_,x,0,0,0,T1S), 121, 106, 6900 , 324, 140), // #1141 + INST(Vpbroadcastmb2d , VexRm_Lx , E(F30F38,3A,_,x,_,0,_,_ ), 0 , 128, 0 , 6913 , 325, 148), // #1142 + INST(Vpbroadcastmb2q , VexRm_Lx , E(F30F38,2A,_,x,_,1,_,_ ), 0 , 191, 0 , 6929 , 325, 148), // #1143 + INST(Vpbroadcastq , VexRm_Lx_Bcst , V(660F38,59,_,x,0,1,3,T1S), E(660F38,7C,_,x,0,1,0,T1S), 120, 107, 6945 , 326, 140), // #1144 + INST(Vpbroadcastw , VexRm_Lx_Bcst , V(660F38,79,_,x,0,0,1,T1S), E(660F38,7B,_,x,0,0,0,T1S), 192, 108, 6958 , 327, 147), // #1145 + INST(Vpclmulqdq , VexRvmi_Lx , V(660F3A,44,_,x,I,_,4,FVM), 0 , 188, 0 , 6971 , 328, 149), // #1146 + INST(Vpcmov , VexRvrmRvmr_Lx , V(XOP_M8,A2,_,x,x,_,_,_ ), 0 , 193, 0 , 6982 , 264, 139), // #1147 + INST(Vpcmpb , VexRvmi_Lx , E(660F3A,3F,_,x,_,0,4,FVM), 0 , 151, 0 , 6989 , 329, 128), // #1148 + INST(Vpcmpd , VexRvmi_Lx , E(660F3A,1F,_,x,_,0,4,FV ), 0 , 108, 0 , 6996 , 330, 126), // #1149 + INST(Vpcmpeqb , VexRvm_Lx , V(660F00,74,_,x,I,I,4,FV ), 0 , 133, 0 , 7003 , 331, 146), // #1150 + INST(Vpcmpeqd , VexRvm_Lx , V(660F00,76,_,x,I,0,4,FVM), 0 , 184, 0 , 7012 , 332, 131), // #1151 + INST(Vpcmpeqq , VexRvm_Lx , V(660F38,29,_,x,I,1,4,FVM), 0 , 194, 0 , 7021 , 333, 131), // #1152 + INST(Vpcmpeqw , VexRvm_Lx , V(660F00,75,_,x,I,I,4,FV ), 0 , 133, 0 , 7030 , 331, 146), // #1153 + INST(Vpcmpestri , VexRmi , V(660F3A,61,_,0,I,_,_,_ ), 0 , 72 , 0 , 7039 , 334, 150), // #1154 + INST(Vpcmpestrm , VexRmi , V(660F3A,60,_,0,I,_,_,_ ), 0 , 72 , 0 , 7050 , 335, 150), // #1155 + INST(Vpcmpgtb , VexRvm_Lx , V(660F00,64,_,x,I,I,4,FV ), 0 , 133, 0 , 7061 , 331, 146), // #1156 + INST(Vpcmpgtd , VexRvm_Lx , V(660F00,66,_,x,I,0,4,FVM), 0 , 184, 0 , 7070 , 332, 131), // #1157 + INST(Vpcmpgtq , VexRvm_Lx , V(660F38,37,_,x,I,1,4,FVM), 0 , 194, 0 , 7079 , 333, 131), // #1158 + INST(Vpcmpgtw , VexRvm_Lx , V(660F00,65,_,x,I,I,4,FV ), 0 , 133, 0 , 7088 , 331, 146), // #1159 + INST(Vpcmpistri , VexRmi , V(660F3A,63,_,0,I,_,_,_ ), 0 , 72 , 0 , 7097 , 336, 150), // #1160 + INST(Vpcmpistrm , VexRmi , V(660F3A,62,_,0,I,_,_,_ ), 0 , 72 , 0 , 7108 , 337, 150), // #1161 + INST(Vpcmpq , VexRvmi_Lx , E(660F3A,1F,_,x,_,1,4,FV ), 0 , 109, 0 , 7119 , 338, 126), // #1162 + INST(Vpcmpub , VexRvmi_Lx , E(660F3A,3E,_,x,_,0,4,FVM), 0 , 151, 0 , 7126 , 329, 128), // #1163 + INST(Vpcmpud , VexRvmi_Lx , E(660F3A,1E,_,x,_,0,4,FV ), 0 , 108, 0 , 7134 , 330, 126), // #1164 + INST(Vpcmpuq , VexRvmi_Lx , E(660F3A,1E,_,x,_,1,4,FV ), 0 , 109, 0 , 7142 , 338, 126), // #1165 + INST(Vpcmpuw , VexRvmi_Lx , E(660F3A,3E,_,x,_,1,4,FVM), 0 , 195, 0 , 7150 , 338, 128), // #1166 + INST(Vpcmpw , VexRvmi_Lx , E(660F3A,3F,_,x,_,1,4,FVM), 0 , 195, 0 , 7158 , 338, 128), // #1167 + INST(Vpcomb , VexRvmi , V(XOP_M8,CC,_,0,0,_,_,_ ), 0 , 193, 0 , 7165 , 252, 139), // #1168 + INST(Vpcomd , VexRvmi , V(XOP_M8,CE,_,0,0,_,_,_ ), 0 , 193, 0 , 7172 , 252, 139), // #1169 + INST(Vpcompressb , VexMr_Lx , E(660F38,63,_,x,_,0,0,T1S), 0 , 196, 0 , 7179 , 221, 151), // #1170 + INST(Vpcompressd , VexMr_Lx , E(660F38,8B,_,x,_,0,2,T1S), 0 , 125, 0 , 7191 , 221, 126), // #1171 + INST(Vpcompressq , VexMr_Lx , E(660F38,8B,_,x,_,1,3,T1S), 0 , 124, 0 , 7203 , 221, 126), // #1172 + INST(Vpcompressw , VexMr_Lx , E(660F38,63,_,x,_,1,1,T1S), 0 , 197, 0 , 7215 , 221, 151), // #1173 + INST(Vpcomq , VexRvmi , V(XOP_M8,CF,_,0,0,_,_,_ ), 0 , 193, 0 , 7227 , 252, 139), // #1174 + INST(Vpcomub , VexRvmi , V(XOP_M8,EC,_,0,0,_,_,_ ), 0 , 193, 0 , 7234 , 252, 139), // #1175 + INST(Vpcomud , VexRvmi , V(XOP_M8,EE,_,0,0,_,_,_ ), 0 , 193, 0 , 7242 , 252, 139), // #1176 + INST(Vpcomuq , VexRvmi , V(XOP_M8,EF,_,0,0,_,_,_ ), 0 , 193, 0 , 7250 , 252, 139), // #1177 + INST(Vpcomuw , VexRvmi , V(XOP_M8,ED,_,0,0,_,_,_ ), 0 , 193, 0 , 7258 , 252, 139), // #1178 + INST(Vpcomw , VexRvmi , V(XOP_M8,CD,_,0,0,_,_,_ ), 0 , 193, 0 , 7266 , 252, 139), // #1179 + INST(Vpconflictd , VexRm_Lx , E(660F38,C4,_,x,_,0,4,FV ), 0 , 111, 0 , 7273 , 339, 148), // #1180 + INST(Vpconflictq , VexRm_Lx , E(660F38,C4,_,x,_,1,4,FV ), 0 , 112, 0 , 7285 , 339, 148), // #1181 + INST(Vpdpbusd , VexRvm_Lx , V(660F38,50,_,x,_,0,4,FV ), 0 , 163, 0 , 7297 , 340, 152), // #1182 + INST(Vpdpbusds , VexRvm_Lx , V(660F38,51,_,x,_,0,4,FV ), 0 , 163, 0 , 7306 , 340, 152), // #1183 + INST(Vpdpwssd , VexRvm_Lx , V(660F38,52,_,x,_,0,4,FV ), 0 , 163, 0 , 7316 , 340, 152), // #1184 + INST(Vpdpwssds , VexRvm_Lx , V(660F38,53,_,x,_,0,4,FV ), 0 , 163, 0 , 7325 , 340, 152), // #1185 + INST(Vperm2f128 , VexRvmi , V(660F3A,06,_,1,0,_,_,_ ), 0 , 154, 0 , 7335 , 341, 123), // #1186 + INST(Vperm2i128 , VexRvmi , V(660F3A,46,_,1,0,_,_,_ ), 0 , 154, 0 , 7346 , 341, 130), // #1187 + INST(Vpermb , VexRvm_Lx , E(660F38,8D,_,x,_,0,4,FVM), 0 , 110, 0 , 7357 , 203, 153), // #1188 + INST(Vpermd , VexRvm_Lx , V(660F38,36,_,x,0,0,4,FV ), 0 , 163, 0 , 7364 , 342, 140), // #1189 + INST(Vpermi2b , VexRvm_Lx , E(660F38,75,_,x,_,0,4,FVM), 0 , 110, 0 , 7371 , 203, 153), // #1190 + INST(Vpermi2d , VexRvm_Lx , E(660F38,76,_,x,_,0,4,FV ), 0 , 111, 0 , 7380 , 204, 126), // #1191 + INST(Vpermi2pd , VexRvm_Lx , E(660F38,77,_,x,_,1,4,FV ), 0 , 112, 0 , 7389 , 205, 126), // #1192 + INST(Vpermi2ps , VexRvm_Lx , E(660F38,77,_,x,_,0,4,FV ), 0 , 111, 0 , 7399 , 204, 126), // #1193 + INST(Vpermi2q , VexRvm_Lx , E(660F38,76,_,x,_,1,4,FV ), 0 , 112, 0 , 7409 , 205, 126), // #1194 + INST(Vpermi2w , VexRvm_Lx , E(660F38,75,_,x,_,1,4,FVM), 0 , 113, 0 , 7418 , 203, 128), // #1195 + INST(Vpermil2pd , VexRvrmiRvmri_Lx , V(660F3A,49,_,x,x,_,_,_ ), 0 , 72 , 0 , 7427 , 343, 139), // #1196 + INST(Vpermil2ps , VexRvrmiRvmri_Lx , V(660F3A,48,_,x,x,_,_,_ ), 0 , 72 , 0 , 7438 , 343, 139), // #1197 + INST(Vpermilpd , VexRvmRmi_Lx , V(660F38,0D,_,x,0,1,4,FV ), V(660F3A,05,_,x,0,1,4,FV ), 198, 109, 7449 , 344, 121), // #1198 + INST(Vpermilps , VexRvmRmi_Lx , V(660F38,0C,_,x,0,0,4,FV ), V(660F3A,04,_,x,0,0,4,FV ), 163, 110, 7459 , 344, 121), // #1199 + INST(Vpermpd , VexRvmRmi_Lx , E(660F38,16,_,x,1,1,4,FV ), V(660F3A,01,_,x,1,1,4,FV ), 199, 111, 7469 , 345, 140), // #1200 + INST(Vpermps , VexRvm_Lx , V(660F38,16,_,x,0,0,4,FV ), 0 , 163, 0 , 7477 , 342, 140), // #1201 + INST(Vpermq , VexRvmRmi_Lx , V(660F38,36,_,x,_,1,4,FV ), V(660F3A,00,_,x,1,1,4,FV ), 198, 112, 7485 , 345, 140), // #1202 + INST(Vpermt2b , VexRvm_Lx , E(660F38,7D,_,x,_,0,4,FVM), 0 , 110, 0 , 7492 , 203, 153), // #1203 + INST(Vpermt2d , VexRvm_Lx , E(660F38,7E,_,x,_,0,4,FV ), 0 , 111, 0 , 7501 , 204, 126), // #1204 + INST(Vpermt2pd , VexRvm_Lx , E(660F38,7F,_,x,_,1,4,FV ), 0 , 112, 0 , 7510 , 205, 126), // #1205 + INST(Vpermt2ps , VexRvm_Lx , E(660F38,7F,_,x,_,0,4,FV ), 0 , 111, 0 , 7520 , 204, 126), // #1206 + INST(Vpermt2q , VexRvm_Lx , E(660F38,7E,_,x,_,1,4,FV ), 0 , 112, 0 , 7530 , 205, 126), // #1207 + INST(Vpermt2w , VexRvm_Lx , E(660F38,7D,_,x,_,1,4,FVM), 0 , 113, 0 , 7539 , 203, 128), // #1208 + INST(Vpermw , VexRvm_Lx , E(660F38,8D,_,x,_,1,4,FVM), 0 , 113, 0 , 7548 , 203, 128), // #1209 + INST(Vpexpandb , VexRm_Lx , E(660F38,62,_,x,_,0,0,T1S), 0 , 196, 0 , 7555 , 255, 151), // #1210 + INST(Vpexpandd , VexRm_Lx , E(660F38,89,_,x,_,0,2,T1S), 0 , 125, 0 , 7565 , 255, 126), // #1211 + INST(Vpexpandq , VexRm_Lx , E(660F38,89,_,x,_,1,3,T1S), 0 , 124, 0 , 7575 , 255, 126), // #1212 + INST(Vpexpandw , VexRm_Lx , E(660F38,62,_,x,_,1,1,T1S), 0 , 197, 0 , 7585 , 255, 151), // #1213 + INST(Vpextrb , VexMri , V(660F3A,14,_,0,0,I,0,T1S), 0 , 200, 0 , 7595 , 346, 154), // #1214 + INST(Vpextrd , VexMri , V(660F3A,16,_,0,0,0,2,T1S), 0 , 159, 0 , 7603 , 259, 155), // #1215 + INST(Vpextrq , VexMri , V(660F3A,16,_,0,1,1,3,T1S), 0 , 201, 0 , 7611 , 347, 155), // #1216 + INST(Vpextrw , VexMri , V(660F3A,15,_,0,0,I,1,T1S), 0 , 202, 0 , 7619 , 348, 154), // #1217 + INST(Vpgatherdd , VexRmvRm_VM , V(660F38,90,_,x,0,_,_,_ ), V(660F38,90,_,x,_,0,2,T1S), 96 , 113, 7627 , 275, 140), // #1218 + INST(Vpgatherdq , VexRmvRm_VM , V(660F38,90,_,x,1,_,_,_ ), V(660F38,90,_,x,_,1,3,T1S), 165, 114, 7638 , 274, 140), // #1219 + INST(Vpgatherqd , VexRmvRm_VM , V(660F38,91,_,x,0,_,_,_ ), V(660F38,91,_,x,_,0,2,T1S), 96 , 115, 7649 , 280, 140), // #1220 + INST(Vpgatherqq , VexRmvRm_VM , V(660F38,91,_,x,1,_,_,_ ), V(660F38,91,_,x,_,1,3,T1S), 165, 116, 7660 , 279, 140), // #1221 + INST(Vphaddbd , VexRm , V(XOP_M9,C2,_,0,0,_,_,_ ), 0 , 77 , 0 , 7671 , 195, 139), // #1222 + INST(Vphaddbq , VexRm , V(XOP_M9,C3,_,0,0,_,_,_ ), 0 , 77 , 0 , 7680 , 195, 139), // #1223 + INST(Vphaddbw , VexRm , V(XOP_M9,C1,_,0,0,_,_,_ ), 0 , 77 , 0 , 7689 , 195, 139), // #1224 + INST(Vphaddd , VexRvm_Lx , V(660F38,02,_,x,I,_,_,_ ), 0 , 96 , 0 , 7698 , 193, 143), // #1225 + INST(Vphadddq , VexRm , V(XOP_M9,CB,_,0,0,_,_,_ ), 0 , 77 , 0 , 7706 , 195, 139), // #1226 + INST(Vphaddsw , VexRvm_Lx , V(660F38,03,_,x,I,_,_,_ ), 0 , 96 , 0 , 7715 , 193, 143), // #1227 + INST(Vphaddubd , VexRm , V(XOP_M9,D2,_,0,0,_,_,_ ), 0 , 77 , 0 , 7724 , 195, 139), // #1228 + INST(Vphaddubq , VexRm , V(XOP_M9,D3,_,0,0,_,_,_ ), 0 , 77 , 0 , 7734 , 195, 139), // #1229 + INST(Vphaddubw , VexRm , V(XOP_M9,D1,_,0,0,_,_,_ ), 0 , 77 , 0 , 7744 , 195, 139), // #1230 + INST(Vphaddudq , VexRm , V(XOP_M9,DB,_,0,0,_,_,_ ), 0 , 77 , 0 , 7754 , 195, 139), // #1231 + INST(Vphadduwd , VexRm , V(XOP_M9,D6,_,0,0,_,_,_ ), 0 , 77 , 0 , 7764 , 195, 139), // #1232 + INST(Vphadduwq , VexRm , V(XOP_M9,D7,_,0,0,_,_,_ ), 0 , 77 , 0 , 7774 , 195, 139), // #1233 + INST(Vphaddw , VexRvm_Lx , V(660F38,01,_,x,I,_,_,_ ), 0 , 96 , 0 , 7784 , 193, 143), // #1234 + INST(Vphaddwd , VexRm , V(XOP_M9,C6,_,0,0,_,_,_ ), 0 , 77 , 0 , 7792 , 195, 139), // #1235 + INST(Vphaddwq , VexRm , V(XOP_M9,C7,_,0,0,_,_,_ ), 0 , 77 , 0 , 7801 , 195, 139), // #1236 + INST(Vphminposuw , VexRm , V(660F38,41,_,0,I,_,_,_ ), 0 , 96 , 0 , 7810 , 195, 123), // #1237 + INST(Vphsubbw , VexRm , V(XOP_M9,E1,_,0,0,_,_,_ ), 0 , 77 , 0 , 7822 , 195, 139), // #1238 + INST(Vphsubd , VexRvm_Lx , V(660F38,06,_,x,I,_,_,_ ), 0 , 96 , 0 , 7831 , 193, 143), // #1239 + INST(Vphsubdq , VexRm , V(XOP_M9,E3,_,0,0,_,_,_ ), 0 , 77 , 0 , 7839 , 195, 139), // #1240 + INST(Vphsubsw , VexRvm_Lx , V(660F38,07,_,x,I,_,_,_ ), 0 , 96 , 0 , 7848 , 193, 143), // #1241 + INST(Vphsubw , VexRvm_Lx , V(660F38,05,_,x,I,_,_,_ ), 0 , 96 , 0 , 7857 , 193, 143), // #1242 + INST(Vphsubwd , VexRm , V(XOP_M9,E2,_,0,0,_,_,_ ), 0 , 77 , 0 , 7865 , 195, 139), // #1243 + INST(Vpinsrb , VexRvmi , V(660F3A,20,_,0,0,I,0,T1S), 0 , 200, 0 , 7874 , 349, 154), // #1244 + INST(Vpinsrd , VexRvmi , V(660F3A,22,_,0,0,0,2,T1S), 0 , 159, 0 , 7882 , 350, 155), // #1245 + INST(Vpinsrq , VexRvmi , V(660F3A,22,_,0,1,1,3,T1S), 0 , 201, 0 , 7890 , 351, 155), // #1246 + INST(Vpinsrw , VexRvmi , V(660F00,C4,_,0,0,I,1,T1S), 0 , 203, 0 , 7898 , 352, 154), // #1247 + INST(Vplzcntd , VexRm_Lx , E(660F38,44,_,x,_,0,4,FV ), 0 , 111, 0 , 7906 , 339, 148), // #1248 + INST(Vplzcntq , VexRm_Lx , E(660F38,44,_,x,_,1,4,FV ), 0 , 112, 0 , 7915 , 353, 148), // #1249 + INST(Vpmacsdd , VexRvmr , V(XOP_M8,9E,_,0,0,_,_,_ ), 0 , 193, 0 , 7924 , 354, 139), // #1250 + INST(Vpmacsdqh , VexRvmr , V(XOP_M8,9F,_,0,0,_,_,_ ), 0 , 193, 0 , 7933 , 354, 139), // #1251 + INST(Vpmacsdql , VexRvmr , V(XOP_M8,97,_,0,0,_,_,_ ), 0 , 193, 0 , 7943 , 354, 139), // #1252 + INST(Vpmacssdd , VexRvmr , V(XOP_M8,8E,_,0,0,_,_,_ ), 0 , 193, 0 , 7953 , 354, 139), // #1253 + INST(Vpmacssdqh , VexRvmr , V(XOP_M8,8F,_,0,0,_,_,_ ), 0 , 193, 0 , 7963 , 354, 139), // #1254 + INST(Vpmacssdql , VexRvmr , V(XOP_M8,87,_,0,0,_,_,_ ), 0 , 193, 0 , 7974 , 354, 139), // #1255 + INST(Vpmacsswd , VexRvmr , V(XOP_M8,86,_,0,0,_,_,_ ), 0 , 193, 0 , 7985 , 354, 139), // #1256 + INST(Vpmacssww , VexRvmr , V(XOP_M8,85,_,0,0,_,_,_ ), 0 , 193, 0 , 7995 , 354, 139), // #1257 + INST(Vpmacswd , VexRvmr , V(XOP_M8,96,_,0,0,_,_,_ ), 0 , 193, 0 , 8005 , 354, 139), // #1258 + INST(Vpmacsww , VexRvmr , V(XOP_M8,95,_,0,0,_,_,_ ), 0 , 193, 0 , 8014 , 354, 139), // #1259 + INST(Vpmadcsswd , VexRvmr , V(XOP_M8,A6,_,0,0,_,_,_ ), 0 , 193, 0 , 8023 , 354, 139), // #1260 + INST(Vpmadcswd , VexRvmr , V(XOP_M8,B6,_,0,0,_,_,_ ), 0 , 193, 0 , 8034 , 354, 139), // #1261 + INST(Vpmadd52huq , VexRvm_Lx , E(660F38,B5,_,x,_,1,4,FV ), 0 , 112, 0 , 8044 , 205, 156), // #1262 + INST(Vpmadd52luq , VexRvm_Lx , E(660F38,B4,_,x,_,1,4,FV ), 0 , 112, 0 , 8056 , 205, 156), // #1263 + INST(Vpmaddubsw , VexRvm_Lx , V(660F38,04,_,x,I,I,4,FVM), 0 , 107, 0 , 8068 , 286, 146), // #1264 + INST(Vpmaddwd , VexRvm_Lx , V(660F00,F5,_,x,I,I,4,FVM), 0 , 184, 0 , 8079 , 286, 146), // #1265 + INST(Vpmaskmovd , VexRvmMvr_Lx , V(660F38,8C,_,x,0,_,_,_ ), V(660F38,8E,_,x,0,_,_,_ ), 96 , 117, 8088 , 294, 130), // #1266 + INST(Vpmaskmovq , VexRvmMvr_Lx , V(660F38,8C,_,x,1,_,_,_ ), V(660F38,8E,_,x,1,_,_,_ ), 165, 118, 8099 , 294, 130), // #1267 + INST(Vpmaxsb , VexRvm_Lx , V(660F38,3C,_,x,I,I,4,FVM), 0 , 107, 0 , 8110 , 355, 146), // #1268 + INST(Vpmaxsd , VexRvm_Lx , V(660F38,3D,_,x,I,0,4,FV ), 0 , 163, 0 , 8118 , 202, 131), // #1269 + INST(Vpmaxsq , VexRvm_Lx , E(660F38,3D,_,x,_,1,4,FV ), 0 , 112, 0 , 8126 , 205, 126), // #1270 + INST(Vpmaxsw , VexRvm_Lx , V(660F00,EE,_,x,I,I,4,FVM), 0 , 184, 0 , 8134 , 355, 146), // #1271 + INST(Vpmaxub , VexRvm_Lx , V(660F00,DE,_,x,I,I,4,FVM), 0 , 184, 0 , 8142 , 355, 146), // #1272 + INST(Vpmaxud , VexRvm_Lx , V(660F38,3F,_,x,I,0,4,FV ), 0 , 163, 0 , 8150 , 202, 131), // #1273 + INST(Vpmaxuq , VexRvm_Lx , E(660F38,3F,_,x,_,1,4,FV ), 0 , 112, 0 , 8158 , 205, 126), // #1274 + INST(Vpmaxuw , VexRvm_Lx , V(660F38,3E,_,x,I,I,4,FVM), 0 , 107, 0 , 8166 , 355, 146), // #1275 + INST(Vpminsb , VexRvm_Lx , V(660F38,38,_,x,I,I,4,FVM), 0 , 107, 0 , 8174 , 355, 146), // #1276 + INST(Vpminsd , VexRvm_Lx , V(660F38,39,_,x,I,0,4,FV ), 0 , 163, 0 , 8182 , 202, 131), // #1277 + INST(Vpminsq , VexRvm_Lx , E(660F38,39,_,x,_,1,4,FV ), 0 , 112, 0 , 8190 , 205, 126), // #1278 + INST(Vpminsw , VexRvm_Lx , V(660F00,EA,_,x,I,I,4,FVM), 0 , 184, 0 , 8198 , 355, 146), // #1279 + INST(Vpminub , VexRvm_Lx , V(660F00,DA,_,x,I,_,4,FVM), 0 , 184, 0 , 8206 , 355, 146), // #1280 + INST(Vpminud , VexRvm_Lx , V(660F38,3B,_,x,I,0,4,FV ), 0 , 163, 0 , 8214 , 202, 131), // #1281 + INST(Vpminuq , VexRvm_Lx , E(660F38,3B,_,x,_,1,4,FV ), 0 , 112, 0 , 8222 , 205, 126), // #1282 + INST(Vpminuw , VexRvm_Lx , V(660F38,3A,_,x,I,_,4,FVM), 0 , 107, 0 , 8230 , 355, 146), // #1283 + INST(Vpmovb2m , VexRm_Lx , E(F30F38,29,_,x,_,0,_,_ ), 0 , 128, 0 , 8238 , 356, 128), // #1284 + INST(Vpmovd2m , VexRm_Lx , E(F30F38,39,_,x,_,0,_,_ ), 0 , 128, 0 , 8247 , 356, 129), // #1285 + INST(Vpmovdb , VexMr_Lx , E(F30F38,31,_,x,_,0,2,QVM), 0 , 204, 0 , 8256 , 357, 126), // #1286 + INST(Vpmovdw , VexMr_Lx , E(F30F38,33,_,x,_,0,3,HVM), 0 , 205, 0 , 8264 , 358, 126), // #1287 + INST(Vpmovm2b , VexRm_Lx , E(F30F38,28,_,x,_,0,_,_ ), 0 , 128, 0 , 8272 , 325, 128), // #1288 + INST(Vpmovm2d , VexRm_Lx , E(F30F38,38,_,x,_,0,_,_ ), 0 , 128, 0 , 8281 , 325, 129), // #1289 + INST(Vpmovm2q , VexRm_Lx , E(F30F38,38,_,x,_,1,_,_ ), 0 , 191, 0 , 8290 , 325, 129), // #1290 + INST(Vpmovm2w , VexRm_Lx , E(F30F38,28,_,x,_,1,_,_ ), 0 , 191, 0 , 8299 , 325, 128), // #1291 + INST(Vpmovmskb , VexRm_Lx , V(660F00,D7,_,x,I,_,_,_ ), 0 , 68 , 0 , 8308 , 306, 143), // #1292 + INST(Vpmovq2m , VexRm_Lx , E(F30F38,39,_,x,_,1,_,_ ), 0 , 191, 0 , 8318 , 356, 129), // #1293 + INST(Vpmovqb , VexMr_Lx , E(F30F38,32,_,x,_,0,1,OVM), 0 , 206, 0 , 8327 , 359, 126), // #1294 + INST(Vpmovqd , VexMr_Lx , E(F30F38,35,_,x,_,0,3,HVM), 0 , 205, 0 , 8335 , 358, 126), // #1295 + INST(Vpmovqw , VexMr_Lx , E(F30F38,34,_,x,_,0,2,QVM), 0 , 204, 0 , 8343 , 357, 126), // #1296 + INST(Vpmovsdb , VexMr_Lx , E(F30F38,21,_,x,_,0,2,QVM), 0 , 204, 0 , 8351 , 357, 126), // #1297 + INST(Vpmovsdw , VexMr_Lx , E(F30F38,23,_,x,_,0,3,HVM), 0 , 205, 0 , 8360 , 358, 126), // #1298 + INST(Vpmovsqb , VexMr_Lx , E(F30F38,22,_,x,_,0,1,OVM), 0 , 206, 0 , 8369 , 359, 126), // #1299 + INST(Vpmovsqd , VexMr_Lx , E(F30F38,25,_,x,_,0,3,HVM), 0 , 205, 0 , 8378 , 358, 126), // #1300 + INST(Vpmovsqw , VexMr_Lx , E(F30F38,24,_,x,_,0,2,QVM), 0 , 204, 0 , 8387 , 357, 126), // #1301 + INST(Vpmovswb , VexMr_Lx , E(F30F38,20,_,x,_,0,3,HVM), 0 , 205, 0 , 8396 , 358, 128), // #1302 + INST(Vpmovsxbd , VexRm_Lx , V(660F38,21,_,x,I,I,2,QVM), 0 , 207, 0 , 8405 , 360, 131), // #1303 + INST(Vpmovsxbq , VexRm_Lx , V(660F38,22,_,x,I,I,1,OVM), 0 , 208, 0 , 8415 , 361, 131), // #1304 + INST(Vpmovsxbw , VexRm_Lx , V(660F38,20,_,x,I,I,3,HVM), 0 , 132, 0 , 8425 , 362, 146), // #1305 + INST(Vpmovsxdq , VexRm_Lx , V(660F38,25,_,x,I,0,3,HVM), 0 , 132, 0 , 8435 , 362, 131), // #1306 + INST(Vpmovsxwd , VexRm_Lx , V(660F38,23,_,x,I,I,3,HVM), 0 , 132, 0 , 8445 , 362, 131), // #1307 + INST(Vpmovsxwq , VexRm_Lx , V(660F38,24,_,x,I,I,2,QVM), 0 , 207, 0 , 8455 , 360, 131), // #1308 + INST(Vpmovusdb , VexMr_Lx , E(F30F38,11,_,x,_,0,2,QVM), 0 , 204, 0 , 8465 , 357, 126), // #1309 + INST(Vpmovusdw , VexMr_Lx , E(F30F38,13,_,x,_,0,3,HVM), 0 , 205, 0 , 8475 , 358, 126), // #1310 + INST(Vpmovusqb , VexMr_Lx , E(F30F38,12,_,x,_,0,1,OVM), 0 , 206, 0 , 8485 , 359, 126), // #1311 + INST(Vpmovusqd , VexMr_Lx , E(F30F38,15,_,x,_,0,3,HVM), 0 , 205, 0 , 8495 , 358, 126), // #1312 + INST(Vpmovusqw , VexMr_Lx , E(F30F38,14,_,x,_,0,2,QVM), 0 , 204, 0 , 8505 , 357, 126), // #1313 + INST(Vpmovuswb , VexMr_Lx , E(F30F38,10,_,x,_,0,3,HVM), 0 , 205, 0 , 8515 , 358, 128), // #1314 + INST(Vpmovw2m , VexRm_Lx , E(F30F38,29,_,x,_,1,_,_ ), 0 , 191, 0 , 8525 , 356, 128), // #1315 + INST(Vpmovwb , VexMr_Lx , E(F30F38,30,_,x,_,0,3,HVM), 0 , 205, 0 , 8534 , 358, 128), // #1316 + INST(Vpmovzxbd , VexRm_Lx , V(660F38,31,_,x,I,I,2,QVM), 0 , 207, 0 , 8542 , 360, 131), // #1317 + INST(Vpmovzxbq , VexRm_Lx , V(660F38,32,_,x,I,I,1,OVM), 0 , 208, 0 , 8552 , 361, 131), // #1318 + INST(Vpmovzxbw , VexRm_Lx , V(660F38,30,_,x,I,I,3,HVM), 0 , 132, 0 , 8562 , 362, 146), // #1319 + INST(Vpmovzxdq , VexRm_Lx , V(660F38,35,_,x,I,0,3,HVM), 0 , 132, 0 , 8572 , 362, 131), // #1320 + INST(Vpmovzxwd , VexRm_Lx , V(660F38,33,_,x,I,I,3,HVM), 0 , 132, 0 , 8582 , 362, 131), // #1321 + INST(Vpmovzxwq , VexRm_Lx , V(660F38,34,_,x,I,I,2,QVM), 0 , 207, 0 , 8592 , 360, 131), // #1322 + INST(Vpmuldq , VexRvm_Lx , V(660F38,28,_,x,I,1,4,FV ), 0 , 198, 0 , 8602 , 199, 131), // #1323 + INST(Vpmulhrsw , VexRvm_Lx , V(660F38,0B,_,x,I,I,4,FVM), 0 , 107, 0 , 8610 , 286, 146), // #1324 + INST(Vpmulhuw , VexRvm_Lx , V(660F00,E4,_,x,I,I,4,FVM), 0 , 184, 0 , 8620 , 286, 146), // #1325 + INST(Vpmulhw , VexRvm_Lx , V(660F00,E5,_,x,I,I,4,FVM), 0 , 184, 0 , 8629 , 286, 146), // #1326 + INST(Vpmulld , VexRvm_Lx , V(660F38,40,_,x,I,0,4,FV ), 0 , 163, 0 , 8637 , 200, 131), // #1327 + INST(Vpmullq , VexRvm_Lx , E(660F38,40,_,x,_,1,4,FV ), 0 , 112, 0 , 8645 , 205, 129), // #1328 + INST(Vpmullw , VexRvm_Lx , V(660F00,D5,_,x,I,I,4,FVM), 0 , 184, 0 , 8653 , 286, 146), // #1329 + INST(Vpmultishiftqb , VexRvm_Lx , E(660F38,83,_,x,_,1,4,FV ), 0 , 112, 0 , 8661 , 205, 153), // #1330 + INST(Vpmuludq , VexRvm_Lx , V(660F00,F4,_,x,I,1,4,FV ), 0 , 102, 0 , 8676 , 199, 131), // #1331 + INST(Vpopcntb , VexRm_Lx , E(660F38,54,_,x,_,0,4,FV ), 0 , 111, 0 , 8685 , 255, 157), // #1332 + INST(Vpopcntd , VexRm_Lx , E(660F38,55,_,x,_,0,4,FVM), 0 , 110, 0 , 8694 , 339, 158), // #1333 + INST(Vpopcntq , VexRm_Lx , E(660F38,55,_,x,_,1,4,FVM), 0 , 113, 0 , 8703 , 353, 158), // #1334 + INST(Vpopcntw , VexRm_Lx , E(660F38,54,_,x,_,1,4,FV ), 0 , 112, 0 , 8712 , 255, 157), // #1335 + INST(Vpor , VexRvm_Lx , V(660F00,EB,_,x,I,_,_,_ ), 0 , 68 , 0 , 8721 , 317, 143), // #1336 + INST(Vpord , VexRvm_Lx , E(660F00,EB,_,x,_,0,4,FV ), 0 , 189, 0 , 8726 , 318, 126), // #1337 + INST(Vporq , VexRvm_Lx , E(660F00,EB,_,x,_,1,4,FV ), 0 , 130, 0 , 8732 , 322, 126), // #1338 + INST(Vpperm , VexRvrmRvmr , V(XOP_M8,A3,_,0,x,_,_,_ ), 0 , 193, 0 , 8738 , 363, 139), // #1339 + INST(Vprold , VexVmi_Lx , E(660F00,72,1,x,_,0,4,FV ), 0 , 209, 0 , 8745 , 364, 126), // #1340 + INST(Vprolq , VexVmi_Lx , E(660F00,72,1,x,_,1,4,FV ), 0 , 210, 0 , 8752 , 365, 126), // #1341 + INST(Vprolvd , VexRvm_Lx , E(660F38,15,_,x,_,0,4,FV ), 0 , 111, 0 , 8759 , 204, 126), // #1342 + INST(Vprolvq , VexRvm_Lx , E(660F38,15,_,x,_,1,4,FV ), 0 , 112, 0 , 8767 , 205, 126), // #1343 + INST(Vprord , VexVmi_Lx , E(660F00,72,0,x,_,0,4,FV ), 0 , 189, 0 , 8775 , 364, 126), // #1344 + INST(Vprorq , VexVmi_Lx , E(660F00,72,0,x,_,1,4,FV ), 0 , 130, 0 , 8782 , 365, 126), // #1345 + INST(Vprorvd , VexRvm_Lx , E(660F38,14,_,x,_,0,4,FV ), 0 , 111, 0 , 8789 , 204, 126), // #1346 + INST(Vprorvq , VexRvm_Lx , E(660F38,14,_,x,_,1,4,FV ), 0 , 112, 0 , 8797 , 205, 126), // #1347 + INST(Vprotb , VexRvmRmvRmi , V(XOP_M9,90,_,0,x,_,_,_ ), V(XOP_M8,C0,_,0,x,_,_,_ ), 77 , 119, 8805 , 366, 139), // #1348 + INST(Vprotd , VexRvmRmvRmi , V(XOP_M9,92,_,0,x,_,_,_ ), V(XOP_M8,C2,_,0,x,_,_,_ ), 77 , 120, 8812 , 366, 139), // #1349 + INST(Vprotq , VexRvmRmvRmi , V(XOP_M9,93,_,0,x,_,_,_ ), V(XOP_M8,C3,_,0,x,_,_,_ ), 77 , 121, 8819 , 366, 139), // #1350 + INST(Vprotw , VexRvmRmvRmi , V(XOP_M9,91,_,0,x,_,_,_ ), V(XOP_M8,C1,_,0,x,_,_,_ ), 77 , 122, 8826 , 366, 139), // #1351 + INST(Vpsadbw , VexRvm_Lx , V(660F00,F6,_,x,I,I,4,FVM), 0 , 184, 0 , 8833 , 194, 146), // #1352 + INST(Vpscatterdd , VexMr_VM , E(660F38,A0,_,x,_,0,2,T1S), 0 , 125, 0 , 8841 , 367, 126), // #1353 + INST(Vpscatterdq , VexMr_VM , E(660F38,A0,_,x,_,1,3,T1S), 0 , 124, 0 , 8853 , 367, 126), // #1354 + INST(Vpscatterqd , VexMr_VM , E(660F38,A1,_,x,_,0,2,T1S), 0 , 125, 0 , 8865 , 368, 126), // #1355 + INST(Vpscatterqq , VexMr_VM , E(660F38,A1,_,x,_,1,3,T1S), 0 , 124, 0 , 8877 , 369, 126), // #1356 + INST(Vpshab , VexRvmRmv , V(XOP_M9,98,_,0,x,_,_,_ ), 0 , 77 , 0 , 8889 , 370, 139), // #1357 + INST(Vpshad , VexRvmRmv , V(XOP_M9,9A,_,0,x,_,_,_ ), 0 , 77 , 0 , 8896 , 370, 139), // #1358 + INST(Vpshaq , VexRvmRmv , V(XOP_M9,9B,_,0,x,_,_,_ ), 0 , 77 , 0 , 8903 , 370, 139), // #1359 + INST(Vpshaw , VexRvmRmv , V(XOP_M9,99,_,0,x,_,_,_ ), 0 , 77 , 0 , 8910 , 370, 139), // #1360 + INST(Vpshlb , VexRvmRmv , V(XOP_M9,94,_,0,x,_,_,_ ), 0 , 77 , 0 , 8917 , 370, 139), // #1361 + INST(Vpshld , VexRvmRmv , V(XOP_M9,96,_,0,x,_,_,_ ), 0 , 77 , 0 , 8924 , 370, 139), // #1362 + INST(Vpshldd , VexRvmi_Lx , E(660F3A,71,_,x,_,0,4,FV ), 0 , 108, 0 , 8931 , 197, 151), // #1363 + INST(Vpshldq , VexRvmi_Lx , E(660F3A,71,_,x,_,1,4,FV ), 0 , 109, 0 , 8939 , 198, 151), // #1364 + INST(Vpshldvd , VexRvm_Lx , E(660F38,71,_,x,_,0,4,FV ), 0 , 111, 0 , 8947 , 204, 151), // #1365 + INST(Vpshldvq , VexRvm_Lx , E(660F38,71,_,x,_,1,4,FV ), 0 , 112, 0 , 8956 , 205, 151), // #1366 + INST(Vpshldvw , VexRvm_Lx , E(660F38,70,_,x,_,0,4,FVM), 0 , 110, 0 , 8965 , 203, 151), // #1367 + INST(Vpshldw , VexRvmi_Lx , E(660F3A,70,_,x,_,0,4,FVM), 0 , 151, 0 , 8974 , 251, 151), // #1368 + INST(Vpshlq , VexRvmRmv , V(XOP_M9,97,_,0,x,_,_,_ ), 0 , 77 , 0 , 8982 , 370, 139), // #1369 + INST(Vpshlw , VexRvmRmv , V(XOP_M9,95,_,0,x,_,_,_ ), 0 , 77 , 0 , 8989 , 370, 139), // #1370 + INST(Vpshrdd , VexRvmi_Lx , E(660F3A,73,_,x,_,0,4,FV ), 0 , 108, 0 , 8996 , 197, 151), // #1371 + INST(Vpshrdq , VexRvmi_Lx , E(660F3A,73,_,x,_,1,4,FV ), 0 , 109, 0 , 9004 , 198, 151), // #1372 + INST(Vpshrdvd , VexRvm_Lx , E(660F38,73,_,x,_,0,4,FV ), 0 , 111, 0 , 9012 , 204, 151), // #1373 + INST(Vpshrdvq , VexRvm_Lx , E(660F38,73,_,x,_,1,4,FV ), 0 , 112, 0 , 9021 , 205, 151), // #1374 + INST(Vpshrdvw , VexRvm_Lx , E(660F38,72,_,x,_,0,4,FVM), 0 , 110, 0 , 9030 , 203, 151), // #1375 + INST(Vpshrdw , VexRvmi_Lx , E(660F3A,72,_,x,_,0,4,FVM), 0 , 151, 0 , 9039 , 251, 151), // #1376 + INST(Vpshufb , VexRvm_Lx , V(660F38,00,_,x,I,I,4,FVM), 0 , 107, 0 , 9047 , 286, 146), // #1377 + INST(Vpshufbitqmb , VexRvm_Lx , E(660F38,8F,_,x,0,0,4,FVM), 0 , 110, 0 , 9055 , 371, 157), // #1378 + INST(Vpshufd , VexRmi_Lx , V(660F00,70,_,x,I,0,4,FV ), 0 , 133, 0 , 9068 , 372, 131), // #1379 + INST(Vpshufhw , VexRmi_Lx , V(F30F00,70,_,x,I,I,4,FVM), 0 , 185, 0 , 9076 , 373, 146), // #1380 + INST(Vpshuflw , VexRmi_Lx , V(F20F00,70,_,x,I,I,4,FVM), 0 , 211, 0 , 9085 , 373, 146), // #1381 + INST(Vpsignb , VexRvm_Lx , V(660F38,08,_,x,I,_,_,_ ), 0 , 96 , 0 , 9094 , 193, 143), // #1382 + INST(Vpsignd , VexRvm_Lx , V(660F38,0A,_,x,I,_,_,_ ), 0 , 96 , 0 , 9102 , 193, 143), // #1383 + INST(Vpsignw , VexRvm_Lx , V(660F38,09,_,x,I,_,_,_ ), 0 , 96 , 0 , 9110 , 193, 143), // #1384 + INST(Vpslld , VexRvmVmi_Lx , V(660F00,F2,_,x,I,0,4,128), V(660F00,72,6,x,I,0,4,FV ), 212, 123, 9118 , 374, 131), // #1385 + INST(Vpslldq , VexEvexVmi_Lx , V(660F00,73,7,x,I,I,4,FVM), 0 , 213, 0 , 9125 , 375, 146), // #1386 + INST(Vpsllq , VexRvmVmi_Lx , V(660F00,F3,_,x,I,1,4,128), V(660F00,73,6,x,I,1,4,FV ), 214, 124, 9133 , 376, 131), // #1387 + INST(Vpsllvd , VexRvm_Lx , V(660F38,47,_,x,0,0,4,FV ), 0 , 163, 0 , 9140 , 200, 140), // #1388 + INST(Vpsllvq , VexRvm_Lx , V(660F38,47,_,x,1,1,4,FV ), 0 , 162, 0 , 9148 , 199, 140), // #1389 + INST(Vpsllvw , VexRvm_Lx , E(660F38,12,_,x,_,1,4,FVM), 0 , 113, 0 , 9156 , 203, 128), // #1390 + INST(Vpsllw , VexRvmVmi_Lx , V(660F00,F1,_,x,I,I,4,FVM), V(660F00,71,6,x,I,I,4,FVM), 184, 125, 9164 , 377, 146), // #1391 + INST(Vpsrad , VexRvmVmi_Lx , V(660F00,E2,_,x,I,0,4,128), V(660F00,72,4,x,I,0,4,FV ), 212, 126, 9171 , 374, 131), // #1392 + INST(Vpsraq , VexRvmVmi_Lx , E(660F00,E2,_,x,_,1,4,128), E(660F00,72,4,x,_,1,4,FV ), 215, 127, 9178 , 378, 126), // #1393 + INST(Vpsravd , VexRvm_Lx , V(660F38,46,_,x,0,0,4,FV ), 0 , 163, 0 , 9185 , 200, 140), // #1394 + INST(Vpsravq , VexRvm_Lx , E(660F38,46,_,x,_,1,4,FV ), 0 , 112, 0 , 9193 , 205, 126), // #1395 + INST(Vpsravw , VexRvm_Lx , E(660F38,11,_,x,_,1,4,FVM), 0 , 113, 0 , 9201 , 203, 128), // #1396 + INST(Vpsraw , VexRvmVmi_Lx , V(660F00,E1,_,x,I,I,4,128), V(660F00,71,4,x,I,I,4,FVM), 212, 128, 9209 , 377, 146), // #1397 + INST(Vpsrld , VexRvmVmi_Lx , V(660F00,D2,_,x,I,0,4,128), V(660F00,72,2,x,I,0,4,FV ), 212, 129, 9216 , 374, 131), // #1398 + INST(Vpsrldq , VexEvexVmi_Lx , V(660F00,73,3,x,I,I,4,FVM), 0 , 216, 0 , 9223 , 375, 146), // #1399 + INST(Vpsrlq , VexRvmVmi_Lx , V(660F00,D3,_,x,I,1,4,128), V(660F00,73,2,x,I,1,4,FV ), 214, 130, 9231 , 376, 131), // #1400 + INST(Vpsrlvd , VexRvm_Lx , V(660F38,45,_,x,0,0,4,FV ), 0 , 163, 0 , 9238 , 200, 140), // #1401 + INST(Vpsrlvq , VexRvm_Lx , V(660F38,45,_,x,1,1,4,FV ), 0 , 162, 0 , 9246 , 199, 140), // #1402 + INST(Vpsrlvw , VexRvm_Lx , E(660F38,10,_,x,_,1,4,FVM), 0 , 113, 0 , 9254 , 203, 128), // #1403 + INST(Vpsrlw , VexRvmVmi_Lx , V(660F00,D1,_,x,I,I,4,128), V(660F00,71,2,x,I,I,4,FVM), 212, 131, 9262 , 377, 146), // #1404 + INST(Vpsubb , VexRvm_Lx , V(660F00,F8,_,x,I,I,4,FVM), 0 , 184, 0 , 9269 , 379, 146), // #1405 + INST(Vpsubd , VexRvm_Lx , V(660F00,FA,_,x,I,0,4,FV ), 0 , 133, 0 , 9276 , 380, 131), // #1406 + INST(Vpsubq , VexRvm_Lx , V(660F00,FB,_,x,I,1,4,FV ), 0 , 102, 0 , 9283 , 381, 131), // #1407 + INST(Vpsubsb , VexRvm_Lx , V(660F00,E8,_,x,I,I,4,FVM), 0 , 184, 0 , 9290 , 379, 146), // #1408 + INST(Vpsubsw , VexRvm_Lx , V(660F00,E9,_,x,I,I,4,FVM), 0 , 184, 0 , 9298 , 379, 146), // #1409 + INST(Vpsubusb , VexRvm_Lx , V(660F00,D8,_,x,I,I,4,FVM), 0 , 184, 0 , 9306 , 379, 146), // #1410 + INST(Vpsubusw , VexRvm_Lx , V(660F00,D9,_,x,I,I,4,FVM), 0 , 184, 0 , 9315 , 379, 146), // #1411 + INST(Vpsubw , VexRvm_Lx , V(660F00,F9,_,x,I,I,4,FVM), 0 , 184, 0 , 9324 , 379, 146), // #1412 + INST(Vpternlogd , VexRvmi_Lx , E(660F3A,25,_,x,_,0,4,FV ), 0 , 108, 0 , 9331 , 197, 126), // #1413 + INST(Vpternlogq , VexRvmi_Lx , E(660F3A,25,_,x,_,1,4,FV ), 0 , 109, 0 , 9342 , 198, 126), // #1414 + INST(Vptest , VexRm_Lx , V(660F38,17,_,x,I,_,_,_ ), 0 , 96 , 0 , 9353 , 271, 150), // #1415 + INST(Vptestmb , VexRvm_Lx , E(660F38,26,_,x,_,0,4,FVM), 0 , 110, 0 , 9360 , 371, 128), // #1416 + INST(Vptestmd , VexRvm_Lx , E(660F38,27,_,x,_,0,4,FV ), 0 , 111, 0 , 9369 , 382, 126), // #1417 + INST(Vptestmq , VexRvm_Lx , E(660F38,27,_,x,_,1,4,FV ), 0 , 112, 0 , 9378 , 383, 126), // #1418 + INST(Vptestmw , VexRvm_Lx , E(660F38,26,_,x,_,1,4,FVM), 0 , 113, 0 , 9387 , 371, 128), // #1419 + INST(Vptestnmb , VexRvm_Lx , E(F30F38,26,_,x,_,0,4,FVM), 0 , 217, 0 , 9396 , 371, 128), // #1420 + INST(Vptestnmd , VexRvm_Lx , E(F30F38,27,_,x,_,0,4,FV ), 0 , 218, 0 , 9406 , 382, 126), // #1421 + INST(Vptestnmq , VexRvm_Lx , E(F30F38,27,_,x,_,1,4,FV ), 0 , 219, 0 , 9416 , 383, 126), // #1422 + INST(Vptestnmw , VexRvm_Lx , E(F30F38,26,_,x,_,1,4,FVM), 0 , 220, 0 , 9426 , 371, 128), // #1423 + INST(Vpunpckhbw , VexRvm_Lx , V(660F00,68,_,x,I,I,4,FVM), 0 , 184, 0 , 9436 , 286, 146), // #1424 + INST(Vpunpckhdq , VexRvm_Lx , V(660F00,6A,_,x,I,0,4,FV ), 0 , 133, 0 , 9447 , 200, 131), // #1425 + INST(Vpunpckhqdq , VexRvm_Lx , V(660F00,6D,_,x,I,1,4,FV ), 0 , 102, 0 , 9458 , 199, 131), // #1426 + INST(Vpunpckhwd , VexRvm_Lx , V(660F00,69,_,x,I,I,4,FVM), 0 , 184, 0 , 9470 , 286, 146), // #1427 + INST(Vpunpcklbw , VexRvm_Lx , V(660F00,60,_,x,I,I,4,FVM), 0 , 184, 0 , 9481 , 286, 146), // #1428 + INST(Vpunpckldq , VexRvm_Lx , V(660F00,62,_,x,I,0,4,FV ), 0 , 133, 0 , 9492 , 200, 131), // #1429 + INST(Vpunpcklqdq , VexRvm_Lx , V(660F00,6C,_,x,I,1,4,FV ), 0 , 102, 0 , 9503 , 199, 131), // #1430 + INST(Vpunpcklwd , VexRvm_Lx , V(660F00,61,_,x,I,I,4,FVM), 0 , 184, 0 , 9515 , 286, 146), // #1431 + INST(Vpxor , VexRvm_Lx , V(660F00,EF,_,x,I,_,_,_ ), 0 , 68 , 0 , 9526 , 319, 143), // #1432 + INST(Vpxord , VexRvm_Lx , E(660F00,EF,_,x,_,0,4,FV ), 0 , 189, 0 , 9532 , 320, 126), // #1433 + INST(Vpxorq , VexRvm_Lx , E(660F00,EF,_,x,_,1,4,FV ), 0 , 130, 0 , 9539 , 321, 126), // #1434 + INST(Vrangepd , VexRvmi_Lx , E(660F3A,50,_,x,_,1,4,FV ), 0 , 109, 0 , 9546 , 260, 129), // #1435 + INST(Vrangeps , VexRvmi_Lx , E(660F3A,50,_,x,_,0,4,FV ), 0 , 108, 0 , 9555 , 261, 129), // #1436 + INST(Vrangesd , VexRvmi , E(660F3A,51,_,I,_,1,3,T1S), 0 , 160, 0 , 9564 , 262, 64 ), // #1437 + INST(Vrangess , VexRvmi , E(660F3A,51,_,I,_,0,2,T1S), 0 , 161, 0 , 9573 , 263, 64 ), // #1438 + INST(Vrcp14pd , VexRm_Lx , E(660F38,4C,_,x,_,1,4,FV ), 0 , 112, 0 , 9582 , 353, 126), // #1439 + INST(Vrcp14ps , VexRm_Lx , E(660F38,4C,_,x,_,0,4,FV ), 0 , 111, 0 , 9591 , 339, 126), // #1440 + INST(Vrcp14sd , VexRvm , E(660F38,4D,_,I,_,1,3,T1S), 0 , 124, 0 , 9600 , 384, 66 ), // #1441 + INST(Vrcp14ss , VexRvm , E(660F38,4D,_,I,_,0,2,T1S), 0 , 125, 0 , 9609 , 385, 66 ), // #1442 + INST(Vrcp28pd , VexRm , E(660F38,CA,_,2,_,1,4,FV ), 0 , 152, 0 , 9618 , 253, 135), // #1443 + INST(Vrcp28ps , VexRm , E(660F38,CA,_,2,_,0,4,FV ), 0 , 153, 0 , 9627 , 254, 135), // #1444 + INST(Vrcp28sd , VexRvm , E(660F38,CB,_,I,_,1,3,T1S), 0 , 124, 0 , 9636 , 281, 135), // #1445 + INST(Vrcp28ss , VexRvm , E(660F38,CB,_,I,_,0,2,T1S), 0 , 125, 0 , 9645 , 282, 135), // #1446 + INST(Vrcpps , VexRm_Lx , V(000F00,53,_,x,I,_,_,_ ), 0 , 71 , 0 , 9654 , 271, 123), // #1447 + INST(Vrcpss , VexRvm , V(F30F00,53,_,I,I,_,_,_ ), 0 , 178, 0 , 9661 , 386, 123), // #1448 + INST(Vreducepd , VexRmi_Lx , E(660F3A,56,_,x,_,1,4,FV ), 0 , 109, 0 , 9668 , 365, 129), // #1449 + INST(Vreduceps , VexRmi_Lx , E(660F3A,56,_,x,_,0,4,FV ), 0 , 108, 0 , 9678 , 364, 129), // #1450 + INST(Vreducesd , VexRvmi , E(660F3A,57,_,I,_,1,3,T1S), 0 , 160, 0 , 9688 , 387, 64 ), // #1451 + INST(Vreducess , VexRvmi , E(660F3A,57,_,I,_,0,2,T1S), 0 , 161, 0 , 9698 , 388, 64 ), // #1452 + INST(Vrndscalepd , VexRmi_Lx , E(660F3A,09,_,x,_,1,4,FV ), 0 , 109, 0 , 9708 , 283, 126), // #1453 + INST(Vrndscaleps , VexRmi_Lx , E(660F3A,08,_,x,_,0,4,FV ), 0 , 108, 0 , 9720 , 284, 126), // #1454 + INST(Vrndscalesd , VexRvmi , E(660F3A,0B,_,I,_,1,3,T1S), 0 , 160, 0 , 9732 , 262, 66 ), // #1455 + INST(Vrndscaless , VexRvmi , E(660F3A,0A,_,I,_,0,2,T1S), 0 , 161, 0 , 9744 , 263, 66 ), // #1456 + INST(Vroundpd , VexRmi_Lx , V(660F3A,09,_,x,I,_,_,_ ), 0 , 72 , 0 , 9756 , 389, 123), // #1457 + INST(Vroundps , VexRmi_Lx , V(660F3A,08,_,x,I,_,_,_ ), 0 , 72 , 0 , 9765 , 389, 123), // #1458 + INST(Vroundsd , VexRvmi , V(660F3A,0B,_,I,I,_,_,_ ), 0 , 72 , 0 , 9774 , 390, 123), // #1459 + INST(Vroundss , VexRvmi , V(660F3A,0A,_,I,I,_,_,_ ), 0 , 72 , 0 , 9783 , 391, 123), // #1460 + INST(Vrsqrt14pd , VexRm_Lx , E(660F38,4E,_,x,_,1,4,FV ), 0 , 112, 0 , 9792 , 353, 126), // #1461 + INST(Vrsqrt14ps , VexRm_Lx , E(660F38,4E,_,x,_,0,4,FV ), 0 , 111, 0 , 9803 , 339, 126), // #1462 + INST(Vrsqrt14sd , VexRvm , E(660F38,4F,_,I,_,1,3,T1S), 0 , 124, 0 , 9814 , 384, 66 ), // #1463 + INST(Vrsqrt14ss , VexRvm , E(660F38,4F,_,I,_,0,2,T1S), 0 , 125, 0 , 9825 , 385, 66 ), // #1464 + INST(Vrsqrt28pd , VexRm , E(660F38,CC,_,2,_,1,4,FV ), 0 , 152, 0 , 9836 , 253, 135), // #1465 + INST(Vrsqrt28ps , VexRm , E(660F38,CC,_,2,_,0,4,FV ), 0 , 153, 0 , 9847 , 254, 135), // #1466 + INST(Vrsqrt28sd , VexRvm , E(660F38,CD,_,I,_,1,3,T1S), 0 , 124, 0 , 9858 , 281, 135), // #1467 + INST(Vrsqrt28ss , VexRvm , E(660F38,CD,_,I,_,0,2,T1S), 0 , 125, 0 , 9869 , 282, 135), // #1468 + INST(Vrsqrtps , VexRm_Lx , V(000F00,52,_,x,I,_,_,_ ), 0 , 71 , 0 , 9880 , 271, 123), // #1469 + INST(Vrsqrtss , VexRvm , V(F30F00,52,_,I,I,_,_,_ ), 0 , 178, 0 , 9889 , 386, 123), // #1470 + INST(Vscalefpd , VexRvm_Lx , E(660F38,2C,_,x,_,1,4,FV ), 0 , 112, 0 , 9898 , 392, 126), // #1471 + INST(Vscalefps , VexRvm_Lx , E(660F38,2C,_,x,_,0,4,FV ), 0 , 111, 0 , 9908 , 393, 126), // #1472 + INST(Vscalefsd , VexRvm , E(660F38,2D,_,I,_,1,3,T1S), 0 , 124, 0 , 9918 , 394, 66 ), // #1473 + INST(Vscalefss , VexRvm , E(660F38,2D,_,I,_,0,2,T1S), 0 , 125, 0 , 9928 , 395, 66 ), // #1474 + INST(Vscatterdpd , VexMr_Lx , E(660F38,A2,_,x,_,1,3,T1S), 0 , 124, 0 , 9938 , 396, 126), // #1475 + INST(Vscatterdps , VexMr_Lx , E(660F38,A2,_,x,_,0,2,T1S), 0 , 125, 0 , 9950 , 367, 126), // #1476 + INST(Vscatterpf0dpd , VexM_VM , E(660F38,C6,5,2,_,1,3,T1S), 0 , 221, 0 , 9962 , 276, 141), // #1477 + INST(Vscatterpf0dps , VexM_VM , E(660F38,C6,5,2,_,0,2,T1S), 0 , 222, 0 , 9977 , 277, 141), // #1478 + INST(Vscatterpf0qpd , VexM_VM , E(660F38,C7,5,2,_,1,3,T1S), 0 , 221, 0 , 9992 , 278, 141), // #1479 + INST(Vscatterpf0qps , VexM_VM , E(660F38,C7,5,2,_,0,2,T1S), 0 , 222, 0 , 10007, 278, 141), // #1480 + INST(Vscatterpf1dpd , VexM_VM , E(660F38,C6,6,2,_,1,3,T1S), 0 , 223, 0 , 10022, 276, 141), // #1481 + INST(Vscatterpf1dps , VexM_VM , E(660F38,C6,6,2,_,0,2,T1S), 0 , 224, 0 , 10037, 277, 141), // #1482 + INST(Vscatterpf1qpd , VexM_VM , E(660F38,C7,6,2,_,1,3,T1S), 0 , 223, 0 , 10052, 278, 141), // #1483 + INST(Vscatterpf1qps , VexM_VM , E(660F38,C7,6,2,_,0,2,T1S), 0 , 224, 0 , 10067, 278, 141), // #1484 + INST(Vscatterqpd , VexMr_Lx , E(660F38,A3,_,x,_,1,3,T1S), 0 , 124, 0 , 10082, 369, 126), // #1485 + INST(Vscatterqps , VexMr_Lx , E(660F38,A3,_,x,_,0,2,T1S), 0 , 125, 0 , 10094, 368, 126), // #1486 + INST(Vshuff32x4 , VexRvmi_Lx , E(660F3A,23,_,x,_,0,4,FV ), 0 , 108, 0 , 10106, 397, 126), // #1487 + INST(Vshuff64x2 , VexRvmi_Lx , E(660F3A,23,_,x,_,1,4,FV ), 0 , 109, 0 , 10117, 398, 126), // #1488 + INST(Vshufi32x4 , VexRvmi_Lx , E(660F3A,43,_,x,_,0,4,FV ), 0 , 108, 0 , 10128, 397, 126), // #1489 + INST(Vshufi64x2 , VexRvmi_Lx , E(660F3A,43,_,x,_,1,4,FV ), 0 , 109, 0 , 10139, 398, 126), // #1490 + INST(Vshufpd , VexRvmi_Lx , V(660F00,C6,_,x,I,1,4,FV ), 0 , 102, 0 , 10150, 399, 121), // #1491 + INST(Vshufps , VexRvmi_Lx , V(000F00,C6,_,x,I,0,4,FV ), 0 , 103, 0 , 10158, 400, 121), // #1492 + INST(Vsqrtpd , VexRm_Lx , V(660F00,51,_,x,I,1,4,FV ), 0 , 102, 0 , 10166, 401, 121), // #1493 + INST(Vsqrtps , VexRm_Lx , V(000F00,51,_,x,I,0,4,FV ), 0 , 103, 0 , 10174, 223, 121), // #1494 + INST(Vsqrtsd , VexRvm , V(F20F00,51,_,I,I,1,3,T1S), 0 , 104, 0 , 10182, 191, 122), // #1495 + INST(Vsqrtss , VexRvm , V(F30F00,51,_,I,I,0,2,T1S), 0 , 105, 0 , 10190, 192, 122), // #1496 + INST(Vstmxcsr , VexM , V(000F00,AE,3,0,I,_,_,_ ), 0 , 225, 0 , 10198, 292, 123), // #1497 + INST(Vsubpd , VexRvm_Lx , V(660F00,5C,_,x,I,1,4,FV ), 0 , 102, 0 , 10207, 189, 121), // #1498 + INST(Vsubps , VexRvm_Lx , V(000F00,5C,_,x,I,0,4,FV ), 0 , 103, 0 , 10214, 190, 121), // #1499 + INST(Vsubsd , VexRvm , V(F20F00,5C,_,I,I,1,3,T1S), 0 , 104, 0 , 10221, 191, 122), // #1500 + INST(Vsubss , VexRvm , V(F30F00,5C,_,I,I,0,2,T1S), 0 , 105, 0 , 10228, 192, 122), // #1501 + INST(Vtestpd , VexRm_Lx , V(660F38,0F,_,x,0,_,_,_ ), 0 , 96 , 0 , 10235, 271, 150), // #1502 + INST(Vtestps , VexRm_Lx , V(660F38,0E,_,x,0,_,_,_ ), 0 , 96 , 0 , 10243, 271, 150), // #1503 + INST(Vucomisd , VexRm , V(660F00,2E,_,I,I,1,3,T1S), 0 , 122, 0 , 10251, 219, 132), // #1504 + INST(Vucomiss , VexRm , V(000F00,2E,_,I,I,0,2,T1S), 0 , 123, 0 , 10260, 220, 132), // #1505 + INST(Vunpckhpd , VexRvm_Lx , V(660F00,15,_,x,I,1,4,FV ), 0 , 102, 0 , 10269, 199, 121), // #1506 + INST(Vunpckhps , VexRvm_Lx , V(000F00,15,_,x,I,0,4,FV ), 0 , 103, 0 , 10279, 200, 121), // #1507 + INST(Vunpcklpd , VexRvm_Lx , V(660F00,14,_,x,I,1,4,FV ), 0 , 102, 0 , 10289, 199, 121), // #1508 + INST(Vunpcklps , VexRvm_Lx , V(000F00,14,_,x,I,0,4,FV ), 0 , 103, 0 , 10299, 200, 121), // #1509 + INST(Vxorpd , VexRvm_Lx , V(660F00,57,_,x,I,1,4,FV ), 0 , 102, 0 , 10309, 381, 127), // #1510 + INST(Vxorps , VexRvm_Lx , V(000F00,57,_,x,I,0,4,FV ), 0 , 103, 0 , 10316, 380, 127), // #1511 + INST(Vzeroall , VexOp , V(000F00,77,_,1,I,_,_,_ ), 0 , 67 , 0 , 10323, 402, 123), // #1512 + INST(Vzeroupper , VexOp , V(000F00,77,_,0,I,_,_,_ ), 0 , 71 , 0 , 10332, 402, 123), // #1513 + INST(Wbinvd , X86Op , O(000F00,09,_,_,_,_,_,_ ), 0 , 4 , 0 , 10343, 30 , 0 ), // #1514 + INST(Wbnoinvd , X86Op , O(F30F00,09,_,_,_,_,_,_ ), 0 , 6 , 0 , 10350, 30 , 159), // #1515 + INST(Wrfsbase , X86M , O(F30F00,AE,2,_,x,_,_,_ ), 0 , 226, 0 , 10359, 167, 102), // #1516 + INST(Wrgsbase , X86M , O(F30F00,AE,3,_,x,_,_,_ ), 0 , 227, 0 , 10368, 167, 102), // #1517 + INST(Wrmsr , X86Op , O(000F00,30,_,_,_,_,_,_ ), 0 , 4 , 0 , 10377, 168, 103), // #1518 + INST(Wrssd , X86Mr , O(000F38,F6,_,_,_,_,_,_ ), 0 , 82 , 0 , 10383, 403, 54 ), // #1519 + INST(Wrssq , X86Mr , O(000F38,F6,_,_,1,_,_,_ ), 0 , 228, 0 , 10389, 404, 54 ), // #1520 + INST(Wrussd , X86Mr , O(660F38,F5,_,_,_,_,_,_ ), 0 , 2 , 0 , 10395, 403, 54 ), // #1521 + INST(Wrussq , X86Mr , O(660F38,F5,_,_,1,_,_,_ ), 0 , 229, 0 , 10402, 404, 54 ), // #1522 + INST(Xabort , X86Op_Mod11RM_I8 , O(000000,C6,7,_,_,_,_,_ ), 0 , 26 , 0 , 10409, 77 , 160), // #1523 + INST(Xadd , X86Xadd , O(000F00,C0,_,_,x,_,_,_ ), 0 , 4 , 0 , 10416, 405, 37 ), // #1524 + INST(Xbegin , X86JmpRel , O(000000,C7,7,_,_,_,_,_ ), 0 , 26 , 0 , 10421, 406, 160), // #1525 + INST(Xchg , X86Xchg , O(000000,86,_,_,x,_,_,_ ), 0 , 0 , 0 , 457 , 407, 0 ), // #1526 + INST(Xend , X86Op , O(000F01,D5,_,_,_,_,_,_ ), 0 , 21 , 0 , 10428, 30 , 160), // #1527 + INST(Xgetbv , X86Op , O(000F01,D0,_,_,_,_,_,_ ), 0 , 21 , 0 , 10433, 168, 161), // #1528 + INST(Xlatb , X86Op , O(000000,D7,_,_,_,_,_,_ ), 0 , 0 , 0 , 10440, 30 , 0 ), // #1529 + INST(Xor , X86Arith , O(000000,30,6,_,x,_,_,_ ), 0 , 31 , 0 , 9528 , 172, 1 ), // #1530 + INST(Xorpd , ExtRm , O(660F00,57,_,_,_,_,_,_ ), 0 , 3 , 0 , 10310, 145, 4 ), // #1531 + INST(Xorps , ExtRm , O(000F00,57,_,_,_,_,_,_ ), 0 , 4 , 0 , 10317, 145, 5 ), // #1532 + INST(Xresldtrk , X86Op , O(F20F01,E9,_,_,_,_,_,_ ), 0 , 92 , 0 , 10446, 30 , 162), // #1533 + INST(Xrstor , X86M_Only , O(000F00,AE,5,_,_,_,_,_ ), 0 , 75 , 0 , 1159 , 408, 161), // #1534 + INST(Xrstor64 , X86M_Only , O(000F00,AE,5,_,1,_,_,_ ), 0 , 230, 0 , 1167 , 409, 161), // #1535 + INST(Xrstors , X86M_Only , O(000F00,C7,3,_,_,_,_,_ ), 0 , 76 , 0 , 10456, 408, 163), // #1536 + INST(Xrstors64 , X86M_Only , O(000F00,C7,3,_,1,_,_,_ ), 0 , 231, 0 , 10464, 409, 163), // #1537 + INST(Xsave , X86M_Only , O(000F00,AE,4,_,_,_,_,_ ), 0 , 97 , 0 , 1177 , 408, 161), // #1538 + INST(Xsave64 , X86M_Only , O(000F00,AE,4,_,1,_,_,_ ), 0 , 232, 0 , 1184 , 409, 161), // #1539 + INST(Xsavec , X86M_Only , O(000F00,C7,4,_,_,_,_,_ ), 0 , 97 , 0 , 10474, 408, 164), // #1540 + INST(Xsavec64 , X86M_Only , O(000F00,C7,4,_,1,_,_,_ ), 0 , 232, 0 , 10481, 409, 164), // #1541 + INST(Xsaveopt , X86M_Only , O(000F00,AE,6,_,_,_,_,_ ), 0 , 78 , 0 , 10490, 408, 165), // #1542 + INST(Xsaveopt64 , X86M_Only , O(000F00,AE,6,_,1,_,_,_ ), 0 , 233, 0 , 10499, 409, 165), // #1543 + INST(Xsaves , X86M_Only , O(000F00,C7,5,_,_,_,_,_ ), 0 , 75 , 0 , 10510, 408, 163), // #1544 + INST(Xsaves64 , X86M_Only , O(000F00,C7,5,_,1,_,_,_ ), 0 , 230, 0 , 10517, 409, 163), // #1545 + INST(Xsetbv , X86Op , O(000F01,D1,_,_,_,_,_,_ ), 0 , 21 , 0 , 10526, 168, 161), // #1546 + INST(Xsusldtrk , X86Op , O(F20F01,E8,_,_,_,_,_,_ ), 0 , 92 , 0 , 10533, 30 , 162), // #1547 + INST(Xtest , X86Op , O(000F01,D6,_,_,_,_,_,_ ), 0 , 21 , 0 , 10543, 30 , 166) // #1548 // ${InstInfo:End} }; #undef NAME_DATA_INDEX @@ -1765,7 +1766,7 @@ const uint32_t InstDB::_mainOpcodeTable[] = { E(660F3A,00,0,0,0,0,4,FV ), // #108 [ref=14x] E(660F3A,00,0,0,0,1,4,FV ), // #109 [ref=14x] E(660F38,00,0,0,0,0,4,FVM), // #110 [ref=9x] - E(660F38,00,0,0,0,0,4,FV ), // #111 [ref=22x] + E(660F38,00,0,0,0,0,4,FV ), // #111 [ref=18x] E(660F38,00,0,0,0,1,4,FV ), // #112 [ref=28x] E(660F38,00,0,0,0,1,4,FVM), // #113 [ref=9x] V(660F38,00,0,1,0,0,0,_ ), // #114 [ref=2x] @@ -1817,7 +1818,7 @@ const uint32_t InstDB::_mainOpcodeTable[] = { E(660F3A,00,0,0,0,1,3,T1S), // #160 [ref=6x] E(660F3A,00,0,0,0,0,2,T1S), // #161 [ref=6x] V(660F38,00,0,0,1,1,4,FV ), // #162 [ref=20x] - V(660F38,00,0,0,0,0,4,FV ), // #163 [ref=32x] + V(660F38,00,0,0,0,0,4,FV ), // #163 [ref=36x] V(660F38,00,0,0,1,1,3,T1S), // #164 [ref=12x] V(660F38,00,0,0,1,0,0,_ ), // #165 [ref=5x] E(660F38,00,1,2,0,1,3,T1S), // #166 [ref=2x] @@ -1895,7 +1896,7 @@ const uint32_t InstDB::_mainOpcodeTable[] = { // ${AltOpcodeTable:Begin} // ------------------- Automatically generated, do not edit ------------------- const uint32_t InstDB::_altOpcodeTable[] = { - 0 , // #0 [ref=1403x] + 0 , // #0 [ref=1404x] O(660F00,1B,_,_,_,_,_,_ ), // #1 [ref=1x] O(000F00,BA,4,_,x,_,_,_ ), // #2 [ref=1x] O(000F00,BA,7,_,x,_,_,_ ), // #3 [ref=1x] @@ -2047,413 +2048,415 @@ const uint32_t InstDB::_altOpcodeTable[] = { #define SINGLE_REG(VAL) InstDB::kSingleReg##VAL const InstDB::CommonInfo InstDB::_commonInfoTable[] = { { 0 , 0 , 0 , CONTROL(None) , SINGLE_REG(None), 0 }, // #0 [ref=1x] - { 0 , 347, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #1 [ref=4x] - { 0 , 348, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #2 [ref=2x] - { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(None), 0 }, // #3 [ref=2x] - { 0 , 156, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #4 [ref=2x] - { F(Vec) , 70 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #5 [ref=54x] - { F(Vec) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #6 [ref=19x] - { F(Vec) , 230, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #7 [ref=16x] - { F(Vec) , 188, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #8 [ref=20x] - { F(Lock)|F(XAcquire)|F(XRelease) , 28 , 11, CONTROL(None) , SINGLE_REG(RO) , 0 }, // #9 [ref=1x] - { F(Vex) , 245, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #10 [ref=3x] - { F(Vec) , 70 , 1 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #11 [ref=12x] - { 0 , 349, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #12 [ref=1x] - { F(Vex) , 247, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #13 [ref=5x] - { F(Vex) , 156, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #14 [ref=12x] - { F(Vec) , 350, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #15 [ref=4x] - { 0 , 249, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #16 [ref=3x] - { F(Mib) , 351, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #17 [ref=1x] - { 0 , 352, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #18 [ref=1x] - { 0 , 251, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #19 [ref=1x] - { F(Mib) , 353, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #20 [ref=1x] - { 0 , 253, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #21 [ref=1x] - { 0 , 155, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #22 [ref=35x] - { 0 , 354, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #23 [ref=3x] - { 0 , 119, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #24 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 119, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #25 [ref=3x] - { F(Rep)|F(RepIgnored) , 255, 2 , CONTROL(Call) , SINGLE_REG(None), 0 }, // #26 [ref=1x] - { 0 , 355, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #27 [ref=1x] - { 0 , 356, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #28 [ref=2x] - { 0 , 330, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #29 [ref=1x] - { 0 , 99 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #30 [ref=83x] - { 0 , 357, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #31 [ref=24x] - { 0 , 358, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #32 [ref=6x] - { 0 , 359, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #33 [ref=1x] - { 0 , 16 , 12, CONTROL(None) , SINGLE_REG(None), 0 }, // #34 [ref=1x] - { F(Rep) , 360, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #35 [ref=1x] - { F(Vec) , 361, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #36 [ref=2x] - { F(Vec) , 362, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #37 [ref=3x] - { F(Lock)|F(XAcquire)|F(XRelease) , 123, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #38 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 363, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #39 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 364, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #40 [ref=1x] - { 0 , 365, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #41 [ref=1x] - { 0 , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #42 [ref=1x] - { 0 , 257, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #43 [ref=1x] - { F(Mmx)|F(Vec) , 367, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #44 [ref=2x] - { F(Mmx)|F(Vec) , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #45 [ref=2x] - { F(Mmx)|F(Vec) , 369, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #46 [ref=2x] - { F(Vec) , 370, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #47 [ref=2x] - { F(Vec) , 371, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #48 [ref=2x] - { F(Vec) , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #49 [ref=2x] - { 0 , 373, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #50 [ref=1x] - { 0 , 374, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #51 [ref=2x] - { F(Lock)|F(XAcquire)|F(XRelease) , 259, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #52 [ref=2x] - { 0 , 39 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #53 [ref=3x] - { F(Mmx) , 99 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #54 [ref=1x] - { 0 , 261, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #55 [ref=2x] - { 0 , 375, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #56 [ref=1x] - { F(Vec) , 376, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #57 [ref=2x] - { F(Vec) , 263, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #58 [ref=1x] - { F(FpuM32)|F(FpuM64) , 158, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #59 [ref=6x] - { 0 , 265, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #60 [ref=9x] - { F(FpuM80) , 377, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #61 [ref=2x] - { 0 , 266, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #62 [ref=13x] - { F(FpuM32)|F(FpuM64) , 267, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #63 [ref=2x] - { F(FpuM16)|F(FpuM32) , 378, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #64 [ref=9x] - { F(FpuM16)|F(FpuM32)|F(FpuM64) , 379, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #65 [ref=3x] - { F(FpuM32)|F(FpuM64)|F(FpuM80) , 380, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #66 [ref=2x] - { F(FpuM16) , 381, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #67 [ref=3x] - { F(FpuM16) , 382, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #68 [ref=2x] - { F(FpuM32)|F(FpuM64) , 268, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #69 [ref=1x] - { 0 , 383, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #70 [ref=2x] - { 0 , 39 , 10, CONTROL(None) , SINGLE_REG(None), 0 }, // #71 [ref=1x] - { 0 , 384, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #72 [ref=1x] - { 0 , 385, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #73 [ref=2x] - { 0 , 314, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #74 [ref=2x] - { F(Rep) , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #75 [ref=1x] - { F(Vec) , 269, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #76 [ref=1x] - { 0 , 387, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #77 [ref=2x] - { 0 , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #78 [ref=8x] - { 0 , 271, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #79 [ref=3x] - { 0 , 273, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #80 [ref=1x] - { 0 , 99 , 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #81 [ref=3x] - { 0 , 389, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #82 [ref=1x] - { F(Rep)|F(RepIgnored) , 275, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #83 [ref=30x] - { F(Rep)|F(RepIgnored) , 277, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #84 [ref=1x] - { F(Rep)|F(RepIgnored) , 279, 2 , CONTROL(Jump) , SINGLE_REG(None), 0 }, // #85 [ref=1x] - { F(Vec)|F(Vex) , 390, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #86 [ref=27x] - { F(Vec)|F(Vex) , 281, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #87 [ref=1x] - { F(Vec)|F(Vex) , 283, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #88 [ref=1x] - { F(Vec)|F(Vex) , 285, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #89 [ref=1x] - { F(Vec)|F(Vex) , 287, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #90 [ref=1x] - { F(Vec)|F(Vex) , 391, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #91 [ref=12x] - { F(Vec)|F(Vex) , 392, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #92 [ref=8x] - { 0 , 393, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #93 [ref=2x] - { 0 , 289, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #94 [ref=1x] - { F(Vec) , 197, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #95 [ref=2x] - { 0 , 394, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #96 [ref=2x] - { 0 , 291, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #97 [ref=2x] - { F(Vex) , 395, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #98 [ref=2x] - { 0 , 396, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #99 [ref=1x] - { 0 , 161, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #100 [ref=3x] - { 0 , 397, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #101 [ref=5x] - { F(Vex) , 398, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #102 [ref=2x] - { F(Rep) , 399, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #103 [ref=1x] - { 0 , 277, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #104 [ref=3x] - { 0 , 293, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #105 [ref=1x] - { F(Vex) , 400, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #106 [ref=2x] - { F(Vec) , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #107 [ref=1x] - { F(Mmx) , 402, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #108 [ref=1x] - { 0 , 403, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #109 [ref=2x] - { F(XRelease) , 0 , 16, CONTROL(None) , SINGLE_REG(None), 0 }, // #110 [ref=1x] - { F(Vec) , 70 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #111 [ref=6x] - { 0 , 64 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #112 [ref=1x] - { F(Mmx)|F(Vec) , 295, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #113 [ref=1x] - { 0 , 404, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #114 [ref=1x] - { 0 , 68 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #115 [ref=2x] - { F(Mmx)|F(Vec) , 405, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #116 [ref=1x] - { F(Vec) , 264, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #117 [ref=2x] - { F(Vec) , 203, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #118 [ref=4x] - { F(Vec) , 406, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #119 [ref=2x] - { F(Vec) , 71 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #120 [ref=3x] - { F(Mmx) , 407, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #121 [ref=1x] - { F(Vec) , 98 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #122 [ref=1x] - { F(Vec) , 206, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #123 [ref=1x] - { F(Mmx)|F(Vec) , 94 , 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #124 [ref=1x] - { F(Mmx)|F(Vec) , 408, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #125 [ref=1x] - { F(Rep) , 409, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #126 [ref=1x] - { F(Vec) , 97 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #127 [ref=1x] - { F(Vec) , 297, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #128 [ref=1x] - { 0 , 299, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #129 [ref=2x] - { 0 , 301, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #130 [ref=1x] - { F(Vex) , 303, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #131 [ref=1x] - { 0 , 410, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #132 [ref=1x] - { 0 , 411, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #133 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 260, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #134 [ref=2x] - { 0 , 99 , 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #135 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(RO) , 0 }, // #136 [ref=1x] - { 0 , 412, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #137 [ref=1x] - { F(Rep) , 413, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #138 [ref=1x] - { F(Mmx)|F(Vec) , 305, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #139 [ref=40x] - { F(Mmx)|F(Vec) , 307, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #140 [ref=1x] - { F(Mmx)|F(Vec) , 305, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #141 [ref=6x] - { F(Mmx)|F(Vec) , 305, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #142 [ref=16x] - { F(Mmx) , 305, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #143 [ref=26x] - { F(Vec) , 70 , 1 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #144 [ref=4x] - { F(Vec) , 414, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #145 [ref=1x] - { F(Vec) , 415, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #146 [ref=1x] - { F(Vec) , 416, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #147 [ref=1x] - { F(Vec) , 417, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #148 [ref=1x] - { F(Vec) , 418, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #149 [ref=1x] - { F(Vec) , 419, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #150 [ref=1x] - { F(Mmx)|F(Vec) , 309, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #151 [ref=1x] - { F(Vec) , 420, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #152 [ref=1x] - { F(Vec) , 421, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #153 [ref=1x] - { F(Vec) , 422, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #154 [ref=1x] - { F(Mmx)|F(Vec) , 423, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #155 [ref=1x] - { F(Mmx)|F(Vec) , 424, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #156 [ref=1x] - { F(Vec) , 233, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #157 [ref=2x] - { 0 , 127, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #158 [ref=1x] - { 0 , 389, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #159 [ref=9x] - { F(Mmx) , 307, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #160 [ref=1x] - { F(Mmx)|F(Vec) , 311, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #161 [ref=8x] - { F(Vec) , 425, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #162 [ref=2x] - { 0 , 426, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #163 [ref=1x] - { 0 , 131, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #164 [ref=1x] - { 0 , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #165 [ref=8x] - { 0 , 428, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #166 [ref=4x] - { 0 , 429, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #167 [ref=8x] - { 0 , 313, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #168 [ref=1x] - { F(Rep)|F(RepIgnored) , 315, 2 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #169 [ref=1x] - { F(Vex) , 317, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #170 [ref=1x] - { F(Lock)|F(XAcquire)|F(XRelease) , 16 , 12, CONTROL(None) , SINGLE_REG(WO) , 0 }, // #171 [ref=3x] - { F(Rep) , 430, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #172 [ref=1x] - { 0 , 431, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #173 [ref=30x] - { 0 , 164, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #174 [ref=2x] - { 0 , 432, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #175 [ref=3x] - { F(Rep) , 433, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #176 [ref=1x] - { F(Vex) , 434, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #177 [ref=5x] - { 0 , 57 , 7 , CONTROL(None) , SINGLE_REG(None), 0 }, // #178 [ref=1x] - { F(Tsib)|F(Vex) , 435, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #179 [ref=2x] - { F(Vex) , 389, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #180 [ref=1x] - { F(Tsib)|F(Vex) , 436, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #181 [ref=1x] - { F(Vex) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #182 [ref=1x] - { 0 , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #183 [ref=2x] - { 0 , 439, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #184 [ref=2x] - { 0 , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #185 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #186 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 442, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #187 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #188 [ref=22x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #189 [ref=22x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #190 [ref=18x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #191 [ref=17x] - { F(Vec)|F(Vex) , 167, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #192 [ref=15x] - { F(Vec)|F(Vex)|F(Evex) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #193 [ref=5x] - { F(Vec)|F(Vex) , 70 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #194 [ref=17x] - { F(Vec)|F(Vex) , 188, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #195 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 170, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #196 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 170, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #197 [ref=4x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #198 [ref=10x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #199 [ref=12x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 167, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #200 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 167, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #201 [ref=6x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #202 [ref=13x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #203 [ref=16x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #204 [ref=19x] - { F(Vec)|F(Vex) , 170, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #205 [ref=6x] - { F(Vec)|F(Vex) , 319, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #206 [ref=3x] - { F(Vec)|F(Vex) , 445, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #207 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 446, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #208 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 447, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #209 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 448, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #210 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 449, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #211 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 446, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #212 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #213 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 173, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #214 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 173, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #215 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 451, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #216 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 452, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #217 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #218 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 230, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #219 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 176, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #220 [ref=6x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 179, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #221 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #222 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 321, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #223 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 321, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #224 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #225 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 321, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #226 [ref=3x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 179, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #227 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 179, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #228 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 185, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #229 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 179, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #230 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #231 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 370, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #232 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 370, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #233 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 453, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #234 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #235 [ref=3x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #236 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #237 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 321, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #238 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #239 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 321, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #240 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #241 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 179, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #242 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #243 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 370, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #244 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512SAE) , 370, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #245 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #246 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512SAE) , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #247 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 179, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #248 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 453, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #249 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 170, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #250 [ref=3x] - { F(Vec)|F(Vex) , 170, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #251 [ref=9x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 74 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #252 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 74 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #253 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #254 [ref=9x] - { F(Vec)|F(Vex) , 186, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #255 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 454, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #256 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 187, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #257 [ref=4x] - { F(Vec)|F(Vex)|F(Evex) , 376, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #258 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 170, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #259 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 170, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #260 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 455, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #261 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 456, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #262 [ref=4x] - { F(Vec)|F(Vex) , 135, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #263 [ref=13x] - { F(Vec)|F(Vex) , 323, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #264 [ref=4x] - { F(Vec)|F(Vex) , 325, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #265 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512K_B64) , 457, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #266 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512K_B32) , 457, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #267 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512K) , 458, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #268 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512K) , 459, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #269 [ref=1x] - { F(Vec)|F(Vex) , 182, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #270 [ref=7x] - { F(Vec)|F(Vex) , 97 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #271 [ref=1x] - { F(Vec)|F(Vex) , 230, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #272 [ref=1x] - { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 104, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #273 [ref=2x] - { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 109, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #274 [ref=2x] - { F(Vsib)|F(Evex)|F(Avx512K) , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #275 [ref=4x] - { F(Vsib)|F(Evex)|F(Avx512K) , 461, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #276 [ref=4x] - { F(Vsib)|F(Evex)|F(Avx512K) , 462, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #277 [ref=8x] - { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 114, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #278 [ref=2x] - { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 139, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #279 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #280 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #281 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 188, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #282 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 188, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #283 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 170, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #284 [ref=3x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #285 [ref=22x] - { F(Vec)|F(Vex) , 327, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #286 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 327, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #287 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 463, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #288 [ref=4x] - { F(Vec)|F(Vex)|F(Evex) , 456, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #289 [ref=1x] - { F(Vec)|F(Vex) , 197, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #290 [ref=1x] - { F(Vex) , 394, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #291 [ref=2x] - { F(Vec)|F(Vex) , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #292 [ref=1x] - { F(Vec)|F(Vex) , 143, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #293 [ref=4x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #294 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #295 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #296 [ref=2x] - { 0 , 329, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #297 [ref=3x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 70 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #298 [ref=4x] - { F(Vec)|F(Vex)|F(Evex) , 331, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #299 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 191, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #300 [ref=1x] - { F(Vec)|F(Vex) , 70 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #301 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 70 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #302 [ref=6x] - { F(Vec)|F(Vex)|F(Evex) , 205, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #303 [ref=2x] - { F(Vec)|F(Vex)|F(Evex) , 333, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #304 [ref=4x] - { F(Vec)|F(Vex) , 464, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #305 [ref=3x] - { F(Vec)|F(Vex)|F(Evex) , 194, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #306 [ref=3x] - { F(Vec)|F(Vex)|F(Evex) , 197, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #307 [ref=1x] - { F(Vec)|F(Vex)|F(Evex) , 200, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #308 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 203, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #309 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #310 [ref=5x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 206, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #311 [ref=1x] - { 0 , 335, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #312 [ref=1x] - { 0 , 337, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #313 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512B32) , 209, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #314 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512B64) , 209, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #315 [ref=1x] - { F(Vec)|F(Vex) , 167, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #316 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 167, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #317 [ref=2x] - { F(Vec)|F(Vex) , 167, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #318 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 167, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #319 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 167, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #320 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 167, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #321 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 465, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #322 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 466, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #323 [ref=1x] - { F(Vec)|F(Evex) , 467, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #324 [ref=6x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 212, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #325 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 468, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #326 [ref=1x] - { F(Vec)|F(Vex)|F(Evex) , 170, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #327 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512K) , 215, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #328 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512K_B32) , 215, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #329 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512K) , 218, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #330 [ref=4x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B32) , 218, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #331 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B64) , 218, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #332 [ref=2x] - { F(Vec)|F(Vex) , 414, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #333 [ref=1x] - { F(Vec)|F(Vex) , 415, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #334 [ref=1x] - { F(Vec)|F(Vex) , 416, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #335 [ref=1x] - { F(Vec)|F(Vex) , 417, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #336 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512K_B64) , 215, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #337 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #338 [ref=6x] - { F(Vec)|F(Vex) , 171, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #339 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 168, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #340 [ref=2x] - { F(Vec)|F(Vex) , 147, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #341 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 76 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #342 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 151, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #343 [ref=2x] - { F(Vec)|F(Vex)|F(Evex) , 418, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #344 [ref=1x] - { F(Vec)|F(Vex)|F(Evex) , 419, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #345 [ref=1x] - { F(Vec)|F(Vex)|F(Evex) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #346 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 470, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #347 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 471, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #348 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 472, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #349 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 473, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #350 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #351 [ref=4x] - { F(Vec)|F(Vex) , 319, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #352 [ref=12x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 167, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #353 [ref=8x] - { F(Vec)|F(Evex) , 474, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #354 [ref=4x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 221, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #355 [ref=6x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 224, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #356 [ref=9x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 227, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #357 [ref=3x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 230, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #358 [ref=4x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 233, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #359 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 179, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #360 [ref=6x] - { F(Vec)|F(Vex) , 135, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #361 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 188, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #362 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 188, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #363 [ref=3x] - { F(Vec)|F(Vex) , 339, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #364 [ref=4x] - { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 236, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #365 [ref=3x] - { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 341, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #366 [ref=2x] - { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 239, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #367 [ref=2x] - { F(Vec)|F(Vex) , 343, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #368 [ref=8x] - { F(Vec)|F(Evex)|F(Avx512K) , 242, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #369 [ref=5x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 188, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #370 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 188, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #371 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #372 [ref=3x] - { F(Vec)|F(Vex)|F(Evex) , 188, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #373 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #374 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 82 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #375 [ref=3x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 88 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #376 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 167, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #377 [ref=6x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 167, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #378 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 167, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #379 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512K_B32) , 242, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #380 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512K_B64) , 242, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #381 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #382 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #383 [ref=2x] - { F(Vec)|F(Vex) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #384 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 455, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #385 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ) , 456, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #386 [ref=1x] - { F(Vec)|F(Vex) , 188, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #387 [ref=2x] - { F(Vec)|F(Vex) , 455, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #388 [ref=1x] - { F(Vec)|F(Vex) , 456, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #389 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #390 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 167, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #391 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #392 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #393 [ref=1x] - { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 345, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #394 [ref=1x] - { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 171, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #395 [ref=2x] - { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 171, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #396 [ref=2x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 170, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #397 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 170, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #398 [ref=1x] - { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 182, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #399 [ref=1x] - { F(Vec)|F(Vex) , 99 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #400 [ref=2x] - { 0 , 23 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #401 [ref=2x] - { 0 , 52 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #402 [ref=2x] - { F(Lock)|F(XAcquire)|F(XRelease) , 49 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #403 [ref=1x] - { 0 , 475, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #404 [ref=1x] - { F(Lock)|F(XAcquire) , 49 , 8 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #405 [ref=1x] - { 0 , 476, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #406 [ref=6x] - { 0 , 477, 1 , CONTROL(None) , SINGLE_REG(None), 0 } // #407 [ref=6x] + { 0 , 363, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #1 [ref=4x] + { 0 , 364, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #2 [ref=2x] + { F(Lock)|F(XAcquire)|F(XRelease) , 23 , 12, CONTROL(None) , SINGLE_REG(None), 0 }, // #3 [ref=2x] + { 0 , 172, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #4 [ref=2x] + { F(Vec) , 86 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #5 [ref=54x] + { F(Vec) , 113, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #6 [ref=19x] + { F(Vec) , 246, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #7 [ref=16x] + { F(Vec) , 204, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #8 [ref=20x] + { F(Lock)|F(XAcquire)|F(XRelease) , 35 , 11, CONTROL(None) , SINGLE_REG(RO) , 0 }, // #9 [ref=1x] + { F(Vex) , 261, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #10 [ref=3x] + { F(Vec) , 86 , 1 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #11 [ref=12x] + { 0 , 365, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #12 [ref=1x] + { F(Vex) , 263, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #13 [ref=5x] + { F(Vex) , 172, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #14 [ref=12x] + { F(Vec) , 366, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #15 [ref=4x] + { 0 , 265, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #16 [ref=3x] + { F(Mib) , 367, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #17 [ref=1x] + { 0 , 368, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #18 [ref=1x] + { 0 , 267, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #19 [ref=1x] + { F(Mib) , 369, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #20 [ref=1x] + { 0 , 269, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #21 [ref=1x] + { 0 , 171, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #22 [ref=35x] + { 0 , 370, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #23 [ref=3x] + { 0 , 135, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #24 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 135, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #25 [ref=3x] + { F(Rep)|F(RepIgnored) , 271, 2 , CONTROL(Call) , SINGLE_REG(None), 0 }, // #26 [ref=1x] + { 0 , 371, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #27 [ref=1x] + { 0 , 372, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #28 [ref=2x] + { 0 , 346, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #29 [ref=1x] + { 0 , 115, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #30 [ref=83x] + { 0 , 373, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #31 [ref=24x] + { 0 , 374, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #32 [ref=6x] + { 0 , 375, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #33 [ref=1x] + { 0 , 23 , 12, CONTROL(None) , SINGLE_REG(None), 0 }, // #34 [ref=1x] + { F(Rep) , 376, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #35 [ref=1x] + { F(Vec) , 377, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #36 [ref=2x] + { F(Vec) , 378, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #37 [ref=3x] + { F(Lock)|F(XAcquire)|F(XRelease) , 139, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #38 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 379, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #39 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 380, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #40 [ref=1x] + { 0 , 381, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #41 [ref=1x] + { 0 , 382, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #42 [ref=1x] + { 0 , 273, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #43 [ref=1x] + { F(Mmx)|F(Vec) , 383, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #44 [ref=2x] + { F(Mmx)|F(Vec) , 384, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #45 [ref=2x] + { F(Mmx)|F(Vec) , 385, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #46 [ref=2x] + { F(Vec) , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #47 [ref=2x] + { F(Vec) , 387, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #48 [ref=2x] + { F(Vec) , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #49 [ref=2x] + { 0 , 389, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #50 [ref=1x] + { 0 , 390, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #51 [ref=2x] + { F(Lock)|F(XAcquire)|F(XRelease) , 275, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #52 [ref=2x] + { 0 , 46 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #53 [ref=3x] + { F(Mmx) , 115, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #54 [ref=1x] + { 0 , 277, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #55 [ref=2x] + { 0 , 391, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #56 [ref=1x] + { F(Vec) , 392, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #57 [ref=2x] + { F(Vec) , 279, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #58 [ref=1x] + { F(FpuM32)|F(FpuM64) , 174, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #59 [ref=6x] + { 0 , 281, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #60 [ref=9x] + { F(FpuM80) , 393, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #61 [ref=2x] + { 0 , 282, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #62 [ref=13x] + { F(FpuM32)|F(FpuM64) , 283, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #63 [ref=2x] + { F(FpuM16)|F(FpuM32) , 394, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #64 [ref=9x] + { F(FpuM16)|F(FpuM32)|F(FpuM64) , 395, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #65 [ref=3x] + { F(FpuM32)|F(FpuM64)|F(FpuM80) , 396, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #66 [ref=2x] + { F(FpuM16) , 397, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #67 [ref=3x] + { F(FpuM16) , 398, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #68 [ref=2x] + { F(FpuM32)|F(FpuM64) , 284, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #69 [ref=1x] + { 0 , 399, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #70 [ref=2x] + { 0 , 46 , 10, CONTROL(None) , SINGLE_REG(None), 0 }, // #71 [ref=1x] + { 0 , 400, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #72 [ref=1x] + { 0 , 401, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #73 [ref=2x] + { 0 , 330, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #74 [ref=2x] + { F(Rep) , 402, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #75 [ref=1x] + { F(Vec) , 285, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #76 [ref=1x] + { 0 , 403, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #77 [ref=2x] + { 0 , 404, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #78 [ref=8x] + { 0 , 287, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #79 [ref=3x] + { 0 , 289, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #80 [ref=1x] + { 0 , 115, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #81 [ref=3x] + { 0 , 405, 1 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #82 [ref=1x] + { F(Rep)|F(RepIgnored) , 291, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #83 [ref=30x] + { F(Rep)|F(RepIgnored) , 293, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #84 [ref=1x] + { F(Rep)|F(RepIgnored) , 295, 2 , CONTROL(Jump) , SINGLE_REG(None), 0 }, // #85 [ref=1x] + { F(Vec)|F(Vex) , 406, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #86 [ref=27x] + { F(Vec)|F(Vex) , 297, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #87 [ref=1x] + { F(Vec)|F(Vex) , 299, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #88 [ref=1x] + { F(Vec)|F(Vex) , 301, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #89 [ref=1x] + { F(Vec)|F(Vex) , 303, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #90 [ref=1x] + { F(Vec)|F(Vex) , 407, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #91 [ref=12x] + { F(Vec)|F(Vex) , 408, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #92 [ref=8x] + { 0 , 409, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #93 [ref=2x] + { 0 , 305, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #94 [ref=1x] + { F(Vec) , 213, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #95 [ref=2x] + { 0 , 410, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #96 [ref=2x] + { 0 , 307, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #97 [ref=2x] + { F(Vex) , 411, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #98 [ref=2x] + { 0 , 412, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #99 [ref=1x] + { 0 , 177, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #100 [ref=3x] + { 0 , 413, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #101 [ref=5x] + { F(Vex) , 414, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #102 [ref=2x] + { F(Rep) , 415, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #103 [ref=1x] + { 0 , 293, 2 , CONTROL(Branch) , SINGLE_REG(None), 0 }, // #104 [ref=3x] + { 0 , 309, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #105 [ref=1x] + { F(Vex) , 416, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #106 [ref=2x] + { F(Vec) , 417, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #107 [ref=1x] + { F(Mmx) , 418, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #108 [ref=1x] + { 0 , 419, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #109 [ref=2x] + { F(XRelease) , 0 , 23, CONTROL(None) , SINGLE_REG(None), 0 }, // #110 [ref=1x] + { 0 , 56 , 9 , CONTROL(None) , SINGLE_REG(None), 0 }, // #111 [ref=1x] + { F(Vec) , 86 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #112 [ref=6x] + { 0 , 80 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #113 [ref=1x] + { F(Mmx)|F(Vec) , 311, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #114 [ref=1x] + { 0 , 420, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #115 [ref=1x] + { 0 , 84 , 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #116 [ref=2x] + { F(Mmx)|F(Vec) , 421, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #117 [ref=1x] + { F(Vec) , 280, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #118 [ref=2x] + { F(Vec) , 219, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #119 [ref=4x] + { F(Vec) , 422, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #120 [ref=2x] + { F(Vec) , 87 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #121 [ref=3x] + { F(Mmx) , 423, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #122 [ref=1x] + { F(Vec) , 114, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #123 [ref=1x] + { F(Vec) , 222, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #124 [ref=1x] + { F(Mmx)|F(Vec) , 110, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #125 [ref=1x] + { F(Mmx)|F(Vec) , 424, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #126 [ref=1x] + { F(Rep) , 425, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #127 [ref=1x] + { F(Vec) , 113, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #128 [ref=1x] + { F(Vec) , 313, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #129 [ref=1x] + { 0 , 315, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #130 [ref=2x] + { 0 , 317, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #131 [ref=1x] + { F(Vex) , 319, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #132 [ref=1x] + { 0 , 426, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #133 [ref=1x] + { 0 , 427, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #134 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 276, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #135 [ref=2x] + { 0 , 115, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #136 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 23 , 12, CONTROL(None) , SINGLE_REG(RO) , 0 }, // #137 [ref=1x] + { 0 , 428, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #138 [ref=1x] + { F(Rep) , 429, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #139 [ref=1x] + { F(Mmx)|F(Vec) , 321, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #140 [ref=40x] + { F(Mmx)|F(Vec) , 323, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #141 [ref=1x] + { F(Mmx)|F(Vec) , 321, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #142 [ref=6x] + { F(Mmx)|F(Vec) , 321, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #143 [ref=16x] + { F(Mmx) , 321, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #144 [ref=26x] + { F(Vec) , 86 , 1 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #145 [ref=4x] + { F(Vec) , 430, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #146 [ref=1x] + { F(Vec) , 431, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #147 [ref=1x] + { F(Vec) , 432, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #148 [ref=1x] + { F(Vec) , 433, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #149 [ref=1x] + { F(Vec) , 434, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #150 [ref=1x] + { F(Vec) , 435, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #151 [ref=1x] + { F(Mmx)|F(Vec) , 325, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #152 [ref=1x] + { F(Vec) , 436, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #153 [ref=1x] + { F(Vec) , 437, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #154 [ref=1x] + { F(Vec) , 438, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #155 [ref=1x] + { F(Mmx)|F(Vec) , 439, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #156 [ref=1x] + { F(Mmx)|F(Vec) , 440, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #157 [ref=1x] + { F(Vec) , 249, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #158 [ref=2x] + { 0 , 143, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #159 [ref=1x] + { 0 , 405, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #160 [ref=9x] + { F(Mmx) , 323, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #161 [ref=1x] + { F(Mmx)|F(Vec) , 327, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #162 [ref=8x] + { F(Vec) , 441, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #163 [ref=2x] + { 0 , 442, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #164 [ref=1x] + { 0 , 147, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #165 [ref=1x] + { 0 , 443, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #166 [ref=8x] + { 0 , 444, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #167 [ref=4x] + { 0 , 445, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #168 [ref=8x] + { 0 , 329, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #169 [ref=1x] + { F(Rep)|F(RepIgnored) , 331, 2 , CONTROL(Return) , SINGLE_REG(None), 0 }, // #170 [ref=1x] + { F(Vex) , 333, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #171 [ref=1x] + { F(Lock)|F(XAcquire)|F(XRelease) , 23 , 12, CONTROL(None) , SINGLE_REG(WO) , 0 }, // #172 [ref=3x] + { F(Rep) , 446, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #173 [ref=1x] + { 0 , 447, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #174 [ref=30x] + { 0 , 180, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #175 [ref=2x] + { 0 , 448, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #176 [ref=3x] + { F(Rep) , 449, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #177 [ref=1x] + { F(Vex) , 450, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #178 [ref=5x] + { 0 , 73 , 7 , CONTROL(None) , SINGLE_REG(None), 0 }, // #179 [ref=1x] + { F(Tsib)|F(Vex) , 451, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #180 [ref=2x] + { F(Vex) , 405, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #181 [ref=1x] + { F(Tsib)|F(Vex) , 452, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #182 [ref=1x] + { F(Vex) , 453, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #183 [ref=1x] + { 0 , 454, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #184 [ref=2x] + { 0 , 455, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #185 [ref=2x] + { 0 , 456, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #186 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 457, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #187 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512T4X)|F(Avx512KZ) , 458, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #188 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #189 [ref=22x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #190 [ref=22x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 459, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #191 [ref=18x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE) , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #192 [ref=17x] + { F(Vec)|F(Vex) , 183, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #193 [ref=15x] + { F(Vec)|F(Vex)|F(Evex) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #194 [ref=5x] + { F(Vec)|F(Vex) , 86 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #195 [ref=17x] + { F(Vec)|F(Vex) , 204, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #196 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #197 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #198 [ref=4x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #199 [ref=10x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #200 [ref=12x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #201 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #202 [ref=6x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #203 [ref=13x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #204 [ref=12x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #205 [ref=19x] + { F(Vec)|F(Vex) , 186, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #206 [ref=6x] + { F(Vec)|F(Vex) , 335, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #207 [ref=3x] + { F(Vec)|F(Vex) , 461, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #208 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 462, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #209 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 463, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #210 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 464, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #211 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 465, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #212 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 462, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #213 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 466, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #214 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 189, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #215 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 189, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #216 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 467, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #217 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 468, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #218 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 113, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #219 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 246, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #220 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 192, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #221 [ref=6x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 195, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #222 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #223 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 337, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #224 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 337, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #225 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #226 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 337, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #227 [ref=3x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 195, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #228 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 195, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #229 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 201, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #230 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 195, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #231 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #232 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #233 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #234 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #235 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #236 [ref=3x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512ER_SAE) , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #237 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #238 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 337, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #239 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #240 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 337, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #241 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #242 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 195, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #243 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #244 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #245 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512SAE) , 386, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #246 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512SAE) , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #247 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512SAE) , 388, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #248 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 195, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #249 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512ER_SAE) , 469, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #250 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #251 [ref=3x] + { F(Vec)|F(Vex) , 186, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #252 [ref=9x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 90 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #253 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 90 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #254 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #255 [ref=9x] + { F(Vec)|F(Vex) , 202, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #256 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 470, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #257 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 203, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #258 [ref=4x] + { F(Vec)|F(Vex)|F(Evex) , 392, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #259 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #260 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #261 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 471, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #262 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 472, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #263 [ref=4x] + { F(Vec)|F(Vex) , 151, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #264 [ref=13x] + { F(Vec)|F(Vex) , 339, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #265 [ref=4x] + { F(Vec)|F(Vex) , 341, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #266 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512K_B64) , 473, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #267 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512K_B32) , 473, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #268 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512K) , 474, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #269 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512K) , 475, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #270 [ref=1x] + { F(Vec)|F(Vex) , 198, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #271 [ref=7x] + { F(Vec)|F(Vex) , 113, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #272 [ref=1x] + { F(Vec)|F(Vex) , 246, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #273 [ref=1x] + { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 120, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #274 [ref=2x] + { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 125, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #275 [ref=2x] + { F(Vsib)|F(Evex)|F(Avx512K) , 476, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #276 [ref=4x] + { F(Vsib)|F(Evex)|F(Avx512K) , 477, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #277 [ref=4x] + { F(Vsib)|F(Evex)|F(Avx512K) , 478, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #278 [ref=8x] + { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 130, 5 , CONTROL(None) , SINGLE_REG(None), 0 }, // #279 [ref=2x] + { F(Vec)|F(Vsib)|F(Vex)|F(Evex)|F(Avx512K) , 155, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #280 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 459, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #281 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE) , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #282 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B64) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #283 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_SAE_B32) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #284 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #285 [ref=3x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #286 [ref=22x] + { F(Vec)|F(Vex) , 343, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #287 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 343, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #288 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 479, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #289 [ref=4x] + { F(Vec)|F(Vex)|F(Evex) , 472, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #290 [ref=1x] + { F(Vec)|F(Vex) , 213, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #291 [ref=1x] + { F(Vex) , 410, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #292 [ref=2x] + { F(Vec)|F(Vex) , 417, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #293 [ref=1x] + { F(Vec)|F(Vex) , 159, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #294 [ref=4x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #295 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #296 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_SAE) , 459, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #297 [ref=2x] + { 0 , 345, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #298 [ref=3x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 86 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #299 [ref=4x] + { F(Vec)|F(Vex)|F(Evex) , 347, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #300 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 207, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #301 [ref=1x] + { F(Vec)|F(Vex) , 86 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #302 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 86 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #303 [ref=6x] + { F(Vec)|F(Vex)|F(Evex) , 221, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #304 [ref=2x] + { F(Vec)|F(Vex)|F(Evex) , 349, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #305 [ref=4x] + { F(Vec)|F(Vex) , 480, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #306 [ref=3x] + { F(Vec)|F(Vex)|F(Evex) , 210, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #307 [ref=3x] + { F(Vec)|F(Vex)|F(Evex) , 213, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #308 [ref=1x] + { F(Vec)|F(Vex)|F(Evex) , 216, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #309 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 219, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #310 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #311 [ref=5x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 222, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #312 [ref=1x] + { 0 , 351, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #313 [ref=1x] + { 0 , 353, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #314 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512B32) , 225, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #315 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512B64) , 225, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #316 [ref=1x] + { F(Vec)|F(Vex) , 183, 2 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #317 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #318 [ref=2x] + { F(Vec)|F(Vex) , 183, 2 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #319 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #320 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #321 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #322 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 481, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #323 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 482, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #324 [ref=1x] + { F(Vec)|F(Evex) , 483, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #325 [ref=6x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 228, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #326 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 484, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #327 [ref=1x] + { F(Vec)|F(Vex)|F(Evex) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #328 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512K) , 231, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #329 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512K_B32) , 231, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #330 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512K) , 234, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #331 [ref=4x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B32) , 234, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #332 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512K_B64) , 234, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #333 [ref=2x] + { F(Vec)|F(Vex) , 430, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #334 [ref=1x] + { F(Vec)|F(Vex) , 431, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #335 [ref=1x] + { F(Vec)|F(Vex) , 432, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #336 [ref=1x] + { F(Vec)|F(Vex) , 433, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #337 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512K_B64) , 231, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #338 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #339 [ref=6x] + { F(Vec)|F(Vex)|F(Evex)|F(PreferEvex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #340 [ref=4x] + { F(Vec)|F(Vex) , 187, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #341 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 184, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #342 [ref=2x] + { F(Vec)|F(Vex) , 163, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #343 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 92 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #344 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 167, 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #345 [ref=2x] + { F(Vec)|F(Vex)|F(Evex) , 434, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #346 [ref=1x] + { F(Vec)|F(Vex)|F(Evex) , 435, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #347 [ref=1x] + { F(Vec)|F(Vex)|F(Evex) , 485, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #348 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 486, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #349 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 487, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #350 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 488, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #351 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 489, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #352 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #353 [ref=4x] + { F(Vec)|F(Vex) , 335, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #354 [ref=12x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 183, 3 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #355 [ref=8x] + { F(Vec)|F(Evex) , 490, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #356 [ref=4x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 237, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #357 [ref=6x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 240, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #358 [ref=9x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 243, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #359 [ref=3x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 246, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #360 [ref=4x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 249, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #361 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 195, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #362 [ref=6x] + { F(Vec)|F(Vex) , 151, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #363 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #364 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #365 [ref=3x] + { F(Vec)|F(Vex) , 355, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #366 [ref=4x] + { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 252, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #367 [ref=3x] + { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 357, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #368 [ref=2x] + { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 255, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #369 [ref=2x] + { F(Vec)|F(Vex) , 359, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #370 [ref=8x] + { F(Vec)|F(Evex)|F(Avx512K) , 258, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #371 [ref=5x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #372 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #373 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 98 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #374 [ref=3x] + { F(Vec)|F(Vex)|F(Evex) , 204, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #375 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 98 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #376 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 98 , 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #377 [ref=3x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 104, 6 , CONTROL(None) , SINGLE_REG(None), 0 }, // #378 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ) , 183, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #379 [ref=6x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #380 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(WO) , 0 }, // #381 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512K_B32) , 258, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #382 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512K_B64) , 258, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #383 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 459, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #384 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #385 [ref=2x] + { F(Vec)|F(Vex) , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #386 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 471, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #387 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ) , 472, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #388 [ref=1x] + { F(Vec)|F(Vex) , 204, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #389 [ref=2x] + { F(Vec)|F(Vex) , 471, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #390 [ref=1x] + { F(Vec)|F(Vex) , 472, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #391 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #392 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE_B32) , 183, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #393 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 459, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #394 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_ER_SAE) , 460, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #395 [ref=1x] + { F(Vec)|F(Vsib)|F(Evex)|F(Avx512K) , 361, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #396 [ref=1x] + { F(Vec)|F(Evex)|F(Avx512KZ_B32) , 187, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #397 [ref=2x] + { F(Vec)|F(Evex)|F(Avx512KZ_B64) , 187, 2 , CONTROL(None) , SINGLE_REG(None), 0 }, // #398 [ref=2x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B32) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #399 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_B64) , 186, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #400 [ref=1x] + { F(Vec)|F(Vex)|F(Evex)|F(Avx512KZ_ER_SAE_B64) , 198, 3 , CONTROL(None) , SINGLE_REG(None), 0 }, // #401 [ref=1x] + { F(Vec)|F(Vex) , 115, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #402 [ref=2x] + { 0 , 30 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #403 [ref=2x] + { 0 , 68 , 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #404 [ref=2x] + { F(Lock)|F(XAcquire)|F(XRelease) , 65 , 4 , CONTROL(None) , SINGLE_REG(None), 0 }, // #405 [ref=1x] + { 0 , 491, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #406 [ref=1x] + { F(Lock)|F(XAcquire) , 65 , 8 , CONTROL(None) , SINGLE_REG(RO) , 0 }, // #407 [ref=1x] + { 0 , 492, 1 , CONTROL(None) , SINGLE_REG(None), 0 }, // #408 [ref=6x] + { 0 , 493, 1 , CONTROL(None) , SINGLE_REG(None), 0 } // #409 [ref=6x] }; #undef SINGLE_REG #undef CONTROL @@ -2469,7 +2472,7 @@ const InstDB::CommonInfo InstDB::_commonInfoTable[] = { // ------------------- Automatically generated, do not edit ------------------- #define EXT(VAL) uint32_t(Features::k##VAL) const InstDB::CommonInfoTableB InstDB::_commonInfoTableB[] = { - { { 0 }, 0, 0 }, // #0 [ref=146x] + { { 0 }, 0, 0 }, // #0 [ref=147x] { { 0 }, 1, 0 }, // #1 [ref=32x] { { 0 }, 2, 0 }, // #2 [ref=2x] { { EXT(ADX) }, 3, 0 }, // #3 [ref=1x] @@ -2621,7 +2624,7 @@ const InstDB::CommonInfoTableB InstDB::_commonInfoTableB[] = { { { EXT(AVX), EXT(AVX512_F), EXT(AVX512_VL), EXT(PCLMULQDQ), EXT(VPCLMULQDQ) }, 0, 0 }, // #149 [ref=1x] { { EXT(AVX) }, 1, 0 }, // #150 [ref=7x] { { EXT(AVX512_VBMI2), EXT(AVX512_VL) }, 0, 0 }, // #151 [ref=16x] - { { EXT(AVX512_VL), EXT(AVX512_VNNI) }, 0, 0 }, // #152 [ref=4x] + { { EXT(AVX512_VL), EXT(AVX512_VNNI), EXT(AVX_VNNI) }, 0, 0 }, // #152 [ref=4x] { { EXT(AVX512_VBMI), EXT(AVX512_VL) }, 0, 0 }, // #153 [ref=4x] { { EXT(AVX), EXT(AVX512_BW) }, 0, 0 }, // #154 [ref=4x] { { EXT(AVX), EXT(AVX512_DQ) }, 0, 0 }, // #155 [ref=4x] @@ -2641,7 +2644,7 @@ const InstDB::CommonInfoTableB InstDB::_commonInfoTableB[] = { #define FLAG(VAL) uint32_t(Status::k##VAL) const InstDB::RWFlagsInfoTable InstDB::_rwFlagsInfoTable[] = { - { 0, 0 }, // #0 [ref=1315x] + { 0, 0 }, // #0 [ref=1316x] { 0, FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #1 [ref=83x] { FLAG(CF), FLAG(AF) | FLAG(CF) | FLAG(OF) | FLAG(PF) | FLAG(SF) | FLAG(ZF) }, // #2 [ref=2x] { FLAG(CF), FLAG(CF) }, // #3 [ref=2x] @@ -2711,15 +2714,15 @@ const char InstDB::_nameData[] = "ktestq\0" "ktestw\0" "kunpckbw\0" "kunpckdq\0" "kunpckwd\0" "kxnorb\0" "kxnord\0" "kxnorq\0" "kxnorw\0" "kxorb\0" "kxord\0" "kxorq\0" "kxorw\0" "lahf\0" "lar\0" "lds\0" "ldtilecfg\0" "lea\0" "leave\0" "les\0" "lfence\0" "lfs\0" "lgdt\0" "lgs\0" "lidt\0" "lldt\0" "llwpcb\0" "lmsw\0" "lods\0" "loop\0" "loope\0" "loopne\0" "lsl\0" "ltr\0" - "lwpins\0" "lwpval\0" "lzcnt\0" "mcommit\0" "mfence\0" "monitorx\0" "movdir64b\0" "movdiri\0" "movdq2q\0" "movnti\0" - "movntq\0" "movntsd\0" "movntss\0" "movq2dq\0" "movsx\0" "movsxd\0" "movzx\0" "mulx\0" "mwaitx\0" "neg\0" "not\0" - "out\0" "outs\0" "pavgusb\0" "pconfig\0" "pdep\0" "pext\0" "pf2id\0" "pf2iw\0" "pfacc\0" "pfadd\0" "pfcmpeq\0" - "pfcmpge\0" "pfcmpgt\0" "pfmax\0" "pfmin\0" "pfmul\0" "pfnacc\0" "pfpnacc\0" "pfrcp\0" "pfrcpit1\0" "pfrcpit2\0" - "pfrcpv\0" "pfrsqit1\0" "pfrsqrt\0" "pfrsqrtv\0" "pfsub\0" "pfsubr\0" "pi2fd\0" "pi2fw\0" "pmulhrw\0" "pop\0" - "popa\0" "popad\0" "popcnt\0" "popf\0" "popfd\0" "popfq\0" "prefetch\0" "prefetchnta\0" "prefetcht0\0" "prefetcht1\0" - "prefetcht2\0" "prefetchw\0" "prefetchwt1\0" "pshufw\0" "psmash\0" "pswapd\0" "ptwrite\0" "push\0" "pusha\0" - "pushad\0" "pushf\0" "pushfd\0" "pushfq\0" "pvalidate\0" "rcl\0" "rcr\0" "rdfsbase\0" "rdgsbase\0" "rdmsr\0" - "rdpid\0" "rdpkru\0" "rdpmc\0" "rdpru\0" "rdrand\0" "rdseed\0" "rdsspd\0" "rdsspq\0" "rdtsc\0" "rdtscp\0" + "lwpins\0" "lwpval\0" "lzcnt\0" "mcommit\0" "mfence\0" "monitorx\0" "movabs\0" "movdir64b\0" "movdiri\0" "movdq2q\0" + "movnti\0" "movntq\0" "movntsd\0" "movntss\0" "movq2dq\0" "movsx\0" "movsxd\0" "movzx\0" "mulx\0" "mwaitx\0" "neg\0" + "not\0" "out\0" "outs\0" "pavgusb\0" "pconfig\0" "pdep\0" "pext\0" "pf2id\0" "pf2iw\0" "pfacc\0" "pfadd\0" + "pfcmpeq\0" "pfcmpge\0" "pfcmpgt\0" "pfmax\0" "pfmin\0" "pfmul\0" "pfnacc\0" "pfpnacc\0" "pfrcp\0" "pfrcpit1\0" + "pfrcpit2\0" "pfrcpv\0" "pfrsqit1\0" "pfrsqrt\0" "pfrsqrtv\0" "pfsub\0" "pfsubr\0" "pi2fd\0" "pi2fw\0" "pmulhrw\0" + "pop\0" "popa\0" "popad\0" "popcnt\0" "popf\0" "popfd\0" "popfq\0" "prefetch\0" "prefetchnta\0" "prefetcht0\0" + "prefetcht1\0" "prefetcht2\0" "prefetchw\0" "prefetchwt1\0" "pshufw\0" "psmash\0" "pswapd\0" "ptwrite\0" "push\0" + "pusha\0" "pushad\0" "pushf\0" "pushfd\0" "pushfq\0" "pvalidate\0" "rcl\0" "rcr\0" "rdfsbase\0" "rdgsbase\0" + "rdmsr\0" "rdpid\0" "rdpkru\0" "rdpmc\0" "rdpru\0" "rdrand\0" "rdseed\0" "rdsspd\0" "rdsspq\0" "rdtsc\0" "rdtscp\0" "rmpadjust\0" "rmpupdate\0" "rol\0" "ror\0" "rorx\0" "rsm\0" "rstorssp\0" "sahf\0" "sal\0" "sar\0" "sarx\0" "saveprevssp\0" "sbb\0" "scas\0" "serialize\0" "seta\0" "setae\0" "setb\0" "setbe\0" "setc\0" "sete\0" "setg\0" "setge\0" "setl\0" "setle\0" "setna\0" "setnae\0" "setnb\0" "setnbe\0" "setnc\0" "setne\0" "setng\0" "setnge\0" @@ -2879,475 +2882,491 @@ const InstDB::InstSignature InstDB::_instSignatureTable[] = { ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32} ROW(2, 0, 1, 0, 15 , 16 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, i32} ROW(2, 0, 1, 0, 8 , 17 , 0 , 0 , 0 , 0 ), // {r64, i64|u64|m64|mem|sreg|creg|dreg} - ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} - ROW(2, 1, 1, 0, 4 , 19 , 0 , 0 , 0 , 0 ), // {r16, m16|mem|sreg} - ROW(2, 1, 1, 0, 6 , 20 , 0 , 0 , 0 , 0 ), // {r32, m32|mem|sreg} - ROW(2, 1, 1, 0, 21 , 22 , 0 , 0 , 0 , 0 ), // {m16|mem, sreg} - ROW(2, 1, 1, 0, 22 , 21 , 0 , 0 , 0 , 0 ), // {sreg, m16|mem} - ROW(2, 1, 0, 0, 6 , 23 , 0 , 0 , 0 , 0 ), // {r32, creg|dreg} - ROW(2, 1, 0, 0, 23 , 6 , 0 , 0 , 0 , 0 ), // {creg|dreg, r32} - ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // #16 {r8lo|r8hi|m8, i8|u8} + ROW(2, 1, 1, 0, 18 , 19 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|al, m8|mem} + ROW(2, 1, 1, 0, 4 , 20 , 0 , 0 , 0 , 0 ), // {r16, m16|mem|sreg} + ROW(2, 1, 1, 0, 6 , 21 , 0 , 0 , 0 , 0 ), // {r32, m32|mem|sreg} + ROW(2, 1, 1, 0, 22 , 23 , 0 , 0 , 0 , 0 ), // {m16|mem, sreg} + ROW(2, 1, 1, 0, 23 , 22 , 0 , 0 , 0 , 0 ), // {sreg, m16|mem} + ROW(2, 1, 1, 0, 24 , 22 , 0 , 0 , 0 , 0 ), // {ax, m16|mem} + ROW(2, 1, 1, 0, 25 , 26 , 0 , 0 , 0 , 0 ), // {eax, m32|mem} + ROW(2, 0, 1, 0, 27 , 28 , 0 , 0 , 0 , 0 ), // {rax, m64|mem} + ROW(2, 1, 1, 0, 19 , 29 , 0 , 0 , 0 , 0 ), // {m8|mem, al} + ROW(2, 1, 1, 0, 22 , 24 , 0 , 0 , 0 , 0 ), // {m16|mem, ax} + ROW(2, 1, 1, 0, 26 , 25 , 0 , 0 , 0 , 0 ), // {m32|mem, eax} + ROW(2, 0, 1, 0, 28 , 27 , 0 , 0 , 0 , 0 ), // {m64|mem, rax} + ROW(2, 1, 0, 0, 6 , 30 , 0 , 0 , 0 , 0 ), // {r32, creg|dreg} + ROW(2, 1, 0, 0, 30 , 6 , 0 , 0 , 0 , 0 ), // {creg|dreg, r32} + ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // #23 {r8lo|r8hi|m8, i8|u8} ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16} ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32} - ROW(2, 0, 1, 0, 15 , 24 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, i32|r64} - ROW(2, 1, 1, 0, 25 , 26 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32|r64|m64|mem, i8} + ROW(2, 0, 1, 0, 15 , 31 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, i32|r64} + ROW(2, 1, 1, 0, 32 , 33 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32|r64|m64|mem, i8} ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8|mem, r8lo|r8hi} - ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // #23 {r32|m32|mem, r32} - ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} - ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} - ROW(2, 1, 1, 0, 6 , 29 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} - ROW(2, 0, 1, 0, 8 , 30 , 0 , 0 , 0 , 0 ), // {r64, m64|mem} - ROW(2, 1, 1, 0, 31 , 10 , 0 , 0 , 0 , 0 ), // #28 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, i8|u8} + ROW(2, 1, 1, 0, 34 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 35 , 6 , 0 , 0 , 0 , 0 ), // #30 {r32|m32|mem, r32} + ROW(2, 1, 1, 0, 2 , 19 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} + ROW(2, 1, 1, 0, 4 , 22 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} + ROW(2, 1, 1, 0, 6 , 26 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} + ROW(2, 0, 1, 0, 8 , 28 , 0 , 0 , 0 , 0 ), // {r64, m64|mem} + ROW(2, 1, 1, 0, 36 , 10 , 0 , 0 , 0 , 0 ), // #35 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, i8|u8} ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16} ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32} - ROW(2, 0, 1, 0, 8 , 32 , 0 , 0 , 0 , 0 ), // {r64, u32|i32|r64|m64|mem} - ROW(2, 0, 1, 0, 30 , 24 , 0 , 0 , 0 , 0 ), // {m64|mem, i32|r64} + ROW(2, 0, 1, 0, 8 , 37 , 0 , 0 , 0 , 0 ), // {r64, u32|i32|r64|m64|mem} + ROW(2, 0, 1, 0, 28 , 31 , 0 , 0 , 0 , 0 ), // {m64|mem, i32|r64} ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8|mem, r8lo|r8hi} - ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} - ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} - ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} - ROW(2, 1, 1, 0, 6 , 29 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} - ROW(2, 1, 1, 1, 33 , 1 , 0 , 0 , 0 , 0 ), // #39 {, r8lo|r8hi|m8|mem} - ROW(3, 1, 1, 2, 34 , 33 , 27 , 0 , 0 , 0 ), // {, , r16|m16|mem} - ROW(3, 1, 1, 2, 35 , 36 , 28 , 0 , 0 , 0 ), // {, , r32|m32|mem} - ROW(3, 0, 1, 2, 37 , 38 , 15 , 0 , 0 , 0 ), // {, , r64|m64|mem} - ROW(2, 1, 1, 0, 4 , 39 , 0 , 0 , 0 , 0 ), // {r16, r16|m16|mem|i8|i16} - ROW(2, 1, 1, 0, 6 , 40 , 0 , 0 , 0 , 0 ), // {r32, r32|m32|mem|i8|i32} - ROW(2, 0, 1, 0, 8 , 41 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem|i8|i32} - ROW(3, 1, 1, 0, 4 , 27 , 42 , 0 , 0 , 0 ), // {r16, r16|m16|mem, i8|i16|u16} - ROW(3, 1, 1, 0, 6 , 28 , 43 , 0 , 0 , 0 ), // {r32, r32|m32|mem, i8|i32|u32} - ROW(3, 0, 1, 0, 8 , 15 , 44 , 0 , 0 , 0 ), // {r64, r64|m64|mem, i8|i32} - ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // #49 {r8lo|r8hi|m8|mem, r8lo|r8hi} - ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} - ROW(2, 0, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // #52 {r64|m64|mem, r64} - ROW(2, 1, 1, 0, 2 , 18 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} - ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} - ROW(2, 1, 1, 0, 6 , 29 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} - ROW(2, 0, 1, 0, 8 , 30 , 0 , 0 , 0 , 0 ), // {r64, m64|mem} - ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // #57 {r8lo|r8hi|m8, i8|u8} + ROW(2, 1, 1, 0, 34 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 35 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 1, 1, 0, 2 , 19 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} + ROW(2, 1, 1, 0, 4 , 22 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} + ROW(2, 1, 1, 0, 6 , 26 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} + ROW(2, 1, 1, 1, 38 , 1 , 0 , 0 , 0 , 0 ), // #46 {, r8lo|r8hi|m8|mem} + ROW(3, 1, 1, 2, 39 , 38 , 34 , 0 , 0 , 0 ), // {, , r16|m16|mem} + ROW(3, 1, 1, 2, 40 , 41 , 35 , 0 , 0 , 0 ), // {, , r32|m32|mem} + ROW(3, 0, 1, 2, 42 , 43 , 15 , 0 , 0 , 0 ), // {, , r64|m64|mem} + ROW(2, 1, 1, 0, 4 , 44 , 0 , 0 , 0 , 0 ), // {r16, r16|m16|mem|i8|i16} + ROW(2, 1, 1, 0, 6 , 45 , 0 , 0 , 0 , 0 ), // {r32, r32|m32|mem|i8|i32} + ROW(2, 0, 1, 0, 8 , 46 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem|i8|i32} + ROW(3, 1, 1, 0, 4 , 34 , 47 , 0 , 0 , 0 ), // {r16, r16|m16|mem, i8|i16|u16} + ROW(3, 1, 1, 0, 6 , 35 , 48 , 0 , 0 , 0 ), // {r32, r32|m32|mem, i8|i32|u32} + ROW(3, 0, 1, 0, 8 , 15 , 49 , 0 , 0 , 0 ), // {r64, r64|m64|mem, i8|i32} + ROW(2, 0, 1, 0, 8 , 50 , 0 , 0 , 0 , 0 ), // #56 {r64, i64|u64} + ROW(2, 0, 1, 0, 29 , 19 , 0 , 0 , 0 , 0 ), // {al, m8|mem} + ROW(2, 0, 1, 0, 24 , 22 , 0 , 0 , 0 , 0 ), // {ax, m16|mem} + ROW(2, 0, 1, 0, 25 , 26 , 0 , 0 , 0 , 0 ), // {eax, m32|mem} + ROW(2, 0, 1, 0, 27 , 28 , 0 , 0 , 0 , 0 ), // {rax, m64|mem} + ROW(2, 0, 1, 0, 19 , 29 , 0 , 0 , 0 , 0 ), // {m8|mem, al} + ROW(2, 0, 1, 0, 22 , 24 , 0 , 0 , 0 , 0 ), // {m16|mem, ax} + ROW(2, 0, 1, 0, 26 , 25 , 0 , 0 , 0 , 0 ), // {m32|mem, eax} + ROW(2, 0, 1, 0, 28 , 27 , 0 , 0 , 0 , 0 ), // {m64|mem, rax} + ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // #65 {r8lo|r8hi|m8|mem, r8lo|r8hi} + ROW(2, 1, 1, 0, 34 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 35 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 0, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // #68 {r64|m64|mem, r64} + ROW(2, 1, 1, 0, 2 , 19 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi, m8|mem} + ROW(2, 1, 1, 0, 4 , 22 , 0 , 0 , 0 , 0 ), // {r16, m16|mem} + ROW(2, 1, 1, 0, 6 , 26 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} + ROW(2, 0, 1, 0, 8 , 28 , 0 , 0 , 0 , 0 ), // {r64, m64|mem} + ROW(2, 1, 1, 0, 9 , 10 , 0 , 0 , 0 , 0 ), // #73 {r8lo|r8hi|m8, i8|u8} ROW(2, 1, 1, 0, 11 , 12 , 0 , 0 , 0 , 0 ), // {r16|m16, i16|u16} ROW(2, 1, 1, 0, 13 , 14 , 0 , 0 , 0 , 0 ), // {r32|m32, i32|u32} - ROW(2, 0, 1, 0, 15 , 24 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, i32|r64} + ROW(2, 0, 1, 0, 15 , 31 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, i32|r64} ROW(2, 1, 1, 0, 1 , 2 , 0 , 0 , 0 , 0 ), // {r8lo|r8hi|m8|mem, r8lo|r8hi} - ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} - ROW(2, 1, 1, 0, 4 , 21 , 0 , 0 , 0 , 0 ), // #64 {r16, m16|mem} - ROW(2, 1, 1, 0, 6 , 29 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} - ROW(2, 0, 1, 0, 8 , 30 , 0 , 0 , 0 , 0 ), // {r64, m64|mem} - ROW(2, 1, 1, 0, 21 , 4 , 0 , 0 , 0 , 0 ), // {m16|mem, r16} - ROW(2, 1, 1, 0, 29 , 6 , 0 , 0 , 0 , 0 ), // #68 {m32|mem, r32} - ROW(2, 0, 1, 0, 30 , 8 , 0 , 0 , 0 , 0 ), // {m64|mem, r64} - ROW(2, 1, 1, 0, 45 , 46 , 0 , 0 , 0 , 0 ), // #70 {xmm, xmm|m128|mem} - ROW(2, 1, 1, 0, 47 , 45 , 0 , 0 , 0 , 0 ), // #71 {m128|mem, xmm} - ROW(2, 1, 1, 0, 48 , 49 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} - ROW(2, 1, 1, 0, 50 , 48 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} - ROW(2, 1, 1, 0, 51 , 52 , 0 , 0 , 0 , 0 ), // #74 {zmm, zmm|m512|mem} - ROW(2, 1, 1, 0, 53 , 51 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm} - ROW(3, 1, 1, 0, 45 , 45 , 54 , 0 , 0 , 0 ), // #76 {xmm, xmm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 45 , 47 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} - ROW(3, 1, 1, 0, 48 , 48 , 55 , 0 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem|i8|u8} - ROW(3, 1, 1, 0, 48 , 50 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} - ROW(3, 1, 1, 0, 51 , 51 , 56 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem|i8|u8} - ROW(3, 1, 1, 0, 51 , 53 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} - ROW(3, 1, 1, 0, 45 , 45 , 54 , 0 , 0 , 0 ), // #82 {xmm, xmm, i8|u8|xmm|m128|mem} - ROW(3, 1, 1, 0, 48 , 48 , 54 , 0 , 0 , 0 ), // {ymm, ymm, i8|u8|xmm|m128|mem} - ROW(3, 1, 1, 0, 45 , 47 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} - ROW(3, 1, 1, 0, 48 , 50 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} - ROW(3, 1, 1, 0, 51 , 51 , 54 , 0 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 51 , 53 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} - ROW(3, 1, 1, 0, 45 , 45 , 54 , 0 , 0 , 0 ), // #88 {xmm, xmm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 45 , 47 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} - ROW(3, 1, 1, 0, 48 , 48 , 54 , 0 , 0 , 0 ), // {ymm, ymm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 48 , 50 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} - ROW(3, 1, 1, 0, 51 , 51 , 54 , 0 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 51 , 53 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} - ROW(2, 1, 1, 0, 57 , 58 , 0 , 0 , 0 , 0 ), // #94 {mm, mm|m64|mem|r64} - ROW(2, 1, 1, 0, 15 , 59 , 0 , 0 , 0 , 0 ), // {m64|mem|r64, mm|xmm} - ROW(2, 0, 1, 0, 45 , 15 , 0 , 0 , 0 , 0 ), // {xmm, r64|m64|mem} - ROW(2, 1, 1, 0, 45 , 60 , 0 , 0 , 0 , 0 ), // #97 {xmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 30 , 45 , 0 , 0 , 0 , 0 ), // #98 {m64|mem, xmm} - ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #99 {} - ROW(1, 1, 1, 0, 61 , 0 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32|r64|m64} - ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 1, 1, 0, 34 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 35 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(2, 1, 1, 0, 4 , 22 , 0 , 0 , 0 , 0 ), // #80 {r16, m16|mem} + ROW(2, 1, 1, 0, 6 , 26 , 0 , 0 , 0 , 0 ), // {r32, m32|mem} + ROW(2, 0, 1, 0, 8 , 28 , 0 , 0 , 0 , 0 ), // {r64, m64|mem} + ROW(2, 1, 1, 0, 22 , 4 , 0 , 0 , 0 , 0 ), // {m16|mem, r16} + ROW(2, 1, 1, 0, 26 , 6 , 0 , 0 , 0 , 0 ), // #84 {m32|mem, r32} + ROW(2, 0, 1, 0, 28 , 8 , 0 , 0 , 0 , 0 ), // {m64|mem, r64} + ROW(2, 1, 1, 0, 51 , 52 , 0 , 0 , 0 , 0 ), // #86 {xmm, xmm|m128|mem} + ROW(2, 1, 1, 0, 53 , 51 , 0 , 0 , 0 , 0 ), // #87 {m128|mem, xmm} + ROW(2, 1, 1, 0, 54 , 55 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} + ROW(2, 1, 1, 0, 56 , 54 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} + ROW(2, 1, 1, 0, 57 , 58 , 0 , 0 , 0 , 0 ), // #90 {zmm, zmm|m512|mem} + ROW(2, 1, 1, 0, 59 , 57 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm} + ROW(3, 1, 1, 0, 51 , 51 , 60 , 0 , 0 , 0 ), // #92 {xmm, xmm, xmm|m128|mem|i8|u8} + ROW(3, 1, 1, 0, 51 , 53 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} + ROW(3, 1, 1, 0, 54 , 54 , 61 , 0 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem|i8|u8} + ROW(3, 1, 1, 0, 54 , 56 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} + ROW(3, 1, 1, 0, 57 , 57 , 62 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem|i8|u8} + ROW(3, 1, 1, 0, 57 , 59 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} + ROW(3, 1, 1, 0, 51 , 51 , 60 , 0 , 0 , 0 ), // #98 {xmm, xmm, i8|u8|xmm|m128|mem} + ROW(3, 1, 1, 0, 54 , 54 , 60 , 0 , 0 , 0 ), // {ymm, ymm, i8|u8|xmm|m128|mem} + ROW(3, 1, 1, 0, 51 , 53 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} + ROW(3, 1, 1, 0, 54 , 56 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} + ROW(3, 1, 1, 0, 57 , 57 , 60 , 0 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem|i8|u8} + ROW(3, 1, 1, 0, 57 , 59 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} + ROW(3, 1, 1, 0, 51 , 51 , 60 , 0 , 0 , 0 ), // #104 {xmm, xmm, xmm|m128|mem|i8|u8} + ROW(3, 1, 1, 0, 51 , 53 , 10 , 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8} + ROW(3, 1, 1, 0, 54 , 54 , 60 , 0 , 0 , 0 ), // {ymm, ymm, xmm|m128|mem|i8|u8} + ROW(3, 1, 1, 0, 54 , 56 , 10 , 0 , 0 , 0 ), // {ymm, m256|mem, i8|u8} + ROW(3, 1, 1, 0, 57 , 57 , 60 , 0 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem|i8|u8} + ROW(3, 1, 1, 0, 57 , 59 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} + ROW(2, 1, 1, 0, 63 , 64 , 0 , 0 , 0 , 0 ), // #110 {mm, mm|m64|mem|r64} + ROW(2, 1, 1, 0, 15 , 65 , 0 , 0 , 0 , 0 ), // {m64|mem|r64, mm|xmm} + ROW(2, 0, 1, 0, 51 , 15 , 0 , 0 , 0 , 0 ), // {xmm, r64|m64|mem} + ROW(2, 1, 1, 0, 51 , 66 , 0 , 0 , 0 , 0 ), // #113 {xmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 28 , 51 , 0 , 0 , 0 , 0 ), // #114 {m64|mem, xmm} + ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #115 {} + ROW(1, 1, 1, 0, 67 , 0 , 0 , 0 , 0 , 0 ), // {r16|m16|r32|m32|r64|m64} + ROW(2, 1, 1, 0, 34 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 35 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} ROW(2, 1, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} - ROW(3, 1, 1, 0, 45 , 62 , 45 , 0 , 0 , 0 ), // #104 {xmm, vm32x, xmm} - ROW(3, 1, 1, 0, 48 , 62 , 48 , 0 , 0 , 0 ), // {ymm, vm32x, ymm} - ROW(2, 1, 1, 0, 45 , 62 , 0 , 0 , 0 , 0 ), // {xmm, vm32x} - ROW(2, 1, 1, 0, 48 , 63 , 0 , 0 , 0 , 0 ), // {ymm, vm32y} - ROW(2, 1, 1, 0, 51 , 64 , 0 , 0 , 0 , 0 ), // {zmm, vm32z} - ROW(3, 1, 1, 0, 45 , 62 , 45 , 0 , 0 , 0 ), // #109 {xmm, vm32x, xmm} - ROW(3, 1, 1, 0, 48 , 63 , 48 , 0 , 0 , 0 ), // {ymm, vm32y, ymm} - ROW(2, 1, 1, 0, 45 , 62 , 0 , 0 , 0 , 0 ), // {xmm, vm32x} - ROW(2, 1, 1, 0, 48 , 63 , 0 , 0 , 0 , 0 ), // {ymm, vm32y} - ROW(2, 1, 1, 0, 51 , 64 , 0 , 0 , 0 , 0 ), // {zmm, vm32z} - ROW(3, 1, 1, 0, 45 , 65 , 45 , 0 , 0 , 0 ), // #114 {xmm, vm64x, xmm} - ROW(3, 1, 1, 0, 48 , 66 , 48 , 0 , 0 , 0 ), // {ymm, vm64y, ymm} - ROW(2, 1, 1, 0, 45 , 65 , 0 , 0 , 0 , 0 ), // {xmm, vm64x} - ROW(2, 1, 1, 0, 48 , 66 , 0 , 0 , 0 , 0 ), // {ymm, vm64y} - ROW(2, 1, 1, 0, 51 , 67 , 0 , 0 , 0 , 0 ), // {zmm, vm64z} - ROW(2, 1, 1, 0, 25 , 10 , 0 , 0 , 0 , 0 ), // #119 {r16|m16|r32|m32|r64|m64|mem, i8|u8} - ROW(2, 1, 1, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} - ROW(2, 1, 1, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} + ROW(3, 1, 1, 0, 51 , 68 , 51 , 0 , 0 , 0 ), // #120 {xmm, vm32x, xmm} + ROW(3, 1, 1, 0, 54 , 68 , 54 , 0 , 0 , 0 ), // {ymm, vm32x, ymm} + ROW(2, 1, 1, 0, 51 , 68 , 0 , 0 , 0 , 0 ), // {xmm, vm32x} + ROW(2, 1, 1, 0, 54 , 69 , 0 , 0 , 0 , 0 ), // {ymm, vm32y} + ROW(2, 1, 1, 0, 57 , 70 , 0 , 0 , 0 , 0 ), // {zmm, vm32z} + ROW(3, 1, 1, 0, 51 , 68 , 51 , 0 , 0 , 0 ), // #125 {xmm, vm32x, xmm} + ROW(3, 1, 1, 0, 54 , 69 , 54 , 0 , 0 , 0 ), // {ymm, vm32y, ymm} + ROW(2, 1, 1, 0, 51 , 68 , 0 , 0 , 0 , 0 ), // {xmm, vm32x} + ROW(2, 1, 1, 0, 54 , 69 , 0 , 0 , 0 , 0 ), // {ymm, vm32y} + ROW(2, 1, 1, 0, 57 , 70 , 0 , 0 , 0 , 0 ), // {zmm, vm32z} + ROW(3, 1, 1, 0, 51 , 71 , 51 , 0 , 0 , 0 ), // #130 {xmm, vm64x, xmm} + ROW(3, 1, 1, 0, 54 , 72 , 54 , 0 , 0 , 0 ), // {ymm, vm64y, ymm} + ROW(2, 1, 1, 0, 51 , 71 , 0 , 0 , 0 , 0 ), // {xmm, vm64x} + ROW(2, 1, 1, 0, 54 , 72 , 0 , 0 , 0 , 0 ), // {ymm, vm64y} + ROW(2, 1, 1, 0, 57 , 73 , 0 , 0 , 0 , 0 ), // {zmm, vm64z} + ROW(2, 1, 1, 0, 32 , 10 , 0 , 0 , 0 , 0 ), // #135 {r16|m16|r32|m32|r64|m64|mem, i8|u8} + ROW(2, 1, 1, 0, 34 , 4 , 0 , 0 , 0 , 0 ), // {r16|m16|mem, r16} + ROW(2, 1, 1, 0, 35 , 6 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, r32} ROW(2, 0, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} - ROW(3, 1, 1, 1, 1 , 2 , 68 , 0 , 0 , 0 ), // #123 {r8lo|r8hi|m8|mem, r8lo|r8hi, } - ROW(3, 1, 1, 1, 27 , 4 , 33 , 0 , 0 , 0 ), // {r16|m16|mem, r16, } - ROW(3, 1, 1, 1, 28 , 6 , 36 , 0 , 0 , 0 ), // {r32|m32|mem, r32, } - ROW(3, 0, 1, 1, 15 , 8 , 38 , 0 , 0 , 0 ), // {r64|m64|mem, r64, } - ROW(1, 1, 1, 0, 69 , 0 , 0 , 0 , 0 , 0 ), // #127 {r16|m16|r64|m64} + ROW(3, 1, 1, 1, 1 , 2 , 74 , 0 , 0 , 0 ), // #139 {r8lo|r8hi|m8|mem, r8lo|r8hi, } + ROW(3, 1, 1, 1, 34 , 4 , 38 , 0 , 0 , 0 ), // {r16|m16|mem, r16, } + ROW(3, 1, 1, 1, 35 , 6 , 41 , 0 , 0 , 0 ), // {r32|m32|mem, r32, } + ROW(3, 0, 1, 1, 15 , 8 , 43 , 0 , 0 , 0 ), // {r64|m64|mem, r64, } + ROW(1, 1, 1, 0, 75 , 0 , 0 , 0 , 0 , 0 ), // #143 {r16|m16|r64|m64} ROW(1, 1, 0, 0, 13 , 0 , 0 , 0 , 0 , 0 ), // {r32|m32} - ROW(1, 1, 0, 0, 70 , 0 , 0 , 0 , 0 , 0 ), // {ds|es|ss} - ROW(1, 1, 1, 0, 71 , 0 , 0 , 0 , 0 , 0 ), // {fs|gs} - ROW(1, 1, 1, 0, 72 , 0 , 0 , 0 , 0 , 0 ), // #131 {r16|m16|r64|m64|i8|i16|i32} - ROW(1, 1, 0, 0, 73 , 0 , 0 , 0 , 0 , 0 ), // {r32|m32|i32|u32} - ROW(1, 1, 0, 0, 74 , 0 , 0 , 0 , 0 , 0 ), // {cs|ss|ds|es} - ROW(1, 1, 1, 0, 71 , 0 , 0 , 0 , 0 , 0 ), // {fs|gs} - ROW(4, 1, 1, 0, 45 , 45 , 45 , 46 , 0 , 0 ), // #135 {xmm, xmm, xmm, xmm|m128|mem} - ROW(4, 1, 1, 0, 45 , 45 , 47 , 45 , 0 , 0 ), // {xmm, xmm, m128|mem, xmm} - ROW(4, 1, 1, 0, 48 , 48 , 48 , 49 , 0 , 0 ), // {ymm, ymm, ymm, ymm|m256|mem} - ROW(4, 1, 1, 0, 48 , 48 , 50 , 48 , 0 , 0 ), // {ymm, ymm, m256|mem, ymm} - ROW(3, 1, 1, 0, 45 , 75 , 45 , 0 , 0 , 0 ), // #139 {xmm, vm64x|vm64y, xmm} - ROW(2, 1, 1, 0, 45 , 65 , 0 , 0 , 0 , 0 ), // {xmm, vm64x} - ROW(2, 1, 1, 0, 48 , 66 , 0 , 0 , 0 , 0 ), // {ymm, vm64y} - ROW(2, 1, 1, 0, 51 , 67 , 0 , 0 , 0 , 0 ), // {zmm, vm64z} - ROW(3, 1, 1, 0, 47 , 45 , 45 , 0 , 0 , 0 ), // #143 {m128|mem, xmm, xmm} - ROW(3, 1, 1, 0, 50 , 48 , 48 , 0 , 0 , 0 ), // {m256|mem, ymm, ymm} - ROW(3, 1, 1, 0, 45 , 45 , 47 , 0 , 0 , 0 ), // {xmm, xmm, m128|mem} - ROW(3, 1, 1, 0, 48 , 48 , 50 , 0 , 0 , 0 ), // {ymm, ymm, m256|mem} - ROW(5, 1, 1, 0, 45 , 45 , 46 , 45 , 76 , 0 ), // #147 {xmm, xmm, xmm|m128|mem, xmm, i4|u4} - ROW(5, 1, 1, 0, 45 , 45 , 45 , 47 , 76 , 0 ), // {xmm, xmm, xmm, m128|mem, i4|u4} - ROW(5, 1, 1, 0, 48 , 48 , 49 , 48 , 76 , 0 ), // {ymm, ymm, ymm|m256|mem, ymm, i4|u4} - ROW(5, 1, 1, 0, 48 , 48 , 48 , 50 , 76 , 0 ), // {ymm, ymm, ymm, m256|mem, i4|u4} - ROW(3, 1, 1, 0, 48 , 49 , 10 , 0 , 0 , 0 ), // #151 {ymm, ymm|m256|mem, i8|u8} - ROW(3, 1, 1, 0, 48 , 48 , 49 , 0 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem} - ROW(3, 1, 1, 0, 51 , 51 , 56 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem|i8|u8} - ROW(3, 1, 1, 0, 51 , 53 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} - ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #155 {r16, r16|m16|mem} - ROW(2, 1, 1, 0, 6 , 28 , 0 , 0 , 0 , 0 ), // #156 {r32, r32|m32|mem} + ROW(1, 1, 0, 0, 76 , 0 , 0 , 0 , 0 , 0 ), // {ds|es|ss} + ROW(1, 1, 1, 0, 77 , 0 , 0 , 0 , 0 , 0 ), // {fs|gs} + ROW(1, 1, 1, 0, 78 , 0 , 0 , 0 , 0 , 0 ), // #147 {r16|m16|r64|m64|i8|i16|i32} + ROW(1, 1, 0, 0, 79 , 0 , 0 , 0 , 0 , 0 ), // {r32|m32|i32|u32} + ROW(1, 1, 0, 0, 80 , 0 , 0 , 0 , 0 , 0 ), // {cs|ss|ds|es} + ROW(1, 1, 1, 0, 77 , 0 , 0 , 0 , 0 , 0 ), // {fs|gs} + ROW(4, 1, 1, 0, 51 , 51 , 51 , 52 , 0 , 0 ), // #151 {xmm, xmm, xmm, xmm|m128|mem} + ROW(4, 1, 1, 0, 51 , 51 , 53 , 51 , 0 , 0 ), // {xmm, xmm, m128|mem, xmm} + ROW(4, 1, 1, 0, 54 , 54 , 54 , 55 , 0 , 0 ), // {ymm, ymm, ymm, ymm|m256|mem} + ROW(4, 1, 1, 0, 54 , 54 , 56 , 54 , 0 , 0 ), // {ymm, ymm, m256|mem, ymm} + ROW(3, 1, 1, 0, 51 , 81 , 51 , 0 , 0 , 0 ), // #155 {xmm, vm64x|vm64y, xmm} + ROW(2, 1, 1, 0, 51 , 71 , 0 , 0 , 0 , 0 ), // {xmm, vm64x} + ROW(2, 1, 1, 0, 54 , 72 , 0 , 0 , 0 , 0 ), // {ymm, vm64y} + ROW(2, 1, 1, 0, 57 , 73 , 0 , 0 , 0 , 0 ), // {zmm, vm64z} + ROW(3, 1, 1, 0, 53 , 51 , 51 , 0 , 0 , 0 ), // #159 {m128|mem, xmm, xmm} + ROW(3, 1, 1, 0, 56 , 54 , 54 , 0 , 0 , 0 ), // {m256|mem, ymm, ymm} + ROW(3, 1, 1, 0, 51 , 51 , 53 , 0 , 0 , 0 ), // {xmm, xmm, m128|mem} + ROW(3, 1, 1, 0, 54 , 54 , 56 , 0 , 0 , 0 ), // {ymm, ymm, m256|mem} + ROW(5, 1, 1, 0, 51 , 51 , 52 , 51 , 82 , 0 ), // #163 {xmm, xmm, xmm|m128|mem, xmm, i4|u4} + ROW(5, 1, 1, 0, 51 , 51 , 51 , 53 , 82 , 0 ), // {xmm, xmm, xmm, m128|mem, i4|u4} + ROW(5, 1, 1, 0, 54 , 54 , 55 , 54 , 82 , 0 ), // {ymm, ymm, ymm|m256|mem, ymm, i4|u4} + ROW(5, 1, 1, 0, 54 , 54 , 54 , 56 , 82 , 0 ), // {ymm, ymm, ymm, m256|mem, i4|u4} + ROW(3, 1, 1, 0, 54 , 55 , 10 , 0 , 0 , 0 ), // #167 {ymm, ymm|m256|mem, i8|u8} + ROW(3, 1, 1, 0, 54 , 54 , 55 , 0 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem} + ROW(3, 1, 1, 0, 57 , 57 , 62 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem|i8|u8} + ROW(3, 1, 1, 0, 57 , 59 , 10 , 0 , 0 , 0 ), // {zmm, m512|mem, i8|u8} + ROW(2, 1, 1, 0, 4 , 34 , 0 , 0 , 0 , 0 ), // #171 {r16, r16|m16|mem} + ROW(2, 1, 1, 0, 6 , 35 , 0 , 0 , 0 , 0 ), // #172 {r32, r32|m32|mem} ROW(2, 0, 1, 0, 8 , 15 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem} - ROW(1, 1, 1, 0, 77 , 0 , 0 , 0 , 0 , 0 ), // #158 {m32|m64} - ROW(2, 1, 1, 0, 78 , 79 , 0 , 0 , 0 , 0 ), // {st0, st} - ROW(2, 1, 1, 0, 79 , 78 , 0 , 0 , 0 , 0 ), // {st, st0} - ROW(2, 1, 1, 0, 4 , 29 , 0 , 0 , 0 , 0 ), // #161 {r16, m32|mem} - ROW(2, 1, 1, 0, 6 , 80 , 0 , 0 , 0 , 0 ), // {r32, m48|mem} - ROW(2, 0, 1, 0, 8 , 81 , 0 , 0 , 0 , 0 ), // {r64, m80|mem} - ROW(3, 1, 1, 0, 27 , 4 , 82 , 0 , 0 , 0 ), // #164 {r16|m16|mem, r16, cl|i8|u8} - ROW(3, 1, 1, 0, 28 , 6 , 82 , 0 , 0 , 0 ), // {r32|m32|mem, r32, cl|i8|u8} - ROW(3, 0, 1, 0, 15 , 8 , 82 , 0 , 0 , 0 ), // {r64|m64|mem, r64, cl|i8|u8} - ROW(3, 1, 1, 0, 45 , 45 , 46 , 0 , 0 , 0 ), // #167 {xmm, xmm, xmm|m128|mem} - ROW(3, 1, 1, 0, 48 , 48 , 49 , 0 , 0 , 0 ), // #168 {ymm, ymm, ymm|m256|mem} - ROW(3, 1, 1, 0, 51 , 51 , 52 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem} - ROW(4, 1, 1, 0, 45 , 45 , 46 , 10 , 0 , 0 ), // #170 {xmm, xmm, xmm|m128|mem, i8|u8} - ROW(4, 1, 1, 0, 48 , 48 , 49 , 10 , 0 , 0 ), // #171 {ymm, ymm, ymm|m256|mem, i8|u8} - ROW(4, 1, 1, 0, 51 , 51 , 52 , 10 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem, i8|u8} - ROW(4, 1, 1, 0, 83 , 45 , 46 , 10 , 0 , 0 ), // #173 {xmm|k, xmm, xmm|m128|mem, i8|u8} - ROW(4, 1, 1, 0, 84 , 48 , 49 , 10 , 0 , 0 ), // {ymm|k, ymm, ymm|m256|mem, i8|u8} - ROW(4, 1, 1, 0, 85 , 51 , 52 , 10 , 0 , 0 ), // {k, zmm, zmm|m512|mem, i8|u8} - ROW(2, 1, 1, 0, 46 , 45 , 0 , 0 , 0 , 0 ), // #176 {xmm|m128|mem, xmm} - ROW(2, 1, 1, 0, 49 , 48 , 0 , 0 , 0 , 0 ), // {ymm|m256|mem, ymm} - ROW(2, 1, 1, 0, 52 , 51 , 0 , 0 , 0 , 0 ), // {zmm|m512|mem, zmm} - ROW(2, 1, 1, 0, 45 , 60 , 0 , 0 , 0 , 0 ), // #179 {xmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 48 , 46 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m128|mem} - ROW(2, 1, 1, 0, 51 , 49 , 0 , 0 , 0 , 0 ), // {zmm, ymm|m256|mem} - ROW(2, 1, 1, 0, 45 , 46 , 0 , 0 , 0 , 0 ), // #182 {xmm, xmm|m128|mem} - ROW(2, 1, 1, 0, 48 , 49 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} - ROW(2, 1, 1, 0, 51 , 52 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem} - ROW(3, 1, 1, 0, 60 , 45 , 10 , 0 , 0 , 0 ), // #185 {xmm|m64|mem, xmm, i8|u8} - ROW(3, 1, 1, 0, 46 , 48 , 10 , 0 , 0 , 0 ), // #186 {xmm|m128|mem, ymm, i8|u8} - ROW(3, 1, 1, 0, 49 , 51 , 10 , 0 , 0 , 0 ), // #187 {ymm|m256|mem, zmm, i8|u8} - ROW(3, 1, 1, 0, 45 , 46 , 10 , 0 , 0 , 0 ), // #188 {xmm, xmm|m128|mem, i8|u8} - ROW(3, 1, 1, 0, 48 , 49 , 10 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem, i8|u8} - ROW(3, 1, 1, 0, 51 , 52 , 10 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem, i8|u8} - ROW(2, 1, 1, 0, 45 , 60 , 0 , 0 , 0 , 0 ), // #191 {xmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 48 , 49 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} - ROW(2, 1, 1, 0, 51 , 52 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem} - ROW(2, 1, 1, 0, 47 , 45 , 0 , 0 , 0 , 0 ), // #194 {m128|mem, xmm} - ROW(2, 1, 1, 0, 50 , 48 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} - ROW(2, 1, 1, 0, 53 , 51 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm} - ROW(2, 1, 1, 0, 45 , 47 , 0 , 0 , 0 , 0 ), // #197 {xmm, m128|mem} - ROW(2, 1, 1, 0, 48 , 50 , 0 , 0 , 0 , 0 ), // {ymm, m256|mem} - ROW(2, 1, 1, 0, 51 , 53 , 0 , 0 , 0 , 0 ), // {zmm, m512|mem} - ROW(2, 0, 1, 0, 15 , 45 , 0 , 0 , 0 , 0 ), // #200 {r64|m64|mem, xmm} - ROW(2, 1, 1, 0, 45 , 86 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m64|mem|r64} - ROW(2, 1, 1, 0, 30 , 45 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} - ROW(2, 1, 1, 0, 30 , 45 , 0 , 0 , 0 , 0 ), // #203 {m64|mem, xmm} - ROW(2, 1, 1, 0, 45 , 30 , 0 , 0 , 0 , 0 ), // {xmm, m64|mem} - ROW(3, 1, 1, 0, 45 , 45 , 45 , 0 , 0 , 0 ), // #205 {xmm, xmm, xmm} - ROW(2, 1, 1, 0, 29 , 45 , 0 , 0 , 0 , 0 ), // #206 {m32|mem, xmm} - ROW(2, 1, 1, 0, 45 , 29 , 0 , 0 , 0 , 0 ), // {xmm, m32|mem} - ROW(3, 1, 1, 0, 45 , 45 , 45 , 0 , 0 , 0 ), // {xmm, xmm, xmm} - ROW(4, 1, 1, 0, 85 , 85 , 45 , 46 , 0 , 0 ), // #209 {k, k, xmm, xmm|m128|mem} - ROW(4, 1, 1, 0, 85 , 85 , 48 , 49 , 0 , 0 ), // {k, k, ymm, ymm|m256|mem} - ROW(4, 1, 1, 0, 85 , 85 , 51 , 52 , 0 , 0 ), // {k, k, zmm, zmm|m512|mem} - ROW(2, 1, 1, 0, 87 , 86 , 0 , 0 , 0 , 0 ), // #212 {xmm|ymm, xmm|m64|mem|r64} - ROW(2, 0, 1, 0, 51 , 8 , 0 , 0 , 0 , 0 ), // {zmm, r64} - ROW(2, 1, 1, 0, 51 , 60 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m64|mem} - ROW(4, 1, 1, 0, 85 , 45 , 46 , 10 , 0 , 0 ), // #215 {k, xmm, xmm|m128|mem, i8|u8} - ROW(4, 1, 1, 0, 85 , 48 , 49 , 10 , 0 , 0 ), // {k, ymm, ymm|m256|mem, i8|u8} - ROW(4, 1, 1, 0, 85 , 51 , 52 , 10 , 0 , 0 ), // {k, zmm, zmm|m512|mem, i8|u8} - ROW(3, 1, 1, 0, 83 , 45 , 46 , 0 , 0 , 0 ), // #218 {xmm|k, xmm, xmm|m128|mem} - ROW(3, 1, 1, 0, 84 , 48 , 49 , 0 , 0 , 0 ), // {ymm|k, ymm, ymm|m256|mem} - ROW(3, 1, 1, 0, 85 , 51 , 52 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem} - ROW(2, 1, 1, 0, 88 , 45 , 0 , 0 , 0 , 0 ), // #221 {xmm|m32|mem, xmm} - ROW(2, 1, 1, 0, 60 , 48 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, ymm} - ROW(2, 1, 1, 0, 46 , 51 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, zmm} - ROW(2, 1, 1, 0, 60 , 45 , 0 , 0 , 0 , 0 ), // #224 {xmm|m64|mem, xmm} - ROW(2, 1, 1, 0, 46 , 48 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, ymm} - ROW(2, 1, 1, 0, 49 , 51 , 0 , 0 , 0 , 0 ), // {ymm|m256|mem, zmm} - ROW(2, 1, 1, 0, 89 , 45 , 0 , 0 , 0 , 0 ), // #227 {xmm|m16|mem, xmm} - ROW(2, 1, 1, 0, 88 , 48 , 0 , 0 , 0 , 0 ), // {xmm|m32|mem, ymm} - ROW(2, 1, 1, 0, 60 , 51 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, zmm} - ROW(2, 1, 1, 0, 45 , 88 , 0 , 0 , 0 , 0 ), // #230 {xmm, xmm|m32|mem} - ROW(2, 1, 1, 0, 48 , 60 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m64|mem} - ROW(2, 1, 1, 0, 51 , 46 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m128|mem} - ROW(2, 1, 1, 0, 45 , 89 , 0 , 0 , 0 , 0 ), // #233 {xmm, xmm|m16|mem} - ROW(2, 1, 1, 0, 48 , 88 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m32|mem} - ROW(2, 1, 1, 0, 51 , 60 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 62 , 45 , 0 , 0 , 0 , 0 ), // #236 {vm32x, xmm} - ROW(2, 1, 1, 0, 63 , 48 , 0 , 0 , 0 , 0 ), // {vm32y, ymm} - ROW(2, 1, 1, 0, 64 , 51 , 0 , 0 , 0 , 0 ), // {vm32z, zmm} - ROW(2, 1, 1, 0, 65 , 45 , 0 , 0 , 0 , 0 ), // #239 {vm64x, xmm} - ROW(2, 1, 1, 0, 66 , 48 , 0 , 0 , 0 , 0 ), // {vm64y, ymm} - ROW(2, 1, 1, 0, 67 , 51 , 0 , 0 , 0 , 0 ), // {vm64z, zmm} - ROW(3, 1, 1, 0, 85 , 45 , 46 , 0 , 0 , 0 ), // #242 {k, xmm, xmm|m128|mem} - ROW(3, 1, 1, 0, 85 , 48 , 49 , 0 , 0 , 0 ), // {k, ymm, ymm|m256|mem} - ROW(3, 1, 1, 0, 85 , 51 , 52 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem} - ROW(3, 1, 1, 0, 6 , 6 , 28 , 0 , 0 , 0 ), // #245 {r32, r32, r32|m32|mem} + ROW(1, 1, 1, 0, 83 , 0 , 0 , 0 , 0 , 0 ), // #174 {m32|m64} + ROW(2, 1, 1, 0, 84 , 85 , 0 , 0 , 0 , 0 ), // {st0, st} + ROW(2, 1, 1, 0, 85 , 84 , 0 , 0 , 0 , 0 ), // {st, st0} + ROW(2, 1, 1, 0, 4 , 26 , 0 , 0 , 0 , 0 ), // #177 {r16, m32|mem} + ROW(2, 1, 1, 0, 6 , 86 , 0 , 0 , 0 , 0 ), // {r32, m48|mem} + ROW(2, 0, 1, 0, 8 , 87 , 0 , 0 , 0 , 0 ), // {r64, m80|mem} + ROW(3, 1, 1, 0, 34 , 4 , 88 , 0 , 0 , 0 ), // #180 {r16|m16|mem, r16, cl|i8|u8} + ROW(3, 1, 1, 0, 35 , 6 , 88 , 0 , 0 , 0 ), // {r32|m32|mem, r32, cl|i8|u8} + ROW(3, 0, 1, 0, 15 , 8 , 88 , 0 , 0 , 0 ), // {r64|m64|mem, r64, cl|i8|u8} + ROW(3, 1, 1, 0, 51 , 51 , 52 , 0 , 0 , 0 ), // #183 {xmm, xmm, xmm|m128|mem} + ROW(3, 1, 1, 0, 54 , 54 , 55 , 0 , 0 , 0 ), // #184 {ymm, ymm, ymm|m256|mem} + ROW(3, 1, 1, 0, 57 , 57 , 58 , 0 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem} + ROW(4, 1, 1, 0, 51 , 51 , 52 , 10 , 0 , 0 ), // #186 {xmm, xmm, xmm|m128|mem, i8|u8} + ROW(4, 1, 1, 0, 54 , 54 , 55 , 10 , 0 , 0 ), // #187 {ymm, ymm, ymm|m256|mem, i8|u8} + ROW(4, 1, 1, 0, 57 , 57 , 58 , 10 , 0 , 0 ), // {zmm, zmm, zmm|m512|mem, i8|u8} + ROW(4, 1, 1, 0, 89 , 51 , 52 , 10 , 0 , 0 ), // #189 {xmm|k, xmm, xmm|m128|mem, i8|u8} + ROW(4, 1, 1, 0, 90 , 54 , 55 , 10 , 0 , 0 ), // {ymm|k, ymm, ymm|m256|mem, i8|u8} + ROW(4, 1, 1, 0, 91 , 57 , 58 , 10 , 0 , 0 ), // {k, zmm, zmm|m512|mem, i8|u8} + ROW(2, 1, 1, 0, 52 , 51 , 0 , 0 , 0 , 0 ), // #192 {xmm|m128|mem, xmm} + ROW(2, 1, 1, 0, 55 , 54 , 0 , 0 , 0 , 0 ), // {ymm|m256|mem, ymm} + ROW(2, 1, 1, 0, 58 , 57 , 0 , 0 , 0 , 0 ), // {zmm|m512|mem, zmm} + ROW(2, 1, 1, 0, 51 , 66 , 0 , 0 , 0 , 0 ), // #195 {xmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 54 , 52 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m128|mem} + ROW(2, 1, 1, 0, 57 , 55 , 0 , 0 , 0 , 0 ), // {zmm, ymm|m256|mem} + ROW(2, 1, 1, 0, 51 , 52 , 0 , 0 , 0 , 0 ), // #198 {xmm, xmm|m128|mem} + ROW(2, 1, 1, 0, 54 , 55 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} + ROW(2, 1, 1, 0, 57 , 58 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem} + ROW(3, 1, 1, 0, 66 , 51 , 10 , 0 , 0 , 0 ), // #201 {xmm|m64|mem, xmm, i8|u8} + ROW(3, 1, 1, 0, 52 , 54 , 10 , 0 , 0 , 0 ), // #202 {xmm|m128|mem, ymm, i8|u8} + ROW(3, 1, 1, 0, 55 , 57 , 10 , 0 , 0 , 0 ), // #203 {ymm|m256|mem, zmm, i8|u8} + ROW(3, 1, 1, 0, 51 , 52 , 10 , 0 , 0 , 0 ), // #204 {xmm, xmm|m128|mem, i8|u8} + ROW(3, 1, 1, 0, 54 , 55 , 10 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem, i8|u8} + ROW(3, 1, 1, 0, 57 , 58 , 10 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem, i8|u8} + ROW(2, 1, 1, 0, 51 , 66 , 0 , 0 , 0 , 0 ), // #207 {xmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 54 , 55 , 0 , 0 , 0 , 0 ), // {ymm, ymm|m256|mem} + ROW(2, 1, 1, 0, 57 , 58 , 0 , 0 , 0 , 0 ), // {zmm, zmm|m512|mem} + ROW(2, 1, 1, 0, 53 , 51 , 0 , 0 , 0 , 0 ), // #210 {m128|mem, xmm} + ROW(2, 1, 1, 0, 56 , 54 , 0 , 0 , 0 , 0 ), // {m256|mem, ymm} + ROW(2, 1, 1, 0, 59 , 57 , 0 , 0 , 0 , 0 ), // {m512|mem, zmm} + ROW(2, 1, 1, 0, 51 , 53 , 0 , 0 , 0 , 0 ), // #213 {xmm, m128|mem} + ROW(2, 1, 1, 0, 54 , 56 , 0 , 0 , 0 , 0 ), // {ymm, m256|mem} + ROW(2, 1, 1, 0, 57 , 59 , 0 , 0 , 0 , 0 ), // {zmm, m512|mem} + ROW(2, 0, 1, 0, 15 , 51 , 0 , 0 , 0 , 0 ), // #216 {r64|m64|mem, xmm} + ROW(2, 1, 1, 0, 51 , 92 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m64|mem|r64} + ROW(2, 1, 1, 0, 28 , 51 , 0 , 0 , 0 , 0 ), // {m64|mem, xmm} + ROW(2, 1, 1, 0, 28 , 51 , 0 , 0 , 0 , 0 ), // #219 {m64|mem, xmm} + ROW(2, 1, 1, 0, 51 , 28 , 0 , 0 , 0 , 0 ), // {xmm, m64|mem} + ROW(3, 1, 1, 0, 51 , 51 , 51 , 0 , 0 , 0 ), // #221 {xmm, xmm, xmm} + ROW(2, 1, 1, 0, 26 , 51 , 0 , 0 , 0 , 0 ), // #222 {m32|mem, xmm} + ROW(2, 1, 1, 0, 51 , 26 , 0 , 0 , 0 , 0 ), // {xmm, m32|mem} + ROW(3, 1, 1, 0, 51 , 51 , 51 , 0 , 0 , 0 ), // {xmm, xmm, xmm} + ROW(4, 1, 1, 0, 91 , 91 , 51 , 52 , 0 , 0 ), // #225 {k, k, xmm, xmm|m128|mem} + ROW(4, 1, 1, 0, 91 , 91 , 54 , 55 , 0 , 0 ), // {k, k, ymm, ymm|m256|mem} + ROW(4, 1, 1, 0, 91 , 91 , 57 , 58 , 0 , 0 ), // {k, k, zmm, zmm|m512|mem} + ROW(2, 1, 1, 0, 93 , 92 , 0 , 0 , 0 , 0 ), // #228 {xmm|ymm, xmm|m64|mem|r64} + ROW(2, 0, 1, 0, 57 , 8 , 0 , 0 , 0 , 0 ), // {zmm, r64} + ROW(2, 1, 1, 0, 57 , 66 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m64|mem} + ROW(4, 1, 1, 0, 91 , 51 , 52 , 10 , 0 , 0 ), // #231 {k, xmm, xmm|m128|mem, i8|u8} + ROW(4, 1, 1, 0, 91 , 54 , 55 , 10 , 0 , 0 ), // {k, ymm, ymm|m256|mem, i8|u8} + ROW(4, 1, 1, 0, 91 , 57 , 58 , 10 , 0 , 0 ), // {k, zmm, zmm|m512|mem, i8|u8} + ROW(3, 1, 1, 0, 89 , 51 , 52 , 0 , 0 , 0 ), // #234 {xmm|k, xmm, xmm|m128|mem} + ROW(3, 1, 1, 0, 90 , 54 , 55 , 0 , 0 , 0 ), // {ymm|k, ymm, ymm|m256|mem} + ROW(3, 1, 1, 0, 91 , 57 , 58 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem} + ROW(2, 1, 1, 0, 94 , 51 , 0 , 0 , 0 , 0 ), // #237 {xmm|m32|mem, xmm} + ROW(2, 1, 1, 0, 66 , 54 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, ymm} + ROW(2, 1, 1, 0, 52 , 57 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, zmm} + ROW(2, 1, 1, 0, 66 , 51 , 0 , 0 , 0 , 0 ), // #240 {xmm|m64|mem, xmm} + ROW(2, 1, 1, 0, 52 , 54 , 0 , 0 , 0 , 0 ), // {xmm|m128|mem, ymm} + ROW(2, 1, 1, 0, 55 , 57 , 0 , 0 , 0 , 0 ), // {ymm|m256|mem, zmm} + ROW(2, 1, 1, 0, 95 , 51 , 0 , 0 , 0 , 0 ), // #243 {xmm|m16|mem, xmm} + ROW(2, 1, 1, 0, 94 , 54 , 0 , 0 , 0 , 0 ), // {xmm|m32|mem, ymm} + ROW(2, 1, 1, 0, 66 , 57 , 0 , 0 , 0 , 0 ), // {xmm|m64|mem, zmm} + ROW(2, 1, 1, 0, 51 , 94 , 0 , 0 , 0 , 0 ), // #246 {xmm, xmm|m32|mem} + ROW(2, 1, 1, 0, 54 , 66 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m64|mem} + ROW(2, 1, 1, 0, 57 , 52 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m128|mem} + ROW(2, 1, 1, 0, 51 , 95 , 0 , 0 , 0 , 0 ), // #249 {xmm, xmm|m16|mem} + ROW(2, 1, 1, 0, 54 , 94 , 0 , 0 , 0 , 0 ), // {ymm, xmm|m32|mem} + ROW(2, 1, 1, 0, 57 , 66 , 0 , 0 , 0 , 0 ), // {zmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 68 , 51 , 0 , 0 , 0 , 0 ), // #252 {vm32x, xmm} + ROW(2, 1, 1, 0, 69 , 54 , 0 , 0 , 0 , 0 ), // {vm32y, ymm} + ROW(2, 1, 1, 0, 70 , 57 , 0 , 0 , 0 , 0 ), // {vm32z, zmm} + ROW(2, 1, 1, 0, 71 , 51 , 0 , 0 , 0 , 0 ), // #255 {vm64x, xmm} + ROW(2, 1, 1, 0, 72 , 54 , 0 , 0 , 0 , 0 ), // {vm64y, ymm} + ROW(2, 1, 1, 0, 73 , 57 , 0 , 0 , 0 , 0 ), // {vm64z, zmm} + ROW(3, 1, 1, 0, 91 , 51 , 52 , 0 , 0 , 0 ), // #258 {k, xmm, xmm|m128|mem} + ROW(3, 1, 1, 0, 91 , 54 , 55 , 0 , 0 , 0 ), // {k, ymm, ymm|m256|mem} + ROW(3, 1, 1, 0, 91 , 57 , 58 , 0 , 0 , 0 ), // {k, zmm, zmm|m512|mem} + ROW(3, 1, 1, 0, 6 , 6 , 35 , 0 , 0 , 0 ), // #261 {r32, r32, r32|m32|mem} ROW(3, 0, 1, 0, 8 , 8 , 15 , 0 , 0 , 0 ), // {r64, r64, r64|m64|mem} - ROW(3, 1, 1, 0, 6 , 28 , 6 , 0 , 0 , 0 ), // #247 {r32, r32|m32|mem, r32} + ROW(3, 1, 1, 0, 6 , 35 , 6 , 0 , 0 , 0 ), // #263 {r32, r32|m32|mem, r32} ROW(3, 0, 1, 0, 8 , 15 , 8 , 0 , 0 , 0 ), // {r64, r64|m64|mem, r64} - ROW(2, 1, 0, 0, 90 , 28 , 0 , 0 , 0 , 0 ), // #249 {bnd, r32|m32|mem} - ROW(2, 0, 1, 0, 90 , 15 , 0 , 0 , 0 , 0 ), // {bnd, r64|m64|mem} - ROW(2, 1, 1, 0, 90 , 91 , 0 , 0 , 0 , 0 ), // #251 {bnd, bnd|mem} - ROW(2, 1, 1, 0, 92 , 90 , 0 , 0 , 0 , 0 ), // {mem, bnd} - ROW(2, 1, 0, 0, 4 , 29 , 0 , 0 , 0 , 0 ), // #253 {r16, m32|mem} - ROW(2, 1, 0, 0, 6 , 30 , 0 , 0 , 0 , 0 ), // {r32, m64|mem} - ROW(1, 1, 0, 0, 93 , 0 , 0 , 0 , 0 , 0 ), // #255 {rel16|r16|m16|r32|m32} - ROW(1, 1, 1, 0, 94 , 0 , 0 , 0 , 0 , 0 ), // {rel32|r64|m64|mem} - ROW(2, 1, 1, 0, 6 , 95 , 0 , 0 , 0 , 0 ), // #257 {r32, r8lo|r8hi|m8|r16|m16|r32|m32} - ROW(2, 0, 1, 0, 8 , 96 , 0 , 0 , 0 , 0 ), // {r64, r8lo|r8hi|m8|r64|m64} - ROW(1, 1, 0, 0, 97 , 0 , 0 , 0 , 0 , 0 ), // #259 {r16|r32} - ROW(1, 1, 1, 0, 31 , 0 , 0 , 0 , 0 , 0 ), // #260 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem} - ROW(2, 1, 0, 0, 98 , 53 , 0 , 0 , 0 , 0 ), // #261 {es:[memBase], m512|mem} - ROW(2, 0, 1, 0, 98 , 53 , 0 , 0 , 0 , 0 ), // {es:[memBase], m512|mem} - ROW(3, 1, 1, 0, 45 , 10 , 10 , 0 , 0 , 0 ), // #263 {xmm, i8|u8, i8|u8} - ROW(2, 1, 1, 0, 45 , 45 , 0 , 0 , 0 , 0 ), // #264 {xmm, xmm} - ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #265 {} - ROW(1, 1, 1, 0, 79 , 0 , 0 , 0 , 0 , 0 ), // #266 {st} - ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #267 {} - ROW(1, 1, 1, 0, 99 , 0 , 0 , 0 , 0 , 0 ), // #268 {m32|m64|st} - ROW(2, 1, 1, 0, 45 , 45 , 0 , 0 , 0 , 0 ), // #269 {xmm, xmm} - ROW(4, 1, 1, 0, 45 , 45 , 10 , 10 , 0 , 0 ), // {xmm, xmm, i8|u8, i8|u8} - ROW(2, 1, 0, 0, 6 , 47 , 0 , 0 , 0 , 0 ), // #271 {r32, m128|mem} - ROW(2, 0, 1, 0, 8 , 47 , 0 , 0 , 0 , 0 ), // {r64, m128|mem} - ROW(2, 1, 0, 2, 36 , 100, 0 , 0 , 0 , 0 ), // #273 {, } - ROW(2, 0, 1, 2, 101, 100, 0 , 0 , 0 , 0 ), // {, } - ROW(1, 1, 1, 0, 102, 0 , 0 , 0 , 0 , 0 ), // #275 {rel8|rel32} - ROW(1, 1, 0, 0, 103, 0 , 0 , 0 , 0 , 0 ), // {rel16} - ROW(2, 1, 0, 1, 104, 105, 0 , 0 , 0 , 0 ), // #277 {, rel8} - ROW(2, 0, 1, 1, 106, 105, 0 , 0 , 0 , 0 ), // {, rel8} - ROW(1, 1, 1, 0, 107, 0 , 0 , 0 , 0 , 0 ), // #279 {rel8|rel32|r64|m64|mem} - ROW(1, 1, 0, 0, 108, 0 , 0 , 0 , 0 , 0 ), // {rel16|r32|m32|mem} - ROW(2, 1, 1, 0, 85 , 109, 0 , 0 , 0 , 0 ), // #281 {k, k|m8|mem|r32|r8lo|r8hi|r16} - ROW(2, 1, 1, 0, 110, 85 , 0 , 0 , 0 , 0 ), // {m8|mem|r32|r8lo|r8hi|r16, k} - ROW(2, 1, 1, 0, 85 , 111, 0 , 0 , 0 , 0 ), // #283 {k, k|m32|mem|r32} - ROW(2, 1, 1, 0, 28 , 85 , 0 , 0 , 0 , 0 ), // {m32|mem|r32, k} - ROW(2, 1, 1, 0, 85 , 112, 0 , 0 , 0 , 0 ), // #285 {k, k|m64|mem|r64} - ROW(2, 1, 1, 0, 15 , 85 , 0 , 0 , 0 , 0 ), // {m64|mem|r64, k} - ROW(2, 1, 1, 0, 85 , 113, 0 , 0 , 0 , 0 ), // #287 {k, k|m16|mem|r32|r16} - ROW(2, 1, 1, 0, 114, 85 , 0 , 0 , 0 , 0 ), // {m16|mem|r32|r16, k} - ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #289 {r16, r16|m16|mem} - ROW(2, 1, 1, 0, 6 , 114, 0 , 0 , 0 , 0 ), // {r32, r32|m16|mem|r16} - ROW(2, 1, 0, 0, 4 , 29 , 0 , 0 , 0 , 0 ), // #291 {r16, m32|mem} - ROW(2, 1, 0, 0, 6 , 80 , 0 , 0 , 0 , 0 ), // {r32, m48|mem} - ROW(2, 1, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #293 {r16, r16|m16|mem} - ROW(2, 1, 1, 0, 115, 114, 0 , 0 , 0 , 0 ), // {r32|r64, r32|m16|mem|r16} - ROW(2, 1, 1, 0, 59 , 28 , 0 , 0 , 0 , 0 ), // #295 {mm|xmm, r32|m32|mem} - ROW(2, 1, 1, 0, 28 , 59 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, mm|xmm} - ROW(2, 1, 1, 0, 45 , 88 , 0 , 0 , 0 , 0 ), // #297 {xmm, xmm|m32|mem} - ROW(2, 1, 1, 0, 29 , 45 , 0 , 0 , 0 , 0 ), // {m32|mem, xmm} - ROW(2, 1, 1, 0, 4 , 9 , 0 , 0 , 0 , 0 ), // #299 {r16, r8lo|r8hi|m8} - ROW(2, 1, 1, 0, 115, 116, 0 , 0 , 0 , 0 ), // {r32|r64, r8lo|r8hi|m8|r16|m16} - ROW(2, 0, 1, 0, 4 , 27 , 0 , 0 , 0 , 0 ), // #301 {r16, r16|m16|mem} - ROW(2, 0, 1, 0, 115, 28 , 0 , 0 , 0 , 0 ), // {r32|r64, r32|m32|mem} - ROW(4, 1, 1, 1, 6 , 6 , 28 , 35 , 0 , 0 ), // #303 {r32, r32, r32|m32|mem, } - ROW(4, 0, 1, 1, 8 , 8 , 15 , 37 , 0 , 0 ), // {r64, r64, r64|m64|mem, } - ROW(2, 1, 1, 0, 57 , 117, 0 , 0 , 0 , 0 ), // #305 {mm, mm|m64|mem} - ROW(2, 1, 1, 0, 45 , 46 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem} - ROW(3, 1, 1, 0, 57 , 117, 10 , 0 , 0 , 0 ), // #307 {mm, mm|m64|mem, i8|u8} - ROW(3, 1, 1, 0, 45 , 46 , 10 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem, i8|u8} - ROW(3, 1, 1, 0, 6 , 59 , 10 , 0 , 0 , 0 ), // #309 {r32, mm|xmm, i8|u8} - ROW(3, 1, 1, 0, 21 , 45 , 10 , 0 , 0 , 0 ), // {m16|mem, xmm, i8|u8} - ROW(2, 1, 1, 0, 57 , 118, 0 , 0 , 0 , 0 ), // #311 {mm, i8|u8|mm|m64|mem} - ROW(2, 1, 1, 0, 45 , 54 , 0 , 0 , 0 , 0 ), // {xmm, i8|u8|xmm|m128|mem} - ROW(1, 1, 0, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #313 {r32} - ROW(1, 0, 1, 0, 8 , 0 , 0 , 0 , 0 , 0 ), // #314 {r64} - ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #315 {} - ROW(1, 1, 1, 0, 119, 0 , 0 , 0 , 0 , 0 ), // {u16} - ROW(3, 1, 1, 0, 6 , 28 , 10 , 0 , 0 , 0 ), // #317 {r32, r32|m32|mem, i8|u8} + ROW(2, 1, 0, 0, 96 , 35 , 0 , 0 , 0 , 0 ), // #265 {bnd, r32|m32|mem} + ROW(2, 0, 1, 0, 96 , 15 , 0 , 0 , 0 , 0 ), // {bnd, r64|m64|mem} + ROW(2, 1, 1, 0, 96 , 97 , 0 , 0 , 0 , 0 ), // #267 {bnd, bnd|mem} + ROW(2, 1, 1, 0, 98 , 96 , 0 , 0 , 0 , 0 ), // {mem, bnd} + ROW(2, 1, 0, 0, 4 , 26 , 0 , 0 , 0 , 0 ), // #269 {r16, m32|mem} + ROW(2, 1, 0, 0, 6 , 28 , 0 , 0 , 0 , 0 ), // {r32, m64|mem} + ROW(1, 1, 0, 0, 99 , 0 , 0 , 0 , 0 , 0 ), // #271 {rel16|r16|m16|r32|m32} + ROW(1, 1, 1, 0, 100, 0 , 0 , 0 , 0 , 0 ), // {rel32|r64|m64|mem} + ROW(2, 1, 1, 0, 6 , 101, 0 , 0 , 0 , 0 ), // #273 {r32, r8lo|r8hi|m8|r16|m16|r32|m32} + ROW(2, 0, 1, 0, 8 , 102, 0 , 0 , 0 , 0 ), // {r64, r8lo|r8hi|m8|r64|m64} + ROW(1, 1, 0, 0, 103, 0 , 0 , 0 , 0 , 0 ), // #275 {r16|r32} + ROW(1, 1, 1, 0, 36 , 0 , 0 , 0 , 0 , 0 ), // #276 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem} + ROW(2, 1, 0, 0, 104, 59 , 0 , 0 , 0 , 0 ), // #277 {es:[memBase], m512|mem} + ROW(2, 0, 1, 0, 104, 59 , 0 , 0 , 0 , 0 ), // {es:[memBase], m512|mem} + ROW(3, 1, 1, 0, 51 , 10 , 10 , 0 , 0 , 0 ), // #279 {xmm, i8|u8, i8|u8} + ROW(2, 1, 1, 0, 51 , 51 , 0 , 0 , 0 , 0 ), // #280 {xmm, xmm} + ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #281 {} + ROW(1, 1, 1, 0, 85 , 0 , 0 , 0 , 0 , 0 ), // #282 {st} + ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #283 {} + ROW(1, 1, 1, 0, 105, 0 , 0 , 0 , 0 , 0 ), // #284 {m32|m64|st} + ROW(2, 1, 1, 0, 51 , 51 , 0 , 0 , 0 , 0 ), // #285 {xmm, xmm} + ROW(4, 1, 1, 0, 51 , 51 , 10 , 10 , 0 , 0 ), // {xmm, xmm, i8|u8, i8|u8} + ROW(2, 1, 0, 0, 6 , 53 , 0 , 0 , 0 , 0 ), // #287 {r32, m128|mem} + ROW(2, 0, 1, 0, 8 , 53 , 0 , 0 , 0 , 0 ), // {r64, m128|mem} + ROW(2, 1, 0, 2, 41 , 106, 0 , 0 , 0 , 0 ), // #289 {, } + ROW(2, 0, 1, 2, 107, 106, 0 , 0 , 0 , 0 ), // {, } + ROW(1, 1, 1, 0, 108, 0 , 0 , 0 , 0 , 0 ), // #291 {rel8|rel32} + ROW(1, 1, 0, 0, 109, 0 , 0 , 0 , 0 , 0 ), // {rel16} + ROW(2, 1, 0, 1, 110, 111, 0 , 0 , 0 , 0 ), // #293 {, rel8} + ROW(2, 0, 1, 1, 112, 111, 0 , 0 , 0 , 0 ), // {, rel8} + ROW(1, 1, 1, 0, 113, 0 , 0 , 0 , 0 , 0 ), // #295 {rel8|rel32|r64|m64|mem} + ROW(1, 1, 0, 0, 114, 0 , 0 , 0 , 0 , 0 ), // {rel16|r32|m32|mem} + ROW(2, 1, 1, 0, 91 , 115, 0 , 0 , 0 , 0 ), // #297 {k, k|m8|mem|r32|r8lo|r8hi|r16} + ROW(2, 1, 1, 0, 116, 91 , 0 , 0 , 0 , 0 ), // {m8|mem|r32|r8lo|r8hi|r16, k} + ROW(2, 1, 1, 0, 91 , 117, 0 , 0 , 0 , 0 ), // #299 {k, k|m32|mem|r32} + ROW(2, 1, 1, 0, 35 , 91 , 0 , 0 , 0 , 0 ), // {m32|mem|r32, k} + ROW(2, 1, 1, 0, 91 , 118, 0 , 0 , 0 , 0 ), // #301 {k, k|m64|mem|r64} + ROW(2, 1, 1, 0, 15 , 91 , 0 , 0 , 0 , 0 ), // {m64|mem|r64, k} + ROW(2, 1, 1, 0, 91 , 119, 0 , 0 , 0 , 0 ), // #303 {k, k|m16|mem|r32|r16} + ROW(2, 1, 1, 0, 120, 91 , 0 , 0 , 0 , 0 ), // {m16|mem|r32|r16, k} + ROW(2, 1, 1, 0, 4 , 34 , 0 , 0 , 0 , 0 ), // #305 {r16, r16|m16|mem} + ROW(2, 1, 1, 0, 6 , 120, 0 , 0 , 0 , 0 ), // {r32, r32|m16|mem|r16} + ROW(2, 1, 0, 0, 4 , 26 , 0 , 0 , 0 , 0 ), // #307 {r16, m32|mem} + ROW(2, 1, 0, 0, 6 , 86 , 0 , 0 , 0 , 0 ), // {r32, m48|mem} + ROW(2, 1, 1, 0, 4 , 34 , 0 , 0 , 0 , 0 ), // #309 {r16, r16|m16|mem} + ROW(2, 1, 1, 0, 121, 120, 0 , 0 , 0 , 0 ), // {r32|r64, r32|m16|mem|r16} + ROW(2, 1, 1, 0, 65 , 35 , 0 , 0 , 0 , 0 ), // #311 {mm|xmm, r32|m32|mem} + ROW(2, 1, 1, 0, 35 , 65 , 0 , 0 , 0 , 0 ), // {r32|m32|mem, mm|xmm} + ROW(2, 1, 1, 0, 51 , 94 , 0 , 0 , 0 , 0 ), // #313 {xmm, xmm|m32|mem} + ROW(2, 1, 1, 0, 26 , 51 , 0 , 0 , 0 , 0 ), // {m32|mem, xmm} + ROW(2, 1, 1, 0, 4 , 9 , 0 , 0 , 0 , 0 ), // #315 {r16, r8lo|r8hi|m8} + ROW(2, 1, 1, 0, 121, 122, 0 , 0 , 0 , 0 ), // {r32|r64, r8lo|r8hi|m8|r16|m16} + ROW(2, 0, 1, 0, 4 , 34 , 0 , 0 , 0 , 0 ), // #317 {r16, r16|m16|mem} + ROW(2, 0, 1, 0, 121, 35 , 0 , 0 , 0 , 0 ), // {r32|r64, r32|m32|mem} + ROW(4, 1, 1, 1, 6 , 6 , 35 , 40 , 0 , 0 ), // #319 {r32, r32, r32|m32|mem, } + ROW(4, 0, 1, 1, 8 , 8 , 15 , 42 , 0 , 0 ), // {r64, r64, r64|m64|mem, } + ROW(2, 1, 1, 0, 63 , 123, 0 , 0 , 0 , 0 ), // #321 {mm, mm|m64|mem} + ROW(2, 1, 1, 0, 51 , 52 , 0 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem} + ROW(3, 1, 1, 0, 63 , 123, 10 , 0 , 0 , 0 ), // #323 {mm, mm|m64|mem, i8|u8} + ROW(3, 1, 1, 0, 51 , 52 , 10 , 0 , 0 , 0 ), // {xmm, xmm|m128|mem, i8|u8} + ROW(3, 1, 1, 0, 6 , 65 , 10 , 0 , 0 , 0 ), // #325 {r32, mm|xmm, i8|u8} + ROW(3, 1, 1, 0, 22 , 51 , 10 , 0 , 0 , 0 ), // {m16|mem, xmm, i8|u8} + ROW(2, 1, 1, 0, 63 , 124, 0 , 0 , 0 , 0 ), // #327 {mm, i8|u8|mm|m64|mem} + ROW(2, 1, 1, 0, 51 , 60 , 0 , 0 , 0 , 0 ), // {xmm, i8|u8|xmm|m128|mem} + ROW(1, 1, 0, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #329 {r32} + ROW(1, 0, 1, 0, 8 , 0 , 0 , 0 , 0 , 0 ), // #330 {r64} + ROW(0, 1, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #331 {} + ROW(1, 1, 1, 0, 125, 0 , 0 , 0 , 0 , 0 ), // {u16} + ROW(3, 1, 1, 0, 6 , 35 , 10 , 0 , 0 , 0 ), // #333 {r32, r32|m32|mem, i8|u8} ROW(3, 0, 1, 0, 8 , 15 , 10 , 0 , 0 , 0 ), // {r64, r64|m64|mem, i8|u8} - ROW(4, 1, 1, 0, 45 , 45 , 46 , 45 , 0 , 0 ), // #319 {xmm, xmm, xmm|m128|mem, xmm} - ROW(4, 1, 1, 0, 48 , 48 , 49 , 48 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem, ymm} - ROW(2, 1, 1, 0, 45 , 120, 0 , 0 , 0 , 0 ), // #321 {xmm, xmm|m128|ymm|m256} - ROW(2, 1, 1, 0, 48 , 52 , 0 , 0 , 0 , 0 ), // {ymm, zmm|m512|mem} - ROW(4, 1, 1, 0, 45 , 45 , 45 , 60 , 0 , 0 ), // #323 {xmm, xmm, xmm, xmm|m64|mem} - ROW(4, 1, 1, 0, 45 , 45 , 30 , 45 , 0 , 0 ), // {xmm, xmm, m64|mem, xmm} - ROW(4, 1, 1, 0, 45 , 45 , 45 , 88 , 0 , 0 ), // #325 {xmm, xmm, xmm, xmm|m32|mem} - ROW(4, 1, 1, 0, 45 , 45 , 29 , 45 , 0 , 0 ), // {xmm, xmm, m32|mem, xmm} - ROW(4, 1, 1, 0, 48 , 48 , 46 , 10 , 0 , 0 ), // #327 {ymm, ymm, xmm|m128|mem, i8|u8} - ROW(4, 1, 1, 0, 51 , 51 , 46 , 10 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem, i8|u8} - ROW(1, 1, 0, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #329 {} - ROW(1, 0, 1, 1, 38 , 0 , 0 , 0 , 0 , 0 ), // #330 {} - ROW(2, 1, 1, 0, 28 , 45 , 0 , 0 , 0 , 0 ), // #331 {r32|m32|mem, xmm} - ROW(2, 1, 1, 0, 45 , 28 , 0 , 0 , 0 , 0 ), // {xmm, r32|m32|mem} - ROW(2, 1, 1, 0, 30 , 45 , 0 , 0 , 0 , 0 ), // #333 {m64|mem, xmm} - ROW(3, 1, 1, 0, 45 , 45 , 30 , 0 , 0 , 0 ), // {xmm, xmm, m64|mem} - ROW(2, 1, 0, 0, 28 , 6 , 0 , 0 , 0 , 0 ), // #335 {r32|m32|mem, r32} + ROW(4, 1, 1, 0, 51 , 51 , 52 , 51 , 0 , 0 ), // #335 {xmm, xmm, xmm|m128|mem, xmm} + ROW(4, 1, 1, 0, 54 , 54 , 55 , 54 , 0 , 0 ), // {ymm, ymm, ymm|m256|mem, ymm} + ROW(2, 1, 1, 0, 51 , 126, 0 , 0 , 0 , 0 ), // #337 {xmm, xmm|m128|ymm|m256} + ROW(2, 1, 1, 0, 54 , 58 , 0 , 0 , 0 , 0 ), // {ymm, zmm|m512|mem} + ROW(4, 1, 1, 0, 51 , 51 , 51 , 66 , 0 , 0 ), // #339 {xmm, xmm, xmm, xmm|m64|mem} + ROW(4, 1, 1, 0, 51 , 51 , 28 , 51 , 0 , 0 ), // {xmm, xmm, m64|mem, xmm} + ROW(4, 1, 1, 0, 51 , 51 , 51 , 94 , 0 , 0 ), // #341 {xmm, xmm, xmm, xmm|m32|mem} + ROW(4, 1, 1, 0, 51 , 51 , 26 , 51 , 0 , 0 ), // {xmm, xmm, m32|mem, xmm} + ROW(4, 1, 1, 0, 54 , 54 , 52 , 10 , 0 , 0 ), // #343 {ymm, ymm, xmm|m128|mem, i8|u8} + ROW(4, 1, 1, 0, 57 , 57 , 52 , 10 , 0 , 0 ), // {zmm, zmm, xmm|m128|mem, i8|u8} + ROW(1, 1, 0, 1, 41 , 0 , 0 , 0 , 0 , 0 ), // #345 {} + ROW(1, 0, 1, 1, 43 , 0 , 0 , 0 , 0 , 0 ), // #346 {} + ROW(2, 1, 1, 0, 35 , 51 , 0 , 0 , 0 , 0 ), // #347 {r32|m32|mem, xmm} + ROW(2, 1, 1, 0, 51 , 35 , 0 , 0 , 0 , 0 ), // {xmm, r32|m32|mem} + ROW(2, 1, 1, 0, 28 , 51 , 0 , 0 , 0 , 0 ), // #349 {m64|mem, xmm} + ROW(3, 1, 1, 0, 51 , 51 , 28 , 0 , 0 , 0 ), // {xmm, xmm, m64|mem} + ROW(2, 1, 0, 0, 35 , 6 , 0 , 0 , 0 , 0 ), // #351 {r32|m32|mem, r32} ROW(2, 0, 1, 0, 15 , 8 , 0 , 0 , 0 , 0 ), // {r64|m64|mem, r64} - ROW(2, 1, 0, 0, 6 , 28 , 0 , 0 , 0 , 0 ), // #337 {r32, r32|m32|mem} + ROW(2, 1, 0, 0, 6 , 35 , 0 , 0 , 0 , 0 ), // #353 {r32, r32|m32|mem} ROW(2, 0, 1, 0, 8 , 15 , 0 , 0 , 0 , 0 ), // {r64, r64|m64|mem} - ROW(3, 1, 1, 0, 45 , 45 , 54 , 0 , 0 , 0 ), // #339 {xmm, xmm, xmm|m128|mem|i8|u8} - ROW(3, 1, 1, 0, 45 , 47 , 121, 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8|xmm} - ROW(2, 1, 1, 0, 75 , 45 , 0 , 0 , 0 , 0 ), // #341 {vm64x|vm64y, xmm} - ROW(2, 1, 1, 0, 67 , 48 , 0 , 0 , 0 , 0 ), // {vm64z, ymm} - ROW(3, 1, 1, 0, 45 , 45 , 46 , 0 , 0 , 0 ), // #343 {xmm, xmm, xmm|m128|mem} - ROW(3, 1, 1, 0, 45 , 47 , 45 , 0 , 0 , 0 ), // {xmm, m128|mem, xmm} - ROW(2, 1, 1, 0, 62 , 87 , 0 , 0 , 0 , 0 ), // #345 {vm32x, xmm|ymm} - ROW(2, 1, 1, 0, 63 , 51 , 0 , 0 , 0 , 0 ), // {vm32y, zmm} - ROW(1, 1, 0, 1, 33 , 0 , 0 , 0 , 0 , 0 ), // #347 {} - ROW(2, 1, 0, 1, 33 , 10 , 0 , 0 , 0 , 0 ), // #348 {, i8|u8} - ROW(2, 1, 0, 0, 27 , 4 , 0 , 0 , 0 , 0 ), // #349 {r16|m16|mem, r16} - ROW(3, 1, 1, 1, 45 , 46 , 122, 0 , 0 , 0 ), // #350 {xmm, xmm|m128|mem, } - ROW(2, 1, 1, 0, 90 , 123, 0 , 0 , 0 , 0 ), // #351 {bnd, mib} - ROW(2, 1, 1, 0, 90 , 92 , 0 , 0 , 0 , 0 ), // #352 {bnd, mem} - ROW(2, 1, 1, 0, 123, 90 , 0 , 0 , 0 , 0 ), // #353 {mib, bnd} - ROW(1, 1, 1, 0, 124, 0 , 0 , 0 , 0 , 0 ), // #354 {r16|r32|r64} - ROW(1, 1, 1, 1, 33 , 0 , 0 , 0 , 0 , 0 ), // #355 {} - ROW(2, 1, 1, 2, 35 , 36 , 0 , 0 , 0 , 0 ), // #356 {, } - ROW(1, 1, 1, 0, 92 , 0 , 0 , 0 , 0 , 0 ), // #357 {mem} - ROW(1, 1, 1, 0, 30 , 0 , 0 , 0 , 0 , 0 ), // #358 {m64|mem} - ROW(1, 1, 1, 1, 125, 0 , 0 , 0 , 0 , 0 ), // #359 {} - ROW(2, 1, 1, 2, 126, 127, 0 , 0 , 0 , 0 ), // #360 {, } - ROW(3, 1, 1, 0, 45 , 60 , 10 , 0 , 0 , 0 ), // #361 {xmm, xmm|m64|mem, i8|u8} - ROW(3, 1, 1, 0, 45 , 88 , 10 , 0 , 0 , 0 ), // #362 {xmm, xmm|m32|mem, i8|u8} - ROW(5, 0, 1, 4, 47 , 37 , 38 , 128, 129, 0 ), // #363 {m128|mem, , , , } - ROW(5, 1, 1, 4, 30 , 35 , 36 , 100, 130, 0 ), // #364 {m64|mem, , , , } - ROW(4, 1, 1, 4, 36 , 130, 100, 35 , 0 , 0 ), // #365 {, , , } - ROW(2, 0, 1, 2, 37 , 38 , 0 , 0 , 0 , 0 ), // #366 {, } - ROW(2, 1, 1, 0, 57 , 46 , 0 , 0 , 0 , 0 ), // #367 {mm, xmm|m128|mem} - ROW(2, 1, 1, 0, 45 , 117, 0 , 0 , 0 , 0 ), // #368 {xmm, mm|m64|mem} - ROW(2, 1, 1, 0, 57 , 60 , 0 , 0 , 0 , 0 ), // #369 {mm, xmm|m64|mem} - ROW(2, 1, 1, 0, 115, 60 , 0 , 0 , 0 , 0 ), // #370 {r32|r64, xmm|m64|mem} - ROW(2, 1, 1, 0, 45 , 131, 0 , 0 , 0 , 0 ), // #371 {xmm, r32|m32|mem|r64|m64} - ROW(2, 1, 1, 0, 115, 88 , 0 , 0 , 0 , 0 ), // #372 {r32|r64, xmm|m32|mem} - ROW(2, 1, 1, 2, 34 , 33 , 0 , 0 , 0 , 0 ), // #373 {, } - ROW(1, 1, 1, 1, 36 , 0 , 0 , 0 , 0 , 0 ), // #374 {} - ROW(2, 1, 1, 0, 12 , 10 , 0 , 0 , 0 , 0 ), // #375 {i16|u16, i8|u8} - ROW(3, 1, 1, 0, 28 , 45 , 10 , 0 , 0 , 0 ), // #376 {r32|m32|mem, xmm, i8|u8} - ROW(1, 1, 1, 0, 81 , 0 , 0 , 0 , 0 , 0 ), // #377 {m80|mem} - ROW(1, 1, 1, 0, 132, 0 , 0 , 0 , 0 , 0 ), // #378 {m16|m32} - ROW(1, 1, 1, 0, 133, 0 , 0 , 0 , 0 , 0 ), // #379 {m16|m32|m64} - ROW(1, 1, 1, 0, 134, 0 , 0 , 0 , 0 , 0 ), // #380 {m32|m64|m80|st} - ROW(1, 1, 1, 0, 21 , 0 , 0 , 0 , 0 , 0 ), // #381 {m16|mem} - ROW(1, 1, 1, 0, 135, 0 , 0 , 0 , 0 , 0 ), // #382 {ax|m16|mem} - ROW(1, 0, 1, 0, 92 , 0 , 0 , 0 , 0 , 0 ), // #383 {mem} - ROW(2, 1, 1, 0, 136, 137, 0 , 0 , 0 , 0 ), // #384 {al|ax|eax, i8|u8|dx} - ROW(1, 1, 1, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #385 {r32} - ROW(2, 1, 1, 0, 138, 139, 0 , 0 , 0 , 0 ), // #386 {es:[memBase|zdi], dx} - ROW(1, 1, 1, 0, 10 , 0 , 0 , 0 , 0 , 0 ), // #387 {i8|u8} - ROW(0, 1, 0, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #388 {} - ROW(0, 0, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #389 {} - ROW(3, 1, 1, 0, 85 , 85 , 85 , 0 , 0 , 0 ), // #390 {k, k, k} - ROW(2, 1, 1, 0, 85 , 85 , 0 , 0 , 0 , 0 ), // #391 {k, k} - ROW(3, 1, 1, 0, 85 , 85 , 10 , 0 , 0 , 0 ), // #392 {k, k, i8|u8} - ROW(1, 1, 1, 1, 140, 0 , 0 , 0 , 0 , 0 ), // #393 {} - ROW(1, 1, 1, 0, 29 , 0 , 0 , 0 , 0 , 0 ), // #394 {m32|mem} - ROW(1, 0, 1, 0, 53 , 0 , 0 , 0 , 0 , 0 ), // #395 {m512|mem} - ROW(2, 1, 1, 0, 124, 141, 0 , 0 , 0 , 0 ), // #396 {r16|r32|r64, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024} - ROW(1, 1, 1, 0, 27 , 0 , 0 , 0 , 0 , 0 ), // #397 {r16|m16|mem} - ROW(1, 1, 1, 0, 115, 0 , 0 , 0 , 0 , 0 ), // #398 {r32|r64} - ROW(2, 1, 1, 2, 142, 126, 0 , 0 , 0 , 0 ), // #399 {, } - ROW(3, 1, 1, 0, 115, 28 , 14 , 0 , 0 , 0 ), // #400 {r32|r64, r32|m32|mem, i32|u32} - ROW(3, 1, 1, 1, 45 , 45 , 143, 0 , 0 , 0 ), // #401 {xmm, xmm, } - ROW(3, 1, 1, 1, 57 , 57 , 143, 0 , 0 , 0 ), // #402 {mm, mm, } - ROW(3, 1, 1, 3, 125, 100, 35 , 0 , 0 , 0 ), // #403 {, , } - ROW(2, 1, 1, 0, 98 , 53 , 0 , 0 , 0 , 0 ), // #404 {es:[memBase], m512|mem} - ROW(2, 1, 1, 0, 57 , 45 , 0 , 0 , 0 , 0 ), // #405 {mm, xmm} - ROW(2, 1, 1, 0, 6 , 45 , 0 , 0 , 0 , 0 ), // #406 {r32, xmm} - ROW(2, 1, 1, 0, 30 , 57 , 0 , 0 , 0 , 0 ), // #407 {m64|mem, mm} - ROW(2, 1, 1, 0, 45 , 57 , 0 , 0 , 0 , 0 ), // #408 {xmm, mm} - ROW(2, 1, 1, 2, 127, 126, 0 , 0 , 0 , 0 ), // #409 {, } - ROW(2, 1, 1, 2, 36 , 100, 0 , 0 , 0 , 0 ), // #410 {, } - ROW(3, 1, 1, 3, 36 , 100, 130, 0 , 0 , 0 ), // #411 {, , } - ROW(2, 1, 1, 0, 144, 136, 0 , 0 , 0 , 0 ), // #412 {u8|dx, al|ax|eax} - ROW(2, 1, 1, 0, 139, 145, 0 , 0 , 0 , 0 ), // #413 {dx, ds:[memBase|zsi]} - ROW(6, 1, 1, 3, 45 , 46 , 10 , 100, 36 , 35 ), // #414 {xmm, xmm|m128|mem, i8|u8, , , } - ROW(6, 1, 1, 3, 45 , 46 , 10 , 122, 36 , 35 ), // #415 {xmm, xmm|m128|mem, i8|u8, , , } - ROW(4, 1, 1, 1, 45 , 46 , 10 , 100, 0 , 0 ), // #416 {xmm, xmm|m128|mem, i8|u8, } - ROW(4, 1, 1, 1, 45 , 46 , 10 , 122, 0 , 0 ), // #417 {xmm, xmm|m128|mem, i8|u8, } - ROW(3, 1, 1, 0, 110, 45 , 10 , 0 , 0 , 0 ), // #418 {r32|m8|mem|r8lo|r8hi|r16, xmm, i8|u8} - ROW(3, 0, 1, 0, 15 , 45 , 10 , 0 , 0 , 0 ), // #419 {r64|m64|mem, xmm, i8|u8} - ROW(3, 1, 1, 0, 45 , 110, 10 , 0 , 0 , 0 ), // #420 {xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8} - ROW(3, 1, 1, 0, 45 , 28 , 10 , 0 , 0 , 0 ), // #421 {xmm, r32|m32|mem, i8|u8} - ROW(3, 0, 1, 0, 45 , 15 , 10 , 0 , 0 , 0 ), // #422 {xmm, r64|m64|mem, i8|u8} - ROW(3, 1, 1, 0, 59 , 114, 10 , 0 , 0 , 0 ), // #423 {mm|xmm, r32|m16|mem|r16, i8|u8} - ROW(2, 1, 1, 0, 6 , 59 , 0 , 0 , 0 , 0 ), // #424 {r32, mm|xmm} - ROW(2, 1, 1, 0, 45 , 10 , 0 , 0 , 0 , 0 ), // #425 {xmm, i8|u8} - ROW(1, 1, 1, 0, 131, 0 , 0 , 0 , 0 , 0 ), // #426 {r32|m32|mem|r64|m64} - ROW(2, 1, 1, 0, 31 , 82 , 0 , 0 , 0 , 0 ), // #427 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, cl|i8|u8} - ROW(1, 0, 1, 0, 115, 0 , 0 , 0 , 0 , 0 ), // #428 {r32|r64} - ROW(3, 1, 1, 3, 35 , 36 , 100, 0 , 0 , 0 ), // #429 {, , } - ROW(2, 1, 1, 2, 142, 127, 0 , 0 , 0 , 0 ), // #430 {, } - ROW(1, 1, 1, 0, 1 , 0 , 0 , 0 , 0 , 0 ), // #431 {r8lo|r8hi|m8|mem} - ROW(1, 1, 1, 0, 146, 0 , 0 , 0 , 0 , 0 ), // #432 {r16|m16|mem|r32|r64} - ROW(2, 1, 1, 2, 127, 142, 0 , 0 , 0 , 0 ), // #433 {, } - ROW(3, 0, 1, 0, 147, 147, 147, 0 , 0 , 0 ), // #434 {tmm, tmm, tmm} - ROW(2, 0, 1, 0, 147, 92 , 0 , 0 , 0 , 0 ), // #435 {tmm, tmem} - ROW(2, 0, 1, 0, 92 , 147, 0 , 0 , 0 , 0 ), // #436 {tmem, tmm} - ROW(1, 0, 1, 0, 147, 0 , 0 , 0 , 0 , 0 ), // #437 {tmm} - ROW(3, 1, 1, 2, 6 , 35 , 36 , 0 , 0 , 0 ), // #438 {r32, , } - ROW(1, 1, 1, 0, 28 , 0 , 0 , 0 , 0 , 0 ), // #439 {r32|m32|mem} - ROW(1, 1, 1, 0, 148, 0 , 0 , 0 , 0 , 0 ), // #440 {ds:[memBase]} - ROW(6, 1, 1, 0, 51 , 51 , 51 , 51 , 51 , 47 ), // #441 {zmm, zmm, zmm, zmm, zmm, m128|mem} - ROW(6, 1, 1, 0, 45 , 45 , 45 , 45 , 45 , 47 ), // #442 {xmm, xmm, xmm, xmm, xmm, m128|mem} - ROW(3, 1, 1, 0, 45 , 45 , 60 , 0 , 0 , 0 ), // #443 {xmm, xmm, xmm|m64|mem} - ROW(3, 1, 1, 0, 45 , 45 , 88 , 0 , 0 , 0 ), // #444 {xmm, xmm, xmm|m32|mem} - ROW(2, 1, 1, 0, 48 , 47 , 0 , 0 , 0 , 0 ), // #445 {ymm, m128|mem} - ROW(2, 1, 1, 0, 149, 60 , 0 , 0 , 0 , 0 ), // #446 {ymm|zmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 149, 47 , 0 , 0 , 0 , 0 ), // #447 {ymm|zmm, m128|mem} - ROW(2, 1, 1, 0, 51 , 50 , 0 , 0 , 0 , 0 ), // #448 {zmm, m256|mem} - ROW(2, 1, 1, 0, 150, 60 , 0 , 0 , 0 , 0 ), // #449 {xmm|ymm|zmm, xmm|m64|mem} - ROW(2, 1, 1, 0, 150, 88 , 0 , 0 , 0 , 0 ), // #450 {xmm|ymm|zmm, m32|mem|xmm} - ROW(4, 1, 1, 0, 83 , 45 , 60 , 10 , 0 , 0 ), // #451 {xmm|k, xmm, xmm|m64|mem, i8|u8} - ROW(4, 1, 1, 0, 83 , 45 , 88 , 10 , 0 , 0 ), // #452 {xmm|k, xmm, xmm|m32|mem, i8|u8} - ROW(3, 1, 1, 0, 45 , 45 , 131, 0 , 0 , 0 ), // #453 {xmm, xmm, r32|m32|mem|r64|m64} - ROW(3, 1, 1, 0, 46 , 149, 10 , 0 , 0 , 0 ), // #454 {xmm|m128|mem, ymm|zmm, i8|u8} - ROW(4, 1, 1, 0, 45 , 45 , 60 , 10 , 0 , 0 ), // #455 {xmm, xmm, xmm|m64|mem, i8|u8} - ROW(4, 1, 1, 0, 45 , 45 , 88 , 10 , 0 , 0 ), // #456 {xmm, xmm, xmm|m32|mem, i8|u8} - ROW(3, 1, 1, 0, 85 , 151, 10 , 0 , 0 , 0 ), // #457 {k, xmm|m128|ymm|m256|zmm|m512, i8|u8} - ROW(3, 1, 1, 0, 85 , 60 , 10 , 0 , 0 , 0 ), // #458 {k, xmm|m64|mem, i8|u8} - ROW(3, 1, 1, 0, 85 , 88 , 10 , 0 , 0 , 0 ), // #459 {k, xmm|m32|mem, i8|u8} - ROW(1, 1, 1, 0, 63 , 0 , 0 , 0 , 0 , 0 ), // #460 {vm32y} - ROW(1, 1, 1, 0, 64 , 0 , 0 , 0 , 0 , 0 ), // #461 {vm32z} - ROW(1, 1, 1, 0, 67 , 0 , 0 , 0 , 0 , 0 ), // #462 {vm64z} - ROW(4, 1, 1, 0, 51 , 51 , 49 , 10 , 0 , 0 ), // #463 {zmm, zmm, ymm|m256|mem, i8|u8} - ROW(2, 1, 1, 0, 6 , 87 , 0 , 0 , 0 , 0 ), // #464 {r32, xmm|ymm} - ROW(2, 1, 1, 0, 150, 152, 0 , 0 , 0 , 0 ), // #465 {xmm|ymm|zmm, xmm|m8|mem|r32|r8lo|r8hi|r16} - ROW(2, 1, 1, 0, 150, 153, 0 , 0 , 0 , 0 ), // #466 {xmm|ymm|zmm, xmm|m32|mem|r32} - ROW(2, 1, 1, 0, 150, 85 , 0 , 0 , 0 , 0 ), // #467 {xmm|ymm|zmm, k} - ROW(2, 1, 1, 0, 150, 154, 0 , 0 , 0 , 0 ), // #468 {xmm|ymm|zmm, xmm|m16|mem|r32|r16} - ROW(3, 1, 1, 0, 114, 45 , 10 , 0 , 0 , 0 ), // #469 {r32|m16|mem|r16, xmm, i8|u8} - ROW(4, 1, 1, 0, 45 , 45 , 110, 10 , 0 , 0 ), // #470 {xmm, xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8} - ROW(4, 1, 1, 0, 45 , 45 , 28 , 10 , 0 , 0 ), // #471 {xmm, xmm, r32|m32|mem, i8|u8} - ROW(4, 0, 1, 0, 45 , 45 , 15 , 10 , 0 , 0 ), // #472 {xmm, xmm, r64|m64|mem, i8|u8} - ROW(4, 1, 1, 0, 45 , 45 , 114, 10 , 0 , 0 ), // #473 {xmm, xmm, r32|m16|mem|r16, i8|u8} - ROW(2, 1, 1, 0, 85 , 150, 0 , 0 , 0 , 0 ), // #474 {k, xmm|ymm|zmm} - ROW(1, 1, 1, 0, 103, 0 , 0 , 0 , 0 , 0 ), // #475 {rel16|rel32} - ROW(3, 1, 1, 2, 92 , 35 , 36 , 0 , 0 , 0 ), // #476 {mem, , } - ROW(3, 0, 1, 2, 92 , 35 , 36 , 0 , 0 , 0 ) // #477 {mem, , } + ROW(3, 1, 1, 0, 51 , 51 , 60 , 0 , 0 , 0 ), // #355 {xmm, xmm, xmm|m128|mem|i8|u8} + ROW(3, 1, 1, 0, 51 , 53 , 127, 0 , 0 , 0 ), // {xmm, m128|mem, i8|u8|xmm} + ROW(2, 1, 1, 0, 81 , 51 , 0 , 0 , 0 , 0 ), // #357 {vm64x|vm64y, xmm} + ROW(2, 1, 1, 0, 73 , 54 , 0 , 0 , 0 , 0 ), // {vm64z, ymm} + ROW(3, 1, 1, 0, 51 , 51 , 52 , 0 , 0 , 0 ), // #359 {xmm, xmm, xmm|m128|mem} + ROW(3, 1, 1, 0, 51 , 53 , 51 , 0 , 0 , 0 ), // {xmm, m128|mem, xmm} + ROW(2, 1, 1, 0, 68 , 93 , 0 , 0 , 0 , 0 ), // #361 {vm32x, xmm|ymm} + ROW(2, 1, 1, 0, 69 , 57 , 0 , 0 , 0 , 0 ), // {vm32y, zmm} + ROW(1, 1, 0, 1, 38 , 0 , 0 , 0 , 0 , 0 ), // #363 {} + ROW(2, 1, 0, 1, 38 , 10 , 0 , 0 , 0 , 0 ), // #364 {, i8|u8} + ROW(2, 1, 0, 0, 34 , 4 , 0 , 0 , 0 , 0 ), // #365 {r16|m16|mem, r16} + ROW(3, 1, 1, 1, 51 , 52 , 128, 0 , 0 , 0 ), // #366 {xmm, xmm|m128|mem, } + ROW(2, 1, 1, 0, 96 , 129, 0 , 0 , 0 , 0 ), // #367 {bnd, mib} + ROW(2, 1, 1, 0, 96 , 98 , 0 , 0 , 0 , 0 ), // #368 {bnd, mem} + ROW(2, 1, 1, 0, 129, 96 , 0 , 0 , 0 , 0 ), // #369 {mib, bnd} + ROW(1, 1, 1, 0, 130, 0 , 0 , 0 , 0 , 0 ), // #370 {r16|r32|r64} + ROW(1, 1, 1, 1, 38 , 0 , 0 , 0 , 0 , 0 ), // #371 {} + ROW(2, 1, 1, 2, 40 , 41 , 0 , 0 , 0 , 0 ), // #372 {, } + ROW(1, 1, 1, 0, 98 , 0 , 0 , 0 , 0 , 0 ), // #373 {mem} + ROW(1, 1, 1, 0, 28 , 0 , 0 , 0 , 0 , 0 ), // #374 {m64|mem} + ROW(1, 1, 1, 1, 131, 0 , 0 , 0 , 0 , 0 ), // #375 {} + ROW(2, 1, 1, 2, 132, 133, 0 , 0 , 0 , 0 ), // #376 {, } + ROW(3, 1, 1, 0, 51 , 66 , 10 , 0 , 0 , 0 ), // #377 {xmm, xmm|m64|mem, i8|u8} + ROW(3, 1, 1, 0, 51 , 94 , 10 , 0 , 0 , 0 ), // #378 {xmm, xmm|m32|mem, i8|u8} + ROW(5, 0, 1, 4, 53 , 42 , 43 , 134, 135, 0 ), // #379 {m128|mem, , , , } + ROW(5, 1, 1, 4, 28 , 40 , 41 , 106, 136, 0 ), // #380 {m64|mem, , , , } + ROW(4, 1, 1, 4, 41 , 136, 106, 40 , 0 , 0 ), // #381 {, , , } + ROW(2, 0, 1, 2, 42 , 43 , 0 , 0 , 0 , 0 ), // #382 {, } + ROW(2, 1, 1, 0, 63 , 52 , 0 , 0 , 0 , 0 ), // #383 {mm, xmm|m128|mem} + ROW(2, 1, 1, 0, 51 , 123, 0 , 0 , 0 , 0 ), // #384 {xmm, mm|m64|mem} + ROW(2, 1, 1, 0, 63 , 66 , 0 , 0 , 0 , 0 ), // #385 {mm, xmm|m64|mem} + ROW(2, 1, 1, 0, 121, 66 , 0 , 0 , 0 , 0 ), // #386 {r32|r64, xmm|m64|mem} + ROW(2, 1, 1, 0, 51 , 137, 0 , 0 , 0 , 0 ), // #387 {xmm, r32|m32|mem|r64|m64} + ROW(2, 1, 1, 0, 121, 94 , 0 , 0 , 0 , 0 ), // #388 {r32|r64, xmm|m32|mem} + ROW(2, 1, 1, 2, 39 , 38 , 0 , 0 , 0 , 0 ), // #389 {, } + ROW(1, 1, 1, 1, 41 , 0 , 0 , 0 , 0 , 0 ), // #390 {} + ROW(2, 1, 1, 0, 12 , 10 , 0 , 0 , 0 , 0 ), // #391 {i16|u16, i8|u8} + ROW(3, 1, 1, 0, 35 , 51 , 10 , 0 , 0 , 0 ), // #392 {r32|m32|mem, xmm, i8|u8} + ROW(1, 1, 1, 0, 87 , 0 , 0 , 0 , 0 , 0 ), // #393 {m80|mem} + ROW(1, 1, 1, 0, 138, 0 , 0 , 0 , 0 , 0 ), // #394 {m16|m32} + ROW(1, 1, 1, 0, 139, 0 , 0 , 0 , 0 , 0 ), // #395 {m16|m32|m64} + ROW(1, 1, 1, 0, 140, 0 , 0 , 0 , 0 , 0 ), // #396 {m32|m64|m80|st} + ROW(1, 1, 1, 0, 22 , 0 , 0 , 0 , 0 , 0 ), // #397 {m16|mem} + ROW(1, 1, 1, 0, 141, 0 , 0 , 0 , 0 , 0 ), // #398 {ax|m16|mem} + ROW(1, 0, 1, 0, 98 , 0 , 0 , 0 , 0 , 0 ), // #399 {mem} + ROW(2, 1, 1, 0, 142, 143, 0 , 0 , 0 , 0 ), // #400 {al|ax|eax, i8|u8|dx} + ROW(1, 1, 1, 0, 6 , 0 , 0 , 0 , 0 , 0 ), // #401 {r32} + ROW(2, 1, 1, 0, 144, 145, 0 , 0 , 0 , 0 ), // #402 {es:[memBase|zdi], dx} + ROW(1, 1, 1, 0, 10 , 0 , 0 , 0 , 0 , 0 ), // #403 {i8|u8} + ROW(0, 1, 0, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #404 {} + ROW(0, 0, 1, 0, 0 , 0 , 0 , 0 , 0 , 0 ), // #405 {} + ROW(3, 1, 1, 0, 91 , 91 , 91 , 0 , 0 , 0 ), // #406 {k, k, k} + ROW(2, 1, 1, 0, 91 , 91 , 0 , 0 , 0 , 0 ), // #407 {k, k} + ROW(3, 1, 1, 0, 91 , 91 , 10 , 0 , 0 , 0 ), // #408 {k, k, i8|u8} + ROW(1, 1, 1, 1, 146, 0 , 0 , 0 , 0 , 0 ), // #409 {} + ROW(1, 1, 1, 0, 26 , 0 , 0 , 0 , 0 , 0 ), // #410 {m32|mem} + ROW(1, 0, 1, 0, 59 , 0 , 0 , 0 , 0 , 0 ), // #411 {m512|mem} + ROW(2, 1, 1, 0, 130, 147, 0 , 0 , 0 , 0 ), // #412 {r16|r32|r64, mem|m8|m16|m32|m48|m64|m80|m128|m256|m512|m1024} + ROW(1, 1, 1, 0, 34 , 0 , 0 , 0 , 0 , 0 ), // #413 {r16|m16|mem} + ROW(1, 1, 1, 0, 121, 0 , 0 , 0 , 0 , 0 ), // #414 {r32|r64} + ROW(2, 1, 1, 2, 148, 132, 0 , 0 , 0 , 0 ), // #415 {, } + ROW(3, 1, 1, 0, 121, 35 , 14 , 0 , 0 , 0 ), // #416 {r32|r64, r32|m32|mem, i32|u32} + ROW(3, 1, 1, 1, 51 , 51 , 149, 0 , 0 , 0 ), // #417 {xmm, xmm, } + ROW(3, 1, 1, 1, 63 , 63 , 149, 0 , 0 , 0 ), // #418 {mm, mm, } + ROW(3, 1, 1, 3, 131, 106, 40 , 0 , 0 , 0 ), // #419 {, , } + ROW(2, 1, 1, 0, 104, 59 , 0 , 0 , 0 , 0 ), // #420 {es:[memBase], m512|mem} + ROW(2, 1, 1, 0, 63 , 51 , 0 , 0 , 0 , 0 ), // #421 {mm, xmm} + ROW(2, 1, 1, 0, 6 , 51 , 0 , 0 , 0 , 0 ), // #422 {r32, xmm} + ROW(2, 1, 1, 0, 28 , 63 , 0 , 0 , 0 , 0 ), // #423 {m64|mem, mm} + ROW(2, 1, 1, 0, 51 , 63 , 0 , 0 , 0 , 0 ), // #424 {xmm, mm} + ROW(2, 1, 1, 2, 133, 132, 0 , 0 , 0 , 0 ), // #425 {, } + ROW(2, 1, 1, 2, 41 , 106, 0 , 0 , 0 , 0 ), // #426 {, } + ROW(3, 1, 1, 3, 41 , 106, 136, 0 , 0 , 0 ), // #427 {, , } + ROW(2, 1, 1, 0, 150, 142, 0 , 0 , 0 , 0 ), // #428 {u8|dx, al|ax|eax} + ROW(2, 1, 1, 0, 145, 151, 0 , 0 , 0 , 0 ), // #429 {dx, ds:[memBase|zsi]} + ROW(6, 1, 1, 3, 51 , 52 , 10 , 106, 41 , 40 ), // #430 {xmm, xmm|m128|mem, i8|u8, , , } + ROW(6, 1, 1, 3, 51 , 52 , 10 , 128, 41 , 40 ), // #431 {xmm, xmm|m128|mem, i8|u8, , , } + ROW(4, 1, 1, 1, 51 , 52 , 10 , 106, 0 , 0 ), // #432 {xmm, xmm|m128|mem, i8|u8, } + ROW(4, 1, 1, 1, 51 , 52 , 10 , 128, 0 , 0 ), // #433 {xmm, xmm|m128|mem, i8|u8, } + ROW(3, 1, 1, 0, 116, 51 , 10 , 0 , 0 , 0 ), // #434 {r32|m8|mem|r8lo|r8hi|r16, xmm, i8|u8} + ROW(3, 0, 1, 0, 15 , 51 , 10 , 0 , 0 , 0 ), // #435 {r64|m64|mem, xmm, i8|u8} + ROW(3, 1, 1, 0, 51 , 116, 10 , 0 , 0 , 0 ), // #436 {xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8} + ROW(3, 1, 1, 0, 51 , 35 , 10 , 0 , 0 , 0 ), // #437 {xmm, r32|m32|mem, i8|u8} + ROW(3, 0, 1, 0, 51 , 15 , 10 , 0 , 0 , 0 ), // #438 {xmm, r64|m64|mem, i8|u8} + ROW(3, 1, 1, 0, 65 , 120, 10 , 0 , 0 , 0 ), // #439 {mm|xmm, r32|m16|mem|r16, i8|u8} + ROW(2, 1, 1, 0, 6 , 65 , 0 , 0 , 0 , 0 ), // #440 {r32, mm|xmm} + ROW(2, 1, 1, 0, 51 , 10 , 0 , 0 , 0 , 0 ), // #441 {xmm, i8|u8} + ROW(1, 1, 1, 0, 137, 0 , 0 , 0 , 0 , 0 ), // #442 {r32|m32|mem|r64|m64} + ROW(2, 1, 1, 0, 36 , 88 , 0 , 0 , 0 , 0 ), // #443 {r8lo|r8hi|m8|r16|m16|r32|m32|r64|m64|mem, cl|i8|u8} + ROW(1, 0, 1, 0, 121, 0 , 0 , 0 , 0 , 0 ), // #444 {r32|r64} + ROW(3, 1, 1, 3, 40 , 41 , 106, 0 , 0 , 0 ), // #445 {, , } + ROW(2, 1, 1, 2, 148, 133, 0 , 0 , 0 , 0 ), // #446 {, } + ROW(1, 1, 1, 0, 1 , 0 , 0 , 0 , 0 , 0 ), // #447 {r8lo|r8hi|m8|mem} + ROW(1, 1, 1, 0, 152, 0 , 0 , 0 , 0 , 0 ), // #448 {r16|m16|mem|r32|r64} + ROW(2, 1, 1, 2, 133, 148, 0 , 0 , 0 , 0 ), // #449 {, } + ROW(3, 0, 1, 0, 153, 153, 153, 0 , 0 , 0 ), // #450 {tmm, tmm, tmm} + ROW(2, 0, 1, 0, 153, 98 , 0 , 0 , 0 , 0 ), // #451 {tmm, tmem} + ROW(2, 0, 1, 0, 98 , 153, 0 , 0 , 0 , 0 ), // #452 {tmem, tmm} + ROW(1, 0, 1, 0, 153, 0 , 0 , 0 , 0 , 0 ), // #453 {tmm} + ROW(3, 1, 1, 2, 6 , 40 , 41 , 0 , 0 , 0 ), // #454 {r32, , } + ROW(1, 1, 1, 0, 35 , 0 , 0 , 0 , 0 , 0 ), // #455 {r32|m32|mem} + ROW(1, 1, 1, 0, 154, 0 , 0 , 0 , 0 , 0 ), // #456 {ds:[memBase]} + ROW(6, 1, 1, 0, 57 , 57 , 57 , 57 , 57 , 53 ), // #457 {zmm, zmm, zmm, zmm, zmm, m128|mem} + ROW(6, 1, 1, 0, 51 , 51 , 51 , 51 , 51 , 53 ), // #458 {xmm, xmm, xmm, xmm, xmm, m128|mem} + ROW(3, 1, 1, 0, 51 , 51 , 66 , 0 , 0 , 0 ), // #459 {xmm, xmm, xmm|m64|mem} + ROW(3, 1, 1, 0, 51 , 51 , 94 , 0 , 0 , 0 ), // #460 {xmm, xmm, xmm|m32|mem} + ROW(2, 1, 1, 0, 54 , 53 , 0 , 0 , 0 , 0 ), // #461 {ymm, m128|mem} + ROW(2, 1, 1, 0, 155, 66 , 0 , 0 , 0 , 0 ), // #462 {ymm|zmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 155, 53 , 0 , 0 , 0 , 0 ), // #463 {ymm|zmm, m128|mem} + ROW(2, 1, 1, 0, 57 , 56 , 0 , 0 , 0 , 0 ), // #464 {zmm, m256|mem} + ROW(2, 1, 1, 0, 156, 66 , 0 , 0 , 0 , 0 ), // #465 {xmm|ymm|zmm, xmm|m64|mem} + ROW(2, 1, 1, 0, 156, 94 , 0 , 0 , 0 , 0 ), // #466 {xmm|ymm|zmm, m32|mem|xmm} + ROW(4, 1, 1, 0, 89 , 51 , 66 , 10 , 0 , 0 ), // #467 {xmm|k, xmm, xmm|m64|mem, i8|u8} + ROW(4, 1, 1, 0, 89 , 51 , 94 , 10 , 0 , 0 ), // #468 {xmm|k, xmm, xmm|m32|mem, i8|u8} + ROW(3, 1, 1, 0, 51 , 51 , 137, 0 , 0 , 0 ), // #469 {xmm, xmm, r32|m32|mem|r64|m64} + ROW(3, 1, 1, 0, 52 , 155, 10 , 0 , 0 , 0 ), // #470 {xmm|m128|mem, ymm|zmm, i8|u8} + ROW(4, 1, 1, 0, 51 , 51 , 66 , 10 , 0 , 0 ), // #471 {xmm, xmm, xmm|m64|mem, i8|u8} + ROW(4, 1, 1, 0, 51 , 51 , 94 , 10 , 0 , 0 ), // #472 {xmm, xmm, xmm|m32|mem, i8|u8} + ROW(3, 1, 1, 0, 91 , 157, 10 , 0 , 0 , 0 ), // #473 {k, xmm|m128|ymm|m256|zmm|m512, i8|u8} + ROW(3, 1, 1, 0, 91 , 66 , 10 , 0 , 0 , 0 ), // #474 {k, xmm|m64|mem, i8|u8} + ROW(3, 1, 1, 0, 91 , 94 , 10 , 0 , 0 , 0 ), // #475 {k, xmm|m32|mem, i8|u8} + ROW(1, 1, 1, 0, 69 , 0 , 0 , 0 , 0 , 0 ), // #476 {vm32y} + ROW(1, 1, 1, 0, 70 , 0 , 0 , 0 , 0 , 0 ), // #477 {vm32z} + ROW(1, 1, 1, 0, 73 , 0 , 0 , 0 , 0 , 0 ), // #478 {vm64z} + ROW(4, 1, 1, 0, 57 , 57 , 55 , 10 , 0 , 0 ), // #479 {zmm, zmm, ymm|m256|mem, i8|u8} + ROW(2, 1, 1, 0, 6 , 93 , 0 , 0 , 0 , 0 ), // #480 {r32, xmm|ymm} + ROW(2, 1, 1, 0, 156, 158, 0 , 0 , 0 , 0 ), // #481 {xmm|ymm|zmm, xmm|m8|mem|r32|r8lo|r8hi|r16} + ROW(2, 1, 1, 0, 156, 159, 0 , 0 , 0 , 0 ), // #482 {xmm|ymm|zmm, xmm|m32|mem|r32} + ROW(2, 1, 1, 0, 156, 91 , 0 , 0 , 0 , 0 ), // #483 {xmm|ymm|zmm, k} + ROW(2, 1, 1, 0, 156, 160, 0 , 0 , 0 , 0 ), // #484 {xmm|ymm|zmm, xmm|m16|mem|r32|r16} + ROW(3, 1, 1, 0, 120, 51 , 10 , 0 , 0 , 0 ), // #485 {r32|m16|mem|r16, xmm, i8|u8} + ROW(4, 1, 1, 0, 51 , 51 , 116, 10 , 0 , 0 ), // #486 {xmm, xmm, r32|m8|mem|r8lo|r8hi|r16, i8|u8} + ROW(4, 1, 1, 0, 51 , 51 , 35 , 10 , 0 , 0 ), // #487 {xmm, xmm, r32|m32|mem, i8|u8} + ROW(4, 0, 1, 0, 51 , 51 , 15 , 10 , 0 , 0 ), // #488 {xmm, xmm, r64|m64|mem, i8|u8} + ROW(4, 1, 1, 0, 51 , 51 , 120, 10 , 0 , 0 ), // #489 {xmm, xmm, r32|m16|mem|r16, i8|u8} + ROW(2, 1, 1, 0, 91 , 156, 0 , 0 , 0 , 0 ), // #490 {k, xmm|ymm|zmm} + ROW(1, 1, 1, 0, 109, 0 , 0 , 0 , 0 , 0 ), // #491 {rel16|rel32} + ROW(3, 1, 1, 2, 98 , 40 , 41 , 0 , 0 , 0 ), // #492 {mem, , } + ROW(3, 0, 1, 2, 98 , 40 , 41 , 0 , 0 , 0 ) // #493 {mem, , } }; #undef ROW @@ -3373,19 +3392,24 @@ const InstDB::OpSignature InstDB::_opSignatureTable[] = { ROW(F(Gpq) | F(Mem), M(M64) | M(Any), 0, 0x00), ROW(F(I32), 0, 0, 0x00), ROW(F(SReg) | F(CReg) | F(DReg) | F(Mem) | F(I64) | F(U64), M(M64) | M(Any), 0, 0x00), + ROW(F(GpbLo) | F(GpbHi), 0, 0, 0x01), ROW(F(Mem), M(M8) | M(Any), 0, 0x00), ROW(F(SReg) | F(Mem), M(M16) | M(Any), 0, 0x00), ROW(F(SReg) | F(Mem), M(M32) | M(Any), 0, 0x00), ROW(F(Mem), M(M16) | M(Any), 0, 0x00), ROW(F(SReg), 0, 0, 0x00), + ROW(F(Gpw), 0, 0, 0x01), + ROW(F(Gpd), 0, 0, 0x01), + ROW(F(Mem), M(M32) | M(Any), 0, 0x00), + ROW(F(Gpq), 0, 0, 0x01), + ROW(F(Mem), M(M64) | M(Any), 0, 0x00), + ROW(F(GpbLo), 0, 0, 0x01), ROW(F(CReg) | F(DReg), 0, 0, 0x00), ROW(F(Gpq) | F(I32), 0, 0, 0x00), ROW(F(Gpw) | F(Gpd) | F(Gpq) | F(Mem), M(M16) | M(M32) | M(M64) | M(Any), 0, 0x00), ROW(F(I8), 0, 0, 0x00), ROW(F(Gpw) | F(Mem), M(M16) | M(Any), 0, 0x00), ROW(F(Gpd) | F(Mem), M(M32) | M(Any), 0, 0x00), - ROW(F(Mem), M(M32) | M(Any), 0, 0x00), - ROW(F(Mem), M(M64) | M(Any), 0, 0x00), ROW(F(GpbLo) | F(GpbHi) | F(Gpw) | F(Gpd) | F(Gpq) | F(Mem), M(M8) | M(M16) | M(M32) | M(M64) | M(Any), 0, 0x00), ROW(F(Gpq) | F(Mem) | F(I32) | F(U32), M(M64) | M(Any), 0, 0x00), ROW(F(Gpw) | F(Implicit), 0, 0, 0x01), @@ -3400,6 +3424,7 @@ const InstDB::OpSignature InstDB::_opSignatureTable[] = { ROW(F(I8) | F(I16) | F(U16), 0, 0, 0x00), ROW(F(I8) | F(I32) | F(U32), 0, 0, 0x00), ROW(F(I8) | F(I32), 0, 0, 0x00), + ROW(F(I64) | F(U64), 0, 0, 0x00), ROW(F(Xmm), 0, 0, 0x00), ROW(F(Xmm) | F(Mem), M(M128) | M(Any), 0, 0x00), ROW(F(Mem), M(M128) | M(Any), 0, 0x00), @@ -3542,54 +3567,55 @@ const uint8_t InstDB::rwInfoIndexA[Inst::_kIdCount] = { 52, 0, 0, 0, 53, 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 53, 54, 55, 56, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 57, 58, 0, 59, 0, 60, 0, 59, 0, 59, 0, 59, 0, 0, 0, 0, 61, 62, 62, 62, 57, 59, 0, 0, 0, 9, 0, 0, 4, 4, 5, 6, 0, 0, 4, 4, 5, 6, - 0, 0, 63, 64, 64, 65, 46, 24, 36, 65, 51, 64, 64, 66, 67, 67, 68, 69, 69, 70, - 70, 58, 58, 65, 58, 58, 69, 69, 71, 47, 51, 72, 47, 7, 7, 46, 73, 9, 64, 64, - 73, 0, 35, 4, 4, 5, 6, 0, 74, 0, 0, 75, 0, 2, 4, 4, 76, 77, 9, 9, 9, 3, 3, 4, - 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 3, 3, 0, 3, 78, 3, 0, 0, 0, 3, 3, 4, 3, 0, 0, 3, - 3, 4, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 27, 78, 78, 78, 78, 78, 78, 78, 78, 78, - 78, 27, 78, 78, 78, 27, 27, 78, 78, 78, 3, 3, 3, 79, 3, 3, 3, 27, 27, 0, 0, - 0, 0, 3, 3, 4, 4, 3, 3, 4, 4, 4, 4, 3, 3, 4, 4, 80, 81, 82, 24, 24, 24, 81, 81, - 82, 24, 24, 24, 81, 4, 3, 78, 3, 3, 4, 3, 3, 0, 0, 0, 9, 0, 0, 0, 3, 0, 0, - 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 83, 3, 3, 0, 3, 3, 3, 83, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 27, 84, 0, 3, 3, 4, 3, 3, 3, 4, 3, 0, 0, 0, 0, 0, 0, 0, - 3, 85, 7, 86, 85, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 87, 0, 0, 0, 0, 85, 85, 0, - 0, 0, 0, 0, 0, 7, 86, 0, 0, 85, 85, 0, 0, 2, 88, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, - 4, 0, 4, 4, 0, 85, 0, 0, 85, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 7, 26, 86, 0, 0, - 0, 0, 0, 0, 89, 0, 0, 2, 4, 4, 5, 6, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, 15, - 90, 90, 0, 91, 0, 0, 9, 9, 20, 21, 0, 0, 0, 0, 0, 4, 4, 4, 4, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 92, 28, 93, 94, 93, 94, 92, 28, 93, 94, 93, 94, 95, 96, 0, 0, 0, 0, 20, 21, - 97, 97, 98, 9, 0, 73, 99, 99, 9, 99, 9, 98, 9, 98, 0, 98, 9, 98, 9, 99, 28, - 0, 28, 0, 0, 0, 33, 33, 99, 9, 99, 9, 9, 98, 9, 98, 28, 28, 33, 33, 98, 9, 9, - 99, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 100, 100, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 63, 64, 65, 65, 66, 46, 24, 36, 66, 51, 65, 65, 67, 68, 68, 69, 70, 70, + 71, 71, 58, 58, 66, 58, 58, 70, 70, 72, 47, 51, 73, 47, 7, 7, 46, 74, 9, 65, + 65, 74, 0, 35, 4, 4, 5, 6, 0, 75, 0, 0, 76, 0, 2, 4, 4, 77, 78, 9, 9, 9, 3, 3, + 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 3, 3, 0, 3, 79, 3, 0, 0, 0, 3, 3, 4, 3, 0, 0, + 3, 3, 4, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 27, 79, 79, 79, 79, 79, 79, 79, 79, + 79, 79, 27, 79, 79, 79, 27, 27, 79, 79, 79, 3, 3, 3, 80, 3, 3, 3, 27, 27, 0, + 0, 0, 0, 3, 3, 4, 4, 3, 3, 4, 4, 4, 4, 3, 3, 4, 4, 81, 82, 83, 24, 24, 24, 82, + 82, 83, 24, 24, 24, 82, 4, 3, 79, 3, 3, 4, 3, 3, 0, 0, 0, 9, 0, 0, 0, 3, 0, + 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 84, 3, 3, 0, 3, 3, 3, 84, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 27, 85, 0, 3, 3, 4, 3, 3, 3, 4, 3, 0, 0, 0, 0, 0, 0, + 0, 3, 86, 7, 87, 86, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 88, 0, 0, 0, 0, 86, 86, + 0, 0, 0, 0, 0, 0, 7, 87, 0, 0, 86, 86, 0, 0, 2, 89, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 4, 4, 4, 0, 4, 4, 0, 86, 0, 0, 86, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 7, 26, 87, 0, + 0, 0, 0, 0, 0, 90, 0, 0, 2, 4, 4, 5, 6, 0, 0, 0, 0, 0, 0, 0, 9, 0, 0, 0, 0, 0, + 15, 91, 91, 0, 92, 0, 0, 9, 9, 20, 21, 0, 0, 0, 0, 0, 4, 4, 4, 4, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 93, 28, 94, 95, 94, 95, 93, 28, 94, 95, 94, 95, 96, 97, 0, 0, 0, 0, 20, + 21, 98, 98, 99, 9, 0, 74, 100, 100, 9, 100, 9, 99, 9, 99, 0, 99, 9, 99, 9, 100, + 28, 0, 28, 0, 0, 0, 33, 33, 100, 9, 100, 9, 9, 99, 9, 99, 28, 28, 33, 33, + 99, 9, 9, 100, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101, 101, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 27, 101, 59, 59, 0, 0, 0, 0, 0, - 0, 0, 0, 59, 59, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 102, - 102, 46, 103, 102, 102, 102, 102, 102, 102, 102, 102, 0, 104, 104, 0, 69, 69, - 105, 106, 65, 65, 65, 65, 107, 69, 9, 9, 71, 102, 102, 0, 0, 0, 97, 0, 0, 0, - 0, 0, 0, 0, 108, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 109, 33, 110, 110, 28, 111, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 97, 97, 97, - 97, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 59, 59, 59, 59, 7, - 7, 7, 0, 7, 0, 7, 7, 7, 7, 7, 7, 0, 7, 7, 79, 7, 0, 7, 0, 0, 7, 0, 0, 0, 0, 9, - 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 112, 112, 113, 114, 110, 110, 110, 110, 80, 112, - 115, 114, 113, 113, 114, 115, 114, 113, 114, 116, 117, 98, 98, 98, 116, 113, 114, - 115, 114, 113, 114, 112, 114, 116, 117, 98, 98, 98, 116, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 65, - 118, 65, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 27, 102, 59, 59, 0, + 0, 0, 0, 0, 0, 0, 0, 59, 59, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 66, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 103, 103, 46, 104, 103, 103, 103, 103, 103, 103, 103, 103, 0, 105, 105, + 0, 70, 70, 106, 107, 66, 66, 66, 66, 108, 70, 9, 9, 72, 103, 103, 0, 0, 0, + 98, 0, 0, 0, 0, 0, 0, 0, 109, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 110, 33, 111, 111, 28, + 112, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 98, 98, 98, 98, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 59, 59, + 59, 59, 7, 7, 7, 0, 7, 0, 7, 7, 7, 7, 7, 7, 0, 7, 7, 80, 7, 0, 7, 0, 0, 7, 0, + 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 113, 113, 114, 115, 111, 111, 111, 111, + 81, 113, 116, 115, 114, 114, 115, 116, 115, 114, 115, 117, 118, 99, 99, 99, + 117, 114, 115, 116, 115, 114, 115, 113, 115, 117, 118, 99, 99, 99, 117, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 9, 9, 9, 9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 66, 66, 119, 66, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 108, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 100, 100, 0, 0, 9, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 100, 100, 0, 0, 9, 0, 0, 0, 0, 0, 65, 65, 0, 0, - 0, 0, 0, 0, 0, 0, 65, 118, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, 0, 108, 108, - 20, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 119, 120, 119, 120, 0, 121, - 0, 122, 0, 0, 0, 2, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 109, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 101, 101, 0, 0, 9, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 101, 101, 0, 0, 9, 0, 0, 0, 0, 0, 66, + 66, 0, 0, 0, 0, 0, 0, 0, 0, 66, 119, 0, 0, 0, 0, 0, 0, 9, 9, 0, 0, 0, 0, 0, 0, + 0, 109, 109, 20, 21, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 120, 121, 120, 121, + 0, 122, 0, 123, 0, 0, 0, 2, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }; const uint8_t InstDB::rwInfoIndexB[Inst::_kIdCount] = { @@ -3612,58 +3638,58 @@ const uint8_t InstDB::rwInfoIndexB[Inst::_kIdCount] = { 0, 0, 53, 0, 54, 0, 0, 0, 0, 0, 10, 0, 10, 55, 56, 55, 0, 0, 0, 0, 0, 0, 55, 57, 57, 0, 58, 59, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 60, 60, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 5, 61, 0, 0, 0, 0, 62, 0, 63, 20, 64, 20, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 6, 5, 5, 0, 0, - 0, 0, 66, 67, 0, 0, 0, 0, 68, 69, 0, 3, 3, 70, 22, 71, 72, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, 39, - 74, 75, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 76, 0, 0, 0, 0, 0, 0, 0, 10, 10, 10, 10, 10, - 10, 10, 0, 0, 2, 2, 2, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 78, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 79, 79, 80, 79, 80, 80, 80, 79, 79, 81, 82, 0, 83, 0, 0, 0, 0, 0, 84, - 2, 2, 85, 86, 0, 0, 0, 11, 87, 0, 0, 4, 0, 0, 0, 0, 88, 88, 88, 88, 88, 88, + 0, 0, 0, 0, 0, 0, 5, 61, 0, 0, 0, 0, 62, 0, 63, 20, 64, 20, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 65, 0, 0, 0, 0, 0, 0, 6, 5, 5, 0, + 0, 0, 0, 66, 67, 0, 0, 0, 0, 68, 69, 0, 3, 3, 70, 22, 71, 72, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 73, + 39, 74, 75, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 76, 0, 0, 0, 0, 0, 0, 0, 10, 10, 10, 10, + 10, 10, 10, 0, 0, 2, 2, 2, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 64, 0, 0, 0, 0, 0, 0, 0, 0, 78, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 79, 79, 80, 79, 80, 80, 80, 79, 79, 81, 82, 0, 83, 0, 0, 0, 0, 0, + 84, 2, 2, 85, 86, 0, 0, 0, 11, 87, 0, 0, 4, 0, 0, 0, 0, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, 88, - 88, 88, 88, 0, 88, 0, 32, 0, 0, 0, 5, 0, 0, 6, 0, 89, 4, 0, 89, 4, 5, 5, 32, - 19, 90, 79, 90, 0, 0, 0, 0, 0, 0, 0, 0, 0, 91, 0, 90, 92, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 93, 93, 93, 93, 93, 0, 0, 0, 0, 0, 94, 95, 0, 0, 0, 0, 96, - 96, 0, 56, 95, 0, 0, 0, 0, 97, 98, 97, 98, 3, 3, 99, 100, 3, 3, 3, 3, 3, 3, - 0, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 101, 101, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 3, 3, 102, 103, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 104, 0, 0, 0, 0, 0, 0, 105, 0, 106, 107, 108, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 106, 107, 3, 3, 3, 99, 100, 3, 109, 3, 55, 55, 0, - 0, 0, 0, 110, 111, 112, 111, 112, 110, 111, 112, 111, 112, 22, 113, 113, 114, - 115, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 116, 117, 118, 118, 119, - 120, 113, 113, 113, 113, 113, 113, 118, 118, 113, 113, 116, 117, 113, 113, - 116, 117, 113, 113, 116, 117, 113, 113, 113, 113, 113, 113, 118, 118, 118, 118, - 119, 120, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 116, 117, 118, - 118, 119, 120, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 121, 122, 118, - 118, 119, 120, 123, 123, 77, 124, 0, 0, 0, 0, 125, 126, 10, 10, 10, 10, 10, - 10, 10, 10, 126, 127, 0, 0, 128, 129, 84, 84, 128, 129, 3, 3, 3, 3, 3, 3, 3, 130, - 131, 132, 131, 132, 130, 131, 132, 131, 132, 100, 0, 53, 58, 133, 133, 3, - 3, 99, 100, 0, 134, 0, 3, 3, 99, 100, 0, 135, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 136, 137, 137, 138, 139, 139, 0, 0, 0, 0, 0, 0, 0, 140, 0, 0, 141, 0, 0, - 3, 11, 134, 0, 0, 142, 135, 3, 3, 99, 100, 0, 11, 3, 3, 143, 143, 144, 144, - 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, - 101, 3, 0, 0, 0, 0, 0, 0, 3, 118, 145, 145, 3, 3, 3, 3, 66, 67, 3, 3, 3, 3, 68, - 69, 145, 145, 145, 145, 145, 145, 109, 109, 0, 0, 0, 0, 109, 109, 109, 109, - 109, 109, 0, 0, 113, 113, 113, 113, 146, 146, 3, 3, 3, 113, 3, 3, 113, 113, 118, - 118, 147, 147, 147, 3, 147, 3, 113, 113, 113, 113, 113, 3, 0, 0, 0, 0, 70, - 22, 71, 148, 126, 125, 127, 126, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 3, 0, 3, 3, 0, 149, 100, 99, 150, 0, 0, 151, 151, 151, 151, 151, 151, 151, - 151, 151, 151, 151, 151, 113, 113, 3, 3, 133, 133, 3, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 0, 0, 0, 0, 3, 3, 3, 152, 84, 84, 3, 3, 84, 84, 3, 3, 153, 153, 153, - 153, 3, 0, 0, 0, 0, 153, 153, 153, 153, 153, 153, 3, 3, 113, 113, 113, 3, 153, - 153, 3, 3, 113, 113, 113, 3, 3, 145, 84, 84, 84, 3, 3, 3, 154, 155, 154, 3, - 3, 3, 154, 154, 154, 3, 3, 3, 154, 154, 155, 154, 3, 3, 3, 154, 3, 3, 3, 3, - 3, 3, 3, 3, 113, 113, 0, 145, 145, 145, 145, 145, 145, 145, 145, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 3, 128, 129, 0, 0, 128, 129, 0, 0, 128, 129, 0, 129, 84, - 84, 128, 129, 84, 84, 128, 129, 84, 84, 128, 129, 0, 0, 128, 129, 0, 0, 128, - 129, 0, 129, 3, 3, 99, 100, 0, 0, 10, 10, 10, 10, 10, 10, 10, 10, 0, 0, 3, 3, - 3, 3, 3, 3, 0, 0, 128, 129, 91, 3, 3, 99, 100, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, - 0, 0, 0, 0, 56, 56, 156, 0, 0, 0, 0, 0, 0, 0, 0, 0, 80, 0, 0, 0, 0, 0, 157, 157, - 157, 157, 158, 158, 158, 158, 158, 158, 158, 158, 156, 0, 0 + 88, 88, 88, 88, 0, 88, 0, 32, 0, 0, 0, 5, 0, 0, 6, 0, 89, 4, 0, 89, 4, 5, 5, + 32, 19, 90, 79, 90, 0, 0, 0, 0, 0, 0, 0, 0, 0, 91, 0, 90, 92, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 93, 93, 93, 93, 93, 0, 0, 0, 0, 0, 94, 95, 0, 0, 0, 0, + 96, 96, 0, 56, 95, 0, 0, 0, 0, 97, 98, 97, 98, 3, 3, 99, 100, 3, 3, 3, 3, 3, + 3, 0, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 101, 101, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 102, 103, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 104, 0, 0, 0, 0, 0, 0, 105, 0, 106, 107, 108, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 106, 107, 3, 3, 3, 99, 100, 3, 109, 3, 55, 55, + 0, 0, 0, 0, 110, 111, 112, 111, 112, 110, 111, 112, 111, 112, 22, 113, 113, + 114, 115, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 116, 117, 118, 118, + 119, 120, 113, 113, 113, 113, 113, 113, 118, 118, 113, 113, 116, 117, 113, 113, + 116, 117, 113, 113, 116, 117, 113, 113, 113, 113, 113, 113, 118, 118, 118, + 118, 119, 120, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 116, 117, 118, + 118, 119, 120, 113, 113, 116, 117, 113, 113, 116, 117, 113, 113, 121, 122, + 118, 118, 119, 120, 123, 123, 77, 124, 0, 0, 0, 0, 125, 126, 10, 10, 10, 10, 10, + 10, 10, 10, 126, 127, 0, 0, 128, 129, 84, 84, 128, 129, 3, 3, 3, 3, 3, 3, 3, + 130, 131, 132, 131, 132, 130, 131, 132, 131, 132, 100, 0, 53, 58, 133, 133, + 3, 3, 99, 100, 0, 134, 0, 3, 3, 99, 100, 0, 135, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 136, 137, 137, 138, 139, 139, 0, 0, 0, 0, 0, 0, 0, 140, 0, 0, 141, 0, + 0, 3, 11, 134, 0, 0, 142, 135, 3, 3, 99, 100, 0, 11, 3, 3, 143, 143, 144, 144, + 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, + 3, 101, 3, 0, 0, 0, 0, 0, 0, 3, 118, 145, 145, 3, 3, 3, 3, 66, 67, 3, 3, 3, 3, + 68, 69, 145, 145, 145, 145, 145, 145, 109, 109, 0, 0, 0, 0, 109, 109, 109, 109, + 109, 109, 0, 0, 113, 113, 113, 113, 146, 146, 3, 3, 3, 113, 3, 3, 113, 113, + 118, 118, 147, 147, 147, 3, 147, 3, 113, 113, 113, 113, 113, 3, 0, 0, 0, 0, 70, + 22, 71, 148, 126, 125, 127, 126, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 0, 3, 0, + 0, 0, 0, 3, 0, 3, 3, 0, 149, 100, 99, 150, 0, 0, 151, 151, 151, 151, 151, 151, + 151, 151, 151, 151, 151, 151, 113, 113, 3, 3, 133, 133, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 0, 0, 0, 0, 3, 3, 3, 152, 84, 84, 3, 3, 84, 84, 3, 3, 153, 153, + 153, 153, 3, 0, 0, 0, 0, 153, 153, 153, 153, 153, 153, 3, 3, 113, 113, 113, 3, + 153, 153, 3, 3, 113, 113, 113, 3, 3, 145, 84, 84, 84, 3, 3, 3, 154, 155, 154, + 3, 3, 3, 154, 154, 154, 3, 3, 3, 154, 154, 155, 154, 3, 3, 3, 154, 3, 3, 3, + 3, 3, 3, 3, 3, 113, 113, 0, 145, 145, 145, 145, 145, 145, 145, 145, 3, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 3, 3, 128, 129, 0, 0, 128, 129, 0, 0, 128, 129, 0, 129, + 84, 84, 128, 129, 84, 84, 128, 129, 84, 84, 128, 129, 0, 0, 128, 129, 0, 0, 128, + 129, 0, 129, 3, 3, 99, 100, 0, 0, 10, 10, 10, 10, 10, 10, 10, 10, 0, 0, 3, + 3, 3, 3, 3, 3, 0, 0, 128, 129, 91, 3, 3, 99, 100, 0, 0, 0, 0, 3, 3, 3, 3, 3, + 3, 0, 0, 0, 0, 56, 56, 156, 0, 0, 0, 0, 0, 0, 0, 0, 0, 80, 0, 0, 0, 0, 0, 157, + 157, 157, 157, 158, 158, 158, 158, 158, 158, 158, 158, 156, 0, 0 }; const InstDB::RWInfo InstDB::rwInfoA[] = { @@ -3731,69 +3757,70 @@ const InstDB::RWInfo InstDB::rwInfoA[] = { { InstDB::RWInfo::kCategoryGeneric , 0 , { 50, 20, 0 , 0 , 0 , 0 } }, // #61 [ref=1x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 57, 0 , 0 , 0 , 0 , 0 } }, // #62 [ref=3x] { InstDB::RWInfo::kCategoryMov , 29, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #63 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 30, { 10, 5 , 0 , 0 , 0 , 0 } }, // #64 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #65 [ref=14x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 36, 60, 0 , 0 , 0 , 0 } }, // #66 [ref=1x] - { InstDB::RWInfo::kCategoryMovh64 , 12, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #67 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 61, 7 , 0 , 0 , 0 , 0 } }, // #68 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 7 , 0 , 0 , 0 , 0 } }, // #69 [ref=7x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 55, 5 , 0 , 0 , 0 , 0 } }, // #70 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 28, { 44, 9 , 0 , 0 , 0 , 0 } }, // #71 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 62, 20, 0 , 0 , 0 , 0 } }, // #72 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 14, { 11, 3 , 0 , 0 , 0 , 0 } }, // #73 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 17, 29, 0 , 0 , 0 , 0 } }, // #74 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 11, { 3 , 3 , 0 , 0 , 0 , 0 } }, // #75 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 51, 22, 0 , 0 , 0 , 0 } }, // #76 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 51, 65, 0 , 0 , 0 , 0 } }, // #77 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 4 , { 26, 7 , 0 , 0 , 0 , 0 } }, // #78 [ref=18x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 68, 5 , 0 , 0 , 0 , 0 } }, // #79 [ref=2x] - { InstDB::RWInfo::kCategoryVmov1_8 , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #80 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 10, 9 , 0 , 0 , 0 , 0 } }, // #81 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 27, { 10, 13, 0 , 0 , 0 , 0 } }, // #82 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #83 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 0 , 0 , 0 } }, // #84 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 70, 0 , 0 , 0 , 0 } }, // #85 [ref=8x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 37, 9 , 0 , 0 , 0 , 0 } }, // #86 [ref=3x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 71, 0 , 0 , 0 , 0 } }, // #87 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 21, 0 , 0 , 0 , 0 } }, // #88 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 62, 22, 0 , 0 , 0 , 0 } }, // #89 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 74, 3 , 0 , 0 , 0 , 0 } }, // #90 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 43, 0 , 0 , 0 , 0 } }, // #91 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 13, { 76, 5 , 0 , 0 , 0 , 0 } }, // #92 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 13, { 11, 5 , 0 , 0 , 0 , 0 } }, // #93 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 37, { 74, 77, 0 , 0 , 0 , 0 } }, // #94 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 38, { 11, 7 , 0 , 0 , 0 , 0 } }, // #95 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 39, { 11, 9 , 0 , 0 , 0 , 0 } }, // #96 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 11, { 11, 3 , 0 , 0 , 0 , 0 } }, // #97 [ref=7x] - { InstDB::RWInfo::kCategoryVmov2_1 , 40, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #98 [ref=14x] - { InstDB::RWInfo::kCategoryVmov1_2 , 14, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #99 [ref=7x] - { InstDB::RWInfo::kCategoryGeneric , 44, { 74, 43, 0 , 0 , 0 , 0 } }, // #100 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 5 , { 44, 9 , 0 , 0 , 0 , 0 } }, // #101 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 51, { 11, 3 , 0 , 0 , 0 , 0 } }, // #102 [ref=12x] - { InstDB::RWInfo::kCategoryVmovddup , 52, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #103 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 60, 0 , 0 , 0 , 0 } }, // #104 [ref=2x] - { InstDB::RWInfo::kCategoryVmovmskpd , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #105 [ref=1x] - { InstDB::RWInfo::kCategoryVmovmskps , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #106 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 53, { 35, 7 , 0 , 0 , 0 , 0 } }, // #107 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 2 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #108 [ref=4x] - { InstDB::RWInfo::kCategoryGeneric , 15, { 11, 40, 0 , 0 , 0 , 0 } }, // #109 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 7 , 0 , 0 , 0 , 0 } }, // #110 [ref=6x] - { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 13, 0 , 0 , 0 , 0 } }, // #111 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 3 , 0 , 0 , 0 , 0 } }, // #112 [ref=4x] - { InstDB::RWInfo::kCategoryVmov1_4 , 57, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #113 [ref=6x] - { InstDB::RWInfo::kCategoryVmov1_2 , 41, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #114 [ref=9x] - { InstDB::RWInfo::kCategoryVmov1_8 , 58, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #115 [ref=3x] - { InstDB::RWInfo::kCategoryVmov4_1 , 59, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #116 [ref=4x] - { InstDB::RWInfo::kCategoryVmov8_1 , 60, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #117 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 18, { 11, 3 , 0 , 0 , 0 , 0 } }, // #118 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 17, { 44, 9 , 0 , 0 , 0 , 0 } }, // #119 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 32, { 35, 7 , 0 , 0 , 0 , 0 } }, // #120 [ref=2x] - { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 2 , 0 , 0 , 0 , 0 } }, // #121 [ref=1x] - { InstDB::RWInfo::kCategoryGeneric , 51, { 2 , 2 , 0 , 0 , 0 , 0 } } // #122 [ref=1x] + { InstDB::RWInfo::kCategoryMovabs , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #64 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 30, { 10, 5 , 0 , 0 , 0 , 0 } }, // #65 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 3 , 0 , 0 , 0 , 0 } }, // #66 [ref=14x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 36, 60, 0 , 0 , 0 , 0 } }, // #67 [ref=1x] + { InstDB::RWInfo::kCategoryMovh64 , 12, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #68 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 61, 7 , 0 , 0 , 0 , 0 } }, // #69 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 7 , 0 , 0 , 0 , 0 } }, // #70 [ref=7x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 55, 5 , 0 , 0 , 0 , 0 } }, // #71 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 28, { 44, 9 , 0 , 0 , 0 , 0 } }, // #72 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 62, 20, 0 , 0 , 0 , 0 } }, // #73 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 14, { 11, 3 , 0 , 0 , 0 , 0 } }, // #74 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 17, 29, 0 , 0 , 0 , 0 } }, // #75 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 11, { 3 , 3 , 0 , 0 , 0 , 0 } }, // #76 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 51, 22, 0 , 0 , 0 , 0 } }, // #77 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 51, 65, 0 , 0 , 0 , 0 } }, // #78 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 4 , { 26, 7 , 0 , 0 , 0 , 0 } }, // #79 [ref=18x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 68, 5 , 0 , 0 , 0 , 0 } }, // #80 [ref=2x] + { InstDB::RWInfo::kCategoryVmov1_8 , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #81 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 10, 9 , 0 , 0 , 0 , 0 } }, // #82 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 27, { 10, 13, 0 , 0 , 0 , 0 } }, // #83 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 4 , 0 , 0 , 0 , 0 , 0 } }, // #84 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 3 , { 5 , 5 , 0 , 0 , 0 , 0 } }, // #85 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 10, { 2 , 70, 0 , 0 , 0 , 0 } }, // #86 [ref=8x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 37, 9 , 0 , 0 , 0 , 0 } }, // #87 [ref=3x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 16, 71, 0 , 0 , 0 , 0 } }, // #88 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 22, 21, 0 , 0 , 0 , 0 } }, // #89 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 62, 22, 0 , 0 , 0 , 0 } }, // #90 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 74, 3 , 0 , 0 , 0 , 0 } }, // #91 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 8 , { 11, 43, 0 , 0 , 0 , 0 } }, // #92 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 76, 5 , 0 , 0 , 0 , 0 } }, // #93 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 13, { 11, 5 , 0 , 0 , 0 , 0 } }, // #94 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 37, { 74, 77, 0 , 0 , 0 , 0 } }, // #95 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 38, { 11, 7 , 0 , 0 , 0 , 0 } }, // #96 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 39, { 11, 9 , 0 , 0 , 0 , 0 } }, // #97 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 11, { 11, 3 , 0 , 0 , 0 , 0 } }, // #98 [ref=7x] + { InstDB::RWInfo::kCategoryVmov2_1 , 40, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #99 [ref=14x] + { InstDB::RWInfo::kCategoryVmov1_2 , 14, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #100 [ref=7x] + { InstDB::RWInfo::kCategoryGeneric , 44, { 74, 43, 0 , 0 , 0 , 0 } }, // #101 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 5 , { 44, 9 , 0 , 0 , 0 , 0 } }, // #102 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 51, { 11, 3 , 0 , 0 , 0 , 0 } }, // #103 [ref=12x] + { InstDB::RWInfo::kCategoryVmovddup , 52, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #104 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 12, { 35, 60, 0 , 0 , 0 , 0 } }, // #105 [ref=2x] + { InstDB::RWInfo::kCategoryVmovmskpd , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #106 [ref=1x] + { InstDB::RWInfo::kCategoryVmovmskps , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #107 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 53, { 35, 7 , 0 , 0 , 0 , 0 } }, // #108 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 2 , { 3 , 3 , 0 , 0 , 0 , 0 } }, // #109 [ref=4x] + { InstDB::RWInfo::kCategoryGeneric , 15, { 11, 40, 0 , 0 , 0 , 0 } }, // #110 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 11, 7 , 0 , 0 , 0 , 0 } }, // #111 [ref=6x] + { InstDB::RWInfo::kCategoryGeneric , 27, { 11, 13, 0 , 0 , 0 , 0 } }, // #112 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 35, 3 , 0 , 0 , 0 , 0 } }, // #113 [ref=4x] + { InstDB::RWInfo::kCategoryVmov1_4 , 57, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #114 [ref=6x] + { InstDB::RWInfo::kCategoryVmov1_2 , 41, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #115 [ref=9x] + { InstDB::RWInfo::kCategoryVmov1_8 , 58, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #116 [ref=3x] + { InstDB::RWInfo::kCategoryVmov4_1 , 59, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #117 [ref=4x] + { InstDB::RWInfo::kCategoryVmov8_1 , 60, { 0 , 0 , 0 , 0 , 0 , 0 } }, // #118 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 18, { 11, 3 , 0 , 0 , 0 , 0 } }, // #119 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 17, { 44, 9 , 0 , 0 , 0 , 0 } }, // #120 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 32, { 35, 7 , 0 , 0 , 0 , 0 } }, // #121 [ref=2x] + { InstDB::RWInfo::kCategoryGeneric , 11, { 2 , 2 , 0 , 0 , 0 , 0 } }, // #122 [ref=1x] + { InstDB::RWInfo::kCategoryGeneric , 51, { 2 , 2 , 0 , 0 , 0 , 0 } } // #123 [ref=1x] }; const InstDB::RWInfo InstDB::rwInfoB[] = { - { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=734x] + { InstDB::RWInfo::kCategoryGeneric , 0 , { 0 , 0 , 0 , 0 , 0 , 0 } }, // #0 [ref=735x] { InstDB::RWInfo::kCategoryGeneric , 0 , { 1 , 0 , 0 , 0 , 0 , 0 } }, // #1 [ref=5x] { InstDB::RWInfo::kCategoryGeneric , 3 , { 10, 5 , 0 , 0 , 0 , 0 } }, // #2 [ref=7x] { InstDB::RWInfo::kCategoryGeneric , 6 , { 11, 3 , 3 , 0 , 0 , 0 } }, // #3 [ref=186x] @@ -3955,7 +3982,7 @@ const InstDB::RWInfo InstDB::rwInfoB[] = { }; const InstDB::RWInfoOp InstDB::rwInfoOp[] = { - { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, 0 }, // #0 [ref=15421x] + { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, 0 }, // #0 [ref=15433x] { 0x0000000000000003u, 0x0000000000000003u, 0x00, { 0 }, OpRWInfo::kRW | OpRWInfo::kRegPhysId }, // #1 [ref=10x] { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRW | OpRWInfo::kZExt }, // #2 [ref=217x] { 0x0000000000000000u, 0x0000000000000000u, 0xFF, { 0 }, OpRWInfo::kRead }, // #3 [ref=989x] @@ -4038,7 +4065,7 @@ const InstDB::RWInfoOp InstDB::rwInfoOp[] = { }; const InstDB::RWInfoRm InstDB::rwInfoRm[] = { - { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , 0, 0 }, // #0 [ref=1880x] + { InstDB::RWInfoRm::kCategoryNone , 0x00, 0 , 0, 0 }, // #0 [ref=1882x] { InstDB::RWInfoRm::kCategoryConsistent, 0x03, 0 , InstDB::RWInfoRm::kFlagAmbiguous, 0 }, // #1 [ref=8x] { InstDB::RWInfoRm::kCategoryConsistent, 0x02, 0 , 0, 0 }, // #2 [ref=194x] { InstDB::RWInfoRm::kCategoryFixed , 0x02, 16, 0, 0 }, // #3 [ref=122x] diff --git a/src/asmjit/x86/x86instdb.h b/src/asmjit/x86/x86instdb.h index 6c40f6a..6de7527 100644 --- a/src/asmjit/x86/x86instdb.h +++ b/src/asmjit/x86/x86instdb.h @@ -168,6 +168,7 @@ enum Flags : uint32_t { kFlagVsib = 0x00040000u, //!< Instruction uses VSIB instead of legacy SIB. kFlagVex = 0x00080000u, //!< Instruction can be encoded by VEX|XOP (AVX|AVX2|BMI|XOP|...). kFlagEvex = 0x00100000u, //!< Instruction can be encoded by EVEX (AVX512). + kFlagPreferEvex = 0x00200000u, //!< EVEX encoding is preferred over VEX encoding (AVX515_VNNI vs AVX_VNNI). // FPU Flags // --------- @@ -331,6 +332,9 @@ struct CommonInfo { //! Tests whether the instruction uses EVEX (can be set together with VEX if both are encodable). inline bool isVexOrEvex() const noexcept { return hasFlag(kFlagVex | kFlagEvex); } + //! Tests whether the instruction should prefer EVEX prefix instead of VEX prefix. + inline bool preferEvex() const noexcept { return hasFlag(kFlagPreferEvex); } + //! Tests whether the instruction supports AVX512 masking {k}. inline bool hasAvx512K() const noexcept { return hasFlag(kFlagAvx512K); } //! Tests whether the instruction supports AVX512 zeroing {k}{z}. diff --git a/src/asmjit/x86/x86instdb_p.h b/src/asmjit/x86/x86instdb_p.h index 9c48bed..2cd14d8 100644 --- a/src/asmjit/x86/x86instdb_p.h +++ b/src/asmjit/x86/x86instdb_p.h @@ -88,6 +88,7 @@ enum EncodingId : uint32_t { kEncodingX86JmpRel, //!< X86 xbegin. kEncodingX86Lea, //!< X86 lea. kEncodingX86Mov, //!< X86 mov (all possible cases). + kEncodingX86Movabs, //!< X86 movabs. kEncodingX86MovsxMovzx, //!< X86 movsx, movzx. kEncodingX86MovntiMovdiri, //!< X86 movnti/movdiri. kEncodingX86EnqcmdMovdir64b, //!< X86 enqcmd/enqcmds/movdir64b. @@ -239,6 +240,7 @@ struct RWInfo { enum Category : uint8_t { kCategoryGeneric, kCategoryMov, + kCategoryMovabs, kCategoryImul, kCategoryMovh64, kCategoryVmaskmov, diff --git a/test/asmjit_test_assembler.cpp b/test/asmjit_test_assembler.cpp new file mode 100644 index 0000000..559235e --- /dev/null +++ b/test/asmjit_test_assembler.cpp @@ -0,0 +1,83 @@ +// AsmJit - Machine code generation for C++ +// +// * Official AsmJit Home Page: https://asmjit.com +// * Official Github Repository: https://github.com/asmjit/asmjit +// +// Copyright (c) 2008-2020 The AsmJit Authors +// +// This software is provided 'as-is', without any express or implied +// warranty. In no event will the authors be held liable for any damages +// arising from the use of this software. +// +// Permission is granted to anyone to use this software for any purpose, +// including commercial applications, and to alter it and redistribute it +// freely, subject to the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software +// in a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// 3. This notice may not be removed or altered from any source distribution. + +#include +#include +#include +#include + +#include "asmjit_test_assembler.h" +#include "cmdline.h" + +using namespace asmjit; + +#if defined(ASMJIT_BUILD_X86) +bool testX86Assembler(const TestSettings& settings) noexcept; +bool testX64Assembler(const TestSettings& settings) noexcept; +#endif + +int main(int argc, char* argv[]) { + CmdLine cmdLine(argc, argv); + + TestSettings settings {}; + settings.quiet = cmdLine.hasArg("--quiet"); + + printf("AsmJit Assembler Test-Suite v%u.%u.%u:\n\n", + unsigned((ASMJIT_LIBRARY_VERSION >> 16) ), + unsigned((ASMJIT_LIBRARY_VERSION >> 8) & 0xFF), + unsigned((ASMJIT_LIBRARY_VERSION ) & 0xFF)); + + printf("Usage:\n"); + printf(" --help Show usage only\n"); + printf(" --arch= Select architecture to run ('all' by default)\n"); + printf(" --quiet Show only assembling errors [%s]\n", settings.quiet ? "x" : " "); + printf("\n"); + + if (cmdLine.hasArg("--help")) + return 0; + + const char* arch = cmdLine.valueOf("--arch", "all"); + bool x86Failed = false; + bool x64Failed = false; + +#if defined(ASMJIT_BUILD_X86) + if ((strcmp(arch, "all") == 0 || strcmp(arch, "x86") == 0)) + x86Failed = !testX86Assembler(settings); + + if ((strcmp(arch, "all") == 0 || strcmp(arch, "x64") == 0)) + x64Failed = !testX64Assembler(settings); +#endif + + bool failed = x86Failed || x64Failed; + + if (failed) { + if (x86Failed) printf("** X86 test suite failed **\n"); + if (x64Failed) printf("** X64 test suite failed **\n"); + printf("** FAILURE **\n"); + } + else { + printf("** SUCCESS **\n"); + } + + return failed ? 1 : 0; +} diff --git a/test/asmjit_test_assembler.h b/test/asmjit_test_assembler.h new file mode 100644 index 0000000..6f7a549 --- /dev/null +++ b/test/asmjit_test_assembler.h @@ -0,0 +1,96 @@ +// AsmJit - Machine code generation for C++ +// +// * Official AsmJit Home Page: https://asmjit.com +// * Official Github Repository: https://github.com/asmjit/asmjit +// +// Copyright (c) 2008-2020 The AsmJit Authors +// +// This software is provided 'as-is', without any express or implied +// warranty. In no event will the authors be held liable for any damages +// arising from the use of this software. +// +// Permission is granted to anyone to use this software for any purpose, +// including commercial applications, and to alter it and redistribute it +// freely, subject to the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software +// in a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// 3. This notice may not be removed or altered from any source distribution. + +#ifndef ASMJIT_TEST_ASSEMBLER_H_INCLUDED +#define ASMJIT_TEST_ASSEMBLER_H_INCLUDED + +#include +#include + +struct TestSettings { + bool quiet; +}; + +template +class AssemblerTester { +public: + asmjit::Environment env {}; + asmjit::CodeHolder code {}; + AssemblerType assembler {}; + const TestSettings& settings; + + size_t passed {}; + size_t count {}; + + AssemblerTester(uint32_t arch, const TestSettings& settings) noexcept + : env(arch), + settings(settings) {} + + void printHeader(const char* archName) noexcept { + printf("%s assembler tests:\n", archName); + } + + void printSummary() noexcept { + printf(" Passed: %zu / %zu tests\n\n", passed, count); + } + + bool didPass() const noexcept { return passed == count; } + + void beforeInstruction() noexcept { + code.init(env, 0); + code.attach(&assembler); + } + + bool testInstruction(const char* expectedOpcode, const char* s, uint32_t err) noexcept { + count++; + + if (err) { + printf(" !! %s\n" + " <%s>\n", s, asmjit::DebugUtils::errorAsString(err)); + return false; + } + + asmjit::String encodedOpcode; + asmjit::Section* text = code.textSection(); + + encodedOpcode.appendHex(text->data(), text->bufferSize()); + if (encodedOpcode != expectedOpcode) { + printf(" !! [%s] <- %s\n" + " [%s] (Expected)\n", encodedOpcode.data(), s, expectedOpcode); + return false; + } + + if (!settings.quiet) + printf(" OK [%s] <- %s\n", encodedOpcode.data(), s); + + passed++; + return true; + } + + void afterInstruction() noexcept { + code.reset(); + } +}; + +#endif // ASMJIT_TEST_ASSEMBLER_H_INCLUDED + diff --git a/test/asmjit_test_assembler_x86.cpp b/test/asmjit_test_assembler_x86.cpp new file mode 100644 index 0000000..323a2da --- /dev/null +++ b/test/asmjit_test_assembler_x86.cpp @@ -0,0 +1,604 @@ +// AsmJit - Machine code generation for C++ +// +// * Official AsmJit Home Page: https://asmjit.com +// * Official Github Repository: https://github.com/asmjit/asmjit +// +// Copyright (c) 2008-2020 The AsmJit Authors +// +// This software is provided 'as-is', without any express or implied +// warranty. In no event will the authors be held liable for any damages +// arising from the use of this software. +// +// Permission is granted to anyone to use this software for any purpose, +// including commercial applications, and to alter it and redistribute it +// freely, subject to the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software +// in a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// 3. This notice may not be removed or altered from any source distribution. + +#include +#if defined(ASMJIT_BUILD_X86) + +#include +#include +#include +#include + +#include "asmjit_test_assembler.h" +#include "cmdline.h" + +using namespace asmjit; + +#define TEST_INSTRUCTION(OPCODE, ...) \ + do { \ + tester.beforeInstruction(); \ + tester.testInstruction(OPCODE, #__VA_ARGS__, tester.assembler.__VA_ARGS__); \ + tester.afterInstruction(); \ + } while (0) + +bool testX86Assembler(const TestSettings& settings) noexcept { + using namespace x86; + + AssemblerTester tester(Environment::kArchX86, settings); + tester.printHeader("X86"); + + // Base Instructions. + TEST_INSTRUCTION("8AE0" , mov(ah, al)); + TEST_INSTRUCTION("8AF0" , mov(dh, al)); + TEST_INSTRUCTION("8BC3" , mov(eax, ebx)); + TEST_INSTRUCTION("89D8" , mod_mr().mov(eax, ebx)); + TEST_INSTRUCTION("B800000000" , mov(eax, 0)); + TEST_INSTRUCTION("BB00000000" , mov(ebx, 0)); + TEST_INSTRUCTION("B8FFFFFFFF" , mov(eax, 0xFFFFFFFF)); + TEST_INSTRUCTION("8CE0" , mov(eax, fs)); + TEST_INSTRUCTION("8EE0" , mov(fs, eax)); + TEST_INSTRUCTION("8B10" , mov(edx, ptr(eax))); + TEST_INSTRUCTION("8B10" , mov(edx, ptr(eax, 0))); + TEST_INSTRUCTION("8B9080000000" , mov(edx, ptr(eax, 128))); + TEST_INSTRUCTION("8B1408" , mov(edx, ptr(eax, ecx))); + TEST_INSTRUCTION("8B940880000000" , mov(edx, ptr(eax, ecx, 0, 128))); + TEST_INSTRUCTION("8B1408" , mov(edx, ptr(eax, ecx))); + TEST_INSTRUCTION("8B544820" , mov(edx, ptr(eax, ecx, 1, 32))); + TEST_INSTRUCTION("8B548840" , mov(edx, ptr(eax, ecx, 2, 64))); + TEST_INSTRUCTION("8B94C800010000" , mov(edx, ptr(eax, ecx, 3, 128 + 128))); + TEST_INSTRUCTION("8B1408" , mov(edx, ptr(eax, ecx))); + TEST_INSTRUCTION("8B940880000000" , mov(edx, ptr(eax, ecx, 0, 128))); + TEST_INSTRUCTION("8B1408" , mov(edx, ptr(eax, ecx))); + TEST_INSTRUCTION("8B544820" , mov(edx, ptr(eax, ecx, 1, 32))); + TEST_INSTRUCTION("8B54C802" , mov(edx, ptr(eax, ecx, 3, 2))); + TEST_INSTRUCTION("0F20C0" , mov(eax, cr0)); + TEST_INSTRUCTION("F00F20C0" , mov(eax, cr8)); + TEST_INSTRUCTION("A344332211" , mov(ptr(0x11223344), eax)); + TEST_INSTRUCTION("890544332211" , mod_mr().mov(ptr(0x11223344), eax)); + TEST_INSTRUCTION("891D44332211" , mov(ptr(0x11223344), ebx)); + TEST_INSTRUCTION("0FBE07" , movsx(eax, byte_ptr(edi))); + TEST_INSTRUCTION("0FBF07" , movsx(eax, word_ptr(edi))); + TEST_INSTRUCTION("0FB607" , movzx(eax, byte_ptr(edi))); + TEST_INSTRUCTION("0FB6C6" , movzx(eax, dh)); + TEST_INSTRUCTION("0FB707" , movzx(eax, word_ptr(edi))); + TEST_INSTRUCTION("03D9" , add(ebx, ecx)); + TEST_INSTRUCTION("83C001" , add(eax, 1)); + TEST_INSTRUCTION("0504030201" , add(eax, 0x01020304)); + TEST_INSTRUCTION("66050201" , add(ax, 0x0102)); + TEST_INSTRUCTION("6603849004030201" , add(ax, ptr(eax, edx, 2, 0x01020304))); + TEST_INSTRUCTION("F00118" , lock().add(ptr(eax), ebx)); + TEST_INSTRUCTION("F00FC138" , lock().xadd(ptr(eax), edi)); + TEST_INSTRUCTION("660FBA2001" , bt(word_ptr(eax), 1)); + TEST_INSTRUCTION("0FBA2001" , bt(dword_ptr(eax), 1)); + TEST_INSTRUCTION("FE00" , inc(byte_ptr(eax))); + TEST_INSTRUCTION("66FF00" , inc(word_ptr(eax))); + TEST_INSTRUCTION("FF00" , inc(dword_ptr(eax))); + TEST_INSTRUCTION("F6D8" , neg(al)); + TEST_INSTRUCTION("F6DC" , neg(ah)); + TEST_INSTRUCTION("F7D8" , neg(eax)); + TEST_INSTRUCTION("F7D0" , not_(eax)); + TEST_INSTRUCTION("0F95C3" , setnz(bl)); + TEST_INSTRUCTION("0F94C7" , setz(bh)); + TEST_INSTRUCTION("F600FF" , test(byte_ptr(eax), 0xFF)); + TEST_INSTRUCTION("66F700FF00" , test(word_ptr(eax), 0xFF)); + TEST_INSTRUCTION("F700FF000000" , test(dword_ptr(eax), 0xFF)); + TEST_INSTRUCTION("A836" , test(al, 0x36)); + TEST_INSTRUCTION("F6C436" , test(ah, 0x36)); + TEST_INSTRUCTION("50" , push(eax)); + TEST_INSTRUCTION("51" , push(ecx)); + TEST_INSTRUCTION("52" , push(edx)); + TEST_INSTRUCTION("53" , push(ebx)); + TEST_INSTRUCTION("54" , push(esp)); + TEST_INSTRUCTION("55" , push(ebp)); + TEST_INSTRUCTION("56" , push(esi)); + TEST_INSTRUCTION("57" , push(edi)); + TEST_INSTRUCTION("0E" , push(cs)); + TEST_INSTRUCTION("16" , push(ss)); + TEST_INSTRUCTION("1E" , push(ds)); + TEST_INSTRUCTION("06" , push(es)); + TEST_INSTRUCTION("0FA0" , push(fs)); + TEST_INSTRUCTION("0FA8" , push(gs)); + TEST_INSTRUCTION("C8010002" , enter(1, 2)); + TEST_INSTRUCTION("C9" , leave()); + TEST_INSTRUCTION("FF10" , call(ptr(eax))); + TEST_INSTRUCTION("FF10" , call(dword_ptr(eax))); + TEST_INSTRUCTION("66C501" , lds(ax, ptr(ecx))); + TEST_INSTRUCTION("C501" , lds(eax, ptr(ecx))); + TEST_INSTRUCTION("66C401" , les(ax, ptr(ecx))); + TEST_INSTRUCTION("C401" , les(eax, ptr(ecx))); + TEST_INSTRUCTION("660FB401" , lfs(ax, ptr(ecx))); + TEST_INSTRUCTION("0FB401" , lfs(eax, ptr(ecx))); + TEST_INSTRUCTION("660FB501" , lgs(ax, ptr(ecx))); + TEST_INSTRUCTION("0FB501" , lgs(eax, ptr(ecx))); + TEST_INSTRUCTION("660FB201" , lss(ax, ptr(ecx))); + TEST_INSTRUCTION("0FB201" , lss(eax, ptr(ecx))); + + // NOP. + TEST_INSTRUCTION("90" , nop()); + TEST_INSTRUCTION("660F1F0400" , nop(word_ptr(eax, eax))); + TEST_INSTRUCTION("660F1F0400" , nop(word_ptr(eax, eax), ax)); + TEST_INSTRUCTION("660F1F1C00" , nop(word_ptr(eax, eax), bx)); + TEST_INSTRUCTION("0F1F0400" , nop(dword_ptr(eax, eax))); + TEST_INSTRUCTION("0F1F0400" , nop(dword_ptr(eax, eax), eax)); + TEST_INSTRUCTION("0F1F1C00" , nop(dword_ptr(eax, eax), ebx)); + + // LEA. + TEST_INSTRUCTION("67668D00" , lea(ax, ptr(bx, si))); + TEST_INSTRUCTION("67668D01" , lea(ax, ptr(bx, di))); + TEST_INSTRUCTION("67668D02" , lea(ax, ptr(bp, si))); + TEST_INSTRUCTION("67668D03" , lea(ax, ptr(bp, di))); + TEST_INSTRUCTION("67668D04" , lea(ax, ptr(si))); + TEST_INSTRUCTION("67668D05" , lea(ax, ptr(di))); + TEST_INSTRUCTION("67668D4600" , lea(ax, ptr(bp))); + TEST_INSTRUCTION("67668D07" , lea(ax, ptr(bx))); + TEST_INSTRUCTION("67668D4010" , lea(ax, ptr(bx, si, 0, 0x10))); + TEST_INSTRUCTION("67668D4120" , lea(ax, ptr(bx, di, 0, 0x20))); + TEST_INSTRUCTION("67668D4240" , lea(ax, ptr(bp, si, 0, 0x40))); + TEST_INSTRUCTION("67668D4360" , lea(ax, ptr(bp, di, 0, 0x60))); + TEST_INSTRUCTION("67668D848000" , lea(ax, ptr(si, 0x80))); + TEST_INSTRUCTION("67668D85A000" , lea(ax, ptr(di, 0xA0))); + TEST_INSTRUCTION("67668D86C000" , lea(ax, ptr(bp, 0xC0))); + TEST_INSTRUCTION("67668D87FF01" , lea(ax, ptr(bx, 0x01FF))); + TEST_INSTRUCTION("678D00" , lea(eax, ptr(bx, si))); + TEST_INSTRUCTION("678D01" , lea(eax, ptr(bx, di))); + TEST_INSTRUCTION("8D0433" , lea(eax, ptr(ebx, esi))); + TEST_INSTRUCTION("8D043B" , lea(eax, ptr(ebx, edi))); + TEST_INSTRUCTION("8D0500000000" , lea(eax, ptr(0))); + + // XACQUIRE|XRELEASE|RTM. + TEST_INSTRUCTION("C6F811" , xabort(0x11)); + TEST_INSTRUCTION("F2F00108" , xacquire().lock().add(dword_ptr(eax), ecx)); + TEST_INSTRUCTION("F3F00108" , xrelease().lock().add(dword_ptr(eax), ecx)); + + // BND. + TEST_INSTRUCTION("660F1ACA" , bndmov(bnd1, bnd2)); + TEST_INSTRUCTION("F20F1ACF" , bndcu(bnd1, edi)); + TEST_INSTRUCTION("0F1A0408" , bndldx(bnd0, ptr(eax, ecx))); + TEST_INSTRUCTION("0F1B0C08" , bndstx(ptr(eax, ecx), bnd1)); + + // BMI+. + TEST_INSTRUCTION("66F30FB8C2" , popcnt(ax, dx)); + TEST_INSTRUCTION("F30FB8C2" , popcnt(eax, edx)); + TEST_INSTRUCTION("66F30FBDC2" , lzcnt(ax, dx)); + TEST_INSTRUCTION("F30FBDC2" , lzcnt(eax, edx)); + TEST_INSTRUCTION("66F30FBCC2" , tzcnt(ax, dx)); + TEST_INSTRUCTION("F30FBCC2" , tzcnt(eax, edx)); + + // CRC32. + TEST_INSTRUCTION("F20F38F0C7" , crc32(eax, bh)); + TEST_INSTRUCTION("66F20F38F1C3" , crc32(eax, bx)); + TEST_INSTRUCTION("F20F38F1C1" , crc32(eax, ecx)); + TEST_INSTRUCTION("F20F38F006" , crc32(eax, byte_ptr(esi))); + TEST_INSTRUCTION("66F20F38F106" , crc32(eax, word_ptr(esi))); + TEST_INSTRUCTION("F20F38F106" , crc32(eax, dword_ptr(esi))); + + // FPU. + TEST_INSTRUCTION("9B" , fwait()); + TEST_INSTRUCTION("D800" , fadd(dword_ptr(eax))); + TEST_INSTRUCTION("DC00" , fadd(qword_ptr(eax))); + + // MMX & SSE. + TEST_INSTRUCTION("0F6FC1" , movq(mm0, mm1)); + TEST_INSTRUCTION("0F6E00" , movd(mm0, ptr(eax))); + TEST_INSTRUCTION("0F6F0418" , movq(mm0, ptr(eax, ebx))); + TEST_INSTRUCTION("0F7E38" , movd(ptr(eax), mm7)); + TEST_INSTRUCTION("0F7F0418" , movq(ptr(eax, ebx), mm0)); + TEST_INSTRUCTION("F30F7EC1" , movq(xmm0, xmm1)); + TEST_INSTRUCTION("660F6E0418" , movd(xmm0, ptr(eax, ebx))); + TEST_INSTRUCTION("F30F7E0418" , movq(xmm0, ptr(eax, ebx))); + TEST_INSTRUCTION("660F7E0C18" , movd(ptr(eax, ebx), xmm1)); + TEST_INSTRUCTION("660FD60C18" , movq(ptr(eax, ebx), xmm1)); + TEST_INSTRUCTION("0F280498" , movaps(xmm0, ptr(eax, ebx, 2))); + TEST_INSTRUCTION("660F280498" , movapd(xmm0, ptr(eax, ebx, 2))); + TEST_INSTRUCTION("660F6F0498" , movdqa(xmm0, ptr(eax, ebx, 2))); + TEST_INSTRUCTION("0F290C98" , movaps(ptr(eax, ebx, 2), xmm1)); + TEST_INSTRUCTION("660F290C98" , movapd(ptr(eax, ebx, 2), xmm1)); + TEST_INSTRUCTION("660F7F0C98" , movdqa(ptr(eax, ebx, 2), xmm1)); + TEST_INSTRUCTION("F30F2DC1" , cvtss2si(eax, xmm1)); + TEST_INSTRUCTION("F20F2DC1" , cvtsd2si(eax, xmm1)); + TEST_INSTRUCTION("F30F2AC2" , cvtsi2ss(xmm0, edx)); + TEST_INSTRUCTION("F20F2AC2" , cvtsi2sd(xmm0, edx)); + TEST_INSTRUCTION("660F3A41C100" , dppd(xmm0, xmm1, 0)); + TEST_INSTRUCTION("0FDBC1" , pand(mm0, mm1)); + TEST_INSTRUCTION("660FDBC1" , pand(xmm0, xmm1)); + TEST_INSTRUCTION("660FFDC1" , paddw(xmm0, xmm1)); + + // AVX & AVX512. + TEST_INSTRUCTION("C5F96E5A10" , vmovd(xmm3, dword_ptr(edx, 0x10))); + TEST_INSTRUCTION("C5FA7E5A10" , vmovq(xmm3, qword_ptr(edx, 0x10))); + TEST_INSTRUCTION("C5F97E5A10" , vmovd(dword_ptr(edx, 0x10), xmm3)); + TEST_INSTRUCTION("C5F9D65A10" , vmovq(qword_ptr(edx, 0x10), xmm3)); + TEST_INSTRUCTION("C5F96EEB" , vmovd(xmm5, ebx)); + TEST_INSTRUCTION("C5F97EEB" , vmovd(ebx, xmm5)); + TEST_INSTRUCTION("C5FA7EC1" , vmovq(xmm0, xmm1)); + TEST_INSTRUCTION("62F17D086EC0" , evex().vmovd(xmm0, eax)); + TEST_INSTRUCTION("62F17D087EC0" , evex().vmovd(eax, xmm0)); + TEST_INSTRUCTION("C5F5FDC7" , vpaddw(ymm0, ymm1, ymm7)); + TEST_INSTRUCTION("C4E37141C200" , vdppd(xmm0, xmm1, xmm2, 0)); + TEST_INSTRUCTION("62F1F5D95800" , k(k1).z().vaddpd(zmm0, zmm1, ptr(eax)._1to8())); + TEST_INSTRUCTION("C5F058C2" , vaddps(xmm0, xmm1, xmm2)); + TEST_INSTRUCTION("62F1748858C2" , z().vaddps(xmm0, xmm1, xmm2)); + TEST_INSTRUCTION("62F1748958C2" , k(k1).z().vaddps(xmm0, xmm1, xmm2)); + TEST_INSTRUCTION("62F16C4FC25498040F" , k(k7).vcmpps(k2, zmm2, zmmword_ptr(eax, ebx, 2, 256), 15)); + TEST_INSTRUCTION("62F16C5FC25498400F" , k(k7).vcmpps(k2, zmm2, dword_ptr(eax, ebx, 2, 256)._1to16(), 15)); + TEST_INSTRUCTION("C5FA2DC1" , vcvtss2si(eax, xmm1)); + TEST_INSTRUCTION("C5FB2DC1" , vcvtsd2si(eax, xmm1)); + TEST_INSTRUCTION("C5F22AC2" , vcvtsi2ss(xmm0, xmm1, edx)); + TEST_INSTRUCTION("C5F32AC2" , vcvtsi2sd(xmm0, xmm1, edx)); + TEST_INSTRUCTION("C5FBE63B" , vcvtpd2dq(xmm7, xmmword_ptr(ebx))); + TEST_INSTRUCTION("C5FFE63B" , vcvtpd2dq(xmm7, ymmword_ptr(ebx))); + TEST_INSTRUCTION("C5F95A3B" , vcvtpd2ps(xmm7, xmmword_ptr(ebx))); + TEST_INSTRUCTION("C5FD5A3B" , vcvtpd2ps(xmm7, ymmword_ptr(ebx))); + TEST_INSTRUCTION("C5F95AC1" , vcvtpd2ps(xmm0, xmm1)); + TEST_INSTRUCTION("C5F95A03" , vcvtpd2ps(xmm0, xmmword_ptr(ebx))); + TEST_INSTRUCTION("C5FD5AC1" , vcvtpd2ps(xmm0, ymm1)); + TEST_INSTRUCTION("C5FD5A03" , vcvtpd2ps(xmm0, ymmword_ptr(ebx))); + TEST_INSTRUCTION("62F1FD485AC1" , vcvtpd2ps(ymm0, zmm1)); + TEST_INSTRUCTION("62F1FD485A03" , vcvtpd2ps(ymm0, zmmword_ptr(ebx))); + TEST_INSTRUCTION("62F1FC08793B" , vcvtpd2udq(xmm7, xmmword_ptr(ebx))); + TEST_INSTRUCTION("62F1FC28793B" , vcvtpd2udq(xmm7, ymmword_ptr(ebx))); + TEST_INSTRUCTION("62F1FC085B3B" , vcvtqq2ps(xmm7, xmmword_ptr(ebx))); + TEST_INSTRUCTION("62F1FC285B3B" , vcvtqq2ps(xmm7, ymmword_ptr(ebx))); + TEST_INSTRUCTION("C5F9E63B" , vcvttpd2dq(xmm7, xmmword_ptr(ebx))); + TEST_INSTRUCTION("C5FDE63B" , vcvttpd2dq(xmm7, ymmword_ptr(ebx))); + TEST_INSTRUCTION("62F1FC08783B" , vcvttpd2udq(xmm7, xmmword_ptr(ebx))); + TEST_INSTRUCTION("62F1FC28783B" , vcvttpd2udq(xmm7, ymmword_ptr(ebx))); + TEST_INSTRUCTION("62F1FF087A3B" , vcvtuqq2ps(xmm7, xmmword_ptr(ebx))); + TEST_INSTRUCTION("62F1FF287A3B" , vcvtuqq2ps(xmm7, ymmword_ptr(ebx))); + TEST_INSTRUCTION("62F3FD08663F01" , vfpclasspd(k7, xmmword_ptr(edi), 0x01)); + TEST_INSTRUCTION("62F3FD28663F01" , vfpclasspd(k7, ymmword_ptr(edi), 0x01)); + TEST_INSTRUCTION("62F3FD48663F01" , vfpclasspd(k7, zmmword_ptr(edi), 0x01)); + TEST_INSTRUCTION("62F37D08663F01" , vfpclassps(k7, xmmword_ptr(edi), 0x01)); + TEST_INSTRUCTION("62F37D28663F01" , vfpclassps(k7, ymmword_ptr(edi), 0x01)); + TEST_INSTRUCTION("62F37D48663F01" , vfpclassps(k7, zmmword_ptr(edi), 0x01)); + TEST_INSTRUCTION("C4E2F990040500000000" , vpgatherdq(xmm0, ptr(0, xmm0), xmm0)); + TEST_INSTRUCTION("C4E2FD91040500000000" , vpgatherqq(ymm0, ptr(0, ymm0), ymm0)); + TEST_INSTRUCTION("C4E2E9920C00" , vgatherdpd(xmm1, ptr(eax, xmm0), xmm2)); + TEST_INSTRUCTION("62F36D083ECB00" , vpcmpub(k1, xmm2, xmm3, 0x0)); + TEST_INSTRUCTION("62F26D48CF4C1101" , vgf2p8mulb(zmm1, zmm2, zmmword_ptr(ecx, edx, 0, 64))); + TEST_INSTRUCTION("62F3ED48CE4C11010F" , vgf2p8affineqb(zmm1, zmm2, zmmword_ptr(ecx, edx, 0, 64), 15)); + TEST_INSTRUCTION("62F3ED48CF4C11010F" , vgf2p8affineinvqb(zmm1, zmm2, zmmword_ptr(ecx, edx, 0, 64), 15)); + TEST_INSTRUCTION("62F2674868246D00F8FFFF" , vp2intersectd(k4, k5, zmm3, zmmword_ptr(0xFFFFF800, ebp, 1))); + + // AVX512_VNNI vs AVX_VNNI. + TEST_INSTRUCTION("62F2552850F4" , vpdpbusd(ymm6, ymm5, ymm4)); + TEST_INSTRUCTION("C4E25550F4" , vex().vpdpbusd(ymm6, ymm5, ymm4)); + + tester.printSummary(); + return tester.didPass(); +} + +bool testX64Assembler(const TestSettings& settings) noexcept { + using namespace x86; + + AssemblerTester tester(Environment::kArchX64, settings); + tester.printHeader("X64"); + + // Base Instructions. + TEST_INSTRUCTION("B800000000" , mov(eax, 0)); + TEST_INSTRUCTION("BB00000000" , mov(ebx, 0)); + TEST_INSTRUCTION("48C7C300000000" , mov(rbx, 0)); + TEST_INSTRUCTION("48BB8877665544332211" , mov(rbx, 0x001122334455667788)); + TEST_INSTRUCTION("48BB0000000000000000" , long_().mov(rbx, 0)); + TEST_INSTRUCTION("8AE0" , mov(ah, al)); + TEST_INSTRUCTION("8AF0" , mov(dh, al)); + TEST_INSTRUCTION("B8E8030000" , mov(eax, 1000)); + TEST_INSTRUCTION("0F20C0" , mov(rax, cr0)); + TEST_INSTRUCTION("440F20C0" , mov(rax, cr8)); + TEST_INSTRUCTION("488B0500000000" , mov(rax, ptr(rip))); + TEST_INSTRUCTION("4A8B0460" , mov(rax, ptr(rax, r12, 1))); + TEST_INSTRUCTION("4A8B0468" , mov(rax, ptr(rax, r13, 1))); + TEST_INSTRUCTION("4A8B846000010000" , mov(rax, ptr(rax, r12, 1, 256))); + TEST_INSTRUCTION("89042544332211" , mov(ptr_abs(0x11223344), eax)); + TEST_INSTRUCTION("891C2544332211" , mov(ptr_abs(0x11223344), ebx)); + TEST_INSTRUCTION("A38877665544332211" , mov(ptr_abs(0x1122334455667788), eax)); + TEST_INSTRUCTION("A34433221100000000" , movabs(ptr(0x0000000011223344), eax)); + TEST_INSTRUCTION("A38877665544332211" , movabs(ptr(0x1122334455667788), eax)); + TEST_INSTRUCTION("48A1EFCDAB8967452301" , movabs(rax, ptr(0x123456789ABCDEF))); + TEST_INSTRUCTION("0FBE07" , movsx(eax, byte_ptr(rdi))); + TEST_INSTRUCTION("480FBE07" , movsx(rax, byte_ptr(rdi))); + TEST_INSTRUCTION("0FBF07" , movsx(eax, word_ptr(rdi))); + TEST_INSTRUCTION("480FBF07" , movsx(rax, word_ptr(rdi))); + TEST_INSTRUCTION("486307" , movsxd(rax, ptr(rdi))); + TEST_INSTRUCTION("486307" , movsxd(rax, dword_ptr(rdi))); + TEST_INSTRUCTION("6663C3" , movsxd(ax, bx)); + TEST_INSTRUCTION("63C3" , movsxd(eax, ebx)); + TEST_INSTRUCTION("4863C3" , movsxd(rax, ebx)); + TEST_INSTRUCTION("0FB6C6" , movzx(eax, dh)); + TEST_INSTRUCTION("0FB607" , movzx(eax, byte_ptr(rdi))); + TEST_INSTRUCTION("480FB607" , movzx(rax, byte_ptr(rdi))); + TEST_INSTRUCTION("440FB6FA" , movzx(r15d, dl)); + TEST_INSTRUCTION("440FB6FD" , movzx(r15d, bpl)); + TEST_INSTRUCTION("0FB707" , movzx(eax, word_ptr(rdi))); + TEST_INSTRUCTION("480FB707" , movzx(rax, word_ptr(rdi))); + TEST_INSTRUCTION("03D9" , add(ebx, ecx)); + TEST_INSTRUCTION("83C001" , add(eax, 1)); + TEST_INSTRUCTION("0504030201" , add(eax, 0x01020304)); + TEST_INSTRUCTION("66050201" , add(ax, 0x0102)); + TEST_INSTRUCTION("6603849004030201" , add(ax, ptr(rax, rdx, 2, 0x01020304))); + TEST_INSTRUCTION("F00118" , lock().add(ptr(rax), ebx)); + TEST_INSTRUCTION("F0480FC138" , lock().xadd(ptr(rax), rdi)); + TEST_INSTRUCTION("660FC8" , bswap(ax)); + TEST_INSTRUCTION("0FC8" , bswap(eax)); + TEST_INSTRUCTION("480FC8" , bswap(rax)); + TEST_INSTRUCTION("660FBA2001" , bt(word_ptr(rax), 1)); + TEST_INSTRUCTION("0FBA2001" , bt(dword_ptr(rax), 1)); + TEST_INSTRUCTION("480FBA2001" , bt(qword_ptr(rax), 1)); + TEST_INSTRUCTION("FE00" , inc(byte_ptr(rax))); + TEST_INSTRUCTION("66FF00" , inc(word_ptr(rax))); + TEST_INSTRUCTION("FF00" , inc(dword_ptr(rax))); + TEST_INSTRUCTION("48FF00" , inc(qword_ptr(rax))); + TEST_INSTRUCTION("411351FD" , adc(edx, dword_ptr(r9, -3))); + TEST_INSTRUCTION("F6D8" , neg(al)); + TEST_INSTRUCTION("F6DC" , neg(ah)); + TEST_INSTRUCTION("40F6DE" , neg(sil)); + TEST_INSTRUCTION("F7D8" , neg(eax)); + TEST_INSTRUCTION("F7D0" , not_(eax)); + TEST_INSTRUCTION("0F95C3" , setnz(bl)); + TEST_INSTRUCTION("0F94C7" , setz(bh)); + TEST_INSTRUCTION("400F94C0" , rex().setz(al)); + TEST_INSTRUCTION("410F94C7" , setz(r15b)); + TEST_INSTRUCTION("F600FF" , test(byte_ptr(rax), 0xFF)); + TEST_INSTRUCTION("66F700FF00" , test(word_ptr(rax), 0xFF)); + TEST_INSTRUCTION("F700FF000000" , test(dword_ptr(rax), 0xFF)); + TEST_INSTRUCTION("48F700FF000000" , test(qword_ptr(rax), 0xFF)); + TEST_INSTRUCTION("A836" , test(al, 0x36)); + TEST_INSTRUCTION("F6C436" , test(ah, 0x36)); + TEST_INSTRUCTION("50" , push(rax)); + TEST_INSTRUCTION("51" , push(rcx)); + TEST_INSTRUCTION("52" , push(rdx)); + TEST_INSTRUCTION("53" , push(rbx)); + TEST_INSTRUCTION("54" , push(rsp)); + TEST_INSTRUCTION("55" , push(rbp)); + TEST_INSTRUCTION("56" , push(rsi)); + TEST_INSTRUCTION("57" , push(rdi)); + TEST_INSTRUCTION("4150" , push(r8)); + TEST_INSTRUCTION("4151" , push(r9)); + TEST_INSTRUCTION("4152" , push(r10)); + TEST_INSTRUCTION("4153" , push(r11)); + TEST_INSTRUCTION("4154" , push(r12)); + TEST_INSTRUCTION("4155" , push(r13)); + TEST_INSTRUCTION("4156" , push(r14)); + TEST_INSTRUCTION("4157" , push(r15)); + TEST_INSTRUCTION("0FA0" , push(fs)); + TEST_INSTRUCTION("0FA8" , push(gs)); + TEST_INSTRUCTION("400FA0" , rex().push(fs)); + TEST_INSTRUCTION("400FA8" , rex().push(gs)); + TEST_INSTRUCTION("C8010002" , enter(1, 2)); + TEST_INSTRUCTION("40C8010002" , rex().enter(1, 2)); + TEST_INSTRUCTION("C9" , leave()); + TEST_INSTRUCTION("FF10" , call(ptr(rax))); + TEST_INSTRUCTION("FF10" , call(qword_ptr(rax))); + TEST_INSTRUCTION("660FB401" , lfs(ax, ptr(rcx))); + TEST_INSTRUCTION("0FB401" , lfs(eax, ptr(rcx))); + TEST_INSTRUCTION("480FB401" , lfs(rax, ptr(rcx))); + TEST_INSTRUCTION("660FB501" , lgs(ax, ptr(rcx))); + TEST_INSTRUCTION("0FB501" , lgs(eax, ptr(rcx))); + TEST_INSTRUCTION("480FB501" , lgs(rax, ptr(rcx))); + TEST_INSTRUCTION("660FB201" , lss(ax, ptr(rcx))); + TEST_INSTRUCTION("0FB201" , lss(eax, ptr(rcx))); + TEST_INSTRUCTION("480FB201" , lss(rax, ptr(rcx))); + TEST_INSTRUCTION("40863424" , xchg(ptr(rsp), sil)); + TEST_INSTRUCTION("40863C24" , xchg(ptr(rsp), dil)); + + // NOP. + TEST_INSTRUCTION("90" , nop()); + TEST_INSTRUCTION("660F1F0400" , nop(word_ptr(rax, rax))); + TEST_INSTRUCTION("660F1F0400" , nop(word_ptr(rax, rax), ax)); + TEST_INSTRUCTION("660F1F1C00" , nop(word_ptr(rax, rax), bx)); + TEST_INSTRUCTION("0F1F0400" , nop(dword_ptr(rax, rax))); + TEST_INSTRUCTION("0F1F0400" , nop(dword_ptr(rax, rax), eax)); + TEST_INSTRUCTION("0F1F1C00" , nop(dword_ptr(rax, rax), ebx)); + TEST_INSTRUCTION("480F1F0400" , nop(qword_ptr(rax, rax))); + TEST_INSTRUCTION("480F1F0400" , nop(qword_ptr(rax, rax), rax)); + TEST_INSTRUCTION("480F1F1C00" , nop(qword_ptr(rax, rax), rbx)); + + // LEA. + TEST_INSTRUCTION("8D042500000000" , lea(eax, ptr(0))); + TEST_INSTRUCTION("488D042500000000" , lea(rax, ptr(0))); + TEST_INSTRUCTION("488D0433" , lea(rax, ptr(rbx, rsi))); + TEST_INSTRUCTION("488D043B" , lea(rax, ptr(rbx, rdi))); + TEST_INSTRUCTION("488D840000400000" , lea(rax, ptr(rax, rax, 0, 0x4000))); + + // CRC32. + TEST_INSTRUCTION("F20F38F0C7" , crc32(eax, bh)); + TEST_INSTRUCTION("66F20F38F1C3" , crc32(eax, bx)); + TEST_INSTRUCTION("F20F38F1C1" , crc32(eax, ecx)); + TEST_INSTRUCTION("F20F38F006" , crc32(eax, byte_ptr(rsi))); + TEST_INSTRUCTION("66F20F38F106" , crc32(eax, word_ptr(rsi))); + TEST_INSTRUCTION("F20F38F106" , crc32(eax, dword_ptr(rsi))); + TEST_INSTRUCTION("F2480F38F0C3" , crc32(rax, bl)); + TEST_INSTRUCTION("F2480F38F1C1" , crc32(rax, rcx)); + TEST_INSTRUCTION("F2480F38F006" , crc32(rax, byte_ptr(rsi))); + TEST_INSTRUCTION("F2480F38F106" , crc32(rax, qword_ptr(rsi))); + + // XACQUIRE|XRELEASE|RTM. + TEST_INSTRUCTION("C6F811" , xabort(0x11)); + TEST_INSTRUCTION("F2F0480108" , xacquire().lock().add(qword_ptr(rax), rcx)); + TEST_INSTRUCTION("F3F0480108" , xrelease().lock().add(qword_ptr(rax), rcx)); + + // BND. + TEST_INSTRUCTION("660F1ACA" , bndmov(bnd1, bnd2)); + TEST_INSTRUCTION("F20F1ACF" , bndcu(bnd1, rdi)); + TEST_INSTRUCTION("0F1A0408" , bndldx(bnd0, ptr(rax, rcx))); + TEST_INSTRUCTION("0F1B0C08" , bndstx(ptr(rax, rcx), bnd1)); + + // BMI+. + TEST_INSTRUCTION("66F30FB8C2" , popcnt(ax, dx)); + TEST_INSTRUCTION("66F3450FB8C1" , popcnt(r8w, r9w)); + TEST_INSTRUCTION("F30FB8C2" , popcnt(eax, edx)); + TEST_INSTRUCTION("F3480FB8C2" , popcnt(rax, rdx)); + TEST_INSTRUCTION("66F30FBDC2" , lzcnt(ax, dx)); + TEST_INSTRUCTION("66F3450FBDC7" , lzcnt(r8w, r15w)); + TEST_INSTRUCTION("F30FBDC2" , lzcnt(eax, edx)); + TEST_INSTRUCTION("F3490FBDC2" , lzcnt(rax, r10)); + TEST_INSTRUCTION("66F30FBCC2" , tzcnt(ax, dx)); + TEST_INSTRUCTION("66F3450FBCC7" , tzcnt(r8w, r15w)); + TEST_INSTRUCTION("F30FBCC2" , tzcnt(eax, edx)); + TEST_INSTRUCTION("F34D0FBCFA" , tzcnt(r15, r10)); + + // FPU. + TEST_INSTRUCTION("9B" , fwait()); + TEST_INSTRUCTION("D800" , fadd(dword_ptr(rax))); + TEST_INSTRUCTION("DC00" , fadd(qword_ptr(rax))); + + // MMX & SSE. + TEST_INSTRUCTION("0F6FC1" , movq(mm0, mm1)); + TEST_INSTRUCTION("0F6E00" , movd(mm0, ptr(rax))); + TEST_INSTRUCTION("0F6F0418" , movq(mm0, ptr(rax, rbx))); + TEST_INSTRUCTION("0F7E38" , movd(ptr(rax), mm7)); + TEST_INSTRUCTION("0F7F0418" , movq(ptr(rax, rbx), mm0)); + TEST_INSTRUCTION("F30F7EC1" , movq(xmm0, xmm1)); + TEST_INSTRUCTION("660F6E0418" , movd(xmm0, ptr(rax, rbx))); + TEST_INSTRUCTION("F30F7E0418" , movq(xmm0, ptr(rax, rbx))); + TEST_INSTRUCTION("660F7E0C18" , movd(ptr(rax, rbx), xmm1)); + TEST_INSTRUCTION("660FD60C18" , movq(ptr(rax, rbx), xmm1)); + TEST_INSTRUCTION("0F280498" , movaps(xmm0, ptr(rax, rbx, 2))); + TEST_INSTRUCTION("660F280498" , movapd(xmm0, ptr(rax, rbx, 2))); + TEST_INSTRUCTION("660F6F0498" , movdqa(xmm0, ptr(rax, rbx, 2))); + TEST_INSTRUCTION("0F290C98" , movaps(ptr(rax, rbx, 2), xmm1)); + TEST_INSTRUCTION("660F290C98" , movapd(ptr(rax, rbx, 2), xmm1)); + TEST_INSTRUCTION("660F7F0C98" , movdqa(ptr(rax, rbx, 2), xmm1)); + TEST_INSTRUCTION("F30F2DC1" , cvtss2si(eax, xmm1)); + TEST_INSTRUCTION("F3480F2DC1" , cvtss2si(rax, xmm1)); + TEST_INSTRUCTION("F20F2DC1" , cvtsd2si(eax, xmm1)); + TEST_INSTRUCTION("F2480F2DC1" , cvtsd2si(rax, xmm1)); + TEST_INSTRUCTION("F30F2AC2" , cvtsi2ss(xmm0, edx)); + TEST_INSTRUCTION("F3480F2AC2" , cvtsi2ss(xmm0, rdx)); + TEST_INSTRUCTION("F20F2AC2" , cvtsi2sd(xmm0, edx)); + TEST_INSTRUCTION("F2480F2AC2" , cvtsi2sd(xmm0, rdx)); + TEST_INSTRUCTION("66450F3A41D300" , dppd(xmm10, xmm11, 0)); + TEST_INSTRUCTION("0FDBC1" , pand(mm0, mm1)); + TEST_INSTRUCTION("660FDBC1" , pand(xmm0, xmm1)); + TEST_INSTRUCTION("660FFDC1" , paddw(xmm0, xmm1)); + + // AVX & AVX512. + TEST_INSTRUCTION("C5F96E5A10" , vmovd(xmm3, dword_ptr(rdx, 0x10))); + TEST_INSTRUCTION("C5FA7E5A10" , vmovq(xmm3, qword_ptr(rdx, 0x10))); + TEST_INSTRUCTION("C5F97E5A10" , vmovd(dword_ptr(rdx, 0x10), xmm3)); + TEST_INSTRUCTION("C5F9D65A10" , vmovq(qword_ptr(rdx, 0x10), xmm3)); + TEST_INSTRUCTION("C5F96EEB" , vmovd(xmm5, ebx)); + TEST_INSTRUCTION("C4E1F96EEB" , vmovq(xmm5, rbx)); + TEST_INSTRUCTION("62617D086EFB" , vmovd(xmm31, ebx)); + TEST_INSTRUCTION("6261FD086EFB" , vmovq(xmm31, rbx)); + TEST_INSTRUCTION("C5F97EEB" , vmovd(ebx, xmm5)); + TEST_INSTRUCTION("C4E1F97EEB" , vmovq(rbx, xmm5)); + TEST_INSTRUCTION("62617D087EFB" , vmovd(ebx, xmm31)); + TEST_INSTRUCTION("6261FD087EFB" , vmovq(rbx, xmm31)); + TEST_INSTRUCTION("C5FA7EC1" , vmovq(xmm0, xmm1)); + TEST_INSTRUCTION("62F17D086EC0" , evex().vmovd(xmm0, eax)); + TEST_INSTRUCTION("62F1FD086EC0" , evex().vmovq(xmm0, rax)); + TEST_INSTRUCTION("62F17D087EC0" , evex().vmovd(eax, xmm0)); + TEST_INSTRUCTION("62F1FD087EC0" , evex().vmovq(rax, xmm0)); + TEST_INSTRUCTION("C44135FDC7" , vpaddw(ymm8, ymm9, ymm15)); + TEST_INSTRUCTION("C4432141D400" , vdppd(xmm10, xmm11, xmm12, 0)); + TEST_INSTRUCTION("6271B5D95808" , k(k1).z().vaddpd(zmm9, zmm9, ptr(rax)._1to8())); + TEST_INSTRUCTION("C5F058C2" , vaddps(xmm0, xmm1, xmm2)); + TEST_INSTRUCTION("62F1748858C2" , z().vaddps(xmm0, xmm1, xmm2)); + TEST_INSTRUCTION("C5FA2DC1" , vcvtss2si(eax, xmm1)); + TEST_INSTRUCTION("C4E1FA2DC1" , vcvtss2si(rax, xmm1)); + TEST_INSTRUCTION("C5FB2DC1" , vcvtsd2si(eax, xmm1)); + TEST_INSTRUCTION("C4E1FB2DC1" , vcvtsd2si(rax, xmm1)); + TEST_INSTRUCTION("C5F22AC2" , vcvtsi2ss(xmm0, xmm1, edx)); + TEST_INSTRUCTION("C4E1F22AC2" , vcvtsi2ss(xmm0, xmm1, rdx)); + TEST_INSTRUCTION("C5F32AC2" , vcvtsi2sd(xmm0, xmm1, edx)); + TEST_INSTRUCTION("C4E1F32AC2" , vcvtsi2sd(xmm0, xmm1, rdx)); + TEST_INSTRUCTION("C57BE63B" , vcvtpd2dq(xmm15, xmmword_ptr(rbx))); + TEST_INSTRUCTION("C57FE63B" , vcvtpd2dq(xmm15, ymmword_ptr(rbx))); + TEST_INSTRUCTION("C5795A3B" , vcvtpd2ps(xmm15, xmmword_ptr(rbx))); + TEST_INSTRUCTION("C57D5A3B" , vcvtpd2ps(xmm15, ymmword_ptr(rbx))); + TEST_INSTRUCTION("6271FC08793B" , vcvtpd2udq(xmm15, xmmword_ptr(rbx))); + TEST_INSTRUCTION("6271FC28793B" , vcvtpd2udq(xmm15, ymmword_ptr(rbx))); + TEST_INSTRUCTION("6271FC085B3B" , vcvtqq2ps(xmm15, xmmword_ptr(rbx))); + TEST_INSTRUCTION("6271FC285B3B" , vcvtqq2ps(xmm15, ymmword_ptr(rbx))); + TEST_INSTRUCTION("C5F95AC1" , vcvtpd2ps(xmm0, xmm1)); + TEST_INSTRUCTION("C5F95A03" , vcvtpd2ps(xmm0, xmmword_ptr(rbx))); + TEST_INSTRUCTION("C5FD5AC1" , vcvtpd2ps(xmm0, ymm1)); + TEST_INSTRUCTION("C5FD5A03" , vcvtpd2ps(xmm0, ymmword_ptr(rbx))); + TEST_INSTRUCTION("62F1FD485AC1" , vcvtpd2ps(ymm0, zmm1)); + TEST_INSTRUCTION("62F1FD485A03" , vcvtpd2ps(ymm0, zmmword_ptr(rbx))); + TEST_INSTRUCTION("C579E63B" , vcvttpd2dq(xmm15, xmmword_ptr(rbx))); + TEST_INSTRUCTION("C57DE63B" , vcvttpd2dq(xmm15, ymmword_ptr(rbx))); + TEST_INSTRUCTION("6271FC08783B" , vcvttpd2udq(xmm15, xmmword_ptr(rbx))); + TEST_INSTRUCTION("6271FC28783B" , vcvttpd2udq(xmm15, ymmword_ptr(rbx))); + TEST_INSTRUCTION("6271FF087A3B" , vcvtuqq2ps(xmm15, xmmword_ptr(rbx))); + TEST_INSTRUCTION("6271FF287A3B" , vcvtuqq2ps(xmm15, ymmword_ptr(rbx))); + TEST_INSTRUCTION("62F3FD08663F01" , vfpclasspd(k7, xmmword_ptr(rdi), 0x01)); + TEST_INSTRUCTION("62F3FD28663701" , vfpclasspd(k6, ymmword_ptr(rdi), 0x01)); + TEST_INSTRUCTION("62F3FD48662F01" , vfpclasspd(k5, zmmword_ptr(rdi), 0x01)); + TEST_INSTRUCTION("62F37D08662701" , vfpclassps(k4, xmmword_ptr(rdi), 0x01)); + TEST_INSTRUCTION("62F37D28661F01" , vfpclassps(k3, ymmword_ptr(rdi), 0x01)); + TEST_INSTRUCTION("62F37D48661701" , vfpclassps(k2, zmmword_ptr(rdi), 0x01)); + TEST_INSTRUCTION("6201951058F4" , rn_sae().vaddpd(zmm30, zmm29, zmm28)); + TEST_INSTRUCTION("6201953058F4" , rd_sae().vaddpd(zmm30, zmm29, zmm28)); + TEST_INSTRUCTION("6201955058F4" , ru_sae().vaddpd(zmm30, zmm29, zmm28)); + TEST_INSTRUCTION("6201957058F4" , rz_sae().vaddpd(zmm30, zmm29, zmm28)); + TEST_INSTRUCTION("62F16C4FC25498040F" , k(k7).vcmpps(k2, zmm2, zmmword_ptr(rax, rbx, 2, 256), 15)); + TEST_INSTRUCTION("62F16C1FC25498400F" , k(k7).vcmpps(k2, xmm2, dword_ptr(rax, rbx, 2, 256)._1to4(), 15)); + TEST_INSTRUCTION("62F16C3FC25498400F" , k(k7).vcmpps(k2, ymm2, dword_ptr(rax, rbx, 2, 256)._1to8(), 15)); + TEST_INSTRUCTION("62F16C5FC25498400F" , k(k7).vcmpps(k2, zmm2, dword_ptr(rax, rbx, 2, 256)._1to16(), 15)); + TEST_INSTRUCTION("62F1FD58C2C100" , sae().vcmppd(k0, zmm0, zmm1, 0x00)); + TEST_INSTRUCTION("6201FD182EF5" , sae().vucomisd(xmm30, xmm29)); + TEST_INSTRUCTION("62017C182EF5" , sae().vucomiss(xmm30, xmm29)); + TEST_INSTRUCTION("C4E2FD91040500000000" , vpgatherqq(ymm0, ptr(0, ymm0), ymm0)); + TEST_INSTRUCTION("C4E2E9920C00" , vgatherdpd(xmm1, ptr(rax, xmm0), xmm2)); + TEST_INSTRUCTION("C4E26990440D00" , vpgatherdd(xmm0, ptr(rbp, xmm1), xmm2)); + TEST_INSTRUCTION("C4C26990040C" , vpgatherdd(xmm0, ptr(r12, xmm1), xmm2)); + TEST_INSTRUCTION("C4C26990440D00" , vpgatherdd(xmm0, ptr(r13, xmm1), xmm2)); + TEST_INSTRUCTION("62F36D083ECB00" , vpcmpub(k1, xmm2, xmm3, 0x0)); + TEST_INSTRUCTION("C5E9FE4C1140" , vpaddd(xmm1, xmm2, ptr(rcx, rdx, 0, 64))); + TEST_INSTRUCTION("C5EDFE4C1140" , vpaddd(ymm1, ymm2, ptr(rcx, rdx, 0, 64))); + TEST_INSTRUCTION("62F16D48FE4C1101" , vpaddd(zmm1, zmm2, ptr(rcx, rdx, 0, 64))); + TEST_INSTRUCTION("62E23D0850441104" , vpdpbusd(xmm16, xmm8, ptr(rcx, rdx, 0, 64))); + TEST_INSTRUCTION("62E23D2850441102" , vpdpbusd(ymm16, ymm8, ptr(rcx, rdx, 0, 64))); + TEST_INSTRUCTION("62E23D4850441101" , vpdpbusd(zmm16, zmm8, ptr(rcx, rdx, 0, 64))); + TEST_INSTRUCTION("62F26D48CF4C1101" , vgf2p8mulb(zmm1, zmm2, zmmword_ptr(rcx, rdx, 0, 64))); + TEST_INSTRUCTION("62F3ED48CE4C11010F" , vgf2p8affineqb(zmm1, zmm2, zmmword_ptr(rcx, rdx, 0, 64), 15)); + TEST_INSTRUCTION("62F3ED48CF4C11010F" , vgf2p8affineinvqb(zmm1, zmm2, zmmword_ptr(rcx, rdx, 0, 64), 15)); + TEST_INSTRUCTION("62F27D087AC6" , vpbroadcastb(xmm0, esi)); + TEST_INSTRUCTION("62F27D287AC6" , vpbroadcastb(ymm0, esi)); + TEST_INSTRUCTION("62F27D487AC6" , vpbroadcastb(zmm0, esi)); + TEST_INSTRUCTION("62F2CD088DF8" , vpermw(xmm7, xmm6, xmm0)); + TEST_INSTRUCTION("C4E3FD01FE01" , vpermpd(ymm7, ymm6, 1)); + TEST_INSTRUCTION("62F3FD4801FE01" , vpermpd(zmm7, zmm6, 1)); + TEST_INSTRUCTION("62F2CD2816F8" , vpermpd(ymm7, ymm6, ymm0)); + TEST_INSTRUCTION("62F2CD4816F8" , vpermpd(zmm7, zmm6, zmm0)); + TEST_INSTRUCTION("C4E24D16F9" , vpermps(ymm7, ymm6, ymm1)); + TEST_INSTRUCTION("62F24D4816F9" , vpermps(zmm7, zmm6, zmm1)); + TEST_INSTRUCTION("6292472068F0" , vp2intersectd(k6, k7, ymm23, ymm24)); + TEST_INSTRUCTION("62B2472068B4F500000010" , vp2intersectd(k6, k7, ymm23, ptr(rbp, r14, 3, 268435456))); + TEST_INSTRUCTION("62F24730683500000000" , vp2intersectd(k6, k7, ymm23, dword_ptr(rip)._1to8())); + TEST_INSTRUCTION("62F2472068742DE0" , vp2intersectd(k6, k7, ymm23, ymmword_ptr(rbp, rbp, 0, -1024))); + TEST_INSTRUCTION("62F2472068717F" , vp2intersectd(k6, k7, ymm23, ymmword_ptr(rcx, 4064))); + + // AVX512_VNNI vs AVX_VNNI. + TEST_INSTRUCTION("62F2552850F4" , vpdpbusd(ymm6, ymm5, ymm4)); + TEST_INSTRUCTION("C4E25550F4" , vex().vpdpbusd(ymm6, ymm5, ymm4)); + + tester.printSummary(); + return tester.didPass(); +} + +#undef TEST_INSTRUCTION + +#endif diff --git a/test/asmjit_test_compiler.cpp b/test/asmjit_test_compiler.cpp index 45adb70..c13ba18 100644 --- a/test/asmjit_test_compiler.cpp +++ b/test/asmjit_test_compiler.cpp @@ -29,6 +29,7 @@ #include #include +#include #include "cmdline.h" #include "asmjit_test_compiler.h" @@ -53,6 +54,27 @@ void compiler_add_a64_tests(TestApp& app); using namespace asmjit; +class PerformanceTimer { +public: + typedef std::chrono::high_resolution_clock::time_point TimePoint; + + TimePoint _startTime {}; + TimePoint _endTime {}; + + inline void start() { + _startTime = std::chrono::high_resolution_clock::now(); + } + + inline void stop() { + _endTime = std::chrono::high_resolution_clock::now(); + } + + inline double duration() const { + std::chrono::duration elapsed = _endTime - _startTime; + return elapsed.count() * 1000; + } +}; + // ============================================================================ // [TestApp] // ============================================================================ @@ -79,7 +101,7 @@ int TestApp::handleArgs(int argc, const char* const* argv) { } void TestApp::showInfo() { - printf("AsmJit Compiler Test-Suite v%u.%u.%u [Arch=%s]:\n", + printf("AsmJit Compiler Test-Suite v%u.%u.%u (Arch=%s):\n", unsigned((ASMJIT_LIBRARY_VERSION >> 16) ), unsigned((ASMJIT_LIBRARY_VERSION >> 8) & 0xFF), unsigned((ASMJIT_LIBRARY_VERSION ) & 0xFF), @@ -109,11 +131,16 @@ int TestApp::run() { stringLogger.addFlags(kFormatFlags); #endif + double compileTime = 0; + double finalizeTime = 0; + for (std::unique_ptr& test : _tests) { JitRuntime runtime; CodeHolder code; SimpleErrorHandler errorHandler; + PerformanceTimer perfTimer; + code.init(runtime.environment()); code.setErrorHandler(&errorHandler); @@ -141,13 +168,20 @@ int TestApp::run() { arm::Compiler cc(&code); #endif + perfTimer.start(); test->compile(cc); + perfTimer.stop(); + compileTime += perfTimer.duration(); void* func = nullptr; Error err = errorHandler._err; - if (!err) + if (!err) { + perfTimer.start(); err = cc.finalize(); + perfTimer.stop(); + finalizeTime += perfTimer.duration(); + } #ifndef ASMJIT_NO_LOGGING if (_dumpAsm) { @@ -213,13 +247,17 @@ int TestApp::run() { } } - if (_nFailed == 0) - printf("\nSuccess:\n All %u tests passed\n", unsigned(_tests.size())); - else - printf("\nFailure:\n %u %s of %u failed\n", _nFailed, _nFailed == 1 ? "test" : "tests", unsigned(_tests.size())); - - printf(" OutputSize=%zu\n", _outputSize); printf("\n"); + printf("Summary:\n"); + printf(" OutputSize: %zu bytes\n", _outputSize); + printf(" CompileTime: %.2f ms\n", compileTime); + printf(" FinalizeTime: %.2f ms\n", finalizeTime); + printf("\n"); + + if (_nFailed == 0) + printf("** SUCCESS: All %u tests passed **\n", unsigned(_tests.size())); + else + printf("** FAILURE: %u of %u tests failed **\n", _nFailed, unsigned(_tests.size())); return _nFailed == 0 ? 0 : 1; #endif diff --git a/test/asmjit_test_x86_asm.cpp b/test/asmjit_test_emitters.cpp similarity index 89% rename from test/asmjit_test_x86_asm.cpp rename to test/asmjit_test_emitters.cpp index 5000c1e..6f94851 100644 --- a/test/asmjit_test_x86_asm.cpp +++ b/test/asmjit_test_emitters.cpp @@ -132,7 +132,7 @@ static uint32_t testFunc(JitRuntime& rt, uint32_t emitterType) noexcept { err = cb.finalize(); if (err) { - printf("x86::Builder::finalize() failed: %s\n", DebugUtils::errorAsString(err)); + printf("** FAILURE: x86::Builder::finalize() failed (%s) **\n", DebugUtils::errorAsString(err)); return 1; } break; @@ -147,7 +147,7 @@ static uint32_t testFunc(JitRuntime& rt, uint32_t emitterType) noexcept { err = cc.finalize(); if (err) { - printf("x86::Compiler::finalize() failed: %s\n", DebugUtils::errorAsString(err)); + printf("** FAILURE: x86::Compiler::finalize() failed (%s) **\n", DebugUtils::errorAsString(err)); return 1; } break; @@ -160,7 +160,7 @@ static uint32_t testFunc(JitRuntime& rt, uint32_t emitterType) noexcept { err = rt.add(&fn, &code); if (err) { - printf("JitRuntime::add() failed: %s\n", DebugUtils::errorAsString(err)); + printf("** FAILURE: JitRuntime::add() failed (%s) **\n", DebugUtils::errorAsString(err)); return 1; } @@ -178,7 +178,11 @@ static uint32_t testFunc(JitRuntime& rt, uint32_t emitterType) noexcept { } int main() { - printf("AsmJit X86 Emitter Test\n\n"); + printf("AsmJit Emitters Test-Suite v%u.%u.%u\n", + unsigned((ASMJIT_LIBRARY_VERSION >> 16) ), + unsigned((ASMJIT_LIBRARY_VERSION >> 8) & 0xFF), + unsigned((ASMJIT_LIBRARY_VERSION ) & 0xFF)); + printf("\n"); JitRuntime rt; unsigned nFailed = 0; @@ -194,9 +198,9 @@ int main() { #endif if (!nFailed) - printf("Success:\n All tests passed\n"); + printf("** SUCCESS **\n"); else - printf("Failure:\n %u %s failed\n", nFailed, nFailed == 1 ? "test" : "tests"); + printf("** FAILURE - %u %s failed ** \n", nFailed, nFailed == 1 ? "test" : "tests"); return nFailed ? 1 : 0; } diff --git a/test/asmjit_test_x86_instinfo.cpp b/test/asmjit_test_instinfo.cpp similarity index 82% rename from test/asmjit_test_x86_instinfo.cpp rename to test/asmjit_test_instinfo.cpp index 68d870d..dc53fd7 100644 --- a/test/asmjit_test_x86_instinfo.cpp +++ b/test/asmjit_test_instinfo.cpp @@ -44,8 +44,6 @@ static void printInfo(uint32_t arch, const BaseInst& inst, const Operand_* opera InstRWInfo rw; InstAPI::queryRWInfo(arch, inst, operands, opCount, &rw); - sb.append("Instruction:\n"); - sb.append(" "); #ifndef ASMJIT_NO_LOGGING Formatter::formatInstruction(sb, 0, nullptr, arch, inst, operands, opCount); #else @@ -53,11 +51,11 @@ static void printInfo(uint32_t arch, const BaseInst& inst, const Operand_* opera #endif sb.append("\n"); - sb.append("Operands:\n"); + sb.append(" Operands:\n"); for (uint32_t i = 0; i < rw.opCount(); i++) { const OpRWInfo& op = rw.operand(i); - sb.appendFormat(" [%u] Op=%c Read=%016llX Write=%016llX Extend=%016llX", + sb.appendFormat(" [%u] Op=%c Read=%016llX Write=%016llX Extend=%016llX", i, accessLetter(op.isRead(), op.isWrite()), op.readByteMask(), @@ -80,7 +78,7 @@ static void printInfo(uint32_t arch, const BaseInst& inst, const Operand_* opera } if (rw.readFlags() | rw.writeFlags()) { - sb.append("Flags: \n"); + sb.append(" Flags: \n"); struct FlagMap { uint32_t flag; @@ -103,7 +101,7 @@ static void printInfo(uint32_t arch, const BaseInst& inst, const Operand_* opera { x86::Status::kC3, "C3" } }; - sb.append(" "); + sb.append(" "); for (uint32_t f = 0; f < 13; f++) { char c = accessLetter((rw.readFlags() & flagMap[f].flag) != 0, (rw.writeFlags() & flagMap[f].flag) != 0); @@ -122,8 +120,8 @@ static void printInfo(uint32_t arch, const BaseInst& inst, const Operand_* opera #ifndef ASMJIT_NO_LOGGING if (!features.empty()) { - sb.append("Features:\n"); - sb.append(" "); + sb.append(" Features:\n"); + sb.append(" "); bool first = true; BaseFeatures::Iterator it(features.iterator()); @@ -142,8 +140,9 @@ static void printInfo(uint32_t arch, const BaseInst& inst, const Operand_* opera } template -static void printInfoSimple(uint32_t arch, uint32_t instId, Args&&... args) { +static void printInfoSimple(uint32_t arch, uint32_t instId, uint32_t options, Args&&... args) { BaseInst inst(instId); + inst.addOptions(options); Operand_ opArray[] = { std::forward(args)... }; printInfo(arch, inst, opArray, sizeof...(args)); } @@ -162,35 +161,43 @@ static void testX86Arch() { uint32_t arch = Environment::kArchX64; printInfoSimple(arch, - x86::Inst::kIdAdd, + x86::Inst::kIdAdd, 0, x86::eax, x86::ebx); printInfoSimple(arch, - x86::Inst::kIdLods, + x86::Inst::kIdLods, 0, x86::eax , dword_ptr(x86::rsi)); printInfoSimple(arch, - x86::Inst::kIdPshufd, + x86::Inst::kIdPshufd, 0, x86::xmm0, x86::xmm1, imm(0)); printInfoSimple(arch, - x86::Inst::kIdPextrw, + x86::Inst::kIdPextrw, 0, x86::eax, x86::xmm1, imm(0)); printInfoSimple(arch, - x86::Inst::kIdPextrw, + x86::Inst::kIdPextrw, 0, x86::ptr(x86::rax), x86::xmm1, imm(0)); printInfoSimple(arch, - x86::Inst::kIdVaddpd, + x86::Inst::kIdVpdpbusd, 0, + x86::xmm0, x86::xmm1, x86::xmm2); + + printInfoSimple(arch, + x86::Inst::kIdVpdpbusd, x86::Inst::kOptionVex, + x86::xmm0, x86::xmm1, x86::xmm2); + + printInfoSimple(arch, + x86::Inst::kIdVaddpd, 0, x86::ymm0, x86::ymm1, x86::ymm2); printInfoSimple(arch, - x86::Inst::kIdVaddpd, + x86::Inst::kIdVaddpd, 0, x86::ymm0, x86::ymm30, x86::ymm31); printInfoSimple(arch, - x86::Inst::kIdVaddpd, + x86::Inst::kIdVaddpd, 0, x86::zmm0, x86::zmm1, x86::zmm2); printInfoExtra(arch, @@ -206,7 +213,11 @@ static void testX86Arch() { } int main() { - printf("AsmJit Instruction Information Test\n\n"); + printf("AsmJit Instruction Info Test-Suite v%u.%u.%u\n", + unsigned((ASMJIT_LIBRARY_VERSION >> 16) ), + unsigned((ASMJIT_LIBRARY_VERSION >> 8) & 0xFF), + unsigned((ASMJIT_LIBRARY_VERSION ) & 0xFF)); + printf("\n"); testX86Arch(); diff --git a/test/asmjit_test_x86_sections.cpp b/test/asmjit_test_x86_sections.cpp index 599fa57..85d2dda 100644 --- a/test/asmjit_test_x86_sections.cpp +++ b/test/asmjit_test_x86_sections.cpp @@ -51,7 +51,7 @@ using namespace asmjit; static const uint8_t dataArray[] = { 2, 9, 4, 7, 1, 3, 8, 5, 6, 0 }; static void fail(const char* message, Error err) { - printf("%s: %s\n", message, DebugUtils::errorAsString(err)); + printf("** FAILURE: %s (%s) **\n", message, DebugUtils::errorAsString(err)); exit(1); } @@ -169,11 +169,11 @@ int main() { fn(3) != dataArray[3] || fn(6) != dataArray[6] || fn(9) != dataArray[9] ) { - printf("Failure:\n The generated function returned incorrect result(s)\n"); + printf("** FAILURE: The generated function returned incorrect result(s) **\n"); return 1; } - printf("Success:\n The generated function returned expected results\n"); + printf("** SUCCESS **\n"); return 0; } diff --git a/tools/tablegen-x86.js b/tools/tablegen-x86.js index 35d8b24..33bf7d5 100644 --- a/tools/tablegen-x86.js +++ b/tools/tablegen-x86.js @@ -69,7 +69,18 @@ const x86isa = new asmdb.x86.ISA({ ["imul", "r64, ib" , "RMI" , "REX.W 6B /r ib", "X64 OF=W SF=W ZF=U AF=U PF=U CF=W"], ["imul", "r16, iw" , "RMI" , "66 69 /r iw" , "ANY OF=W SF=W ZF=U AF=U PF=U CF=W"], ["imul", "r32, id" , "RMI" , "69 /r id" , "ANY OF=W SF=W ZF=U AF=U PF=U CF=W"], - ["imul", "r64, id" , "RMI" , "REX.W 69 /r id", "X64 OF=W SF=W ZF=U AF=U PF=U CF=W"] + ["imul", "r64, id" , "RMI" , "REX.W 69 /r id", "X64 OF=W SF=W ZF=U AF=U PF=U CF=W"], + + // Movabs (X64 only). + ["movabs", "W:r64, iq/uq" , "I" , "REX.W B8+r iq", "X64"], + ["movabs", "w:al, moff8" , "NONE", "A0" , "X64"], + ["movabs", "w:ax, moff16" , "NONE", "66 A1" , "X64"], + ["movabs", "W:eax, moff32", "NONE", "A1" , "X64"], + ["movabs", "W:rax, moff64", "NONE", "REX.W A1" , "X64"], + ["movabs", "W:moff8, al" , "NONE", "A2" , "X64"], + ["movabs", "W:moff16, ax" , "NONE", "66 A3" , "X64"], + ["movabs", "W:moff32, eax", "NONE", "A3" , "X64"], + ["movabs", "W:moff64, rax", "NONE", "REX.W A3" , "X64"] ] }); @@ -233,6 +244,9 @@ class GenUtils { if (dbInst.prefix === "EVEX") { f.Evex = true; + if (dbInst.extensions["AVX512_VNNI"]) + f.PreferEvex = true; + if (dbInst.kmask) f.Avx512K = true; if (dbInst.zmask) f.Avx512Z = true; @@ -682,11 +696,21 @@ class IdEnum extends core.IdEnum { var text = ""; var features = GenUtils.cpuFeaturesOf(dbInsts); + const priorityFeatures = ["AVX_VNNI"]; + if (features.length) { text += "{"; const avxFeatures = filterAVX(features, true); const otherFeatures = filterAVX(features, false); + for (const pf of priorityFeatures) { + const index = avxFeatures.indexOf(pf); + if (index != -1) { + avxFeatures.splice(index, 1); + avxFeatures.unshift(pf); + } + } + const vl = avxFeatures.indexOf("AVX512_VL"); if (vl !== -1) avxFeatures.splice(vl, 1); @@ -781,138 +805,6 @@ class AltOpcodeTable extends core.Task { } } -// ============================================================================ -// [tablegen.x86.SseToAvxTable] -// ============================================================================ -/* -// Removed from asmjit. -class InstSseToAvxTable extends core.Task { - constructor() { - super("InstSseToAvxTable", ["IdEnum"]); - } - - run() { - const insts = this.ctx.insts; - - const dataTable = new IndexedArray(); - const indexTable = []; - - function add(data) { - return dataTable.addIndexed("{ " + `SseToAvxData::kMode${data.mode}`.padEnd(28) + ", " + String(data.delta).padEnd(4) + " }"); - } - - // This will receive a zero index, which means that no SseToAvx or AvxToSSe translation is possible. - const kInvalidIndex = add({ mode: "None", delta: 0 }); - insts.forEach((inst) => { indexTable.push(kInvalidIndex); }); - - insts.forEach((inst) => { - // If it's not `kInvalidIndex` it's an AVX instruction that shares the - // SseToAvx data. We won't touch it as it already has the index assigned. - if (indexTable[inst.id] === kInvalidIndex) { - const data = this.calcSseToAvxData(inst.dbInsts); - const index = add(data); - - indexTable[inst.id] = index; - if (data.delta !== 0) - indexTable[this.ctx.instMap["v" + inst.name].id] = index; - } - }); - - this.inject("SseToAvxIndex", - disclaimer(`static const uint8_t sseToAvxIndex[] = {\n${StringUtils.format(indexTable, kIndent, -1)}\n};\n`), - indexTable.length * 1); - - this.inject("SseToAvxTable", - disclaimer(`static const SseToAvxData sseToAvxData[] = {\n${StringUtils.format(dataTable, kIndent, true)}\n};\n`), - dataTable.length * 2); - } - - filterSseToAvx(dbInsts) { - const filtered = []; - for (var x = 0; x < dbInsts.length; x++) { - const dbInst = dbInsts[x]; - const ops = dbInst.operands; - - // SSE instruction does never share its name with AVX one. - if (/^(VEX|XOP|EVEX)$/.test(dbInst.prefix)) - return []; - - var ok = false; - for (var y = 0; y < ops.length; y++) { - // There is no AVX instruction that works with MMX regs. - if (ops[y].reg === "mm") { ok = false; break; } - if (ops[y].reg === "xmm") { ok = true; } - } - - if (ok) - filtered.push(dbInst); - } - - return filtered; - } - - calcSseToAvxData(dbInsts) { - const data = { - mode : "None", // No conversion by default. - delta: 0 // 0 if no conversion is possible. - }; - - const dbSseInsts = this.filterSseToAvx(dbInsts); - if (!dbSseInsts.length) - return data; - - const sseName = dbSseInsts[0].name; - const avxName = "v" + sseName; - - const dbAvxInsts = this.ctx.query(avxName); - if (!dbAvxInsts.length) { - DEBUG(`SseToAvx: Instruction '${sseName}' has no AVX counterpart`); - return data; - } - - if (avxName === "vblendvpd" || avxName === "vblendvps" || avxName === "vpblendvb") { - // Special cases first. - data.mode = "Blend"; - } - else { - // Common case, deduce conversion mode by checking both SSE and AVX instructions. - const map = Object.create(null); - for (var sseIndex = 0; sseIndex < dbSseInsts.length; sseIndex++) { - const sseInst = dbSseInsts[sseIndex]; - var match = false; - - for (var avxIndex = 0; avxIndex < dbAvxInsts.length; avxIndex++) { - const avxInst = dbAvxInsts[avxIndex]; - - // Select only VEX instructions. - if (avxInst.prefix !== "VEX") continue; - - // Check if the AVX version is the same. - if (GenUtils.eqOps(avxInst.operands, 0, sseInst.operands, 0)) { - map.raw = true; - match = true; - } - else if (avxInst.operands[0].data === "xmm" && GenUtils.eqOps(avxInst.operands, 1, sseInst.operands, 0)) { - map.nds = true; - match = true; - } - } - - if (!match) { - const signature = sseInst.operands.map(function(op) { return op.data; }).join(", "); - console.log(`SseToAvx: Instruction '${sseName}(${signature})' has no AVX counterpart`); - return data; - } - } - - data.mode = (map.raw && !map.nds) ? "Move" : (map.raw && map.nds) ? "MoveIfMem" : "Extend"; - } - data.delta = this.ctx.instMap[avxName].id - this.ctx.instMap[sseName].id; - return data; - } -} -*/ - // ============================================================================ // [tablegen.x86.InstSignatureTable] // ============================================================================ @@ -1456,14 +1348,7 @@ class SignatureArray extends Array { class InstSignatureTable extends core.Task { constructor() { super("InstSignatureTable"); - this.maxOpRows = 0; - this.opBlackList = { - "moff8" : true, - "moff16": true, - "moff32": true, - "moff64": true - }; } run() { @@ -1637,10 +1522,8 @@ class InstSignatureTable extends core.Task { var imm = iop.imm; var rel = iop.rel; - // Terminate if this operand is something asmjit doesn't support - // and skip all instructions having implicit `imm` operand of `1`, - // which are handled fine by asmjit. - if (this.opBlackList[mem] === true || iop.immValue !== null) + // Skip all instructions having implicit `imm` operand of `1`. + if (iop.immValue !== null) break; if (reg === "r8") reg = "r8lo"; @@ -1648,6 +1531,11 @@ class InstSignatureTable extends core.Task { if (reg === "st(i)") reg = "st"; if (reg === "st(0)") reg = "st0"; + if (mem === "moff8") mem = "m8"; + if (mem === "moff16") mem = "m16"; + if (mem === "moff32") mem = "m32"; + if (mem === "moff64") mem = "m64"; + if (mem === "m32fp") mem = "m32"; if (mem === "m64fp") mem = "m64"; if (mem === "m80fp") mem = "m80"; @@ -1850,6 +1738,7 @@ class InstRWInfoTable extends core.Task { this.rwCategoryByName = { "imul" : "Imul", "mov" : "Mov", + "movabs" : "Movabs", "movhpd" : "Movh64", "movhps" : "Movh64", "vmaskmovpd": "Vmaskmov",