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https://github.com/asmjit/asmjit.git
synced 2025-12-17 04:24:37 +03:00
Added new instructions + xacquire|xrelease prefixes, reorganized instruction options
This commit is contained in:
@@ -272,12 +272,13 @@ class GenUtils {
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for (i = 0; i < group.length; i++) {
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const inst = group[i];
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const name = inst.name;
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const operands = inst.operands;
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if (inst.attributes.LOCK ) f.Lock = true;
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if (inst.attributes.REP ) f.Rep = true;
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if (inst.attributes.REPNZ) f.Repnz = true;
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if (inst.attributes.LOCK ) f.Lock = true;
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if (inst.attributes.REP ) f.Rep = true;
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if (inst.attributes.REPNZ ) f.Repnz = true;
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if (inst.attributes.XACQUIRE) f.XAcquire = true;
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if (inst.attributes.XRELEASE) f.XRelease = true;
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if (inst.fpu) {
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for (var j = 0; j < operands.length; j++) {
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@@ -458,6 +459,7 @@ class GenUtils {
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case "loop":
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case "loope":
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case "loopne":
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case "xbegin":
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return "Conditional";
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case "jmp" : return "Direct";
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@@ -480,7 +482,7 @@ const RegOp = MapUtils.arrayToMap([
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]);
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const MemOp = MapUtils.arrayToMap([
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"m8", "m16", "m32", "m64", "m80", "m128", "m256", "m512", "m1024"
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"m8", "m16", "m32", "m48", "m64", "m80", "m128", "m256", "m512", "m1024"
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]);
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const OpSortPriority = {
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@@ -510,22 +512,23 @@ const OpSortPriority = {
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"m8" : 32,
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"m16" : 33,
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"m32" : 34,
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"m64" : 35,
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"m80" : 36,
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"m128" : 37,
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"m256" : 38,
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"m512" : 39,
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"m1024" : 40,
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"mib" : 41,
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"vm32x" : 42,
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"vm32y" : 43,
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"vm32z" : 44,
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"vm64x" : 45,
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"vm64y" : 46,
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"vm64z" : 47,
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"memBase" : 48,
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"memES" : 49,
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"memDS" : 50,
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"m48" : 35,
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"m64" : 36,
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"m80" : 37,
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"m128" : 38,
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"m256" : 39,
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"m512" : 40,
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"m1024" : 41,
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"mib" : 42,
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"vm32x" : 43,
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"vm32y" : 44,
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"vm32z" : 45,
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"vm64x" : 46,
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"vm64y" : 47,
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"vm64z" : 48,
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"memBase" : 49,
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"memES" : 50,
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"memDS" : 51,
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"i4" : 60,
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"u4" : 61,
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@@ -570,6 +573,7 @@ const OpToAsmJitOp = {
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"m8" : "MEM(M8)",
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"m16" : "MEM(M16)",
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"m32" : "MEM(M32)",
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"m48" : "MEM(M48)",
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"m64" : "MEM(M64)",
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"m80" : "MEM(M80)",
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"m128" : "MEM(M128)",
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@@ -757,15 +761,16 @@ class OSignature {
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case "ymm" :
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case "zmm" : mFlags[k] = true; break;
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case "m8" : mFlags.mem = true; mMemFlags.m8 = true; break;
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case "m16" : mFlags.mem = true; mMemFlags.m16 = true; break;
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case "m32" : mFlags.mem = true; mMemFlags.m32 = true; break;
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case "m64" : mFlags.mem = true; mMemFlags.m64 = true; break;
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case "m80" : mFlags.mem = true; mMemFlags.m80 = true; break;
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case "m128" : mFlags.mem = true; mMemFlags.m128 = true; break;
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case "m256" : mFlags.mem = true; mMemFlags.m256 = true; break;
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case "m512" : mFlags.mem = true; mMemFlags.m512 = true; break;
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case "m1024" : mFlags.mem = true; mMemFlags.m1024 = true; break;
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case "m8" :
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case "m16" :
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case "m32" :
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case "m48" :
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case "m64" :
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case "m80" :
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case "m128" :
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case "m256" :
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case "m512" :
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case "m1024" : mFlags.mem = true; mMemFlags[k] = true; break;
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case "mib" : mFlags.mem = true; mMemFlags.mib = true; break;
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case "mem" : mFlags.mem = true; mMemFlags.mAny = true; break;
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@@ -800,6 +805,12 @@ class OSignature {
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mFlags[k] = true;
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break;
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case "rel16" :
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mFlags.i32 = true;
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mFlags.i64 = true;
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mFlags.rel32 = true;
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break;
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default: {
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switch (k) {
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case "es" : mFlags.sreg = true; sRegMask |= 1 << 1; break;
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@@ -1150,6 +1161,10 @@ class X86Generator extends base.BaseGenerator {
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if (mem === "m32int") mem = "m32";
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if (mem === "m64int") mem = "m64";
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if (mem === "m16_16") mem = "m32";
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if (mem === "m16_32") mem = "m48";
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if (mem === "m16_64") mem = "m80";
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const op = new OSignature();
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if (iop.read) op.flags.read = true;
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@@ -1709,6 +1724,7 @@ class X86Generator extends base.BaseGenerator {
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StringUtils.padLeft(inst.opcode1 , 26) + ", " +
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StringUtils.padLeft(inst.writeIndex , 2) + ", " +
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StringUtils.padLeft(inst.writeSize , 2) + ", " +
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StringUtils.padLeft("0", 4) + ", " +
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StringUtils.padLeft("0", 3) + ", " +
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StringUtils.padLeft("0", 3) + ", " +
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StringUtils.padLeft("0", 3) + "),\n";
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@@ -1720,7 +1736,7 @@ class X86Generator extends base.BaseGenerator {
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newInstFromInsts(insts) {
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function composeOpCode(obj) {
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return `${obj.type}(${obj.prefix},${obj.opcode},${obj.o},${obj.l},${obj.w},${obj.ew},${obj.en})`;
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return `${obj.type}(${obj.prefix},${obj.opcode},${obj.o},${obj.l},${obj.w},${obj.ew},${obj.en},${obj.tt})`;
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}
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function GetAccess(inst) {
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@@ -1778,7 +1794,8 @@ class X86Generator extends base.BaseGenerator {
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l : vexL !== undefined ? vexL : "_",
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w : vexW !== undefined ? vexW : "_",
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ew : evexW !== undefined ? vexEW : "_",
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en : "_"
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en : "_",
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tt : "_ "
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});
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return {
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