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Added possibility to use certain FPU instruction without operand by implicitly using fp1 (st1).

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This commit is contained in:
kobalicekp
2014-02-02 20:44:24 +01:00
parent 5c7123fbb3
commit 483c21db2d
5 changed files with 59 additions and 13 deletions
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14
src/app/test/genopcode.h
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@@ -228,14 +228,17 @@ static void opcode(asmjit::host::Assembler& a) {
a.fadd(dword_ptr(gp0));
a.fadd(qword_ptr(gp0));
a.faddp(fpx);
a.faddp();
a.fbld(dword_ptr(gp0));
a.fbstp(dword_ptr(gp0));
a.fchs();
a.fclex();
a.fcom(fpx);
a.fcom();
a.fcom(dword_ptr(gp0));
a.fcom(qword_ptr(gp0));
a.fcomp(fpx);
a.fcomp();
a.fcomp(dword_ptr(gp0));
a.fcomp(qword_ptr(gp0));
a.fcompp();
@@ -246,11 +249,13 @@ static void opcode(asmjit::host::Assembler& a) {
a.fdiv(dword_ptr(gp0));
a.fdiv(qword_ptr(gp0));
a.fdivp(fpx);
a.fdivp();
a.fdivr(fp0, fpx);
a.fdivr(fpx, fp0);
a.fdivr(dword_ptr(gp0));
a.fdivr(qword_ptr(gp0));
a.fdivrp(fpx);
a.fdivrp();
a.fiadd(dword_ptr(gp0));
a.ficom(word_ptr(gp0));
a.ficom(dword_ptr(gp0));
@@ -294,6 +299,7 @@ static void opcode(asmjit::host::Assembler& a) {
a.fmul(dword_ptr(gp0));
a.fmul(qword_ptr(gp0));
a.fmulp(fpx);
a.fmulp();
a.fnclex();
a.fnop();
a.fnsave(ptr_gp0);
@@ -322,12 +328,20 @@ static void opcode(asmjit::host::Assembler& a) {
a.fsub(dword_ptr(gp0));
a.fsub(qword_ptr(gp0));
a.fsubp(fpx);
a.fsubp();
a.fsubr(fp0, fpx);
a.fsubr(fpx, fp0);
a.fsubr(dword_ptr(gp0));
a.fsubr(qword_ptr(gp0));
a.fsubrp(fpx);
a.fsubrp();
a.ftst();
a.fucom(fpx);
a.fucom();
a.fucom(fpx);
a.fucomi(fpx);
a.fucomip(fpx);
a.fucomp(fpx);
a.fucompp();
a.fxam();
a.fxrstor(ptr_gp0);

12
src/asmjit/x86/x86assembler.cpp
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@@ -2076,6 +2076,11 @@ _EmitFpArith_Mem:
break;
case kInstGroupFpuCom:
if (encoded == ENC_OPS(None, None, None)) {
rmReg = 1;
goto _EmitFpArith_Reg;
}
if (encoded == ENC_OPS(Reg, None, None)) {
rmReg = static_cast<const FpReg*>(o0)->getRegIndex();
goto _EmitFpArith_Reg;
@@ -2146,6 +2151,13 @@ _EmitFpArith_Mem:
}
break;
case kInstGroupFpuRDef:
if (encoded == ENC_OPS(None, None, None)) {
opCode += 1;
goto _EmitFpuOp;
}
// ... Fall through ...
case kInstGroupFpuR:
if (encoded == ENC_OPS(Reg, None, None)) {
opCode += static_cast<const FpReg*>(o0)->getRegIndex();

26
src/asmjit/x86/x86assembler.h
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@@ -1186,6 +1186,8 @@ struct X86X64Assembler : public BaseAssembler {
INST_1x(fadd, kInstFadd, Mem)
//! @brief Add fp0 to @a o0 and POP register stack (FPU).
INST_1x(faddp, kInstFaddp, FpReg)
//! @overload.
INST_0x(faddp, kInstFaddp)
//! @brief Load binary coded decimal (FPU).
INST_1x(fbld, kInstFbld, Mem)
@@ -1216,10 +1218,14 @@ struct X86X64Assembler : public BaseAssembler {
//! @brief Compare fp0 with @a o0 (FPU).
INST_1x(fcom, kInstFcom, FpReg)
//! @brief Compare fp0 with fp1 (FPU).
INST_0x(fcom, kInstFcom)
//! @brief Compare fp0 with 4-byte or 8-byte FP at @a src (FPU).
INST_1x(fcom, kInstFcom, Mem)
//! @brief Compare fp0 with @a o0 and pop the stack (FPU).
INST_1x(fcomp, kInstFcomp, FpReg)
//! @brief Compare fp0 with fp1 and pop the stack (FPU).
INST_0x(fcomp, kInstFcomp)
//! @brief Compare fp0 with 4-byte or 8-byte FP at @a adr and pop the stack (FPU).
INST_1x(fcomp, kInstFcomp, Mem)
//! @brief Compare fp0 with fp1 and pop register stack twice (FPU).
@@ -1243,6 +1249,8 @@ struct X86X64Assembler : public BaseAssembler {
INST_1x(fdiv, kInstFdiv, Mem)
//! @brief Divide @a o0 by fp0 (FPU).
INST_1x(fdivp, kInstFdivp, FpReg)
//! @overload.
INST_0x(fdivp, kInstFdivp)
//! @brief Reverse divide @a o0 by @a o1 (FPU).
//!
@@ -1252,6 +1260,8 @@ struct X86X64Assembler : public BaseAssembler {
INST_1x(fdivr, kInstFdivr, Mem)
//! @brief Reverse divide @a o0 by fp0 (FPU).
INST_1x(fdivrp, kInstFdivrp, FpReg)
//! @overload.
INST_0x(fdivrp, kInstFdivrp)
//! @brief Free FP register (FPU).
//!
@@ -1332,6 +1342,8 @@ struct X86X64Assembler : public BaseAssembler {
//! @brief Multiply fp0 by @a o0 and POP register stack (FPU).
INST_1x(fmulp, kInstFmulp, FpReg)
//! @overload.
INST_0x(fmulp, kInstFmulp)
//! @brief Clear exceptions (FPU).
INST_0x(fnclex, kInstFnclex)
@@ -1440,6 +1452,8 @@ struct X86X64Assembler : public BaseAssembler {
INST_1x_(fsub, kInstFsub, Mem, o0.getSize() == 4 || o0.getSize() == 8)
//! @brief Subtract fp0 from @a o0 and POP register stack (FPU).
INST_1x(fsubp, kInstFsubp, FpReg)
//! @overload.
INST_0x(fsubp, kInstFsubp)
//! @brief Reverse subtract @a o1 from @a o0 and store result in @a o0 (FPU).
//!
@@ -1449,20 +1463,24 @@ struct X86X64Assembler : public BaseAssembler {
INST_1x_(fsubr, kInstFsubr, Mem, o0.getSize() == 4 || o0.getSize() == 8)
//! @brief Reverse subtract fp0 from @a o0 and POP register stack (FPU).
INST_1x(fsubrp, kInstFsubrp, FpReg)
//! @overload.
INST_0x(fsubrp, kInstFsubrp)
//! @brief Floating point test - Compare fp0 with 0.0. (FPU).
INST_0x(ftst, kInstFtst)
//! @brief Unordered compare fp0 with @a o0 (FPU).
INST_1x(fucom, kInstFucom, FpReg)
//! @brief Unordered compare fp0 and @a o0, check for ordered values
//! and Set EFLAGS (FPU).
//! @brief Unordered compare fp0 with fp1 (FPU).
INST_0x(fucom, kInstFucom)
//! @brief Unordered compare fp0 and @a o0, check for ordered values and Set EFLAGS (FPU).
INST_1x(fucomi, kInstFucomi, FpReg)
//! @brief Unordered compare fp0 and @a o0, Check for ordered values
//! and Set EFLAGS and pop the stack (FPU).
//! @brief Unordered compare fp0 and @a o0, Check for ordered values and Set EFLAGS and pop the stack (FPU).
INST_1x(fucomip, kInstFucomip, FpReg)
//! @brief Unordered compare fp0 with @a o0 and pop register stack (FPU).
INST_1x(fucomp, kInstFucomp, FpReg)
//! @brief Unordered compare fp0 with fp1 and pop register stack (FPU).
INST_0x(fucomp, kInstFucomp)
//! @brief Unordered compare fp0 with fp1 and pop register stack twice (FPU).
INST_0x(fucompp, kInstFucompp)

16
src/asmjit/x86/x86defs.cpp
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@@ -2102,7 +2102,7 @@ const InstInfo _instInfo[] = {
INST(kInstF2xm1 , "f2xm1" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(D9F0,U) , U ),
INST(kInstFabs , "fabs" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(D9E1,U) , U ),
INST(kInstFadd , "fadd" , G(FpuArith) , F(Fp)|F(Mem4_8) , O(FpMem) , O(Fp) , U , U , O_00_X(C0C0,0) , U ),
INST(kInstFaddp , "faddp" , G(FpuR) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEC0,U) , U ),
INST(kInstFaddp , "faddp" , G(FpuRDef) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEC0,U) , U ),
INST(kInstFbld , "fbld" , G(X86M) , F(Fp) , O(Mem) , U , U , U , O_000000(DF,4) , U ),
INST(kInstFbstp , "fbstp" , G(X86M) , F(Fp) , O(Mem) , U , U , U , O_000000(DF,6) , U ),
INST(kInstFchs , "fchs" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(D9E0,U) , U ),
@@ -2123,9 +2123,9 @@ const InstInfo _instInfo[] = {
INST(kInstFcos , "fcos" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(D9FF,U) , U ),
INST(kInstFdecstp , "fdecstp" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(D9F6,U) , U ),
INST(kInstFdiv , "fdiv" , G(FpuArith) , F(Fp)|F(Mem4_8) , O(FpMem) , O(Fp) , U , U , O_00_X(F0F8,6) , U ),
INST(kInstFdivp , "fdivp" , G(FpuR) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEF8,U) , U ),
INST(kInstFdivp , "fdivp" , G(FpuRDef) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEF8,U) , U ),
INST(kInstFdivr , "fdivr" , G(FpuArith) , F(Fp)|F(Mem4_8) , O(FpMem) , O(Fp) , U , U , O_00_X(F8F0,7) , U ),
INST(kInstFdivrp , "fdivrp" , G(FpuR) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEF0,U) , U ),
INST(kInstFdivrp , "fdivrp" , G(FpuRDef) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEF0,U) , U ),
INST(kInstFemms , "femms" , G(X86Op) , F(Fp) , U , U , U , U , O_000F00(0E,U) , U ),
INST(kInstFfree , "ffree" , G(FpuR) , F(Fp) , O(Fp) , U , U , U , O_00_X(DDC0,U) , U ),
INST(kInstFiadd , "fiadd" , G(FpuM) , F(Fp)|F(Mem2_4) , O(Mem) , U , U , U , O_000000(DA,0) , U ),
@@ -2153,7 +2153,7 @@ const InstInfo _instInfo[] = {
INST(kInstFldpi , "fldpi" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(D9EB,U) , U ),
INST(kInstFldz , "fldz" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(D9EE,U) , U ),
INST(kInstFmul , "fmul" , G(FpuArith) , F(Fp)|F(Mem4_8) , O(FpMem) , O(Fp) , U , U , O_00_X(C8C8,1) , U ),
INST(kInstFmulp , "fmulp" , G(FpuR) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEC8,U) , U ),
INST(kInstFmulp , "fmulp" , G(FpuRDef) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEC8,U) , U ),
INST(kInstFnclex , "fnclex" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(DBE2,U) , U ),
INST(kInstFninit , "fninit" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(DBE3,U) , U ),
INST(kInstFnop , "fnop" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(D9D0,U) , U ),
@@ -2178,14 +2178,14 @@ const InstInfo _instInfo[] = {
INST(kInstFstp , "fstp" , G(FpuFldFst) , F(Fp)|F(Mem4_8_10) , O(Mem) , U , U , U , O_000000(D9,3) , O_000000(DB,7) ),
INST(kInstFstsw , "fstsw" , G(FpuStsw) , F(Fp) , O(Mem) , U , U , U , O_9B0000(DD,7) , O_9B_X(DFE0,U) ),
INST(kInstFsub , "fsub" , G(FpuArith) , F(Fp)|F(Mem4_8) , O(FpMem) , O(Fp) , U , U , O_00_X(E0E8,4) , U ),
INST(kInstFsubp , "fsubp" , G(FpuR) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEE8,U) , U ),
INST(kInstFsubp , "fsubp" , G(FpuRDef) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEE8,U) , U ),
INST(kInstFsubr , "fsubr" , G(FpuArith) , F(Fp)|F(Mem4_8) , O(FpMem) , O(Fp) , U , U , O_00_X(E8E0,5) , U ),
INST(kInstFsubrp , "fsubrp" , G(FpuR) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEE0,U) , U ),
INST(kInstFsubrp , "fsubrp" , G(FpuRDef) , F(Fp) , O(Fp) , U , U , U , O_00_X(DEE0,U) , U ),
INST(kInstFtst , "ftst" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(D9E4,U) , U ),
INST(kInstFucom , "fucom" , G(FpuR) , F(Fp) , O(Fp) , U , U , U , O_00_X(DDE0,U) , U ),
INST(kInstFucom , "fucom" , G(FpuRDef) , F(Fp) , O(Fp) , U , U , U , O_00_X(DDE0,U) , U ),
INST(kInstFucomi , "fucomi" , G(FpuR) , F(Fp) , O(Fp) , U , U , U , O_00_X(DBE8,U) , U ),
INST(kInstFucomip , "fucomip" , G(FpuR) , F(Fp) , O(Fp) , U , U , U , O_00_X(DFE8,U) , U ),
INST(kInstFucomp , "fucomp" , G(FpuR) , F(Fp) , O(Fp) , U , U , U , O_00_X(DDE8,U) , U ),
INST(kInstFucomp , "fucomp" , G(FpuRDef) , F(Fp) , O(Fp) , U , U , U , O_00_X(DDE8,U) , U ),
INST(kInstFucompp , "fucompp" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(DAE9,U) , U ),
INST(kInstFwait , "fwait" , G(X86Op) , F(Fp) , U , U , U , U , O_000000(DB,U) , U ),
INST(kInstFxam , "fxam" , G(FpuOp) , F(Fp) , U , U , U , U , O_00_X(D9E5,U) , U ),

4
src/asmjit/x86/x86defs.h
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@@ -1517,8 +1517,10 @@ ASMJIT_ENUM(kInstGroup) {
kInstGroupFpuFldFst,
//! @brief Fiadd/Ficom/Ficomp/Fidiv/Fidivr/Fild/Fimul/Fist/Fistp/Fisttp/Fisub/Fisubr.
kInstGroupFpuM,
//! @brief Faddp/Fcmov/Fcomi/Fcomip/Fdivp/Fdivrp/Ffree/Fmulp/Fsubp/Fsubrp/Fucom/Fucomi/Fucomip/Fucomp/Fxch.
//! @brief Fcmov/Fcomi/Fcomip/Ffree/Fucom/Fucomi/Fucomip/Fucomp/Fxch.
kInstGroupFpuR,
//! @brief Faddp/Fdivp/Fdivrp/Fmulp/Fsubp/Fsubrp.
kInstGroupFpuRDef,
//! @brief Fnstsw/Fstsw.
kInstGroupFpuStsw,