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src/resources/cheatsheets/riscv-32bit.md
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src/resources/cheatsheets/riscv-32bit.md
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# RISC-V Assembler Cheat Sheet
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A thorough reference to 32-bit RISC-V instructions, registers, and fundamental concepts. This guide is intended for software developers working with the RISC-V assembly language and includes grouped instructions by purpose, common pseudoinstructions, and usage examples.
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## Table of Contents
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1. [Arithmetic Instructions](#arithmetic-instructions)
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2. [Bitwise Logic Instructions](#bitwise-logic-instructions)
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3. [Shift Instructions](#shift-instructions)
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4. [Load Immediate Instructions](#load-immediate-instructions)
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5. [Load and Store Instructions](#load-and-store-instructions)
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6. [Jump and Function Instructions](#jump-and-function-instructions)
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7. [Branch Instructions](#branch-instructions)
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8. [Set Instructions](#set-instructions)
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9. [Counter Instructions](#counter-instructions)
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10. [Miscellaneous Instructions](#miscellaneous-instructions)
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11. [Instruction Terminology](#instruction-terminology)
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12. [RV32 ABI Registers](#rv32-abi-registers)
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13. [RISC-V Concepts](#risc-v-concepts)
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14. [Usage Examples](#usage-examples)
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---
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## Arithmetic Instructions
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Arithmetic operations perform basic mathematical computations.
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| **Instruction** | **Description** | **Usage** | **Result** | **Guide** |
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|-----------------|-------------------------|---------------------|-------------------------------------|--------------|
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| `add` | Add | `add rd, rs1, rs2` | `rd = rs1 + rs2` | Arithmetic |
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| `addi` | Add Immediate | `addi rd, rs1, imm` | `rd = rs1 + imm` | Arithmetic |
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| `neg` | Negate (pseudoinstruction)| `neg rd, rs2` | `rd = -rs2` | Arithmetic |
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| `sub` | Subtract | `sub rd, rs1, rs2` | `rd = rs1 - rs2` | Arithmetic |
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| `mul` | Multiply | `mul rd, rs1, rs2` | `rd = (rs1 * rs2)[31:0]` | Multiply |
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| `mulh` | Multiply High | `mulh rd, rs1, rs2` | `rd = (rs1 * rs2)[63:32]` | Multiply |
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| `mulhu` | Multiply High Unsigned | `mulhu rd, rs1, rs2`| `rd = (rs1 * rs2)[63:32]` | Multiply |
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| `mulhsu` | Multiply High Signed Unsigned | `mulhsu rd, rs1, rs2` | `rd = (rs1 * rs2)[63:32]` | Multiply |
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| `div` | Divide | `div rd, rs1, rs2` | `rd = rs1 / rs2` | Divide |
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| `rem` | Remainder | `rem rd, rs1, rs2` | `rd = rs1 % rs2` | Divide |
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**Notes:**
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- Use `addi` for subtracting with an immediate value: `addi rd, rs1, -imm`
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- Multiply and divide instructions require the **M** extension.
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### Example:
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```assembly
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addi t0, t1, 10 # t0 = t1 + 10
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sub t2, t0, t1 # t2 = t0 - t1
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mul t3, t2, t1 # t3 = t2 * t1
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```
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---
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## Bitwise Logic Instructions
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Perform logical operations on binary data.
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| **Instruction** | **Description** | **Usage** | **Result** | **Guide** |
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|-----------------|-----------------------|---------------------|-------------------------------------|--------------|
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| `and` | Logical AND | `and rd, rs1, rs2` | `rd = rs1 & rs2` | Logical |
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| `andi` | AND Immediate | `andi rd, rs1, imm` | `rd = rs1 & imm` | Logical |
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| `not` | Logical NOT (pseudoinstruction) | `not rd, rs1` | `rd = ~rs1` | Logical |
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| `or` | Logical OR | `or rd, rs1, rs2` | `rd = rs1 | rs2` | Logical |
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| `ori` | OR Immediate | `ori rd, rs1, imm` | `rd = rs1 | imm` | Logical |
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| `xor` | Logical XOR | `xor rd, rs1, rs2` | `rd = rs1 ^ rs2` | Logical |
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| `xori` | XOR Immediate | `xori rd, rs1, imm` | `rd = rs1 ^ imm` | Logical |
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### Example:
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```assembly
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and t0, t1, t2 # t0 = t1 & t2
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ori t3, t0, 0xFF # t3 = t0 | 0xFF
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not t4, t3 # t4 = ~t3
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```
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---
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## Shift Instructions
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Handle bitwise shifting operations.
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| **Instruction** | **Description** | **Usage** | **Result** | **Guide** |
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|-----------------|-------------------------------|--------------------------|-------------------------------------|--------------|
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| `sll` | Shift Left Logical | `sll rd, rs1, rs2` | `rd = rs1 << rs2` | Shift |
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| `slli` | Shift Left Logical Immediate | `slli rd, rs1, imm` | `rd = rs1 << imm` | Shift |
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| `srl` | Shift Right Logical | `srl rd, rs1, rs2` | `rd = rs1 >> rs2` | Shift |
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| `srli` | Shift Right Logical Immediate | `srli rd, rs1, imm` | `rd = rs1 >> imm` | Shift |
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| `sra` | Shift Right Arithmetic | `sra rd, rs1, rs2` | `rd = rs1 >>> rs2` | Shift |
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| `srai` | Shift Right Arithmetic Immediate | `srai rd, rs1, imm` | `rd = rs1 >>> imm` | Shift |
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### Example:
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```assembly
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slli t0, t1, 2 # t0 = t1 << 2
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srli t2, t0, 1 # t2 = t0 >> 1
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sra t3, t2, t1 # t3 = t2 >>> t1
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```
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---
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## Load Immediate Instructions
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Load immediate values into registers.
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| **Instruction** | **Description** | **Usage** | **Result** | **Guide** |
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|-----------------|------------------------------|---------------------|-------------------------------------|--------------|
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| `li` | Load Immediate (pseudoinstruction) | `li rd, imm` | `rd = imm` | Arithmetic |
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| `lui` | Load Upper Immediate | `lui rd, imm` | `rd = imm << 12` | Arithmetic |
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| `auipc` | Add Upper Immediate to PC | `auipc rd, imm` | `rd = pc + (imm << 12)` | Branch |
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### Example:
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```assembly
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li t0, 100 # t0 = 100
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lui t1, 0x1F # t1 = 0x1F000
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auipc t2, 0x10 # t2 = pc + 0x10000
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```
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---
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## Load and Store Instructions
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Manage data movement between registers and memory.
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| **Instruction** | **Description** | **Usage** | **Result** | **Guide** |
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|-----------------|-----------------------------|--------------------------|--------------------------------------------|--------------|
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| `lw` | Load Word | `lw rd, imm(rs1)` | `rd = mem[rs1 + imm]` | Load |
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| `lh` | Load Half | `lh rd, imm(rs1)` | `rd = mem[rs1 + imm][0:15]` | Load |
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| `lhu` | Load Half Unsigned | `lhu rd, imm(rs1)` | `rd = mem[rs1 + imm][0:15]` | Load |
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| `lb` | Load Byte | `lb rd, imm(rs1)` | `rd = mem[rs1 + imm][0:7]` | Load |
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| `lbu` | Load Byte Unsigned | `lbu rd, imm(rs1)` | `rd = mem[rs1 + imm][0:7]` | Load |
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| `la` | Load Symbol Address (pseudoinstruction) | `la rd, symbol` | `rd = &symbol` | Load |
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| `sw` | Store Word | `sw rs2, imm(rs1)` | `mem[rs1 + imm] = rs2` | Store |
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| `sh` | Store Half | `sh rs2, imm(rs1)` | `mem[rs1 + imm][0:15] = rs2` | Store |
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| `sb` | Store Byte | `sb rs2, imm(rs1)` | `mem[rs1 + imm][0:7] = rs2` | Store |
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### Example:
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```assembly
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lw t0, 0(sp) # t0 = mem[sp + 0]
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sw t1, 4(sp) # mem[sp + 4] = t1
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la t2, data_label # t2 = address of data_label
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```
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---
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## Jump and Function Instructions
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Control the flow of the program through jumps and function calls.
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| **Instruction** | **Description** | **Usage** | **Result** | **Guide** |
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|-----------------|------------------------------------------------|-----------------------------|---------------------------------------------|--------------|
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| `j` | Jump (pseudoinstruction) | `j imm` | `pc += imm` | Jump |
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| `jal` | Jump and Link | `jal rd, imm` | `rd = pc + 4; pc += imm` | Jump |
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| `jalr` | Jump and Link Register | `jalr rd, rs1, imm` | `rd = pc + 4; pc = rs1 + imm` | Jump |
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| `call` | Call Function (pseudoinstruction) | `call symbol` | `ra = pc + 4; pc = &symbol` | Function |
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| `ret` | Return from Function (pseudoinstruction) | `ret` | `pc = ra` | Function |
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**Notes:**
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- Labels can be used in place of immediate values for jump instructions.
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### Example:
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```assembly
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jal ra, function_label # Jump to function_label and store return address in ra
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call main # Call the main function
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ret # Return from the current function
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```
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---
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## Branch Instructions
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Conditional branching based on comparisons.
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| **Instruction** | **Description** | **Usage** | **Result** | **Guide** |
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|-----------------|-----------------------------|-----------------------------|-----------------------------------------------|--------------|
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| `beq` | Branch Equal | `beq rs1, rs2, imm` | `if(rs1 == rs2) pc += imm` | Branch |
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| `beqz` | Branch Equal Zero (pseudoinstruction) | `beqz rs1, imm` | `if(rs1 == 0) pc += imm` | Branch |
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| `bne` | Branch Not Equal | `bne rs1, rs2, imm` | `if(rs1 ≠ rs2) pc += imm` | Branch |
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| `bnez` | Branch Not Equal Zero (pseudoinstruction) | `bnez rs1, imm` | `if(rs1 ≠ 0) pc += imm` | Branch |
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| `blt` | Branch Less Than | `blt rs1, rs2, imm` | `if(rs1 < rs2) pc += imm` | Branch |
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| `bltu` | Branch Less Than Unsigned | `bltu rs1, rs2, imm` | `if(rs1 < rs2) pc += imm` | Branch |
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| `bltz` | Branch Less Than Zero (pseudoinstruction) | `bltz rs1, imm` | `if(rs1 < 0) pc += imm` | Branch |
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| `bgt` | Branch Greater Than (pseudoinstruction) | `bgt rs1, rs2, imm` | `if(rs1 > rs2) pc += imm` | Branch |
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| `bgtu` | Branch Greater Than Unsigned (pseudoinstruction) | `bgtu rs1, rs2, imm` | `if(rs1 > rs2) pc += imm` | Branch |
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| `bgtz` | Branch Greater Than Zero (pseudoinstruction) | `bgtz rs1, imm` | `if(rs1 > 0) pc += imm` | Branch |
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| `ble` | Branch Less or Equal (pseudoinstruction) | `ble rs1, rs2, imm` | `if(rs1 ≤ rs2) pc += imm` | Branch |
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| `bleu` | Branch Less or Equal Unsigned (pseudoinstruction) | `bleu rs1, rs2, imm` | `if(rs1 ≤ rs2) pc += imm` | Branch |
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| `blez` | Branch Less or Equal Zero (pseudoinstruction) | `blez rs1, imm` | `if(rs1 ≤ 0) pc += imm` | Branch |
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| `bge` | Branch Greater or Equal | `bge rs1, rs2, imm` | `if(rs1 ≥ rs2) pc += imm` | Branch |
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| `bgeu` | Branch Greater or Equal Unsigned | `bgeu rs1, rs2, imm` | `if(rs1 ≥ rs2) pc += imm` | Branch |
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| `bgez` | Branch Greater or Equal Zero (pseudoinstruction) | `bgez rs1, imm` | `if(rs1 ≥ 0) pc += imm` | Branch |
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**Notes:**
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- Labels can be used in place of immediate values for branch instructions.
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### Example:
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```assembly
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beq t0, t1, equal_label # If t0 == t1, jump to equal_label
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bnez t2, not_zero_label # If t2 != 0, jump to not_zero_label
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blt t3, t4, less_than_label # If t3 < t4, jump to less_than_label
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```
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---
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## Set Instructions
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Set register values based on comparisons.
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| **Instruction** | **Description** | **Usage** | **Result** | **Guide** |
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|-----------------|-----------------------------|-----------------------------|-----------------------------------------------|--------------|
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| `slt` | Set Less Than | `slt rd, rs1, rs2` | `rd = (rs1 < rs2)` | Set |
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| `slti` | Set Less Than Immediate | `slti rd, rs1, imm` | `rd = (rs1 < imm)` | Set |
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| `sltu` | Set Less Than Unsigned | `sltu rd, rs1, rs2` | `rd = (rs1 < rs2)` | Set |
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| `sltiu` | Set Less Than Immediate Unsigned | `sltiu rd, rs1, imm` | `rd = (rs1 < imm)` | Set |
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| `seqz` | Set Equal Zero (pseudoinstruction) | `seqz rd, rs1` | `rd = (rs1 == 0)` | Set |
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| `snez` | Set Not Equal Zero (pseudoinstruction) | `snez rd, rs1` | `rd = (rs1 ≠ 0)` | Set |
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| `sltz` | Set Less Than Zero (pseudoinstruction) | `sltz rd, rs1` | `rd = (rs1 < 0)` | Set |
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| `sgtz` | Set Greater Than Zero (pseudoinstruction) | `sgtz rd, rs1` | `rd = (rs1 > 0)` | Set |
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### Example:
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```assembly
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slt t0, t1, t2 # t0 = (t1 < t2)
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slti t3, t0, 5 # t3 = (t0 < 5)
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seqz t4, t3 # t4 = (t3 == 0)
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```
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---
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## Counter Instructions
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Access CPU cycle and instruction counters. *Note: These instructions require the Zicntr and Zicsr extensions and are not yet available in all implementations.*
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| **Instruction** | **Description** | **Usage** | **Result** | **Guide** |
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|-----------------|---------------------------------|------------------------------|--------------------------------------------------|--------------|
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| `rdcycle` | CPU Cycle Count (pseudoinstruction) | `rdcycle rd` | `rd = csr_cycle[31:0]` | Not Available |
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| `rdcycleh` | CPU Cycle Count High (pseudoinstruction) | `rdcycleh rd` | `rd = csr_cycle[63:32]` | Not Available |
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| `rdtime` | Current Time (pseudoinstruction) | `rdtime rd` | `rd = csr_time[31:0]` | Not Available |
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| `rdtimeh` | Current Time High (pseudoinstruction) | `rdtimeh rd` | `rd = csr_time[63:32]` | Not Available |
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| `rdinstret` | CPU Instructions Retired (pseudoinstruction) | `rdinstret rd` | `rd = csr_instret[31:0]` | Not Available |
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| `rdinstreth` | CPU Instructions Retired High (pseudoinstruction) | `rdinstreth rd` | `rd = csr_instret[63:32]` | Not Available |
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---
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## Miscellaneous Instructions
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Additional instructions for various purposes.
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| **Instruction** | **Description** | **Usage** | **Result** | **Guide** |
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|-----------------|------------------------------------------|-----------------------------|-----------------------------------------------|--------------|
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| `ebreak` | Environment Break (Debugger Call) | `ebreak` | - | Not Available |
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| `ecall` | Environment Call (OS Function) | `ecall` | - | Not Available |
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| `fence` | I/O Ordering | `fence` | - | Not Available |
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| `mv` | Copy Register (pseudoinstruction) | `mv rd, rs1` | `rd = rs1` | Arithmetic |
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| `nop` | No Operation (pseudoinstruction) | `nop` | - | Arithmetic |
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**Notes:**
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- The `fence` instruction requires the **Zifencei** extension.
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### Example:
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```assembly
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mv t0, t1 # t0 = t1
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nop # No operation
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ecall # Environment call
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```
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---
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## Instruction Terminology
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Understanding the terminology used in RISC-V assembly instructions.
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| **Term** | **Description** |
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|-----------|----------------------------------------------------|
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| `imm` | Immediate value (normally sign-extended) |
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| `mem` | Memory |
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| `(p)` | Pseudoinstruction |
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| `pc` | Program counter |
|
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| `pc+4` | Next instruction on RV32 |
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| `ra` | Return address register (x1) |
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| `rd` | Destination register |
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| `rs1` | First source register |
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| `rs2` | Second source register |
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| `symbol` | Symbol (may be a label in assembly) |
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||||
---
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## RV32 ABI Registers
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Overview of the ABI (Application Binary Interface) registers for RV32.
|
||||
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||||
| **ABI Name** | **Register** | **Description** | **Preserved** |
|
||||
|--------------|--------------|--------------------------------|---------------|
|
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| `zero` | `x0` | Always 0 (zero) | N/A |
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| `ra` | `x1` | Return address | No |
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||||
| `sp` | `x2` | Stack pointer | Yes |
|
||||
| `gp` | `x3` | Global pointer* | N/A |
|
||||
| `tp` | `x4` | Thread pointer* | N/A |
|
||||
| `t0` | `x5` | Temporary | No |
|
||||
| `t1` | `x6` | Temporary | No |
|
||||
| `t2` | `x7` | Temporary | No |
|
||||
| `fp (s0)` | `x8` | Frame pointer† | Yes |
|
||||
| `s1` | `x9` | Saved register | Yes |
|
||||
| `a0` | `x10` | Function argument‡ | No |
|
||||
| `a1` | `x11` | Function argument‡ | No |
|
||||
| `a2` | `x12` | Function argument | No |
|
||||
| `a3` | `x13` | Function argument | No |
|
||||
| `a4` | `x14` | Function argument | No |
|
||||
| `a5` | `x15` | Function argument | No |
|
||||
| `a6` | `x16` | Function argument | No |
|
||||
| `a7` | `x17` | Function argument | No |
|
||||
| `s2` | `x18` | Saved register | Yes |
|
||||
| `s3` | `x19` | Saved register | Yes |
|
||||
| `s4` | `x20` | Saved register | Yes |
|
||||
| `s5` | `x21` | Saved register | Yes |
|
||||
| `s6` | `x22` | Saved register | Yes |
|
||||
| `s7` | `x23` | Saved register | Yes |
|
||||
| `s8` | `x24` | Saved register | Yes |
|
||||
| `s9` | `x25` | Saved register | Yes |
|
||||
| `s10` | `x26` | Saved register | Yes |
|
||||
| `s11` | `x27` | Saved register | Yes |
|
||||
| `t3` | `x28` | Temporary | No |
|
||||
| `t4` | `x29` | Temporary | No |
|
||||
| `t5` | `x30` | Temporary | No |
|
||||
| `t6` | `x31` | Temporary | No |
|
||||
|
||||
**Notes:**
|
||||
- \* Let the compiler/linker use the global `gp` and thread `tp` pointers; ignore them in your own code.
|
||||
- † The frame pointer `fp` supports local variables but can be used as a regular saved register.
|
||||
- ‡ Argument registers `a0` and `a1` also handle the function return value.
|
||||
|
||||
---
|
||||
|
||||
## RISC-V Concepts
|
||||
|
||||
Key concepts to understand when working with RISC-V assembly:
|
||||
|
||||
- **Extensions:** RISC-V is modular, allowing for different extensions (e.g., M for Multiply/Divide, A for Atomic, etc.) to add functionality.
|
||||
- **Base Instruction Set:** This cheat sheet focuses on the base integer instruction set (RV32I).
|
||||
- **Pseudoinstructions:** These are simplified instructions that are translated into one or more actual RISC-V instructions by the assembler.
|
||||
|
||||
---
|
||||
|
||||
## Usage Examples
|
||||
|
||||
Below are examples demonstrating how to use various RISC-V instructions in assembly code.
|
||||
|
||||
### Example 1: Simple Arithmetic Operations
|
||||
|
||||
```assembly
|
||||
.section .text
|
||||
.globl main
|
||||
|
||||
main:
|
||||
li t0, 10 # Load immediate 10 into t0
|
||||
li t1, 20 # Load immediate 20 into t1
|
||||
add t2, t0, t1 # t2 = t0 + t1 (30)
|
||||
sub t3, t1, t0 # t3 = t1 - t0 (10)
|
||||
mul t4, t2, t3 # t4 = t2 * t3 (300)
|
||||
ecall # Exit program
|
||||
```
|
||||
|
||||
### Example 2: Branching Based on Comparison
|
||||
|
||||
```assembly
|
||||
.section .text
|
||||
.globl main
|
||||
|
||||
main:
|
||||
li t0, 5 # t0 = 5
|
||||
li t1, 10 # t1 = 10
|
||||
blt t0, t1, less_than_label # If t0 < t1, jump to less_than_label
|
||||
j end_label # Else, jump to end_label
|
||||
|
||||
less_than_label:
|
||||
li a0, 1 # Set a0 to 1 (indicating true)
|
||||
j end_label
|
||||
|
||||
end_label:
|
||||
li a0, 0 # Set a0 to 0 (indicating false)
|
||||
ecall # Exit program
|
||||
```
|
||||
|
||||
### Example 3: Function Call and Return
|
||||
|
||||
```assembly
|
||||
.section .text
|
||||
.globl main
|
||||
|
||||
main:
|
||||
jal ra, function_label # Jump to function_label and save return address
|
||||
li a0, 0 # Set return value to 0
|
||||
ecall # Exit program
|
||||
|
||||
function_label:
|
||||
addi sp, sp, -16 # Allocate stack space
|
||||
sw ra, 12(sp) # Save return address
|
||||
li t0, 42 # Perform some operations
|
||||
lw ra, 12(sp) # Restore return address
|
||||
addi sp, sp, 16 # Deallocate stack space
|
||||
jalr ra, 0(ra) # Return to caller
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Additional Resources
|
||||
|
||||
- [Project F RISC-V Assembler Guide](#)
|
||||
- [RISC-V Specification](https://riscv.org/technical/specifications/)
|
||||
|
||||
---
|
||||
|
||||
*This cheat sheet covers the base integer instruction set (RV32I) and some standard extensions. Make sure to consult the official RISC-V documentation for comprehensive information and updates.*
|
||||
Reference in New Issue
Block a user